Haiying Wang d111d6382c Empirically set cpo and clk_adjust for mpc85xx DDR2 support
This patch is against u-boot-mpc85xx.git of www.denx.com

Setting cpo to 0x9 for frequencies higher than 333MHz is verified on
both MPC8548CDS board and MPC8568MDS board, especially for supporting
533MHz DDR2.

Setting clk_adjust to 0x6(3/4 late cycle) for MPC8568MDS board is for
DDR2 on all current board versions especially ver 1.92 or later to bring
up.

Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
2007-08-14 01:45:51 -05:00
..
2007-05-09 11:41:58 +01:00
2007-08-13 17:35:16 +02:00
2007-08-10 11:02:32 -05:00
2007-08-12 21:34:34 +02:00