Andy Fleming 9343dbf85b Tweak DDR ECC error counter
Enable single-bit error counter when memory was cleared by ddr controller.

Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2007-04-23 19:58:28 -05:00
..
2007-03-04 01:36:05 +01:00
2007-04-04 02:09:30 +02:00
2007-03-21 23:26:15 +01:00
2007-04-23 19:58:28 -05:00