u-boot: update version /home/liliana/Dingussy/local/releases/tt1860562
This commit is contained in:
Mia Pilchová
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6694ffcc73
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6024743d64
0
MODULE_LICENSE_GPL2
Normal file
0
MODULE_LICENSE_GPL2
Normal file
298
NOTICE
Normal file
298
NOTICE
Normal file
@ -0,0 +1,298 @@
|
||||
NOTE! This copyright does *not* cover the so-called "standalone"
|
||||
applications that use U-Boot services by means of the jump table
|
||||
provided by U-Boot exactly for this purpose - this is merely
|
||||
considered normal use of U-Boot, and does *not* fall under the
|
||||
heading of "derived work".
|
||||
|
||||
The header files "include/image.h" and "include/asm-*/u-boot.h"
|
||||
define interfaces to U-Boot. Including these (unmodified) header
|
||||
files in another file is considered normal use of U-Boot, and does
|
||||
*not* fall under the heading of "derived work".
|
||||
|
||||
Also note that the GPL below is copyrighted by the Free Software
|
||||
Foundation, but the instance of code that it refers to (the U-Boot
|
||||
source code) is copyrighted by me and others who actually wrote it.
|
||||
-- Wolfgang Denk
|
||||
|
||||
=======================================================================
|
||||
|
||||
GNU GENERAL PUBLIC LICENSE
|
||||
Version 2, June 1991
|
||||
|
||||
Copyright (C) 1989, 1991 Free Software Foundation, Inc.
|
||||
59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
Everyone is permitted to copy and distribute verbatim copies
|
||||
of this license document, but changing it is not allowed.
|
||||
|
||||
Preamble
|
||||
|
||||
The licenses for most software are designed to take away your
|
||||
freedom to share and change it. By contrast, the GNU General Public
|
||||
License is intended to guarantee your freedom to share and change free
|
||||
software--to make sure the software is free for all its users. This
|
||||
General Public License applies to most of the Free Software
|
||||
Foundation's software and to any other program whose authors commit to
|
||||
using it. (Some other Free Software Foundation software is covered by
|
||||
the GNU Library General Public License instead.) You can apply it to
|
||||
your programs, too.
|
||||
|
||||
When we speak of free software, we are referring to freedom, not
|
||||
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|
||||
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||||
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|
||||
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|
||||
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||||
|
||||
To protect your rights, we need to make restrictions that forbid
|
||||
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|
||||
These restrictions translate to certain responsibilities for you if you
|
||||
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||||
For example, if you distribute copies of such a program, whether
|
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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||||
Finally, any free program is threatened constantly by software
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||||
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||||
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||||
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||||
The precise terms and conditions for copying, distribution and
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||||
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|
||||
|
||||
GNU GENERAL PUBLIC LICENSE
|
||||
TERMS AND CONDITIONS FOR COPYING, DISTRIBUTION AND MODIFICATION
|
||||
|
||||
0. This License applies to any program or other work which contains
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||||
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||||
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|
||||
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Whether that is true depends on what the Program does.
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These requirements apply to the modified work as a whole. If
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||||
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||||
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Thus, it is not the intent of this section to claim rights or contest
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In addition, mere aggregation of another work not based on the Program
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3. You may copy and distribute the Program (or a work based on it,
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The source code for a work means the preferred form of the work for
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4. You may not copy, modify, sublicense, or distribute the Program
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||||
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You are not responsible for enforcing compliance by third parties to
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7. If, as a consequence of a court judgment or allegation of patent
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||||
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||||
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||||
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||||
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||||
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If any portion of this section is held invalid or unenforceable under
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It is not the purpose of this section to induce you to infringe any
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This section is intended to make thoroughly clear what is believed to
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8. If the distribution and/or use of the Program is restricted in
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||||
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||||
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||||
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|
||||
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|
||||
|
||||
9. The Free Software Foundation may publish revised and/or new versions
|
||||
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|
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||||
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Each version is given a distinguishing version number. If the Program
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|
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|
||||
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|
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10. If you wish to incorporate parts of the Program into other free
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NO WARRANTY
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11. BECAUSE THE PROGRAM IS LICENSED FREE OF CHARGE, THERE IS NO WARRANTY
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FOR THE PROGRAM, TO THE EXTENT PERMITTED BY APPLICABLE LAW. EXCEPT WHEN
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PROVIDE THE PROGRAM "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESSED
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OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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TO THE QUALITY AND PERFORMANCE OF THE PROGRAM IS WITH YOU. SHOULD THE
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REPAIR OR CORRECTION.
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12. IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING
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WILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MAY MODIFY AND/OR
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END OF TERMS AND CONDITIONS
|
||||
80
board/tomtom/strasbourg/Makefile
Normal file
80
board/tomtom/strasbourg/Makefile
Normal file
@ -0,0 +1,80 @@
|
||||
#
|
||||
# (C) Copyright 2009 Texas Instruments.
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
include $(TOPDIR)/config.mk
|
||||
|
||||
COMMONDIR = ../common
|
||||
PLAT_DIR = $(TOPDIR)/plat-tomtom/offenburg
|
||||
|
||||
LIB = lib$(BOARD).a
|
||||
|
||||
# Boot shell scripts
|
||||
USHOBJS := bootcmd.o altbootcmd.o preboot.o preboot_plat.o
|
||||
|
||||
# U-Boot 1.1.4 build system sucks :P
|
||||
ifeq (,$(shell fgrep -q 'CONFIG_DEBUG_BUILD' \
|
||||
$(TOPDIR)/include/`sed -ne 's|.*<\(.*\)>.*|\1|p' $(TOPDIR)/include/config.h` \
|
||||
2>/dev/null || echo x))
|
||||
USHOBJS += bootcmd_debug.o altbootcmd_debug.o preboot_debug.o
|
||||
endif
|
||||
|
||||
OBJS := strasbourg.o \
|
||||
${PLAT_DIR}/board.o \
|
||||
${PLAT_DIR}/security.o \
|
||||
${PLAT_DIR}/sys_info.o \
|
||||
bricknum.o \
|
||||
mfd_feat.o \
|
||||
epic_fail.o
|
||||
|
||||
OBJS += $(COMMONDIR)/bootcount.o \
|
||||
$(COMMONDIR)/env_init.o \
|
||||
|
||||
$(LIB): $(OBJS) $(USHOBJS)
|
||||
$(AR) crv $@ $^
|
||||
|
||||
%.o: %.image
|
||||
cd $(<D); \
|
||||
$(OBJCOPY) -I binary -O elf32-littlearm -B arm \
|
||||
--rename-section .data=.bootscript $(<F) $(@F)
|
||||
|
||||
.SECONDARY: $(USHOBJS:.o=.image)
|
||||
|
||||
%.image: %.ush Makefile
|
||||
$(TOPDIR)/tools/mkimage -A arm -O linux -T script -C none \
|
||||
-a 0 -e 0 -n $(*F) -d $< $@.tmp
|
||||
-dd if=$@.tmp bs=4 of=$@ conv=sync
|
||||
$(RM) $@.tmp
|
||||
|
||||
clean:
|
||||
rm -f $(OBJS) $(USHOBJS)
|
||||
|
||||
distclean: clean
|
||||
rm -f $(LIB) core *.bak .depend
|
||||
|
||||
#########################################################################
|
||||
|
||||
.depend: Makefile $(OBJS:.o=.c)
|
||||
$(CC) -M $(CPPFLAGS) $(OBJS:.o=.c) > $@
|
||||
|
||||
-include .depend
|
||||
|
||||
#########################################################################
|
||||
48
board/tomtom/strasbourg/mfd_feat.c
Normal file
48
board/tomtom/strasbourg/mfd_feat.c
Normal file
@ -0,0 +1,48 @@
|
||||
/*
|
||||
* Copyright (C) 2012 TomTom International BV
|
||||
* Written by Domenico Andreoli <domenico.andreoli@tomtom.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
*/
|
||||
|
||||
#include "mfd_feat.h"
|
||||
|
||||
#include <common.h>
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
#if defined(__VARIANT_STUTTGART_B1)
|
||||
# define MFD_VARIANT MFD_VARIANT_STUTTGART_B1
|
||||
#elif defined(__VARIANT_RENNES_B1)
|
||||
# define MFD_VARIANT MFD_VARIANT_RENNES_B1
|
||||
#elif defined(__VARIANT_RENNES_A1)
|
||||
# define MFD_VARIANT MFD_VARIANT_RENNES_A1
|
||||
#elif defined(__VARIANT_B2)
|
||||
# define MFD_VARIANT MFD_VARIANT_STRASBOURG_B2
|
||||
#elif defined(__VARIANT_B1)
|
||||
# define MFD_VARIANT MFD_VARIANT_STRASBOURG_B1
|
||||
#else
|
||||
# define MFD_VARIANT MFD_VARIANT_STRASBOURG
|
||||
#endif
|
||||
|
||||
const struct mfd_feat *mfd_lookup(const struct mfd_feat *feat)
|
||||
{
|
||||
for (; feat; feat++) {
|
||||
if (feat->mach && feat->mach != gd->bd->bi_arch_number)
|
||||
continue;
|
||||
if (feat->rev && feat->rev != MFD_VARIANT)
|
||||
continue;
|
||||
|
||||
/* there must be a default (terminator) entry that breaks the loop */
|
||||
break;
|
||||
}
|
||||
|
||||
return feat;
|
||||
}
|
||||
|
||||
u32 get_board_rev(void)
|
||||
{
|
||||
return MFD_VARIANT;
|
||||
}
|
||||
64
board/tomtom/strasbourg/mfd_feat.h
Normal file
64
board/tomtom/strasbourg/mfd_feat.h
Normal file
@ -0,0 +1,64 @@
|
||||
/*
|
||||
* Copyright (C) 2012 TomTom International BV
|
||||
* Written by Domenico Andreoli <domenico.andreoli@tomtom.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef TOMTOM_MFD_FEAT_H
|
||||
#define TOMTOM_MFD_FEAT_H
|
||||
|
||||
#define MFD_VARIANT_STRASBOURG_A2 0x10
|
||||
#define MFD_VARIANT_STRASBOURG_B1 0x11
|
||||
#define MFD_VARIANT_STRASBOURG_B2 0x12
|
||||
#define MFD_VARIANT_RENNES_A1 0x13
|
||||
#define MFD_VARIANT_RENNES_B1 0x14
|
||||
#define MFD_VARIANT_STUTTGART_B1 0x15
|
||||
|
||||
/*
|
||||
* Helper struct to hold a TomTom MFD board specific feature in form
|
||||
* of a pointer. Specific features are selected in base of the mach and
|
||||
* rev fields.
|
||||
*/
|
||||
struct mfd_feat {
|
||||
unsigned int mach;
|
||||
unsigned int rev;
|
||||
void *priv;
|
||||
};
|
||||
|
||||
/* Helper macros to init arrays of MFD features */
|
||||
#define MFD_FEAT_INIT(_mach, _rev, _feat) { \
|
||||
.mach = _mach, \
|
||||
.rev = _rev, \
|
||||
.priv = _feat, \
|
||||
}
|
||||
|
||||
/*
|
||||
* The default entry is mandatory, it grants that mfd_lookup() is not
|
||||
* an infinite loop. Entries after the default are ignored so normally
|
||||
* it is last. It also provides a means to return a possibly meaningful
|
||||
* value in case no MFD cadidate is found.
|
||||
*/
|
||||
#define MFD_DEFAULT(_feat) MFD_FEAT_INIT(0, 0, _feat)
|
||||
|
||||
#define MFD_1_0_A1(_feat) MFD_FEAT_INIT(MACH_TYPE_STRASBOURG, 0, _feat)
|
||||
#define MFD_1_0_A2(_feat) MFD_FEAT_INIT(MACH_TYPE_STRASBOURG_A2, MFD_VARIANT_STRASBOURG_A2, _feat)
|
||||
#define MFD_1_0_B1(_feat) MFD_FEAT_INIT(MACH_TYPE_STRASBOURG_A2, MFD_VARIANT_STRASBOURG_B1, _feat)
|
||||
#define MFD_1_0_B2(_feat) MFD_FEAT_INIT(MACH_TYPE_STRASBOURG_A2, MFD_VARIANT_STRASBOURG_B2, _feat)
|
||||
#define MFD_1_05(_feat) MFD_FEAT_INIT(MACH_TYPE_STRASBOURG_A2, MFD_VARIANT_RENNES_A1, _feat)
|
||||
#define MFD_1_1(_feat) MFD_FEAT_INIT(MACH_TYPE_STRASBOURG_A2, MFD_VARIANT_RENNES_B1, _feat)
|
||||
#define MFD_2_0(_feat) MFD_FEAT_INIT(MACH_TYPE_STRASBOURG_A2, MFD_VARIANT_STUTTGART_B1, _feat)
|
||||
|
||||
/* Lookup functions to find the first matching MFD feature */
|
||||
const struct mfd_feat *mfd_lookup(const struct mfd_feat *feat);
|
||||
|
||||
static inline void *mfd_feature(const struct mfd_feat *feat)
|
||||
{
|
||||
const struct mfd_feat *_f = mfd_lookup(feat);
|
||||
return _f ? _f->priv : 0;
|
||||
}
|
||||
|
||||
#endif /* TOMTOM_MFD_FEAT_H */
|
||||
16
board/tomtom/strasbourg/preboot.ush
Normal file
16
board/tomtom/strasbourg/preboot.ush
Normal file
@ -0,0 +1,16 @@
|
||||
run preboot_plat
|
||||
setenv autoscript no
|
||||
setenv bootfile /zImage
|
||||
setenv conf.file /uboot.conf
|
||||
setenv conf.maxsize 0x80
|
||||
setenv flash.part.bootfs /dev/mmcblk${kernel.bootdev}p${flash.part.bootfs.num}
|
||||
setenv flash.part.rootfs /dev/mmcblk${kernel.root.num}p${flash.part.rootfs.num}
|
||||
setenv kernel.console.options ${baudrate}
|
||||
setenv kernel.extrabootargs
|
||||
setenv timeout 2
|
||||
setenv verify no
|
||||
setenv no_trybooty no
|
||||
setenv bootargs root=${flash.part.rootfs} ${kernel.root.options} console=${kernel.console},${kernel.console.options} ${kernel.extrabootargs} androidboot.console=${kernel.console} sysboot_mode=${sysboot_mode} init=/init videoout=omap24xxvout vram=3M,0x83000000 lpj=2334720
|
||||
mw.w ${fdaddr} 0x00000000 ${conf.maxsize}
|
||||
ignore ext2load ${bootdev.class} ${bootdev}:${flash.part.bootfs.num} ${fdaddr} /uboot.conf ${conf.maxsize}
|
||||
ignore bootconf ${fdaddr}
|
||||
677
board/tomtom/strasbourg/strasbourg.c
Normal file
677
board/tomtom/strasbourg/strasbourg.c
Normal file
@ -0,0 +1,677 @@
|
||||
|
||||
/*
|
||||
* (C) Copyright 2004-2009
|
||||
* Texas Instruments, <www.ti.com>
|
||||
* Richard Woodruff <r-woodruff2@ti.com>
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
#include <common.h>
|
||||
#include <asm/arch/cpu.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/arch/bits.h>
|
||||
#include <asm/arch/mux.h>
|
||||
#include <asm/arch/sys_proto.h>
|
||||
#include <asm/arch/sys_info.h>
|
||||
#include <asm/arch/clocks.h>
|
||||
#include <asm/arch/mem.h>
|
||||
#include <asm/arch/gpio.h>
|
||||
#include <asm/arch/i2c.h>
|
||||
#include <asm/memprot.h>
|
||||
#include <tomtom.h>
|
||||
#include <i2c.h>
|
||||
#include <mmc.h>
|
||||
#include <asm/mach-types.h>
|
||||
#include <linux/mtd/nand_ecc.h>
|
||||
#include <twl4030.h>
|
||||
#include <flipflop.h>
|
||||
#include "logo.h"
|
||||
#include "mfd_feat.h"
|
||||
#include <plat-tomtom/offenburg/offenburg.h>
|
||||
|
||||
/* Before including the padconfig settings, we have to set proper config */
|
||||
#define BOOTLOADER_UBOOT_PADCONFIG
|
||||
#if defined(__VARIANT_STUTTGART_B1)
|
||||
# include <linux/padconfig_stuttgart_b1.h>
|
||||
#elif defined( __VARIANT_RENNES_B1)
|
||||
# include <linux/padconfig_rennes_b1.h>
|
||||
#elif defined(__VARIANT_A1)
|
||||
# include <linux/padconfig_strasbourg.h>
|
||||
#else
|
||||
# include <linux/padconfig_strasbourg_a2.h>
|
||||
#endif
|
||||
|
||||
#define GPIO_LCD_UD (12)
|
||||
#define GPIO_LCD_LR (19)
|
||||
#define GPIO_LCM_PWR_ON (137)
|
||||
#define GPIO_nLCD_RESET (156)
|
||||
#define GPIO_BACKLIGHT_ON (65)
|
||||
#define GPIO_SENSE_11V0 (17)
|
||||
#define SENSE_11V0_MAX_RETRY (5)
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
extern void detect_boot_mode(void);
|
||||
extern void hw_watchdog_init(void);
|
||||
|
||||
extern const uchar __diagsys_start;
|
||||
#define DIAGSYS_ADDR_START (&__diagsys_start)
|
||||
extern const uchar __diagsys_end;
|
||||
#define DIAGSYS_ADDR_END (&__diagsys_end)
|
||||
#define DIAGSYS_LEN ((size_t) (DIAGSYS_ADDR_END - \
|
||||
DIAGSYS_ADDR_START))
|
||||
#define DIAGSYS_ADDR_NOR ((uchar *) 0x08300000UL)
|
||||
|
||||
#define DEFAULT_FDT_START ((uchar *) 0x81FE0000UL)
|
||||
#define DEFAULT_FDT_LEN ((size_t) 0xe00U) /* 7 sectors */
|
||||
|
||||
unsigned exec_applet = 0;
|
||||
|
||||
extern const int __framebuffer_start;
|
||||
#define FRAMEBUFFER_ADDR_START 0x83000000
|
||||
extern const int __framebuffer_end;
|
||||
#define FRAMEBUFFER_ADDR_END (&__framebuffer_end)
|
||||
#define FRAMEBUFFER_LEN ((size_t) (FRAMEBUFFER_ADDR_END - \
|
||||
FRAMEBUFFER_ADDR_START))
|
||||
#define FDT_SCR_ROT_OFFSET (0x1150)
|
||||
#define FDT_SCR_VCOM_OFFSET (0x124e)
|
||||
#define EOL_SAT_TUN_OFFSET (0x0113)
|
||||
|
||||
/* Timer related definitions */
|
||||
#define OMAP34XX_GPTIMER10_BASE (0x48086000)
|
||||
#define TIMER_CTRL_GPOCFG (1 << 14)
|
||||
#define TIMER_CTRL_CAPTMODE (1 << 13)
|
||||
#define TIMER_CTRL_PT (1 << 12)
|
||||
#define TIMER_CTRL_TRG_OVERFLOW (1 << 10)
|
||||
#define TIMER_CTRL_TRG_OVERFLOW_MATCH (2 << 10)
|
||||
#define TIMER_CTRL_TCM_LOWTOHIGH (0x1 << 8)
|
||||
#define TIMER_CTRL_TCM_HIGHTOLOW (0x2 << 8)
|
||||
#define TIMER_CTRL_TCM_BOTHEDGES (0x3 << 8)
|
||||
#define TIMER_CTRL_SCPWM (1 << 7)
|
||||
#define TIMER_CTRL_CE (1 << 6) /* compare enable */
|
||||
#define TIMER_CTRL_PRE (1 << 5) /* prescaler enable */
|
||||
#define TIMER_CTRL_POSTED (1 << 2)
|
||||
#define TIMER_CTRL_AR (1 << 1) /* auto-reload enable */
|
||||
#define TIMER_CTRL_ST (1 << 0) /* start timer */
|
||||
|
||||
/* CONTROL_PROG_IO1 bit definitions */
|
||||
#define PRG_SDMMC1_SPEEDCTRL (1 << 20)
|
||||
|
||||
void eth_init(void *);
|
||||
|
||||
#ifdef __VARIANT_A1
|
||||
# define BOOTDEV_SDCARD 0
|
||||
# define BOOTDEV_MOVI 1
|
||||
|
||||
#else
|
||||
# define BOOTDEV_MOVI 0
|
||||
#endif
|
||||
|
||||
extern unsigned char __mmu_table_start;
|
||||
|
||||
/* Fudge kernel bootdevice on A1 if sd card is present:
|
||||
* - root=/dev/mmcblk0p2 if no SD card present OR if booting from SD
|
||||
* - root=/dev/mmcblk1p2 if have SD card and booting from movi
|
||||
*/
|
||||
int kernel_root_num = 0;
|
||||
|
||||
static unsigned char sat_tun = 0;
|
||||
|
||||
/*****************************************
|
||||
* Routine: board_init
|
||||
* Description: Early hardware init.
|
||||
*****************************************/
|
||||
int board_init(void)
|
||||
{
|
||||
detect_boot_mode();
|
||||
|
||||
if (get_device_type() != GP_DEVICE) {
|
||||
set_default_map((uint32_t) &__mmu_table_start);
|
||||
}
|
||||
dcache_enable();
|
||||
|
||||
if (SYSBOOT_MODE_COLD == gd->tomtom.sysboot_mode)
|
||||
/* cold boot => initialize the flipflop, we can't rely on the
|
||||
state of the scratchpad register */
|
||||
flipflop_set(0);
|
||||
|
||||
/* In general, load the kernel from MoviNAND; on A1 the SD slot is useful for recovery */
|
||||
gd->tomtom.bootdev = BOOTDEV_MOVI;
|
||||
|
||||
/* STRBDEV-2049 Reduce the drive strength on the MoviNand signals */
|
||||
__raw_writel(__raw_readl(CONTROL_PROG_IO1) & ~PRG_SDMMC1_SPEEDCTRL, CONTROL_PROG_IO1);
|
||||
|
||||
mmc_init(BOOTDEV_MOVI);
|
||||
#ifdef BOOTDEV_SDCARD
|
||||
kernel_root_num = !mmc_init(BOOTDEV_SDCARD);
|
||||
|
||||
if ((__raw_readl(0x480029c0) & 0xff) == 0x6) { /* Booted from the A1 SD slot? */
|
||||
gd->tomtom.bootdev = BOOTDEV_SDCARD;
|
||||
kernel_root_num = 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
/* Enable GPIO4 clocks FCLK and ICLK */
|
||||
__raw_writel(__raw_readl(CM_FCLKEN_WKUP) | (1 << CLKEN_PER_EN_GPIO2_BIT),
|
||||
CM_FCLKEN_WKUP);
|
||||
__raw_writel(__raw_readl(CM_ICLKEN_WKUP) | (1 << CLKEN_PER_EN_GPIO2_BIT),
|
||||
CM_ICLKEN_WKUP);
|
||||
delay(10000);
|
||||
|
||||
#if !defined(__VARIANT_A1)
|
||||
if (!(__raw_readl(OMAP34XX_GPIO2_BASE + OMAP34XX_GPIO_DATAIN) & GPIO9)) {
|
||||
memcpy(DIAGSYS_ADDR_START, DIAGSYS_ADDR_NOR, DIAGSYS_LEN);
|
||||
memcpy(DEFAULT_FDT_START, DIAGSYS_ADDR_START+DIAGSYS_LEN-DEFAULT_FDT_LEN-512, DEFAULT_FDT_LEN);
|
||||
exec_applet=1;
|
||||
}
|
||||
#endif
|
||||
|
||||
gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
|
||||
#if defined(__VARIANT_A1)
|
||||
gd->bd->bi_arch_number = MACH_TYPE_STRASBOURG; /* Linux mach id */
|
||||
#else
|
||||
gd->bd->bi_arch_number = MACH_TYPE_STRASBOURG_A2; /* Linux mach id */
|
||||
#endif
|
||||
gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100); /* boot param addr */
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**********************************************************
|
||||
* Routine: dss_init
|
||||
* Description: Initializes the display and fills the
|
||||
framebuffer with the logo.
|
||||
**********************************************************/
|
||||
void dss_init(void)
|
||||
{
|
||||
unsigned long i, y;
|
||||
unsigned long p = 0;
|
||||
unsigned char pixel[3];
|
||||
|
||||
/* Draw logo into frame buffer */
|
||||
for (i = 0; i < header_data_rle_size; i++) {
|
||||
for (y = 0; y < header_data_rle[i][0]; y++) {
|
||||
HEADER_PIXEL(header_data_rle[i][1], pixel);
|
||||
*((unsigned int *)(FRAMEBUFFER_ADDR_START + p*4)) =
|
||||
(pixel[0] << 16) |
|
||||
(pixel[1] << 8) |
|
||||
(pixel[2]);
|
||||
p++;
|
||||
}
|
||||
}
|
||||
|
||||
/* Reset lcd */
|
||||
if (omap_request_gpio(GPIO_nLCD_RESET)) {
|
||||
printf ("Error when requesting nLCD_RESET\n");
|
||||
return;
|
||||
}
|
||||
omap_set_gpio_dataout(GPIO_nLCD_RESET, 0);
|
||||
omap_set_gpio_direction(GPIO_nLCD_RESET, 0);
|
||||
|
||||
/* Enable lcm power */
|
||||
if (omap_request_gpio(GPIO_LCM_PWR_ON)) {
|
||||
printf ("Error when requesting LCM_PWR_ON\n");
|
||||
return;
|
||||
}
|
||||
|
||||
#if defined(__VARIANT_B2) || defined(__VARIANT_RENNES_A1) || defined(__VARIANT_RENNES_B1)
|
||||
if (omap_request_gpio(GPIO_SENSE_11V0)) {
|
||||
printf ("Error when requesting LCM_PWR_ON\n");
|
||||
return;
|
||||
}
|
||||
omap_set_gpio_direction(GPIO_SENSE_11V0, 1);
|
||||
omap_set_gpio_dataout(GPIO_LCM_PWR_ON, 0);
|
||||
omap_set_gpio_direction(GPIO_LCM_PWR_ON, 0);
|
||||
for (i = 0; i < SENSE_11V0_MAX_RETRY; i++) {
|
||||
/* attempt to activate LCD power supply */
|
||||
omap_set_gpio_dataout(GPIO_LCM_PWR_ON, 1);
|
||||
/* T8 */
|
||||
delay(600000); /* 2 ms */
|
||||
if (omap_get_gpio_datain(GPIO_SENSE_11V0))
|
||||
break;
|
||||
}
|
||||
if (i == SENSE_11V0_MAX_RETRY)
|
||||
printf("Failed to power on the LCM!!!");
|
||||
#else
|
||||
omap_set_gpio_dataout(GPIO_LCM_PWR_ON, 1);
|
||||
omap_set_gpio_direction(GPIO_LCM_PWR_ON, 0);
|
||||
#endif
|
||||
delay (9000000); /* 30 ms */
|
||||
|
||||
/* Release Reset line */
|
||||
omap_set_gpio_dataout(GPIO_nLCD_RESET, 1);
|
||||
delay (9000000); /* 30 ms */
|
||||
|
||||
/* Setup lcm */
|
||||
writel(0x00000001, 0x48050010);
|
||||
writel(0x00000000, 0x48050040);
|
||||
/* Enable RFBI set in bypass mode */
|
||||
writel(0x00000002, 0x48050840);
|
||||
writel(0x00310000, 0x48050860);
|
||||
/* Config display controller */
|
||||
writel(0x05F05F00, 0x48050464);
|
||||
writel(0x00a00a00, 0x48050468);
|
||||
writel(0x00000000, 0x4805046c);
|
||||
writel(0x00010006, 0x48050470);
|
||||
writel(0x000000ff, 0x48050474);
|
||||
writel(0x00000000, 0x48050478);
|
||||
writel(0x01DF031F, 0x4805047c);
|
||||
writel(FRAMEBUFFER_ADDR_START, 0x48050480);
|
||||
writel(0x01df031f, 0x4805048c);
|
||||
writel(0x000000b1, 0x480504a0);
|
||||
writel(0x03ff03c0, 0x480504a4);
|
||||
writel(0x08018309, 0x48050440);//DISPC_CONTROL enable disp
|
||||
}
|
||||
|
||||
/**********************************************************
|
||||
* Routine: config_screen_rotation
|
||||
* Description: Configure the screen rotation based on the
|
||||
EEPROM setting
|
||||
**********************************************************/
|
||||
static void config_screen_rotation(void)
|
||||
{
|
||||
unsigned char fdt_rotation;
|
||||
|
||||
/* Request the rotation GPIOs */
|
||||
if (omap_request_gpio(GPIO_LCD_UD)) {
|
||||
printf ("Error when requesting LCD_UD\n");
|
||||
return;
|
||||
}
|
||||
if (omap_request_gpio(GPIO_LCD_LR)) {
|
||||
printf ("Error when requesting LCD_LR\n");
|
||||
return;
|
||||
}
|
||||
|
||||
/* Read the rotation value from EEPROM */
|
||||
select_bus(CFG_I2C_EEPROM_BUS, OMAP_I2C_FAST_MODE);
|
||||
if (eeprom_read (CFG_DEF_EEPROM_ADDR, FDT_SCR_ROT_OFFSET, &fdt_rotation, 1)) {
|
||||
printf("** Error reading screen rotation from EEPROM\n");
|
||||
fdt_rotation = 0;
|
||||
}
|
||||
select_bus(CFG_I2C_BUS, CFG_I2C_SPEED);
|
||||
|
||||
/* Set the rotation GPIOs accordingly */
|
||||
if (fdt_rotation == '1') {
|
||||
omap_set_gpio_dataout(GPIO_LCD_UD, 0);
|
||||
omap_set_gpio_dataout(GPIO_LCD_LR, 1);
|
||||
}
|
||||
else {
|
||||
omap_set_gpio_dataout(GPIO_LCD_UD, 1);
|
||||
omap_set_gpio_dataout(GPIO_LCD_LR, 0);
|
||||
}
|
||||
omap_set_gpio_direction(GPIO_LCD_UD, 0);
|
||||
omap_set_gpio_direction(GPIO_LCD_LR, 0);
|
||||
}
|
||||
|
||||
static unsigned char vcom_to_pwmaoff_rennes_b1(unsigned char vcom)
|
||||
{
|
||||
unsigned char pwmaoff;
|
||||
|
||||
if (vcom >= 0x80)
|
||||
pwmaoff = 0x3f;
|
||||
else if (vcom == 0x7f)
|
||||
pwmaoff = 0x01;
|
||||
else if (vcom == 0x00)
|
||||
pwmaoff = 0x00;
|
||||
else
|
||||
pwmaoff = vcom + 1;
|
||||
|
||||
return pwmaoff;
|
||||
}
|
||||
|
||||
static void config_screen_vcom_rennes_b1(void)
|
||||
{
|
||||
unsigned char vcom, data;
|
||||
|
||||
/* Read the vcom value from EEPROM */
|
||||
select_bus(CFG_I2C_EEPROM_BUS, OMAP_I2C_FAST_MODE);
|
||||
if (eeprom_read (CFG_DEF_EEPROM_ADDR, FDT_SCR_VCOM_OFFSET, &vcom, 1)) {
|
||||
printf("** Error reading screen VCOM from EEPROM\n");
|
||||
vcom = 0xff;
|
||||
}
|
||||
select_bus(CFG_I2C_BUS, CFG_I2C_SPEED);
|
||||
|
||||
/* clear VIBRA_CTL[0] - VIBRA_EN */
|
||||
i2c_read(0x49, 0x45, 1, &data, 1);
|
||||
data &= ~1;
|
||||
i2c_write(0x49, 0x45, 1, &data, 1);
|
||||
|
||||
/* set LEDEN[0] - LEDAON */
|
||||
i2c_read(0x4a, 0xee, 1, &data, 1);
|
||||
data |= 1;
|
||||
i2c_write(0x4a, 0xee, 1, &data, 1);
|
||||
|
||||
/* set LEDEN[4] - LEDAPWM */
|
||||
i2c_read(0x4a, 0xee, 1, &data, 1);
|
||||
data |= (1 << 4);
|
||||
i2c_write(0x4a, 0xee, 1, &data, 1);
|
||||
|
||||
/* clear LEDEN[2] - LEDAEXT */
|
||||
i2c_read(0x4a, 0xee, 1, &data, 1);
|
||||
data &= ~(1 << 2);
|
||||
i2c_write(0x4a, 0xee, 1, &data, 1);
|
||||
|
||||
/* set PWMAON */
|
||||
data = 1;
|
||||
i2c_write(0x4a, 0xef, 1, &data, 1);
|
||||
|
||||
/* set PWMAOFF */
|
||||
data = vcom_to_pwmaoff_rennes_b1(vcom);
|
||||
i2c_write(0x4a, 0xf0, 1, &data, 1);
|
||||
}
|
||||
|
||||
static void switch_on_bl_pmic_pwm(void)
|
||||
{
|
||||
unsigned char data;
|
||||
|
||||
/* PWM0ON */
|
||||
data = 0x2;
|
||||
i2c_write(0x4a, 0xF8, 1, &data, 1);
|
||||
/* PWM0OFF */
|
||||
data = 0x44;
|
||||
i2c_write(0x4a, 0xF9, 1, &data, 1);
|
||||
/* PMBR1 */
|
||||
i2c_read(0x49, 0x92, 1, &data, 1);
|
||||
data |= (1<<2);
|
||||
i2c_write(0x49, 0x92, 1, &data, 1);
|
||||
/* GPBR1 */
|
||||
i2c_read(0x49, 0x91, 1, &data, 1);
|
||||
data |= ((1<<2) | (1));
|
||||
i2c_write(0x49, 0x91, 1, &data, 1);
|
||||
|
||||
/* Set GPIO13 (BL enable) output high*/
|
||||
data = 0x0;
|
||||
i2c_read(0x49, 0x9c, 1, &data, 1);
|
||||
data |= 0x20;
|
||||
i2c_write(0x49, 0x9c, 1, &data, 1);
|
||||
data = 0x0;
|
||||
i2c_read(0x49, 0x9f, 1, &data, 1);
|
||||
data |= 0x20;
|
||||
i2c_write(0x49, 0x9f, 1, &data, 1);
|
||||
}
|
||||
|
||||
static void switch_on_bl_omap_pwm(void)
|
||||
{
|
||||
/* Configure GPT10 source (1: sys_clk, 0: 32K_clk) */
|
||||
sr32(CM_CLKSEL_CORE, 6, 1, 1);
|
||||
|
||||
/* TSICR register: non-posted mode */
|
||||
writel(0x0, OMAP34XX_GPTIMER10_BASE + TSICR);
|
||||
|
||||
/* Timer load register */
|
||||
writel(0xfffcd37e, OMAP34XX_GPTIMER10_BASE + TLDR);
|
||||
|
||||
/* Trigger register */
|
||||
writel(0x0, OMAP34XX_GPTIMER10_BASE + TTGR);
|
||||
|
||||
/* Match register */
|
||||
writel(0xfffdc5a7, OMAP34XX_GPTIMER10_BASE + TMAR);
|
||||
|
||||
/* Timer counter register */
|
||||
writel(0xfffffffe, OMAP34XX_GPTIMER10_BASE + TCRR);
|
||||
|
||||
/* Start the timer */
|
||||
writel(TIMER_CTRL_ST | TIMER_CTRL_AR | TIMER_CTRL_CE |
|
||||
TIMER_CTRL_PT | TIMER_CTRL_TRG_OVERFLOW_MATCH,
|
||||
OMAP34XX_GPTIMER10_BASE + TCLR);
|
||||
|
||||
/* Enable the backlight */
|
||||
if (omap_request_gpio(GPIO_BACKLIGHT_ON)) {
|
||||
printf ("Error when requesting BACKLIGHT_ON gpio\n");
|
||||
return;
|
||||
}
|
||||
omap_set_gpio_dataout(GPIO_BACKLIGHT_ON, 1);
|
||||
omap_set_gpio_direction(GPIO_BACKLIGHT_ON, 0);
|
||||
}
|
||||
|
||||
static void switch_on_bl_omap_pwm_rennes_b1(void)
|
||||
{
|
||||
unsigned char data;
|
||||
|
||||
/*
|
||||
* switch off VDD_1V8_AUX2 so to hide the otherwise visible
|
||||
* white flash on reboot
|
||||
*/
|
||||
i2c_read(0x4b, 0x76, 1, &data, 1);
|
||||
data &= ~0x20;
|
||||
i2c_write(0x4b, 0x76, 1, &data, 1);
|
||||
|
||||
/* Configure the screen VCOM based on the EEPROM value */
|
||||
config_screen_vcom_rennes_b1();
|
||||
|
||||
/* continue with the usual omap pwm configuration */
|
||||
switch_on_bl_omap_pwm();
|
||||
}
|
||||
|
||||
static struct mfd_feat bl_feats[] = {
|
||||
MFD_1_0_A2(switch_on_bl_pmic_pwm),
|
||||
MFD_1_0_B1(switch_on_bl_pmic_pwm),
|
||||
MFD_1_0_B2(switch_on_bl_omap_pwm),
|
||||
MFD_1_05(switch_on_bl_omap_pwm),
|
||||
MFD_1_1(switch_on_bl_omap_pwm_rennes_b1),
|
||||
MFD_2_0(switch_on_bl_omap_pwm_rennes_b1),
|
||||
MFD_DEFAULT(NULL),
|
||||
};
|
||||
|
||||
/**********************************************************
|
||||
* Routine: switch_on_bl
|
||||
* Description: Switches on the display backlight
|
||||
**********************************************************/
|
||||
static void switch_on_bl(void)
|
||||
{
|
||||
void (*switch_mfd_bl)(void) = mfd_feature(bl_feats);
|
||||
|
||||
/* Configure the screen rotation based on the EEPROM value */
|
||||
config_screen_rotation();
|
||||
|
||||
if (switch_mfd_bl)
|
||||
switch_mfd_bl();
|
||||
|
||||
/* Print out APTS tag */
|
||||
printf ("\n[APTS Logo/]\n\n");
|
||||
}
|
||||
|
||||
static void detect_sat_tuner_stuttgart_b1(void)
|
||||
{
|
||||
select_bus(CFG_I2C_EEPROM_BUS, OMAP_I2C_FAST_MODE);
|
||||
if (eeprom_read(CFG_DEF_EEPROM_ADDR, EOL_SAT_TUN_OFFSET, &sat_tun, 1))
|
||||
printf("** Error reading Diags_conf_13 Satellite Tuner\n");
|
||||
select_bus(CFG_I2C_BUS, CFG_I2C_SPEED);
|
||||
|
||||
/* check bit 2 (SAT_CNF) */
|
||||
sat_tun = (sat_tun != 0xff) && (sat_tun & 0x4);
|
||||
}
|
||||
|
||||
static struct mfd_feat sat_tun_feats[] = {
|
||||
MFD_2_0(detect_sat_tuner_stuttgart_b1),
|
||||
MFD_DEFAULT(NULL),
|
||||
};
|
||||
|
||||
/*******************************************************
|
||||
* Routine: misc_init_r
|
||||
* Description: Init ethernet (done here so udelay works)
|
||||
********************************************************/
|
||||
int misc_init_r(void)
|
||||
{
|
||||
void (*detect_mfd_sat_tun)(void) = mfd_feature(sat_tun_feats);
|
||||
|
||||
#ifdef CONFIG_DRIVER_OMAP34XX_I2C
|
||||
unsigned char data;
|
||||
|
||||
i2c_init(CFG_I2C_SPEED, CFG_I2C_SLAVE);
|
||||
|
||||
twl4030_usb_init();
|
||||
|
||||
/* Disable the PMU watchdog. The main SoC watchdog
|
||||
* is enabled by this time */
|
||||
data = 0;
|
||||
i2c_write(0x4b, 0x5e, 1, &data, 1);
|
||||
#endif
|
||||
|
||||
if (detect_mfd_sat_tun)
|
||||
detect_mfd_sat_tun();
|
||||
|
||||
switch_on_bl();
|
||||
dieid_num_r();
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
/*
|
||||
* IEN - Input Enable
|
||||
* IDIS - Input Disable
|
||||
* PTD - Pull type Down
|
||||
* PTU - Pull type Up
|
||||
* DIS - Pull type selection is inactive
|
||||
* EN - Pull type selection is active
|
||||
* M0 - Mode 0
|
||||
* The commented string gives the final mux configuration for that pin
|
||||
*/
|
||||
#define MUX_DEFAULT_ES2()\
|
||||
/*Die to Die */\
|
||||
MUX_VAL(CP(d2d_mcad0), (IEN | PTD | EN | M0)) /*d2d_mcad0*/\
|
||||
MUX_VAL(CP(d2d_mcad1), (IEN | PTD | EN | M0)) /*d2d_mcad1*/\
|
||||
MUX_VAL(CP(d2d_mcad2), (IEN | PTD | EN | M0)) /*d2d_mcad2*/\
|
||||
MUX_VAL(CP(d2d_mcad3), (IEN | PTD | EN | M0)) /*d2d_mcad3*/\
|
||||
MUX_VAL(CP(d2d_mcad4), (IEN | PTD | EN | M0)) /*d2d_mcad4*/\
|
||||
MUX_VAL(CP(d2d_mcad5), (IEN | PTD | EN | M0)) /*d2d_mcad5*/\
|
||||
MUX_VAL(CP(d2d_mcad6), (IEN | PTD | EN | M0)) /*d2d_mcad6*/\
|
||||
MUX_VAL(CP(d2d_mcad7), (IEN | PTD | EN | M0)) /*d2d_mcad7*/\
|
||||
MUX_VAL(CP(d2d_mcad8), (IEN | PTD | EN | M0)) /*d2d_mcad8*/\
|
||||
MUX_VAL(CP(d2d_mcad9), (IEN | PTD | EN | M0)) /*d2d_mcad9*/\
|
||||
MUX_VAL(CP(d2d_mcad10), (IEN | PTD | EN | M0)) /*d2d_mcad10*/\
|
||||
MUX_VAL(CP(d2d_mcad11), (IEN | PTD | EN | M0)) /*d2d_mcad11*/\
|
||||
MUX_VAL(CP(d2d_mcad12), (IEN | PTD | EN | M0)) /*d2d_mcad12*/\
|
||||
MUX_VAL(CP(d2d_mcad13), (IEN | PTD | EN | M0)) /*d2d_mcad13*/\
|
||||
MUX_VAL(CP(d2d_mcad14), (IEN | PTD | EN | M0)) /*d2d_mcad14*/\
|
||||
MUX_VAL(CP(d2d_mcad15), (IEN | PTD | EN | M0)) /*d2d_mcad15*/\
|
||||
MUX_VAL(CP(d2d_mcad16), (IEN | PTD | EN | M0)) /*d2d_mcad16*/\
|
||||
MUX_VAL(CP(d2d_mcad17), (IEN | PTD | EN | M0)) /*d2d_mcad17*/\
|
||||
MUX_VAL(CP(d2d_mcad18), (IEN | PTD | EN | M0)) /*d2d_mcad18*/\
|
||||
MUX_VAL(CP(d2d_mcad19), (IEN | PTD | EN | M0)) /*d2d_mcad19*/\
|
||||
MUX_VAL(CP(d2d_mcad20), (IEN | PTD | EN | M0)) /*d2d_mcad20*/\
|
||||
MUX_VAL(CP(d2d_mcad21), (IEN | PTD | EN | M0)) /*d2d_mcad21*/\
|
||||
MUX_VAL(CP(d2d_mcad22), (IEN | PTD | EN | M0)) /*d2d_mcad22*/\
|
||||
MUX_VAL(CP(d2d_mcad23), (IEN | PTD | EN | M0)) /*d2d_mcad23*/\
|
||||
MUX_VAL(CP(d2d_mcad24), (IEN | PTD | EN | M0)) /*d2d_mcad24*/\
|
||||
MUX_VAL(CP(d2d_mcad25), (IEN | PTD | EN | M0)) /*d2d_mcad25*/\
|
||||
MUX_VAL(CP(d2d_mcad26), (IEN | PTD | EN | M0)) /*d2d_mcad26*/\
|
||||
MUX_VAL(CP(d2d_mcad27), (IEN | PTD | EN | M0)) /*d2d_mcad27*/\
|
||||
MUX_VAL(CP(d2d_mcad28), (IEN | PTD | EN | M0)) /*d2d_mcad28*/\
|
||||
MUX_VAL(CP(d2d_mcad29), (IEN | PTD | EN | M0)) /*d2d_mcad29*/\
|
||||
MUX_VAL(CP(d2d_mcad30), (IEN | PTD | EN | M0)) /*d2d_mcad30*/\
|
||||
MUX_VAL(CP(d2d_mcad31), (IEN | PTD | EN | M0)) /*d2d_mcad31*/\
|
||||
MUX_VAL(CP(d2d_mcad32), (IEN | PTD | EN | M0)) /*d2d_mcad32*/\
|
||||
MUX_VAL(CP(d2d_mcad33), (IEN | PTD | EN | M0)) /*d2d_mcad33*/\
|
||||
MUX_VAL(CP(d2d_mcad34), (IEN | PTD | EN | M0)) /*d2d_mcad34*/\
|
||||
MUX_VAL(CP(d2d_mcad35), (IEN | PTD | EN | M0)) /*d2d_mcad35*/\
|
||||
MUX_VAL(CP(d2d_mcad36), (IEN | PTD | EN | M0)) /*d2d_mcad36*/\
|
||||
MUX_VAL(CP(d2d_clk26mi), (IEN | PTD | DIS | M0)) /*d2d_clk26mi */\
|
||||
MUX_VAL(CP(d2d_nrespwron ), (IEN | PTD | EN | M0)) /*d2d_nrespwron*/\
|
||||
MUX_VAL(CP(d2d_nreswarm), (IEN | PTU | EN | M0)) /*d2d_nreswarm */\
|
||||
MUX_VAL(CP(d2d_arm9nirq), (IEN | PTD | DIS | M0)) /*d2d_arm9nirq */\
|
||||
MUX_VAL(CP(d2d_uma2p6fiq ), (IEN | PTD | DIS | M0)) /*d2d_uma2p6fiq*/\
|
||||
MUX_VAL(CP(d2d_spint), (IEN | PTD | EN | M0)) /*d2d_spint*/\
|
||||
MUX_VAL(CP(d2d_frint), (IEN | PTD | EN | M0)) /*d2d_frint*/\
|
||||
MUX_VAL(CP(d2d_dmareq0), (IEN | PTD | DIS | M0)) /*d2d_dmareq0 */\
|
||||
MUX_VAL(CP(d2d_dmareq1), (IEN | PTD | DIS | M0)) /*d2d_dmareq1 */\
|
||||
MUX_VAL(CP(d2d_dmareq2), (IEN | PTD | DIS | M0)) /*d2d_dmareq2 */\
|
||||
MUX_VAL(CP(d2d_dmareq3), (IEN | PTD | DIS | M0)) /*d2d_dmareq3 */\
|
||||
MUX_VAL(CP(d2d_n3gtrst), (IEN | PTD | DIS | M0)) /*d2d_n3gtrst */\
|
||||
MUX_VAL(CP(d2d_n3gtdi), (IEN | PTD | DIS | M0)) /*d2d_n3gtdi*/\
|
||||
MUX_VAL(CP(d2d_n3gtdo), (IEN | PTD | DIS | M0)) /*d2d_n3gtdo*/\
|
||||
MUX_VAL(CP(d2d_n3gtms), (IEN | PTD | DIS | M0)) /*d2d_n3gtms*/\
|
||||
MUX_VAL(CP(d2d_n3gtck), (IEN | PTD | DIS | M0)) /*d2d_n3gtck*/\
|
||||
MUX_VAL(CP(d2d_n3grtck), (IEN | PTD | DIS | M0)) /*d2d_n3grtck */\
|
||||
MUX_VAL(CP(d2d_mstdby), (IEN | PTU | EN | M0)) /*d2d_mstdby*/\
|
||||
MUX_VAL(CP(d2d_swakeup), (IEN | PTD | EN | M0)) /*d2d_swakeup */\
|
||||
MUX_VAL(CP(d2d_idlereq), (IEN | PTD | DIS | M0)) /*d2d_idlereq */\
|
||||
MUX_VAL(CP(d2d_idleack), (IEN | PTU | EN | M0)) /*d2d_idleack */\
|
||||
MUX_VAL(CP(d2d_mwrite), (IEN | PTD | DIS | M0)) /*d2d_mwrite*/\
|
||||
MUX_VAL(CP(d2d_swrite), (IEN | PTD | DIS | M0)) /*d2d_swrite*/\
|
||||
MUX_VAL(CP(d2d_mread), (IEN | PTD | DIS | M0)) /*d2d_mread*/\
|
||||
MUX_VAL(CP(d2d_sread), (IEN | PTD | DIS | M0)) /*d2d_sread*/\
|
||||
MUX_VAL(CP(d2d_mbusflag), (IEN | PTD | DIS | M0)) /*d2d_mbusflag */\
|
||||
MUX_VAL(CP(d2d_sbusflag), (IEN | PTD | DIS | M0)) /*d2d_sbusflag */\
|
||||
MUX_VAL(CP(sdrc_cke0), (IDIS | PTU | EN | M0)) /*sdrc_cke0 */\
|
||||
MUX_VAL(CP(sdrc_cke1), (IDIS | PTD | DIS | M7)) /*sdrc_cke1 unused*/
|
||||
|
||||
/**********************************************************
|
||||
* Routine: set_muxconf_regs
|
||||
* Description: Setting up the configuration Mux registers
|
||||
* specific to the hardware. Many pins need
|
||||
* to be moved from protect to primary mode.
|
||||
*********************************************************/
|
||||
void set_muxconf_regs(void)
|
||||
{
|
||||
PADCONFIG_SETTINGS_UBOOT
|
||||
PADCONFIG_SETTINGS_COMMON
|
||||
MUX_DEFAULT_ES2();
|
||||
}
|
||||
|
||||
/******************************************************************************
|
||||
* Routine: update_mux()
|
||||
* Description:Update balls which are different between boards. All should be
|
||||
* updated to match functionality. However, I'm only updating ones
|
||||
* which I'll be using for now. When power comes into play they
|
||||
* all need updating.
|
||||
*****************************************************************************/
|
||||
void update_mux(u32 btype, u32 mtype)
|
||||
{
|
||||
/* NOTHING as of now... */
|
||||
}
|
||||
|
||||
void board_env_init(void)
|
||||
{
|
||||
char ulong_str[16]; /* Needs to be as long as "0x12345678" + '\0' */
|
||||
|
||||
/* Replace with factory data when available */
|
||||
switch(gd->bd->bi_arch_number) {
|
||||
case MACH_TYPE_STRASBOURG_A2:
|
||||
setenv("kernel.console", "ttyO2");
|
||||
break;
|
||||
case MACH_TYPE_STRASBOURG:
|
||||
default:
|
||||
setenv("kernel.console", "ttyO0");
|
||||
break;
|
||||
}
|
||||
|
||||
/* disable the console in case of satellite tuner */
|
||||
if (sat_tun) {
|
||||
printf("## Silent boot due to SAT_CNF\n\n");
|
||||
setenv("kernel.console", "");
|
||||
}
|
||||
|
||||
sprintf(ulong_str, "%u", kernel_root_num);
|
||||
setenv("kernel.root.num", ulong_str);
|
||||
|
||||
sprintf(ulong_str, "%#lx", (unsigned long) DIAGSYS_ADDR_START);
|
||||
setenv("applet.addr", ulong_str);
|
||||
|
||||
if (exec_applet) {
|
||||
sprintf(ulong_str, "%u", DIAGSYS_LEN-44); /* 44 byte DSA sig at end */
|
||||
setenv("applet.size", ulong_str);
|
||||
|
||||
sprintf(ulong_str, "%lx", DEFAULT_FDT_START);
|
||||
setenv("fdt.default.addr", ulong_str);
|
||||
|
||||
setenv("exec_applet", "yes");
|
||||
} else {
|
||||
setenv("exec_applet", "no");
|
||||
}
|
||||
}
|
||||
118
board/tomtom/strasbourg/u-boot.lds
Normal file
118
board/tomtom/strasbourg/u-boot.lds
Normal file
@ -0,0 +1,118 @@
|
||||
/*
|
||||
* January 2004 - Changed to support H4 device
|
||||
* Copyright (c) 2004 Texas Instruments
|
||||
*
|
||||
* (C) Copyright 2002
|
||||
* Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
|
||||
OUTPUT_ARCH(arm)
|
||||
ENTRY(_start)
|
||||
SECTIONS
|
||||
{
|
||||
. = 0x00000000;
|
||||
|
||||
/* NOBITS section to contain the kernel */
|
||||
. = 0x80008000;
|
||||
.xkern . (COPY) :
|
||||
{
|
||||
__xkern_start = .;
|
||||
. = . + 8M;
|
||||
__xkern_end = .;
|
||||
}
|
||||
|
||||
.text :
|
||||
{
|
||||
cpu/omap3/start.o (.text)
|
||||
*(.text)
|
||||
}
|
||||
|
||||
. = ALIGN(4);
|
||||
.rodata : { *(.rodata) }
|
||||
|
||||
. = ALIGN(4);
|
||||
.data : { *(.data) }
|
||||
|
||||
. = ALIGN(4);
|
||||
.bootscript : { *(.bootscript) }
|
||||
|
||||
. = ALIGN(4);
|
||||
.got : { *(.got) }
|
||||
|
||||
__u_boot_cmd_start = .;
|
||||
.u_boot_cmd : { *(.u_boot_cmd) }
|
||||
__u_boot_cmd_end = .;
|
||||
|
||||
. = ALIGN(4);
|
||||
__bss_start = .;
|
||||
.bss : { *(.bss) }
|
||||
. = ALIGN(4);
|
||||
_end = .;
|
||||
|
||||
/* NOBITS section to contain the MMU page table */
|
||||
. = ALIGN(0x4000);
|
||||
.mmu_table . (COPY) :
|
||||
{
|
||||
__mmu_table_start = .;
|
||||
. = . + 16K; /* ARM page table is always 16K */
|
||||
}
|
||||
|
||||
. = 0x83300000;
|
||||
/* NOBITS section to contain the FDT */
|
||||
.fdt . (COPY) :
|
||||
{
|
||||
__fdt_start = .;
|
||||
. = . + 128K; /* Max FDT len is 128K */
|
||||
__fdt_end = .;
|
||||
}
|
||||
|
||||
. = ALIGN(128);
|
||||
/* NOBITS section to contain the kernel */
|
||||
.kern . (COPY) :
|
||||
{
|
||||
. = . + 16K; /* For the decompressor page table */
|
||||
__kern_start = .;
|
||||
. = . + 4M;
|
||||
__kern_end = .;
|
||||
}
|
||||
|
||||
. = 0x82000000;
|
||||
.diagsys . (COPY) :
|
||||
{
|
||||
__diagsys_start = .;
|
||||
. = . + 1M;
|
||||
__diagsys_end = .;
|
||||
}
|
||||
|
||||
. = ALIGN(4);
|
||||
|
||||
. = 0x83000000;
|
||||
.framebuffer . (COPY) :
|
||||
{
|
||||
__framebuffer_start = .;
|
||||
. = . + 3M;
|
||||
__framebuffer_end = .;
|
||||
}
|
||||
|
||||
. = ALIGN(4);
|
||||
}
|
||||
|
||||
1877
common/cmd_bootm.c
1877
common/cmd_bootm.c
File diff suppressed because it is too large
Load Diff
@ -128,12 +128,6 @@ typedef enum {
|
||||
|
||||
#define SDP_SDRC_MR_0_DDR 0x00000032
|
||||
|
||||
#ifdef CONFIG_STRASBOURG
|
||||
#define SDP_SDRC_EMR2_0_DDR 0x00000020
|
||||
#else
|
||||
#define SDP_SDRC_EMR2_0_DDR 0x00000000
|
||||
#endif
|
||||
|
||||
/* optimized timings good for current shipping parts */
|
||||
#define SDP_3430_SDRC_RFR_CTRL_100MHz 0x0002da01
|
||||
#define SDP_3430_SDRC_RFR_CTRL_133MHz 0x0003de01 /* 7.8us/7.5ns - 50=0x3de */
|
||||
@ -261,7 +255,7 @@ typedef enum {
|
||||
#elif defined(CONFIG_3430ZOOM2_512M) ||\
|
||||
defined(CONFIG_3630ZOOM3) || defined(CONFIG_3630SDP)\
|
||||
|| defined(CONFIG_3630SDP_1G) || defined(CONFIG_3630ZOOM3_1G) \
|
||||
|| defined(CONFIG_3730OVERO) || (defined(CONFIG_STRASBOURG) && defined(DDR_MT46H64M32))
|
||||
|| defined(CONFIG_3730OVERO)
|
||||
|
||||
/* Hynix part of 3430 Zoom2 (166MHz optimized) 6.02ns
|
||||
* ACTIMA
|
||||
|
||||
27
include/configs/rennes_b1-debug.h
Normal file
27
include/configs/rennes_b1-debug.h
Normal file
@ -0,0 +1,27 @@
|
||||
/*
|
||||
* DEBUG Configuration for Strasbourg
|
||||
*
|
||||
* Copyright (C) 2010 TomTom International B.V.
|
||||
*
|
||||
************************************************************************
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* as published by the Free Software Foundation; either version 2
|
||||
* of the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
|
||||
* 02110-1301, USA.
|
||||
************************************************************************
|
||||
*/
|
||||
|
||||
#define CONFIG_DEBUG_BUILD
|
||||
#include "rennes_b1.h"
|
||||
|
||||
/* EOF */
|
||||
42
include/configs/rennes_b1.h
Normal file
42
include/configs/rennes_b1.h
Normal file
@ -0,0 +1,42 @@
|
||||
/*
|
||||
* U-Boot configuration for Strasbourg
|
||||
*
|
||||
* Copyright (C) 2010 TomTom International B.V.
|
||||
*
|
||||
************************************************************************
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* as published by the Free Software Foundation; either version 2
|
||||
* of the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
|
||||
* 02110-1301, USA.
|
||||
************************************************************************
|
||||
*/
|
||||
|
||||
#ifndef __BOARD_CONFIG_H
|
||||
#define __BOARD_CONFIG_H
|
||||
|
||||
#define __VARIANT_RENNES_B1
|
||||
//#define CFG_NS16550_COM1 OMAP34XX_UART1
|
||||
//#define CFG_NS16550_COM2 OMAP34XX_UART2
|
||||
#define CFG_NS16550_COM3 OMAP34XX_UART3
|
||||
|
||||
/* select serial console configuration */
|
||||
#define CONFIG_SERIAL3 3
|
||||
#define CONFIG_CONS_INDEX 3
|
||||
|
||||
/* DDR chip */
|
||||
#define DDR_MT46H128M16
|
||||
|
||||
#include "strasbourg_core.h"
|
||||
|
||||
#endif /* __BOARD_CONFIG_H */
|
||||
|
||||
27
include/configs/stuttgart_b1-debug.h
Normal file
27
include/configs/stuttgart_b1-debug.h
Normal file
@ -0,0 +1,27 @@
|
||||
/*
|
||||
* DEBUG Configuration for Stuttgart
|
||||
*
|
||||
* Copyright (C) 2012 TomTom International B.V.
|
||||
*
|
||||
************************************************************************
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* as published by the Free Software Foundation; either version 2
|
||||
* of the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
|
||||
* 02110-1301, USA.
|
||||
************************************************************************
|
||||
*/
|
||||
|
||||
#define CONFIG_DEBUG_BUILD
|
||||
#include "stuttgart_b1.h"
|
||||
|
||||
/* EOF */
|
||||
43
include/configs/stuttgart_b1.h
Normal file
43
include/configs/stuttgart_b1.h
Normal file
@ -0,0 +1,43 @@
|
||||
/*
|
||||
* U-Boot configuration for Stuttgart
|
||||
*
|
||||
* Copyright (C) 2012 TomTom International B.V.
|
||||
*
|
||||
************************************************************************
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* as published by the Free Software Foundation; either version 2
|
||||
* of the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
|
||||
* 02110-1301, USA.
|
||||
************************************************************************
|
||||
*/
|
||||
|
||||
#ifndef __BOARD_CONFIG_H
|
||||
#define __BOARD_CONFIG_H
|
||||
|
||||
#define __VARIANT_STUTTGART_B1
|
||||
#define __VARIANT_RENNES_B1
|
||||
//#define CFG_NS16550_COM1 OMAP34XX_UART1
|
||||
//#define CFG_NS16550_COM2 OMAP34XX_UART2
|
||||
#define CFG_NS16550_COM3 OMAP34XX_UART3
|
||||
|
||||
/* select serial console configuration */
|
||||
#define CONFIG_SERIAL3 3
|
||||
#define CONFIG_CONS_INDEX 3
|
||||
|
||||
/* DDR chip */
|
||||
#define DDR_MT46H128M16
|
||||
|
||||
#include "strasbourg_core.h"
|
||||
|
||||
#endif /* __BOARD_CONFIG_H */
|
||||
|
||||
191
include/linux/padconfig_common.h
Normal file
191
include/linux/padconfig_common.h
Normal file
@ -0,0 +1,191 @@
|
||||
/*
|
||||
* Copyright (C) 2009 TomTom BV <http://www.tomtom.com/>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef PADCONFIG_COMMON_H
|
||||
#define PADCONFIG_COMMON_H
|
||||
|
||||
/*
|
||||
* INFO: this file was created to clean up the mux config settings which were
|
||||
* at the time of the creation of this file in the x-loader, u-boot and kernel.
|
||||
* All modules initialized all PADCONFIG. This ofcourse is overdone, but besides
|
||||
* being initialized three times, all the settings were defined three times,
|
||||
* using different defines each time. This modules first step will be to make
|
||||
* one single table with all the PADCONFIG configuration which can be used in
|
||||
* all three modules.
|
||||
*/
|
||||
|
||||
/* To keep the names short: PC = PADCONF */
|
||||
|
||||
/* First the defines which allow the table to be mapped to the header files */
|
||||
/* from TI. These defines have to be copied into the module using this table */
|
||||
/* So all following defines are between #if 0 and #endif statement but should */
|
||||
/* not be removed. */
|
||||
|
||||
/********************************************/
|
||||
/************* SAMPLE DEFINES ***************/
|
||||
/********************************************/
|
||||
#if 0
|
||||
/*********** BIT DEFINES, never used, just for info, but could be used :-) ****/
|
||||
#define PC_MODE0 (0 << 0)
|
||||
#define PC_MODE1 (1 << 0)
|
||||
#define PC_MODE2 (2 << 0)
|
||||
#define PC_MODE3 (3 << 0)
|
||||
#define PC_MODE4 (4 << 0)
|
||||
#define PC_MODE5 (5 << 0)
|
||||
#define PC_MODE6 (6 << 0)
|
||||
#define PC_MODE7 (7 << 0)
|
||||
|
||||
#define PC_INPUT (1 << 8)
|
||||
#define PC_OUTPUT (0 << 8)
|
||||
|
||||
#define PC_PULL_ENA (1 << 3)
|
||||
#define PC_PULL_DIS (0 << 3)
|
||||
|
||||
#define PC_PULL_UP (1 << 4)
|
||||
#define PC_PULL_DOWN (0 << 4)
|
||||
/********************************************/
|
||||
/*********** END SAMPLE DEFINES *************/
|
||||
/********************************************/
|
||||
#endif // 0
|
||||
|
||||
/*********** BOOTLOADER/U-BOOT, used in case of bootloader or u-boot **********/
|
||||
#ifdef BOOTLOADER_UBOOT_PADCONFIG
|
||||
|
||||
/* Brilliantly enough the naming of the PADs are different between the */
|
||||
/* x-loader and kernel. So we use defines to overcome the problem */
|
||||
|
||||
#define CONTROL_PADCONF_SYS_NIRQ CONTROL_PADCONF_SYS_nIRQ
|
||||
#define CONTROL_PADCONF_SYS_NRESWARM 0x0A08
|
||||
#define CONTROL_PADCONF_MCBSP3_CLKX CONTROL_PADCONF_McBSP3_CLKX
|
||||
#define CONTROL_PADCONF_MCBSP3_DR CONTROL_PADCONF_McBSP3_DR
|
||||
#define CONTROL_PADCONF_MCBSP3_DX CONTROL_PADCONF_McBSP3_DX
|
||||
#define CONTROL_PADCONF_MCBSP3_FSX CONTROL_PADCONF_McBSP3_FSX
|
||||
#define CONTROL_PADCONF_MCBSP4_FSX CONTROL_PADCONF_McBSP4_FSX
|
||||
#define CONTROL_PADCONF_MCBSP1_CLKX CONTROL_PADCONF_McBSP1_CLKX
|
||||
#define CONTROL_PADCONF_MCBSP1_DR CONTROL_PADCONF_McBSP1_DR
|
||||
#define CONTROL_PADCONF_MCBSP1_DX CONTROL_PADCONF_McBSP1_DX
|
||||
#define CONTROL_PADCONF_MCBSP1_FSX CONTROL_PADCONF_McBSP1_FSX
|
||||
#define CONTROL_PADCONF_MCBSP2_CLKX CONTROL_PADCONF_McBSP2_CLKX
|
||||
#define CONTROL_PADCONF_MCBSP2_DR CONTROL_PADCONF_McBSP2_DR
|
||||
#define CONTROL_PADCONF_MCBSP2_DX CONTROL_PADCONF_McBSP2_DX
|
||||
#define CONTROL_PADCONF_MCBSP2_FSX CONTROL_PADCONF_McBSP2_FSX
|
||||
#define CONTROL_PADCONF_MCSPI1_CLK CONTROL_PADCONF_McSPI1_CLK
|
||||
#define CONTROL_PADCONF_MCSPI1_SIMO CONTROL_PADCONF_McSPI1_SIMO
|
||||
#define CONTROL_PADCONF_MCSPI1_SOMI CONTROL_PADCONF_McSPI1_SOMI
|
||||
#define CONTROL_PADCONF_MCSPI1_CS0 CONTROL_PADCONF_McSPI1_CS0
|
||||
#define CONTROL_PADCONF_MCSPI1_CS1 CONTROL_PADCONF_McSPI1_CS1
|
||||
#define CONTROL_PADCONF_MCSPI1_CS2 CONTROL_PADCONF_McSPI1_CS2
|
||||
#define CONTROL_PADCONF_MCSPI1_CS3 CONTROL_PADCONF_McSPI1_CS3
|
||||
#define CONTROL_PADCONF_MCSPI2_CLK CONTROL_PADCONF_McSPI2_CLK
|
||||
#define CONTROL_PADCONF_MCSPI2_SIMO CONTROL_PADCONF_McSPI2_SIMO
|
||||
#define CONTROL_PADCONF_MCSPI2_SOMI CONTROL_PADCONF_McSPI2_SOMI
|
||||
#define CONTROL_PADCONF_MCSPI2_CS0 CONTROL_PADCONF_McSPI2_CS0
|
||||
#define CONTROL_PADCONF_MCSPI2_CS1 CONTROL_PADCONF_McSPI2_CS1
|
||||
#define CONTROL_PADCONF_SDMMC1_CLK CONTROL_PADCONF_MMC1_CLK
|
||||
#define CONTROL_PADCONF_SDMMC1_CMD CONTROL_PADCONF_MMC1_CMD
|
||||
#define CONTROL_PADCONF_SDMMC1_DAT0 CONTROL_PADCONF_MMC1_DAT0
|
||||
#define CONTROL_PADCONF_SDMMC1_DAT1 CONTROL_PADCONF_MMC1_DAT1
|
||||
#define CONTROL_PADCONF_SDMMC1_DAT2 CONTROL_PADCONF_MMC1_DAT2
|
||||
#define CONTROL_PADCONF_SDMMC1_DAT3 CONTROL_PADCONF_MMC1_DAT3
|
||||
#define CONTROL_PADCONF_SDMMC1_DAT6 CONTROL_PADCONF_MMC1_DAT6
|
||||
#define CONTROL_PADCONF_SDMMC2_CLK CONTROL_PADCONF_MMC2_CLK
|
||||
#define CONTROL_PADCONF_SDMMC2_CMD CONTROL_PADCONF_MMC2_CMD
|
||||
#define CONTROL_PADCONF_SDMMC2_DAT0 CONTROL_PADCONF_MMC2_DAT0
|
||||
#define CONTROL_PADCONF_SDMMC2_DAT1 CONTROL_PADCONF_MMC2_DAT1
|
||||
#define CONTROL_PADCONF_SDMMC2_DAT2 CONTROL_PADCONF_MMC2_DAT2
|
||||
#define CONTROL_PADCONF_SDMMC2_DAT3 CONTROL_PADCONF_MMC2_DAT3
|
||||
#define CONTROL_PADCONF_SDMMC2_DAT4 CONTROL_PADCONF_MMC2_DAT4
|
||||
#define CONTROL_PADCONF_SDMMC2_DAT5 CONTROL_PADCONF_MMC2_DAT5
|
||||
#define CONTROL_PADCONF_SDMMC2_DAT6 CONTROL_PADCONF_MMC2_DAT6
|
||||
#define CONTROL_PADCONF_SDMMC2_DAT7 CONTROL_PADCONF_MMC2_DAT7
|
||||
#define CONTROL_PADCONF_GPMC_NCS0 CONTROL_PADCONF_GPMC_nCS0
|
||||
#define CONTROL_PADCONF_GPMC_NCS6 CONTROL_PADCONF_GPMC_nCS6
|
||||
#define CONTROL_PADCONF_GPMC_NCS7 CONTROL_PADCONF_GPMC_nCS7
|
||||
#define CONTROL_PADCONF_GPMC_NWE CONTROL_PADCONF_GPMC_nWE
|
||||
#define CONTROL_PADCONF_GPMC_NOE CONTROL_PADCONF_GPMC_nOE
|
||||
#define CONTROL_PADCONF_GPMC_NADV_ALE CONTROL_PADCONF_GPMC_nADV_ALE
|
||||
#define CONTROL_PADCONF_GPMC_NWP CONTROL_PADCONF_GPMC_nWP
|
||||
#define CONTROL_PADCONF_MCBSP4_CLKX CONTROL_PADCONF_McBSP4_CLKX
|
||||
#define CONTROL_PADCONF_MCBSP4_DR CONTROL_PADCONF_McBSP4_DR
|
||||
#define CONTROL_PADCONF_MCBSP4_DX CONTROL_PADCONF_McBSP4_DX
|
||||
#define CONTROL_PADCONF_MCBSP1_CLKR CONTROL_PADCONF_McBSP1_CLKR
|
||||
#define CONTROL_PADCONF_MCBSP1_FSR CONTROL_PADCONF_McBSP1_FSR
|
||||
#define CONTROL_PADCONF_MCBSP_CLKS CONTROL_PADCONF_McBSP_CLKS
|
||||
#define CONTROL_PADCONF_SDMMC1_DAT4 CONTROL_PADCONF_MMC1_DAT4
|
||||
#define CONTROL_PADCONF_SDMMC1_DAT5 CONTROL_PADCONF_MMC1_DAT5
|
||||
#define CONTROL_PADCONF_SDMMC1_DAT7 CONTROL_PADCONF_MMC1_DAT7
|
||||
#define CONTROL_PADCONF_GPMC_NCS1 CONTROL_PADCONF_GPMC_nCS1
|
||||
#define CONTROL_PADCONF_GPMC_NCS2 CONTROL_PADCONF_GPMC_nCS2
|
||||
#define CONTROL_PADCONF_GPMC_NCS3 CONTROL_PADCONF_GPMC_nCS3
|
||||
#define CONTROL_PADCONF_GPMC_NCS4 CONTROL_PADCONF_GPMC_nCS4
|
||||
#define CONTROL_PADCONF_GPMC_NCS5 CONTROL_PADCONF_GPMC_nCS5
|
||||
#define CONTROL_PADCONF_GPMC_NBE0_CLE CONTROL_PADCONF_GPMC_nBE0_CLE
|
||||
#define CONTROL_PADCONF_GPMC_NBE1 CONTROL_PADCONF_GPMC_nBE1
|
||||
|
||||
#define PC_DEFINE MUX_VAL
|
||||
#define PC_MODE0 M0
|
||||
#define PC_MODE1 M1
|
||||
#define PC_MODE2 M2
|
||||
#define PC_MODE3 M3
|
||||
#define PC_MODE4 M4
|
||||
#define PC_MODE5 M5
|
||||
#define PC_MODE6 M6
|
||||
#define PC_MODE7 M7
|
||||
#define PC_INPUT IEN
|
||||
#define PC_OUTPUT IDIS
|
||||
#define PC_PULL_ENA EN
|
||||
#define PC_PULL_DIS DIS
|
||||
#define PC_PULL_UP PTU
|
||||
#define PC_PULL_DOWN PTD
|
||||
#define PC_WAKEUP_EN (1 << 14)
|
||||
#define PC_OFF_EN (1 << 9)
|
||||
#define PC_OFFOUT_EN (1 << 10)
|
||||
#define PC_OFF_PULL_EN (1 << 12)
|
||||
#define PC_OFF_PULL_UP (1 << 13)
|
||||
#define PC_OFF_OUT_LOW (PC_OFF_EN)
|
||||
#define PC_OFF_IN_NOPULL (PC_OFF_EN | PC_OFFOUT_EN)
|
||||
#define PC_OFF_IN_PULLUP (PC_OFF_IN_NOPULL | PC_OFF_PULL_EN | PC_OFF_PULL_UP)
|
||||
#define PC_OFF_IN_PULLDOWN (PC_OFF_IN_NOPULL | PC_OFF_PULL_EN)
|
||||
|
||||
#endif // BOOTLOADER_UBOOT_PADCONFIG
|
||||
|
||||
/*********** KERNEL, used in case of kernel build, board-santiago.c ***********/
|
||||
#ifdef KERNEL_PADCONFIG
|
||||
|
||||
#define PC_DEFINE(x,y) OMAP3_MUX(x,y),
|
||||
#define CP(x) x
|
||||
#define PC_MODE0 OMAP_MUX_MODE0
|
||||
#define PC_MODE1 OMAP_MUX_MODE1
|
||||
#define PC_MODE2 OMAP_MUX_MODE2
|
||||
#define PC_MODE3 OMAP_MUX_MODE3
|
||||
#define PC_MODE4 OMAP_MUX_MODE4
|
||||
#define PC_MODE5 OMAP_MUX_MODE5
|
||||
#define PC_MODE6 OMAP_MUX_MODE6
|
||||
#define PC_MODE7 OMAP_MUX_MODE7
|
||||
#define PC_INPUT OMAP_PIN_INPUT
|
||||
#define PC_OUTPUT OMAP_PIN_OUTPUT
|
||||
#define PC_PULL_ENA OMAP_PULL_ENA
|
||||
#define PC_PULL_DIS (0 << 3)
|
||||
#define PC_PULL_UP OMAP_PULL_UP
|
||||
#define PC_PULL_DOWN (0 << 4)
|
||||
#define PC_WAKEUP_EN OMAP_WAKEUP_EN
|
||||
#define PC_OFF_EN OMAP_OFF_EN
|
||||
#define PC_OFFOUT_EN OMAP_OFFOUT_EN
|
||||
#define PC_OFFOUT_VAL OMAP_OFFOUT_VAL
|
||||
#define PC_OFF_PULL_EN OMAP_OFF_PULL_EN
|
||||
#define PC_OFF_PULL_UP OMAP_OFF_PULL_UP
|
||||
#define PC_OFF_OUT_LOW OMAP_PIN_OFF_OUTPUT_LOW
|
||||
#define PC_OFF_OUT_HIGH OMAP_PIN_OFF_OUTPUT_HIGH
|
||||
#define PC_OFF_IN_NOPULL OMAP_PIN_OFF_INPUT_NOPULL
|
||||
#define PC_OFF_IN_PULLUP OMAP_PIN_OFF_INPUT_PULLUP
|
||||
#define PC_OFF_IN_PULLDOWN OMAP_PIN_OFF_INPUT_PULLDOWN
|
||||
|
||||
#endif // KERNEL_PADCONFIG
|
||||
|
||||
#endif
|
||||
327
include/linux/padconfig_monopoli.h
Normal file
327
include/linux/padconfig_monopoli.h
Normal file
@ -0,0 +1,327 @@
|
||||
/*
|
||||
* Copyright (C) 2009 TomTom BV <http://www.tomtom.com/>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef PADCONFIG_SANTIAGO_H
|
||||
#define PADCONFIG_SANTIAGO_H
|
||||
|
||||
#include "padconfig_common.h"
|
||||
|
||||
/*******************************/
|
||||
/*********** TABLES ************/
|
||||
/*******************************/
|
||||
|
||||
|
||||
#define PADCONFIG_SETTINGS_XLOADER \
|
||||
/*SDRC*/ \
|
||||
PC_DEFINE(CP(SDRC_D0), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /*SDRC_D0*/ \
|
||||
PC_DEFINE(CP(SDRC_D1), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /*SDRC_D1*/ \
|
||||
PC_DEFINE(CP(SDRC_D2), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /*SDRC_D2*/ \
|
||||
PC_DEFINE(CP(SDRC_D3), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /*SDRC_D3*/ \
|
||||
PC_DEFINE(CP(SDRC_D4), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /*SDRC_D4*/ \
|
||||
PC_DEFINE(CP(SDRC_D5), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /*SDRC_D5*/ \
|
||||
PC_DEFINE(CP(SDRC_D6), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /*SDRC_D6*/ \
|
||||
PC_DEFINE(CP(SDRC_D7), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /*SDRC_D7*/ \
|
||||
PC_DEFINE(CP(SDRC_D8), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /*SDRC_D8*/ \
|
||||
PC_DEFINE(CP(SDRC_D9), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /*SDRC_D9*/ \
|
||||
PC_DEFINE(CP(SDRC_D10), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /*SDRC_D10*/ \
|
||||
PC_DEFINE(CP(SDRC_D11), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /*SDRC_D11*/ \
|
||||
PC_DEFINE(CP(SDRC_D12), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /*SDRC_D12*/ \
|
||||
PC_DEFINE(CP(SDRC_D13), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /*SDRC_D13*/ \
|
||||
PC_DEFINE(CP(SDRC_D14), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /*SDRC_D14*/ \
|
||||
PC_DEFINE(CP(SDRC_D15), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /*SDRC_D15*/ \
|
||||
PC_DEFINE(CP(SDRC_D16), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /*SDRC_D16*/ \
|
||||
PC_DEFINE(CP(SDRC_D17), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /*SDRC_D17*/ \
|
||||
PC_DEFINE(CP(SDRC_D18), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /*SDRC_D18*/ \
|
||||
PC_DEFINE(CP(SDRC_D19), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /*SDRC_D19*/ \
|
||||
PC_DEFINE(CP(SDRC_D20), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /*SDRC_D20*/ \
|
||||
PC_DEFINE(CP(SDRC_D21), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /*SDRC_D21*/ \
|
||||
PC_DEFINE(CP(SDRC_D22), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /*SDRC_D22*/ \
|
||||
PC_DEFINE(CP(SDRC_D23), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /*SDRC_D23*/ \
|
||||
PC_DEFINE(CP(SDRC_D24), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /*SDRC_D24*/ \
|
||||
PC_DEFINE(CP(SDRC_D25), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /*SDRC_D25*/ \
|
||||
PC_DEFINE(CP(SDRC_D26), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /*SDRC_D26*/ \
|
||||
PC_DEFINE(CP(SDRC_D27), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /*SDRC_D27*/ \
|
||||
PC_DEFINE(CP(SDRC_D28), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /*SDRC_D28*/ \
|
||||
PC_DEFINE(CP(SDRC_D29), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /*SDRC_D29*/ \
|
||||
PC_DEFINE(CP(SDRC_D30), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /*SDRC_D30*/ \
|
||||
PC_DEFINE(CP(SDRC_D31), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /*SDRC_D31*/ \
|
||||
PC_DEFINE(CP(SDRC_CLK), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /*SDRC_CLK*/ \
|
||||
PC_DEFINE(CP(SDRC_DQS0), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /*SDRC_DQS0*/ \
|
||||
PC_DEFINE(CP(SDRC_DQS1), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /*SDRC_DQS1*/ \
|
||||
PC_DEFINE(CP(SDRC_DQS2), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /*SDRC_DQS2*/ \
|
||||
PC_DEFINE(CP(SDRC_DQS3), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /*SDRC_DQS3*/ \
|
||||
\
|
||||
/* MMC lines */ \
|
||||
PC_DEFINE(CP(SDMMC1_CLK), PC_INPUT | PC_PULL_ENA | PC_PULL_UP | PC_MODE0) \
|
||||
PC_DEFINE(CP(SDMMC1_CMD), PC_INPUT | PC_PULL_ENA | PC_PULL_UP | PC_MODE0) \
|
||||
PC_DEFINE(CP(SDMMC1_DAT0), PC_INPUT | PC_PULL_ENA | PC_PULL_UP | PC_MODE0) \
|
||||
PC_DEFINE(CP(SDMMC1_DAT1), PC_INPUT | PC_PULL_ENA | PC_PULL_UP | PC_MODE0) \
|
||||
PC_DEFINE(CP(SDMMC1_DAT2), PC_INPUT | PC_PULL_ENA | PC_PULL_UP | PC_MODE0) \
|
||||
PC_DEFINE(CP(SDMMC1_DAT3), PC_INPUT | PC_PULL_ENA | PC_PULL_UP | PC_MODE0) \
|
||||
PC_DEFINE(CP(SDMMC2_CLK), PC_INPUT | PC_PULL_ENA | PC_PULL_UP | PC_MODE0) \
|
||||
PC_DEFINE(CP(SDMMC2_CMD), PC_INPUT | PC_PULL_ENA | PC_PULL_UP | PC_MODE0) \
|
||||
PC_DEFINE(CP(SDMMC2_DAT0), PC_INPUT | PC_PULL_ENA | PC_PULL_UP | PC_MODE0) \
|
||||
PC_DEFINE(CP(SDMMC2_DAT1), PC_INPUT | PC_PULL_ENA | PC_PULL_UP | PC_MODE0) \
|
||||
PC_DEFINE(CP(SDMMC2_DAT2), PC_INPUT | PC_PULL_ENA | PC_PULL_UP | PC_MODE0) \
|
||||
PC_DEFINE(CP(SDMMC2_DAT3), PC_INPUT | PC_PULL_ENA | PC_PULL_UP | PC_MODE0) \
|
||||
PC_DEFINE(CP(SDMMC2_DAT4), PC_INPUT | PC_PULL_ENA | PC_PULL_UP | PC_MODE0) \
|
||||
PC_DEFINE(CP(SDMMC2_DAT5), PC_INPUT | PC_PULL_ENA | PC_PULL_UP | PC_MODE0) \
|
||||
PC_DEFINE(CP(SDMMC2_DAT6), PC_INPUT | PC_PULL_ENA | PC_PULL_UP | PC_MODE0) \
|
||||
PC_DEFINE(CP(SDMMC2_DAT7), PC_INPUT | PC_PULL_ENA | PC_PULL_UP | PC_MODE0) \
|
||||
\
|
||||
/* UART4 lines */ \
|
||||
PC_DEFINE(CP(GPMC_WAIT2), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE2) /* DEBUG_TX */ \
|
||||
PC_DEFINE(CP(GPMC_WAIT3), PC_INPUT | PC_PULL_ENA | PC_PULL_UP | PC_MODE2) /* DEBUG_RX */ \
|
||||
\
|
||||
/* GPIO lines */ \
|
||||
PC_DEFINE(CP(ETK_D13), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE4) /* 27: AUX_MOVI */ \
|
||||
PC_DEFINE(CP(ETK_D14), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE4) /* 28: AUX_SD */ \
|
||||
|
||||
#define PADCONFIG_SETTINGS_UBOOT \
|
||||
|
||||
|
||||
|
||||
#define PADCONFIG_SETTINGS_KERNEL \
|
||||
/* GPIO lines */ \
|
||||
PC_DEFINE(CP(GPIO126), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE4) /* 126: GSM_SYS_RST */ \
|
||||
PC_DEFINE(CP(GPIO127), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE4) /* 127: GSM_SYS_EN */ \
|
||||
\
|
||||
/* UART1 lines */ \
|
||||
PC_DEFINE(CP(UART1_TX), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0 | OMAP_PIN_OFF_OUTPUT_LOW) /* uP_UART1_TX */ \
|
||||
PC_DEFINE(CP(UART1_RTS), PC_INPUT | PC_PULL_ENA | PC_PULL_UP | PC_MODE0 | OMAP_PIN_OFF_OUTPUT_LOW) /* uP_UART1_RTS */ \
|
||||
PC_DEFINE(CP(UART1_CTS), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0 | OMAP_PIN_OFF_OUTPUT_LOW) /* uP_UART1_CTS */ \
|
||||
PC_DEFINE(CP(UART1_RX), PC_INPUT | PC_PULL_ENA | PC_PULL_UP | PC_MODE0 | OMAP_PIN_OFF_OUTPUT_LOW) /* uP_UART1_RX */ \
|
||||
\
|
||||
/* UART2 lines */ \
|
||||
PC_DEFINE(CP(UART2_CTS), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0 | OMAP_PIN_OFF_OUTPUT_HIGH) /* uP_UART2_CTS */ \
|
||||
PC_DEFINE(CP(UART2_RTS), PC_INPUT | PC_PULL_ENA | PC_PULL_UP | PC_MODE0 | OMAP_PIN_OFF_OUTPUT_HIGH) /* uP_UART2_RTS */ \
|
||||
PC_DEFINE(CP(UART2_TX), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0 | OMAP_PIN_OFF_OUTPUT_HIGH) /* uP_UART2_TX */ \
|
||||
PC_DEFINE(CP(UART2_RX), PC_INPUT | PC_PULL_ENA | PC_PULL_UP | PC_MODE0 | OMAP_PIN_OFF_OUTPUT_HIGH) /* uP_UART2_RX */ \
|
||||
\
|
||||
/* UART3 lines */ \
|
||||
PC_DEFINE(CP(UART3_CTS_RCTX), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0 | OMAP_PIN_OFF_OUTPUT_LOW) /* uP_UART3_CTS */ \
|
||||
PC_DEFINE(CP(UART3_RTS_SD), PC_INPUT | PC_PULL_ENA | PC_PULL_UP | PC_MODE0 | OMAP_PIN_OFF_OUTPUT_LOW) /* uP_UART3_RTS */ \
|
||||
PC_DEFINE(CP(UART3_RX_IRRX), PC_INPUT | PC_PULL_ENA | PC_PULL_UP | PC_MODE0 | OMAP_PIN_OFF_OUTPUT_LOW) /* uP_UART3_RX */ \
|
||||
PC_DEFINE(CP(UART3_TX_IRTX), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0 | OMAP_PIN_OFF_OUTPUT_LOW) /* uP_UART3_TX */ \
|
||||
\
|
||||
/* UART4 lines */ \
|
||||
PC_DEFINE(CP(GPMC_WAIT2), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE2 | OMAP_PIN_OFF_OUTPUT_LOW) /* DEBUG_TX */ \
|
||||
PC_DEFINE(CP(GPMC_WAIT3), PC_INPUT | PC_PULL_ENA | PC_PULL_UP | PC_MODE2 | OMAP_PIN_OFF_OUTPUT_LOW) /* DEBUG_RX */ \
|
||||
\
|
||||
/* PCM BT lines */ \
|
||||
PC_DEFINE(CP(MCBSP1_CLKX), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0 | OMAP_PIN_OFF_OUTPUT_LOW) /* BT_PCM_CLK */ \
|
||||
PC_DEFINE(CP(MCBSP1_DR), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0 | OMAP_PIN_OFF_OUTPUT_LOW) /* BT_PCM_OUT */ \
|
||||
PC_DEFINE(CP(MCBSP1_DX), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0 | OMAP_PIN_OFF_OUTPUT_LOW) /* BT_PCM_IN */ \
|
||||
PC_DEFINE(CP(MCBSP1_FSX), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0 | OMAP_PIN_OFF_OUTPUT_LOW) /* BT_PCM_SYNC */ \
|
||||
\
|
||||
/* PCM PMIC lines */ \
|
||||
PC_DEFINE(CP(MCBSP3_CLKX), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0 | OMAP_PIN_OFF_OUTPUT_LOW) /* PCM_VDX */ \
|
||||
PC_DEFINE(CP(MCBSP3_DR), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0 | OMAP_PIN_OFF_OUTPUT_LOW) /* PCM_VFS */ \
|
||||
PC_DEFINE(CP(MCBSP3_DX), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0 | OMAP_PIN_OFF_OUTPUT_LOW) /* PCM_VCK */ \
|
||||
PC_DEFINE(CP(MCBSP3_FSX), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0 | OMAP_PIN_OFF_OUTPUT_LOW) /* PCM_VDR */ \
|
||||
\
|
||||
/* PMIC I2S lines */ \
|
||||
PC_DEFINE(CP(MCBSP2_CLKX), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0 | OMAP_PIN_OFF_OUTPUT_LOW) /* MCBSP2_CLK */ \
|
||||
PC_DEFINE(CP(MCBSP2_DR), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0 | OMAP_PIN_OFF_OUTPUT_LOW) /* MCBSP2_DR */ \
|
||||
PC_DEFINE(CP(MCBSP2_DX), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0 | OMAP_PIN_OFF_OUTPUT_LOW) /* MCBSP2_DX */ \
|
||||
PC_DEFINE(CP(MCBSP2_FSX), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0 | OMAP_PIN_OFF_OUTPUT_LOW) /* MCBSP2_FSX */ \
|
||||
\
|
||||
/* MCSPI1 lines */ \
|
||||
PC_DEFINE(CP(MCSPI1_CLK), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0 | OMAP_PIN_OFF_OUTPUT_LOW) /* DR_SCLK */ \
|
||||
PC_DEFINE(CP(MCSPI1_SIMO), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0 | OMAP_PIN_OFF_OUTPUT_LOW) /* DR_SDI */ \
|
||||
PC_DEFINE(CP(MCSPI1_SOMI), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0 | OMAP_PIN_OFF_OUTPUT_LOW) /* DR_SDO */ \
|
||||
PC_DEFINE(CP(MCSPI1_CS0), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0 | OMAP_PIN_OFF_OUTPUT_LOW) /* ACC_CS0 */ \
|
||||
PC_DEFINE(CP(MCSPI1_CS1), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0 | OMAP_PIN_OFF_OUTPUT_LOW) /* TP196 */ \
|
||||
PC_DEFINE(CP(MCSPI1_CS2), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0 | OMAP_PIN_OFF_OUTPUT_LOW) /* BARO_Csn */ \
|
||||
PC_DEFINE(CP(MCSPI1_CS3), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE7 | OMAP_PIN_OFF_OUTPUT_LOW) /* TP181 */ \
|
||||
\
|
||||
/* MCSPI2 (LCM) lines */ \
|
||||
PC_DEFINE(CP(MCSPI2_CLK), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0 | OMAP_PIN_OFF_OUTPUT_LOW) /* SPI_LCM_CLK */ \
|
||||
PC_DEFINE(CP(MCSPI2_SIMO), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0 | OMAP_PIN_OFF_OUTPUT_LOW) /* SPI_LCM_OUT */ \
|
||||
PC_DEFINE(CP(MCSPI2_SOMI), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE7 | OMAP_PIN_OFF_OUTPUT_LOW) /* TP182 */ \
|
||||
PC_DEFINE(CP(MCSPI2_CS0), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0 | OMAP_PIN_OFF_OUTPUT_LOW) /* SPI_LCM_CS0 */ \
|
||||
PC_DEFINE(CP(MCSPI2_CS1), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE7 | OMAP_PIN_OFF_OUTPUT_LOW) /* TP186 */ \
|
||||
\
|
||||
/* WiFi lines */ \
|
||||
PC_DEFINE(CP(ETK_CLK), PC_INPUT | PC_PULL_ENA | PC_PULL_UP | PC_MODE2 | OMAP_PIN_OFF_OUTPUT_LOW) /* WIFI_CLK */ \
|
||||
PC_DEFINE(CP(ETK_CTL), PC_INPUT | PC_PULL_ENA | PC_PULL_UP | PC_MODE2 | OMAP_PIN_OFF_OUTPUT_LOW) /* WIFI_CMD */ \
|
||||
PC_DEFINE(CP(ETK_D3), PC_INPUT | PC_PULL_ENA | PC_PULL_UP | PC_MODE2 | OMAP_PIN_OFF_OUTPUT_LOW) /* WIFI_DATA3 */ \
|
||||
PC_DEFINE(CP(ETK_D4), PC_INPUT | PC_PULL_ENA | PC_PULL_UP | PC_MODE2 | OMAP_PIN_OFF_OUTPUT_LOW) /* WIFI_DATA0 */ \
|
||||
PC_DEFINE(CP(ETK_D5), PC_INPUT | PC_PULL_ENA | PC_PULL_UP | PC_MODE2 | OMAP_PIN_OFF_OUTPUT_LOW) /* WIFI_DATA1 */ \
|
||||
PC_DEFINE(CP(ETK_D6), PC_INPUT | PC_PULL_ENA | PC_PULL_UP | PC_MODE2 | OMAP_PIN_OFF_OUTPUT_LOW) /* WIFI_DATA2 */ \
|
||||
\
|
||||
/* GPIO lines */ \
|
||||
PC_DEFINE(CP(MCBSP1_CLKR), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE4 | OMAP_PIN_OFF_OUTPUT_LOW) /* 156: nLCD_RESET */ \
|
||||
PC_DEFINE(CP(GPMC_NCS3), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE4 | OMAP_PIN_OFF_OUTPUT_LOW) /* 54: nTP_IRQ */ \
|
||||
PC_DEFINE(CP(GPMC_A6), PC_INPUT | PC_PULL_ENA | PC_PULL_UP | PC_MODE4 | OMAP_PIN_OFF_OUTPUT_LOW) /* 39: nCD_SD_micro */\
|
||||
PC_DEFINE(CP(GPMC_D15), PC_INPUT | PC_PULL_ENA | PC_PULL_UP | PC_MODE4 | OMAP_PIN_OFF_OUTPUT_LOW) /* 51: HPDETECTn */ \
|
||||
PC_DEFINE(CP(GPMC_NCS1), PC_INPUT | PC_PULL_ENA | PC_PULL_UP | PC_MODE4 | OMAP_PIN_OFF_OUTPUT_LOW) /* 52: USB_DETECTn */ \
|
||||
PC_DEFINE(CP(GPMC_A4), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE4 | OMAP_PIN_OFF_OUTPUT_LOW) /* 37: AMP_PWR_EN */ \
|
||||
PC_DEFINE(CP(ETK_D13), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE4 | OMAP_PIN_OFF_OUTPUT_LOW) /* 27: AUX_MOVI */ \
|
||||
PC_DEFINE(CP(ETK_D14), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE4 | OMAP_PIN_OFF_OUTPUT_LOW) /* 28: AUX_SD */ \
|
||||
PC_DEFINE(CP(MCBSP1_FSR), PC_INPUT | PC_PULL_ENA | PC_PULL_UP | PC_MODE4 | OMAP_PIN_OFF_OUTPUT_LOW) /* 157: TSP_RST */ \
|
||||
PC_DEFINE(CP(ETK_D10), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE4 | OMAP_PIN_OFF_OUTPUT_LOW) /* 24: DR_POWER_EN */ \
|
||||
PC_DEFINE(CP(GPMC_NBE0_CLE), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE4 | OMAP_PIN_OFF_OUTPUT_LOW) /* 60: nBT_RST */ \
|
||||
PC_DEFINE(CP(ETK_D15), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE4 | OMAP_PIN_OFF_OUTPUT_LOW) /* 29: WIFI_RSTn */ \
|
||||
PC_DEFINE(CP(ETK_D1), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE4 | OMAP_PIN_OFF_OUTPUT_LOW) /* 15: WIFI_EN */ \
|
||||
|
||||
|
||||
#define PADCONFIG_SETTINGS_COMMON \
|
||||
/* CAM lines */ \
|
||||
PC_DEFINE(CP(CAM_D0), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /* CAM_D0 */ \
|
||||
PC_DEFINE(CP(CAM_D1), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /* CAM_D1 */ \
|
||||
PC_DEFINE(CP(CAM_D2), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /* CAM_D2 */ \
|
||||
PC_DEFINE(CP(CAM_D3), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /* CAM_D3 */ \
|
||||
PC_DEFINE(CP(CAM_D4), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /* CAM_D4 */ \
|
||||
PC_DEFINE(CP(CAM_D5), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /* CAM_D5 */ \
|
||||
PC_DEFINE(CP(CAM_D6), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /* CAM_D6 */ \
|
||||
PC_DEFINE(CP(CAM_D7), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /* CAM_D7 */ \
|
||||
PC_DEFINE(CP(CAM_D8), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /* CAM_D8 */ \
|
||||
PC_DEFINE(CP(CAM_D9), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /* CAM_D9 */ \
|
||||
PC_DEFINE(CP(CAM_XCLKB), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /* h_CAM_XCLKB */ \
|
||||
PC_DEFINE(CP(CAM_PCLK), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /* CAM_PCLK */ \
|
||||
PC_DEFINE(CP(CAM_VS), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /* CAM_VS */ \
|
||||
PC_DEFINE(CP(CAM_HS), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /* CAM_HS */ \
|
||||
PC_DEFINE(CP(CAM_FLD), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE2) /* CAM_nRESET */ \
|
||||
PC_DEFINE(CP(CSI2_DX0), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /* CSI1_DX0 */ \
|
||||
PC_DEFINE(CP(CSI2_DY0), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /* CSI1_DX0 */ \
|
||||
PC_DEFINE(CP(CSI2_DX1), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /* CSI1_DX0 */ \
|
||||
PC_DEFINE(CP(CSI2_DY1), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /* CSI1_DX0 */ \
|
||||
\
|
||||
/* LCD lines */ \
|
||||
PC_DEFINE(CP(DSS_ACBIAS), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /* LCD_DAT_EN */ \
|
||||
PC_DEFINE(CP(DSS_DATA0), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /* LCD_D0 */ \
|
||||
PC_DEFINE(CP(DSS_DATA1), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /* LCD_D1 */ \
|
||||
PC_DEFINE(CP(DSS_DATA2), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /* LCD_D2 */ \
|
||||
PC_DEFINE(CP(DSS_DATA3), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /* LCD_D3 */ \
|
||||
PC_DEFINE(CP(DSS_DATA4), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /* LCD_D4 */ \
|
||||
PC_DEFINE(CP(DSS_DATA5), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /* LCD_D5 */ \
|
||||
PC_DEFINE(CP(DSS_DATA6), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /* LCD_D6 */ \
|
||||
PC_DEFINE(CP(DSS_DATA7), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /* LCD_D7 */ \
|
||||
PC_DEFINE(CP(DSS_DATA8), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /* LCD_D8 */ \
|
||||
PC_DEFINE(CP(DSS_DATA9), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /* LCD_D9 */ \
|
||||
PC_DEFINE(CP(DSS_DATA10), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /* LCD_D10 */ \
|
||||
PC_DEFINE(CP(DSS_DATA11), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /* LCD_D11 */ \
|
||||
PC_DEFINE(CP(DSS_DATA12), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /* LCD_D12 */ \
|
||||
PC_DEFINE(CP(DSS_DATA13), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /* LCD_D13 */ \
|
||||
PC_DEFINE(CP(DSS_DATA14), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /* LCD_D14 */ \
|
||||
PC_DEFINE(CP(DSS_DATA15), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /* LCD_D15 */ \
|
||||
PC_DEFINE(CP(DSS_DATA16), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /* LCD_D16 */ \
|
||||
PC_DEFINE(CP(DSS_DATA17), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /* LCD_D17 */ \
|
||||
PC_DEFINE(CP(DSS_DATA18), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /* LCD_D18 */ \
|
||||
PC_DEFINE(CP(DSS_DATA19), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /* LCD_D19 */ \
|
||||
PC_DEFINE(CP(DSS_DATA20), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /* LCD_D20 */ \
|
||||
PC_DEFINE(CP(DSS_DATA21), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /* LCD_D21 */ \
|
||||
PC_DEFINE(CP(DSS_DATA22), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /* LCD_D22 */ \
|
||||
PC_DEFINE(CP(DSS_DATA23), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /* LCD_D23 */ \
|
||||
PC_DEFINE(CP(DSS_PCLK), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /* LCD_DCLK */ \
|
||||
PC_DEFINE(CP(DSS_HSYNC), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /* LCD_HSYNC */ \
|
||||
PC_DEFINE(CP(DSS_VSYNC), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /* LCD_VSYNC */ \
|
||||
\
|
||||
/* WiFi lines */ \
|
||||
PC_DEFINE(CP(ETK_D9), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE7) \
|
||||
PC_DEFINE(CP(ETK_D10), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE7) \
|
||||
PC_DEFINE(CP(ETK_D11), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE7) \
|
||||
PC_DEFINE(CP(ETK_D12), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE7) \
|
||||
\
|
||||
/* USB0 lines */ \
|
||||
PC_DEFINE(CP(HSUSB0_DATA0), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /* USB0_ULPI_DATA0 */ \
|
||||
PC_DEFINE(CP(HSUSB0_DATA1), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /* USB0_ULPI_DATA1 */ \
|
||||
PC_DEFINE(CP(HSUSB0_DATA2), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /* USB0_ULPI_DATA2 */ \
|
||||
PC_DEFINE(CP(HSUSB0_DATA3), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /* USB0_ULPI_DATA3 */ \
|
||||
PC_DEFINE(CP(HSUSB0_DATA4), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /* USB0_ULPI_DATA4 */ \
|
||||
PC_DEFINE(CP(HSUSB0_DATA5), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /* USB0_ULPI_DATA5 */ \
|
||||
PC_DEFINE(CP(HSUSB0_DATA6), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /* USB0_ULPI_DATA6 */ \
|
||||
PC_DEFINE(CP(HSUSB0_DATA7), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /* USB0_ULPI_DATA7 */ \
|
||||
PC_DEFINE(CP(HSUSB0_CLK), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /* USB0_ULPI_CLK */ \
|
||||
PC_DEFINE(CP(HSUSB0_STP), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /* USB0_ULPI_STP */ \
|
||||
PC_DEFINE(CP(HSUSB0_DIR), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /* USB0_ULPI_DIR */ \
|
||||
PC_DEFINE(CP(HSUSB0_NXT), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /* USB0_ULPI_NXT */ \
|
||||
\
|
||||
/* SYS lines */ \
|
||||
PC_DEFINE(CP(SYS_BOOT0), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /* SYS_BOOT0 */ \
|
||||
PC_DEFINE(CP(SYS_BOOT1), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /* SYS_BOOT1 */ \
|
||||
PC_DEFINE(CP(SYS_BOOT2), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /* SYS_BOOT2 */ \
|
||||
PC_DEFINE(CP(SYS_BOOT3), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /* SYS_BOOT3 */ \
|
||||
PC_DEFINE(CP(SYS_BOOT4), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /* SYS_BOOT4 */ \
|
||||
PC_DEFINE(CP(SYS_BOOT5), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /* SYS_BOOT5 */ \
|
||||
PC_DEFINE(CP(SYS_BOOT6), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /* SYS_BOOT6 */ \
|
||||
PC_DEFINE(CP(SYS_CLKREQ), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /* SYS_CLKREQ */ \
|
||||
PC_DEFINE(CP(SYS_NIRQ), PC_INPUT | PC_PULL_ENA | PC_PULL_UP | PC_MODE0 | PC_WAKEUP_EN) /* SYS_NIRQ */ \
|
||||
PC_DEFINE(CP(SYS_NRESWARM), PC_INPUT | PC_PULL_ENA | PC_PULL_UP | PC_MODE0) /* SYS_NRESWARM */ \
|
||||
PC_DEFINE(CP(SYS_OFF_MODE), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /* SYS_OFF_MODE */ \
|
||||
PC_DEFINE(CP(SYS_CLKOUT1), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE7) /* TP32 */ \
|
||||
\
|
||||
/* Unused GPMC lines (no mode7 for d0..d7 !) */ \
|
||||
PC_DEFINE(CP(GPMC_D0), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /* GPMC_D0 */ \
|
||||
PC_DEFINE(CP(GPMC_D1), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /* GPMC_D1 */ \
|
||||
PC_DEFINE(CP(GPMC_D2), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /* GPMC_D2 */ \
|
||||
PC_DEFINE(CP(GPMC_D3), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /* GPMC_D3 */ \
|
||||
PC_DEFINE(CP(GPMC_D4), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /* GPMC_D4 */ \
|
||||
PC_DEFINE(CP(GPMC_D5), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /* GPMC_D5 */ \
|
||||
PC_DEFINE(CP(GPMC_D6), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /* GPMC_D6 */ \
|
||||
PC_DEFINE(CP(GPMC_D7), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /* GPMC_D7 */ \
|
||||
PC_DEFINE(CP(GPMC_A5), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE7) /* TP183 */ \
|
||||
PC_DEFINE(CP(GPMC_NCS0), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /* TP144 */ \
|
||||
PC_DEFINE(CP(GPMC_NCS6), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE7) /* TP145 */ \
|
||||
PC_DEFINE(CP(GPMC_NCS7), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE7) /* TP146 */ \
|
||||
PC_DEFINE(CP(GPMC_CLK), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE7) /* TP2 */ \
|
||||
PC_DEFINE(CP(GPMC_NWE), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE7) /* TP4 */ \
|
||||
PC_DEFINE(CP(GPMC_NOE), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE7) /* TP10 */ \
|
||||
PC_DEFINE(CP(GPMC_NADV_ALE), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE7) /* TP3 */ \
|
||||
PC_DEFINE(CP(GPMC_NWP), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE7) /* TP7 */ \
|
||||
PC_DEFINE(CP(GPMC_WAIT0), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /* TP23 */ \
|
||||
PC_DEFINE(CP(GPMC_WAIT1), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE7) /* TP19 */ \
|
||||
\
|
||||
/* I2C lines */ \
|
||||
PC_DEFINE(CP(I2C2_SCL), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) \
|
||||
PC_DEFINE(CP(I2C2_SDA), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) \
|
||||
PC_DEFINE(CP(I2C3_SCL), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) \
|
||||
PC_DEFINE(CP(I2C3_SDA), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) \
|
||||
PC_DEFINE(CP(I2C4_SCL), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) \
|
||||
PC_DEFINE(CP(I2C4_SDA), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) \
|
||||
\
|
||||
/* Unused JTAG lines */ \
|
||||
PC_DEFINE(CP(JTAG_EMU0), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE7) /* TP24 */ \
|
||||
PC_DEFINE(CP(JTAG_EMU1), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE7) /* TP29 */ \
|
||||
\
|
||||
/* GPIO lines */ \
|
||||
PC_DEFINE(CP(CAM_XCLKA), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE4) /* 96: CAM_PWR_ON */ \
|
||||
PC_DEFINE(CP(CAM_WEN), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE4) /* 167: TP33 */ \
|
||||
PC_DEFINE(CP(CAM_D10), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE4) /* 109: DISP_ON */ \
|
||||
PC_DEFINE(CP(CAM_D11), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE4) /* 110: LCM_PWR_ENn_1 */ \
|
||||
PC_DEFINE(CP(ETK_D0), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE4) /* 14: BT_EN */ \
|
||||
PC_DEFINE(CP(ETK_D2), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE4) /* 16: BT_WAKE */ \
|
||||
PC_DEFINE(CP(ETK_D7), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE4) /* 21: HPWR */ \
|
||||
PC_DEFINE(CP(ETK_D8), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE4) /* 22: USB_SUSP */ \
|
||||
PC_DEFINE(CP(MCBSP4_CLKX), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE4) /* 152: BT_HOST_WAKE */\
|
||||
PC_DEFINE(CP(MCBSP4_DR), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE4) /* 153: nGPS_TCXO_ON */\
|
||||
PC_DEFINE(CP(MCBSP4_DX), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE4) /* 154: LCM_ID */ \
|
||||
PC_DEFINE(CP(MCBSP_CLKS), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE4) /* 160: nGPS_RESET */ \
|
||||
PC_DEFINE(CP(GPMC_A1), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE4) /* 34: RDS_IRQ */ \
|
||||
PC_DEFINE(CP(GPMC_A2), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE4) /* 35: RDS_RSTn */ \
|
||||
PC_DEFINE(CP(GPMC_A3), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE4) /* 36: MUTE */ \
|
||||
PC_DEFINE(CP(GPMC_A7), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE4) /* 40: LCD_PWR_ON */ \
|
||||
PC_DEFINE(CP(GPMC_A8), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE4) /* 41: nLCD_STBY */ \
|
||||
PC_DEFINE(CP(GPMC_A9), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE4) /* 42: GPS_1PPS */ \
|
||||
PC_DEFINE(CP(GPMC_A10), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE4) /* 43: CPU_WAKE */ \
|
||||
PC_DEFINE(CP(GPMC_D8), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE4) /* 44: DOCK_DET1 */ \
|
||||
PC_DEFINE(CP(GPMC_D9), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE4) /* 45: DOCK_DET0 */ \
|
||||
PC_DEFINE(CP(GPMC_D10), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE4) /* 46: EEPROM_WP */ \
|
||||
PC_DEFINE(CP(GPMC_D11), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE4) /* 47: AR_BTRSTOUTn */\
|
||||
PC_DEFINE(CP(GPMC_D12), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE4) /* 48: TILT_PWR */ \
|
||||
PC_DEFINE(CP(GPMC_D13), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE4) /* 49: TILT_OUT */ \
|
||||
PC_DEFINE(CP(GPMC_D14), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE4) /* 50: ACCESSORY_PWREN */ \
|
||||
PC_DEFINE(CP(GPMC_NCS2), PC_INPUT | PC_PULL_ENA | PC_PULL_DOWN | PC_MODE4) /* 53: USB_CHRG_DET */\
|
||||
PC_DEFINE(CP(GPMC_NCS4), PC_INPUT | PC_PULL_ENA | PC_PULL_UP | PC_MODE4) /* 55: nON_OFF */ \
|
||||
PC_DEFINE(CP(GPMC_NCS5), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE4) /* 56: LCM_nCS */ \
|
||||
PC_DEFINE(CP(GPMC_NBE1), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE4) /* 61: LOW_DC_VDD */ \
|
||||
PC_DEFINE(CP(SYS_CLKOUT2), PC_OUTPUT | PC_PULL_ENA | PC_PULL_DOWN | PC_MODE4) /* 186: WALL_SENSE_CONNECT */
|
||||
#endif // PADCONFIG_SANTIAGO_H
|
||||
|
||||
407
include/linux/padconfig_rennes_b1.h
Normal file
407
include/linux/padconfig_rennes_b1.h
Normal file
@ -0,0 +1,407 @@
|
||||
/*
|
||||
* Copyright (C) 2009 TomTom BV <http://www.tomtom.com/>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef PADCONFIG_RENNES_B1_H
|
||||
#define PADCONFIG_RENNES_B1_H
|
||||
|
||||
#include "padconfig_common.h"
|
||||
|
||||
/*******************************/
|
||||
/*********** TABLES ************/
|
||||
/*******************************/
|
||||
|
||||
#define PADCONFIG_SETTINGS_XLOADER_RENNES_B1 \
|
||||
/*SDRC*/ \
|
||||
PC_DEFINE(CP(SDRC_D0), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /*SDRC_D0*/ \
|
||||
PC_DEFINE(CP(SDRC_D1), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /*SDRC_D1*/ \
|
||||
PC_DEFINE(CP(SDRC_D2), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /*SDRC_D2*/ \
|
||||
PC_DEFINE(CP(SDRC_D3), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /*SDRC_D3*/ \
|
||||
PC_DEFINE(CP(SDRC_D4), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /*SDRC_D4*/ \
|
||||
PC_DEFINE(CP(SDRC_D5), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /*SDRC_D5*/ \
|
||||
PC_DEFINE(CP(SDRC_D6), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /*SDRC_D6*/ \
|
||||
PC_DEFINE(CP(SDRC_D7), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /*SDRC_D7*/ \
|
||||
PC_DEFINE(CP(SDRC_D8), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /*SDRC_D8*/ \
|
||||
PC_DEFINE(CP(SDRC_D9), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /*SDRC_D9*/ \
|
||||
PC_DEFINE(CP(SDRC_D10), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /*SDRC_D10*/ \
|
||||
PC_DEFINE(CP(SDRC_D11), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /*SDRC_D11*/ \
|
||||
PC_DEFINE(CP(SDRC_D12), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /*SDRC_D12*/ \
|
||||
PC_DEFINE(CP(SDRC_D13), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /*SDRC_D13*/ \
|
||||
PC_DEFINE(CP(SDRC_D14), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /*SDRC_D14*/ \
|
||||
PC_DEFINE(CP(SDRC_D15), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /*SDRC_D15*/ \
|
||||
PC_DEFINE(CP(SDRC_D16), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /*SDRC_D16*/ \
|
||||
PC_DEFINE(CP(SDRC_D17), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /*SDRC_D17*/ \
|
||||
PC_DEFINE(CP(SDRC_D18), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /*SDRC_D18*/ \
|
||||
PC_DEFINE(CP(SDRC_D19), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /*SDRC_D19*/ \
|
||||
PC_DEFINE(CP(SDRC_D20), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /*SDRC_D20*/ \
|
||||
PC_DEFINE(CP(SDRC_D21), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /*SDRC_D21*/ \
|
||||
PC_DEFINE(CP(SDRC_D22), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /*SDRC_D22*/ \
|
||||
PC_DEFINE(CP(SDRC_D23), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /*SDRC_D23*/ \
|
||||
PC_DEFINE(CP(SDRC_D24), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /*SDRC_D24*/ \
|
||||
PC_DEFINE(CP(SDRC_D25), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /*SDRC_D25*/ \
|
||||
PC_DEFINE(CP(SDRC_D26), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /*SDRC_D26*/ \
|
||||
PC_DEFINE(CP(SDRC_D27), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /*SDRC_D27*/ \
|
||||
PC_DEFINE(CP(SDRC_D28), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /*SDRC_D28*/ \
|
||||
PC_DEFINE(CP(SDRC_D29), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /*SDRC_D29*/ \
|
||||
PC_DEFINE(CP(SDRC_D30), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /*SDRC_D30*/ \
|
||||
PC_DEFINE(CP(SDRC_D31), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /*SDRC_D31*/ \
|
||||
PC_DEFINE(CP(SDRC_CLK), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /*SDRC_CLK*/ \
|
||||
PC_DEFINE(CP(SDRC_DQS0), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /*SDRC_DQS0*/ \
|
||||
PC_DEFINE(CP(SDRC_DQS1), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /*SDRC_DQS1*/ \
|
||||
PC_DEFINE(CP(SDRC_DQS2), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /*SDRC_DQS2*/ \
|
||||
PC_DEFINE(CP(SDRC_DQS3), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /*SDRC_DQS3*/ \
|
||||
\
|
||||
/* MMC lines */ \
|
||||
PC_DEFINE(CP(SDMMC1_CLK), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) \
|
||||
PC_DEFINE(CP(SDMMC1_CMD), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) \
|
||||
PC_DEFINE(CP(SDMMC1_DAT0), PC_INPUT | PC_PULL_ENA | PC_PULL_UP | PC_MODE0) \
|
||||
PC_DEFINE(CP(SDMMC1_DAT1), PC_INPUT | PC_PULL_ENA | PC_PULL_UP | PC_MODE0) \
|
||||
PC_DEFINE(CP(SDMMC1_DAT2), PC_INPUT | PC_PULL_ENA | PC_PULL_UP | PC_MODE0) \
|
||||
PC_DEFINE(CP(SDMMC1_DAT3), PC_INPUT | PC_PULL_ENA | PC_PULL_UP | PC_MODE0) \
|
||||
\
|
||||
/* USB0 lines */ \
|
||||
PC_DEFINE(CP(HSUSB0_CLK), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) \
|
||||
PC_DEFINE(CP(HSUSB0_DATA0), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) \
|
||||
PC_DEFINE(CP(HSUSB0_DATA1), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) \
|
||||
PC_DEFINE(CP(HSUSB0_DATA2), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) \
|
||||
PC_DEFINE(CP(HSUSB0_DATA3), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) \
|
||||
PC_DEFINE(CP(HSUSB0_DATA4), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) \
|
||||
PC_DEFINE(CP(HSUSB0_DATA5), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) \
|
||||
PC_DEFINE(CP(HSUSB0_DATA6), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) \
|
||||
PC_DEFINE(CP(HSUSB0_DATA7), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) \
|
||||
PC_DEFINE(CP(HSUSB0_DIR), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) \
|
||||
PC_DEFINE(CP(HSUSB0_NXT), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) \
|
||||
PC_DEFINE(CP(HSUSB0_STP), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) \
|
||||
\
|
||||
/* USB1 lines */ \
|
||||
PC_DEFINE(CP(ETK_D0), PC_INPUT | PC_PULL_ENA | PC_PULL_DOWN | PC_MODE4) /* MM1_RXRCV */ \
|
||||
PC_DEFINE(CP(ETK_D1), PC_INPUT | PC_PULL_ENA | PC_PULL_DOWN | PC_MODE4) /* MM1_TXSE0 */ \
|
||||
PC_DEFINE(CP(ETK_D2), PC_INPUT | PC_PULL_ENA | PC_PULL_DOWN | PC_MODE4) /* MM1_TXDAT */ \
|
||||
PC_DEFINE(CP(ETK_D7), PC_INPUT | PC_PULL_ENA | PC_PULL_DOWN | PC_MODE4) /* MM1_TXEN */ \
|
||||
PC_DEFINE(CP(MCBSP3_DR), PC_OUTPUT | PC_PULL_ENA | PC_PULL_DOWN | PC_MODE4) /* USB1_SPEED */ \
|
||||
PC_DEFINE(CP(MCBSP3_DX), PC_INPUT | PC_PULL_ENA | PC_PULL_UP | PC_MODE4) /* USB1_SUSPEND */ \
|
||||
\
|
||||
/* USB2 lines - TI CSR ticket OMAPS00262728: HSUSB2_DATA2 and HSUSB2_DATA6 */ \
|
||||
PC_DEFINE(CP(MCSPI1_CS3), PC_INPUT | PC_PULL_ENA | PC_PULL_DOWN | PC_MODE4) /* HSUSB2_DATA2 */ \
|
||||
PC_DEFINE(CP(MCSPI2_CS0), PC_INPUT | PC_PULL_ENA | PC_PULL_DOWN | PC_MODE4) /* HSUSB2_DATA6 */ \
|
||||
\
|
||||
/* The following settings are there to overcome TS problem */ \
|
||||
\
|
||||
/* UART1 lines */ \
|
||||
PC_DEFINE(CP(UART1_CTS), PC_OUTPUT | PC_PULL_ENA | PC_PULL_DOWN | PC_MODE4) /* GPS_RTS_SOC_CTS */ \
|
||||
PC_DEFINE(CP(UART1_RTS), PC_OUTPUT | PC_PULL_ENA | PC_PULL_DOWN | PC_MODE4) /* GPS_CTS_SOC_RTS */ \
|
||||
PC_DEFINE(CP(UART1_RX), PC_OUTPUT | PC_PULL_ENA | PC_PULL_DOWN | PC_MODE4) /* GPS_TX_SOC_RX */ \
|
||||
PC_DEFINE(CP(UART1_TX), PC_OUTPUT | PC_PULL_ENA | PC_PULL_DOWN | PC_MODE4) /* GPS_RX_SOC_TX */ \
|
||||
\
|
||||
/* UART2 lines */ \
|
||||
PC_DEFINE(CP(MCBSP3_CLKX), PC_OUTPUT | PC_PULL_ENA | PC_PULL_DOWN | PC_MODE4) /* BT_RX */ \
|
||||
PC_DEFINE(CP(MCBSP3_FSX), PC_OUTPUT | PC_PULL_ENA | PC_PULL_DOWN | PC_MODE4) /* BT_TX */ \
|
||||
\
|
||||
/* SDARS lines */ \
|
||||
PC_DEFINE(CP(ETK_D8), PC_INPUT | PC_PULL_ENA | PC_PULL_UP | PC_MODE4) /* nTUN_PWREN_UB */ \
|
||||
\
|
||||
/* GPIO lines */ \
|
||||
PC_DEFINE(CP(CAM_WEN), PC_INPUT | PC_PULL_ENA | PC_PULL_DOWN | PC_MODE4) /* GPS_CORE_PWR_EN */ \
|
||||
PC_DEFINE(CP(GPMC_NBE0_CLE), PC_INPUT | PC_PULL_ENA | PC_PULL_DOWN | PC_MODE4) /* nBT_RST */ \
|
||||
PC_DEFINE(CP(CAM_XCLKA), PC_INPUT | PC_PULL_ENA | PC_PULL_UP | PC_MODE4) /* CAM_PWR_ON */ \
|
||||
PC_DEFINE(CP(SDMMC2_DAT1), PC_INPUT | PC_PULL_ENA | PC_PULL_UP | PC_MODE4) /* nCAM_RST */ \
|
||||
PC_DEFINE(CP(MCBSP_CLKS), PC_INPUT | PC_PULL_ENA | PC_PULL_DOWN | PC_MODE4) /* nGPS2_RESET */ \
|
||||
PC_DEFINE(CP(UART3_RTS_SD), PC_INPUT | PC_PULL_ENA | PC_PULL_DOWN | PC_MODE4) /* GPS_HOST_REQ */ \
|
||||
\
|
||||
/* MCBSP1 lines */ \
|
||||
PC_DEFINE(CP(MCBSP1_CLKX), PC_INPUT | PC_PULL_ENA | PC_PULL_DOWN | PC_MODE4) /* BT_PCM_CLK */ \
|
||||
PC_DEFINE(CP(MCBSP1_DR), PC_INPUT | PC_PULL_ENA | PC_PULL_DOWN | PC_MODE4) /* BT_PCM_OUT */ \
|
||||
PC_DEFINE(CP(MCBSP1_DX), PC_INPUT | PC_PULL_ENA | PC_PULL_DOWN | PC_MODE4) /* BT_PCM_IN */ \
|
||||
PC_DEFINE(CP(MCBSP1_FSX), PC_INPUT | PC_PULL_ENA | PC_PULL_DOWN | PC_MODE4) /* BT_PCM_SYNC */ \
|
||||
|
||||
#ifndef PADCONFIG_SETTINGS_XLOADER
|
||||
#define PADCONFIG_SETTINGS_XLOADER PADCONFIG_SETTINGS_XLOADER_RENNES_B1
|
||||
#endif /* PADCONFIG_SETTINGS_XLOADER */
|
||||
|
||||
#define PADCONFIG_SETTINGS_UBOOT_RENNES_B1 \
|
||||
/* LCD lines */ \
|
||||
PC_DEFINE(CP(DSS_ACBIAS), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0 | PC_OFF_OUT_LOW) /* LCD_DAT_EN */ \
|
||||
PC_DEFINE(CP(DSS_DATA0), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0 | PC_OFF_OUT_LOW) /* LCD_D0 */ \
|
||||
PC_DEFINE(CP(DSS_DATA1), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0 | PC_OFF_OUT_LOW) /* LCD_D1 */ \
|
||||
PC_DEFINE(CP(DSS_DATA2), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0 | PC_OFF_OUT_LOW) /* LCD_D2 */ \
|
||||
PC_DEFINE(CP(DSS_DATA3), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0 | PC_OFF_OUT_LOW) /* LCD_D3 */ \
|
||||
PC_DEFINE(CP(DSS_DATA4), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0 | PC_OFF_OUT_LOW) /* LCD_D4 */ \
|
||||
PC_DEFINE(CP(DSS_DATA5), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0 | PC_OFF_OUT_LOW) /* LCD_D5 */ \
|
||||
PC_DEFINE(CP(DSS_DATA6), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0 | PC_OFF_OUT_LOW) /* LCD_D6 */ \
|
||||
PC_DEFINE(CP(DSS_DATA7), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0 | PC_OFF_OUT_LOW) /* LCD_D7 */ \
|
||||
PC_DEFINE(CP(DSS_DATA8), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0 | PC_OFF_OUT_LOW) /* LCD_D8 */ \
|
||||
PC_DEFINE(CP(DSS_DATA9), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0 | PC_OFF_OUT_LOW) /* LCD_D9 */ \
|
||||
PC_DEFINE(CP(DSS_DATA10), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0 | PC_OFF_OUT_LOW) /* LCD_D10 */ \
|
||||
PC_DEFINE(CP(DSS_DATA11), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0 | PC_OFF_OUT_LOW) /* LCD_D11 */ \
|
||||
PC_DEFINE(CP(DSS_DATA12), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0 | PC_OFF_OUT_LOW) /* LCD_D12 */ \
|
||||
PC_DEFINE(CP(DSS_DATA13), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0 | PC_OFF_OUT_LOW) /* LCD_D13 */ \
|
||||
PC_DEFINE(CP(DSS_DATA14), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0 | PC_OFF_OUT_LOW) /* LCD_D14 */ \
|
||||
PC_DEFINE(CP(DSS_DATA15), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0 | PC_OFF_OUT_LOW) /* LCD_D15 */ \
|
||||
PC_DEFINE(CP(DSS_DATA16), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0 | PC_OFF_OUT_LOW) /* LCD_D16 */ \
|
||||
PC_DEFINE(CP(DSS_DATA17), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0 | PC_OFF_OUT_LOW) /* LCD_D17 */ \
|
||||
PC_DEFINE(CP(DSS_DATA18), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0 | PC_OFF_OUT_LOW) /* LCD_D18 */ \
|
||||
PC_DEFINE(CP(DSS_DATA19), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0 | PC_OFF_OUT_LOW) /* LCD_D19 */ \
|
||||
PC_DEFINE(CP(DSS_DATA20), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0 | PC_OFF_OUT_LOW) /* LCD_D20 */ \
|
||||
PC_DEFINE(CP(DSS_DATA21), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0 | PC_OFF_OUT_LOW) /* LCD_D21 */ \
|
||||
PC_DEFINE(CP(DSS_DATA22), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0 | PC_OFF_OUT_LOW) /* LCD_D22 */ \
|
||||
PC_DEFINE(CP(DSS_DATA23), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0 | PC_OFF_OUT_LOW) /* LCD_D23 */ \
|
||||
PC_DEFINE(CP(DSS_PCLK), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0 | PC_OFF_OUT_LOW) /* LCD_PCLK */ \
|
||||
PC_DEFINE(CP(SDMMC2_DAT5), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE4) /* LCM_PWR_ON */ \
|
||||
PC_DEFINE(CP(MCBSP1_CLKR), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE4) /* nLCD_RESET */ \
|
||||
\
|
||||
|
||||
#ifndef PADCONFIG_SETTINGS_UBOOT
|
||||
#define PADCONFIG_SETTINGS_UBOOT PADCONFIG_SETTINGS_UBOOT_RENNES_B1
|
||||
#endif /* PADCONFIG_SETTINGS_UBOOT */
|
||||
|
||||
#define PADCONFIG_SETTINGS_KERNEL_RENNES_B1 \
|
||||
/* UART1 lines */ \
|
||||
PC_DEFINE(CP(UART1_CTS), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0 | PC_OFF_OUT_LOW) /* GPS_RTS_SOC_CTS */ \
|
||||
PC_DEFINE(CP(UART1_RTS), PC_INPUT | PC_PULL_ENA | PC_PULL_UP | PC_MODE0 | PC_OFF_OUT_LOW) /* GPS_CTS_SOC_RTS */ \
|
||||
PC_DEFINE(CP(UART1_RX), PC_INPUT | PC_PULL_ENA | PC_PULL_UP | PC_MODE0 | PC_OFF_OUT_LOW) /* GPS_TX_SOC_RX */ \
|
||||
PC_DEFINE(CP(UART1_TX), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0 | PC_OFF_OUT_LOW) /* GPS_RX_SOC_TX */ \
|
||||
\
|
||||
/* UART2 lines */ \
|
||||
PC_DEFINE(CP(MCBSP3_CLKX), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE1 | PC_OFF_OUT_LOW) /* BT_RX */ \
|
||||
PC_DEFINE(CP(MCBSP3_FSX), PC_INPUT | PC_PULL_ENA | PC_PULL_UP | PC_MODE1 | PC_OFF_OUT_LOW) /* BT_TX */ \
|
||||
\
|
||||
/* SDARS lines */ \
|
||||
PC_DEFINE(CP(ETK_D8), PC_INPUT | PC_PULL_ENA | PC_PULL_UP | PC_MODE4 | PC_OFF_OUT_HIGH) /* nTUN_PWREN_UB */ \
|
||||
\
|
||||
/* MCBSP1 lines */ \
|
||||
PC_DEFINE(CP(MCBSP1_CLKX), PC_INPUT | PC_PULL_ENA | PC_PULL_DOWN | PC_MODE0 | PC_OFF_OUT_LOW) /* BT_PCM_CLK */ \
|
||||
PC_DEFINE(CP(MCBSP1_DR), PC_INPUT | PC_PULL_ENA | PC_PULL_DOWN | PC_MODE0 | PC_OFF_OUT_LOW) /* BT_PCM_OUT */ \
|
||||
PC_DEFINE(CP(MCBSP1_DX), PC_OUTPUT | PC_PULL_ENA | PC_PULL_DOWN | PC_MODE0 | PC_OFF_OUT_LOW) /* BT_PCM_IN */ \
|
||||
PC_DEFINE(CP(MCBSP1_FSX), PC_INPUT | PC_PULL_ENA | PC_PULL_DOWN | PC_MODE0 | PC_OFF_OUT_LOW) /* BT_PCM_SYNC */ \
|
||||
\
|
||||
/* USB1 lines */ \
|
||||
PC_DEFINE(CP(ETK_D0), PC_INPUT | PC_PULL_ENA | PC_PULL_DOWN | PC_MODE4) /* MM1_RXRCV */ \
|
||||
PC_DEFINE(CP(ETK_D1), PC_INPUT | PC_PULL_ENA | PC_PULL_DOWN | PC_MODE4) /* MM1_TXSE0 */ \
|
||||
PC_DEFINE(CP(ETK_D2), PC_INPUT | PC_PULL_ENA | PC_PULL_DOWN | PC_MODE4) /* MM1_TXDAT */ \
|
||||
PC_DEFINE(CP(ETK_D7), PC_INPUT | PC_PULL_ENA | PC_PULL_DOWN | PC_MODE4 | PC_OFF_OUT_LOW) /* MM1_TXEN */ \
|
||||
PC_DEFINE(CP(MCBSP3_DR), PC_OUTPUT | PC_PULL_ENA | PC_PULL_DOWN | PC_MODE4) /* USB1_SPEED */ \
|
||||
PC_DEFINE(CP(MCBSP3_DX), PC_INPUT | PC_PULL_ENA | PC_PULL_UP | PC_MODE4 | PC_OFF_OUT_HIGH) /* USB1_SUSPEND */ \
|
||||
\
|
||||
/* USB2 lines - TI CSR ticket OMAPS00262728: HSUSB2_DATA2 and HSUSB2_DATA6 */ \
|
||||
PC_DEFINE(CP(MCSPI1_CS3), PC_INPUT | PC_PULL_ENA | PC_PULL_DOWN | PC_MODE4) /* HSUSB2_DATA2 */ \
|
||||
PC_DEFINE(CP(MCSPI2_CS0), PC_INPUT | PC_PULL_ENA | PC_PULL_DOWN | PC_MODE4) /* HSUSB2_DATA6 */ \
|
||||
\
|
||||
/* LCD lines */ \
|
||||
PC_DEFINE(CP(DSS_ACBIAS), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0 | PC_OFF_OUT_LOW) /* LCD_DAT_EN */ \
|
||||
PC_DEFINE(CP(DSS_DATA0), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0 | PC_OFF_OUT_LOW) /* LCD_D0 */ \
|
||||
PC_DEFINE(CP(DSS_DATA1), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0 | PC_OFF_OUT_LOW) /* LCD_D1 */ \
|
||||
PC_DEFINE(CP(DSS_DATA2), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0 | PC_OFF_OUT_LOW) /* LCD_D2 */ \
|
||||
PC_DEFINE(CP(DSS_DATA3), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0 | PC_OFF_OUT_LOW) /* LCD_D3 */ \
|
||||
PC_DEFINE(CP(DSS_DATA4), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0 | PC_OFF_OUT_LOW) /* LCD_D4 */ \
|
||||
PC_DEFINE(CP(DSS_DATA5), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0 | PC_OFF_OUT_LOW) /* LCD_D5 */ \
|
||||
PC_DEFINE(CP(DSS_DATA6), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0 | PC_OFF_OUT_LOW) /* LCD_D6 */ \
|
||||
PC_DEFINE(CP(DSS_DATA7), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0 | PC_OFF_OUT_LOW) /* LCD_D7 */ \
|
||||
PC_DEFINE(CP(DSS_DATA8), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0 | PC_OFF_OUT_LOW) /* LCD_D8 */ \
|
||||
PC_DEFINE(CP(DSS_DATA9), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0 | PC_OFF_OUT_LOW) /* LCD_D9 */ \
|
||||
PC_DEFINE(CP(DSS_DATA10), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0 | PC_OFF_OUT_LOW) /* LCD_D10 */ \
|
||||
PC_DEFINE(CP(DSS_DATA11), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0 | PC_OFF_OUT_LOW) /* LCD_D11 */ \
|
||||
PC_DEFINE(CP(DSS_DATA12), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0 | PC_OFF_OUT_LOW) /* LCD_D12 */ \
|
||||
PC_DEFINE(CP(DSS_DATA13), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0 | PC_OFF_OUT_LOW) /* LCD_D13 */ \
|
||||
PC_DEFINE(CP(DSS_DATA14), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0 | PC_OFF_OUT_LOW) /* LCD_D14 */ \
|
||||
PC_DEFINE(CP(DSS_DATA15), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0 | PC_OFF_OUT_LOW) /* LCD_D15 */ \
|
||||
PC_DEFINE(CP(DSS_DATA16), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0 | PC_OFF_OUT_LOW) /* LCD_D16 */ \
|
||||
PC_DEFINE(CP(DSS_DATA17), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0 | PC_OFF_OUT_LOW) /* LCD_D17 */ \
|
||||
PC_DEFINE(CP(DSS_DATA18), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0 | PC_OFF_OUT_LOW) /* LCD_D18 */ \
|
||||
PC_DEFINE(CP(DSS_DATA19), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0 | PC_OFF_OUT_LOW) /* LCD_D19 */ \
|
||||
PC_DEFINE(CP(DSS_DATA20), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0 | PC_OFF_OUT_LOW) /* LCD_D20 */ \
|
||||
PC_DEFINE(CP(DSS_DATA21), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0 | PC_OFF_OUT_LOW) /* LCD_D21 */ \
|
||||
PC_DEFINE(CP(DSS_DATA22), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0 | PC_OFF_OUT_LOW) /* LCD_D22 */ \
|
||||
PC_DEFINE(CP(DSS_DATA23), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0 | PC_OFF_OUT_LOW) /* LCD_D23 */ \
|
||||
PC_DEFINE(CP(DSS_PCLK), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0 | PC_OFF_OUT_LOW) /* LCD_PCLK */ \
|
||||
\
|
||||
/* JTAG lines */ \
|
||||
PC_DEFINE(CP(JTAG_NTRST), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /* uP_nTRST */ \
|
||||
PC_DEFINE(CP(JTAG_TCK), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /* uP_TCK */ \
|
||||
PC_DEFINE(CP(JTAG_TMS_TMSC), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /* uP_nTMS */ \
|
||||
PC_DEFINE(CP(JTAG_RTCK), PC_INPUT | PC_PULL_ENA | PC_PULL_DOWN | PC_MODE0) /* uP_nRTCK */ \
|
||||
PC_DEFINE(CP(JTAG_NTRST), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /* uP_nTRST */ \
|
||||
PC_DEFINE(CP(JTAG_TDI), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /* uP_TDI */ \
|
||||
PC_DEFINE(CP(JTAG_TDO), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /* uP_TDO */ \
|
||||
\
|
||||
/* GPIO lines */ \
|
||||
PC_DEFINE(CP(CAM_WEN), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE4 | PC_OFF_OUT_LOW) /* GPS_CORE_PWR_EN */ \
|
||||
PC_DEFINE(CP(CAM_XCLKA), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE4 | PC_OFF_OUT_LOW) /* CAM_PWR_ON */ \
|
||||
PC_DEFINE(CP(SDMMC2_DAT1), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE4 | PC_OFF_OUT_LOW) /* nCAM_RST */ \
|
||||
PC_DEFINE(CP(GPMC_NBE0_CLE), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE4 | PC_OFF_OUT_LOW) /* nBT_RST */ \
|
||||
PC_DEFINE(CP(MCBSP_CLKS), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE4 | PC_OFF_OUT_LOW) /* nGPS_RESET */ \
|
||||
PC_DEFINE(CP(UART3_RTS_SD), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE4 | PC_OFF_OUT_LOW) /* GPS_HOST_REQ */ \
|
||||
PC_DEFINE(CP(GPIO126), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE4 | PC_OFF_OUT_LOW) /* nAUTH_RST */ \
|
||||
PC_DEFINE(CP(GPIO129), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE4 | PC_OFF_OUT_LOW) /* CAM_ON */ \
|
||||
PC_DEFINE(CP(GPMC_NBE1), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE4 | OMAP_PIN_OFF_OUTPUT_HIGH)/* PWR_HOLD */ \
|
||||
|
||||
#ifndef PADCONFIG_SETTINGS_KERNEL
|
||||
#define PADCONFIG_SETTINGS_KERNEL PADCONFIG_SETTINGS_KERNEL_RENNES_B1
|
||||
#endif /* PADCONFIG_SETTINGS_KERNEL */
|
||||
|
||||
#define PADCONFIG_SETTINGS_COMMON_RENNES_B1 \
|
||||
/* CAM lines */ \
|
||||
PC_DEFINE(CP(CAM_D0), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /* CAM_D0 */ \
|
||||
PC_DEFINE(CP(CAM_D1), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /* CAM_D1 */ \
|
||||
PC_DEFINE(CP(CAM_D2), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /* CAM_D2 */ \
|
||||
PC_DEFINE(CP(CAM_D3), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /* CAM_D3 */ \
|
||||
PC_DEFINE(CP(CAM_D4), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /* CAM_D4 */ \
|
||||
PC_DEFINE(CP(CAM_D5), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /* CAM_D5 */ \
|
||||
PC_DEFINE(CP(CAM_D6), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /* CAM_D6 */ \
|
||||
PC_DEFINE(CP(CAM_D7), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /* CAM_D7 */ \
|
||||
PC_DEFINE(CP(CAM_FLD), PC_INPUT | PC_PULL_ENA | PC_PULL_DOWN | PC_MODE0) /* CAM_FLD */ \
|
||||
PC_DEFINE(CP(CAM_HS), PC_INPUT | PC_PULL_ENA | PC_PULL_DOWN | PC_MODE0) /* CAM_HS */ \
|
||||
PC_DEFINE(CP(CAM_PCLK), PC_INPUT | PC_PULL_ENA | PC_PULL_DOWN | PC_MODE0) /* CAM_PCLK */ \
|
||||
PC_DEFINE(CP(CAM_VS), PC_INPUT | PC_PULL_ENA | PC_PULL_DOWN | PC_MODE0) /* CAM_VS */ \
|
||||
\
|
||||
/* GPMC lines */ \
|
||||
PC_DEFINE(CP(GPMC_A1), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /* GPMC_A1 */ \
|
||||
PC_DEFINE(CP(GPMC_A2), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /* GPMC_A2 */ \
|
||||
PC_DEFINE(CP(GPMC_A3), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /* GPMC_A3 */ \
|
||||
PC_DEFINE(CP(GPMC_A4), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /* GPMC_A4 */ \
|
||||
PC_DEFINE(CP(GPMC_A5), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /* GPMC_A5 */ \
|
||||
PC_DEFINE(CP(GPMC_A6), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /* GPMC_A6 */ \
|
||||
PC_DEFINE(CP(GPMC_CLK), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /* GPMC_CLK */ \
|
||||
PC_DEFINE(CP(GPMC_D0), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /* GPMC_D0 */ \
|
||||
PC_DEFINE(CP(GPMC_D1), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /* GPMC_D1 */ \
|
||||
PC_DEFINE(CP(GPMC_D2), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /* GPMC_D2 */ \
|
||||
PC_DEFINE(CP(GPMC_D3), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /* GPMC_D3 */ \
|
||||
PC_DEFINE(CP(GPMC_D4), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /* GPMC_D4 */ \
|
||||
PC_DEFINE(CP(GPMC_D5), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /* GPMC_D5 */ \
|
||||
PC_DEFINE(CP(GPMC_D6), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /* GPMC_D6 */ \
|
||||
PC_DEFINE(CP(GPMC_D7), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /* GPMC_D7 */ \
|
||||
PC_DEFINE(CP(GPMC_D8), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /* GPMC_D8 */ \
|
||||
PC_DEFINE(CP(GPMC_D9), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /* GPMC_D9 */ \
|
||||
PC_DEFINE(CP(GPMC_D10), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /* GPMC_D10 */ \
|
||||
PC_DEFINE(CP(GPMC_D11), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /* GPMC_D11 */ \
|
||||
PC_DEFINE(CP(GPMC_D12), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /* GPMC_D12 */ \
|
||||
PC_DEFINE(CP(GPMC_D13), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /* GPMC_D13 */ \
|
||||
PC_DEFINE(CP(GPMC_D14), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /* GPMC_D14 */ \
|
||||
PC_DEFINE(CP(GPMC_D15), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /* GPMC_D15 */ \
|
||||
PC_DEFINE(CP(GPMC_NWP), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /* GPMC_nWP */ \
|
||||
PC_DEFINE(CP(GPMC_NCS0), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /* GPMC_nCS0 */ \
|
||||
PC_DEFINE(CP(GPMC_NCS1), PC_INPUT | PC_PULL_ENA | PC_PULL_DOWN | PC_MODE4) /* GPMC_nCS1 */ \
|
||||
PC_DEFINE(CP(GPMC_NCS2), PC_INPUT | PC_PULL_ENA | PC_PULL_DOWN | PC_MODE4) /* GPMC_nCS2 */ \
|
||||
PC_DEFINE(CP(GPMC_NOE), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /* GPMC_nOE */ \
|
||||
PC_DEFINE(CP(GPMC_NADV_ALE), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /* GPMC_nADV_ALE */ \
|
||||
PC_DEFINE(CP(GPMC_NWE), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /* GPMC_nWE */ \
|
||||
\
|
||||
/* MCBSP4 lines */ \
|
||||
PC_DEFINE(CP(GPMC_NCS4), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE2 | PC_OFF_OUT_LOW) /* MCBSP4_CLK */ \
|
||||
PC_DEFINE(CP(GPMC_NCS6), PC_OUTPUT | PC_PULL_ENA | PC_PULL_DOWN | PC_MODE2 | PC_OFF_OUT_LOW) /* MCBSP4_DX */ \
|
||||
PC_DEFINE(CP(GPMC_NCS7), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE2 | PC_OFF_OUT_LOW) /* MCBSP4_FSX */ \
|
||||
\
|
||||
/* I2C lines */ \
|
||||
PC_DEFINE(CP(I2C2_SCL), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) \
|
||||
PC_DEFINE(CP(I2C2_SDA), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) \
|
||||
PC_DEFINE(CP(I2C3_SCL), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) \
|
||||
PC_DEFINE(CP(I2C3_SDA), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) \
|
||||
PC_DEFINE(CP(I2C4_SCL), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE7) \
|
||||
PC_DEFINE(CP(I2C4_SDA), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE7) \
|
||||
PC_DEFINE(CP(I2C1_SCL), PC_INPUT | PC_PULL_ENA | PC_PULL_UP | PC_MODE0) \
|
||||
PC_DEFINE(CP(I2C1_SDA), PC_INPUT | PC_PULL_ENA | PC_PULL_UP | PC_MODE0) \
|
||||
\
|
||||
/* MCBSP2 lines */ \
|
||||
PC_DEFINE(CP(MCBSP2_CLKX), PC_INPUT | PC_PULL_ENA | PC_PULL_DOWN | PC_MODE0 | PC_OFF_IN_NOPULL) /* MCBSP2_CLK */ \
|
||||
PC_DEFINE(CP(MCBSP2_DR), PC_INPUT | PC_PULL_ENA | PC_PULL_DOWN | PC_MODE0 | PC_OFF_IN_NOPULL) /* MCBSP2_DR */ \
|
||||
PC_DEFINE(CP(MCBSP2_DX), PC_OUTPUT | PC_PULL_ENA | PC_PULL_DOWN | PC_MODE0 | PC_OFF_OUT_LOW) /* MCBSP2_DX */ \
|
||||
PC_DEFINE(CP(MCBSP2_FSX), PC_INPUT | PC_PULL_ENA | PC_PULL_DOWN | PC_MODE0 | PC_OFF_IN_NOPULL) /* MCBSP2_FSX */ \
|
||||
\
|
||||
/* MCSPI1 lines */ \
|
||||
PC_DEFINE(CP(MCSPI1_CLK), PC_INPUT | PC_PULL_ENA | PC_PULL_DOWN | PC_MODE0 | PC_OFF_IN_PULLDOWN) /* SPI_CAN_CLK */ \
|
||||
PC_DEFINE(CP(MCSPI1_SIMO), PC_INPUT | PC_PULL_ENA | PC_PULL_DOWN | PC_MODE0 | PC_OFF_IN_PULLDOWN) /* SPI_CAN_SIMO */ \
|
||||
PC_DEFINE(CP(MCSPI1_SOMI), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0 | PC_OFF_IN_PULLDOWN) /* SPI_CAN_SOMI */ \
|
||||
PC_DEFINE(CP(MCSPI1_CS0), PC_INPUT | PC_PULL_ENA | PC_PULL_DOWN | PC_MODE0 | PC_OFF_IN_PULLDOWN) /* SPI_CAN_CS0 */ \
|
||||
\
|
||||
/* SYS lines */ \
|
||||
PC_DEFINE(CP(SYS_BOOT0), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /* SYS_BOOT0 */ \
|
||||
PC_DEFINE(CP(SYS_BOOT1), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /* SYS_BOOT1 */ \
|
||||
PC_DEFINE(CP(SYS_BOOT2), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /* SYS_BOOT2 */ \
|
||||
PC_DEFINE(CP(SYS_BOOT3), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /* SYS_BOOT3 */ \
|
||||
PC_DEFINE(CP(SYS_BOOT4), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /* SYS_BOOT4 */ \
|
||||
PC_DEFINE(CP(SYS_BOOT5), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /* SYS_BOOT5 */ \
|
||||
PC_DEFINE(CP(SYS_BOOT6), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /* SYS_BOOT6 */ \
|
||||
PC_DEFINE(CP(SYS_CLKREQ), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /* SYS_CLKREQ */ \
|
||||
PC_DEFINE(CP(SYS_NIRQ), PC_INPUT | PC_PULL_ENA | PC_PULL_UP | PC_MODE0 | PC_WAKEUP_EN) /* SYS_NIRQ */ \
|
||||
PC_DEFINE(CP(SYS_NRESWARM), PC_INPUT | PC_PULL_ENA | PC_PULL_UP | PC_MODE0) /* SYS_NRESWARM */ \
|
||||
PC_DEFINE(CP(SYS_OFF_MODE), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /* SYS_OFF_MODE */ \
|
||||
\
|
||||
/* UART3 lines */ \
|
||||
PC_DEFINE(CP(UART3_RX_IRRX), PC_INPUT | PC_PULL_ENA | PC_PULL_UP | PC_MODE0 | PC_OFF_IN_PULLDOWN) /* DEBUG_RX */ \
|
||||
PC_DEFINE(CP(UART3_TX_IRTX), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0 | PC_OFF_OUT_LOW) /* DEBUG_TX */ \
|
||||
\
|
||||
/* BACKLIGHT lines */ \
|
||||
PC_DEFINE(CP(GPMC_NCS5), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE3 | PC_OFF_IN_NOPULL) /* BACKLIGHT_PWM */ \
|
||||
PC_DEFINE(CP(GPMC_WAIT3), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE4 | PC_OFF_OUT_LOW) /* BACKLIGHT_ON */ \
|
||||
\
|
||||
/* nACCEL_IRQ and nGYRO_IRQ lines */ \
|
||||
PC_DEFINE(CP(ETK_D5), PC_INPUT | PC_PULL_ENA | PC_PULL_DOWN | PC_MODE4 | PC_OFF_OUT_LOW) /* nGYRO_IRQ */ \
|
||||
PC_DEFINE(CP(CAM_D10), PC_INPUT | PC_PULL_ENA | PC_PULL_DOWN | PC_MODE4 | PC_OFF_OUT_LOW) /* nACCEL_IRQ */ \
|
||||
\
|
||||
/* Unused lines set as GPIOs */ \
|
||||
PC_DEFINE(CP(UART2_CTS), PC_INPUT | PC_PULL_ENA | PC_PULL_DOWN | PC_MODE4) /* UART_CTS as GPIO */ \
|
||||
PC_DEFINE(CP(UART2_RTS), PC_INPUT | PC_PULL_ENA | PC_PULL_DOWN | PC_MODE4) /* UART_RTS as GPIO */ \
|
||||
PC_DEFINE(CP(UART2_RX), PC_INPUT | PC_PULL_ENA | PC_PULL_DOWN | PC_MODE4) /* UART_RX as GPIO */ \
|
||||
PC_DEFINE(CP(UART2_TX), PC_INPUT | PC_PULL_ENA | PC_PULL_DOWN | PC_MODE4) /* UART_TX as GPIO */ \
|
||||
PC_DEFINE(CP(GPMC_A7), PC_INPUT | PC_PULL_ENA | PC_PULL_DOWN | PC_MODE4) /* GPMC_A7 as GPIO */ \
|
||||
PC_DEFINE(CP(GPMC_A10), PC_INPUT | PC_PULL_ENA | PC_PULL_DOWN | PC_MODE4) /* GPMC_A10 as GPIO */ \
|
||||
PC_DEFINE(CP(SDMMC2_CLK), PC_INPUT | PC_PULL_ENA | PC_PULL_DOWN | PC_MODE4 | PC_OFF_OUT_LOW) /* MCSPI3_CLK */ \
|
||||
PC_DEFINE(CP(SDMMC2_CMD), PC_INPUT | PC_PULL_ENA | PC_PULL_DOWN | PC_MODE4 | PC_OFF_OUT_LOW) /* MCSPI3_SIMO */ \
|
||||
PC_DEFINE(CP(SDMMC2_DAT0), PC_INPUT | PC_PULL_ENA | PC_PULL_DOWN | PC_MODE4 | PC_OFF_OUT_LOW) /* MCSPI3_SOMI */ \
|
||||
PC_DEFINE(CP(SDMMC2_DAT2), PC_INPUT | PC_PULL_ENA | PC_PULL_DOWN | PC_MODE4) /* SDMMC2_DAT2 as GPIO */\
|
||||
PC_DEFINE(CP(SDMMC2_DAT3), PC_INPUT | PC_PULL_ENA | PC_PULL_DOWN | PC_MODE4 | PC_OFF_OUT_LOW) /* MCSPI3_CS0 */ \
|
||||
PC_DEFINE(CP(SDMMC2_DAT6), PC_INPUT | PC_PULL_ENA | PC_PULL_DOWN | PC_MODE4) /* SDMMC2_DAT6 as GPIO */\
|
||||
PC_DEFINE(CP(CAM_STROBE), PC_INPUT | PC_PULL_ENA | PC_PULL_DOWN | PC_MODE4) /* CAM_STROBE as GPIO */\
|
||||
PC_DEFINE(CP(DSS_HSYNC), PC_INPUT | PC_PULL_ENA | PC_PULL_DOWN | PC_MODE4) /* LCD_HSYNC as GPIO */ \
|
||||
PC_DEFINE(CP(DSS_VSYNC), PC_INPUT | PC_PULL_ENA | PC_PULL_DOWN | PC_MODE4) /* LCD_VSYNC as GPIO */ \
|
||||
PC_DEFINE(CP(ETK_CTL), PC_INPUT | PC_PULL_ENA | PC_PULL_DOWN | PC_MODE4) /* ETK_CTL as GPIO */ \
|
||||
PC_DEFINE(CP(ETK_D4), PC_INPUT | PC_PULL_ENA | PC_PULL_DOWN | PC_MODE4) /* ETK_D4 as GPIO */ \
|
||||
PC_DEFINE(CP(ETK_D6), PC_INPUT | PC_PULL_ENA | PC_PULL_DOWN | PC_MODE4) /* ETK_D6 as GPIO */ \
|
||||
PC_DEFINE(CP(ETK_D9), PC_INPUT | PC_PULL_ENA | PC_PULL_DOWN | PC_MODE4) /* ETK_D9 as GPIO */ \
|
||||
PC_DEFINE(CP(MCBSP4_CLKX), PC_INPUT | PC_PULL_ENA | PC_PULL_DOWN | PC_MODE4) /* MCBSP4_CLKX as GPIO */\
|
||||
PC_DEFINE(CP(MCBSP4_DR), PC_INPUT | PC_PULL_ENA | PC_PULL_DOWN | PC_MODE4) /* MCBSP4_DR as GPIO */ \
|
||||
PC_DEFINE(CP(MCBSP4_DX), PC_INPUT | PC_PULL_ENA | PC_PULL_DOWN | PC_MODE4 | PC_OFF_OUT_LOW) /* MCBSP4_DX as GPIO */ \
|
||||
PC_DEFINE(CP(MCBSP4_FSX), PC_INPUT | PC_PULL_ENA | PC_PULL_DOWN | PC_MODE4 | PC_OFF_OUT_LOW) /* MCBSP4_FSX as GPIO */ \
|
||||
PC_DEFINE(CP(MCSPI1_CS1), PC_INPUT | PC_PULL_ENA | PC_PULL_DOWN | PC_MODE4) /* MCSPI1_CS1 as GPIO */ \
|
||||
PC_DEFINE(CP(MCSPI1_CS2), PC_INPUT | PC_PULL_ENA | PC_PULL_DOWN | PC_MODE4) /* MCSPI1_CS2 as GPIO */ \
|
||||
PC_DEFINE(CP(GPMC_NCS1), PC_INPUT | PC_PULL_ENA | PC_PULL_DOWN | PC_MODE4) /* GPMC_nCS1 as GPIO */ \
|
||||
PC_DEFINE(CP(GPMC_NCS2), PC_INPUT | PC_PULL_ENA | PC_PULL_DOWN | PC_MODE4) /* GPMC_nCS2 as GPIO */ \
|
||||
PC_DEFINE(CP(GPMC_WAIT1), PC_INPUT | PC_PULL_ENA | PC_PULL_DOWN | PC_MODE4) /* GPMC_WAIT1 as GPIO */ \
|
||||
PC_DEFINE(CP(GPMC_WAIT2), PC_INPUT | PC_PULL_ENA | PC_PULL_DOWN | PC_MODE4) /* GPMC_WAIT2 as GPIO */ \
|
||||
PC_DEFINE(CP(CSI2_DX0), PC_INPUT | PC_PULL_ENA | PC_PULL_DOWN | PC_MODE4) /* CSI2_DX0 as GPIO */ \
|
||||
PC_DEFINE(CP(CSI2_DY0), PC_INPUT | PC_PULL_ENA | PC_PULL_DOWN | PC_MODE4) /* CSI2_DY0 as GPIO */ \
|
||||
PC_DEFINE(CP(CSI2_DX1), PC_INPUT | PC_PULL_ENA | PC_PULL_DOWN | PC_MODE4) /* CSI2_DX1 as GPIO */ \
|
||||
PC_DEFINE(CP(CSI2_DY1), PC_INPUT | PC_PULL_ENA | PC_PULL_DOWN | PC_MODE4) /* CSI2_DY1 as GPIO */ \
|
||||
\
|
||||
/* GPIO lines */ \
|
||||
PC_DEFINE(CP(CAM_D8), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE4 | PC_OFF_IN_PULLDOWN) /* nCAM_IRQ */ \
|
||||
PC_DEFINE(CP(CAM_D9), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE4) /* nGPS_ANT_SHORT */ \
|
||||
PC_DEFINE(CP(CAM_D11), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE4 | PC_OFF_OUT_LOW) /* nUSB2_RESET */ \
|
||||
PC_DEFINE(CP(CAM_XCLKB), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE4 | PC_OFF_OUT_LOW) /* MIC_ON */ \
|
||||
PC_DEFINE(CP(SDMMC2_DAT4), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE4 | PC_OFF_OUT_LOW) /* nCAN_RST */ \
|
||||
PC_DEFINE(CP(SDMMC2_DAT5), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE4 | PC_OFF_OUT_LOW) /* LCM_PWR_ON */ \
|
||||
PC_DEFINE(CP(SDMMC2_DAT7), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE4 | PC_OFF_OUT_LOW) /* nCAN_IRQ */ \
|
||||
PC_DEFINE(CP(GPMC_A8), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE4 | PC_OFF_IN_NOPULL) /* nDIAGSYS_BOOT */ \
|
||||
PC_DEFINE(CP(GPMC_A9), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE4 | PC_OFF_OUT_LOW) /* GPS_1PPS */ \
|
||||
PC_DEFINE(CP(GPMC_NCS3), PC_INPUT | PC_PULL_ENA | PC_PULL_UP | PC_MODE4 | PC_OFF_OUT_LOW) /* nTP_IRQ */ \
|
||||
PC_DEFINE(CP(HDQ_SIO), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE4 | PC_OFF_IN_PULLDOWN) /* CAN_RST_MON */ \
|
||||
PC_DEFINE(CP(JTAG_EMU0), PC_INPUT | PC_PULL_ENA | PC_PULL_UP | PC_MODE4 | PC_OFF_IN_NOPULL) /* nUSB3_POWER_FAULT */\
|
||||
PC_DEFINE(CP(JTAG_EMU1), PC_INPUT | PC_PULL_ENA | PC_PULL_UP | PC_MODE4 | PC_OFF_IN_NOPULL) /* nUSB1_POWER_FAULT */\
|
||||
PC_DEFINE(CP(MCBSP1_CLKR), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE4 | PC_OFF_OUT_LOW) /* nLCD_RESET */ \
|
||||
PC_DEFINE(CP(MCBSP1_FSR), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE4 | PC_OFF_OUT_LOW) /* nTP_RESET */ \
|
||||
PC_DEFINE(CP(SYS_CLKOUT1), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE4) /* nON_OFF */ \
|
||||
PC_DEFINE(CP(SYS_CLKOUT2), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE4 | PC_OFF_OUT_LOW) /* CAN_BT_MD */ \
|
||||
PC_DEFINE(CP(UART3_CTS_RCTX),PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE4 | PC_OFF_OUT_LOW) /* CAN_SYNC */ \
|
||||
PC_DEFINE(CP(ETK_CLK), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE4) /* LCD_UD */ \
|
||||
PC_DEFINE(CP(ETK_D3), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE4 | PC_OFF_OUT_LOW) /* SENSE_11V0 */ \
|
||||
|
||||
#ifndef PADCONFIG_SETTINGS_COMMON
|
||||
#define PADCONFIG_SETTINGS_COMMON PADCONFIG_SETTINGS_COMMON_RENNES_B1
|
||||
#endif /* PADCONFIG_SETTINGS_COMMON */
|
||||
|
||||
#endif // PADCONFIG_RENNES_B1_H
|
||||
|
||||
407
include/linux/padconfig_stuttgart_b1.h
Normal file
407
include/linux/padconfig_stuttgart_b1.h
Normal file
@ -0,0 +1,407 @@
|
||||
/*
|
||||
* Copyright (C) 2009 TomTom BV <http://www.tomtom.com/>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef PADCONFIG_STUTTGART_B1_H
|
||||
#define PADCONFIG_STUTTGART_B1_H
|
||||
|
||||
#include "padconfig_common.h"
|
||||
|
||||
/*******************************/
|
||||
/*********** TABLES ************/
|
||||
/*******************************/
|
||||
|
||||
#define PADCONFIG_SETTINGS_XLOADER_STUTTGART_B1 \
|
||||
/*SDRC*/ \
|
||||
PC_DEFINE(CP(SDRC_D0), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /*SDRC_D0*/ \
|
||||
PC_DEFINE(CP(SDRC_D1), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /*SDRC_D1*/ \
|
||||
PC_DEFINE(CP(SDRC_D2), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /*SDRC_D2*/ \
|
||||
PC_DEFINE(CP(SDRC_D3), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /*SDRC_D3*/ \
|
||||
PC_DEFINE(CP(SDRC_D4), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /*SDRC_D4*/ \
|
||||
PC_DEFINE(CP(SDRC_D5), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /*SDRC_D5*/ \
|
||||
PC_DEFINE(CP(SDRC_D6), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /*SDRC_D6*/ \
|
||||
PC_DEFINE(CP(SDRC_D7), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /*SDRC_D7*/ \
|
||||
PC_DEFINE(CP(SDRC_D8), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /*SDRC_D8*/ \
|
||||
PC_DEFINE(CP(SDRC_D9), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /*SDRC_D9*/ \
|
||||
PC_DEFINE(CP(SDRC_D10), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /*SDRC_D10*/ \
|
||||
PC_DEFINE(CP(SDRC_D11), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /*SDRC_D11*/ \
|
||||
PC_DEFINE(CP(SDRC_D12), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /*SDRC_D12*/ \
|
||||
PC_DEFINE(CP(SDRC_D13), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /*SDRC_D13*/ \
|
||||
PC_DEFINE(CP(SDRC_D14), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /*SDRC_D14*/ \
|
||||
PC_DEFINE(CP(SDRC_D15), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /*SDRC_D15*/ \
|
||||
PC_DEFINE(CP(SDRC_D16), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /*SDRC_D16*/ \
|
||||
PC_DEFINE(CP(SDRC_D17), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /*SDRC_D17*/ \
|
||||
PC_DEFINE(CP(SDRC_D18), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /*SDRC_D18*/ \
|
||||
PC_DEFINE(CP(SDRC_D19), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /*SDRC_D19*/ \
|
||||
PC_DEFINE(CP(SDRC_D20), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /*SDRC_D20*/ \
|
||||
PC_DEFINE(CP(SDRC_D21), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /*SDRC_D21*/ \
|
||||
PC_DEFINE(CP(SDRC_D22), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /*SDRC_D22*/ \
|
||||
PC_DEFINE(CP(SDRC_D23), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /*SDRC_D23*/ \
|
||||
PC_DEFINE(CP(SDRC_D24), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /*SDRC_D24*/ \
|
||||
PC_DEFINE(CP(SDRC_D25), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /*SDRC_D25*/ \
|
||||
PC_DEFINE(CP(SDRC_D26), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /*SDRC_D26*/ \
|
||||
PC_DEFINE(CP(SDRC_D27), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /*SDRC_D27*/ \
|
||||
PC_DEFINE(CP(SDRC_D28), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /*SDRC_D28*/ \
|
||||
PC_DEFINE(CP(SDRC_D29), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /*SDRC_D29*/ \
|
||||
PC_DEFINE(CP(SDRC_D30), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /*SDRC_D30*/ \
|
||||
PC_DEFINE(CP(SDRC_D31), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /*SDRC_D31*/ \
|
||||
PC_DEFINE(CP(SDRC_CLK), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /*SDRC_CLK*/ \
|
||||
PC_DEFINE(CP(SDRC_DQS0), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /*SDRC_DQS0*/ \
|
||||
PC_DEFINE(CP(SDRC_DQS1), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /*SDRC_DQS1*/ \
|
||||
PC_DEFINE(CP(SDRC_DQS2), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /*SDRC_DQS2*/ \
|
||||
PC_DEFINE(CP(SDRC_DQS3), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /*SDRC_DQS3*/ \
|
||||
\
|
||||
/* MMC lines */ \
|
||||
PC_DEFINE(CP(SDMMC1_CLK), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) \
|
||||
PC_DEFINE(CP(SDMMC1_CMD), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) \
|
||||
PC_DEFINE(CP(SDMMC1_DAT0), PC_INPUT | PC_PULL_ENA | PC_PULL_UP | PC_MODE0) \
|
||||
PC_DEFINE(CP(SDMMC1_DAT1), PC_INPUT | PC_PULL_ENA | PC_PULL_UP | PC_MODE0) \
|
||||
PC_DEFINE(CP(SDMMC1_DAT2), PC_INPUT | PC_PULL_ENA | PC_PULL_UP | PC_MODE0) \
|
||||
PC_DEFINE(CP(SDMMC1_DAT3), PC_INPUT | PC_PULL_ENA | PC_PULL_UP | PC_MODE0) \
|
||||
\
|
||||
/* USB0 lines */ \
|
||||
PC_DEFINE(CP(HSUSB0_CLK), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) \
|
||||
PC_DEFINE(CP(HSUSB0_DATA0), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) \
|
||||
PC_DEFINE(CP(HSUSB0_DATA1), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) \
|
||||
PC_DEFINE(CP(HSUSB0_DATA2), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) \
|
||||
PC_DEFINE(CP(HSUSB0_DATA3), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) \
|
||||
PC_DEFINE(CP(HSUSB0_DATA4), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) \
|
||||
PC_DEFINE(CP(HSUSB0_DATA5), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) \
|
||||
PC_DEFINE(CP(HSUSB0_DATA6), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) \
|
||||
PC_DEFINE(CP(HSUSB0_DATA7), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) \
|
||||
PC_DEFINE(CP(HSUSB0_DIR), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) \
|
||||
PC_DEFINE(CP(HSUSB0_NXT), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) \
|
||||
PC_DEFINE(CP(HSUSB0_STP), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) \
|
||||
\
|
||||
/* USB1 lines */ \
|
||||
PC_DEFINE(CP(ETK_D0), PC_INPUT | PC_PULL_ENA | PC_PULL_DOWN | PC_MODE4) /* MM1_RXRCV */ \
|
||||
PC_DEFINE(CP(ETK_D1), PC_INPUT | PC_PULL_ENA | PC_PULL_DOWN | PC_MODE4) /* MM1_TXSE0 */ \
|
||||
PC_DEFINE(CP(ETK_D2), PC_INPUT | PC_PULL_ENA | PC_PULL_DOWN | PC_MODE4) /* MM1_TXDAT */ \
|
||||
PC_DEFINE(CP(ETK_D7), PC_INPUT | PC_PULL_ENA | PC_PULL_DOWN | PC_MODE4) /* MM1_TXEN */ \
|
||||
PC_DEFINE(CP(MCBSP3_DR), PC_OUTPUT | PC_PULL_ENA | PC_PULL_DOWN | PC_MODE4) /* USB1_SPEED */ \
|
||||
PC_DEFINE(CP(MCBSP3_DX), PC_INPUT | PC_PULL_ENA | PC_PULL_UP | PC_MODE4) /* USB1_SUSPEND */ \
|
||||
\
|
||||
/* USB2 lines - TI CSR ticket OMAPS00262728: HSUSB2_DATA2 and HSUSB2_DATA6 */ \
|
||||
PC_DEFINE(CP(MCSPI1_CS3), PC_INPUT | PC_PULL_ENA | PC_PULL_DOWN | PC_MODE4) /* HSUSB2_DATA2 */ \
|
||||
PC_DEFINE(CP(MCSPI2_CS0), PC_INPUT | PC_PULL_ENA | PC_PULL_DOWN | PC_MODE4) /* HSUSB2_DATA6 */ \
|
||||
\
|
||||
/* The following settings are there to overcome TS problem */ \
|
||||
\
|
||||
/* UART1 lines */ \
|
||||
PC_DEFINE(CP(UART1_CTS), PC_OUTPUT | PC_PULL_ENA | PC_PULL_DOWN | PC_MODE4) /* GPS_RTS_SOC_CTS */ \
|
||||
PC_DEFINE(CP(UART1_RTS), PC_OUTPUT | PC_PULL_ENA | PC_PULL_DOWN | PC_MODE4) /* GPS_CTS_SOC_RTS */ \
|
||||
PC_DEFINE(CP(UART1_RX), PC_OUTPUT | PC_PULL_ENA | PC_PULL_DOWN | PC_MODE4) /* GPS_TX_SOC_RX */ \
|
||||
PC_DEFINE(CP(UART1_TX), PC_OUTPUT | PC_PULL_ENA | PC_PULL_DOWN | PC_MODE4) /* GPS_RX_SOC_TX */ \
|
||||
\
|
||||
/* UART2 lines */ \
|
||||
PC_DEFINE(CP(MCBSP3_CLKX), PC_OUTPUT | PC_PULL_ENA | PC_PULL_DOWN | PC_MODE4) /* BT_RX */ \
|
||||
PC_DEFINE(CP(MCBSP3_FSX), PC_OUTPUT | PC_PULL_ENA | PC_PULL_DOWN | PC_MODE4) /* BT_TX */ \
|
||||
\
|
||||
/* SDARS lines */ \
|
||||
PC_DEFINE(CP(ETK_D8), PC_INPUT | PC_PULL_ENA | PC_PULL_UP | PC_MODE4) /* nTUN_PWREN_UB */ \
|
||||
\
|
||||
/* GPIO lines */ \
|
||||
PC_DEFINE(CP(CAM_WEN), PC_INPUT | PC_PULL_ENA | PC_PULL_DOWN | PC_MODE4) /* GPS_CORE_PWR_EN */ \
|
||||
PC_DEFINE(CP(GPMC_NBE0_CLE), PC_INPUT | PC_PULL_ENA | PC_PULL_DOWN | PC_MODE4) /* nBT_RST */ \
|
||||
PC_DEFINE(CP(CAM_XCLKA), PC_INPUT | PC_PULL_ENA | PC_PULL_UP | PC_MODE4) /* CAM_PWR_ON */ \
|
||||
PC_DEFINE(CP(SDMMC2_DAT1), PC_INPUT | PC_PULL_ENA | PC_PULL_UP | PC_MODE4) /* nCAM_RST */ \
|
||||
PC_DEFINE(CP(MCBSP_CLKS), PC_INPUT | PC_PULL_ENA | PC_PULL_DOWN | PC_MODE4) /* nGPS2_RESET */ \
|
||||
PC_DEFINE(CP(UART3_RTS_SD), PC_INPUT | PC_PULL_ENA | PC_PULL_DOWN | PC_MODE4) /* GPS_HOST_REQ */ \
|
||||
\
|
||||
/* MCBSP1 lines */ \
|
||||
PC_DEFINE(CP(MCBSP1_CLKX), PC_INPUT | PC_PULL_ENA | PC_PULL_DOWN | PC_MODE4) /* BT_PCM_CLK */ \
|
||||
PC_DEFINE(CP(MCBSP1_DR), PC_INPUT | PC_PULL_ENA | PC_PULL_DOWN | PC_MODE4) /* BT_PCM_OUT */ \
|
||||
PC_DEFINE(CP(MCBSP1_DX), PC_INPUT | PC_PULL_ENA | PC_PULL_DOWN | PC_MODE4) /* BT_PCM_IN */ \
|
||||
PC_DEFINE(CP(MCBSP1_FSX), PC_INPUT | PC_PULL_ENA | PC_PULL_DOWN | PC_MODE4) /* BT_PCM_SYNC */ \
|
||||
|
||||
#ifndef PADCONFIG_SETTINGS_XLOADER
|
||||
#define PADCONFIG_SETTINGS_XLOADER PADCONFIG_SETTINGS_XLOADER_STUTTGART_B1
|
||||
#endif /* PADCONFIG_SETTINGS_XLOADER */
|
||||
|
||||
#define PADCONFIG_SETTINGS_UBOOT_STUTTGART_B1 \
|
||||
/* LCD lines */ \
|
||||
PC_DEFINE(CP(DSS_ACBIAS), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0 | PC_OFF_OUT_LOW) /* LCD_DAT_EN */ \
|
||||
PC_DEFINE(CP(DSS_DATA0), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0 | PC_OFF_OUT_LOW) /* LCD_D0 */ \
|
||||
PC_DEFINE(CP(DSS_DATA1), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0 | PC_OFF_OUT_LOW) /* LCD_D1 */ \
|
||||
PC_DEFINE(CP(DSS_DATA2), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0 | PC_OFF_OUT_LOW) /* LCD_D2 */ \
|
||||
PC_DEFINE(CP(DSS_DATA3), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0 | PC_OFF_OUT_LOW) /* LCD_D3 */ \
|
||||
PC_DEFINE(CP(DSS_DATA4), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0 | PC_OFF_OUT_LOW) /* LCD_D4 */ \
|
||||
PC_DEFINE(CP(DSS_DATA5), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0 | PC_OFF_OUT_LOW) /* LCD_D5 */ \
|
||||
PC_DEFINE(CP(DSS_DATA6), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0 | PC_OFF_OUT_LOW) /* LCD_D6 */ \
|
||||
PC_DEFINE(CP(DSS_DATA7), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0 | PC_OFF_OUT_LOW) /* LCD_D7 */ \
|
||||
PC_DEFINE(CP(DSS_DATA8), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0 | PC_OFF_OUT_LOW) /* LCD_D8 */ \
|
||||
PC_DEFINE(CP(DSS_DATA9), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0 | PC_OFF_OUT_LOW) /* LCD_D9 */ \
|
||||
PC_DEFINE(CP(DSS_DATA10), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0 | PC_OFF_OUT_LOW) /* LCD_D10 */ \
|
||||
PC_DEFINE(CP(DSS_DATA11), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0 | PC_OFF_OUT_LOW) /* LCD_D11 */ \
|
||||
PC_DEFINE(CP(DSS_DATA12), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0 | PC_OFF_OUT_LOW) /* LCD_D12 */ \
|
||||
PC_DEFINE(CP(DSS_DATA13), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0 | PC_OFF_OUT_LOW) /* LCD_D13 */ \
|
||||
PC_DEFINE(CP(DSS_DATA14), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0 | PC_OFF_OUT_LOW) /* LCD_D14 */ \
|
||||
PC_DEFINE(CP(DSS_DATA15), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0 | PC_OFF_OUT_LOW) /* LCD_D15 */ \
|
||||
PC_DEFINE(CP(DSS_DATA16), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0 | PC_OFF_OUT_LOW) /* LCD_D16 */ \
|
||||
PC_DEFINE(CP(DSS_DATA17), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0 | PC_OFF_OUT_LOW) /* LCD_D17 */ \
|
||||
PC_DEFINE(CP(DSS_DATA18), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0 | PC_OFF_OUT_LOW) /* LCD_D18 */ \
|
||||
PC_DEFINE(CP(DSS_DATA19), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0 | PC_OFF_OUT_LOW) /* LCD_D19 */ \
|
||||
PC_DEFINE(CP(DSS_DATA20), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0 | PC_OFF_OUT_LOW) /* LCD_D20 */ \
|
||||
PC_DEFINE(CP(DSS_DATA21), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0 | PC_OFF_OUT_LOW) /* LCD_D21 */ \
|
||||
PC_DEFINE(CP(DSS_DATA22), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0 | PC_OFF_OUT_LOW) /* LCD_D22 */ \
|
||||
PC_DEFINE(CP(DSS_DATA23), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0 | PC_OFF_OUT_LOW) /* LCD_D23 */ \
|
||||
PC_DEFINE(CP(DSS_PCLK), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0 | PC_OFF_OUT_LOW) /* LCD_PCLK */ \
|
||||
PC_DEFINE(CP(SDMMC2_DAT5), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE4) /* LCM_PWR_ON */ \
|
||||
PC_DEFINE(CP(MCBSP1_CLKR), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE4) /* nLCD_RESET */ \
|
||||
\
|
||||
|
||||
#ifndef PADCONFIG_SETTINGS_UBOOT
|
||||
#define PADCONFIG_SETTINGS_UBOOT PADCONFIG_SETTINGS_UBOOT_STUTTGART_B1
|
||||
#endif /* PADCONFIG_SETTINGS_UBOOT */
|
||||
|
||||
#define PADCONFIG_SETTINGS_KERNEL_STUTTGART_B1 \
|
||||
/* UART1 lines */ \
|
||||
PC_DEFINE(CP(UART1_CTS), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0 | PC_OFF_OUT_LOW) /* GPS_RTS_SOC_CTS */ \
|
||||
PC_DEFINE(CP(UART1_RTS), PC_INPUT | PC_PULL_ENA | PC_PULL_UP | PC_MODE0 | PC_OFF_OUT_LOW) /* GPS_CTS_SOC_RTS */ \
|
||||
PC_DEFINE(CP(UART1_RX), PC_INPUT | PC_PULL_ENA | PC_PULL_UP | PC_MODE0 | PC_OFF_OUT_LOW) /* GPS_TX_SOC_RX */ \
|
||||
PC_DEFINE(CP(UART1_TX), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0 | PC_OFF_OUT_LOW) /* GPS_RX_SOC_TX */ \
|
||||
\
|
||||
/* UART2 lines */ \
|
||||
PC_DEFINE(CP(MCBSP3_CLKX), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE1 | PC_OFF_OUT_LOW) /* BT_RX */ \
|
||||
PC_DEFINE(CP(MCBSP3_FSX), PC_INPUT | PC_PULL_ENA | PC_PULL_UP | PC_MODE1 | PC_OFF_OUT_LOW) /* BT_TX */ \
|
||||
\
|
||||
/* SDARS lines */ \
|
||||
PC_DEFINE(CP(ETK_D8), PC_INPUT | PC_PULL_ENA | PC_PULL_UP | PC_MODE4 | PC_OFF_OUT_HIGH) /* nTUN_PWREN_UB */ \
|
||||
\
|
||||
/* MCBSP1 lines */ \
|
||||
PC_DEFINE(CP(MCBSP1_CLKX), PC_INPUT | PC_PULL_ENA | PC_PULL_DOWN | PC_MODE0 | PC_OFF_OUT_LOW) /* BT_PCM_CLK */ \
|
||||
PC_DEFINE(CP(MCBSP1_DR), PC_INPUT | PC_PULL_ENA | PC_PULL_DOWN | PC_MODE0 | PC_OFF_OUT_LOW) /* BT_PCM_OUT */ \
|
||||
PC_DEFINE(CP(MCBSP1_DX), PC_OUTPUT | PC_PULL_ENA | PC_PULL_DOWN | PC_MODE0 | PC_OFF_OUT_LOW) /* BT_PCM_IN */ \
|
||||
PC_DEFINE(CP(MCBSP1_FSX), PC_INPUT | PC_PULL_ENA | PC_PULL_DOWN | PC_MODE0 | PC_OFF_OUT_LOW) /* BT_PCM_SYNC */ \
|
||||
\
|
||||
/* USB1 lines */ \
|
||||
PC_DEFINE(CP(ETK_D0), PC_INPUT | PC_PULL_ENA | PC_PULL_DOWN | PC_MODE4) /* MM1_RXRCV */ \
|
||||
PC_DEFINE(CP(ETK_D1), PC_INPUT | PC_PULL_ENA | PC_PULL_DOWN | PC_MODE4) /* MM1_TXSE0 */ \
|
||||
PC_DEFINE(CP(ETK_D2), PC_INPUT | PC_PULL_ENA | PC_PULL_DOWN | PC_MODE4) /* MM1_TXDAT */ \
|
||||
PC_DEFINE(CP(ETK_D7), PC_INPUT | PC_PULL_ENA | PC_PULL_DOWN | PC_MODE4 | PC_OFF_OUT_LOW) /* MM1_TXEN */ \
|
||||
PC_DEFINE(CP(MCBSP3_DR), PC_OUTPUT | PC_PULL_ENA | PC_PULL_DOWN | PC_MODE4) /* USB1_SPEED */ \
|
||||
PC_DEFINE(CP(MCBSP3_DX), PC_INPUT | PC_PULL_ENA | PC_PULL_UP | PC_MODE4 | PC_OFF_OUT_HIGH) /* USB1_SUSPEND */ \
|
||||
\
|
||||
/* USB2 lines - TI CSR ticket OMAPS00262728: HSUSB2_DATA2 and HSUSB2_DATA6 */ \
|
||||
PC_DEFINE(CP(MCSPI1_CS3), PC_INPUT | PC_PULL_ENA | PC_PULL_DOWN | PC_MODE4) /* HSUSB2_DATA2 */ \
|
||||
PC_DEFINE(CP(MCSPI2_CS0), PC_INPUT | PC_PULL_ENA | PC_PULL_DOWN | PC_MODE4) /* HSUSB2_DATA6 */ \
|
||||
\
|
||||
/* LCD lines */ \
|
||||
PC_DEFINE(CP(DSS_ACBIAS), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0 | PC_OFF_OUT_LOW) /* LCD_DAT_EN */ \
|
||||
PC_DEFINE(CP(DSS_DATA0), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0 | PC_OFF_OUT_LOW) /* LCD_D0 */ \
|
||||
PC_DEFINE(CP(DSS_DATA1), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0 | PC_OFF_OUT_LOW) /* LCD_D1 */ \
|
||||
PC_DEFINE(CP(DSS_DATA2), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0 | PC_OFF_OUT_LOW) /* LCD_D2 */ \
|
||||
PC_DEFINE(CP(DSS_DATA3), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0 | PC_OFF_OUT_LOW) /* LCD_D3 */ \
|
||||
PC_DEFINE(CP(DSS_DATA4), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0 | PC_OFF_OUT_LOW) /* LCD_D4 */ \
|
||||
PC_DEFINE(CP(DSS_DATA5), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0 | PC_OFF_OUT_LOW) /* LCD_D5 */ \
|
||||
PC_DEFINE(CP(DSS_DATA6), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0 | PC_OFF_OUT_LOW) /* LCD_D6 */ \
|
||||
PC_DEFINE(CP(DSS_DATA7), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0 | PC_OFF_OUT_LOW) /* LCD_D7 */ \
|
||||
PC_DEFINE(CP(DSS_DATA8), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0 | PC_OFF_OUT_LOW) /* LCD_D8 */ \
|
||||
PC_DEFINE(CP(DSS_DATA9), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0 | PC_OFF_OUT_LOW) /* LCD_D9 */ \
|
||||
PC_DEFINE(CP(DSS_DATA10), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0 | PC_OFF_OUT_LOW) /* LCD_D10 */ \
|
||||
PC_DEFINE(CP(DSS_DATA11), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0 | PC_OFF_OUT_LOW) /* LCD_D11 */ \
|
||||
PC_DEFINE(CP(DSS_DATA12), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0 | PC_OFF_OUT_LOW) /* LCD_D12 */ \
|
||||
PC_DEFINE(CP(DSS_DATA13), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0 | PC_OFF_OUT_LOW) /* LCD_D13 */ \
|
||||
PC_DEFINE(CP(DSS_DATA14), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0 | PC_OFF_OUT_LOW) /* LCD_D14 */ \
|
||||
PC_DEFINE(CP(DSS_DATA15), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0 | PC_OFF_OUT_LOW) /* LCD_D15 */ \
|
||||
PC_DEFINE(CP(DSS_DATA16), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0 | PC_OFF_OUT_LOW) /* LCD_D16 */ \
|
||||
PC_DEFINE(CP(DSS_DATA17), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0 | PC_OFF_OUT_LOW) /* LCD_D17 */ \
|
||||
PC_DEFINE(CP(DSS_DATA18), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0 | PC_OFF_OUT_LOW) /* LCD_D18 */ \
|
||||
PC_DEFINE(CP(DSS_DATA19), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0 | PC_OFF_OUT_LOW) /* LCD_D19 */ \
|
||||
PC_DEFINE(CP(DSS_DATA20), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0 | PC_OFF_OUT_LOW) /* LCD_D20 */ \
|
||||
PC_DEFINE(CP(DSS_DATA21), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0 | PC_OFF_OUT_LOW) /* LCD_D21 */ \
|
||||
PC_DEFINE(CP(DSS_DATA22), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0 | PC_OFF_OUT_LOW) /* LCD_D22 */ \
|
||||
PC_DEFINE(CP(DSS_DATA23), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0 | PC_OFF_OUT_LOW) /* LCD_D23 */ \
|
||||
PC_DEFINE(CP(DSS_PCLK), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0 | PC_OFF_OUT_LOW) /* LCD_PCLK */ \
|
||||
\
|
||||
/* JTAG lines */ \
|
||||
PC_DEFINE(CP(JTAG_NTRST), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /* uP_nTRST */ \
|
||||
PC_DEFINE(CP(JTAG_TCK), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /* uP_TCK */ \
|
||||
PC_DEFINE(CP(JTAG_TMS_TMSC), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /* uP_nTMS */ \
|
||||
PC_DEFINE(CP(JTAG_RTCK), PC_INPUT | PC_PULL_ENA | PC_PULL_DOWN | PC_MODE0) /* uP_nRTCK */ \
|
||||
PC_DEFINE(CP(JTAG_NTRST), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /* uP_nTRST */ \
|
||||
PC_DEFINE(CP(JTAG_TDI), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /* uP_TDI */ \
|
||||
PC_DEFINE(CP(JTAG_TDO), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /* uP_TDO */ \
|
||||
\
|
||||
/* GPIO lines */ \
|
||||
PC_DEFINE(CP(CAM_WEN), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE4 | PC_OFF_OUT_LOW) /* GPS_CORE_PWR_EN */ \
|
||||
PC_DEFINE(CP(CAM_XCLKA), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE4 | PC_OFF_OUT_LOW) /* CAM_PWR_ON */ \
|
||||
PC_DEFINE(CP(SDMMC2_DAT1), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE4 | PC_OFF_OUT_LOW) /* nCAM_RST */ \
|
||||
PC_DEFINE(CP(GPMC_NBE0_CLE), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE4 | PC_OFF_OUT_LOW) /* nBT_RST */ \
|
||||
PC_DEFINE(CP(MCBSP_CLKS), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE4 | PC_OFF_OUT_LOW) /* nGPS_RESET */ \
|
||||
PC_DEFINE(CP(UART3_RTS_SD), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE4 | PC_OFF_OUT_LOW) /* GPS_HOST_REQ */ \
|
||||
PC_DEFINE(CP(GPIO126), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE4 | PC_OFF_OUT_LOW) /* nAUTH_RST */ \
|
||||
PC_DEFINE(CP(GPIO129), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE4 | PC_OFF_OUT_LOW) /* CAM_ON */ \
|
||||
PC_DEFINE(CP(GPMC_NBE1), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE4 | OMAP_PIN_OFF_OUTPUT_HIGH)/* PWR_HOLD */ \
|
||||
|
||||
#ifndef PADCONFIG_SETTINGS_KERNEL
|
||||
#define PADCONFIG_SETTINGS_KERNEL PADCONFIG_SETTINGS_KERNEL_STUTTGART_B1
|
||||
#endif /* PADCONFIG_SETTINGS_KERNEL */
|
||||
|
||||
#define PADCONFIG_SETTINGS_COMMON_STUTTGART_B1 \
|
||||
/* CAM lines */ \
|
||||
PC_DEFINE(CP(CAM_D0), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /* CAM_D0 */ \
|
||||
PC_DEFINE(CP(CAM_D1), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /* CAM_D1 */ \
|
||||
PC_DEFINE(CP(CAM_D2), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /* CAM_D2 */ \
|
||||
PC_DEFINE(CP(CAM_D3), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /* CAM_D3 */ \
|
||||
PC_DEFINE(CP(CAM_D4), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /* CAM_D4 */ \
|
||||
PC_DEFINE(CP(CAM_D5), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /* CAM_D5 */ \
|
||||
PC_DEFINE(CP(CAM_D6), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /* CAM_D6 */ \
|
||||
PC_DEFINE(CP(CAM_D7), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /* CAM_D7 */ \
|
||||
PC_DEFINE(CP(CAM_FLD), PC_INPUT | PC_PULL_ENA | PC_PULL_DOWN | PC_MODE0) /* CAM_FLD */ \
|
||||
PC_DEFINE(CP(CAM_HS), PC_INPUT | PC_PULL_ENA | PC_PULL_DOWN | PC_MODE0) /* CAM_HS */ \
|
||||
PC_DEFINE(CP(CAM_PCLK), PC_INPUT | PC_PULL_ENA | PC_PULL_DOWN | PC_MODE0) /* CAM_PCLK */ \
|
||||
PC_DEFINE(CP(CAM_VS), PC_INPUT | PC_PULL_ENA | PC_PULL_DOWN | PC_MODE0) /* CAM_VS */ \
|
||||
\
|
||||
/* GPMC lines */ \
|
||||
PC_DEFINE(CP(GPMC_A1), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /* GPMC_A1 */ \
|
||||
PC_DEFINE(CP(GPMC_A2), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /* GPMC_A2 */ \
|
||||
PC_DEFINE(CP(GPMC_A3), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /* GPMC_A3 */ \
|
||||
PC_DEFINE(CP(GPMC_A4), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /* GPMC_A4 */ \
|
||||
PC_DEFINE(CP(GPMC_A5), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /* GPMC_A5 */ \
|
||||
PC_DEFINE(CP(GPMC_A6), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /* GPMC_A6 */ \
|
||||
PC_DEFINE(CP(GPMC_CLK), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /* GPMC_CLK */ \
|
||||
PC_DEFINE(CP(GPMC_D0), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /* GPMC_D0 */ \
|
||||
PC_DEFINE(CP(GPMC_D1), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /* GPMC_D1 */ \
|
||||
PC_DEFINE(CP(GPMC_D2), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /* GPMC_D2 */ \
|
||||
PC_DEFINE(CP(GPMC_D3), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /* GPMC_D3 */ \
|
||||
PC_DEFINE(CP(GPMC_D4), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /* GPMC_D4 */ \
|
||||
PC_DEFINE(CP(GPMC_D5), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /* GPMC_D5 */ \
|
||||
PC_DEFINE(CP(GPMC_D6), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /* GPMC_D6 */ \
|
||||
PC_DEFINE(CP(GPMC_D7), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /* GPMC_D7 */ \
|
||||
PC_DEFINE(CP(GPMC_D8), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /* GPMC_D8 */ \
|
||||
PC_DEFINE(CP(GPMC_D9), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /* GPMC_D9 */ \
|
||||
PC_DEFINE(CP(GPMC_D10), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /* GPMC_D10 */ \
|
||||
PC_DEFINE(CP(GPMC_D11), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /* GPMC_D11 */ \
|
||||
PC_DEFINE(CP(GPMC_D12), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /* GPMC_D12 */ \
|
||||
PC_DEFINE(CP(GPMC_D13), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /* GPMC_D13 */ \
|
||||
PC_DEFINE(CP(GPMC_D14), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /* GPMC_D14 */ \
|
||||
PC_DEFINE(CP(GPMC_D15), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /* GPMC_D15 */ \
|
||||
PC_DEFINE(CP(GPMC_NWP), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /* GPMC_nWP */ \
|
||||
PC_DEFINE(CP(GPMC_NCS0), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /* GPMC_nCS0 */ \
|
||||
PC_DEFINE(CP(GPMC_NCS1), PC_INPUT | PC_PULL_ENA | PC_PULL_DOWN | PC_MODE4) /* GPMC_nCS1 */ \
|
||||
PC_DEFINE(CP(GPMC_NCS2), PC_INPUT | PC_PULL_ENA | PC_PULL_DOWN | PC_MODE4) /* GPMC_nCS2 */ \
|
||||
PC_DEFINE(CP(GPMC_NOE), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /* GPMC_nOE */ \
|
||||
PC_DEFINE(CP(GPMC_NADV_ALE), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /* GPMC_nADV_ALE */ \
|
||||
PC_DEFINE(CP(GPMC_NWE), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /* GPMC_nWE */ \
|
||||
\
|
||||
/* MCBSP4 lines */ \
|
||||
PC_DEFINE(CP(GPMC_NCS4), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE2 | PC_OFF_OUT_LOW) /* MCBSP4_CLK */ \
|
||||
PC_DEFINE(CP(GPMC_NCS6), PC_OUTPUT | PC_PULL_ENA | PC_PULL_DOWN | PC_MODE2 | PC_OFF_OUT_LOW) /* MCBSP4_DX */ \
|
||||
PC_DEFINE(CP(GPMC_NCS7), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE2 | PC_OFF_OUT_LOW) /* MCBSP4_FSX */ \
|
||||
\
|
||||
/* I2C lines */ \
|
||||
PC_DEFINE(CP(I2C2_SCL), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) \
|
||||
PC_DEFINE(CP(I2C2_SDA), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) \
|
||||
PC_DEFINE(CP(I2C3_SCL), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) \
|
||||
PC_DEFINE(CP(I2C3_SDA), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) \
|
||||
PC_DEFINE(CP(I2C4_SCL), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE7) \
|
||||
PC_DEFINE(CP(I2C4_SDA), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE7) \
|
||||
PC_DEFINE(CP(I2C1_SCL), PC_INPUT | PC_PULL_ENA | PC_PULL_UP | PC_MODE0) \
|
||||
PC_DEFINE(CP(I2C1_SDA), PC_INPUT | PC_PULL_ENA | PC_PULL_UP | PC_MODE0) \
|
||||
\
|
||||
/* MCBSP2 lines */ \
|
||||
PC_DEFINE(CP(MCBSP2_CLKX), PC_INPUT | PC_PULL_ENA | PC_PULL_DOWN | PC_MODE0 | PC_OFF_IN_NOPULL) /* MCBSP2_CLK */ \
|
||||
PC_DEFINE(CP(MCBSP2_DR), PC_INPUT | PC_PULL_ENA | PC_PULL_DOWN | PC_MODE0 | PC_OFF_IN_NOPULL) /* MCBSP2_DR */ \
|
||||
PC_DEFINE(CP(MCBSP2_DX), PC_OUTPUT | PC_PULL_ENA | PC_PULL_DOWN | PC_MODE0 | PC_OFF_OUT_LOW) /* MCBSP2_DX */ \
|
||||
PC_DEFINE(CP(MCBSP2_FSX), PC_INPUT | PC_PULL_ENA | PC_PULL_DOWN | PC_MODE0 | PC_OFF_IN_NOPULL) /* MCBSP2_FSX */ \
|
||||
\
|
||||
/* MCSPI1 lines */ \
|
||||
PC_DEFINE(CP(MCSPI1_CLK), PC_INPUT | PC_PULL_ENA | PC_PULL_DOWN | PC_MODE0 | PC_OFF_IN_PULLDOWN) /* SPI_CAN_CLK */ \
|
||||
PC_DEFINE(CP(MCSPI1_SIMO), PC_INPUT | PC_PULL_ENA | PC_PULL_DOWN | PC_MODE0 | PC_OFF_IN_PULLDOWN) /* SPI_CAN_SIMO */ \
|
||||
PC_DEFINE(CP(MCSPI1_SOMI), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0 | PC_OFF_IN_PULLDOWN) /* SPI_CAN_SOMI */ \
|
||||
PC_DEFINE(CP(MCSPI1_CS0), PC_INPUT | PC_PULL_ENA | PC_PULL_DOWN | PC_MODE0 | PC_OFF_IN_PULLDOWN) /* SPI_CAN_CS0 */ \
|
||||
\
|
||||
/* SYS lines */ \
|
||||
PC_DEFINE(CP(SYS_BOOT0), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /* SYS_BOOT0 */ \
|
||||
PC_DEFINE(CP(SYS_BOOT1), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /* SYS_BOOT1 */ \
|
||||
PC_DEFINE(CP(SYS_BOOT2), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /* SYS_BOOT2 */ \
|
||||
PC_DEFINE(CP(SYS_BOOT3), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /* SYS_BOOT3 */ \
|
||||
PC_DEFINE(CP(SYS_BOOT4), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /* SYS_BOOT4 */ \
|
||||
PC_DEFINE(CP(SYS_BOOT5), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /* SYS_BOOT5 */ \
|
||||
PC_DEFINE(CP(SYS_BOOT6), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /* SYS_BOOT6 */ \
|
||||
PC_DEFINE(CP(SYS_CLKREQ), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /* SYS_CLKREQ */ \
|
||||
PC_DEFINE(CP(SYS_NIRQ), PC_INPUT | PC_PULL_ENA | PC_PULL_UP | PC_MODE0 | PC_WAKEUP_EN) /* SYS_NIRQ */ \
|
||||
PC_DEFINE(CP(SYS_NRESWARM), PC_INPUT | PC_PULL_ENA | PC_PULL_UP | PC_MODE0) /* SYS_NRESWARM */ \
|
||||
PC_DEFINE(CP(SYS_OFF_MODE), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0) /* SYS_OFF_MODE */ \
|
||||
\
|
||||
/* UART3 lines */ \
|
||||
PC_DEFINE(CP(UART3_RX_IRRX), PC_INPUT | PC_PULL_ENA | PC_PULL_UP | PC_MODE0 | PC_OFF_IN_PULLDOWN) /* DEBUG_RX */ \
|
||||
PC_DEFINE(CP(UART3_TX_IRTX), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE0 | PC_OFF_OUT_LOW) /* DEBUG_TX */ \
|
||||
\
|
||||
/* BACKLIGHT lines */ \
|
||||
PC_DEFINE(CP(GPMC_NCS5), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE3 | PC_OFF_IN_NOPULL) /* BACKLIGHT_PWM */ \
|
||||
PC_DEFINE(CP(GPMC_WAIT3), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE4 | PC_OFF_OUT_LOW) /* BACKLIGHT_ON */ \
|
||||
\
|
||||
/* nACCEL_IRQ and nGYRO_IRQ lines */ \
|
||||
PC_DEFINE(CP(ETK_D5), PC_INPUT | PC_PULL_ENA | PC_PULL_DOWN | PC_MODE4 | PC_OFF_OUT_LOW) /* nGYRO_IRQ */ \
|
||||
PC_DEFINE(CP(CAM_D10), PC_INPUT | PC_PULL_ENA | PC_PULL_DOWN | PC_MODE4 | PC_OFF_OUT_LOW) /* nACCEL_IRQ */ \
|
||||
\
|
||||
/* Unused lines set as GPIOs */ \
|
||||
PC_DEFINE(CP(UART2_CTS), PC_INPUT | PC_PULL_ENA | PC_PULL_DOWN | PC_MODE4) /* UART_CTS as GPIO */ \
|
||||
PC_DEFINE(CP(UART2_RTS), PC_INPUT | PC_PULL_ENA | PC_PULL_DOWN | PC_MODE4) /* UART_RTS as GPIO */ \
|
||||
PC_DEFINE(CP(UART2_RX), PC_INPUT | PC_PULL_ENA | PC_PULL_DOWN | PC_MODE4) /* UART_RX as GPIO */ \
|
||||
PC_DEFINE(CP(UART2_TX), PC_INPUT | PC_PULL_ENA | PC_PULL_DOWN | PC_MODE4) /* UART_TX as GPIO */ \
|
||||
PC_DEFINE(CP(GPMC_A7), PC_INPUT | PC_PULL_ENA | PC_PULL_DOWN | PC_MODE4) /* GPMC_A7 as GPIO */ \
|
||||
PC_DEFINE(CP(GPMC_A10), PC_INPUT | PC_PULL_ENA | PC_PULL_DOWN | PC_MODE4) /* GPMC_A10 as GPIO */ \
|
||||
PC_DEFINE(CP(SDMMC2_CLK), PC_INPUT | PC_PULL_ENA | PC_PULL_DOWN | PC_MODE4 | PC_OFF_OUT_LOW) /* MCSPI3_CLK */ \
|
||||
PC_DEFINE(CP(SDMMC2_CMD), PC_INPUT | PC_PULL_ENA | PC_PULL_DOWN | PC_MODE4 | PC_OFF_OUT_LOW) /* MCSPI3_SIMO */ \
|
||||
PC_DEFINE(CP(SDMMC2_DAT0), PC_INPUT | PC_PULL_ENA | PC_PULL_DOWN | PC_MODE4 | PC_OFF_OUT_LOW) /* MCSPI3_SOMI */ \
|
||||
PC_DEFINE(CP(SDMMC2_DAT2), PC_INPUT | PC_PULL_ENA | PC_PULL_DOWN | PC_MODE4) /* SDMMC2_DAT2 as GPIO */\
|
||||
PC_DEFINE(CP(SDMMC2_DAT3), PC_INPUT | PC_PULL_ENA | PC_PULL_DOWN | PC_MODE4 | PC_OFF_OUT_LOW) /* MCSPI3_CS0 */ \
|
||||
PC_DEFINE(CP(SDMMC2_DAT6), PC_INPUT | PC_PULL_ENA | PC_PULL_DOWN | PC_MODE4) /* SDMMC2_DAT6 as GPIO */\
|
||||
PC_DEFINE(CP(CAM_STROBE), PC_INPUT | PC_PULL_ENA | PC_PULL_DOWN | PC_MODE4) /* CAM_STROBE as GPIO */\
|
||||
PC_DEFINE(CP(DSS_HSYNC), PC_INPUT | PC_PULL_ENA | PC_PULL_DOWN | PC_MODE4) /* LCD_HSYNC as GPIO */ \
|
||||
PC_DEFINE(CP(DSS_VSYNC), PC_INPUT | PC_PULL_ENA | PC_PULL_DOWN | PC_MODE4) /* LCD_VSYNC as GPIO */ \
|
||||
PC_DEFINE(CP(ETK_CTL), PC_INPUT | PC_PULL_ENA | PC_PULL_DOWN | PC_MODE4) /* ETK_CTL as GPIO */ \
|
||||
PC_DEFINE(CP(ETK_D4), PC_INPUT | PC_PULL_ENA | PC_PULL_DOWN | PC_MODE4) /* ETK_D4 as GPIO */ \
|
||||
PC_DEFINE(CP(ETK_D6), PC_INPUT | PC_PULL_ENA | PC_PULL_DOWN | PC_MODE4) /* ETK_D6 as GPIO */ \
|
||||
PC_DEFINE(CP(ETK_D9), PC_INPUT | PC_PULL_ENA | PC_PULL_DOWN | PC_MODE4) /* ETK_D9 as GPIO */ \
|
||||
PC_DEFINE(CP(MCBSP4_CLKX), PC_INPUT | PC_PULL_ENA | PC_PULL_DOWN | PC_MODE4) /* MCBSP4_CLKX as GPIO */\
|
||||
PC_DEFINE(CP(MCBSP4_DR), PC_INPUT | PC_PULL_ENA | PC_PULL_DOWN | PC_MODE4) /* MCBSP4_DR as GPIO */ \
|
||||
PC_DEFINE(CP(MCBSP4_DX), PC_INPUT | PC_PULL_ENA | PC_PULL_DOWN | PC_MODE4 | PC_OFF_OUT_LOW) /* MCBSP4_DX as GPIO */ \
|
||||
PC_DEFINE(CP(MCBSP4_FSX), PC_INPUT | PC_PULL_ENA | PC_PULL_DOWN | PC_MODE4 | PC_OFF_OUT_LOW) /* MCBSP4_FSX as GPIO */ \
|
||||
PC_DEFINE(CP(MCSPI1_CS1), PC_INPUT | PC_PULL_ENA | PC_PULL_DOWN | PC_MODE4) /* MCSPI1_CS1 as GPIO */ \
|
||||
PC_DEFINE(CP(MCSPI1_CS2), PC_INPUT | PC_PULL_ENA | PC_PULL_DOWN | PC_MODE4) /* MCSPI1_CS2 as GPIO */ \
|
||||
PC_DEFINE(CP(GPMC_NCS1), PC_INPUT | PC_PULL_ENA | PC_PULL_DOWN | PC_MODE4) /* GPMC_nCS1 as GPIO */ \
|
||||
PC_DEFINE(CP(GPMC_NCS2), PC_INPUT | PC_PULL_ENA | PC_PULL_DOWN | PC_MODE4) /* GPMC_nCS2 as GPIO */ \
|
||||
PC_DEFINE(CP(GPMC_WAIT1), PC_INPUT | PC_PULL_ENA | PC_PULL_DOWN | PC_MODE4) /* GPMC_WAIT1 as GPIO */ \
|
||||
PC_DEFINE(CP(GPMC_WAIT2), PC_INPUT | PC_PULL_ENA | PC_PULL_DOWN | PC_MODE4) /* GPMC_WAIT2 as GPIO */ \
|
||||
PC_DEFINE(CP(CSI2_DX0), PC_INPUT | PC_PULL_ENA | PC_PULL_DOWN | PC_MODE4) /* CSI2_DX0 as GPIO */ \
|
||||
PC_DEFINE(CP(CSI2_DY0), PC_INPUT | PC_PULL_ENA | PC_PULL_DOWN | PC_MODE4) /* CSI2_DY0 as GPIO */ \
|
||||
PC_DEFINE(CP(CSI2_DX1), PC_INPUT | PC_PULL_ENA | PC_PULL_DOWN | PC_MODE4) /* CSI2_DX1 as GPIO */ \
|
||||
PC_DEFINE(CP(CSI2_DY1), PC_INPUT | PC_PULL_ENA | PC_PULL_DOWN | PC_MODE4) /* CSI2_DY1 as GPIO */ \
|
||||
\
|
||||
/* GPIO lines */ \
|
||||
PC_DEFINE(CP(CAM_D8), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE4 | PC_OFF_IN_PULLDOWN) /* nCAM_IRQ */ \
|
||||
PC_DEFINE(CP(CAM_D9), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE4) /* nGPS_ANT_SHORT */ \
|
||||
PC_DEFINE(CP(CAM_D11), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE4 | PC_OFF_OUT_LOW) /* nUSB2_RESET */ \
|
||||
PC_DEFINE(CP(CAM_XCLKB), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE4 | PC_OFF_OUT_LOW) /* MIC_ON */ \
|
||||
PC_DEFINE(CP(SDMMC2_DAT4), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE4 | PC_OFF_OUT_LOW) /* nCAN_RST */ \
|
||||
PC_DEFINE(CP(SDMMC2_DAT5), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE4 | PC_OFF_OUT_LOW) /* LCM_PWR_ON */ \
|
||||
PC_DEFINE(CP(SDMMC2_DAT7), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE4 | PC_OFF_OUT_LOW) /* nCAN_IRQ */ \
|
||||
PC_DEFINE(CP(GPMC_A8), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE4 | PC_OFF_IN_NOPULL) /* nDIAGSYS_BOOT */ \
|
||||
PC_DEFINE(CP(GPMC_A9), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE4 | PC_OFF_OUT_LOW) /* GPS_1PPS */ \
|
||||
PC_DEFINE(CP(GPMC_NCS3), PC_INPUT | PC_PULL_DIS | PC_PULL_UP | PC_MODE4 | PC_OFF_OUT_LOW) /* nTP_IRQ */ \
|
||||
PC_DEFINE(CP(HDQ_SIO), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE4 | PC_OFF_IN_PULLDOWN) /* CAN_RST_MON */ \
|
||||
PC_DEFINE(CP(JTAG_EMU0), PC_INPUT | PC_PULL_ENA | PC_PULL_UP | PC_MODE4 | PC_OFF_IN_NOPULL) /* nUSB3_POWER_FAULT */\
|
||||
PC_DEFINE(CP(JTAG_EMU1), PC_INPUT | PC_PULL_ENA | PC_PULL_UP | PC_MODE4 | PC_OFF_IN_NOPULL) /* nUSB1_POWER_FAULT */\
|
||||
PC_DEFINE(CP(MCBSP1_CLKR), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE4 | PC_OFF_OUT_LOW) /* nLCD_RESET */ \
|
||||
PC_DEFINE(CP(MCBSP1_FSR), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE4 | PC_OFF_OUT_LOW) /* nTP_RESET */ \
|
||||
PC_DEFINE(CP(SYS_CLKOUT1), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE4) /* nON_OFF */ \
|
||||
PC_DEFINE(CP(SYS_CLKOUT2), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE4 | PC_OFF_OUT_LOW) /* CAN_BT_MD */ \
|
||||
PC_DEFINE(CP(UART3_CTS_RCTX),PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE4 | PC_OFF_OUT_LOW) /* CAN_SYNC */ \
|
||||
PC_DEFINE(CP(ETK_CLK), PC_OUTPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE4) /* LCD_UD */ \
|
||||
PC_DEFINE(CP(ETK_D3), PC_INPUT | PC_PULL_DIS | PC_PULL_DOWN | PC_MODE4 | PC_OFF_OUT_LOW) /* SENSE_11V0 */ \
|
||||
|
||||
#ifndef PADCONFIG_SETTINGS_COMMON
|
||||
#define PADCONFIG_SETTINGS_COMMON PADCONFIG_SETTINGS_COMMON_STUTTGART_B1
|
||||
#endif /* PADCONFIG_SETTINGS_COMMON */
|
||||
|
||||
#endif // PADCONFIG_STUTTGART_B1_H
|
||||
|
||||
338
lib_arm/board.c
338
lib_arm/board.c
@ -43,7 +43,33 @@
|
||||
#include <malloc.h>
|
||||
#include <devices.h>
|
||||
#include <version.h>
|
||||
#if defined(CONFIG_CMD_NET)
|
||||
#include <net.h>
|
||||
#endif
|
||||
#include <asm/io.h>
|
||||
#if defined(CONFIG_SMDK6410) || defined(CONFIG_SMDK6430) || defined(CONFIG_SMDK6440) ||\
|
||||
defined(CONFIG_SEOUL) || defined(CONFIG_LIMA) || defined(CONFIG_VENICE)||\
|
||||
defined(CONFIG_HAVANA) || defined(CONFIG_CORDOBA) || defined(CONFIG_CATANIA_S)
|
||||
#include <movi.h>
|
||||
#include <regs.h>
|
||||
#elif defined(CONFIG_SMDK6450) || defined(CONFIG_VALDEZ)
|
||||
#include <mmc.h>
|
||||
#endif
|
||||
#include <serial.h>
|
||||
|
||||
#ifdef CONFIG_TT_HEADER
|
||||
# include <tt_header.h>
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_CMD_NAND
|
||||
#include <nand.h>
|
||||
#endif
|
||||
#ifdef CONFIG_CMD_ONENAND
|
||||
#include <onenand_uboot.h>
|
||||
#endif
|
||||
|
||||
|
||||
#undef DEBUG
|
||||
|
||||
#ifdef CONFIG_DRIVER_SMC91111
|
||||
#include "../drivers/smc91111.h"
|
||||
@ -54,25 +80,8 @@
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
#if (CONFIG_COMMANDS & CFG_CMD_NAND)
|
||||
#ifdef ENV_IS_VARIABLE
|
||||
extern u8 is_nand;
|
||||
#endif
|
||||
void nand_init (void);
|
||||
#endif
|
||||
|
||||
#if (CONFIG_COMMANDS & CFG_CMD_FLASH)
|
||||
#ifdef ENV_IS_VARIABLE
|
||||
extern u8 is_flash;
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#if (CONFIG_COMMANDS & CFG_CMD_ONENAND)
|
||||
#ifdef ENV_IS_VARIABLE
|
||||
extern u8 is_onenand;
|
||||
#endif
|
||||
void onenand_init(void);
|
||||
#endif
|
||||
|
||||
ulong monitor_flash_len;
|
||||
|
||||
@ -93,14 +102,17 @@ const char version_string[] =
|
||||
U_BOOT_VERSION" (" __DATE__ " - " __TIME__ ")"CONFIG_IDENT_STRING;
|
||||
|
||||
#ifdef CONFIG_DRIVER_CS8900
|
||||
extern void cs8900_get_enetaddr (uchar * addr);
|
||||
extern int cs8900_get_enetaddr (uchar * addr);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_DRIVER_RTL8019
|
||||
extern void rtl8019_get_enetaddr (uchar * addr);
|
||||
#endif
|
||||
|
||||
extern void tomtom_env_init(void);
|
||||
#if defined(CONFIG_HARD_I2C) || \
|
||||
defined(CONFIG_SOFT_I2C)
|
||||
#include <i2c.h>
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Begin and End of memory area for malloc(), and current "brk"
|
||||
@ -109,8 +121,7 @@ static ulong mem_malloc_start = 0;
|
||||
static ulong mem_malloc_end = 0;
|
||||
static ulong mem_malloc_brk = 0;
|
||||
|
||||
static
|
||||
void mem_malloc_init (ulong dest_addr)
|
||||
static void mem_malloc_init (ulong dest_addr)
|
||||
{
|
||||
mem_malloc_start = dest_addr;
|
||||
mem_malloc_end = dest_addr + CFG_MALLOC_LEN;
|
||||
@ -133,6 +144,40 @@ void *sbrk (ptrdiff_t increment)
|
||||
return ((void *) old);
|
||||
}
|
||||
|
||||
char *strmhz(char *buf, long hz)
|
||||
{
|
||||
long l, n;
|
||||
long m;
|
||||
|
||||
n = hz / 1000000L;
|
||||
l = sprintf (buf, "%ld", n);
|
||||
m = (hz % 1000000L) / 1000L;
|
||||
if (m != 0)
|
||||
sprintf (buf + l, ".%03ld", m);
|
||||
return (buf);
|
||||
}
|
||||
|
||||
|
||||
/************************************************************************
|
||||
* Coloured LED functionality
|
||||
************************************************************************
|
||||
* May be supplied by boards if desired
|
||||
*/
|
||||
void inline __coloured_LED_init (void) {}
|
||||
void inline coloured_LED_init (void) __attribute__((weak, alias("__coloured_LED_init")));
|
||||
void inline __red_LED_on (void) {}
|
||||
void inline red_LED_on (void) __attribute__((weak, alias("__red_LED_on")));
|
||||
void inline __red_LED_off(void) {}
|
||||
void inline red_LED_off(void) __attribute__((weak, alias("__red_LED_off")));
|
||||
void inline __green_LED_on(void) {}
|
||||
void inline green_LED_on(void) __attribute__((weak, alias("__green_LED_on")));
|
||||
void inline __green_LED_off(void) {}
|
||||
void inline green_LED_off(void)__attribute__((weak, alias("__green_LED_off")));
|
||||
void inline __yellow_LED_on(void) {}
|
||||
void inline yellow_LED_on(void)__attribute__((weak, alias("__yellow_LED_on")));
|
||||
void inline __yellow_LED_off(void) {}
|
||||
void inline yellow_LED_off(void)__attribute__((weak, alias("__yellow_LED_off")));
|
||||
|
||||
/************************************************************************
|
||||
* Init Utilities *
|
||||
************************************************************************
|
||||
@ -155,8 +200,14 @@ static int init_baudrate (void)
|
||||
static int display_banner (void)
|
||||
{
|
||||
printf ("\n\n%s\n\n", version_string);
|
||||
|
||||
debug ("U-Boot code: %08lX -> %08lX BSS: -> %08lX\n",
|
||||
_armboot_start, _bss_start, _bss_end);
|
||||
#ifdef CONFIG_MEMORY_UPPER_CODE /* by scsuh */
|
||||
debug("\t\bMalloc and Stack is above the U-Boot Code.\n");
|
||||
#else
|
||||
debug("\t\bMalloc and Stack is below the U-Boot Code.\n");
|
||||
#endif
|
||||
#ifdef CONFIG_MODEM_SUPPORT
|
||||
debug ("Modem Support enabled\n");
|
||||
#endif
|
||||
@ -192,6 +243,7 @@ static int display_dram_config (void)
|
||||
for (i=0; i<CONFIG_NR_DRAM_BANKS; i++) {
|
||||
size += gd->bd->bi_dram[i].size;
|
||||
}
|
||||
|
||||
puts("DRAM: ");
|
||||
print_size(size, "\n");
|
||||
#endif
|
||||
@ -207,6 +259,27 @@ static void display_flash_config (ulong size)
|
||||
}
|
||||
#endif /* CFG_NO_FLASH */
|
||||
|
||||
#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SOFT_I2C)
|
||||
static int init_func_i2c (void)
|
||||
{
|
||||
puts ("I2C: ");
|
||||
i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE);
|
||||
puts ("ready\n");
|
||||
return (0);
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SKIP_RELOCATE_UBOOT
|
||||
/*
|
||||
* This routine sets the relocation done flag, because even if
|
||||
* relocation is skipped, the flag is used by other generic code.
|
||||
*/
|
||||
static int reloc_init(void)
|
||||
{
|
||||
gd->flags |= GD_FLG_RELOC;
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Breathe some life into the board...
|
||||
@ -237,6 +310,11 @@ int print_cpuinfo (void); /* test-only */
|
||||
|
||||
init_fnc_t *init_sequence[] = {
|
||||
cpu_init, /* basic cpu dependent setup */
|
||||
#if defined(CONFIG_SKIP_RELOCATE_UBOOT)
|
||||
reloc_init, /* Set the relocation done flag, must
|
||||
do this AFTER cpu_init(), but as soon
|
||||
as possible */
|
||||
#endif
|
||||
board_init, /* basic board dependent setup */
|
||||
interrupt_init, /* set up exceptions */
|
||||
env_init, /* initialize environment */
|
||||
@ -249,9 +327,15 @@ init_fnc_t *init_sequence[] = {
|
||||
#endif
|
||||
#if defined(CONFIG_DISPLAY_BOARDINFO)
|
||||
checkboard, /* display board info */
|
||||
#endif
|
||||
#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SOFT_I2C)
|
||||
init_func_i2c,
|
||||
#endif
|
||||
dram_init, /* configure available RAM banks */
|
||||
display_dram_config,
|
||||
#if defined(CONFIG_TT_HEADER)
|
||||
check_bricknum, /* is this release allowed to run? */
|
||||
#endif
|
||||
NULL,
|
||||
};
|
||||
|
||||
@ -259,15 +343,35 @@ void start_armboot (void)
|
||||
{
|
||||
init_fnc_t **init_fnc_ptr;
|
||||
char *s;
|
||||
#ifndef CFG_NO_FLASH
|
||||
ulong size = 0;
|
||||
#if !defined(CFG_NO_FLASH) || defined (CONFIG_VFD) || defined(CONFIG_LCD)
|
||||
ulong size;
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_VFD) || defined(CONFIG_LCD)
|
||||
unsigned long addr;
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_BOOT_MOVINAND)
|
||||
uint *magic = (uint *) (PHYS_SDRAM_1);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_S3C_MMC_BOOT
|
||||
clear_bss();
|
||||
#endif
|
||||
|
||||
/* Pointer is writable since we allocated a register for it */
|
||||
#ifdef CONFIG_MEMORY_UPPER_CODE /* by scsuh */
|
||||
ulong gd_base;
|
||||
|
||||
gd_base = CFG_UBOOT_BASE + CFG_UBOOT_SIZE - CFG_MALLOC_LEN - CFG_STACK_SIZE - sizeof(gd_t);
|
||||
#ifdef CONFIG_USE_IRQ
|
||||
gd_base -= (CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ);
|
||||
#endif
|
||||
gd = (gd_t*)gd_base;
|
||||
#else
|
||||
gd = (gd_t*)(_armboot_start - CFG_MALLOC_LEN - sizeof(gd_t));
|
||||
#endif
|
||||
|
||||
/* compiler optimization barrier needed for GCC >= 3.4 */
|
||||
__asm__ __volatile__("": : :"memory");
|
||||
|
||||
@ -275,6 +379,8 @@ void start_armboot (void)
|
||||
gd->bd = (bd_t*)((char*)gd - sizeof(bd_t));
|
||||
memset (gd->bd, 0, sizeof (bd_t));
|
||||
|
||||
gd->flags |= GD_FLG_RELOC;
|
||||
|
||||
monitor_flash_len = _bss_start - _armboot_start;
|
||||
|
||||
for (init_fnc_ptr = init_sequence; *init_fnc_ptr; ++init_fnc_ptr) {
|
||||
@ -285,9 +391,6 @@ void start_armboot (void)
|
||||
|
||||
#ifndef CFG_NO_FLASH
|
||||
/* configure available FLASH banks */
|
||||
#ifdef ENV_IS_VARIABLE
|
||||
if (is_flash)
|
||||
#endif
|
||||
size = flash_init ();
|
||||
display_flash_config (size);
|
||||
#endif /* CFG_NO_FLASH */
|
||||
@ -306,6 +409,8 @@ void start_armboot (void)
|
||||
#endif /* CONFIG_VFD */
|
||||
|
||||
#ifdef CONFIG_LCD
|
||||
/* board init may have inited fb_base */
|
||||
if (!gd->fb_base) {
|
||||
# ifndef PAGE_SIZE
|
||||
# define PAGE_SIZE 4096
|
||||
# endif
|
||||
@ -316,26 +421,152 @@ void start_armboot (void)
|
||||
addr = (_bss_end + (PAGE_SIZE - 1)) & ~(PAGE_SIZE - 1);
|
||||
size = lcd_setmem (addr);
|
||||
gd->fb_base = addr;
|
||||
}
|
||||
#endif /* CONFIG_LCD */
|
||||
|
||||
/* armboot_start is defined in the board-specific linker script */
|
||||
#ifdef CONFIG_MEMORY_UPPER_CODE /* by scsuh */
|
||||
mem_malloc_init (CFG_UBOOT_BASE + CFG_UBOOT_SIZE - CFG_MALLOC_LEN - CFG_STACK_SIZE);
|
||||
#else
|
||||
mem_malloc_init (_armboot_start - CFG_MALLOC_LEN);
|
||||
|
||||
#if (CONFIG_COMMANDS & CFG_CMD_NAND)
|
||||
#ifdef ENV_IS_VARIABLE
|
||||
if (is_nand)
|
||||
#endif
|
||||
|
||||
/* samsung socs: auto-detect devices */
|
||||
#if defined(CONFIG_SMDK6410) || defined(CONFIG_SMDK6430) || defined(CONFIG_SMDKC100) ||\
|
||||
defined(CONFIG_SEOUL) || defined(CONFIG_LIMA) || defined(CONFIG_VENICE)
|
||||
|
||||
#if defined(CONFIG_MMC)
|
||||
#if 0 /* TODO ? (not required for PND??) */
|
||||
#if defined(CONFIG_S3C_MMC_BL0)
|
||||
/* Use S3C64xx BL0 gathered information to set INF_REG3_REG */
|
||||
/* refer to location of global variable set by S3C64xx IROM (BL0, from IROM spec)*/
|
||||
#define S3C6400_IROM_HSMMC_BASE_ADDR (* (unsigned int*) (((void *)0) + (TCM_BASE-0x14)))
|
||||
|
||||
if (S3C6400_IROM_HSMMC_BASE_ADDR == ELFIN_HSMMC_0_BASE)
|
||||
{
|
||||
/* booted from mmc ch0 */
|
||||
INF_REG3_REG = 0;
|
||||
}
|
||||
else if (S3C6400_IROM_HSMMC_BASE_ADDR == ELFIN_HSMMC_1_BASE)
|
||||
{
|
||||
/* booted from mmc ch1 */
|
||||
INF_REG3_REG = 7;
|
||||
}
|
||||
#endif /* defined(CONFIG_S3C_MMC_BL0) */
|
||||
#endif /* 0 */
|
||||
puts("SD/MMC: ");
|
||||
|
||||
#if !defined(CONFIG_SMDKC100)
|
||||
if (INF_REG3_REG == 0)
|
||||
movi_ch = 0;
|
||||
else
|
||||
movi_ch = 1;
|
||||
#else /* CONFIG_SMDKC100 */
|
||||
movi_ch = 0;
|
||||
#endif /* CONFIG_SMDKC100 */
|
||||
|
||||
movi_set_capacity();
|
||||
movi_set_ofs(MOVI_TOTAL_BLKCNT);
|
||||
movi_init();
|
||||
#endif
|
||||
|
||||
#if !defined(CONFIG_SEOUL) && !defined(CONFIG_LIMA) && !defined(CONFIG_VENICE)
|
||||
if (INF_REG3_REG == 1) {
|
||||
puts("OneNAND: ");
|
||||
onenand_init();
|
||||
/*setenv("bootcmd", "onenand read c0008000 80000 380000;bootm c0008000");*/
|
||||
} else {
|
||||
puts("NAND: ");
|
||||
nand_init(); /* go init the NAND */
|
||||
nand_init();
|
||||
|
||||
#if !defined(CONFIG_SMDKC100)
|
||||
if (INF_REG3_REG == 0 || INF_REG3_REG == 7)
|
||||
// setenv("bootcmd", "movi read kernel c0008000;movi read rootfs c0800000;bootm c0008000");
|
||||
setenv("bootcmd", CONFIG_BOOTCOMMAND);
|
||||
else
|
||||
setenv("bootcmd", "nand read c0008000 80000 380000;bootm c0008000");
|
||||
#endif /* CONFIG_SMDKC100 */
|
||||
}
|
||||
#endif /* CONFIG_SEOUL && CONFIG_LIMA && CONFIG_VENICE */
|
||||
|
||||
/* samsung socs: another auto-detect devices */
|
||||
#elif defined(CONFIG_SMDK6440) || defined(CONFIG_HAVANA) || defined(CONFIG_CORDOBA) || defined(CONFIG_CATANIA_S)
|
||||
|
||||
#if defined(CONFIG_MMC)
|
||||
if (INF_REG3_REG == 1) { /* eMMC_4.3 */
|
||||
puts("eMMC: ");
|
||||
movi_ch = 1;
|
||||
movi_emmc = 1;
|
||||
|
||||
movi_set_ofs(0);
|
||||
movi_init();
|
||||
} else if (INF_REG3_REG == 7 || INF_REG3_REG == 0) { /* SD/MMC */
|
||||
if (INF_REG3_REG & 0x1)
|
||||
movi_ch = 1;
|
||||
else
|
||||
movi_ch = 0;
|
||||
|
||||
puts("SD/MMC: ");
|
||||
|
||||
movi_set_capacity();
|
||||
movi_set_ofs(MOVI_TOTAL_BLKCNT);
|
||||
movi_init();
|
||||
} else {
|
||||
|
||||
}
|
||||
#endif /* CONFIG_MMC */
|
||||
|
||||
#ifdef CONFIG_SMDK6440
|
||||
if (INF_REG3_REG == 2) {
|
||||
; /* N/A */
|
||||
} else {
|
||||
puts("NAND: ");
|
||||
nand_init();
|
||||
|
||||
//setenv("bootcmd", "nand read c0008000 80000 380000;bootm c0008000");
|
||||
}
|
||||
#endif
|
||||
|
||||
#if (CONFIG_COMMANDS & CFG_CMD_ONENAND)
|
||||
#ifdef ENV_IS_VARIABLE
|
||||
if (is_onenand)
|
||||
#endif
|
||||
/* samsung socs: no auto-detect devices */
|
||||
#elif defined(CONFIG_SMDK6400) || defined(CONFIG_SMDK2450) || defined(CONFIG_SMDK2416)
|
||||
|
||||
#if defined(CONFIG_NAND)
|
||||
puts("NAND: ");
|
||||
nand_init();
|
||||
#endif /* CONFIG_NAND */
|
||||
|
||||
#if defined(CONFIG_ONENAND)
|
||||
puts("OneNAND: ");
|
||||
onenand_init();
|
||||
#endif /* CONFIG_ONENAND */
|
||||
|
||||
#if defined(CONFIG_BOOT_MOVINAND)
|
||||
puts("SD/MMC: ");
|
||||
|
||||
if ((0x24564236 == magic[0]) && (0x20764316 == magic[1])) {
|
||||
printf("Boot up for burning\n");
|
||||
} else {
|
||||
movi_set_capacity();
|
||||
movi_set_ofs(MOVI_TOTAL_BLKCNT);
|
||||
movi_init();
|
||||
}
|
||||
#endif /* CONFIG_BOOT_MOVINAND */
|
||||
|
||||
/* others */
|
||||
#else /* defined(CONFIG_SMDK6400) || defined(CONFIG_SMDK2450) || defined(CONFIG_SMDK2416) */
|
||||
|
||||
#if defined(CONFIG_CMD_NAND)
|
||||
puts ("NAND: ");
|
||||
nand_init();
|
||||
#endif /* CONFIG_CMD_NAND */
|
||||
|
||||
/* CONFIG_SMDK6450, CONFIG_VALDEZ use this */
|
||||
#if defined(CONFIG_GENERIC_MMC)
|
||||
puts("SD/MMC: ");
|
||||
if (mmc_initialize(gd->bd))
|
||||
puts ("0 MB\n");
|
||||
#endif /* CONFIG_GENERIC_MMC */
|
||||
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_HAS_DATAFLASH
|
||||
@ -351,14 +582,17 @@ void start_armboot (void)
|
||||
/* initialize environment */
|
||||
env_relocate ();
|
||||
|
||||
/* set TomTom specific environment variables */
|
||||
tomtom_env_init();
|
||||
|
||||
#ifdef CONFIG_VFD
|
||||
/* must do this after the framebuffer is allocated */
|
||||
drv_vfd_init();
|
||||
#endif /* CONFIG_VFD */
|
||||
|
||||
#ifdef CONFIG_SERIAL_MULTI
|
||||
serial_initialize();
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_NET
|
||||
|
||||
/* IP Address */
|
||||
gd->bd->bi_ip_addr = getenv_IPaddr ("ipaddr");
|
||||
|
||||
@ -389,7 +623,7 @@ void start_armboot (void)
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
#endif
|
||||
devices_init (); /* get the devices list going. */
|
||||
|
||||
#ifdef CONFIG_CMC_PU2
|
||||
@ -409,6 +643,13 @@ void start_armboot (void)
|
||||
enable_interrupts ();
|
||||
|
||||
/* Perform network card initialisation if necessary */
|
||||
#ifdef CONFIG_DRIVER_TI_EMAC
|
||||
extern void dm644x_eth_set_mac_addr (const u_int8_t *addr);
|
||||
if (getenv ("ethaddr")) {
|
||||
dm644x_eth_set_mac_addr(gd->bd->bi_enetaddr);
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_DRIVER_CS8900
|
||||
cs8900_get_enetaddr (gd->bd->bi_enetaddr);
|
||||
#endif
|
||||
@ -423,20 +664,24 @@ void start_armboot (void)
|
||||
if ((s = getenv ("loadaddr")) != NULL) {
|
||||
load_addr = simple_strtoul (s, NULL, 16);
|
||||
}
|
||||
#if (CONFIG_COMMANDS & CFG_CMD_NET)
|
||||
#if defined(CONFIG_CMD_NET)
|
||||
if ((s = getenv ("bootfile")) != NULL) {
|
||||
copy_filename (BootFile, s, sizeof (BootFile));
|
||||
}
|
||||
#endif /* CFG_CMD_NET */
|
||||
#endif
|
||||
|
||||
#ifdef BOARD_LATE_INIT
|
||||
board_late_init ();
|
||||
#endif
|
||||
#if (CONFIG_COMMANDS & CFG_CMD_NET)
|
||||
#if defined(CONFIG_CMD_NET)
|
||||
#if defined(CONFIG_NET_MULTI)
|
||||
puts ("Net: ");
|
||||
#endif
|
||||
eth_initialize(gd->bd);
|
||||
#if defined(CONFIG_RESET_PHY_R)
|
||||
debug ("Reset Ethernet PHY\n");
|
||||
reset_phy();
|
||||
#endif
|
||||
#endif
|
||||
/* main_loop() can return to retry autoboot, if so just run it again. */
|
||||
for (;;) {
|
||||
@ -450,11 +695,18 @@ extern void epicfail(void);
|
||||
|
||||
void hang (void)
|
||||
{
|
||||
puts ("### ERROR ### Please RESET the board ###\n");
|
||||
#ifdef EPICFAIL_POWEROFF
|
||||
puts ("ERROR: volountary epic fail\n");
|
||||
epicfail();
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_CMD_BOOTWATCHDOG
|
||||
/* Tell bootwatchdog the signature check failed */
|
||||
bootwatchdog_pulse(20000, 0);
|
||||
puts ("### ERROR ### Please RESET the board ###\n");
|
||||
#else
|
||||
for (;;);
|
||||
#endif
|
||||
}
|
||||
|
||||
#ifdef CONFIG_MODEM_SUPPORT
|
||||
|
||||
334
plat-tomtom/offenburg/sys_info.c
Normal file
334
plat-tomtom/offenburg/sys_info.c
Normal file
@ -0,0 +1,334 @@
|
||||
/*
|
||||
* (C) Copyright 2009
|
||||
* Texas Instruments, <www.ti.com>
|
||||
* Richard Woodruff <r-woodruff2@ti.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/arch/cpu.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/arch/bits.h>
|
||||
#include <asm/arch/mem.h> /* get mem tables */
|
||||
#include <asm/arch/sys_proto.h>
|
||||
#include <asm/arch/sys_info.h>
|
||||
#include <asm/arch/rev.h>
|
||||
#include <i2c.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
u32 get_board_rev(void);
|
||||
|
||||
/****************************************************
|
||||
* get_cpu_type() - low level get cpu type
|
||||
* - no C globals yet.
|
||||
****************************************************/
|
||||
u32 get_cpu_type(void)
|
||||
{
|
||||
// fixme, need to get register defines for 3430
|
||||
return (CPU_3430);
|
||||
}
|
||||
|
||||
/*
|
||||
* cpu_is_3410(void) - returns true for 3410
|
||||
*/
|
||||
u32 cpu_is_3410(void)
|
||||
{
|
||||
int status;
|
||||
if (get_cpu_rev() < CPU_3XX_ES20) {
|
||||
return 0;
|
||||
} else {
|
||||
/* read scalability status and return 1 for 3410*/
|
||||
status = __raw_readl(CONTROL_SCALABLE_OMAP_STATUS);
|
||||
/*
|
||||
* Check whether MPU frequency is set to 266 MHz which
|
||||
* is nominal for 3410. If yes return true else false
|
||||
*/
|
||||
if (((status >> 8) & 0x3) == 0x2)
|
||||
return 1;
|
||||
else
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
|
||||
/****************************************************
|
||||
* is_mem_sdr() - return 1 if mem type in use is SDR
|
||||
****************************************************/
|
||||
u32 is_mem_sdr(void)
|
||||
{
|
||||
volatile u32 *burst = (volatile u32 *)(SDRC_MR_0 + SDRC_CS0_OSET);
|
||||
if (*burst == SDP_SDRC_MR_0_SDR)
|
||||
return (1);
|
||||
return (0);
|
||||
}
|
||||
|
||||
/***********************************************************
|
||||
* get_mem_type() - identify type of mDDR part used.
|
||||
***********************************************************/
|
||||
u32 get_mem_type(void)
|
||||
{
|
||||
#if (defined(CONFIG_STRASBOURG) && defined(__VARIANT_RENNES_A1))
|
||||
return (DDR_STACKED);
|
||||
#else
|
||||
return (DDR_DISCRETE);
|
||||
#endif
|
||||
}
|
||||
|
||||
/***********************************************************************
|
||||
* get_cs0_size() - get size of chip select 0/1
|
||||
************************************************************************/
|
||||
u32 get_sdr_cs_size(u32 offset)
|
||||
{
|
||||
u32 size;
|
||||
|
||||
/* get ram size field */
|
||||
size = __raw_readl(SDRC_MCFG_0 + offset) >> 8;
|
||||
size &= 0x3FF; /* remove unwanted bits */
|
||||
size *= SZ_2M; /* find size in MB */
|
||||
return (size);
|
||||
}
|
||||
|
||||
/*
|
||||
* get_board_type() - get board type based on current production stats.
|
||||
* - NOTE-1-: 2 I2C EEPROMs will someday be populated with proper info.
|
||||
* when they are available we can get info from there. This should
|
||||
* be correct of all known boards up until today.
|
||||
* - NOTE-2- EEPROMs are populated but they are updated very slowly. To
|
||||
* avoid waiting on them we will use ES version of the chip to get info.
|
||||
* A later version of the FPGA migth solve their speed issue.
|
||||
*/
|
||||
u32 get_board_type(void)
|
||||
{
|
||||
if (get_cpu_rev() >= CPU_3XX_ES20)
|
||||
return SDP_3430_V2;
|
||||
else
|
||||
return SDP_3430_V1;
|
||||
}
|
||||
|
||||
/******************************************************************
|
||||
* get_sysboot_value() - get init word settings
|
||||
******************************************************************/
|
||||
inline u32 get_sysboot_value(void)
|
||||
{
|
||||
return (0x0000003F & __raw_readl(CONTROL_STATUS));
|
||||
}
|
||||
|
||||
/***************************************************************************
|
||||
* get_gpmc0_base() - Return current address hardware will be
|
||||
* fetching from. The below effectively gives what is correct, its a bit
|
||||
* mis-leading compared to the TRM. For the most general case the mask
|
||||
* needs to be also taken into account this does work in practice.
|
||||
* - for u-boot we currently map:
|
||||
* -- 0 to nothing,
|
||||
* -- 4 to flash
|
||||
* -- 8 to enent
|
||||
* -- c to wifi
|
||||
****************************************************************************/
|
||||
u32 get_gpmc0_base(void)
|
||||
{
|
||||
u32 b;
|
||||
|
||||
b = __raw_readl(GPMC_CONFIG_CS0 + GPMC_CONFIG7);
|
||||
b &= 0x1F; /* keep base [5:0] */
|
||||
b = b << 24; /* ret 0x0b000000 */
|
||||
return (b);
|
||||
}
|
||||
|
||||
/*******************************************************************
|
||||
* get_gpmc0_width() - See if bus is in x8 or x16 (mainly for nand)
|
||||
*******************************************************************/
|
||||
u32 get_gpmc0_width(void)
|
||||
{
|
||||
return (WIDTH_16BIT);
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* display_board_info() - print banner with board info.
|
||||
*********************************************************************/
|
||||
void display_board_info(u32 btype)
|
||||
{
|
||||
enum {
|
||||
BOOTMODE_NOR,
|
||||
BOOTMODE_ONND,
|
||||
BOOTMODE_NAND,
|
||||
BOOTMODE_MMC
|
||||
};
|
||||
|
||||
char *bootmode[] = {
|
||||
"NOR",
|
||||
"ONND",
|
||||
"NAND",
|
||||
"MMC"
|
||||
};
|
||||
u32 brev = get_board_rev();
|
||||
char cpu_3430s[] = CONFIG_OMAP3_SOC_NAME;
|
||||
char db_ver[] = "0.0"; /* board type */
|
||||
char mem_sdr[] = "mSDR"; /* memory type */
|
||||
char mem_ddr[] = "mDDR";
|
||||
char t_tst[] = "TST"; /* security level */
|
||||
char t_emu[] = "EMU";
|
||||
char t_hs[] = "HS";
|
||||
char t_gp[] = "GP";
|
||||
char unk[] = "?";
|
||||
#ifdef CONFIG_LED_INFO
|
||||
char led_string[CONFIG_LED_LEN] = { 0 };
|
||||
#endif
|
||||
|
||||
#if defined(L3_200MHZ)
|
||||
char p_l3[] = "200";
|
||||
#elif defined(L3_165MHZ)
|
||||
char p_l3[] = "165";
|
||||
#elif defined(L3_110MHZ)
|
||||
char p_l3[] = "110";
|
||||
#elif defined(L3_133MHZ)
|
||||
char p_l3[] = "133";
|
||||
#elif defined(L3_100MHZ)
|
||||
char p_l3[] = "100";
|
||||
#endif
|
||||
|
||||
#if defined(PRCM_PCLK_OPP1)
|
||||
char p_cpu[] = "1";
|
||||
#elif defined(PRCM_PCLK_OPP2)
|
||||
char p_cpu[] = "2";
|
||||
#elif defined(PRCM_PCLK_OPP3)
|
||||
char p_cpu[] = "3";
|
||||
#elif defined(PRCM_PCLK_OPP4)
|
||||
char p_cpu[] = "4";
|
||||
#endif
|
||||
char *cpu_s, *db_s, *mem_s, *sec_s;
|
||||
u32 cpu, rev, sec;
|
||||
|
||||
rev = get_cpu_rev();
|
||||
cpu = get_cpu_type();
|
||||
sec = get_device_type();
|
||||
|
||||
if (is_mem_sdr())
|
||||
mem_s = mem_sdr;
|
||||
else
|
||||
mem_s = mem_ddr;
|
||||
|
||||
cpu_s = cpu_3430s;
|
||||
|
||||
db_s = db_ver;
|
||||
db_s[0] += (brev >> 4) & 0xF;
|
||||
db_s[2] += brev & 0xF;
|
||||
|
||||
switch (sec) {
|
||||
case TST_DEVICE:
|
||||
sec_s = t_tst;
|
||||
break;
|
||||
case EMU_DEVICE:
|
||||
sec_s = t_emu;
|
||||
break;
|
||||
case HS_DEVICE:
|
||||
sec_s = t_hs;
|
||||
break;
|
||||
case GP_DEVICE:
|
||||
sec_s = t_gp;
|
||||
break;
|
||||
default:
|
||||
sec_s = unk;
|
||||
}
|
||||
|
||||
printf("OMAP%s-%s rev %d, CPU-OPP%s L3-%sMHz\n", cpu_s, sec_s, rev,
|
||||
p_cpu, p_l3);
|
||||
printf("OMAP" CONFIG_OMAP3_SOC_NAME " " CONFIG_BOARD_NAME " %s Version + %s (Boot %s)\n", db_s,
|
||||
mem_s, bootmode[BOOTMODE_MMC]);
|
||||
printf("Machine: %lu, Revision: %x\n", gd->bd->bi_arch_number, get_board_rev());
|
||||
#ifdef CONFIG_LED_INFO
|
||||
/* Format: 0123456789ABCDEF
|
||||
* 3430C GP L3-100 NAND
|
||||
*/
|
||||
sprintf(led_string, "%5s%3s%3s %4s", cpu_s, sec_s, p_l3,
|
||||
bootmode[2]);
|
||||
/* reuse sec */
|
||||
for (sec = 0; sec < CONFIG_LED_LEN; sec += 2) {
|
||||
/* invert byte loc */
|
||||
u16 val = led_string[sec] << 8;
|
||||
val |= led_string[sec + 1];
|
||||
__raw_writew(val, LED_REGISTER + sec);
|
||||
}
|
||||
#endif
|
||||
|
||||
}
|
||||
|
||||
/********************************************************
|
||||
* get_base(); get upper addr of current execution
|
||||
*******************************************************/
|
||||
u32 get_base(void)
|
||||
{
|
||||
u32 val;
|
||||
__asm__ __volatile__("mov %0, pc \n":"=r"(val)::"memory");
|
||||
val &= 0xF0000000;
|
||||
val >>= 28;
|
||||
return (val);
|
||||
}
|
||||
|
||||
/********************************************************
|
||||
* running_in_flash() - tell if currently running in
|
||||
* flash.
|
||||
*******************************************************/
|
||||
u32 running_in_flash(void)
|
||||
{
|
||||
if (get_base() < 4)
|
||||
return (1); /* in flash */
|
||||
return (0); /* running in SRAM or SDRAM */
|
||||
}
|
||||
|
||||
/********************************************************
|
||||
* running_in_sram() - tell if currently running in
|
||||
* sram.
|
||||
*******************************************************/
|
||||
u32 running_in_sram(void)
|
||||
{
|
||||
if (get_base() == 4)
|
||||
return (1); /* in SRAM */
|
||||
return (0); /* running in FLASH or SDRAM */
|
||||
}
|
||||
|
||||
/********************************************************
|
||||
* running_in_sdram() - tell if currently running in
|
||||
* sdram.
|
||||
*******************************************************/
|
||||
u32 running_in_sdram(void)
|
||||
{
|
||||
if (get_base() > 4)
|
||||
return (1); /* in sdram */
|
||||
return (0); /* running in SRAM or FLASH */
|
||||
}
|
||||
|
||||
/***************************************************************
|
||||
* get_boot_type() - Is this an XIP type device or a stream one
|
||||
* bits 4-0 specify type. Bit 5 sys mem/perif
|
||||
***************************************************************/
|
||||
u32 get_boot_type(void)
|
||||
{
|
||||
u32 v;
|
||||
|
||||
v = get_sysboot_value() & (BIT4 | BIT3 | BIT2 | BIT1 | BIT0);
|
||||
return v;
|
||||
}
|
||||
|
||||
/*************************************************************
|
||||
* get_device_type(): tell if GP/HS/EMU/TST
|
||||
*************************************************************/
|
||||
u32 get_device_type(void)
|
||||
{
|
||||
int mode;
|
||||
mode = __raw_readl(CONTROL_STATUS) & (DEVICE_MASK);
|
||||
return (mode >>= 8);
|
||||
}
|
||||
Loading…
x
Reference in New Issue
Block a user