Shinya Kuribayashi decaba6f5c [MIPS] Cleanup CP0 Status initialization ...

Add setup_c0_status from Linux. For the moment we disable interrupts, set
CU0, mark the kernel mode, and clear ERL and EXL. This is good enough for
reset-time configuration and will work well across most processors.

Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>

2008-03-25 21:30:07 +09:00

..

asc_serial.c

* Patch by Steven Scholz, 10 Oct 2003

2003-10-09 20:09:04 +00:00

asc_serial.h

* Patch by Steven Scholz, 10 Oct 2003

2003-10-09 20:09:04 +00:00

au1x00_eth.c

[MIPS] au1x00_eth.c: Fixed a warning on pb1000 build.

2007-11-17 18:54:16 +09:00

au1x00_serial.c

Fix au1x00_serial baud rate calculation:

2005-09-25 16:50:33 +02:00

au1x00_usb_ohci.c

Add support for AMD's Pb1x00 eval board;

2005-09-25 00:53:22 +02:00

au1x00_usb_ohci.h

Add support for AMD's Pb1x00 eval board;

2005-09-25 00:53:22 +02:00

cache.S

[MIPS] Fix I-/D-cache initialization loops

2008-03-25 21:30:06 +09:00

config.mk

cpu/mips/cofigl.mk: Make a needlessly deffered expansion immediate.

2008-02-23 09:44:19 +01:00

cpu.c

[MIPS] Implement flush_cache()

2008-03-25 21:30:06 +09:00

incaip_clock.c

Code cleanup, especially MIPS for GCC 4.x

2005-12-04 00:40:34 +01:00

incaip_wdt.S

* Code cleanup:

2003-06-27 21:31:46 +00:00

interrupts.c

* Code cleanup:

2003-06-27 21:31:46 +00:00

Makefile

Move "ar" flags to config.mk to allow for silent "make -s"

2006-10-09 01:02:05 +02:00

start.S

[MIPS] Cleanup CP0 Status initialization

2008-03-25 21:30:07 +09:00