b4ec9c2d43
Implement functions for configuring the macb0 and macb1 pins, as well as functions for getting the clock rate of the various busses the macb ethernet controllers are connected to. Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
128 lines
4.2 KiB
C
128 lines
4.2 KiB
C
/*
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* Copyright (C) 2006 Atmel Corporation
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/arch/gpio.h>
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/*
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* Lots of small functions here. We depend on --gc-sections getting
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* rid of the ones we don't need.
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*/
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void gpio_enable_ebi(void)
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{
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#ifdef CFG_HSDRAMC
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#ifndef CFG_SDRAM_16BIT
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gpio_select_periph_A(GPIO_PIN_PE0, 0);
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gpio_select_periph_A(GPIO_PIN_PE1, 0);
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gpio_select_periph_A(GPIO_PIN_PE2, 0);
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gpio_select_periph_A(GPIO_PIN_PE3, 0);
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gpio_select_periph_A(GPIO_PIN_PE4, 0);
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gpio_select_periph_A(GPIO_PIN_PE5, 0);
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gpio_select_periph_A(GPIO_PIN_PE6, 0);
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gpio_select_periph_A(GPIO_PIN_PE7, 0);
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gpio_select_periph_A(GPIO_PIN_PE8, 0);
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gpio_select_periph_A(GPIO_PIN_PE9, 0);
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gpio_select_periph_A(GPIO_PIN_PE10, 0);
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gpio_select_periph_A(GPIO_PIN_PE11, 0);
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gpio_select_periph_A(GPIO_PIN_PE12, 0);
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gpio_select_periph_A(GPIO_PIN_PE13, 0);
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gpio_select_periph_A(GPIO_PIN_PE14, 0);
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gpio_select_periph_A(GPIO_PIN_PE15, 0);
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#endif
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gpio_select_periph_A(GPIO_PIN_PE26, 0);
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#endif
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}
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void gpio_enable_usart0(void)
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{
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gpio_select_periph_B(GPIO_PIN_PA8, 0);
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gpio_select_periph_B(GPIO_PIN_PA9, 0);
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}
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void gpio_enable_usart1(void)
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{
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gpio_select_periph_A(GPIO_PIN_PA17, 0);
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gpio_select_periph_A(GPIO_PIN_PA18, 0);
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}
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void gpio_enable_usart2(void)
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{
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gpio_select_periph_B(GPIO_PIN_PB26, 0);
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gpio_select_periph_B(GPIO_PIN_PB27, 0);
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}
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void gpio_enable_usart3(void)
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{
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gpio_select_periph_B(GPIO_PIN_PB18, 0);
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gpio_select_periph_B(GPIO_PIN_PB19, 0);
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}
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void gpio_enable_macb0(void)
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{
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gpio_select_periph_A(GPIO_PIN_PC3, 0); /* TXD0 */
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gpio_select_periph_A(GPIO_PIN_PC4, 0); /* TXD1 */
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gpio_select_periph_A(GPIO_PIN_PC7, 0); /* TXEN */
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gpio_select_periph_A(GPIO_PIN_PC8, 0); /* TXCK */
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gpio_select_periph_A(GPIO_PIN_PC9, 0); /* RXD0 */
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gpio_select_periph_A(GPIO_PIN_PC10, 0); /* RXD1 */
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gpio_select_periph_A(GPIO_PIN_PC13, 0); /* RXER */
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gpio_select_periph_A(GPIO_PIN_PC15, 0); /* RXDV */
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gpio_select_periph_A(GPIO_PIN_PC16, 0); /* MDC */
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gpio_select_periph_A(GPIO_PIN_PC17, 0); /* MDIO */
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#if !defined(CONFIG_RMII)
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gpio_select_periph_A(GPIO_PIN_PC0, 0); /* COL */
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gpio_select_periph_A(GPIO_PIN_PC1, 0); /* CRS */
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gpio_select_periph_A(GPIO_PIN_PC2, 0); /* TXER */
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gpio_select_periph_A(GPIO_PIN_PC5, 0); /* TXD2 */
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gpio_select_periph_A(GPIO_PIN_PC6, 0); /* TXD3 */
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gpio_select_periph_A(GPIO_PIN_PC11, 0); /* RXD2 */
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gpio_select_periph_A(GPIO_PIN_PC12, 0); /* RXD3 */
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gpio_select_periph_A(GPIO_PIN_PC14, 0); /* RXCK */
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gpio_select_periph_A(GPIO_PIN_PC18, 0); /* SPD */
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#endif
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}
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void gpio_enable_macb1(void)
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{
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gpio_select_periph_B(GPIO_PIN_PD13, 0); /* TXD0 */
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gpio_select_periph_B(GPIO_PIN_PD14, 0); /* TXD1 */
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gpio_select_periph_B(GPIO_PIN_PD11, 0); /* TXEN */
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gpio_select_periph_B(GPIO_PIN_PD12, 0); /* TXCK */
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gpio_select_periph_B(GPIO_PIN_PD10, 0); /* RXD0 */
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gpio_select_periph_B(GPIO_PIN_PD6, 0); /* RXD1 */
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gpio_select_periph_B(GPIO_PIN_PD5, 0); /* RXER */
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gpio_select_periph_B(GPIO_PIN_PD4, 0); /* RXDV */
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gpio_select_periph_B(GPIO_PIN_PD3, 0); /* MDC */
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gpio_select_periph_B(GPIO_PIN_PD2, 0); /* MDIO */
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#if !defined(CONFIG_RMII)
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gpio_select_periph_B(GPIO_PIN_PC19, 0); /* COL */
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gpio_select_periph_B(GPIO_PIN_PC23, 0); /* CRS */
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gpio_select_periph_B(GPIO_PIN_PC26, 0); /* TXER */
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gpio_select_periph_B(GPIO_PIN_PC27, 0); /* TXD2 */
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gpio_select_periph_B(GPIO_PIN_PC28, 0); /* TXD3 */
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gpio_select_periph_B(GPIO_PIN_PC29, 0); /* RXD2 */
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gpio_select_periph_B(GPIO_PIN_PC30, 0); /* RXD3 */
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gpio_select_periph_B(GPIO_PIN_PC24, 0); /* RXCK */
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gpio_select_periph_B(GPIO_PIN_PD15, 0); /* SPD */
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#endif
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}
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