Grzegorz Bernacki 7f19139389 [PPC440SPe] Improve PCIe configuration space access
- correct configuration space mapping
- correct bus numbering
- better access to config space

Prior to this patch, the 440SPe host/PCIe bridge was able to configure only the
first device on the first bus. We now allow to configure up to 16 buses;
also, scanning for devices behind the PCIe-PCIe bridge is supported, so
peripheral devices farther in hierarchy can be identified.

Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com>
2007-09-07 18:20:23 +02:00
..
2007-08-12 18:28:18 +02:00
2007-07-04 01:05:23 +02:00
2006-11-30 18:02:20 +01:00
2007-03-04 01:36:05 +01:00
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