276 lines
9.9 KiB
C
276 lines
9.9 KiB
C
/*
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* (C) Copyright 2006 - 2009
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* Texas Instruments, <www.ti.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*
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*/
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#ifndef _OMAP34XX_CPU_H
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#define _OMAP34XX_CPU_H
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#include <asm/arch/omap3430.h>
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/* Register offsets of common modules */
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/* Control */
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#define CONTROL_STATUS (OMAP34XX_CTRL_BASE + 0x2F0)
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#define OMAP34XX_MCR (OMAP34XX_CTRL_BASE + 0x8C)
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#define CONTROL_SCALABLE_OMAP_STATUS (OMAP34XX_CTRL_BASE + 0x44C)
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#define CONTROL_SCALABLE_OMAP_OCP (OMAP34XX_CTRL_BASE + 0x534)
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#define OMAP34XX_ID_L4_IO_BASE 0x4830A200
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#ifndef __ASSEMBLY__
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typedef struct ctrl_id {
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unsigned char res1[0x4];
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unsigned int idcode; /* 0x04 */
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unsigned int prod_id; /* 0x08 */
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unsigned char res2[0x0C];
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unsigned int die_id_0; /* 0x18 */
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unsigned int die_id_1; /* 0x1C */
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unsigned int die_id_2; /* 0x20 */
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unsigned int die_id_3; /* 0x24 */
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} ctrl_id_t;
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#endif /* __ASSEMBLY__ */
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/* Tap Information */
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#define TAP_IDCODE_REG (OMAP34XX_TAP_BASE+0x204)
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#define PRODUCTION_ID (OMAP34XX_TAP_BASE+0x208)
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/* device type */
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#define DEVICE_MASK (BIT8|BIT9|BIT10)
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#define TST_DEVICE 0x0
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#define EMU_DEVICE 0x1
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#define HS_DEVICE 0x2
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#define GP_DEVICE 0x3
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/* GPMC CS3/cs4/cs6 not avaliable */
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#define GPMC_BASE (OMAP34XX_GPMC_BASE)
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#define GPMC_SYSCONFIG (OMAP34XX_GPMC_BASE+0x10)
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#define GPMC_IRQSTATUS (OMAP34XX_GPMC_BASE+0x18)
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#define GPMC_IRQENABLE (OMAP34XX_GPMC_BASE+0x1C)
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#define GPMC_TIMEOUT_CONTROL (OMAP34XX_GPMC_BASE+0x40)
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#define GPMC_CONFIG (OMAP34XX_GPMC_BASE+0x50)
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#define GPMC_STATUS (OMAP34XX_GPMC_BASE+0x54)
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#define GPMC_CONFIG_CS0 (OMAP34XX_GPMC_BASE+0x60)
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#define GPMC_CONFIG_WIDTH (0x30)
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#define GPMC_CONFIG1 (0x00)
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#define GPMC_CONFIG2 (0x04)
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#define GPMC_CONFIG3 (0x08)
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#define GPMC_CONFIG4 (0x0C)
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#define GPMC_CONFIG5 (0x10)
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#define GPMC_CONFIG6 (0x14)
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#define GPMC_CONFIG7 (0x18)
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#define GPMC_NAND_CMD (0x1C)
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#define GPMC_NAND_ADR (0x20)
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#define GPMC_NAND_DAT (0x24)
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#define GPMC_ECC_CONFIG (0x1F4)
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#define GPMC_ECC_CONTROL (0x1F8)
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#define GPMC_ECC_SIZE_CONFIG (0x1FC)
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#define GPMC_ECC1_RESULT (0x200)
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#define GPMC_ECC2_RESULT (0x204)
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#define GPMC_ECC3_RESULT (0x208)
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#define GPMC_ECC4_RESULT (0x20C)
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#define GPMC_ECC5_RESULT (0x210)
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#define GPMC_ECC6_RESULT (0x214)
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#define GPMC_ECC7_RESULT (0x218)
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#define GPMC_ECC8_RESULT (0x21C)
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#define GPMC_ECC9_RESULT (0x220)
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#define GPMC_PREFETCH_CONFIG1 (0x1e0)
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#define GPMC_PREFETCH_CONFIG2 (0x1e4)
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#define GPMC_PREFETCH_CONTROL (0x1ec)
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#define GPMC_PREFETCH_STATUS (0x1f0)
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/* GPMC Mapping */
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# define FLASH_BASE 0x10000000 /* NOR flash (aligned to 256 Meg) */
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# define FLASH_BASE_SDPV1 0x04000000 /* NOR flash (aligned to 64 Meg) */
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# define FLASH_BASE_SDPV2 0x10000000 /* NOR flash (aligned to 256 Meg) */
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# define DEBUG_BASE 0x08000000 /* debug board */
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# define NAND_BASE 0x30000000 /* NAND addr (actual size small port)*/
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# define PISMO2_BASE 0x18000000 /* PISMO2 CS1/2 */
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# define ONENAND_MAP 0x20000000 /* OneNand addr (actual size small port */
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# define SERIAL_TL16CP754C_BASE 0x10000000 /* Zoom2 Serial chip address */
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/* SMS */
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#define SMS_SYSCONFIG (OMAP34XX_SMS_BASE+0x10)
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#define SMS_RG_ATT0 (OMAP34XX_SMS_BASE+0x48)
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#define SMS_CLASS_ARB0 (OMAP34XX_SMS_BASE+0xD0)
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#define BURSTCOMPLETE_GROUP7 BIT31
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/* SDRC */
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#define SDRC_SYSCONFIG (OMAP34XX_SDRC_BASE+0x10)
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#define SDRC_STATUS (OMAP34XX_SDRC_BASE+0x14)
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#define SDRC_CS_CFG (OMAP34XX_SDRC_BASE+0x40)
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#define SDRC_SHARING (OMAP34XX_SDRC_BASE+0x44)
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#define SDRC_DLLA_CTRL (OMAP34XX_SDRC_BASE+0x60)
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#define SDRC_DLLA_STATUS (OMAP34XX_SDRC_BASE+0x64)
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#define SDRC_DLLB_CTRL (OMAP34XX_SDRC_BASE+0x68)
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#define SDRC_DLLB_STATUS (OMAP34XX_SDRC_BASE+0x6C)
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#define DLLPHASE BIT1
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#define LOADDLL BIT2
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#define DLL_DELAY_MASK 0xFF00
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#define DLL_NO_FILTER_MASK (BIT8|BIT9)
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#define SDRC_POWER (OMAP34XX_SDRC_BASE+0x70)
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#define WAKEUPPROC BIT26
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#define SDRC_MCFG_0 (OMAP34XX_SDRC_BASE+0x80)
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#define SDRC_MCFG_1 (OMAP34XX_SDRC_BASE+0x80 + 0x30)
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#define SDRC_MR_0 (OMAP34XX_SDRC_BASE+0x84)
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#define SDRC_MR_1 (OMAP34XX_SDRC_BASE+0x84 + 0x30)
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#define SDRC_EMR2_0 (OMAP34XX_SDRC_BASE+0x8C)
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#define SDRC_EMR2_1 (OMAP34XX_SDRC_BASE+0x8C + 0x30)
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#define SDRC_ACTIM_CTRLA_0 (OMAP34XX_SDRC_BASE+0x9C)
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#define SDRC_ACTIM_CTRLA_1 (OMAP34XX_SDRC_BASE+0x9C + 0x28)
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#define SDRC_ACTIM_CTRLB_0 (OMAP34XX_SDRC_BASE+0xA0)
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#define SDRC_ACTIM_CTRLB_1 (OMAP34XX_SDRC_BASE+0xA0 + 0x28)
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#define SDRC_RFR_CTRL_0 (OMAP34XX_SDRC_BASE+0xA4)
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#define SDRC_RFR_CTRL_1 (OMAP34XX_SDRC_BASE + 0xA4 + 0x30)
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#define SDRC_MANUAL_0 (OMAP34XX_SDRC_BASE+0xA8)
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#define SDRC_MANUAL_1 (OMAP34XX_SDRC_BASE+0xA8 + 0x30)
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#define OMAP34XX_SDRC_CS0 0x80000000
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#define OMAP34XX_SDRC_CS1 0xA0000000
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#define CMD_NOP 0x0
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#define CMD_PRECHARGE 0x1
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#define CMD_AUTOREFRESH 0x2
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#define CMD_ENTR_PWRDOWN 0x3
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#define CMD_EXIT_PWRDOWN 0x4
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#define CMD_ENTR_SRFRSH 0x5
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#define CMD_CKE_HIGH 0x6
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#define CMD_CKE_LOW 0x7
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#define SOFTRESET BIT1
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#define SMART_IDLE (0x2 << 3)
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#define REF_ON_IDLE (0x1 << 6)
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/* timer regs offsets (32 bit regs) */
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#define TIDR 0x0 /* r */
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#define TIOCP_CFG 0x10 /* rw */
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#define TISTAT 0x14 /* r */
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#define TISR 0x18 /* rw */
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#define TIER 0x1C /* rw */
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#define TWER 0x20 /* rw */
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#define TCLR 0x24 /* rw */
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#define TCRR 0x28 /* rw */
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#define TLDR 0x2C /* rw */
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#define TTGR 0x30 /* rw */
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#define TWPS 0x34 /* r */
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#define TMAR 0x38 /* rw */
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#define TCAR1 0x3c /* r */
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#define TSICR 0x40 /* rw */
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#define TCAR2 0x44 /* r */
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#define GPT_EN ((0<<2)|BIT1|BIT0) /* enable sys_clk NO-prescale /1 */
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/* Watchdog */
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#define WWPS 0x34 /* r */
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#define WSPR 0x48 /* rw */
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#define WLDR 0x2c /* rw */
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#define WTGR 0x30 /* rw */
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#define WD_UNLOCK1 0xAAAA
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#define WD_UNLOCK2 0x5555
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/* PRCM */
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#define CM_FCLKEN_IVA2 0x48004000
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#define CM_CLKEN_PLL_IVA2 0x48004004
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#define CM_IDLEST_PLL_IVA2 0x48004024
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#define CM_CLKSEL1_PLL_IVA2 0x48004040
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#define CM_CLKSEL2_PLL_IVA2 0x48004044
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#define CM_CLKEN_PLL_MPU 0x48004904
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#define CM_IDLEST_PLL_MPU 0x48004924
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#define CM_CLKSEL1_PLL_MPU 0x48004940
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#define CM_CLKSEL2_PLL_MPU 0x48004944
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#define CM_FCLKEN1_CORE 0x48004a00
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#define CM_ICLKEN1_CORE 0x48004a10
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#define CM_ICLKEN2_CORE 0x48004a14
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#define CM_IDLEST1_CORE 0x48004a20
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#define CM_AUTOIDLE1_CORE 0x48004a30
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#define CM_CLKSEL_CORE 0x48004a40
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#define CM_FCLKEN_GFX 0x48004b00
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#define CM_ICLKEN_GFX 0x48004b10
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#define CM_CLKSEL_GFX 0x48004b40
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#define CM_FCLKEN_WKUP 0x48004c00
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#define CM_ICLKEN_WKUP 0x48004c10
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#define CM_CLKSEL_WKUP 0x48004c40
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#define CM_IDLEST_WKUP 0x48004c20
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#define CM_CLKEN_PLL 0x48004d00
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#define CM_IDLEST_CKGEN 0x48004d20
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#define CM_CLKSEL1_PLL 0x48004d40
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#define CM_CLKSEL2_PLL 0x48004d44
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#define CM_CLKSEL3_PLL 0x48004d48
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#define CM_FCLKEN_DSS 0x48004e00
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#define CM_ICLKEN_DSS 0x48004e10
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#define CM_CLKSEL_DSS 0x48004e40
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#define CM_FCLKEN_CAM 0x48004f00
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#define CM_ICLKEN_CAM 0x48004f10
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#define CM_CLKSEL_CAM 0x48004F40
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#define CM_FCLKEN_PER 0x48005000
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#define CM_ICLKEN_PER 0x48005010
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#define CM_CLKSEL_PER 0x48005040
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#define CM_CLKSEL1_EMU 0x48005140
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#define PRM_CLKSEL 0x48306d40
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#define PRM_RSTCTRL 0x48307250
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#define PRM_CLKSRC_CTRL 0x48307270
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#define PRM_RSTTST 0x48307258
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/* SMX-APE */
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#define PM_RT_APE_BASE_ADDR_ARM (SMX_APE_BASE + 0x10000)
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#define PM_GPMC_BASE_ADDR_ARM (SMX_APE_BASE + 0x12400)
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#define PM_OCM_RAM_BASE_ADDR_ARM (SMX_APE_BASE + 0x12800)
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#define PM_OCM_ROM_BASE_ADDR_ARM (SMX_APE_BASE + 0x12C00)
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#define PM_IVA2_BASE_ADDR_ARM (SMX_APE_BASE + 0x14000)
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#define RT_REQ_INFO_PERMISSION_1 (PM_RT_APE_BASE_ADDR_ARM + 0x68)
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#define RT_READ_PERMISSION_0 (PM_RT_APE_BASE_ADDR_ARM + 0x50)
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#define RT_WRITE_PERMISSION_0 (PM_RT_APE_BASE_ADDR_ARM + 0x58)
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#define RT_ADDR_MATCH_1 (PM_RT_APE_BASE_ADDR_ARM + 0x60)
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#define GPMC_REQ_INFO_PERMISSION_0 (PM_GPMC_BASE_ADDR_ARM + 0x48)
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#define GPMC_READ_PERMISSION_0 (PM_GPMC_BASE_ADDR_ARM + 0x50)
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#define GPMC_WRITE_PERMISSION_0 (PM_GPMC_BASE_ADDR_ARM + 0x58)
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#define OCM_REQ_INFO_PERMISSION_0 (PM_OCM_RAM_BASE_ADDR_ARM + 0x48)
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#define OCM_READ_PERMISSION_0 (PM_OCM_RAM_BASE_ADDR_ARM + 0x50)
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#define OCM_WRITE_PERMISSION_0 (PM_OCM_RAM_BASE_ADDR_ARM + 0x58)
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#define OCM_ADDR_MATCH_2 (PM_OCM_RAM_BASE_ADDR_ARM + 0x80)
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#define IVA2_REQ_INFO_PERMISSION_0 (PM_IVA2_BASE_ADDR_ARM + 0x48)
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#define IVA2_READ_PERMISSION_0 (PM_IVA2_BASE_ADDR_ARM + 0x50)
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#define IVA2_WRITE_PERMISSION_0 (PM_IVA2_BASE_ADDR_ARM + 0x58)
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#define IVA2_REQ_INFO_PERMISSION_1 (PM_IVA2_BASE_ADDR_ARM + 0x68)
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#define IVA2_READ_PERMISSION_1 (PM_IVA2_BASE_ADDR_ARM + 0x70)
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#define IVA2_WRITE_PERMISSION_1 (PM_IVA2_BASE_ADDR_ARM + 0x78)
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#define IVA2_REQ_INFO_PERMISSION_2 (PM_IVA2_BASE_ADDR_ARM + 0x88)
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#define IVA2_READ_PERMISSION_2 (PM_IVA2_BASE_ADDR_ARM + 0x90)
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#define IVA2_WRITE_PERMISSION_2 (PM_IVA2_BASE_ADDR_ARM + 0x98)
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#define IVA2_REQ_INFO_PERMISSION_3 (PM_IVA2_BASE_ADDR_ARM + 0xA8)
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#define IVA2_READ_PERMISSION_3 (PM_IVA2_BASE_ADDR_ARM + 0xB0)
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#define IVA2_WRITE_PERMISSION_3 (PM_IVA2_BASE_ADDR_ARM + 0xB8)
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/* I2C base */
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#define I2C_BASE1 (OMAP34XX_CORE_L4_IO_BASE + 0x70000)
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#define I2C_BASE2 (OMAP34XX_CORE_L4_IO_BASE + 0x72000)
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#define I2C_BASE3 (OMAP34XX_CORE_L4_IO_BASE + 0x60000)
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#endif
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