155 lines
4.5 KiB
C
155 lines
4.5 KiB
C
/*
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* (C) Copyright 2006
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* Texas Instruments, <www.ti.com>
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* Richard Woodruff <r-woodruff2@ti.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef _OMAP343X_CLOCKS_H_
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#define _OMAP343X_CLOCKS_H_
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#define PLL_STOP 1 /* PER & IVA */
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#define PLL_LOW_POWER_BYPASS 5 /* MPU, IVA & CORE */
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#define PLL_FAST_RELOCK_BYPASS 6 /* CORE */
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#define PLL_LOCK 7 /* MPU, IVA, CORE & PER */
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/* The following configurations are OPP and SysClk value independant
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* and hence are defined here. All the other DPLL related values are
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* tabulated in lowlevel_init.S.
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*/
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/* CORE DPLL */
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# define CORE_M3X2 2 /* 332MHz : CM_CLKSEL1_EMU */
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# define CORE_SSI_DIV 3 /* 221MHz : CM_CLKSEL_CORE */
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# define CORE_FUSB_DIV 2 /* 41.5MHz: */
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# define CORE_L4_DIV 2 /* 83MHz : L4 */
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# define CORE_L3_DIV 2 /* 166MHz : L3 {DDR} */
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# define GFX_DIV 0 /* 110MHz : CM_CLKSEL_GFX */
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# define WKUP_RSM 2 /* 41.5MHz: CM_CLKSEL_WKUP */
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/* PER DPLL */
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# define PER_M6X2 3 /* 288MHz: CM_CLKSEL1_EMU */
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# define PER_M5X2 4 /* 216MHz: CM_CLKSEL_CAM */
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# define PER_M4X2 9 /* 96MHz : CM_CLKSEL_DSS-dss1 */
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# define PER_M3X2 16 /* 54MHz : CM_CLKSEL_DSS-tv */
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# define CLSEL1_EMU_VAL ((CORE_M3X2 << 16) | (PER_M6X2 << 24) | (0x0a50))
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#ifdef PRCM_CLK_CFG2_332MHZ
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# define M_12 0xA6
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# define N_12 0x05
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# define FSEL_12 0x07
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# define M2_12 0x01 /* M3 of 2 */
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# define M_12_ES1 0x0E
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# define FSL_12_ES1 0x03
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# define M2_12_ES1 0x1 /* M3 of 2 */
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# define M_13 0x14C
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# define N_13 0x0C
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# define FSEL_13 0x03
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# define M2_13 0x01 /* M3 of 2 */
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# define M_13_ES1 0x1B2
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# define N_13_ES1 0x10
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# define FSL_13_ES1 0x03
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# define M2_13_ES1 0x01 /* M3 of 2 */
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# define M_19p2 0x19F
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# define N_19p2 0x17
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# define FSEL_19p2 0x03
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# define M2_19p2 0x01 /* M3 of 2 */
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# define M_19p2_ES1 0x19F
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# define N_19p2_ES1 0x17
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# define FSL_19p2_ES1 0x03
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# define M2_19p2_ES1 0x01 /* M3 of 2 */
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# define M_26 0xA6
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# define N_26 0x0C
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# define FSEL_26 0x07
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# define M2_26 0x01 /* M3 of 2 */
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# define M_26_ES1 0x1B2
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# define N_26_ES1 0x21
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# define FSL_26_ES1 0x03
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# define M2_26_ES1 0x01 /* M3 of 2 */
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# define M_38p4 0x19F
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# define N_38p4 0x2F
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# define FSEL_38p4 0x03
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# define M2_38p4 0x01 /* M3 of 2 */
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# define M_38p4_ES1 0x19F
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# define N_38p4_ES1 0x2F
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# define FSL_38p4_ES1 0x03
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# define M2_38p4_ES1 0x01 /* M3 of 2 */
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#elif defined(PRCM_CLK_CFG2_266MHZ)
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# define M_12 0x85
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# define N_12 0x05
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# define FSEL_12 0x07
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# define M2_12 0x02 /* M3 of 2 */
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# define M_12_ES1 0x85 /* 0x10A */
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# define N_12_ES1 0x05 /* 0x05 */
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# define FSL_12_ES1 0x07 /* 0x7 */
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# define M2_12_ES1 0x2 /* 0x2 with an M3 of 4*/
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# define M_13 0x10A
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# define N_13 0x0C
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# define FSEL_13 0x3
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# define M2_13 0x1 /* M3 of 2 */
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# define M_13_ES1 0x10A /* 0x214 */
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# define N_13_ES1 0x0C /* 0xC */
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# define FSL_13_ES1 0x3 /* 0x3 */
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# define M2_13_ES1 0x1 /* 0x2 with an M3 of 4*/
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# define M_19p2 0x115
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# define N_19p2 0x13
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# define FSEL_19p2 0x03
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# define M2_19p2 0x01 /* M3 of 2 */
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# define M_19p2_ES1 0x115 /* 0x299 */
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# define N_19p2_ES1 0x13 /* 0x17 */
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# define FSL_19p2_ES1 0x03 /* 0x03 */
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# define M2_19p2_ES1 0x01 /* 0x2 with M3 of 4 */
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# define M_26 0x85
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# define N_26 0x0C
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# define FSEL_26 0x07
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# define M2_26 0x01 /* M3 of 2 */
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# define M_26_ES1 0x85 /* 0x10A */
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# define N_26_ES1 0x0C /* 0xC */
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# define FSL_26_ES1 0x07 /* 0x7 */
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# define M2_26_ES1 0x01 /* 0x2 with an M3 of 4 */
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# define M_38p4 0x11C
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# define N_38p4 0x28
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# define FSEL_38p4 0x03
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# define M2_38p4 0x01 /* M3 of 2 */
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# define M_38p4_ES1 0x11C /* 0x299 */
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# define N_38p4_ES1 0x28 /* 0x2f */
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# define FSL_38p4_ES1 0x03 /* 0x3 */
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# define M2_38p4_ES1 0x01 /* 0x2 with an M3 of 4*/
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#endif
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#endif /* endif _OMAP343X_CLOCKS_H_ */
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