139 lines
4.5 KiB
C
139 lines
4.5 KiB
C
/*
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* (C) Copyright 2004-2005
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* Texas Instruments, <www.ti.com>
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* Richard Woodruff <r-woodruff2@ti.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef _OMAP2430_SYS_H_
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#define _OMAP2430_SYS_H_
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#include <asm/arch/sizes.h>
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/*
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* 2430 specific Section
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*/
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/* Stuff on L3 Interconnect */
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#define SMX_APE_BASE 0x68000000
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/* L3 Firewall */
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#define A_REQINFOPERM0 (SMX_APE_BASE + 0x05048)
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#define A_READPERM0 (SMX_APE_BASE + 0x05050)
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#define A_WRITEPERM0 (SMX_APE_BASE + 0x05058)
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/* GPMC */
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#define OMAP24XX_GPMC_BASE (0x6E000000)
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/* SMS */
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#define OMAP24XX_SMS_BASE 0x6C000000
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/* SDRC */
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#define OMAP24XX_SDRC_BASE 0x6D000000
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/*
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* L4 Peripherals - L4 Wakeup and L4 Core now
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*/
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#define OMAP243X_CORE_L4_IO_BASE 0x48000000
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#define OMAP243X_WAKEUP_L4_IO_BASE 0x49000000
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#define OMAP24XX_L4_IO_BASE OMAP243X_CORE_L4_IO_BASE
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/* CONTROL */
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#define OMAP24XX_CTRL_BASE (OMAP243X_WAKEUP_L4_IO_BASE+0x2000)
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/* TAP information */
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#define OMAP24XX_TAP_BASE (OMAP243X_WAKEUP_L4_IO_BASE+0xA000)
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/* UART */
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#define OMAP24XX_UART1 (OMAP24XX_L4_IO_BASE+0x6a000)
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#define OMAP24XX_UART2 (OMAP24XX_L4_IO_BASE+0x6c000)
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#define OMAP24XX_UART3 (OMAP24XX_L4_IO_BASE+0x6e000)
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/* General Purpose Timers */
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#define OMAP24XX_GPT1 (OMAP243X_WAKEUP_L4_IO_BASE+0x18000)
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#define OMAP24XX_GPT2 (OMAP24XX_L4_IO_BASE+0x2A000)
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#define OMAP24XX_GPT3 (OMAP24XX_L4_IO_BASE+0x78000)
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#define OMAP24XX_GPT4 (OMAP24XX_L4_IO_BASE+0x7A000)
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#define OMAP24XX_GPT5 (OMAP24XX_L4_IO_BASE+0x7C000)
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#define OMAP24XX_GPT6 (OMAP24XX_L4_IO_BASE+0x7E000)
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#define OMAP24XX_GPT7 (OMAP24XX_L4_IO_BASE+0x80000)
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#define OMAP24XX_GPT8 (OMAP24XX_L4_IO_BASE+0x82000)
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#define OMAP24XX_GPT9 (OMAP24XX_L4_IO_BASE+0x84000)
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#define OMAP24XX_GPT10 (OMAP24XX_L4_IO_BASE+0x86000)
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#define OMAP24XX_GPT11 (OMAP24XX_L4_IO_BASE+0x88000)
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#define OMAP24XX_GPT12 (OMAP24XX_L4_IO_BASE+0x8A000)
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/* WatchDog Timers (1 secure, 3 GP) */
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#define WD1_BASE (OMAP243X_WAKEUP_L4_IO_BASE+0x14000)
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#define WD2_BASE (OMAP243X_WAKEUP_L4_IO_BASE+0x16000)
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#define WD3_BASE (OMAP24XX_L4_IO_BASE+0x24000) /* not present */
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#define WD4_BASE (OMAP24XX_L4_IO_BASE+0x26000)
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/* 32KTIMER */
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#define SYNC_32KTIMER_BASE (OMAP243X_WAKEUP_L4_IO_BASE+0x20000)
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#define S32K_CR (SYNC_32KTIMER_BASE+0x10)
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/* PRCM */
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#define OMAP24XX_CM_BASE (OMAP243X_WAKEUP_L4_IO_BASE+0x06000)
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/*
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* SDP2430 specific Section
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*/
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/*
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* The 243x's chip selects are programmable. The mask ROM
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* does configure CS0 to 0x08000000 before dispatch. So, if
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* you want your code to live below that address, you have to
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* be prepared to jump though hoops, to reset the base address.
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* Same as in SDP2430
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*/
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#if (CONFIG_2430SDP)
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/* base address for indirect vectors (internal boot mode) */
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#define SRAM_OFFSET0 0x40000000
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#define SRAM_OFFSET1 0x00200000
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#define SRAM_OFFSET2 0x0000F800
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#define SRAM_VECT_CODE (SRAM_OFFSET0|SRAM_OFFSET1|SRAM_OFFSET2)
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#define LOW_LEVEL_SRAM_STACK 0x4020FFFC
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#define PERIFERAL_PORT_BASE 0x480FE003
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/* FPGA on Debug board.*/
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#define ETH_CONTROL_REG (DEBUG_BASE+0x30b)
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#define LAN_RESET_REGISTER (DEBUG_BASE+0x1c)
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#define DIP_SWITCH_INPUT_REG2 (DEBUG_BASE+0x60)
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#define LED_REGISTER (DEBUG_BASE+0x40)
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#define FPGA_REV_REGISTER (DEBUG_BASE+0x10)
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#define EEPROM_MAIN_BRD (DEBUG_BASE+0x10000+0x1800)
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#define EEPROM_CONN_BRD (DEBUG_BASE+0x10000+0x1900)
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#define EEPROM_UI_BRD (DEBUG_BASE+0x10000+0x1A00)
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#define EEPROM_MCAM_BRD (DEBUG_BASE+0x10000+0x1B00)
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#define I2C2_MEMORY_STATUS_REG (DEBUG_BASE+0x10000+0xA)
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#define ENHANCED_UI_EE_NAME "750-2038"
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#define GDP_MB_EE_NAME "750-2031-3"
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#endif /* endif (CONFIG_2430SDP) */
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#endif
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