116 lines
3.2 KiB
C
116 lines
3.2 KiB
C
/*
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* (C) Copyright 2004
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* Texas Instruments, <www.ti.com>
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* Richard Woodruff <r-woodruff2@ti.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef _OMAP2420_SYS_H_
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#define _OMAP2420_SYS_H_
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#include <asm/arch/sizes.h>
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/*
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* 2420 specific Section
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*/
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#define OMAP24XX_L4_IO_BASE (0x48000000)
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/* L3 Firewall */
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#define A_REQINFOPERM0 0x68005048
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#define A_READPERM0 0x68005050
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#define A_WRITEPERM0 0x68005058
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/* CONTROL */
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#define OMAP24XX_CTRL_BASE (0x48000000)
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/* TAP information */
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#define OMAP24XX_TAP_BASE (0x48014000)
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/* GPMC */
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#define OMAP24XX_GPMC_BASE (0x6800A000)
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/* SMS */
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#define OMAP24XX_SMS_BASE 0x68008000
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/* SDRC */
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#define OMAP24XX_SDRC_BASE 0x68009000
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/* UART */
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#define OMAP24XX_UART1 0x4806A000
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#define OMAP24XX_UART2 0x4806C000
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#define OMAP24XX_UART3 0x4806E000
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/* General Purpose Timers */
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#define OMAP24XX_GPT1 0x48028000
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#define OMAP24XX_GPT2 0x4802A000
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#define OMAP24XX_GPT3 0x48078000
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#define OMAP24XX_GPT4 0x4807A000
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#define OMAP24XX_GPT5 0x4807C000
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#define OMAP24XX_GPT6 0x4807E000
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#define OMAP24XX_GPT7 0x48080000
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#define OMAP24XX_GPT8 0x48082000
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#define OMAP24XX_GPT9 0x48084000
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#define OMAP24XX_GPT10 0x48086000
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#define OMAP24XX_GPT11 0x48088000
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#define OMAP24XX_GPT12 0x4808A000
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/* WatchDog Timers (1 secure, 3 GP) */
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#define WD1_BASE 0x48020000
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#define WD2_BASE 0x48022000
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#define WD3_BASE 0x48024000
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#define WD4_BASE 0x48026000
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/* 32KTIMER */
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#define SYNC_32KTIMER 0x48004000
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#define S32K_CR (SYNC_32KTIMER+0x10)
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/* PRCM */
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#define OMAP24XX_CM_BASE 0x48008000
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/*
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* H4 specific Section
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*/
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/*
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* The 2420's chip selects are programmable. The mask ROM
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* does configure CS0 to 0x08000000 before dispatch. So, if
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* you want your code to live below that address, you have to
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* be prepared to jump though hoops, to reset the base address.
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*/
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#if defined(CONFIG_OMAP24XXH4)
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/* base address for indirect vectors (internal boot mode) */
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#define SRAM_OFFSET0 0x40000000
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#define SRAM_OFFSET1 0x00200000
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#define SRAM_OFFSET2 0x0000F800
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#define SRAM_VECT_CODE (SRAM_OFFSET0|SRAM_OFFSET1|SRAM_OFFSET2)
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#define LOW_LEVEL_SRAM_STACK 0x4020FFFC
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#define PERIFERAL_PORT_BASE 0x480FE003
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/* FPGA on Debug board.*/
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#define ETH_CONTROL_REG (DEBUG_BASE+0x30b)
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#define LAN_RESET_REGISTER (DEBUG_BASE+0x1c)
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#endif /* endif CONFIG_2420H4 */
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#endif
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