384 lines
14 KiB
C
384 lines
14 KiB
C
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/*
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* (C) Copyright 2004-2005
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* Texas Instruments, <www.ti.com>
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* Richard Woodruff <r-woodruff2@ti.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef _OMAP24XX_MEM_H_
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#define _OMAP24XX_MEM_H_
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#define SDRC_CS0_OSET 0x0
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#define SDRC_CS1_OSET 0x30 /* mirror CS1 regs appear offset 0x30 from CS0 */
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#ifndef __ASSEMBLY__
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/* struct's for holding data tables for current boards, they are getting used
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early in init when NO global access are there */
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struct sdrc_data_s {
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u32 sdrc_sharing;
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u32 sdrc_mdcfg_0_ddr;
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u32 sdrc_mdcfg_0_sdr;
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u32 sdrc_actim_ctrla_0;
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u32 sdrc_actim_ctrlb_0;
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u32 sdrc_rfr_ctrl;
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u32 sdrc_mr_0_ddr;
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u32 sdrc_mr_0_sdr;
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u32 sdrc_dllab_ctrl;
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} /*__attribute__ ((packed))*/;
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typedef struct sdrc_data_s sdrc_data_t;
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typedef enum {
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STACKED = 0,
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IP_DDR = 1,
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COMBO_DDR = 2,
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IP_SDR = 3,
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} mem_t;
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#endif
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/* set the 243x-SDRC incoming address convention */
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#if defined(SDRC_B_R_C)
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#define B_ALL (0 << 6) /* bank-row-column */
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#elif defined(SDRC_B1_R_B0_C)
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#define B_ALL (1 << 6) /* bank1-row-bank0-column */
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#elif defined(SDRC_R_B_C)
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#define B_ALL (2 << 6) /* row-bank-column */
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#endif
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/* Slower full frequency range default timings for x32 operation*/
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#define H4_2420_SDRC_SHARING 0x00000100
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#define H4_2420_SDRC_MDCFG_0_SDR 0x00D04010 /* discrete sdr module */
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#define H4_2420_SDRC_MR_0_SDR 0x00000031
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#define H4_2420_SDRC_MDCFG_0_DDR 0x01702011 /* descrite ddr module */
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#define SDP_2430_SDRC_MDCFG_0_DDR (0x02584019|B_ALL) /* Infin ddr module */
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#define H4_2420_COMBO_MDCFG_0_DDR 0x00801011 /* combo module */
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#define H4_2420_SDRC_MR_0_DDR 0x00000032
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#define H4_2422_SDRC_SHARING 0x00004b00
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#define H4_2422_SDRC_MDCFG_MONO_DDR 0x01A02011 /* stacked mono die ddr on 2422 */
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#define H4_2422_SDRC_MDCFG_0_DDR 0x00801011 /* stacked dual die ddr on 2422 */
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#define H4_2422_SDRC_MR_0_DDR 0x00000032
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#define H4_2423_SDRC_SHARING 0x00004900 /* 2420POP board cke1 not connected */
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#define H4_2423_SDRC_MDCFG_0_DDR 0x01A02011 /* stacked dual die ddr on 2423 */
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#define H4_2423_SDRC_MDCFG_1_DDR 0x00801011 /* stacked dual die ddr on 2423 */
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/* ES1 work around timings */
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#define H4_242x_SDRC_ACTIM_CTRLA_0_ES1 0x9bead909 /* 165Mhz for use with 100/133 */
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#define H4_242x_SDRC_ACTIM_CTRLB_0_ES1 0x00000020
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#define H4_242x_SDRC_RFR_CTRL_ES1 0x00002401 /* use over refresh for ES1 */
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/* optimized timings good for current shipping parts */
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#define H4_242X_SDRC_ACTIM_CTRLA_0_100MHz 0x5A59B485
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#define H4_242X_SDRC_ACTIM_CTRLB_0_100MHz 0x0000000e
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#define H4_242X_SDRC_ACTIM_CTRLA_0_133MHz 0x8BA6E6C8 /* temp warn 0 settings */
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#define H4_242X_SDRC_ACTIM_CTRLB_0_133MHz 0x00000010 /* temp warn 0 settings */
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#define H4_242X_SDRC_RFR_CTRL_100MHz 0x0002da01
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#define H4_242X_SDRC_RFR_CTRL_133MHz 0x0003de01 /* 7.8us/7.5ns - 50 = 0x3de */
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#define SDP_24XX_SDRC_RFR_CTRL_165MHz 0x0004e201 /* 7.8us/6ns - 50 = 0x4e2 */
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#define H4_242X_SDRC_DLLAB_CTRL_100MHz 0x0000980E /* 90deg, allow DPLLout*1 to work (combo)*/
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#define H4_242X_SDRC_DLLAB_CTRL_133MHz 0x0000690E /* 90deg, for ES2 */
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#define SDP_24XX_SDRC_DLLAB_CTRL_165MHz 0x0000170C /* 72deg, code will recalc dll load */
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/* Infineon part of 2430SDP (133MHz optimized) ~ 7.5ns
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* TDAL = Twr/Tck + Trp/tck = 15/7.5 + 22.5/7.5 = 2 + 3 = 5
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* TDPL = 15/7.5 = 2
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* TRRD = 15/2.5 = 2
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* TRCD = 22.5/7.5 = 3
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* TRP = 22.5/7.5 = 3
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* TRAS = 45/7.5 = 6
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* TRC = 65/7.5 = 8.6->9
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* TRFC = 75/7.5 = 10
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* ACTIMB
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* TCKE = 2 <new in 2430>
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* XSR = 120/7.5 = 16
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*/
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#define TDAL_133 5
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#define TDPL_133 2
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#define TRRD_133 2
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#define TRCD_133 3
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#define TRP_133 3
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#define TRAS_133 6
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#define TRC_133 9
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#define TRFC_133 10
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#define V_ACTIMA_133 ((TRFC_133 << 27) | (TRC_133 << 22) | (TRAS_133 << 18) |(TRP_133 << 15) | \
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(TRCD_133 << 12) |(TRRD_133 << 9) |(TDPL_133 << 6) | (TDAL_133))
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#define TCKE_133 2
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#define XSR_133 16
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#define V_ACTIMB_133 ((TCKE_133 << 12) | (XSR_133 << 0))
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/* Infineon part of 2430SDP (165MHz optimized) 6.06ns
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* ACTIMA
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* TDAL = Twr/Tck + Trp/tck = 15/6 + 18/6 = 2.5 + 3 = 5.5 -> 6
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* TDPL (Twr) = 15/6 = 2.5 -> 3
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* TRRD = 12/6 = 2
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* TRCD = 18/6 = 3
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* TRP = 18/6 = 3
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* TRAS = 42/6 = 7
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* TRC = 60/6 = 10
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* TRFC = 72/6 = 12
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* ACTIMB
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* TCKE = 2 <new in 2430>
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* XSR = 120/6 = 20
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*/
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#define TDAL_165 6
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#define TDPL_165 3
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#define TRRD_165 2
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#define TRCD_165 3
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#define TRP_165 3
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#define TRAS_165 7
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#define TRC_165 10
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#define TRFC_165 12
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#define V_ACTIMA_165 ((TRFC_165 << 27) | (TRC_165 << 22) | (TRAS_165 << 18) |(TRP_165 << 15) | \
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(TRCD_165 << 12) |(TRRD_165 << 9) |(TDPL_165 << 6) | (TDAL_165))
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#define TCKE_165 2
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#define XSR_165 20
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#define V_ACTIMB_165 ((TCKE_165 << 12) | (XSR_165 << 0))
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#if defined(PRCM_CONFIG_II) || defined(PRCM_CONFIG_5B)
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# define H4_2420_SDRC_ACTIM_CTRLA_0 H4_242X_SDRC_ACTIM_CTRLA_0_100MHz
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# define SDP_2430_SDRC_ACTIM_CTRLA_0 V_ACTIMA_133
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# define H4_2420_SDRC_ACTIM_CTRLB_0 H4_242X_SDRC_ACTIM_CTRLB_0_100MHz
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# define H4_2420_SDRC_RFR_CTRL H4_242X_SDRC_RFR_CTRL_100MHz
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# define H4_2420_SDRC_DLLAB_CTRL H4_242X_SDRC_DLLAB_CTRL_100MHz
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# define SDP_2430_SDRC_DLLAB_CTRL 0x0000730E
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# define H4_2422_SDRC_ACTIM_CTRLA_0 H4_242X_SDRC_ACTIM_CTRLA_0_100MHz
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# define H4_2422_SDRC_ACTIM_CTRLB_0 H4_242X_SDRC_ACTIM_CTRLB_0_100MHz
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# define H4_2422_SDRC_RFR_CTRL H4_242X_SDRC_RFR_CTRL_100MHz
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# define H4_2422_SDRC_DLLAB_CTRL H4_242X_SDRC_DLLAB_CTRL_100MHz
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#elif defined(PRCM_CONFIG_III) || defined(PRCM_CONFIG_5A) || defined(PRCM_CONFIG_3)
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# define H4_2420_SDRC_ACTIM_CTRLA_0 H4_242X_SDRC_ACTIM_CTRLA_0_133MHz
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# define SDP_2430_SDRC_ACTIM_CTRLA_0 V_ACTIMA_133
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# define H4_2420_SDRC_ACTIM_CTRLB_0 H4_242X_SDRC_ACTIM_CTRLB_0_133MHz
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# define H4_2420_SDRC_RFR_CTRL H4_242X_SDRC_RFR_CTRL_133MHz
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# define H4_2420_SDRC_DLLAB_CTRL H4_242X_SDRC_DLLAB_CTRL_133MHz
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# define SDP_2430_SDRC_DLLAB_CTRL 0x0000730E
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# define H4_2422_SDRC_ACTIM_CTRLA_0 H4_242X_SDRC_ACTIM_CTRLA_0_133MHz
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# define H4_2422_SDRC_ACTIM_CTRLB_0 H4_242X_SDRC_ACTIM_CTRLB_0_133MHz
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# define H4_2422_SDRC_RFR_CTRL H4_242X_SDRC_RFR_CTRL_133MHz
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# define H4_2422_SDRC_DLLAB_CTRL H4_242X_SDRC_DLLAB_CTRL_133MHz
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#elif defined(PRCM_CONFIG_I) || defined(PRCM_CONFIG_2)
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# define H4_2420_SDRC_ACTIM_CTRLA_0 V_ACTIMA_165
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# define SDP_2430_SDRC_ACTIM_CTRLA_0 V_ACTIMA_165
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# define H4_2420_SDRC_ACTIM_CTRLB_0 V_ACTIMB_165
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# define H4_2420_SDRC_RFR_CTRL SDP_24XX_SDRC_RFR_CTRL_165MHz
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# define H4_2420_SDRC_DLLAB_CTRL SDP_24XX_SDRC_DLLAB_CTRL_165MHz
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# define SDP_2430_SDRC_DLLAB_CTRL SDP_24XX_SDRC_DLLAB_CTRL_165MHz
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# define H4_2422_SDRC_ACTIM_CTRLA_0 V_ACTIMA_165
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# define H4_2422_SDRC_ACTIM_CTRLB_0 V_ACTIMB_165
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# define H4_2422_SDRC_RFR_CTRL SDP_24XX_SDRC_RFR_CTRL_165MHz
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# define H4_2422_SDRC_DLLAB_CTRL SDP_24XX_SDRC_DLLAB_CTRL_165MHz
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#endif
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/*
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* GPMC settings -
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* Definitions is as per the following format
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* # define <PART>_GPMC_CONFIG<x> <value>
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* Where:
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* PART is the part name e.g. STNOR - Intel Strata Flash
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* x is GPMC config registers from 1 to 6 (there will be 6 macros)
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* Value is corresponding value
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*
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* For every valid PRCM configuration there should be only one definition of the same.
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* if values are independent of the board, this definition will be present in this file
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* if values are dependent on the board, then this should go into corresponding mem-boardName.h file
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*
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* Currently valid part Names are (PART):
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* STNOR - Intel Strata Flash
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* SMNAND - Samsung NAND
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* MPDB - H4 MPDB board
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* SBNOR - Sibley NOR
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* ONNAND - Samsung One NAND
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*
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* include/configs/file.h contains the following defn - for all CS we are interested
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* #define OMAP24XX_GPMC_CSx PART
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* #define OMAP24XX_GPMC_CSx_SIZE Size
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* #define OMAP24XX_GPMC_CSx_MAP Map
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* Where:
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* x - CS number
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* PART - Part Name as defined above
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* SIZE - how big is the mapping to be
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* GPMC_SIZE_128M - 0x8
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* GPMC_SIZE_64M - 0xC
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* GPMC_SIZE_32M - 0xE
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* GPMC_SIZE_16M - 0xF
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* MAP - Map this CS to which address(GPMC address space)- Absolute address
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* >>24 before being used.
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*/
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#define GPMC_SIZE_256M 0x0
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#define GPMC_SIZE_128M 0x8
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#define GPMC_SIZE_64M 0xC
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#define GPMC_SIZE_32M 0xE
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#define GPMC_SIZE_16M 0xF
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#if defined(PRCM_CONFIG_II) || defined(PRCM_CONFIG_5B) /* L3 at 100MHz */
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# define SMNAND_GPMC_CONFIG1 0x0
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# define SMNAND_GPMC_CONFIG2 0x00141400
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# define SMNAND_GPMC_CONFIG3 0x00141400
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# define SMNAND_GPMC_CONFIG4 0x0F010F01
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# define SMNAND_GPMC_CONFIG5 0x010C1414
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# define SMNAND_GPMC_CONFIG6 0x00000A80
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# define STNOR_GPMC_CONFIG1 0x3
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# define STNOR_GPMC_CONFIG2 0x000f0f01
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# define STNOR_GPMC_CONFIG3 0x00050502
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# define STNOR_GPMC_CONFIG4 0x0C060C06
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# define STNOR_GPMC_CONFIG5 0x01131F1F
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# define STNOR_GPMC_CONFIG6 0x0 /* 0? Not defined so far... this value is reset val as per gpmc doc */
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# define MPDB_GPMC_CONFIG1 0x00011000
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# define MPDB_GPMC_CONFIG2 0x001F1F00
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# define MPDB_GPMC_CONFIG3 0x00080802
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# define MPDB_GPMC_CONFIG4 0x1C091C09
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# define MPDB_GPMC_CONFIG5 0x031A1F1F
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# define MPDB_GPMC_CONFIG6 0x000003C2
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#endif
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#if defined(PRCM_CONFIG_III) || defined(PRCM_CONFIG_5A) || defined(PRCM_CONFIG_3) /* L3 at 133MHz */
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# define SMNAND_GPMC_CONFIG1 0x00001800
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# define SMNAND_GPMC_CONFIG2 0x00141400
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# define SMNAND_GPMC_CONFIG3 0x00141400
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# define SMNAND_GPMC_CONFIG4 0x0F010F01
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# define SMNAND_GPMC_CONFIG5 0x010C1414
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# define SMNAND_GPMC_CONFIG6 0x00000A80
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# define SMNAND_GPMC_CONFIG7 0x00000C44
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# define STNOR_GPMC_CONFIG1 0x3
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# define STNOR_GPMC_CONFIG2 0x00151501
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# define STNOR_GPMC_CONFIG3 0x00060602
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# define STNOR_GPMC_CONFIG4 0x10081008
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# define STNOR_GPMC_CONFIG5 0x01131F1F
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# define STNOR_GPMC_CONFIG6 0x000004c4
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# define MPDB_GPMC_CONFIG1 0x00011000
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# define MPDB_GPMC_CONFIG2 0x001f1f01
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# define MPDB_GPMC_CONFIG3 0x00080803
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# define MPDB_GPMC_CONFIG4 0x1C091C09
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# define MPDB_GPMC_CONFIG5 0x041f1F1F
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# define MPDB_GPMC_CONFIG6 0x000004C4
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# define SIBNOR_GPMC_CONFIG1 0x3
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# define SIBNOR_GPMC_CONFIG2 0x00151501
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# define SIBNOR_GPMC_CONFIG3 0x00060602
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# define SIBNOR_GPMC_CONFIG4 0x10081008
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# define SIBNOR_GPMC_CONFIG5 0x01131F1F
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# define SIBNOR_GPMC_CONFIG6 0x00000000
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# define ONENAND_GPMC_CONFIG1 0x00001200
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# define ONENAND_GPMC_CONFIG2 0x000c0c01
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# define ONENAND_GPMC_CONFIG3 0x00030301
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# define ONENAND_GPMC_CONFIG4 0x0c040c04
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# define ONENAND_GPMC_CONFIG5 0x010C1010
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# define ONENAND_GPMC_CONFIG6 0x00000000
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# define PCMCIA_GPMC_CONFIG1 0x01E91200
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# define PCMCIA_GPMC_CONFIG2 0x001E1E01
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# define PCMCIA_GPMC_CONFIG3 0x00020203
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# define PCMCIA_GPMC_CONFIG4 0x1D041D04
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# define PCMCIA_GPMC_CONFIG5 0x031D1F1F
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# define PCMCIA_GPMC_CONFIG6 0x000004C4
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#endif /* endif CFG_PRCM_III */
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#if defined (PRCM_CONFIG_I) || defined(PRCM_CONFIG_2) /* L3 at 165MHz */
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# define SMNAND_GPMC_CONFIG1 0x00001800
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# define SMNAND_GPMC_CONFIG2 0x00141400
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# define SMNAND_GPMC_CONFIG3 0x00141400
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# define SMNAND_GPMC_CONFIG4 0x0F010F01
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# define SMNAND_GPMC_CONFIG5 0x010C1414
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# define SMNAND_GPMC_CONFIG6 0x00000A80
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# define SMNAND_GPMC_CONFIG7 0x00000C44
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# define STNOR_GPMC_CONFIG1 0x3
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# define STNOR_GPMC_CONFIG2 0x00151501
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# define STNOR_GPMC_CONFIG3 0x00060602
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# define STNOR_GPMC_CONFIG4 0x11091109
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# define STNOR_GPMC_CONFIG5 0x01141F1F
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# define STNOR_GPMC_CONFIG6 0x000004c4
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# define MPDB_GPMC_CONFIG1 0x00011000
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# define MPDB_GPMC_CONFIG2 0x001f1f01
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# define MPDB_GPMC_CONFIG3 0x00080803
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# define MPDB_GPMC_CONFIG4 0x1c0b1c0a
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# define MPDB_GPMC_CONFIG5 0x041f1F1F
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# define MPDB_GPMC_CONFIG6 0x000004C4
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# define SIBNOR_GPMC_CONFIG1 0x3
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# define SIBNOR_GPMC_CONFIG2 0x00151501
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# define SIBNOR_GPMC_CONFIG3 0x00060602
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# define SIBNOR_GPMC_CONFIG4 0x11091109
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# define SIBNOR_GPMC_CONFIG5 0x01141F1F
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# define SIBNOR_GPMC_CONFIG6 0x00000000
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# define ONENAND_GPMC_CONFIG1 0x00001200
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# define ONENAND_GPMC_CONFIG2 0x000F0F01
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# define ONENAND_GPMC_CONFIG3 0x00030301
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# define ONENAND_GPMC_CONFIG4 0x0F040F04
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# define ONENAND_GPMC_CONFIG5 0x010F1010
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# define ONENAND_GPMC_CONFIG6 0x00000000
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# define PCMCIA_GPMC_CONFIG1 0x01E91200
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# define PCMCIA_GPMC_CONFIG2 0x001E1E01
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# define PCMCIA_GPMC_CONFIG3 0x00020203
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# define PCMCIA_GPMC_CONFIG4 0x1D041D04
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# define PCMCIA_GPMC_CONFIG5 0x031D1F1F
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# define PCMCIA_GPMC_CONFIG6 0x000004C4
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#endif
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#if 0
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/* Board Specific Settings for each of the configurations for chips
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* whose values change as per platform. - None currently
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*/
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#if CONFIG_OMAP24XXH4
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#include <asm/arch/mem-h4.h>
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#endif
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#if CONFIG_2430SDP
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#include <asm/arch/mem-sdp2430.h>
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#endif
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#endif /* if 0 */
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/* max number of GPMC Chip Selects */
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#define GPMC_MAX_CS 8
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/* max number of GPMC regs */
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#define GPMC_MAX_REG 7
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#define PROC_NOR 1
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#define PROC_NAND 2
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#define PISMO_SIBLEY0 3
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#define PISMO_SIBLEY1 4
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#define PISMO_ONENAND 5
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#define DBG_MPDB 6
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#define PISMO_PCMCIA 7
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/* make it readable for the gpmc_init */
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#define PROC_NOR_BASE FLASH_BASE
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#define PROC_NAND_BASE NAND_BASE
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#define PISMO_SIB0_BASE SIBLEY_MAP1
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#define PISMO_SIB1_BASE SIBLEY_MAP2
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#define PISMO_ONEN_BASE ONENAND_MAP
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#define DBG_MPDB_BASE DEBUG_BASE
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#define PISMO_PCMCIA_BASE PCMCIA_BASE
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#endif /* endif _OMAP24XX_MEM_H_ */
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