189 lines
6.8 KiB
C
189 lines
6.8 KiB
C
/*
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* (C) Copyright 2005
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* Texas Instruments, <www.ti.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*
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*/
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#ifndef _OMAP24XX_CPU_H
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#define _OMAP24XX_CPU_H
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/* CPU Specific Headers */
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#ifdef CONFIG_OMAP242X
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#include <asm/arch/omap2420.h>
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#endif
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#ifdef CONFIG_OMAP243X
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#include <asm/arch/omap2430.h>
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#endif
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/* Register offsets of common modules */
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/* Control */
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#define CONTROL_STATUS (OMAP24XX_CTRL_BASE + 0x2F8)
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#define OMAP24XX_MCR (OMAP24XX_CTRL_BASE + 0x8C)
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/* Tap Information */
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#define TAP_IDCODE_REG (OMAP24XX_TAP_BASE+0x204)
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#define PRODUCTION_ID (OMAP24XX_TAP_BASE+0x208)
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/* device type */
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#define DEVICE_MASK (BIT8|BIT9|BIT10)
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#define TST_DEVICE 0x0
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#define EMU_DEVICE 0x1
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#define HS_DEVICE 0x2
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#define GP_DEVICE 0x3
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/* GPMC CS3/cs4/cs6 not avaliable */
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#define GPMC_SYSCONFIG (OMAP24XX_GPMC_BASE+0x10)
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#define GPMC_IRQENABLE (OMAP24XX_GPMC_BASE+0x1C)
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#define GPMC_TIMEOUT_CONTROL (OMAP24XX_GPMC_BASE+0x40)
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#define GPMC_CONFIG (OMAP24XX_GPMC_BASE+0x50)
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#define GPMC_CONFIG_CS0 (OMAP24XX_GPMC_BASE+0x60)
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#define GPMC_CONFIG_WIDTH (0x30)
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#define GPMC_CONFIG1 (0x00)
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#define GPMC_CONFIG2 (0x04)
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#define GPMC_CONFIG3 (0x08)
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#define GPMC_CONFIG4 (0x0C)
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#define GPMC_CONFIG5 (0x10)
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#define GPMC_CONFIG6 (0x14)
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#define GPMC_CONFIG7 (0x18)
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#define GPMC_NAND_CMD (0x1C)
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#define GPMC_NAND_ADR (0x20)
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#define GPMC_NAND_DAT (0x24)
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/* GPMC Mapping */
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# define FLASH_BASE 0x04000000 /* NOR flash (64 Meg aligned) */
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# define DEBUG_BASE 0x08000000 /* debug board */
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# define NAND_BASE 0x0C000000 /* NAND flash */
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# define SIBLEY_MAP1 0x10000000 /* Sibley1 flash */
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# define SIBLEY_MAP2 0x14000000 /* Sibley2 flash */
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# define PCMCIA_BASE 0x18000000 /* PCMCIA region */
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# define ONENAND_MAP 0x20000000 /* OneNand flash */
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/* SMS */
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#define SMS_SYSCONFIG (OMAP24XX_SMS_BASE+0x10)
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#define SMS_CLASS_ARB0 (OMAP24XX_SMS_BASE+0xD0)
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#define BURSTCOMPLETE_GROUP7 BIT31
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/* SDRC */
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#define SDRC_SYSCONFIG (OMAP24XX_SDRC_BASE+0x10)
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#define SDRC_STATUS (OMAP24XX_SDRC_BASE+0x14)
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#define SDRC_CS_CFG (OMAP24XX_SDRC_BASE+0x40)
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#define SDRC_SHARING (OMAP24XX_SDRC_BASE+0x44)
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#define SDRC_DLLA_CTRL (OMAP24XX_SDRC_BASE+0x60)
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#define SDRC_DLLA_STATUS (OMAP24XX_SDRC_BASE+0x64)
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#define SDRC_DLLB_CTRL (OMAP24XX_SDRC_BASE+0x68)
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#define SDRC_DLLB_STATUS (OMAP24XX_SDRC_BASE+0x6C)
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#define DLLPHASE BIT1
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#define LOADDLL BIT2
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#define DLL_DELAY_MASK 0xFF00
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#define DLL_NO_FILTER_MASK (BIT8|BIT9)
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#define SDRC_POWER (OMAP24XX_SDRC_BASE+0x70)
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#define SDRC_MCFG_0 (OMAP24XX_SDRC_BASE+0x80)
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#define SDRC_MR_0 (OMAP24XX_SDRC_BASE+0x84)
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#define SDRC_ACTIM_CTRLA_0 (OMAP24XX_SDRC_BASE+0x9C)
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#define SDRC_ACTIM_CTRLB_0 (OMAP24XX_SDRC_BASE+0xA0)
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#define SDRC_ACTIM_CTRLA_1 (OMAP24XX_SDRC_BASE+0xC4)
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#define SDRC_ACTIM_CTRLB_1 (OMAP24XX_SDRC_BASE+0xC8)
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#define SDRC_RFR_CTRL (OMAP24XX_SDRC_BASE+0xA4)
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#define SDRC_MANUAL_0 (OMAP24XX_SDRC_BASE+0xA8)
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#define OMAP24XX_SDRC_CS0 0x80000000
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#define OMAP24XX_SDRC_CS1 0xA0000000
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#define CMD_NOP 0x0
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#define CMD_PRECHARGE 0x1
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#define CMD_AUTOREFRESH 0x2
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#define CMD_ENTR_PWRDOWN 0x3
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#define CMD_EXIT_PWRDOWN 0x4
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#define CMD_ENTR_SRFRSH 0x5
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#define CMD_CKE_HIGH 0x6
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#define CMD_CKE_LOW 0x7
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#define SOFTRESET BIT1
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#define SMART_IDLE (0x2 << 3)
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#define REF_ON_IDLE (0x1 << 6)
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/* timer regs offsets (32 bit regs) */
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#define TIDR 0x0 /* r */
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#define TIOCP_CFG 0x10 /* rw */
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#define TISTAT 0x14 /* r */
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#define TISR 0x18 /* rw */
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#define TIER 0x1C /* rw */
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#define TWER 0x20 /* rw */
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#define TCLR 0x24 /* rw */
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#define TCRR 0x28 /* rw */
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#define TLDR 0x2C /* rw */
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#define TTGR 0x30 /* rw */
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#define TWPS 0x34 /* r */
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#define TMAR 0x38 /* rw */
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#define TCAR1 0x3c /* r */
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#define TSICR 0x40 /* rw */
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#define TCAR2 0x44 /* r */
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/* Watchdog */
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#define WWPS 0x34 /* r */
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#define WSPR 0x48 /* rw */
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#define WD_UNLOCK1 0xAAAA
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#define WD_UNLOCK2 0x5555
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/* PRCM */
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#define PRCM_CLKSRC_CTRL (OMAP24XX_CM_BASE+0x060)
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#define PRCM_CLKOUT_CTRL (OMAP24XX_CM_BASE+0x070)
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#define PRCM_CLKEMUL_CTRL (OMAP24XX_CM_BASE+0x078)
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#define PRCM_CLKCFG_CTRL (OMAP24XX_CM_BASE+0x080)
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#define PRCM_CLKCFG_STATUS (OMAP24XX_CM_BASE+0x084)
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#define CM_CLKSEL_MPU (OMAP24XX_CM_BASE+0x140)
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#define RM_RSTST_MPU (OMAP24XX_CM_BASE+0x158)
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#define CM_FCLKEN1_CORE (OMAP24XX_CM_BASE+0x200)
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#define CM_FCLKEN2_CORE (OMAP24XX_CM_BASE+0x204)
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#define CM_ICLKEN1_CORE (OMAP24XX_CM_BASE+0x210)
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#define CM_ICLKEN2_CORE (OMAP24XX_CM_BASE+0x214)
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#define CM_CLKSEL1_CORE (OMAP24XX_CM_BASE+0x240)
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#define CM_CLKSEL_WKUP (OMAP24XX_CM_BASE+0x440)
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#define CM_CLKSEL2_CORE (OMAP24XX_CM_BASE+0x244)
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#define CM_FCLKEN_GFX (OMAP24XX_CM_BASE+0x300)
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#define CM_ICLKEN_GFX (OMAP24XX_CM_BASE+0x310)
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#define CM_CLKSEL_GFX (OMAP24XX_CM_BASE+0x340)
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#define RM_RSTCTRL_GFX (OMAP24XX_CM_BASE+0x350)
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#define CM_FCLKEN_WKUP (OMAP24XX_CM_BASE+0x400)
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#define CM_ICLKEN_WKUP (OMAP24XX_CM_BASE+0x410)
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#define CM_CLKSEL_WKUP (OMAP24XX_CM_BASE+0x440)
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#define PM_RSTCTRL_WKUP (OMAP24XX_CM_BASE+0x450)
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#define CM_CLKEN_PLL (OMAP24XX_CM_BASE+0x500)
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#define CM_IDLEST_CKGEN (OMAP24XX_CM_BASE+0x520)
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#define CM_CLKSEL1_PLL (OMAP24XX_CM_BASE+0x540)
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#define CM_CLKSEL2_PLL (OMAP24XX_CM_BASE+0x544)
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#define CM_CLKSEL_DSP (OMAP24XX_CM_BASE+0x840)
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#define CM_CLKSEL_MDM (OMAP24XX_CM_BASE+0xC40)
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/* SMX-APE */
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#define PM_RT_APE_BASE_ADDR_ARM (SMX_APE_BASE + 0x10000)
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#define PM_GPMC_BASE_ADDR_ARM (SMX_APE_BASE + 0x12400)
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#define PM_OCM_RAM_BASE_ADDR_ARM (SMX_APE_BASE + 0x12800)
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#define PM_OCM_ROM_BASE_ADDR_ARM (SMX_APE_BASE + 0x12C00)
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/* IVA2 */
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#define PM_IVA2_BASE_ADDR_ARM (SMX_APE_BASE + 0x14000)
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/* I2C base */
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#define I2C_BASE1 (OMAP24XX_L4_IO_BASE + 0x70000)
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#define I2C_BASE2 (OMAP24XX_L4_IO_BASE + 0x72000)
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#endif
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