Shinya Kuribayashi 2e0e5271aa [MIPS] Fix I-/D-cache initialization loops
Currently we do 1) Index_Store_Tag_I, 2) Fill and 3) Index_Store_Tag_I
again per a loop for I-cache initialization. But according to 'See MIPS
Run', we're encouraged to use three separate loops rather than combining
them *for both I- and D-cache*. This patch tries to fix this.

In accordance with fixing above, mips_init_[id]cache are separated from
mips_cache_reset(), and rewrite cache loops are completely rewritten with
useful macros.

Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
2008-03-25 21:30:06 +09:00
..
2003-06-27 21:31:46 +00:00
2003-06-27 21:31:46 +00:00