c480861bf0
Updated the MPC8568 MDS config to use libfdt and assume use of aliases for ethernet, pci, and serial for the various fixups that are done. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
558 lines
12 KiB
C
558 lines
12 KiB
C
/*
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* Copyright 2007 Freescale Semiconductor.
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*
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* (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <pci.h>
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#include <asm/processor.h>
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#include <asm/immap_85xx.h>
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#include <asm/immap_fsl_pci.h>
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#include <spd.h>
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#include <i2c.h>
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#include <ioports.h>
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#include <libfdt.h>
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#include <fdt_support.h>
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#include "bcsr.h"
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const qe_iop_conf_t qe_iop_conf_tab[] = {
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/* GETH1 */
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{4, 10, 1, 0, 2}, /* TxD0 */
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{4, 9, 1, 0, 2}, /* TxD1 */
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{4, 8, 1, 0, 2}, /* TxD2 */
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{4, 7, 1, 0, 2}, /* TxD3 */
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{4, 23, 1, 0, 2}, /* TxD4 */
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{4, 22, 1, 0, 2}, /* TxD5 */
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{4, 21, 1, 0, 2}, /* TxD6 */
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{4, 20, 1, 0, 2}, /* TxD7 */
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{4, 15, 2, 0, 2}, /* RxD0 */
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{4, 14, 2, 0, 2}, /* RxD1 */
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{4, 13, 2, 0, 2}, /* RxD2 */
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{4, 12, 2, 0, 2}, /* RxD3 */
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{4, 29, 2, 0, 2}, /* RxD4 */
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{4, 28, 2, 0, 2}, /* RxD5 */
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{4, 27, 2, 0, 2}, /* RxD6 */
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{4, 26, 2, 0, 2}, /* RxD7 */
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{4, 11, 1, 0, 2}, /* TX_EN */
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{4, 24, 1, 0, 2}, /* TX_ER */
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{4, 16, 2, 0, 2}, /* RX_DV */
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{4, 30, 2, 0, 2}, /* RX_ER */
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{4, 17, 2, 0, 2}, /* RX_CLK */
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{4, 19, 1, 0, 2}, /* GTX_CLK */
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{1, 31, 2, 0, 3}, /* GTX125 */
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/* GETH2 */
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{5, 10, 1, 0, 2}, /* TxD0 */
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{5, 9, 1, 0, 2}, /* TxD1 */
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{5, 8, 1, 0, 2}, /* TxD2 */
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{5, 7, 1, 0, 2}, /* TxD3 */
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{5, 23, 1, 0, 2}, /* TxD4 */
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{5, 22, 1, 0, 2}, /* TxD5 */
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{5, 21, 1, 0, 2}, /* TxD6 */
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{5, 20, 1, 0, 2}, /* TxD7 */
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{5, 15, 2, 0, 2}, /* RxD0 */
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{5, 14, 2, 0, 2}, /* RxD1 */
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{5, 13, 2, 0, 2}, /* RxD2 */
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{5, 12, 2, 0, 2}, /* RxD3 */
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{5, 29, 2, 0, 2}, /* RxD4 */
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{5, 28, 2, 0, 2}, /* RxD5 */
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{5, 27, 2, 0, 3}, /* RxD6 */
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{5, 26, 2, 0, 2}, /* RxD7 */
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{5, 11, 1, 0, 2}, /* TX_EN */
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{5, 24, 1, 0, 2}, /* TX_ER */
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{5, 16, 2, 0, 2}, /* RX_DV */
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{5, 30, 2, 0, 2}, /* RX_ER */
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{5, 17, 2, 0, 2}, /* RX_CLK */
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{5, 19, 1, 0, 2}, /* GTX_CLK */
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{1, 31, 2, 0, 3}, /* GTX125 */
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{4, 6, 3, 0, 2}, /* MDIO */
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{4, 5, 1, 0, 2}, /* MDC */
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{0, 0, 0, 0, QE_IOP_TAB_END}, /* END of table */
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};
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#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
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extern void ddr_enable_ecc(unsigned int dram_size);
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#endif
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extern long int spd_sdram(void);
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void local_bus_init(void);
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void sdram_init(void);
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int board_early_init_f (void)
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{
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/*
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* Initialize local bus.
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*/
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local_bus_init ();
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enable_8568mds_duart();
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enable_8568mds_flash_write();
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#if defined(CONFIG_QE) && !defined(CONFIG_eTSEC_MDIO_BUS)
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enable_8568mds_qe_mdio();
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#endif
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#ifdef CFG_I2C2_OFFSET
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/* Enable I2C2_SCL and I2C2_SDA */
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volatile struct par_io *port_c;
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port_c = (struct par_io*)(CFG_IMMR + 0xe0140);
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port_c->cpdir2 |= 0x0f000000;
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port_c->cppar2 &= ~0x0f000000;
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port_c->cppar2 |= 0x0a000000;
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#endif
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return 0;
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}
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int checkboard (void)
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{
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printf ("Board: 8568 MDS\n");
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return 0;
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}
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long int
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initdram(int board_type)
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{
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long dram_size = 0;
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puts("Initializing\n");
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#if defined(CONFIG_DDR_DLL)
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{
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/*
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* Work around to stabilize DDR DLL MSYNC_IN.
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* Errata DDR9 seems to have been fixed.
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* This is now the workaround for Errata DDR11:
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* Override DLL = 1, Course Adj = 1, Tap Select = 0
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*/
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volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
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gur->ddrdllcr = 0x81000000;
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asm("sync;isync;msync");
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udelay(200);
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}
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#endif
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dram_size = spd_sdram();
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#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
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/*
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* Initialize and enable DDR ECC.
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*/
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ddr_enable_ecc(dram_size);
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#endif
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/*
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* SDRAM Initialization
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*/
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sdram_init();
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puts(" DDR: ");
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return dram_size;
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}
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/*
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* Initialize Local Bus
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*/
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void
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local_bus_init(void)
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{
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volatile immap_t *immap = (immap_t *)CFG_IMMR;
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volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
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volatile ccsr_lbc_t *lbc = &immap->im_lbc;
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uint clkdiv;
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uint lbc_hz;
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sys_info_t sysinfo;
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get_sys_info(&sysinfo);
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clkdiv = (lbc->lcrr & 0x0f) * 2;
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lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
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gur->lbiuiplldcr1 = 0x00078080;
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if (clkdiv == 16) {
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gur->lbiuiplldcr0 = 0x7c0f1bf0;
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} else if (clkdiv == 8) {
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gur->lbiuiplldcr0 = 0x6c0f1bf0;
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} else if (clkdiv == 4) {
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gur->lbiuiplldcr0 = 0x5c0f1bf0;
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}
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lbc->lcrr |= 0x00030000;
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asm("sync;isync;msync");
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}
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/*
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* Initialize SDRAM memory on the Local Bus.
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*/
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void
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sdram_init(void)
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{
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#if defined(CFG_OR2_PRELIM) && defined(CFG_BR2_PRELIM)
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uint idx;
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volatile immap_t *immap = (immap_t *)CFG_IMMR;
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volatile ccsr_lbc_t *lbc = &immap->im_lbc;
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uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE;
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uint lsdmr_common;
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puts(" SDRAM: ");
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print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
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/*
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* Setup SDRAM Base and Option Registers
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*/
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lbc->or2 = CFG_OR2_PRELIM;
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asm("msync");
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lbc->br2 = CFG_BR2_PRELIM;
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asm("msync");
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lbc->lbcr = CFG_LBC_LBCR;
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asm("msync");
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lbc->lsrt = CFG_LBC_LSRT;
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lbc->mrtpr = CFG_LBC_MRTPR;
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asm("msync");
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/*
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* MPC8568 uses "new" 15-16 style addressing.
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*/
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lsdmr_common = CFG_LBC_LSDMR_COMMON;
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lsdmr_common |= CFG_LBC_LSDMR_BSMA1516;
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/*
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* Issue PRECHARGE ALL command.
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*/
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lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_PCHALL;
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asm("sync;msync");
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*sdram_addr = 0xff;
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ppcDcbf((unsigned long) sdram_addr);
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udelay(100);
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/*
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* Issue 8 AUTO REFRESH commands.
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*/
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for (idx = 0; idx < 8; idx++) {
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lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_ARFRSH;
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asm("sync;msync");
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*sdram_addr = 0xff;
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ppcDcbf((unsigned long) sdram_addr);
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udelay(100);
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}
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/*
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* Issue 8 MODE-set command.
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*/
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lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_MRW;
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asm("sync;msync");
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*sdram_addr = 0xff;
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ppcDcbf((unsigned long) sdram_addr);
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udelay(100);
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/*
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* Issue NORMAL OP command.
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*/
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lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_NORMAL;
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asm("sync;msync");
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*sdram_addr = 0xff;
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ppcDcbf((unsigned long) sdram_addr);
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udelay(200); /* Overkill. Must wait > 200 bus cycles */
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#endif /* enable SDRAM init */
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}
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#if defined(CFG_DRAM_TEST)
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int
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testdram(void)
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{
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uint *pstart = (uint *) CFG_MEMTEST_START;
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uint *pend = (uint *) CFG_MEMTEST_END;
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uint *p;
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printf("Testing DRAM from 0x%08x to 0x%08x\n",
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CFG_MEMTEST_START,
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CFG_MEMTEST_END);
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printf("DRAM test phase 1:\n");
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for (p = pstart; p < pend; p++)
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*p = 0xaaaaaaaa;
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for (p = pstart; p < pend; p++) {
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if (*p != 0xaaaaaaaa) {
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printf ("DRAM test fails at: %08x\n", (uint) p);
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return 1;
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}
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}
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printf("DRAM test phase 2:\n");
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for (p = pstart; p < pend; p++)
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*p = 0x55555555;
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for (p = pstart; p < pend; p++) {
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if (*p != 0x55555555) {
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printf ("DRAM test fails at: %08x\n", (uint) p);
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return 1;
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}
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}
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printf("DRAM test passed.\n");
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return 0;
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}
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#endif
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#if defined(CONFIG_PCI)
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#ifndef CONFIG_PCI_PNP
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static struct pci_config_table pci_mpc8568mds_config_table[] = {
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{
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PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
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pci_cfgfunc_config_device,
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{PCI_ENET0_IOADDR,
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PCI_ENET0_MEMADDR,
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PCI_COMMON_MEMORY | PCI_COMMAND_MASTER}
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},
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{}
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};
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#endif
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static struct pci_controller pci1_hose = {
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#ifndef CONFIG_PCI_PNP
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config_table: pci_mpc8568mds_config_table,
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#endif
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};
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#endif /* CONFIG_PCI */
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#ifdef CONFIG_PCIE1
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static struct pci_controller pcie1_hose;
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#endif /* CONFIG_PCIE1 */
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int first_free_busno = 0;
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/*
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* pib_init() -- Initialize the PCA9555 IO expander on the PIB board
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*/
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void
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pib_init(void)
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{
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u8 val8, orig_i2c_bus;
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/*
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* Assign PIB PMC2/3 to PCI bus
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*/
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/*switch temporarily to I2C bus #2 */
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orig_i2c_bus = i2c_get_bus_num();
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i2c_set_bus_num(1);
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val8 = 0x00;
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i2c_write(0x23, 0x6, 1, &val8, 1);
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i2c_write(0x23, 0x7, 1, &val8, 1);
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val8 = 0xff;
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i2c_write(0x23, 0x2, 1, &val8, 1);
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i2c_write(0x23, 0x3, 1, &val8, 1);
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val8 = 0x00;
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i2c_write(0x26, 0x6, 1, &val8, 1);
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val8 = 0x34;
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i2c_write(0x26, 0x7, 1, &val8, 1);
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val8 = 0xf9;
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i2c_write(0x26, 0x2, 1, &val8, 1);
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val8 = 0xff;
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i2c_write(0x26, 0x3, 1, &val8, 1);
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val8 = 0x00;
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i2c_write(0x27, 0x6, 1, &val8, 1);
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i2c_write(0x27, 0x7, 1, &val8, 1);
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val8 = 0xff;
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i2c_write(0x27, 0x2, 1, &val8, 1);
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val8 = 0xef;
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i2c_write(0x27, 0x3, 1, &val8, 1);
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asm("eieio");
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}
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#ifdef CONFIG_PCI
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void
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pci_init_board(void)
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{
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volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
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uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
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uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16;
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#ifdef CONFIG_PCI1
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{
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pib_init();
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volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCI1_ADDR;
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extern void fsl_pci_init(struct pci_controller *hose);
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struct pci_controller *hose = &pci1_hose;
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uint pci_32 = 1; /* PORDEVSR[15] */
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uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; /* PORDEVSR[14] */
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uint pci_clk_sel = gur->porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; /* PORPLLSR[16] */
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uint pci_agent = (host_agent == 3) || (host_agent == 4 ) || (host_agent == 6);
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uint pci_speed = 66666000;
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if (!(gur->devdisr & MPC85xx_DEVDISR_PCI1)) {
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printf (" PCI: %d bit, %s MHz, %s, %s, %s\n",
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(pci_32) ? 32 : 64,
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(pci_speed == 33333000) ? "33" :
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(pci_speed == 66666000) ? "66" : "unknown",
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pci_clk_sel ? "sync" : "async",
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pci_agent ? "agent" : "host",
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pci_arb ? "arbiter" : "external-arbiter"
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);
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/* inbound */
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pci_set_region(hose->regions + 0,
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CFG_PCI_MEMORY_BUS,
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CFG_PCI_MEMORY_PHYS,
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CFG_PCI_MEMORY_SIZE,
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PCI_REGION_MEM | PCI_REGION_MEMORY);
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/* outbound memory */
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pci_set_region(hose->regions + 1,
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CFG_PCI1_MEM_BASE,
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CFG_PCI1_MEM_PHYS,
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CFG_PCI1_MEM_SIZE,
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PCI_REGION_MEM);
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/* outbound io */
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pci_set_region(hose->regions + 2,
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CFG_PCI1_IO_BASE,
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CFG_PCI1_IO_PHYS,
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CFG_PCI1_IO_SIZE,
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PCI_REGION_IO);
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hose->region_count = 3;
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hose->first_busno = first_free_busno;
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pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
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fsl_pci_init(hose);
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first_free_busno = hose->last_busno+1;
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printf ("PCI on bus %02x - %02x\n",hose->first_busno,hose->last_busno);
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} else {
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printf (" PCI: disabled\n");
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}
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}
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#else
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gur->devdisr |= MPC85xx_DEVDISR_PCI1; /* disable */
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#endif
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#ifdef CONFIG_PCIE1
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{
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volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE1_ADDR;
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extern void fsl_pci_init(struct pci_controller *hose);
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struct pci_controller *hose = &pcie1_hose;
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int pcie_ep = (host_agent == 0) || (host_agent == 2 ) || (host_agent == 3);
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int pcie_configured = io_sel >= 1;
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if (pcie_configured && !(gur->devdisr & MPC85xx_DEVDISR_PCIE)){
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printf ("\n PCIE connected to slot as %s (base address %x)",
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pcie_ep ? "End Point" : "Root Complex",
|
|
(uint)pci);
|
|
|
|
if (pci->pme_msg_det) {
|
|
pci->pme_msg_det = 0xffffffff;
|
|
debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det);
|
|
}
|
|
printf ("\n");
|
|
|
|
/* inbound */
|
|
pci_set_region(hose->regions + 0,
|
|
CFG_PCI_MEMORY_BUS,
|
|
CFG_PCI_MEMORY_PHYS,
|
|
CFG_PCI_MEMORY_SIZE,
|
|
PCI_REGION_MEM | PCI_REGION_MEMORY);
|
|
|
|
/* outbound memory */
|
|
pci_set_region(hose->regions + 1,
|
|
CFG_PCIE1_MEM_BASE,
|
|
CFG_PCIE1_MEM_PHYS,
|
|
CFG_PCIE1_MEM_SIZE,
|
|
PCI_REGION_MEM);
|
|
|
|
/* outbound io */
|
|
pci_set_region(hose->regions + 2,
|
|
CFG_PCIE1_IO_BASE,
|
|
CFG_PCIE1_IO_PHYS,
|
|
CFG_PCIE1_IO_SIZE,
|
|
PCI_REGION_IO);
|
|
|
|
hose->region_count = 3;
|
|
|
|
hose->first_busno=first_free_busno;
|
|
pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
|
|
|
|
fsl_pci_init(hose);
|
|
printf ("PCIE on bus %02x - %02x\n",hose->first_busno,hose->last_busno);
|
|
|
|
first_free_busno=hose->last_busno+1;
|
|
|
|
} else {
|
|
printf (" PCIE: disabled\n");
|
|
}
|
|
}
|
|
#else
|
|
gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */
|
|
#endif
|
|
}
|
|
#endif /* CONFIG_PCI */
|
|
|
|
#if defined(CONFIG_OF_BOARD_SETUP)
|
|
void
|
|
ft_board_setup(void *blob, bd_t *bd)
|
|
{
|
|
int node, tmp[2];
|
|
const char *path;
|
|
|
|
ft_cpu_setup(blob, bd);
|
|
|
|
node = fdt_path_offset(blob, "/aliases");
|
|
tmp[0] = 0;
|
|
if (node >= 0) {
|
|
#ifdef CONFIG_PCI1
|
|
path = fdt_getprop(blob, node, "pci0", NULL);
|
|
if (path) {
|
|
tmp[1] = pci1_hose.last_busno - pci1_hose.first_busno;
|
|
do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
|
|
}
|
|
#endif
|
|
#ifdef CONFIG_PCIE1
|
|
path = fdt_getprop(blob, node, "pci1", NULL);
|
|
if (path) {
|
|
tmp[1] = pcie1_hose.last_busno - pcie1_hose.first_busno;
|
|
do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
|
|
}
|
|
#endif
|
|
}
|
|
}
|
|
#endif
|