176 lines
3.5 KiB
ArmAsm
176 lines
3.5 KiB
ArmAsm
/*
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* Board specific setup info
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*
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* (C) Copyright 2004-2006
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* Texas Instruments, <www.ti.com>
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* Richard Woodruff <r-woodruff2@ti.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/* DPLL(1-4) PARAM TABLES */
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/* Each of the tables has M, N, FREQSEL, M2 values defined for nominal
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* OPP (1.2V). The fields are defined according to dpll_param struct(clock.c).
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* The values are defined for all possible sysclk and for ES1 and ES2.
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*/
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mpu_dpll_param:
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/* 12MHz */
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/* ES1 */
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.word 0x0FE,0x07,0x05,0x01
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/* ES2 */
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.word 0x0FA,0x05,0x07,0x01
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/* 3410 */
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.word 0x085,0x05,0x07,0x01
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/* 13MHz */
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/* ES1 */
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.word 0x17D,0x0C,0x03,0x01
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/* ES2 */
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.word 0x1F4,0x0C,0x03,0x01
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/* 3410 */
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.word 0x10A,0x0C,0x03,0x01
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/* 19.2MHz */
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/* ES1 */
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.word 0x179,0x12,0x04,0x01
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/* ES2 */
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.word 0x271,0x17,0x03,0x01
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/* 3410 */
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.word 0x14C,0x17,0x03,0x01
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/* 26MHz */
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/* ES1 */
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.word 0x17D,0x19,0x03,0x01
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/* ES2 */
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.word 0x0FA,0x0C,0x07,0x01
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/* 3410 */
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.word 0x085,0x0C,0x07,0x01
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/* 38.4MHz */
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/* ES1 */
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.word 0x1FA,0x32,0x03,0x01
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/* ES2 */
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.word 0x271,0x2F,0x03,0x01
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/* 3410 */
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.word 0x14C,0x2F,0x03,0x01
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iva_dpll_param:
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/* 12MHz */
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/* ES1 */
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.word 0x07D,0x05,0x07,0x01
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/* ES2 */
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.word 0x0B4,0x05,0x07,0x01
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/* 3410 */
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.word 0x085,0x05,0x07,0x01
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/* 13MHz */
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/* ES1 */
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.word 0x0FA,0x0C,0x03,0x01
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/* ES2 */
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.word 0x168,0x0C,0x03,0x01
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/* 3410 */
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.word 0x10A,0x0C,0x03,0x01
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/* 19.2MHz */
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/* ES1 */
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.word 0x082,0x09,0x07,0x01
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/* ES2 */
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.word 0x0E1,0x0B,0x06,0x01
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/* 3410 */
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.word 0x14C,0x17,0x03,0x01
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/* 26MHz */
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/* ES1 */
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.word 0x07D,0x0C,0x07,0x01
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/* ES2 */
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.word 0x0B4,0x0C,0x07,0x01
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/* 3410 */
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.word 0x085,0x0C,0x07,0x01
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/* 38.4MHz */
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/* ES1 */
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.word 0x13F,0x30,0x03,0x01
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/* ES2 */
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.word 0x0E1,0x17,0x06,0x01
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/* 3410 */
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.word 0x14C,0x2F,0x03,0x01
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/* Core DPLL targets for L3 at 166 & L133 */
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core_dpll_param:
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/* 12MHz */
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/* ES1 */
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.word M_12_ES1,M_12_ES1,FSL_12_ES1,M2_12_ES1
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/* ES2 */
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.word M_12,N_12,FSEL_12,M2_12
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/* 3410 */
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.word M_12,N_12,FSEL_12,M2_12
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/* 13MHz */
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/* ES1 */
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.word M_13_ES1,N_13_ES1,FSL_13_ES1,M2_13_ES1
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/* ES2 */
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.word M_13,N_13,FSEL_13,M2_13
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/* 3410 */
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.word M_13,N_13,FSEL_13,M2_13
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/* 19.2MHz */
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/* ES1 */
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.word M_19p2_ES1,N_19p2_ES1,FSL_19p2_ES1,M2_19p2_ES1
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/* ES2 */
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.word M_19p2,N_19p2,FSEL_19p2,M2_19p2
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/* 3410 */
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.word M_19p2,N_19p2,FSEL_19p2,M2_19p2
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/* 26MHz */
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/* ES1 */
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.word M_26_ES1,N_26_ES1,FSL_26_ES1,M2_26_ES1
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/* ES2 */
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.word M_26,N_26,FSEL_26,M2_26
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/* 3410 */
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.word M_26,N_26,FSEL_26,M2_26
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/* 38.4MHz */
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/* ES1 */
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.word M_38p4_ES1,N_38p4_ES1,FSL_38p4_ES1,M2_38p4_ES1
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/* ES2 */
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.word M_38p4,N_38p4,FSEL_38p4,M2_38p4
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/* 3410 */
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.word M_38p4,N_38p4,FSEL_38p4,M2_38p4
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/* PER DPLL values are same for both ES1 and ES2 */
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per_dpll_param:
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/* 12MHz */
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.word 0xD8,0x05,0x07,0x09
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/* 13MHz */
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.word 0x1B0,0x0C,0x03,0x09
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/* 19.2MHz */
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.word 0xE1,0x09,0x07,0x09
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/* 26MHz */
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.word 0xD8,0x0C,0x07,0x09
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/* 38.4MHz */
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.word 0xE1,0x13,0x07,0x09
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