551 lines
15 KiB
C
551 lines
15 KiB
C
/*
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* (C) Copyright 2004-2009 Texas Instruments, <www.ti.com>
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* Rohit Choraria <rohitkc@ti.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/mem.h>
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#include <linux/mtd/nand_ecc.h>
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#if (CONFIG_COMMANDS & CFG_CMD_NAND) && !defined(CFG_NAND_LEGACY)
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#include <nand.h>
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#if (CONFIG_FASTBOOT)
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#include <fastboot.h>
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#endif
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unsigned char cs;
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volatile unsigned long gpmc_cs_base_add;
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#define GPMC_BUF_EMPTY 0
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#define GPMC_BUF_FULL 1
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#define ECC_P1_128_E(val) ((val) & 0x000000FF) /* Bit 0 to 7 */
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#define ECC_P512_2048_E(val) (((val) & 0x00000F00)>>8) /* Bit 8 to 11 */
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#define ECC_P1_128_O(val) (((val) & 0x00FF0000)>>16) /* Bit 16 to Bit 23 */
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#define ECC_P512_2048_O(val) (((val) & 0x0F000000)>>24) /* Bit 24 to Bit 27 */
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void omap_nand_switch_ecc(struct mtd_info *, int );
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int nand_unlock(struct mtd_info *mtd, unsigned long off, unsigned long size)
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{
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register struct nand_chip *this = mtd->priv;
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unsigned long start_block, end_block;
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printk("\nUnlocking %x - %x. locking rest..\n", off, off + size);
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if (off + size == this->chipsize)
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size -= mtd->erasesize;
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start_block = (unsigned long) (off >> this->page_shift);
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end_block = (unsigned long) ((off + size) >> this->page_shift);
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this->cmdfunc(mtd, 0x23, -1, start_block);
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this->cmdfunc(mtd, 0x24, -1, end_block);
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ndelay (100);
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return 0;
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}
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/*
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* omap_nand_hwcontrol - Set the address pointers corretly for the
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* following address/data/command operation
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* @mtd: MTD device structure
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* @ctrl: Says whether Address or Command or Data is following.
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*/
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static void omap_nand_hwcontrol(struct mtd_info *mtd, int ctrl)
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{
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register struct nand_chip *this = mtd->priv;
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/*
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* Point the IO_ADDR to DATA and ADDRESS registers instead of chip address
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*/
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switch (ctrl) {
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case NAND_CTL_SETCLE:
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this->IO_ADDR_W = (void *) gpmc_cs_base_add + GPMC_NAND_CMD;
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this->IO_ADDR_R = (void *) gpmc_cs_base_add + GPMC_NAND_DAT;
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break;
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case NAND_CTL_SETALE:
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this->IO_ADDR_W = (void *) gpmc_cs_base_add + GPMC_NAND_ADR;
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this->IO_ADDR_R = (void *) gpmc_cs_base_add + GPMC_NAND_DAT;
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break;
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case NAND_CTL_CLRCLE:
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this->IO_ADDR_W = (void *) gpmc_cs_base_add + GPMC_NAND_DAT;
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this->IO_ADDR_R = (void *) gpmc_cs_base_add + GPMC_NAND_DAT;
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break;
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case NAND_CTL_CLRALE:
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this->IO_ADDR_W = (void *) gpmc_cs_base_add + GPMC_NAND_DAT;
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this->IO_ADDR_R = (void *) gpmc_cs_base_add + GPMC_NAND_DAT;
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break;
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}
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}
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/*
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* omap_nand_wait - called primarily after a program/erase operation
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* so that we access NAND again only after the device
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* is ready again.
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* @mtd: MTD device structure
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* @chip: nand_chip structure
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* @state: State from which wait function is being called i.e write/erase.
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*/
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static int omap_nand_wait(struct mtd_info *mtd, struct nand_chip *chip, int state)
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{
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register struct nand_chip *this = mtd->priv;
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int status = 0;
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void *nand_ptr_r, *nand_ptr_w;
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this->IO_ADDR_W = (void *) gpmc_cs_base_add + GPMC_NAND_CMD;
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this->IO_ADDR_R = (void *) gpmc_cs_base_add + GPMC_NAND_DAT;
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nand_ptr_w = this->IO_ADDR_W;
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nand_ptr_r = this->IO_ADDR_R;
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/* Send the status command and loop until the device is free */
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while(!(status & 0x40)){
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__raw_writeb(NAND_CMD_STATUS & 0xFF, nand_ptr_w);
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status = __raw_readb(nand_ptr_r);
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}
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return status;
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}
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#ifdef CFG_NAND_WIDTH_16
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/**
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* omap_nand_write_buf16 - [DEFAULT] write buffer to chip
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* @mtd: MTD device structure
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* @buf: data buffer
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* @len: number of bytes to write
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*
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* Default write function for 16bit buswith
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*/
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static void omap_nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len)
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{
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int i;
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struct nand_chip *this = mtd->priv;
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u16 *p = (u16 *) buf;
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void *nand_ptr_w = this->IO_ADDR_W;
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len >>= 1;
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for (i=0; i<len; i++){
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writew(p[i], nand_ptr_w);
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while (GPMC_BUF_EMPTY == (readl(GPMC_STATUS) & GPMC_BUF_FULL));
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}
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}
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/**
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* nand_read_buf16 - [DEFAULT] read chip data into buffer
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* @mtd: MTD device structure
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* @buf: buffer to store date
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* @len: number of bytes to read
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*
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* Default read function for 16bit buswith
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*/
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static void omap_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
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{
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int i;
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struct nand_chip *this = mtd->priv;
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u16 *p = (u16 *) buf;
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void *nand_ptr_r = this->IO_ADDR_R;
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len >>= 1;
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for (i=0; i<len; i++)
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p[i] = readw(nand_ptr_r);
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}
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#else
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/*
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* omap_nand_write_buf - write buffer to NAND controller
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* @mtd: MTD device structure
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* @buf: data buffer
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* @len: number of bytes to write
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*
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*/
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static void omap_nand_write_buf(struct mtd_info *mtd, const uint8_t * buf,
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int len)
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{
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int i;
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int j=0;
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struct nand_chip *this = mtd->priv;
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void *nand_ptr_w = this->IO_ADDR_W;
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for (i = 0; i < len; i++) {
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writeb(buf[i], nand_ptr_w);
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for(j=0;j<10;j++);
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}
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}
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/*
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* omap_nand_read_buf - read data from NAND controller into buffer
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* @mtd: MTD device structure
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* @buf: buffer to store date
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* @len: number of bytes to read
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*
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*/
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static void omap_nand_read_buf(struct mtd_info *mtd, uint8_t * buf, int len)
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{
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int i;
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int j=0;
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struct nand_chip *this = mtd->priv;
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void *nand_ptr_r = this->IO_ADDR_R;
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for (i = 0; i < len; i++) {
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buf[i] = readb(nand_ptr_r);
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while (GPMC_BUF_EMPTY == (readl(GPMC_STATUS) & GPMC_BUF_FULL));
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}
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}
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#endif
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/*
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* omap_hwecc_init - Initialize the Hardware ECC for NAND flash in GPMC controller
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* @mtd: MTD device structure
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*
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*/
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static void omap_hwecc_init(struct nand_chip *chip)
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{
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unsigned long val = 0x0;
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/* Init ECC Control Register */
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/* Clear all ECC | Enable Reg1 */
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val = ( (0x00000001<<8) | 0x00000001 );
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__raw_writel(val, GPMC_BASE + GPMC_ECC_CONTROL);
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__raw_writel(0x3fcff000, GPMC_BASE + GPMC_ECC_SIZE_CONFIG);
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}
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/*
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* omap_correct_data - Compares the ecc read from nand spare area with ECC registers values
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* and corrects one bit error if it has occured
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* @mtd: MTD device structure
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* @dat: page data
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* @read_ecc: ecc read from nand flash
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* @calc_ecc: ecc read from ECC registers
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*/
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static int omap_correct_data(struct mtd_info *mtd,u_char *dat,
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u_char *read_ecc, u_char *calc_ecc)
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{
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return 0;
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}
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/*
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* omap_calculate_ecc - Generate non-inverted ECC bytes.
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*
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* Using noninverted ECC can be considered ugly since writing a blank
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* page ie. padding will clear the ECC bytes. This is no problem as
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* long nobody is trying to write data on the seemingly unused page.
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* Reading an erased page will produce an ECC mismatch between
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* generated and read ECC bytes that has to be dealt with separately.
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* @mtd: MTD structure
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* @dat: unused
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* @ecc_code: ecc_code buffer
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*/
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static int omap_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
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u_char *ecc_code)
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{
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unsigned long val = 0x0;
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unsigned long reg;
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/* Start Reading from HW ECC1_Result = 0x200 */
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reg = (unsigned long)(GPMC_BASE + GPMC_ECC1_RESULT);
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val = __raw_readl(reg);
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*ecc_code++ = ECC_P1_128_E(val);
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*ecc_code++ = ECC_P1_128_O(val);
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*ecc_code++ = ECC_P512_2048_E(val) | ECC_P512_2048_O(val) << 4;
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return 0;
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}
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/*
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* omap_enable_ecc - This function enables the hardware ecc functionality
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* @mtd: MTD device structure
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* @mode: Read/Write mode
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*/
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static void omap_enable_hwecc(struct mtd_info *mtd , int mode)
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{
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struct nand_chip *chip = mtd->priv;
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unsigned int val = __raw_readl(GPMC_BASE + GPMC_ECC_CONFIG);
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unsigned int dev_width = (chip->options & NAND_BUSWIDTH_16) >> 1;
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switch (mode) {
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case NAND_ECC_READ :
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__raw_writel(0x101, GPMC_BASE + GPMC_ECC_CONTROL);
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/* ECC col width) | ( CS ) | ECC Enable */
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val = (dev_width << 7) | (cs << 1) | (0x1) ;
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break;
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case NAND_ECC_READSYN :
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__raw_writel(0x100, GPMC_BASE + GPMC_ECC_CONTROL);
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/* ECC col width) | ( CS ) | ECC Enable */
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val = (dev_width << 7) | (cs << 1) | (0x1) ;
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break;
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case NAND_ECC_WRITE :
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__raw_writel(0x101, GPMC_BASE + GPMC_ECC_CONTROL);
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/* ECC col width) | ( CS ) | ECC Enable */
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val = (dev_width << 7) | (cs << 1) | (0x1) ;
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break;
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default:
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printf("Error: Unrecognized Mode[%d]!\n", mode);
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break;
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}
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__raw_writel(val, GPMC_BASE + GPMC_ECC_CONFIG);
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}
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static struct nand_oobinfo hw_nand_oob_64 = {
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.useecc = MTD_NANDECC_AUTOPLACE,
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.eccbytes = 12,
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.eccpos = {
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2, 3, 4, 5,
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6, 7, 8, 9,
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10, 11, 12, 13
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},
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.oobfree = { {14, 50} } /* don't care */
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};
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static struct nand_oobinfo sw_nand_oob_64 = {
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.useecc = MTD_NANDECC_AUTOPLACE,
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.eccbytes = 24,
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.eccpos = {
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40, 41, 42, 43, 44, 45, 46, 47,
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48, 49, 50, 51, 52, 53, 54, 55,
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56, 57, 58, 59, 60, 61, 62, 63
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},
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.oobfree = { {2, 38} }
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};
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void omap_nand_switch_ecc(struct mtd_info *mtd, int hardware)
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{
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struct nand_chip *nand = mtd->priv;
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if (!hardware) {
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nand->eccmode = NAND_ECC_SOFT;
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nand->autooob = &sw_nand_oob_64;
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#if (CFG_SW_ECC_512)
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nand->eccsize = 512;
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#else
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nand->eccsize = 256;
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#endif
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nand->eccbytes = 3;
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nand->eccsteps = mtd->oobblock / nand->eccsize;
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nand->enable_hwecc = 0;
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nand->calculate_ecc = nand_calculate_ecc;
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nand->correct_data = nand_correct_data;
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} else {
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nand->eccmode = NAND_ECC_HW3_512;
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nand->autooob = &hw_nand_oob_64;
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nand->eccsize = 512;
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nand->eccbytes = 3;
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nand->eccsteps = 4;
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nand->enable_hwecc = omap_enable_hwecc;
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nand->correct_data = omap_correct_data;
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nand->calculate_ecc = omap_calculate_ecc;
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omap_hwecc_init(nand);
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}
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mtd->eccsize = nand->eccsize;
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nand->oobdirty = 1;
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if (nand->options & NAND_BUSWIDTH_16) {
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mtd->oobavail = mtd->oobsize - (nand->autooob->eccbytes + 2);
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if (nand->autooob->eccbytes & 0x01)
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mtd->oobavail--;
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} else
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mtd->oobavail = mtd->oobsize - (nand->autooob->eccbytes + 1);
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}
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/*
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* Board-specific NAND initialization. The following members of the
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* argument are board-specific (per include/linux/mtd/nand_new.h):
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* - IO_ADDR_R?: address to read the 8 I/O lines of the flash device
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* - IO_ADDR_W?: address to write the 8 I/O lines of the flash device
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* - hwcontrol: hardwarespecific function for accesing control-lines
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* - dev_ready: hardwarespecific function for accesing device ready/busy line
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* - enable_hwecc?: function to enable (reset) hardware ecc generator. Must
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* only be provided if a hardware ECC is available
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* - eccmode: mode of ecc, see defines
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* - chip_delay: chip dependent delay for transfering data from array to
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* read regs (tR)
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* - options: various chip options. They can partly be set to inform
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* nand_scan about special functionality. See the defines for further
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* explanation
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* Members with a "?" were not set in the merged testing-NAND branch,
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* so they are not set here either.
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*/
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void board_nand_init(struct nand_chip *nand)
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{
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int gpmc_config=0;
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cs = 0;
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while (cs <= GPMC_MAX_CS) {
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/* Each GPMC set for a single CS is at offset 0x30 */
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/* already remapped for us */
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gpmc_cs_base_add = (GPMC_CONFIG_CS0 + (cs*0x30));
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/* xloader/Uboot would have written the NAND type for us
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* -NOTE This is a temporary measure and cannot handle ONENAND.
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* The proper way of doing this is to pass the setup of u-boot up to kernel
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* using kernel params - something on the lines of machineID
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*/
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/* Check if NAND type is set */
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if ((__raw_readl(gpmc_cs_base_add + GPMC_CONFIG1) & 0xC00)==0x800) {
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/* Found it!! */
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break;
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}
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cs++;
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}
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if (cs > GPMC_MAX_CS) {
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printk ("NAND: Unable to find NAND settings in GPMC Configuration - quitting\n");
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}
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gpmc_config = __raw_readl(GPMC_CONFIG);
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/* Disable Write protect */
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gpmc_config |= 0x10;
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__raw_writel(gpmc_config, GPMC_CONFIG);
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nand->IO_ADDR_R = (void *)gpmc_cs_base_add + GPMC_NAND_DAT;
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nand->IO_ADDR_W = (void *)gpmc_cs_base_add + GPMC_NAND_CMD;
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nand->hwcontrol = omap_nand_hwcontrol;
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nand->options = NAND_NO_PADDING | NAND_CACHEPRG | NAND_NO_AUTOINCR |
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NAND_BUSWIDTH_16 | NAND_NO_AUTOINCR;
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nand->read_buf = omap_nand_read_buf;
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nand->write_buf = omap_nand_write_buf;
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#if (CFG_HW_ECC_ROMCODE)
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nand->eccmode = NAND_ECC_HW3_512;
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nand->autooob = &hw_nand_oob_64;
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nand->eccsize = 512;
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nand->eccbytes = 3;
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nand->eccsteps = 4;
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nand->enable_hwecc = omap_enable_hwecc;
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nand->correct_data = omap_correct_data;
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nand->calculate_ecc = omap_calculate_ecc;
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omap_hwecc_init(nand);
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#else
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nand->eccmode = NAND_ECC_SOFT;
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#if (CFG_SW_ECC_512)
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nand->eccsize = 512;
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#else
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nand->eccsize = 256;
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#endif
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#endif
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/* if RDY/BSY line is connected to OMAP then use the omap ready funcrtion
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* and the generic nand_wait function which reads the status register after
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* monitoring the RDY/BSY line. Otherwise use a standard chip delay which
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* is slightly more than tR (AC Timing) of the NAND device and read the
|
|
* status register until you get a failure or success
|
|
*/
|
|
|
|
#if 0
|
|
nand->dev_ready = omap_nand_dev_ready;
|
|
#else
|
|
nand->waitfunc = omap_nand_wait;
|
|
nand->chip_delay = 50*2;
|
|
#endif
|
|
|
|
#if (CONFIG_FASTBOOT)
|
|
/* Initialize the name of fastboot flash name mappings */
|
|
fastboot_ptentry ptn[7] = {
|
|
{
|
|
.name = "xloader",
|
|
.start = 0x0000000,
|
|
.length = 0x0020000,
|
|
/* Written into the first 4 0x20000 blocks
|
|
Use HW ECC */
|
|
.flags = FASTBOOT_PTENTRY_FLAGS_WRITE_I |
|
|
FASTBOOT_PTENTRY_FLAGS_WRITE_HW_ECC,
|
|
},
|
|
|
|
{
|
|
.name = "bootloader",
|
|
.start = 0x0080000,
|
|
.length = 0x0180000, /* 1.5 M */
|
|
/* Skip bad blocks on write
|
|
Use HW ECC */
|
|
.flags = FASTBOOT_PTENTRY_FLAGS_WRITE_I |
|
|
FASTBOOT_PTENTRY_FLAGS_WRITE_HW_ECC,
|
|
},
|
|
{
|
|
.name = "environment",
|
|
.start = SMNAND_ENV_OFFSET, /* set in config file */
|
|
.length = 0x0040000,
|
|
.flags = FASTBOOT_PTENTRY_FLAGS_WRITE_HW_ECC |
|
|
FASTBOOT_PTENTRY_FLAGS_WRITE_ENV,
|
|
},
|
|
|
|
{
|
|
.name = "kernel",
|
|
/* Test with start close to bad block
|
|
The is dependent on the individual board.
|
|
Change to what is required */
|
|
/* .start = 0x0a00000, */
|
|
|
|
/* The real start */
|
|
.start = 0x0200000,
|
|
.length = 0x1D00000, /* 30M */
|
|
.flags = FASTBOOT_PTENTRY_FLAGS_WRITE_HW_ECC |
|
|
FASTBOOT_PTENTRY_FLAGS_WRITE_I,
|
|
},
|
|
#ifndef CFG_NAND_YAFFS_WRITE
|
|
#warn "CFG_NAND_YAFFS_WRITE must be defined"
|
|
#endif
|
|
{
|
|
.name = "system",
|
|
.start = 0x2000000,
|
|
.flags = FASTBOOT_PTENTRY_FLAGS_WRITE_HW_ECC |
|
|
FASTBOOT_PTENTRY_FLAGS_WRITE_YAFFS,
|
|
},
|
|
{
|
|
.name = "userdata",
|
|
.start = 0xD400000,
|
|
.length = 0x4000000, /* 64M */
|
|
.flags = FASTBOOT_PTENTRY_FLAGS_WRITE_HW_ECC |
|
|
FASTBOOT_PTENTRY_FLAGS_WRITE_YAFFS,
|
|
},
|
|
{
|
|
.name = "cache",
|
|
.start = 0x11400000,
|
|
.length = 0x2000000, /* 32M */
|
|
.flags = FASTBOOT_PTENTRY_FLAGS_WRITE_HW_ECC |
|
|
FASTBOOT_PTENTRY_FLAGS_WRITE_YAFFS,
|
|
},
|
|
};
|
|
int i;
|
|
for (i = 0; i < 7; i++)
|
|
fastboot_flash_add_ptn (&ptn[i]);
|
|
|
|
#endif
|
|
|
|
}
|
|
|
|
|
|
#endif /* (CONFIG_COMMANDS & CFG_CMD_NAND) */
|
|
|