509 lines
11 KiB
ArmAsm
509 lines
11 KiB
ArmAsm
/*
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* G-Sample Board specific setup info
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*
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* (C) Copyright 2004-2005
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* Texas Instruments, <www.ti.com>
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* Kshitij Gupta <Kshitij@ti.com>
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* Jian Zhang <jzhang@ti.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <config.h>
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#include <version.h>
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#if defined(CONFIG_OMAPV1030)
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#include <./configs/omap1510.h>
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#endif
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_TEXT_BASE:
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.word TEXT_BASE /* sdram load addr from config.mk */
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.globl platformsetup
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platformsetup:
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/*------------------------------------------------------*
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* Set up ARM CLM registers (IDLECT1) *
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*------------------------------------------------------*/
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ldr r0, REG_ARM_IDLECT1
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ldr r1, VAL_ARM_IDLECT1
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str r1, [r0]
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/*------------------------------------------------------*
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* Set up ARM CLM registers (IDLECT2) *
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*------------------------------------------------------*/
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ldr r0, REG_ARM_IDLECT2
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ldr r1, VAL_ARM_IDLECT2
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str r1, [r0]
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/*------------------------------------------------------*
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* Set up ARM CLM registers (IDLECT3) *
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*------------------------------------------------------*/
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ldr r0, REG_ARM_IDLECT3
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ldr r1, VAL_ARM_IDLECT3
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str r1, [r0]
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mov r1, #0x05 /* PER_EN bit */
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ldr r0, REG_ARM_RSTCT2
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strh r1, [r0] /* CLKM; Peripheral reset. */
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/* check lock bit is not good enough:
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when boot from NOR flash and control goes here
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lock bit is set, ADPLL1 reg1 is zero. This is x2
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mode which is not what we want. We want x16.
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*/
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#if 0
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/* check if ADPLL LOCK bit (BIT 4) set or not */
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ldr r0, REG_ADPLL1_3
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ldrh r1, [r0]
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ands r1, r1, #0x10 /* Check the LOCK bit.*/
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bne skip_adpll /* skip if already locked*/
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#else
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/* Load physical SDRAM base. */
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mov r0, #0x10000000
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/* Get current execution location. */
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mov r1, pc
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/* Compare. */
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cmp r1, r0
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/* Skip over ADPLL initialization if running from SDRAM. */
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bge skip_adpll
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#endif
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/* Set CLKM to bypass mode so DPLL multiplier/divider can be changed */
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/* Otherwise DPLL won't lock */
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/* I supposedly need to enable the dsp clock before switching */
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ldr r1, VAL1_ARM_SYSST
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ldr r0, REG_ARM_SYSST
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strh r1, [r0]
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mov r0, #0x400
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1:
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subs r0, r0, #0x1 /* wait for any bubbles to finish */
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bne 1b
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ldr r1, VAL1_ARM_CKCTL /* for now, let arm/dsp/tc be dpll/2 */
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ldr r0, REG_ARM_CKCTL
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strh r1, [r0]
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/* a few nops to let settle */
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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/* setup ADPLL1 */
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/* Ramp up the clock to 13*16Mhz */
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ldr r0, REG_ADPLL1_1 /* X16 */
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mov r1, #0x140
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strh r1, [r0]
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/* clear and set enable bit (BIT 14) */
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ldr r0, REG_ADPLL1_3
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mov r1, #0
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strh r1, [r0]
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mov r1, #0x4000
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strh r1, [r0]
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/* set, clear, and set INITZ bit (BIT 7) */
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orr r1, r1, #0x80
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strh r1, [r0]
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mov r1, #0x4000
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strh r1, [r0]
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orr r1, r1, #0x80
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strh r1, [r0]
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/* get all bits right */
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ldr r1, VAL_ADPLL1_3
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strh r1, [r0]
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/* wait until LOCK bit (BIT 4) set */
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2:
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ldrh r1, [r0]
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ands r1, r1, #0x10 /* Check the LOCK bit.*/
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beq 2b /* loop until bit goes hi. */
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lock_end:
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/* Now set CLKM to Sync-Scalable */
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/* I supposedly need to enable the dsp clock before switching */
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ldr r1, VAL2_ARM_SYSST
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ldr r0, REG_ARM_SYSST
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strh r1, [r0]
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mov r0, #0x400
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3:
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subs r0, r0, #0x1 /* wait for any bubbles to finish */
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bne 3b
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ldr r1, VAL2_ARM_CKCTL /* for now, let arm/dsp/tc be dpll/2 */
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ldr r0, REG_ARM_CKCTL
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strh r1, [r0]
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/* a few nops to let settle */
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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skip_adpll:
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/*------------------------------------------------------*
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* Turn off the watchdog during init... *
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*------------------------------------------------------*/
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ldr r0, REG_WATCHDOG
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ldr r1, WATCHDOG_VAL1
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str r1, [r0]
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ldr r1, WATCHDOG_VAL2
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str r1, [r0]
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ldr r0, REG_WSPRDOG
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ldr r1, WSPRDOG_VAL1
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str r1, [r0]
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ldr r0, REG_WWPSDOG
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watch1Wait:
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ldr r1, [r0]
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tst r1, #0x10
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bne watch1Wait
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ldr r0, REG_WSPRDOG
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ldr r1, WSPRDOG_VAL2
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str r1, [r0]
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ldr r0, REG_WWPSDOG
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watch2Wait:
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ldr r1, [r0]
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tst r1, #0x10
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bne watch2Wait
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/* Set memory timings corresponding to the new clock speed */
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/* Check execution location to determine current execution location
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* and branch to appropriate initialization code.
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*/
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/* Load physical SDRAM base. */
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mov r0, #0x10000000
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/* Get current execution location. */
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mov r1, pc
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/* Compare. */
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cmp r1, r0
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/* Skip over EMIF-fast initialization if running from SDRAM. */
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bge skip_sdram
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/* Enable EMIFF TC Doubler in OMAP1710 */
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ldr r0, REG_EMIFF_DOUBLER
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mov r1, #0x1
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str r1, [r0]
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/*
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* Delay for SDRAM initialization.
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*/
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mov r3, #0x1800 /* value should be checked */
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4:
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subs r3, r3, #0x1 /* Decrement count */
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bne 4b
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/*
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* Set SDRAM control values. Disable refresh before MRS command.
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*/
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/* mobile ddr operation */
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ldr r0, REG_SDRAM_OPERATION //cc80
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mov r2, #07
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str r2, [r0]
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/* config register */
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ldr r0, REG_SDRAM_CONFIG //cc20
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ldr r1, SDRAM_CONFIG_VAL
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str r1, [r0]
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/* manual command register */
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ldr r0, REG_SDRAM_MANUAL_CMD //cc84
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/* issue set cke high */
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mov r1, #CMD_SDRAM_CKE_SET_HIGH //#7
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str r1, [r0]
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/* issue nop */
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mov r1, #CMD_SDRAM_NOP //#0
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str r1, [r0]
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mov r2, #0x0100
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waitMDDR1:
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subs r2, r2, #1
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bne waitMDDR1 /* delay loop */
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/* issue precharge */
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mov r1, #CMD_SDRAM_PRECHARGE
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str r1, [r0]
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/* issue autorefresh x 2 */
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mov r1, #CMD_SDRAM_AUTOREFRESH
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str r1, [r0]
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str r1, [r0]
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/* mrs register ddr mobile */
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ldr r0, REG_SDRAM_MRS
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mov r1, #0x33
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str r1, [r0]
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/* emrs1 low-power register */
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ldr r0, REG_SDRAM_EMRS1
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/* self refresh on all banks */
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mov r1, #0
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str r1, [r0]
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ldr r0, REG_DLL_URD_CONTROL
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ldr r1, DLL_URD_CONTROL_VAL
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str r1, [r0]
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ldr r0, REG_DLL_LRD_CONTROL
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ldr r1, DLL_LRD_CONTROL_VAL
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str r1, [r0]
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ldr r0, REG_DLL_WRT_CONTROL
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ldr r1, DLL_WRT_CONTROL_VAL
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str r1, [r0]
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/* delay loop */
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mov r2, #0x0100
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waitMDDR2:
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subs r2, r2, #1
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bne waitMDDR2
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/*
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* Delay for SDRAM initialization.
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*/
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mov r3, #0x1800
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5:
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subs r3, r3, #1 /* Decrement count. */
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bne 5b
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b common_tc
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skip_sdram:
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ldr r0, REG_SDRAM_CONFIG
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ldr r1, SDRAM_CONFIG_VAL
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str r1, [r0]
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common_tc:
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/* slow interface */
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ldr r1, VAL_TC_EMIFS_CONFIG
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ldr r0, REG_TC_EMIFS_CONFIG
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str r1, [r0]
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ldr r1, VAL_TC_EMIFS_CS0_CONFIG
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ldr r0, REG_TC_EMIFS_CS0_CONFIG
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str r1, [r0] /* Chip Select 0 */
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ldr r1, VAL_TC_EMIFS_CS1_CONFIG
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ldr r0, REG_TC_EMIFS_CS1_CONFIG
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str r1, [r0] /* Chip Select 1 */
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ldr r1, VAL_TC_EMIFS_CS2_CONFIG
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ldr r0, REG_TC_EMIFS_CS2_CONFIG
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str r1, [r0] /* Chip Select 2 */
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ldr r1, VAL_TC_EMIFS_CS3_CONFIG
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ldr r0, REG_TC_EMIFS_CS3_CONFIG
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str r1, [r0] /* Chip Select 3 */
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/* inserting additional 2 clock cycle hold time for testing LAN */
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ldr r0, REG_TC_EMIFS_CS2_ADVANCED
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ldr r1, VAL_TC_EMIFS_CS2_ADVANCED
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str r1, [r0]
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/* Start MPU Timer 1 */
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ldr r0, REG_MPU_LOAD_TIMER
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ldr r1, VAL_MPU_LOAD_TIMER
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str r1, [r0]
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ldr r0, REG_MPU_CNTL_TIMER
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ldr r1, VAL_MPU_CNTL_TIMER
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str r1, [r0]
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/* back to arch calling code */
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mov pc, lr
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/* the literal pools origin */
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.ltorg
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REG_TC_EMIFS_CONFIG: /* 32 bits */
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.word 0xfffecc0c
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REG_TC_EMIFS_CS0_CONFIG: /* 32 bits */
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.word 0xfffecc10
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REG_TC_EMIFS_CS1_CONFIG: /* 32 bits */
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.word 0xfffecc14
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REG_TC_EMIFS_CS2_CONFIG: /* 32 bits */
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.word 0xfffecc18
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REG_TC_EMIFS_CS3_CONFIG: /* 32 bits */
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.word 0xfffecc1c
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REG_TC_EMIFS_CS2_ADVANCED: /* 32 bits */
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.word 0xfffecc58
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/* MPU clock/reset/power mode control registers */
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REG_ARM_CKCTL: /* 16 bits */
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.word 0xfffece00
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REG_ARM_IDLECT3: /* 16 bits */
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.word 0xfffece24
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REG_ARM_IDLECT2: /* 16 bits */
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.word 0xfffece08
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REG_ARM_IDLECT1: /* 16 bits */
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.word 0xfffece04
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REG_ARM_RSTCT2: /* 16 bits */
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.word 0xfffece14
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REG_ARM_SYSST: /* 16 bits */
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.word 0xfffece18
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/* ADPLL registers */
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REG_ADPLL1_1: /* 16 bits */
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.word 0xfffecf02
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REG_ADPLL1_3: /* 16 bits */
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.word 0xfffecf06
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VAL_ADPLL1_3:
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.word 0x0000dc98
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/* Watch Dog register */
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/* secure watchdog stop */
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REG_WSPRDOG:
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.word 0xfffeb048
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/* watchdog write pending */
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REG_WWPSDOG:
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.word 0xfffeb034
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WSPRDOG_VAL1:
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.word 0x0000aaaa
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WSPRDOG_VAL2:
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.word 0x00005555
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/* SDRAM config is: auto refresh enabled, 16 bit 4 bank,
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counter @8192 rows, 10 ns, 8 burst */
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REG_SDRAM_CONFIG:
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.word 0xfffecc20
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/* Operation register */
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REG_SDRAM_OPERATION:
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.word 0xfffecc80
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REG_EMIFF_DOUBLER:
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.word 0xfffecc60
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/* Manual command register */
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REG_SDRAM_MANUAL_CMD:
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.word 0xfffecc84
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/* SDRAM MRS (New) config is: CAS latency is 2, burst length 8 */
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REG_SDRAM_MRS:
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.word 0xfffecc70
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/* SDRAM MRS (New) config is: CAS latency is 2, burst length 8 */
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REG_SDRAM_EMRS1:
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.word 0xfffecc78
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/* WRT DLL register */
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REG_DLL_WRT_CONTROL:
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.word 0xfffecc64
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DLL_WRT_CONTROL_VAL:
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.word 0x00000006
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/* URD DLL register */
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REG_DLL_URD_CONTROL:
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.word 0xfffeccc0
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DLL_URD_CONTROL_VAL:
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.word 0x00000006
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/* LRD DLL register */
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REG_DLL_LRD_CONTROL:
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.word 0xfffecccc
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REG_WATCHDOG:
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.word 0xfffec808
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REG_MPU_LOAD_TIMER:
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.word 0xfffec600
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REG_MPU_CNTL_TIMER:
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.word 0xfffec500
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/* 96 MHz Samsung Mobile DDR */
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SDRAM_CONFIG_VAL:
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.word 0x0003f7f6
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DLL_LRD_CONTROL_VAL:
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.word 0x00000006
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VAL1_ARM_CKCTL:
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.word 0x1555
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VAL2_ARM_CKCTL:
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.word 0x350e
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VAL1_ARM_SYSST:
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.word 0x2800
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VAL2_ARM_SYSST:
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.word 0x1001
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VAL_DPLL1_CTL:
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.word 0x2810
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VAL_TC_EMIFS_CONFIG:
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.word 0x00000010
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VAL_TC_EMIFS_CS0_CONFIG:
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.word 0x0017000c
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VAL_TC_EMIFS_CS1_CONFIG:
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.word 0x0010fffb
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/* EMIFS CS2 Configuration Register: A/D Multiplexed, 8 RWS, 8 WWS,
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WELEN = 4, 1 BT WST, Asynchronous Read mode & Ref_Clk = TC_Clock */
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VAL_TC_EMIFS_CS2_CONFIG:
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.word 0x0040488b
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VAL_TC_EMIFS_CS3_CONFIG:
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.word 0xffc0fff3
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/* EMIFS CS2 Advanced Configuration Register: ADV hold = 2 Ref_Clk cycles,
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OE SETUP = 3 */
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VAL_TC_EMIFS_CS2_ADVANCED:
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.word 0x00000103
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VAL_TC_EMIFF_SDRAM_CONFIG:
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.word 0x010290fc
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VAL_TC_EMIFF_MRS:
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.word 0x00000027
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VAL_ARM_IDLECT1:
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.word 0x000014c6
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VAL_ARM_IDLECT2:
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.word 0x000009ff
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VAL_ARM_IDLECT3:
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.word 0x0000003f
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WATCHDOG_VAL1:
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.word 0x000000f5
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WATCHDOG_VAL2:
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.word 0x000000a0
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VAL_MPU_LOAD_TIMER:
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.word 0xffffffff
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VAL_MPU_CNTL_TIMER:
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.word 0xffffffa1
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/* command values */
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.equ CMD_SDRAM_NOP, 0x00000000
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.equ CMD_SDRAM_PRECHARGE, 0x00000001
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.equ CMD_SDRAM_AUTOREFRESH, 0x00000002
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.equ CMD_SDRAM_CKE_SET_HIGH, 0x00000007
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