363 lines
12 KiB
C
363 lines
12 KiB
C
/*
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* (C) Copyright 2009 - 2010 Texas Instruments SA.
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*
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* Configuration settings for the 3730 OVERO board.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/*
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* High Level Configuration Options
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*/
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#define CONFIG_ARMCORTEXA8 1 /* This is an ARM V7 CPU core */
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#define CONFIG_OMAP 1 /* in a TI OMAP core */
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#define CONFIG_OMAP36XX 1 /* which is a 36XX */
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#define CONFIG_OMAP34XX 1 /* reuse the 34XX setup */
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#define CONFIG_OMAP3430 1 /* which is in a 3430 */
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#define CONFIG_3730OVERO 1
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#define CONFIG_3530OVERO 1
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//#define CONFIG_FASTBOOT 1 /* Using fastboot interface */
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#define CONFIG_TWL4030_USB 1 /* Initialize twl usb */
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//#define CONFIG_3430_AS_3410 1 /* true for 3430 in 3410 mode */
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#include <asm/arch/cpu.h> /* get chip and board defs */
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/* Clock Defines */
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#define V_OSCK 26000000 /* Clock output from T2 */
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#define V_SCLK (V_OSCK >> 1)
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#define PRCM_CLK_CFG2_400MHZ 1 /* VDD2=1.15v - 200MHz DDR */
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//#define PRCM_CLK_CFG2_332MHZ 1 /* VDD2=1.15v - 166MHz DDR */
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#define PRCM_PCLK_OPP2 1 /* ARM=500MHz - VDD1=1.20v */
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#undef CONFIG_USE_IRQ /* no support for IRQs */
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#define CONFIG_MISC_INIT_R
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#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
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#define CONFIG_SETUP_MEMORY_TAGS 1
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#define CONFIG_INITRD_TAG 1
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#define CONFIG_REVISION_TAG 1
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/*
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* Size of malloc() pool
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*/
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#define CFG_ENV_SIZE SZ_128K /* Total Size Environment Sector */
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#define CFG_MALLOC_LEN (CFG_ENV_SIZE + SZ_128K)
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#define CFG_GBL_DATA_SIZE 128 /* bytes reserved for initial data */
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/*
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* Hardware drivers
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*/
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/*
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* NS16550 Configuration:
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*/
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#define V_NS16550_CLK (48000000) /* 48 MHz */
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#define CFG_NS16550
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#define CFG_NS16550_SERIAL
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#define CFG_NS16550_REG_SIZE (-4)
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#define CFG_NS16550_CLK V_NS16550_CLK
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//#define CFG_NS16550_COM1 OMAP34XX_UART1
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//#define CFG_NS16550_COM2 OMAP34XX_UART2
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#define CFG_NS16550_COM3 OMAP34XX_UART3
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/*
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* select serial console configuration
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*/
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#define CONFIG_SERIAL3 3 /* UART3 on board */
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/* allow to overwrite serial and ethaddr */
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#define CONFIG_ENV_OVERWRITE
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#define CONFIG_CONS_INDEX 3
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#define CONFIG_BAUDRATE 115200
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#define CFG_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, 115200}
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#define CONFIG_MMC 1
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#define CFG_MMC_BASE 0xF0000000
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#define CONFIG_DOS_PARTITION 1
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#ifndef CONFIG_OPTIONAL_NOR_POPULATED
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//#define C_MSK (CFG_CMD_FLASH | CFG_CMD_IMLS)
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#define C_MSK (CFG_CMD_IMLS | CFG_CMD_FLASH)
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#endif
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/* Config CMD */
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#define CONFIG_COMMANDS ((CFG_CMD_I2C | CONFIG_CMD_DFL |\
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CFG_CMD_FAT | CFG_CMD_MMC ) \
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& ~(C_MSK | CFG_CMD_NET | CFG_CMD_NFS | \
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CFG_CMD_FPGA | CFG_CMD_IMI | CFG_CMD_NAND))
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/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
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#include <cmd_confdefs.h>
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#if (CONFIG_COMMANDS & CFG_CMD_I2C)
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#define CFG_I2C_SPEED 400
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#define CFG_I2C_SLAVE 1
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#define CFG_I2C_BUS 0
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#define CFG_I2C_BUS_SELECT 1
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#define CONFIG_DRIVER_OMAP34XX_I2C 1
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#endif
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#ifdef CFG_NAND
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/*
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* Board NAND Info.
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*/
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#define CFG_NAND_ADDR NAND_BASE /* physical address to access nand*/
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#define CFG_NAND_BASE NAND_BASE /* physical address to access nand at CS0*/
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#define CFG_NAND_WIDTH_16
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#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
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#define SECTORSIZE 512
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/* To use the 256/512 byte s/w ecc define CFG_SW_ECC_(256/512) */
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/* Use the 512 byte ROM CODE HW ecc */
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#define CFG_HW_ECC_ROMCODE 1
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#define NAND_ALLOW_ERASE_ALL
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#define ADDR_COLUMN 1
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#define ADDR_PAGE 2
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#define ADDR_COLUMN_PAGE 3
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#define NAND_ChipID_UNKNOWN 0x00
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#define NAND_MAX_FLOORS 1
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#define NAND_NO_RB 1
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#define CFG_NAND_WP
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#endif // #ifdef CFG_NAND
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#define NAND_MAX_CHIPS 1 // needed by nand.h even though CFG_CMD_NAND is undefined! hm...
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#define CONFIG_BOOTDELAY 3
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"loadaddr=0x81c00000\0" \
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"nandloadaddr=0x81000000\0" \
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"console=ttyS2,115200n8\0" \
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"mmcroot=/dev/mmcblk0p2\0" \
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"nandroot=/dev/ram0\0" \
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"mmcargs=setenv bootargs console=${console} " \
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"root=${mmcroot} rootdelay=2\0" \
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"nandargs=setenv bootargs console=${console} " \
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"rootdelay=2\0" \
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"loaduimage=fatload mmc 0:1 ${loadaddr} uImage\0"\
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"mmcboot=echo Booting from mmc ...;" \
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" run mmcargs;" \
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" bootm ${loadaddr}\0" \
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"nandboot=echo Booting from nand ...;" \
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" nand unlock;" \
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" nand read.i ${nandloadaddr}" \
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" ${kernel_nand_offset}" \
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" ${kernel_nand_size};" \
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" run nandargs;" \
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" bootm ${nandloadaddr}\0" \
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"autoboot=if mmc init 0; then" \
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" run loaduimage;" \
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" run mmcboot;" \
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" else run nandboot;" \
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" fi;\0" \
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#define CONFIG_BOOTCOMMAND "run autoboot"
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#define CONFIG_AUTO_COMPLETE 1
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/*
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* Miscellaneous configurable options
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*/
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#define V_PROMPT "OMAP3730 OVERO # "
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#define CFG_LONGHELP /* undef to save memory */
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#define CFG_PROMPT V_PROMPT
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#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
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/* Print Buffer Size */
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#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)
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#define CFG_MAXARGS 24 /* max number of command args */
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#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
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#define CFG_MEMTEST_START (OMAP34XX_SDRC_CS0) /* memtest works on */
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#define CFG_MEMTEST_END (OMAP34XX_SDRC_CS0+SZ_31M)
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#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
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#define CFG_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load address */
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/* 2430 has 12 GP timers, they can be driven by the SysClk (12/13/19.2) or by
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* 32KHz clk, or from external sig. This rate is divided by a local divisor.
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*/
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#define V_PVT 7
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#define CFG_TIMERBASE OMAP34XX_GPT2
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#define CFG_PVT V_PVT /* 2^(pvt+1) */
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#define CFG_HZ ((V_SCLK)/(2 << CFG_PVT))
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/*-----------------------------------------------------------------------
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* Stack sizes
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*
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* The stack sizes are set up in start.S using the settings below
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*/
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#define CONFIG_STACKSIZE SZ_128K /* regular stack */
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#ifdef CONFIG_USE_IRQ
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#define CONFIG_STACKSIZE_IRQ SZ_4K /* IRQ stack */
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#define CONFIG_STACKSIZE_FIQ SZ_4K /* FIQ stack */
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#endif
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/*-----------------------------------------------------------------------
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* Physical Memory Map
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*/
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#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
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#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
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#define PHYS_SDRAM_1_SIZE SZ_32M /* at least 32 meg */
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#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
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/* SDRAM Bank Allocation method */
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/*#define SDRC_B_R_C 1 */
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/*#define SDRC_B1_R_B0_C 1 */
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#define SDRC_R_B_C 1
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/*-----------------------------------------------------------------------
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* FLASH and environment organization
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*/
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/* **** PISMO SUPPORT *** */
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/* Configure the PISMO */
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/** REMOVE ME ***/
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#define PISMO1_NOR_SIZE_SDPV2 GPMC_SIZE_128M
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#define PISMO1_NOR_SIZE GPMC_SIZE_64M
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#define PISMO1_NAND_SIZE GPMC_SIZE_128M
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#define PISMO1_ONEN_SIZE GPMC_SIZE_128M
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#define DBG_MPDB_SIZE GPMC_SIZE_16M
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#define PISMO2_SIZE 0
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#define SERIAL_TL16CP754C_SIZE GPMC_SIZE_16M
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#define CFG_MAX_FLASH_SECT (520) /* max number of sectors on one chip */
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#define CFG_MAX_FLASH_BANKS 2 /* max number of flash banks */
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#define CFG_MONITOR_LEN SZ_256K /* Reserve 2 sectors */
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#define PHYS_FLASH_SIZE_SDPV2 SZ_128M
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#define PHYS_FLASH_SIZE SZ_32M
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#define CFG_FLASH_BASE boot_flash_base
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#define PHYS_FLASH_SECT_SIZE boot_flash_sec
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/* Dummy declaration of flash banks to get compilation right */
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#define CFG_FLASH_BANKS_LIST {0, 0}
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#define CFG_MONITOR_BASE CFG_FLASH_BASE /* Monitor at start of flash */
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#if 0
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#define CFG_ENV_IS_IN_NAND 1
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#define ENV_IS_VARIABLE 1
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#else
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#define CFG_ENV_IS_NOWHERE 1
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#endif
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#ifdef CONFIG_OPTIONAL_NOR_POPULATED
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# define CFG_ENV_IS_IN_FLASH 1
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#endif
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#define SMNAND_ENV_OFFSET 0x1c0000 /* environment starts here */
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#define CFG_ENV_SECT_SIZE boot_flash_sec
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#define CFG_ENV_OFFSET boot_flash_off
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#define CFG_ENV_ADDR boot_flash_env_addr
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/*-----------------------------------------------------------------------
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* CFI FLASH driver setup
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*/
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#ifndef CONFIG_OPTIONAL_NOR_POPULATED
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#define CFG_NO_FLASH 1 /* Disable NOR Flash support */
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#else
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#define CFG_FLASH_CFI 1 /* Flash memory is CFI compliant */
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#define CFG_FLASH_CFI_DRIVER 1 /* Use drivers/cfi_flash.c */
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#if (!ENV_IS_VARIABLE)
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/* saveenv fails when this variable is defined.
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If env is variable, do not use buffered writes */
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#define CFG_FLASH_USE_BUFFER_WRITE 1 /* Use buffered writes (~10x faster) */
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#endif
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#define CFG_FLASH_PROTECTION 1 /* Use hardware sector protection */
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#define CFG_FLASH_QUIET_TEST 1 /* Dont crib abt missing chips */
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#define CFG_FLASH_CFI_WIDTH 0x02
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/* timeout values are in ticks */
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#define CFG_FLASH_ERASE_TOUT (100*CFG_HZ) /* Timeout for Flash Erase */
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#define CFG_FLASH_WRITE_TOUT (100*CFG_HZ) /* Timeout for Flash Write */
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/* Flash banks JFFS2 should use */
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#define CFG_MAX_MTD_BANKS (CFG_MAX_FLASH_BANKS+CFG_MAX_NAND_DEVICE)
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#define CFG_JFFS2_MEM_NAND
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#define CFG_JFFS2_FIRST_BANK CFG_MAX_FLASH_BANKS /* use flash_info[2] */
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#define CFG_JFFS2_NUM_BANKS 1
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#define CONFIG_LED_INFOnand_read_buf16
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#define CONFIG_LED_LEN 16
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#endif /* optional NOR flash */
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#ifndef __ASSEMBLY__
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extern unsigned int nand_cs_base;
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extern unsigned int boot_flash_base;
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extern volatile unsigned int boot_flash_env_addr;
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extern unsigned int boot_flash_off;
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extern unsigned int boot_flash_sec;
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extern unsigned int boot_flash_type;
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#endif
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#define WRITE_NAND_COMMAND(d, adr) __raw_writew(d, (nand_cs_base + GPMC_NAND_CMD))
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#define WRITE_NAND_ADDRESS(d, adr) __raw_writew(d, (nand_cs_base + GPMC_NAND_ADR))
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#define WRITE_NAND(d, adr) __raw_writew(d, (nand_cs_base + GPMC_NAND_DAT))
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#define READ_NAND(adr) __raw_readw((nand_cs_base + GPMC_NAND_DAT))
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/* Other NAND Access APIs */
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#define NAND_WP_OFF() do {*(volatile u32 *)(GPMC_CONFIG) |= 0x00000010;} while(0)
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#define NAND_WP_ON() do {*(volatile u32 *)(GPMC_CONFIG) &= ~0x00000010;} while(0)
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#define NAND_DISABLE_CE(nand)
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#define NAND_ENABLE_CE(nand)
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#define NAND_WAIT_READY(nand) udelay(10)
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/* Fastboot variables */
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#define CFG_FASTBOOT_TRANSFER_BUFFER (PHYS_SDRAM_1 + SZ_16M)
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#define CFG_FASTBOOT_TRANSFER_BUFFER_SIZE (SZ_256M - SZ_16M)
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#define CFG_FASTBOOT_PREBOOT_KEYS 1
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#define CFG_FASTBOOT_PREBOOT_KEY1 0x37 /* 'ok' */
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#define CFG_FASTBOOT_PREBOOT_KEY2 0x00 /* unused */
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#define CFG_FASTBOOT_PREBOOT_INITIAL_WAIT (0)
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#define CFG_FASTBOOT_PREBOOT_LOOP_MAXIMUM (1)
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#define CFG_FASTBOOT_PREBOOT_LOOP_WAIT (0)
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/* Yaffs variables */
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#define CFG_NAND_YAFFS_WRITE
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/* Command shell */
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#define CFG_HUSH_PARSER
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#define CFG_PROMPT_HUSH_PS2 "> "
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/* Clock command */
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#define CONFIG_CMD_CLOCK 1
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#define CONFIG_CMD_CLOCK_INFO_CPU 1
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/* Voltage command */
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#define CONFIG_CMD_VOLTAGE 1
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#endif /* __CONFIG_H */
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