378 lines
10 KiB
C
378 lines
10 KiB
C
/*
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* (C) Copyright 2009
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* Texas Instruments, <www.ti.com>
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* Richard Woodruff <r-woodruff2@ti.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/arch/cpu.h>
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#include <asm/io.h>
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#include <asm/arch/bits.h>
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#include <asm/arch/mem.h> /* get mem tables */
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#include <asm/arch/sys_proto.h>
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#include <asm/arch/sys_info.h>
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#include <asm/arch/rev.h>
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#include <i2c.h>
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/**************************************************************************
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* get_cpu_type() - Read the FPGA Debug registers and provide the DIP switch
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* settings
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* 1 is on
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* 0 is off
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* Will return Index of type of gpmc
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***************************************************************************/
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u32 get_gpmc0_type(void)
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{
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u8 cs;
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if(get_board_type() == SDP_3430_V2)
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/* change (S8-1:4=DS-2:0) to (S8-4:1=DS-2:0) */
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cs = ((cs & 8) >> 3) | ((cs & 4) >> 1) |
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((cs & 2) << 1) | ((cs & 1) << 3);
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else
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/* change (S8-1:3=DS-2:0) to (S8-3:1=DS-2:0) */
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cs = ((cs & 4) >> 2) | (cs & 2) | ((cs & 1) << 2);
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return (cs);
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}
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/****************************************************
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* get_cpu_type() - low level get cpu type
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* - no C globals yet.
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****************************************************/
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u32 get_cpu_type(void)
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{
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// fixme, need to get register defines for 3430
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return (CPU_3430);
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}
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/*
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* cpu_is_3410(void) - returns true for 3410
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*/
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u32 cpu_is_3410(void)
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{
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int status;
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if (get_cpu_rev() < CPU_3XX_ES20) {
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return 0;
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} else {
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/* read scalability status and return 1 for 3410*/
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status = __raw_readl(CONTROL_SCALABLE_OMAP_STATUS);
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/*
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* Check whether MPU frequency is set to 266 MHz which
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* is nominal for 3410. If yes return true else false
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*/
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if (((status >> 8) & 0x3) == 0x2)
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return 1;
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else
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return 0;
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}
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}
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/****************************************************
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* is_mem_sdr() - return 1 if mem type in use is SDR
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****************************************************/
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u32 is_mem_sdr(void)
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{
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volatile u32 *burst = (volatile u32 *)(SDRC_MR_0 + SDRC_CS0_OSET);
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if (*burst == SDP_SDRC_MR_0_SDR)
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return (1);
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return (0);
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}
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/***********************************************************
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* get_mem_type() - identify type of mDDR part used.
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***********************************************************/
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u32 get_mem_type(void)
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{
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/* Current SDP3430 uses 2x16 MDDR Infenion parts */
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return (DDR_DISCRETE);
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}
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/***********************************************************************
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* get_cs0_size() - get size of chip select 0/1
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************************************************************************/
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u32 get_sdr_cs_size(u32 offset)
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{
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u32 size;
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/* get ram size field */
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size = __raw_readl(SDRC_MCFG_0 + offset) >> 8;
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size &= 0x3FF; /* remove unwanted bits */
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size *= SZ_2M; /* find size in MB */
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return (size);
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}
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/*
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* get_board_type() - get board type based on current production stats.
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* - NOTE-1-: 2 I2C EEPROMs will someday be populated with proper info.
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* when they are available we can get info from there. This should
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* be correct of all known boards up until today.
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* - NOTE-2- EEPROMs are populated but they are updated very slowly. To
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* avoid waiting on them we will use ES version of the chip to get info.
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* A later version of the FPGA migth solve their speed issue.
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*/
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u32 get_board_type(void)
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{
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if (get_cpu_rev() >= CPU_3XX_ES20)
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return SDP_3430_V2;
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else
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return SDP_3430_V1;
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}
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/******************************************************************
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* get_sysboot_value() - get init word settings
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******************************************************************/
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inline u32 get_sysboot_value(void)
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{
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return (0x0000003F & __raw_readl(CONTROL_STATUS));
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}
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/***************************************************************************
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* get_gpmc0_base() - Return current address hardware will be
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* fetching from. The below effectively gives what is correct, its a bit
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* mis-leading compared to the TRM. For the most general case the mask
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* needs to be also taken into account this does work in practice.
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* - for u-boot we currently map:
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* -- 0 to nothing,
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* -- 4 to flash
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* -- 8 to enent
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* -- c to wifi
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****************************************************************************/
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u32 get_gpmc0_base(void)
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{
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u32 b;
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b = __raw_readl(GPMC_CONFIG_CS0 + GPMC_CONFIG7);
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b &= 0x1F; /* keep base [5:0] */
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b = b << 24; /* ret 0x0b000000 */
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return (b);
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}
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/*******************************************************************
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* get_gpmc0_width() - See if bus is in x8 or x16 (mainly for nand)
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*******************************************************************/
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u32 get_gpmc0_width(void)
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{
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return (WIDTH_16BIT);
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}
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/*************************************************************************
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* get_board_rev() - setup to pass kernel board revision information
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* returns:(bit[0-3] sub version, higher bit[7-4] is higher version)
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*************************************************************************/
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u32 get_board_rev(void)
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{
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/* Currently reading EEPROM reg to get UI board version and try it out
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*/
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#if 0
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if (!check_uieeprom_avail()) {
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/* timed out OR fpga rev not found!! */
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/* Assume 1.0 */
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return 0x01;
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}
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/* Move ahead to name location */
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ui_brd_name += 0x08;
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count = sizeof(enhanced_ui_brd_name) - 2;
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while ((enhanced_ui_brd_name[count] == ui_brd_name[count]) && count) {
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count--;
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}
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/* Match?? */
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if (!count) {
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/* Enhanced UI board.. SDP1.1 */
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return 0x11;
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}
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#endif
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/* Legacy UI - hope they are all 1.0 boards.. */
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return (0x10);
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}
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/*********************************************************************
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* display_board_info() - print banner with board info.
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*********************************************************************/
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void display_board_info(u32 btype)
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{
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enum {
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BOOTMODE_NOR,
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BOOTMODE_ONND,
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BOOTMODE_NAND,
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BOOTMODE_MMC
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};
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char *bootmode[] = {
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"NOR",
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"ONND",
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"NAND",
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"MMC"
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};
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u32 brev = get_board_rev();
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char cpu_3430s[] = "3630";
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char db_ver[] = "0.0"; /* board type */
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char mem_sdr[] = "mSDR"; /* memory type */
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char mem_ddr[] = "mDDR";
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char t_tst[] = "TST"; /* security level */
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char t_emu[] = "EMU";
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char t_hs[] = "HS";
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char t_gp[] = "GP";
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char unk[] = "?";
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#ifdef CONFIG_LED_INFO
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char led_string[CONFIG_LED_LEN] = { 0 };
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#endif
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#if defined(L3_200MHZ)
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char p_l3[] = "200";
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#elif defined(L3_165MHZ)
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char p_l3[] = "165";
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#elif defined(L3_110MHZ)
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char p_l3[] = "110";
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#elif defined(L3_133MHZ)
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char p_l3[] = "133";
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#elif defined(L3_100MHZ)
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char p_l3[] = "100";
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#endif
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#if defined(PRCM_PCLK_OPP1)
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char p_cpu[] = "1";
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#elif defined(PRCM_PCLK_OPP2)
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char p_cpu[] = "2";
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#elif defined(PRCM_PCLK_OPP3)
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char p_cpu[] = "3";
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#elif defined(PRCM_PCLK_OPP4)
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char p_cpu[] = "4";
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#endif
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char *cpu_s, *db_s, *mem_s, *sec_s;
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u32 cpu, rev, sec;
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rev = get_cpu_rev();
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cpu = get_cpu_type();
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sec = get_device_type();
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if (is_mem_sdr())
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mem_s = mem_sdr;
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else
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mem_s = mem_ddr;
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cpu_s = cpu_3430s;
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db_s = db_ver;
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db_s[0] += (brev >> 4) & 0xF;
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db_s[2] += brev & 0xF;
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switch (sec) {
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case TST_DEVICE:
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sec_s = t_tst;
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break;
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case EMU_DEVICE:
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sec_s = t_emu;
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break;
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case HS_DEVICE:
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sec_s = t_hs;
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break;
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case GP_DEVICE:
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sec_s = t_gp;
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break;
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default:
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sec_s = unk;
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}
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printf("OMAP%s-%s rev %d, CPU-OPP%s L3-%sMHz\n", cpu_s, sec_s, rev,
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p_cpu, p_l3);
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printf("OMAP3630 Strasbourg %s Version + %s (Boot %s)\n", db_s,
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mem_s, bootmode[BOOTMODE_MMC]);
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#ifdef CONFIG_LED_INFO
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/* Format: 0123456789ABCDEF
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* 3430C GP L3-100 NAND
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*/
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sprintf(led_string, "%5s%3s%3s %4s", cpu_s, sec_s, p_l3,
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bootmode[2]);
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/* reuse sec */
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for (sec = 0; sec < CONFIG_LED_LEN; sec += 2) {
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/* invert byte loc */
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u16 val = led_string[sec] << 8;
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val |= led_string[sec + 1];
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__raw_writew(val, LED_REGISTER + sec);
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}
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#endif
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}
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/********************************************************
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* get_base(); get upper addr of current execution
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*******************************************************/
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u32 get_base(void)
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{
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u32 val;
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__asm__ __volatile__("mov %0, pc \n":"=r"(val)::"memory");
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val &= 0xF0000000;
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val >>= 28;
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return (val);
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}
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/********************************************************
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* running_in_flash() - tell if currently running in
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* flash.
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*******************************************************/
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u32 running_in_flash(void)
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{
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if (get_base() < 4)
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return (1); /* in flash */
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return (0); /* running in SRAM or SDRAM */
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}
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/********************************************************
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* running_in_sram() - tell if currently running in
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* sram.
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*******************************************************/
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u32 running_in_sram(void)
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{
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if (get_base() == 4)
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return (1); /* in SRAM */
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return (0); /* running in FLASH or SDRAM */
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}
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/********************************************************
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* running_in_sdram() - tell if currently running in
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* sdram.
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*******************************************************/
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u32 running_in_sdram(void)
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{
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if (get_base() > 4)
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return (1); /* in sdram */
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return (0); /* running in SRAM or FLASH */
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}
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/***************************************************************
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* get_boot_type() - Is this an XIP type device or a stream one
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* bits 4-0 specify type. Bit 5 sys mem/perif
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***************************************************************/
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u32 get_boot_type(void)
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{
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u32 v;
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v = get_sysboot_value() & (BIT4 | BIT3 | BIT2 | BIT1 | BIT0);
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return v;
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}
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/*************************************************************
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* get_device_type(): tell if GP/HS/EMU/TST
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*************************************************************/
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u32 get_device_type(void)
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{
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int mode;
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mode = __raw_readl(CONTROL_STATUS) & (DEVICE_MASK);
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return (mode >>= 8);
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}
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