/* * Configuration settings for the Gumstix Overo board. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of * the License, or (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, * MA 02111-1307 USA */ #ifndef __CONFIG_H #define __CONFIG_H /* * High Level Configuration Options */ #define CONFIG_ARMCORTEXA8 1 /* This is an ARM V7 CPU core */ #define CONFIG_OMAP 1 /* in a TI OMAP core */ #define CONFIG_OMAP34XX 1 /* which is a 34XX */ #define CONFIG_OMAP3430 1 /* which is in a 3430 */ #define CONFIG_3530OVERO 1 /* working on OMAP3530 OVERO */ #define CONFIG_FASTBOOT 1 /* Using fastboot interface */ #define CONFIG_TWL4030_USB 1 /* Initialize twl usb */ //#define CONFIG_3430_AS_3410 1 /* true for 3430 in 3410 mode */ #include /* get chip and board defs */ /* Clock Defines */ #define V_OSCK 26000000 /* Clock output from T2 */ #define V_SCLK (V_OSCK >> 1) //#define PRCM_CLK_CFG2_266MHZ 1 /* VDD2=1.15v - 133MHz DDR */ #define PRCM_CLK_CFG2_332MHZ 1 /* VDD2=1.15v - 166MHz DDR */ #define PRCM_PCLK_OPP2 1 /* ARM=500MHz - VDD1=1.20v */ #undef CONFIG_USE_IRQ /* no support for IRQs */ #define CONFIG_MISC_INIT_R #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ #define CONFIG_SETUP_MEMORY_TAGS 1 #define CONFIG_INITRD_TAG 1 #define CONFIG_REVISION_TAG 1 /* * Size of malloc() pool */ #define CFG_ENV_SIZE SZ_128K /* Total Size Environment Sector */ #define CFG_MALLOC_LEN (CFG_ENV_SIZE + SZ_128K) #define CFG_GBL_DATA_SIZE 128 /* bytes reserved for initial data */ /* * Hardware drivers */ /* * NS16550 Configuration: */ //#define V_NS16550_CLK (1843200) /* 1.8432 Mhz */ #define V_NS16550_CLK (48000000) /* 1.8432 Mhz */ #define CFG_NS16550 #define CFG_NS16550_SERIAL #define CFG_NS16550_REG_SIZE (-4) #define CFG_NS16550_CLK V_NS16550_CLK //#define CFG_NS16550_COM1 OMAP34XX_UART1 //#define CFG_NS16550_COM2 OMAP34XX_UART2 #define CFG_NS16550_COM3 OMAP34XX_UART3 /* * select serial console configuration */ #define CONFIG_SERIAL3 3 /* UART3 on board */ /* allow to overwrite serial and ethaddr */ #define CONFIG_ENV_OVERWRITE #define CONFIG_CONS_INDEX 3 #define CONFIG_BAUDRATE 115200 #define CFG_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, 115200} #define CONFIG_MMC 1 #define CFG_MMC_BASE 0xF0000000 #define CONFIG_DOS_PARTITION 1 #ifndef CONFIG_OPTIONAL_NOR_POPULATED //#define C_MSK (CFG_CMD_FLASH | CFG_CMD_IMLS) #define C_MSK (CFG_CMD_IMLS | CFG_CMD_FLASH) #endif /* Config CMD */ #define CONFIG_COMMANDS ((CFG_CMD_I2C | CONFIG_CMD_DFL |\ CFG_CMD_FAT | CFG_CMD_MMC | \ CFG_CMD_NAND) & ~(C_MSK | CFG_CMD_NET | CFG_CMD_NFS | \ CFG_CMD_FPGA | CFG_CMD_IMI)) /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ #include #if (CONFIG_COMMANDS & CFG_CMD_I2C) #define CFG_I2C_SPEED 100 #define CFG_I2C_SLAVE 1 #define CFG_I2C_BUS 0 #define CFG_I2C_BUS_SELECT 1 #define CONFIG_DRIVER_OMAP34XX_I2C 1 #endif /* * Board NAND Info. */ #define CFG_NAND_ADDR NAND_BASE /* physical address to access nand*/ #define CFG_NAND_BASE NAND_BASE /* physical address to access nand at CS0*/ #define CFG_NAND_WIDTH_16 #define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ #define SECTORSIZE 512 /* To use the 256/512 byte s/w ecc define CFG_SW_ECC_(256/512) */ /* Use the 512 byte ROM CODE HW ecc */ #define CFG_HW_ECC_ROMCODE 1 #define NAND_ALLOW_ERASE_ALL #define ADDR_COLUMN 1 #define ADDR_PAGE 2 #define ADDR_COLUMN_PAGE 3 #define NAND_ChipID_UNKNOWN 0x00 #define NAND_MAX_FLOORS 1 #define NAND_MAX_CHIPS 1 #define NAND_NO_RB 1 #define CFG_NAND_WP #define CONFIG_BOOTDELAY 3 #define CONFIG_EXTRA_ENV_SETTINGS \ "loadaddr=0x82000000\0" \ "console=ttyS2,115200n8\0" \ "vram=12M\0" \ "dvimode=1024x768MR-16@60\0" \ "defaultdisplay=dvi\0" \ "mmcroot=/dev/mmcblk0p2 rw\0" \ "mmcrootfstype=ext3 rootwait\0" \ "nandroot=/dev/mtdblock4 rw\0" \ "nandrootfstype=jffs2\0" \ "mmcargs=setenv bootargs console=${console} " \ "vram=${vram} " \ "omapfb.mode=dvi:${dvimode} " \ "omapfb.debug=y " \ "omapdss.def_disp=${defaultdisplay} " \ "root=${mmcroot} " \ "rootfstype=${mmcrootfstype}\0" \ "nandargs=setenv bootargs console=${console} " \ "vram=${vram} " \ "omapfb.mode=dvi:${dvimode} " \ "omapfb.debug=y " \ "omapdss.def_disp=${defaultdisplay} " \ "root=${nandroot} " \ "rootfstype=${nandrootfstype}\0" \ "loadbootscript=fatload mmc 0 ${loadaddr} boot.scr\0" \ "bootscript=echo Running bootscript from mmc ...; " \ "autoscr ${loadaddr}\0" \ "loaduimage=fatload mmc 0 ${loadaddr} uImage\0" \ "mmcboot=echo Booting from mmc ...; " \ "run mmcargs; " \ "bootm ${loadaddr}\0" \ "nandboot=echo Booting from nand ...; " \ "run nandargs; " \ "nand read ${loadaddr} 280000 400000; " \ "bootm ${loadaddr}\0" \ #define CONFIG_BOOTCOMMAND \ "if mmc init 0; then " \ "if run loadbootscript; then " \ "run bootscript; " \ "else " \ "if run loaduimage; then " \ "run mmcboot; " \ "else run nandboot; " \ "fi; " \ "fi; " \ "else run nandboot; fi" #define CONFIG_AUTO_COMPLETE 1 /* * Miscellaneous configurable options */ #define V_PROMPT "OMAP3 OVERO # " #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT V_PROMPT #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ /* Print Buffer Size */ #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) #define CFG_MAXARGS 16 /* max number of command args */ #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ #define CFG_MEMTEST_START (OMAP34XX_SDRC_CS0) /* memtest works on */ #define CFG_MEMTEST_END (OMAP34XX_SDRC_CS0+SZ_31M) #undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ #define CFG_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load address */ /* 2430 has 12 GP timers, they can be driven by the SysClk (12/13/19.2) or by * 32KHz clk, or from external sig. This rate is divided by a local divisor. */ #define V_PVT 7 #define CFG_TIMERBASE OMAP34XX_GPT2 #define CFG_PVT V_PVT /* 2^(pvt+1) */ #define CFG_HZ ((V_SCLK)/(2 << CFG_PVT)) /*----------------------------------------------------------------------- * Stack sizes * * The stack sizes are set up in start.S using the settings below */ #define CONFIG_STACKSIZE SZ_128K /* regular stack */ #ifdef CONFIG_USE_IRQ #define CONFIG_STACKSIZE_IRQ SZ_4K /* IRQ stack */ #define CONFIG_STACKSIZE_FIQ SZ_4K /* FIQ stack */ #endif /*----------------------------------------------------------------------- * Physical Memory Map */ #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 #define PHYS_SDRAM_1_SIZE SZ_32M /* at least 32 meg */ #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 /* SDRAM Bank Allocation method */ #define SDRC_R_B_C 1 /*----------------------------------------------------------------------- * FLASH and environment organization */ /* **** PISMO SUPPORT *** */ /* Configure the PISMO */ /** REMOVE ME ***/ #define PISMO1_NOR_SIZE_SDPV2 GPMC_SIZE_128M #define PISMO1_NOR_SIZE GPMC_SIZE_64M #define PISMO1_NAND_SIZE GPMC_SIZE_128M #define PISMO1_ONEN_SIZE GPMC_SIZE_128M #define DBG_MPDB_SIZE GPMC_SIZE_16M #define PISMO2_SIZE 0 #define SERIAL_TL16CP754C_SIZE GPMC_SIZE_16M #define CFG_MAX_FLASH_SECT (520) /* max number of sectors on one chip */ #define CFG_MAX_FLASH_BANKS 2 /* max number of flash banks */ #define CFG_MONITOR_LEN SZ_256K /* Reserve 2 sectors */ #define PHYS_FLASH_SIZE_SDPV2 SZ_128M #define PHYS_FLASH_SIZE SZ_32M #define CFG_FLASH_BASE boot_flash_base #define PHYS_FLASH_SECT_SIZE boot_flash_sec /* Dummy declaration of flash banks to get compilation right */ #define CFG_FLASH_BANKS_LIST {0, 0} #define CFG_MONITOR_BASE CFG_FLASH_BASE /* Monitor at start of flash */ #if 1 #define CFG_ENV_IS_IN_NAND 1 #define ENV_IS_VARIABLE 1 #else #define CFG_ENV_IS_NOWHERE 1 #endif #ifdef CONFIG_OPTIONAL_NOR_POPULATED # define CFG_ENV_IS_IN_FLASH 1 #endif #define SMNAND_ENV_OFFSET 0x1c0000 /* environment starts here */ #define CFG_ENV_SECT_SIZE boot_flash_sec #define CFG_ENV_OFFSET boot_flash_off #define CFG_ENV_ADDR boot_flash_env_addr /*----------------------------------------------------------------------- * CFI FLASH driver setup */ #ifndef CONFIG_OPTIONAL_NOR_POPULATED #define CFG_NO_FLASH 1 /* Disable NOR Flash support */ #else #define CFG_FLASH_CFI 1 /* Flash memory is CFI compliant */ #define CFG_FLASH_CFI_DRIVER 1 /* Use drivers/cfi_flash.c */ #if (!ENV_IS_VARIABLE) /* saveenv fails when this variable is defined. If env is variable, do not use buffered writes */ #define CFG_FLASH_USE_BUFFER_WRITE 1 /* Use buffered writes (~10x faster) */ #endif #define CFG_FLASH_PROTECTION 1 /* Use hardware sector protection */ #define CFG_FLASH_QUIET_TEST 1 /* Dont crib abt missing chips */ #define CFG_FLASH_CFI_WIDTH 0x02 /* timeout values are in ticks */ #define CFG_FLASH_ERASE_TOUT (100*CFG_HZ) /* Timeout for Flash Erase */ #define CFG_FLASH_WRITE_TOUT (100*CFG_HZ) /* Timeout for Flash Write */ /* Flash banks JFFS2 should use */ #define CFG_MAX_MTD_BANKS (CFG_MAX_FLASH_BANKS+CFG_MAX_NAND_DEVICE) #define CFG_JFFS2_MEM_NAND #define CFG_JFFS2_FIRST_BANK CFG_MAX_FLASH_BANKS /* use flash_info[2] */ #define CFG_JFFS2_NUM_BANKS 1 #define CONFIG_LED_INFOnand_read_buf16 #define CONFIG_LED_LEN 16 #endif /* optional NOR flash */ #ifndef __ASSEMBLY__ extern unsigned int nand_cs_base; extern unsigned int boot_flash_base; extern volatile unsigned int boot_flash_env_addr; extern unsigned int boot_flash_off; extern unsigned int boot_flash_sec; extern unsigned int boot_flash_type; #endif #define WRITE_NAND_COMMAND(d, adr) __raw_writew(d, (nand_cs_base + GPMC_NAND_CMD)) #define WRITE_NAND_ADDRESS(d, adr) __raw_writew(d, (nand_cs_base + GPMC_NAND_ADR)) #define WRITE_NAND(d, adr) __raw_writew(d, (nand_cs_base + GPMC_NAND_DAT)) #define READ_NAND(adr) __raw_readw((nand_cs_base + GPMC_NAND_DAT)) /* Other NAND Access APIs */ #define NAND_WP_OFF() do {*(volatile u32 *)(GPMC_CONFIG) |= 0x00000010;} while(0) #define NAND_WP_ON() do {*(volatile u32 *)(GPMC_CONFIG) &= ~0x00000010;} while(0) #define NAND_DISABLE_CE(nand) #define NAND_ENABLE_CE(nand) #define NAND_WAIT_READY(nand) udelay(10) /* Fastboot variables */ #define CFG_FASTBOOT_TRANSFER_BUFFER (PHYS_SDRAM_1 + SZ_16M) #define CFG_FASTBOOT_TRANSFER_BUFFER_SIZE (SZ_256M - SZ_16M) #define CFG_FASTBOOT_PREBOOT_KEYS 1 #define CFG_FASTBOOT_PREBOOT_KEY1 0x37 /* 'ok' */ #define CFG_FASTBOOT_PREBOOT_KEY2 0x00 /* unused */ #define CFG_FASTBOOT_PREBOOT_INITIAL_WAIT (0) #define CFG_FASTBOOT_PREBOOT_LOOP_MAXIMUM (1) #define CFG_FASTBOOT_PREBOOT_LOOP_WAIT (0) /* Yaffs variables */ #define CFG_NAND_YAFFS_WRITE /* Command shell */ #define CFG_HUSH_PARSER #define CFG_PROMPT_HUSH_PS2 "> " /* Clock command */ #define CONFIG_CMD_CLOCK 1 #define CONFIG_CMD_CLOCK_INFO_CPU 1 /* Voltage command */ #define CONFIG_CMD_VOLTAGE 1 #if defined(CONFIG_CMD_NET) /*---------------------------------------------------------------------------- * SMSC9211 Ethernet from SMSC9118 family *---------------------------------------------------------------------------- */ #define CONFIG_NET_MULTI #define CONFIG_SMC911X 1 #define CONFIG_SMC911X_32_BIT #define CONFIG_SMC911X_BASE 0x2C000000 #endif /* (CONFIG_CMD_NET) */ #endif /* __CONFIG_H */