/*
 * (C) Copyright 2004-2009
 * Texas Instruments, <www.ti.com>
 * Richard Woodruff <r-woodruff2@ti.com>
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */
#include <common.h>
#include <asm/arch/cpu.h>
#include <asm/io.h>
#include <asm/arch/bits.h>
#include <asm/arch/mux.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/sys_info.h>
#include <asm/arch/clocks.h>
#include <asm/arch/mem.h>
#include <asm/arch/gpio.h>
#include <asm/arch/i2c.h>
#include <asm/memprot.h>
#include <tomtom.h>
#include <i2c.h>
#include <mmc.h>
#include <asm/mach-types.h>
#include <linux/mtd/nand_ecc.h>
#include <twl4030.h>
#include <flipflop.h>
#include "logo.h"
#include "mfd_feat.h"
#include <plat-tomtom/offenburg/offenburg.h>

/* Before including the padconfig settings, we have to set proper config */
#define BOOTLOADER_UBOOT_PADCONFIG
#if defined(__VARIANT_STUTTGART_B1)
# include <linux/padconfig_stuttgart_b1.h>
#elif defined( __VARIANT_RENNES_B1)
# include <linux/padconfig_rennes_b1.h>
#elif defined(__VARIANT_A1)
# include <linux/padconfig_strasbourg.h>
#else
# include <linux/padconfig_strasbourg_a2.h>
#endif

#define GPIO_LCD_UD		(12)
#define GPIO_LCD_LR		(19)
#define GPIO_LCM_PWR_ON		(137)
#define GPIO_nLCD_RESET		(156)
#define GPIO_BACKLIGHT_ON	(65)
#define GPIO_SENSE_11V0		(17)
#define SENSE_11V0_MAX_RETRY	(5)
DECLARE_GLOBAL_DATA_PTR;

extern void detect_boot_mode(void);
extern void hw_watchdog_init(void);

extern const uchar __diagsys_start;
#define DIAGSYS_ADDR_START	(&__diagsys_start)
extern const uchar __diagsys_end;
#define DIAGSYS_ADDR_END	(&__diagsys_end)
#define DIAGSYS_LEN		((size_t) (DIAGSYS_ADDR_END -	\
					   DIAGSYS_ADDR_START))
#define DIAGSYS_ADDR_NOR	((uchar *) 0x08300000UL)

#define DEFAULT_FDT_START	((uchar *) 0x81FE0000UL)
#define DEFAULT_FDT_LEN		((size_t)  0xe00U) /* 7 sectors */

unsigned exec_applet = 0;

extern const int __framebuffer_start;
#define FRAMEBUFFER_ADDR_START	0x83000000
extern const int __framebuffer_end;
#define FRAMEBUFFER_ADDR_END	(&__framebuffer_end)
#define FRAMEBUFFER_LEN		((size_t) (FRAMEBUFFER_ADDR_END -	\
					   FRAMEBUFFER_ADDR_START))
#define FDT_SCR_ROT_OFFSET	(0x1150)
#define FDT_SCR_VCOM_OFFSET	(0x124e)
#define EOL_SAT_TUN_OFFSET	(0x0113)

/* Timer related definitions */
#define OMAP34XX_GPTIMER10_BASE	(0x48086000)
#define	TIMER_CTRL_GPOCFG		(1 << 14)
#define	TIMER_CTRL_CAPTMODE		(1 << 13)
#define	TIMER_CTRL_PT			(1 << 12)
#define TIMER_CTRL_TRG_OVERFLOW		(1 << 10)
#define	TIMER_CTRL_TRG_OVERFLOW_MATCH 	(2 << 10)
#define	TIMER_CTRL_TCM_LOWTOHIGH	(0x1 << 8)
#define	TIMER_CTRL_TCM_HIGHTOLOW	(0x2 << 8)
#define	TIMER_CTRL_TCM_BOTHEDGES	(0x3 << 8)
#define	TIMER_CTRL_SCPWM		(1 << 7)
#define	TIMER_CTRL_CE			(1 << 6) /* compare enable */
#define	TIMER_CTRL_PRE			(1 << 5) /* prescaler enable */
#define	TIMER_CTRL_POSTED		(1 << 2)
#define	TIMER_CTRL_AR			(1 << 1) /* auto-reload enable */
#define	TIMER_CTRL_ST			(1 << 0) /* start timer */

/* CONTROL_PROG_IO1 bit definitions */
#define PRG_SDMMC1_SPEEDCTRL		(1 << 20)

void eth_init(void *);

#ifdef __VARIANT_A1
# define BOOTDEV_SDCARD 0
# define BOOTDEV_MOVI   1

#else
# define BOOTDEV_MOVI   0
#endif

extern unsigned char __mmu_table_start;

/* Fudge kernel bootdevice on A1 if sd card is present:
 * - root=/dev/mmcblk0p2 if no SD card present OR if booting from SD
 * - root=/dev/mmcblk1p2 if have SD card and booting from movi
 */
int kernel_root_num = 0;

static unsigned char sat_tun = 0;

/*****************************************
 * Routine: board_init
 * Description: Early hardware init.
 *****************************************/
int board_init(void)
{
	detect_boot_mode();

	if (get_device_type() != GP_DEVICE) {
		set_default_map((uint32_t) &__mmu_table_start);
	}
	dcache_enable();

	if (SYSBOOT_MODE_COLD == gd->tomtom.sysboot_mode)
		/* cold boot => initialize the flipflop, we can't rely on the
		   state of the scratchpad register */
		flipflop_set(0);

	/* In general, load the kernel from MoviNAND; on A1 the SD slot is useful for recovery */
	gd->tomtom.bootdev = BOOTDEV_MOVI;

	/* STRBDEV-2049 Reduce the drive strength on the MoviNand signals */
	__raw_writel(__raw_readl(CONTROL_PROG_IO1) & ~PRG_SDMMC1_SPEEDCTRL, CONTROL_PROG_IO1);

	mmc_init(BOOTDEV_MOVI);
#ifdef BOOTDEV_SDCARD
	kernel_root_num = !mmc_init(BOOTDEV_SDCARD);

	if ((__raw_readl(0x480029c0) & 0xff) == 0x6) { /* Booted from the A1 SD slot? */
		gd->tomtom.bootdev = BOOTDEV_SDCARD;
		kernel_root_num = 0;
	}
#endif

	/* Enable GPIO4 clocks FCLK and ICLK */
	__raw_writel(__raw_readl(CM_FCLKEN_WKUP) | (1 << CLKEN_PER_EN_GPIO2_BIT),
		            CM_FCLKEN_WKUP);
	__raw_writel(__raw_readl(CM_ICLKEN_WKUP) | (1 << CLKEN_PER_EN_GPIO2_BIT),
		            CM_ICLKEN_WKUP);
	delay(10000);

#if !defined(__VARIANT_A1)
	if (!(__raw_readl(OMAP34XX_GPIO2_BASE + OMAP34XX_GPIO_DATAIN) & GPIO9)) {
		memcpy(DIAGSYS_ADDR_START, DIAGSYS_ADDR_NOR, DIAGSYS_LEN);
		memcpy(DEFAULT_FDT_START, DIAGSYS_ADDR_START+DIAGSYS_LEN-DEFAULT_FDT_LEN-512, DEFAULT_FDT_LEN);
		exec_applet=1;
	}
#endif

	gpmc_init();		/* in SRAM or SDRAM, finish GPMC */
#if defined(__VARIANT_A1)
 	gd->bd->bi_arch_number = MACH_TYPE_STRASBOURG; /* Linux mach id */
#else
 	gd->bd->bi_arch_number = MACH_TYPE_STRASBOURG_A2; /* Linux mach id */
#endif
	gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100); /* boot param addr */

	return 0;
}

/**********************************************************
 * Routine: dss_init
 * Description: Initializes the display and fills the 
                framebuffer with the logo.
 **********************************************************/
void dss_init(void)
{
	unsigned long i, y;
	unsigned long p = 0;
	unsigned char pixel[3];

	/* Draw logo into frame buffer */
	for (i = 0; i < header_data_rle_size; i++) {
		for (y = 0; y < header_data_rle[i][0]; y++) {
			HEADER_PIXEL(header_data_rle[i][1], pixel);
			*((unsigned int *)(FRAMEBUFFER_ADDR_START + p*4)) =
			(pixel[0] << 16) |
			(pixel[1] << 8) |
			(pixel[2]);
			p++;
		}
	}

	/* Reset lcd */
	if (omap_request_gpio(GPIO_nLCD_RESET)) {
		printf ("Error when requesting nLCD_RESET\n");
		return;
	}
	omap_set_gpio_dataout(GPIO_nLCD_RESET, 0);
	omap_set_gpio_direction(GPIO_nLCD_RESET, 0);

	/* Enable lcm power */
	if (omap_request_gpio(GPIO_LCM_PWR_ON)) {
		printf ("Error when requesting LCM_PWR_ON\n");
		return;
	}

#if defined(__VARIANT_B2) || defined(__VARIANT_RENNES_A1) || defined(__VARIANT_RENNES_B1)
	if (omap_request_gpio(GPIO_SENSE_11V0)) {
		printf ("Error when requesting LCM_PWR_ON\n");
		return;
	}
	omap_set_gpio_direction(GPIO_SENSE_11V0, 1);
	omap_set_gpio_dataout(GPIO_LCM_PWR_ON, 0);
	omap_set_gpio_direction(GPIO_LCM_PWR_ON, 0);
	for (i = 0; i < SENSE_11V0_MAX_RETRY; i++) {
		/* attempt to activate LCD power supply */
		omap_set_gpio_dataout(GPIO_LCM_PWR_ON, 1);
		/* T8 */
		delay(600000); /* 2 ms */
		if (omap_get_gpio_datain(GPIO_SENSE_11V0))
			break;
	}
	if (i == SENSE_11V0_MAX_RETRY)
		printf("Failed to power on the LCM!!!");
#else
	omap_set_gpio_dataout(GPIO_LCM_PWR_ON, 1);
	omap_set_gpio_direction(GPIO_LCM_PWR_ON, 0);
#endif
	delay (9000000); /* 30 ms */

	/* Release Reset line */
	omap_set_gpio_dataout(GPIO_nLCD_RESET, 1);
	delay (9000000); /* 30 ms */
	
	/* Setup lcm */
	writel(0x00000001, 0x48050010);
	writel(0x00000000, 0x48050040);
	/* Enable RFBI set in bypass mode */
	writel(0x00000002, 0x48050840);
	writel(0x00310000, 0x48050860);
	/* Config display controller */
	writel(0x05F05F00, 0x48050464);
	writel(0x00a00a00, 0x48050468);
	writel(0x00000000, 0x4805046c);
	writel(0x00010006, 0x48050470);
	writel(0x000000ff, 0x48050474);
	writel(0x00000000, 0x48050478);
	writel(0x01DF031F, 0x4805047c);
	writel(FRAMEBUFFER_ADDR_START, 0x48050480);
	writel(0x01df031f, 0x4805048c);
	writel(0x000000b1, 0x480504a0);
	writel(0x03ff03c0, 0x480504a4);
	writel(0x08018309, 0x48050440);//DISPC_CONTROL enable disp
}

/**********************************************************
 * Routine: config_screen_rotation
 * Description: Configure the screen rotation based on the 
                EEPROM setting
 **********************************************************/
static void config_screen_rotation(void)
{
	unsigned char fdt_rotation;
	
	/* Request the rotation GPIOs */
	if (omap_request_gpio(GPIO_LCD_UD)) {
		printf ("Error when requesting LCD_UD\n");
		return;
	}
	if (omap_request_gpio(GPIO_LCD_LR)) {
		printf ("Error when requesting LCD_LR\n");
		return;
	}
	
	/* Read the rotation value from EEPROM */
	select_bus(CFG_I2C_EEPROM_BUS, OMAP_I2C_FAST_MODE);
	if (eeprom_read (CFG_DEF_EEPROM_ADDR, FDT_SCR_ROT_OFFSET, &fdt_rotation, 1)) {
		printf("** Error reading screen rotation from EEPROM\n");
		fdt_rotation = 0;
	}
	select_bus(CFG_I2C_BUS, CFG_I2C_SPEED);
	
	/* Set the rotation GPIOs accordingly */
	if (fdt_rotation == '1') {
		omap_set_gpio_dataout(GPIO_LCD_UD, 0);
		omap_set_gpio_dataout(GPIO_LCD_LR, 1);
	}
	else {
		omap_set_gpio_dataout(GPIO_LCD_UD, 1);
		omap_set_gpio_dataout(GPIO_LCD_LR, 0);
	}
	omap_set_gpio_direction(GPIO_LCD_UD, 0);
	omap_set_gpio_direction(GPIO_LCD_LR, 0);
}

static unsigned char vcom_to_pwmaoff_rennes_b1(unsigned char vcom)
{
	unsigned char pwmaoff;

	if (vcom >= 0x80)
		pwmaoff = 0x3f;
	else if (vcom == 0x7f)
		pwmaoff = 0x01;
	else if (vcom == 0x00)
		pwmaoff = 0x00;
	else
		pwmaoff = vcom + 1;

	return pwmaoff;
}

static void config_screen_vcom_rennes_b1(void)
{
	unsigned char vcom, data;

	/* Read the vcom value from EEPROM */
	select_bus(CFG_I2C_EEPROM_BUS, OMAP_I2C_FAST_MODE);
	if (eeprom_read (CFG_DEF_EEPROM_ADDR, FDT_SCR_VCOM_OFFSET, &vcom, 1)) {
		printf("** Error reading screen VCOM from EEPROM\n");
		vcom = 0xff;
	}
	select_bus(CFG_I2C_BUS, CFG_I2C_SPEED);

	/* clear VIBRA_CTL[0] - VIBRA_EN */
	i2c_read(0x49, 0x45, 1, &data, 1);
	data &= ~1;
	i2c_write(0x49, 0x45, 1, &data, 1);

	/* set LEDEN[0] - LEDAON */
	i2c_read(0x4a, 0xee, 1, &data, 1);
	data |= 1;
	i2c_write(0x4a, 0xee, 1, &data, 1);

	/* set LEDEN[4] - LEDAPWM */
	i2c_read(0x4a, 0xee, 1, &data, 1);
	data |= (1 << 4);
	i2c_write(0x4a, 0xee, 1, &data, 1);

	/* clear LEDEN[2] - LEDAEXT */
	i2c_read(0x4a, 0xee, 1, &data, 1);
	data &= ~(1 << 2);
	i2c_write(0x4a, 0xee, 1, &data, 1);

	/* set PWMAON */
	data = 1;
	i2c_write(0x4a, 0xef, 1, &data, 1);

	/* set PWMAOFF */
	data = vcom_to_pwmaoff_rennes_b1(vcom);
	i2c_write(0x4a, 0xf0, 1, &data, 1);
}

static void switch_on_bl_pmic_pwm(void)
{
	unsigned char data;

	/* PWM0ON */
	data = 0x2;
	i2c_write(0x4a, 0xF8, 1, &data, 1); 
	/* PWM0OFF */
	data = 0x44;
	i2c_write(0x4a, 0xF9, 1, &data, 1);
	/* PMBR1 */
	i2c_read(0x49, 0x92, 1, &data, 1);
	data |= (1<<2);
	i2c_write(0x49, 0x92, 1, &data, 1);
	/* GPBR1 */
	i2c_read(0x49, 0x91, 1, &data, 1);
	data |= ((1<<2) | (1));
	i2c_write(0x49, 0x91, 1, &data, 1);

	/* Set GPIO13 (BL enable) output high*/
	data = 0x0;
	i2c_read(0x49, 0x9c, 1, &data, 1); 
	data |= 0x20;
	i2c_write(0x49, 0x9c, 1, &data, 1); 
	data = 0x0;
	i2c_read(0x49, 0x9f, 1, &data, 1); 
	data |= 0x20;
	i2c_write(0x49, 0x9f, 1, &data, 1); 
}

static void switch_on_bl_omap_pwm(void)
{
	/* Configure GPT10 source (1: sys_clk, 0: 32K_clk) */
	sr32(CM_CLKSEL_CORE, 6, 1, 1);

	/* TSICR register: non-posted mode */
	writel(0x0, OMAP34XX_GPTIMER10_BASE + TSICR);

	/* Timer load register */
	writel(0xfffcd37e, OMAP34XX_GPTIMER10_BASE + TLDR);

	/* Trigger register */
	writel(0x0, OMAP34XX_GPTIMER10_BASE + TTGR);

	/* Match register */
	writel(0xfffdc5a7, OMAP34XX_GPTIMER10_BASE + TMAR);

	/* Timer counter register */
	writel(0xfffffffe, OMAP34XX_GPTIMER10_BASE + TCRR);

	/* Start the timer */
	writel(TIMER_CTRL_ST | TIMER_CTRL_AR | TIMER_CTRL_CE |
	       TIMER_CTRL_PT | TIMER_CTRL_TRG_OVERFLOW_MATCH,
	       OMAP34XX_GPTIMER10_BASE + TCLR);

	/* Enable the backlight */
	if (omap_request_gpio(GPIO_BACKLIGHT_ON)) {
		printf ("Error when requesting BACKLIGHT_ON gpio\n");
		return;
	}
	omap_set_gpio_dataout(GPIO_BACKLIGHT_ON, 1);
	omap_set_gpio_direction(GPIO_BACKLIGHT_ON, 0);
}

static void switch_on_bl_omap_pwm_rennes_b1(void)
{
	unsigned char data;

	/*
	 * switch off VDD_1V8_AUX2 so to hide the otherwise visible
	 * white flash on reboot
	 */
	i2c_read(0x4b, 0x76, 1, &data, 1);
	data &= ~0x20;
	i2c_write(0x4b, 0x76, 1, &data, 1);

	/* Configure the screen VCOM based on the EEPROM value */
	config_screen_vcom_rennes_b1();

	/* continue with the usual omap pwm configuration */
	switch_on_bl_omap_pwm();
}

static struct mfd_feat bl_feats[] = {
	MFD_1_0_A2(switch_on_bl_pmic_pwm),
	MFD_1_0_B1(switch_on_bl_pmic_pwm),
	MFD_1_0_B2(switch_on_bl_omap_pwm),
	MFD_1_05(switch_on_bl_omap_pwm),
	MFD_1_1(switch_on_bl_omap_pwm_rennes_b1),
	MFD_2_0(switch_on_bl_omap_pwm_rennes_b1),
	MFD_DEFAULT(NULL),
};

/**********************************************************
 * Routine: switch_on_bl
 * Description: Switches on the display backlight
 **********************************************************/
static void switch_on_bl(void)
{
	void (*switch_mfd_bl)(void) = mfd_feature(bl_feats);

	/* Configure the screen rotation based on the EEPROM value */
	config_screen_rotation();

	if (switch_mfd_bl)
		switch_mfd_bl();

	/* Print out APTS tag */
	printf ("\n[APTS Logo/]\n\n");
}

static void detect_sat_tuner_stuttgart_b1(void)
{
	select_bus(CFG_I2C_EEPROM_BUS, OMAP_I2C_FAST_MODE);
	if (eeprom_read(CFG_DEF_EEPROM_ADDR, EOL_SAT_TUN_OFFSET, &sat_tun, 1))
		printf("** Error reading Diags_conf_13 Satellite Tuner\n");
	select_bus(CFG_I2C_BUS, CFG_I2C_SPEED);

	/* check bit 2 (SAT_CNF) */
	sat_tun = (sat_tun != 0xff) && (sat_tun & 0x4);
}

static struct mfd_feat sat_tun_feats[] = {
	MFD_2_0(detect_sat_tuner_stuttgart_b1),
	MFD_DEFAULT(NULL),
};

/*******************************************************
 * Routine: misc_init_r
 * Description: Init ethernet (done here so udelay works)
 ********************************************************/
int misc_init_r(void)
{
	void (*detect_mfd_sat_tun)(void) = mfd_feature(sat_tun_feats);

#ifdef CONFIG_DRIVER_OMAP34XX_I2C
	unsigned char data;

	i2c_init(CFG_I2C_SPEED, CFG_I2C_SLAVE);

	twl4030_usb_init();

	/* Disable the PMU watchdog. The main SoC watchdog
	 * is enabled by this time */
	data = 0;
	i2c_write(0x4b, 0x5e, 1, &data, 1);
#endif

	if (detect_mfd_sat_tun)
		detect_mfd_sat_tun();

	switch_on_bl();
	dieid_num_r();

	return (0);
}

/*
 * IEN  - Input Enable
 * IDIS - Input Disable
 * PTD  - Pull type Down
 * PTU  - Pull type Up
 * DIS  - Pull type selection is inactive
 * EN   - Pull type selection is active
 * M0   - Mode 0
 * The commented string gives the final mux configuration for that pin
 */
#define MUX_DEFAULT_ES2()\
	/*Die to Die */\
	MUX_VAL(CP(d2d_mcad0),      (IEN  | PTD | EN  | M0)) /*d2d_mcad0*/\
	MUX_VAL(CP(d2d_mcad1),      (IEN  | PTD | EN  | M0)) /*d2d_mcad1*/\
	MUX_VAL(CP(d2d_mcad2),      (IEN  | PTD | EN  | M0)) /*d2d_mcad2*/\
	MUX_VAL(CP(d2d_mcad3),      (IEN  | PTD | EN  | M0)) /*d2d_mcad3*/\
	MUX_VAL(CP(d2d_mcad4),      (IEN  | PTD | EN  | M0)) /*d2d_mcad4*/\
	MUX_VAL(CP(d2d_mcad5),      (IEN  | PTD | EN  | M0)) /*d2d_mcad5*/\
	MUX_VAL(CP(d2d_mcad6),      (IEN  | PTD | EN  | M0)) /*d2d_mcad6*/\
	MUX_VAL(CP(d2d_mcad7),      (IEN  | PTD | EN  | M0)) /*d2d_mcad7*/\
	MUX_VAL(CP(d2d_mcad8),      (IEN  | PTD | EN  | M0)) /*d2d_mcad8*/\
	MUX_VAL(CP(d2d_mcad9),      (IEN  | PTD | EN  | M0)) /*d2d_mcad9*/\
	MUX_VAL(CP(d2d_mcad10),     (IEN  | PTD | EN  | M0)) /*d2d_mcad10*/\
	MUX_VAL(CP(d2d_mcad11),     (IEN  | PTD | EN  | M0)) /*d2d_mcad11*/\
	MUX_VAL(CP(d2d_mcad12),     (IEN  | PTD | EN  | M0)) /*d2d_mcad12*/\
	MUX_VAL(CP(d2d_mcad13),     (IEN  | PTD | EN  | M0)) /*d2d_mcad13*/\
	MUX_VAL(CP(d2d_mcad14),     (IEN  | PTD | EN  | M0)) /*d2d_mcad14*/\
	MUX_VAL(CP(d2d_mcad15),     (IEN  | PTD | EN  | M0)) /*d2d_mcad15*/\
	MUX_VAL(CP(d2d_mcad16),     (IEN  | PTD | EN  | M0)) /*d2d_mcad16*/\
	MUX_VAL(CP(d2d_mcad17),     (IEN  | PTD | EN  | M0)) /*d2d_mcad17*/\
	MUX_VAL(CP(d2d_mcad18),     (IEN  | PTD | EN  | M0)) /*d2d_mcad18*/\
	MUX_VAL(CP(d2d_mcad19),     (IEN  | PTD | EN  | M0)) /*d2d_mcad19*/\
	MUX_VAL(CP(d2d_mcad20),     (IEN  | PTD | EN  | M0)) /*d2d_mcad20*/\
	MUX_VAL(CP(d2d_mcad21),     (IEN  | PTD | EN  | M0)) /*d2d_mcad21*/\
	MUX_VAL(CP(d2d_mcad22),     (IEN  | PTD | EN  | M0)) /*d2d_mcad22*/\
	MUX_VAL(CP(d2d_mcad23),     (IEN  | PTD | EN  | M0)) /*d2d_mcad23*/\
	MUX_VAL(CP(d2d_mcad24),     (IEN  | PTD | EN  | M0)) /*d2d_mcad24*/\
	MUX_VAL(CP(d2d_mcad25),     (IEN  | PTD | EN  | M0)) /*d2d_mcad25*/\
	MUX_VAL(CP(d2d_mcad26),     (IEN  | PTD | EN  | M0)) /*d2d_mcad26*/\
	MUX_VAL(CP(d2d_mcad27),     (IEN  | PTD | EN  | M0)) /*d2d_mcad27*/\
	MUX_VAL(CP(d2d_mcad28),     (IEN  | PTD | EN  | M0)) /*d2d_mcad28*/\
	MUX_VAL(CP(d2d_mcad29),     (IEN  | PTD | EN  | M0)) /*d2d_mcad29*/\
	MUX_VAL(CP(d2d_mcad30),     (IEN  | PTD | EN  | M0)) /*d2d_mcad30*/\
	MUX_VAL(CP(d2d_mcad31),     (IEN  | PTD | EN  | M0)) /*d2d_mcad31*/\
	MUX_VAL(CP(d2d_mcad32),     (IEN  | PTD | EN  | M0)) /*d2d_mcad32*/\
	MUX_VAL(CP(d2d_mcad33),     (IEN  | PTD | EN  | M0)) /*d2d_mcad33*/\
	MUX_VAL(CP(d2d_mcad34),     (IEN  | PTD | EN  | M0)) /*d2d_mcad34*/\
	MUX_VAL(CP(d2d_mcad35),     (IEN  | PTD | EN  | M0)) /*d2d_mcad35*/\
	MUX_VAL(CP(d2d_mcad36),     (IEN  | PTD | EN  | M0)) /*d2d_mcad36*/\
	MUX_VAL(CP(d2d_clk26mi),    (IEN  | PTD | DIS | M0)) /*d2d_clk26mi  */\
	MUX_VAL(CP(d2d_nrespwron ), (IEN  | PTD | EN  | M0)) /*d2d_nrespwron*/\
	MUX_VAL(CP(d2d_nreswarm),   (IEN  | PTU | EN  | M0)) /*d2d_nreswarm */\
	MUX_VAL(CP(d2d_arm9nirq),   (IEN  | PTD | DIS | M0)) /*d2d_arm9nirq */\
	MUX_VAL(CP(d2d_uma2p6fiq ), (IEN  | PTD | DIS | M0)) /*d2d_uma2p6fiq*/\
	MUX_VAL(CP(d2d_spint),      (IEN  | PTD | EN  | M0)) /*d2d_spint*/\
	MUX_VAL(CP(d2d_frint),      (IEN  | PTD | EN  | M0)) /*d2d_frint*/\
	MUX_VAL(CP(d2d_dmareq0),    (IEN  | PTD | DIS | M0)) /*d2d_dmareq0  */\
	MUX_VAL(CP(d2d_dmareq1),    (IEN  | PTD | DIS | M0)) /*d2d_dmareq1  */\
	MUX_VAL(CP(d2d_dmareq2),    (IEN  | PTD | DIS | M0)) /*d2d_dmareq2  */\
	MUX_VAL(CP(d2d_dmareq3),    (IEN  | PTD | DIS | M0)) /*d2d_dmareq3  */\
	MUX_VAL(CP(d2d_n3gtrst),    (IEN  | PTD | DIS | M0)) /*d2d_n3gtrst  */\
	MUX_VAL(CP(d2d_n3gtdi),     (IEN  | PTD | DIS | M0)) /*d2d_n3gtdi*/\
	MUX_VAL(CP(d2d_n3gtdo),     (IEN  | PTD | DIS | M0)) /*d2d_n3gtdo*/\
	MUX_VAL(CP(d2d_n3gtms),     (IEN  | PTD | DIS | M0)) /*d2d_n3gtms*/\
	MUX_VAL(CP(d2d_n3gtck),     (IEN  | PTD | DIS | M0)) /*d2d_n3gtck*/\
	MUX_VAL(CP(d2d_n3grtck),    (IEN  | PTD | DIS | M0)) /*d2d_n3grtck  */\
	MUX_VAL(CP(d2d_mstdby),     (IEN  | PTU | EN  | M0)) /*d2d_mstdby*/\
	MUX_VAL(CP(d2d_swakeup),    (IEN  | PTD | EN  | M0)) /*d2d_swakeup  */\
	MUX_VAL(CP(d2d_idlereq),    (IEN  | PTD | DIS | M0)) /*d2d_idlereq  */\
	MUX_VAL(CP(d2d_idleack),    (IEN  | PTU | EN  | M0)) /*d2d_idleack  */\
	MUX_VAL(CP(d2d_mwrite),     (IEN  | PTD | DIS | M0)) /*d2d_mwrite*/\
	MUX_VAL(CP(d2d_swrite),     (IEN  | PTD | DIS | M0)) /*d2d_swrite*/\
	MUX_VAL(CP(d2d_mread),      (IEN  | PTD | DIS | M0)) /*d2d_mread*/\
	MUX_VAL(CP(d2d_sread),      (IEN  | PTD | DIS | M0)) /*d2d_sread*/\
	MUX_VAL(CP(d2d_mbusflag),   (IEN  | PTD | DIS | M0)) /*d2d_mbusflag */\
	MUX_VAL(CP(d2d_sbusflag),   (IEN  | PTD | DIS | M0)) /*d2d_sbusflag */\
	MUX_VAL(CP(sdrc_cke0),      (IDIS | PTU | EN  | M0)) /*sdrc_cke0 */\
	MUX_VAL(CP(sdrc_cke1),      (IDIS | PTD | DIS | M7)) /*sdrc_cke1 unused*/

/**********************************************************
 * Routine: set_muxconf_regs
 * Description: Setting up the configuration Mux registers
 *              specific to the hardware. Many pins need
 *              to be moved from protect to primary mode.
 *********************************************************/
void set_muxconf_regs(void)
{
	PADCONFIG_SETTINGS_UBOOT
	PADCONFIG_SETTINGS_COMMON
	MUX_DEFAULT_ES2();
}

/******************************************************************************
 * Routine: update_mux()
 * Description:Update balls which are different between boards.  All should be
 *             updated to match functionality.  However, I'm only updating ones
 *             which I'll be using for now.  When power comes into play they
 *             all need updating.
 *****************************************************************************/
void update_mux(u32 btype, u32 mtype)
{
	/* NOTHING as of now... */
}

void board_env_init(void)
{
	char ulong_str[16]; /* Needs to be as long as "0x12345678" + '\0' */

	/* Replace with factory data when available */
	switch(gd->bd->bi_arch_number) {
	case MACH_TYPE_STRASBOURG_A2:
		setenv("kernel.console", "ttyO2");
		break;
	case MACH_TYPE_STRASBOURG:
	default:
		setenv("kernel.console", "ttyO0");
		break;
	}

	/* disable the console in case of satellite tuner */
	if (sat_tun) {
		printf("## Silent boot due to SAT_CNF\n\n");
		setenv("kernel.console", "");
	}

	sprintf(ulong_str, "%u", kernel_root_num);
	setenv("kernel.root.num", ulong_str);

	sprintf(ulong_str, "%#lx", (unsigned long) DIAGSYS_ADDR_START);
	setenv("applet.addr", ulong_str);

	if (exec_applet) {
		sprintf(ulong_str, "%u", DIAGSYS_LEN-44); /* 44 byte DSA sig at end */
		setenv("applet.size", ulong_str);

		sprintf(ulong_str, "%lx", DEFAULT_FDT_START);
		setenv("fdt.default.addr", ulong_str);

		setenv("exec_applet", "yes");
	} else {
		setenv("exec_applet", "no");
	}
}