Added code for reading and writing Mac addresses to/from ID EEPROM(0x57).
With attached patch, we can use command "mac/mac read/mac save/"
to read and write EEPROM under u-boot prompt.
U-boot will calculate the checksum of EEPROM while bootup,
if it is right, then u-boot will check whether the mac address
of eTSEC0/1/2/3 is availalbe (non-zero).
If there is mac address availabe in EEPROM, u-boot will use it,
otherewise, u-boot will use the mac address defined in
MPC8641HPCN.h. This matches the requirement to set unique mac address
for each TSEC port.
Signed-off-by: Haiying Wang <haiying.wang@freescale.com>
Signed-off-by: York Sun <yorksun@freescale.com>
All MII configuration is done via FEC1 registers. But MII_SPEED was
configured according to FEC used. So if only FEC2 was used, this caused
the real MII_SPEED register in FEC1 to stay uninitalised, what lead
to "mii_send STUCK!" messages. Fix: always configure MII_SPEED on FEC1
only.
Notes:
- Board-dependend code for RPXLITE and RPXCLASSIC-based boards
placed to the drivers/rpx_pmcia.c file to avoid duplication.
Same for TQM8xx-based boards (drivers/tqm8xx_pmcia.c).
- drivers/i82365.c has been split into two parts located at
board/atc/ti113x.c and board/cpc45/pd67290.c (ATC and CPC45 are
the only boards using CONFIG_82365).
- Changes were tested for clean build and *very* *few* boards.
When tftp a non-exist file from the tftp server, u-boot will check
the link of all eth port. The original file will return wrong link
state on the no link ports.
signed-off-by: Jason Jin <Jason.Jin@freescale.com>
During the pci scan process, Some devices return bar_reponse with the
highest bytes 0, such as the pci bridge in uli1575 return bar_response
with 0xffffff, So the bar_size should be manually set under 64K.
Signed-off-by: Jason Jin <jason.jin@freescale.com>
Patch by Martin Krause, 8 Jun 2006
This patch supports two serial consoles on boards with
a MPC5xxx CPU. The console can be switched at runtime
by setting stdin, stdout and stderr to the desired serial
interface (serial0 or serial1). The PSCs to be used as
console port are definded by CONFIG_PSC_CONSOLE
and CONFIG_PSC_CONSOLE2.
See README.serial_multi for details.
If the bus is blocked because of a previously interrupted
transfer, up to eleven clocks are generated on the I2CSCL
line to complete the transfer and to free the bus.
With this fix pin I2CSCL (PG6) is really configured as GPIO
so the clock pulses are really generated.
Patch by Martin Krause, 04 Apr 2006
