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Add system memory to the PCI region list for AMCC PPC44x CPUs.

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Enabled it for Yucca board.
This commit is contained in:
Marian Balakowicz 2006-07-04 00:55:47 +02:00
parent fe84b48a94
commit fbb0b559ae
3 changed files with 21 additions and 0 deletions
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3
CHANGELOG
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@ -2,6 +2,9 @@
Changes since U-Boot 1.1.4: Changes since U-Boot 1.1.4:
====================================================================== ======================================================================
* Add system memory to the PCI region list for AMCC PPC44x CPUs.
Enabled it for Yucca board.
* Cleanup config file and bootup output for Yucca board. * Cleanup config file and bootup output for Yucca board.
* Fix CONFIG_440_GX define usage. * Fix CONFIG_440_GX define usage.

13
cpu/ppc4xx/405gp_pci.c
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@ -465,17 +465,30 @@ void pci_440_init (struct pci_controller *hose)
hose->first_busno = 0; hose->first_busno = 0;
hose->last_busno = 0xff; hose->last_busno = 0xff;
/* PCI I/O space */
pci_set_region(hose->regions + reg_num++, pci_set_region(hose->regions + reg_num++,
0x00000000, 0x00000000,
PCIX0_IOBASE, PCIX0_IOBASE,
0x10000, 0x10000,
PCI_REGION_IO); PCI_REGION_IO);
/* PCI memory space */
pci_set_region(hose->regions + reg_num++, pci_set_region(hose->regions + reg_num++,
CFG_PCI_TARGBASE, CFG_PCI_TARGBASE,
CFG_PCI_MEMBASE, CFG_PCI_MEMBASE,
0x10000000, 0x10000000,
PCI_REGION_MEM ); PCI_REGION_MEM );
#if defined(CONFIG_PCI_SYS_MEM_BUS) && defined(CONFIG_PCI_SYS_MEM_PHYS) && \
defined(CONFIG_PCI_SYS_MEM_SIZE)
/* System memory space */
pci_set_region(hose->regions + reg_num++,
CONFIG_PCI_SYS_MEM_BUS,
CONFIG_PCI_SYS_MEM_PHYS,
CONFIG_PCI_SYS_MEM_SIZE,
PCI_REGION_MEM | PCI_REGION_MEMORY );
#endif
hose->region_count = reg_num; hose->region_count = reg_num;
pci_setup_indirect(hose, PCIX0_CFGADR, PCIX0_CFGDATA); pci_setup_indirect(hose, PCIX0_CFGADR, PCIX0_CFGDATA);

5
include/configs/yucca.h
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@ -75,6 +75,11 @@
/* #define CFG_PCI_BASE_REGS 0xBEC00000 */ /* internal PCI regs */ /* #define CFG_PCI_BASE_REGS 0xBEC00000 */ /* internal PCI regs */
/* #define CFG_PCI_BASE_CYCLE 0xBED00000 */ /* internal PCI regs */ /* #define CFG_PCI_BASE_CYCLE 0xBED00000 */ /* internal PCI regs */
/* System RAM mapped to PCI space */
#define CONFIG_PCI_SYS_MEM_BUS CFG_SDRAM_BASE
#define CONFIG_PCI_SYS_MEM_PHYS CFG_SDRAM_BASE
#define CONFIG_PCI_SYS_MEM_SIZE (1024 * 1024 * 1024)
#define CFG_FPGA_BASE 0xe2000000 /* epld */ #define CFG_FPGA_BASE 0xe2000000 /* epld */
#define CFG_OPER_FLASH 0xe7000000 /* SRAM - OPER Flash */ #define CFG_OPER_FLASH 0xe7000000 /* SRAM - OPER Flash */