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Clean up the code according to codestyle:

Browse Source 
(1) remove some C++ comments.
(2) remove trailing white space.
(3) remove trailing empty line.
(4) Indentation by table.
(5) remove {} in one line condition.
(6) add space before '(' in function call.
Remove some weird printf () output.
Add necessary comments.
Modified Makefile to support building in a separate directory.
This commit is contained in:
roy zang 2006-12-01 11:47:36 +08:00 committed by Zang Tiefei
parent 6bd87c0aee
commit ee311214e0
13 changed files with 1687 additions and 1734 deletions
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2
Makefile
View File

@ -1722,7 +1722,7 @@ EVB64260_750CX_config: unconfig
@$(MKCONFIG) EVB64260 ppc 74xx_7xx evb64260 @$(MKCONFIG) EVB64260 ppc 74xx_7xx evb64260
mpc7448hpc2_config: unconfig mpc7448hpc2_config: unconfig
@./mkconfig $(@:_config=) ppc 74xx_7xx mpc7448hpc2 @$(MKCONFIG) $(@:_config=) ppc 74xx_7xx mpc7448hpc2
P3G4_config: unconfig P3G4_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc 74xx_7xx evb64260 @$(MKCONFIG) $(@:_config=) ppc 74xx_7xx evb64260

20
board/mpc7448hpc2/Makefile
View File

@ -23,26 +23,30 @@
include $(TOPDIR)/config.mk include $(TOPDIR)/config.mk
LIB = lib$(BOARD).a LIB = $(obj)lib$(BOARD).a
OBJS = $(BOARD).o tsi108_init.o COBJS := $(BOARD).o tsi108_init.o
SOBJS := asm_init.o
SOBJS = asm_init.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): .depend $(OBJS) $(SOBJS) $(LIB): $(obj).depend $(OBJS) $(SOBJS)
$(AR) crv $@ $(OBJS) $(SOBJS) $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
clean: clean:
rm -f $(SOBJS) $(OBJS) rm -f $(SOBJS) $(OBJS)
.PHONY: distclean
distclean: clean distclean: clean
rm -f $(LIB) core *.bak .depend rm -f $(LIB) core *.bak .depend
######################################################################### #########################################################################
.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) # defines $(obj).depend target
$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ include $(SRCTREE)/rules.mk
sinclude .depend sinclude ($obj).depend
######################################################################### #########################################################################

263
board/mpc7448hpc2/asm_init.S
View File

@ -1,4 +1,4 @@
/***************************************************************************** /*
* (C) Copyright 2004-05; Tundra Semiconductor Corp. * (C) Copyright 2004-05; Tundra Semiconductor Corp.
* *
* Added automatic detect of SDC settings * Added automatic detect of SDC settings
@ -19,9 +19,9 @@
* along with this program; if not, write to the Free Software * along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA * MA 02111-1307 USA
****************************************************************************/ */
/*---------------------------------------------------------------------------- /*
* FILENAME: asm_init.s * FILENAME: asm_init.s
* *
* Originator: Alex Bounine * Originator: Alex Bounine
@ -29,7 +29,7 @@
* DESCRIPTION: * DESCRIPTION:
* Initialization code for the Tundra Tsi108 bridge chip * Initialization code for the Tundra Tsi108 bridge chip
* *
*---------------------------------------------------------------------------*/ */
#include <config.h> #include <config.h>
#include <version.h> #include <version.h>
@ -40,7 +40,7 @@
#include <tsi108.h> #include <tsi108.h>
/*=========================================================================== /*
* Build Configuration Options * Build Configuration Options
*/ */
@ -48,7 +48,7 @@
/* #define SDC_HARDCODED_INIT config SDRAM controller with hardcoded values */ /* #define SDC_HARDCODED_INIT config SDRAM controller with hardcoded values */
/* #define SDC_AUTOPRECH_EN enable SDRAM auto precharge */ /* #define SDC_AUTOPRECH_EN enable SDRAM auto precharge */
/* =========================================================================== /*
* Hardcoded SDC settings * Hardcoded SDC settings
*/ */
@ -65,24 +65,24 @@
#endif /* SDC_HARDCODED_INIT */ #endif /* SDC_HARDCODED_INIT */
/*--------------------------------------------------------------------------- /*
CPU Configuration: CPU Configuration:
CPU Address and Data Parity enables. CPU Address and Data Parity enables.
#define CPU_AP #define CPU_AP
#define CPU_DP #define CPU_DP
*/
=========================================================================== /*
Macros * Macros
* !!! Attention !!! Macros LOAD_PTR, LOAD_U32 and LOAD_MEM defined below are
!!! Attention !!! Macros LOAD_PTR, LOAD_U32 and LOAD_MEM defined below are * expected to work correctly for the CSR space within 32KB range.
expected to work correctly for the CSR space within 32KB range. *
* LOAD_PTR and LOAD_U32 - load specified register with a 32 bit constant.
LOAD_PTR and LOAD_U32 - load specified register with a 32 bit constant. * These macros are absolutely identical except their names. This difference
These macros are absolutely identical except their names. This difference * is provided intentionally for better readable code.
is provided intentionally for better readable code. */
-------------------------------------------------------------------------*/
#define LOAD_PTR(reg,const32) \ #define LOAD_PTR(reg,const32) \
addis reg,r0,const32@h; ori reg,reg,const32@l addis reg,r0,const32@h; ori reg,reg,const32@l
@ -90,8 +90,9 @@
#define LOAD_U32(reg,const32) \ #define LOAD_U32(reg,const32) \
addis reg,r0,const32@h; ori reg,reg,const32@l addis reg,r0,const32@h; ori reg,reg,const32@l
/* LOADMEM initializes a register with the contents of a specified 32-bit memory /* LOADMEM initializes a register with the contents of a specified 32-bit
location, usually a CSR value.*/ * memory location, usually a CSR value.
*/
#define LOAD_MEM(reg,addr32) \ #define LOAD_MEM(reg,addr32) \
addis reg,r0,addr32@ha; lwz reg,addr32@l(reg) addis reg,r0,addr32@ha; lwz reg,addr32@l(reg)
@ -102,37 +103,30 @@ sdc_clk_sync:
.long 0, 0, 6, 10, 8, 6, 5, 4 /* nSec */ .long 0, 0, 6, 10, 8, 6, 5, 4 /* nSec */
#endif #endif
/*=========================================================================== /*
board_asm_init() - early initialization function. Coded to be portable to * board_asm_init() - early initialization function. Coded to be portable to
dual-CPU configuration. * dual-CPU configuration.
Checks CPU number and performs board HW initialization if called for CPU0. * Checks CPU number and performs board HW initialization if called for CPU0.
* Registers used: r3,r4,r5,r6,r19,r29
Registers used: r3,r4,r5,r6,r19,r29 *
=========================================================================== * NOTE: For dual-CPU configuration only CPU0 is allowed to configure Tsi108
* and the rest of the board. Current implementation demonstrates two
--------------------------------------------------------------------------- * possible ways to identify CPU number:
NOTE: For dual-CPU configuration only CPU0 is allowed to configure Tsi108 * - for MPC74xx platform: uses MSSCR0[ID] bit as defined in UM.
and the rest of the board. Current implementation demonstrates two * - for PPC750FX/GX boards: uses WHO_AM_I bit reported by Tsi108.
possible ways to identify CPU number: */
- for MPC74xx platform: uses MSSCR0[ID] bit as defined in UM.
- for PPC750FX/GX boards: uses WHO_AM_I bit reported by Tsi108.
---------------------------------------------------------------------------*/
.globl board_asm_init .globl board_asm_init
board_asm_init: board_asm_init:
mflr r19 /* Save LR to be able return later. */ mflr r19 /* Save LR to be able return later. */
bl icache_enable /* Enable icache to reduce reads from flash. */ bl icache_enable /* Enable icache to reduce reads from flash. */
/* Initialize pointer to Tsi108 register space /* Initialize pointer to Tsi108 register space */
-------------------------------------------------------------------------*/
LOAD_PTR(r29,CFG_TSI108_CSR_RST_BASE)/* r29 - pointer to tsi108 CSR space */ LOAD_PTR(r29,CFG_TSI108_CSR_RST_BASE)/* r29 - pointer to tsi108 CSR space */
ori r4,r29,TSI108_PB_REG_OFFSET ori r4,r29,TSI108_PB_REG_OFFSET
/*------------------------------------------------------------------------- /* Check Processor Version Number */
Check Processor Version Number */
mfspr r3, PVR mfspr r3, PVR
rlwinm r3,r3,16,16,23 /* get ((Processor Version Number) & 0xFF00) */ rlwinm r3,r3,16,16,23 /* get ((Processor Version Number) & 0xFF00) */
@ -140,10 +134,10 @@ board_asm_init:
cmpli 0,0,r3,0x8000 /* MPC74xx */ cmpli 0,0,r3,0x8000 /* MPC74xx */
bne cont_brd_init bne cont_brd_init
/* ------------------------------------------ /*
For MPC744x/5x enable extended BATs[4-7] * For MPC744x/5x enable extended BATs[4-7]
Sri: Set HIGH_BAT_EN and XBSEN, and SPD =1 * Sri: Set HIGH_BAT_EN and XBSEN, and SPD =1
to disable prefetch * to disable prefetch
*/ */
mfspr r5, HID0 mfspr r5, HID0
@ -167,11 +161,10 @@ board_asm_init:
isync isync
sync sync
#if(1) /* def CONFIG_DUAL_CPU /* def CONFIG_DUAL_CPU
------------------------------------------------------------------------- * For MPC74xx processor, use MSSCR0[ID] bit to identify CPU number.
For MPC74xx processor, use MSSCR0[ID] bit to identify CPU number.
*/ */
#if(1)
mfspr r3,1014 /* read MSSCR0 */ mfspr r3,1014 /* read MSSCR0 */
rlwinm. r3,r3,27,31,31 /* get processor ID number */ rlwinm. r3,r3,27,31,31 /* get processor ID number */
mtspr SPRN_PIR,r3 /* Save CPU ID */ mtspr SPRN_PIR,r3 /* Save CPU ID */
@ -182,33 +175,29 @@ board_asm_init:
cont_brd_init: cont_brd_init:
/* An alternative method of checking the processor number (in addition /* An alternative method of checking the processor number (in addition
to configuration using MSSCR0[ID] bit on MPC74xx). * to configuration using MSSCR0[ID] bit on MPC74xx).
Good for IBM PPC750FX/GX. * Good for IBM PPC750FX/GX.
*/ */
lwz r3,PB_BUS_MS_SELECT(r4) /* read PB_ID register */ lwz r3,PB_BUS_MS_SELECT(r4) /* read PB_ID register */
rlwinm. r3,r3,24,31,31 /* get processor ID number */ rlwinm. r3,r3,24,31,31 /* get processor ID number */
bne init_done bne init_done
#else #else
cont_brd_init: cont_brd_init:
#endif /* CONFIG_DUAL_CPU */ #endif /* CONFIG_DUAL_CPU */
/* Initialize Tsi108 chip /* Initialize Tsi108 chip */
---------------------------------------------------------------------------
*/
do_tsi108_init: do_tsi108_init:
/*-------------------------------------------------------------------------- /*
Adjust HLP/Flash parameters. By default after reset the HLP port is set * Adjust HLP/Flash parameters. By default after reset the HLP port is
to support slow devices. Better performance can be achived when an optimal * set to support slow devices. Better performance can be achived when
parameters are used for specific EPROM device. * an optimal parameters are used for specific EPROM device.
NOTE: This should be performed ASAP for the emulation platform because * NOTE: This should be performed ASAP for the emulation platform
it has 5MHz HLP clocking. * because it has 5MHz HLP clocking.
*/ */
#ifdef CONFIG_TSI108EMU #ifdef CONFIG_TSI108EMU
@ -221,28 +210,25 @@ do_tsi108_init:
sync sync
#endif #endif
/* ------------------------------------------------------------------------- /* Initialize PB interface. */
* Initialize PB interface.
*/
ori r4,r29,TSI108_PB_REG_OFFSET ori r4,r29,TSI108_PB_REG_OFFSET
#if (CFG_TSI108_CSR_BASE != CFG_TSI108_CSR_RST_BASE) #if (CFG_TSI108_CSR_BASE != CFG_TSI108_CSR_RST_BASE)
/* Relocate (if required) Tsi108 registers. Set new value for PB_REG_BAR: /* Relocate (if required) Tsi108 registers. Set new value for
* PB_REG_BAR:
* Note we are in the 32-bit address mode. * Note we are in the 32-bit address mode.
*/ */
LOAD_U32(r5,(CFG_TSI108_CSR_BASE | 0x01)) /* value for PB_REG_BAR: BA + EN*/ LOAD_U32(r5,(CFG_TSI108_CSR_BASE | 0x01)) /* PB_REG_BAR: BA + EN */
stw r5,PB_REG_BAR(r4) stw r5,PB_REG_BAR(r4)
andis. r29,r5,0xFFFF andis. r29,r5,0xFFFF
sync sync
ori r4,r29,TSI108_PB_REG_OFFSET ori r4,r29,TSI108_PB_REG_OFFSET
#endif #endif
/* Set PB Slave configuration register */ /* Set PB Slave configuration register */
/* LOAD_U32(r5,0x000024C7) value for PB_SCR: TEA enabled,AACK delay = 7 */ LOAD_U32(r5,0x00002481) /* PB_SCR: TEA enabled,AACK delay = 1 */
LOAD_U32(r5,0x00002481) /* value for PB_SCR: TEA enabled,AACK delay = 1 */
lwz r3, PB_RSR(r4) /* get PB bus mode */ lwz r3, PB_RSR(r4) /* get PB bus mode */
xori r3,r3,0x0001 /* mask PB_BMODE: r3 -> (0 = 60X, 1 = MPX) */ xori r3,r3,0x0001 /* mask PB_BMODE: r3 -> (0 = 60X, 1 = MPX) */
rlwimi r5,r3,14,17,17 /* for MPX: set DTI_MODE bit */ rlwimi r5,r3,14,17,17 /* for MPX: set DTI_MODE bit */
@ -257,10 +243,7 @@ do_tsi108_init:
ori r3,r3,0x1000 /* add PBM_EN to clear (enabled by default) */ ori r3,r3,0x1000 /* add PBM_EN to clear (enabled by default) */
#endif #endif
andc r5,r5,r3 /* Clear the masked bit fields */ andc r5,r5,r3 /* Clear the masked bit fields */
/* ori r5,r5,0x0040 Set pipeline depth 4 ori r5,r5,0x0001 /* Set pipeline depth */
ori r5,r5,0x0080 Set pipeline depth 8
ori r5,r5,0x0020 !!!avb Testing: set pipeline depth 2 */
ori r5,r5,0x0001
stw r5,PB_ARB_CTRL(r4) stw r5,PB_ARB_CTRL(r4)
#if (0) /* currently using the default settings for PBM after reset */ #if (0) /* currently using the default settings for PBM after reset */
@ -274,9 +257,9 @@ do_tsi108_init:
#endif #endif
/* Disable or enable PVT based on processor bus frequency /* Disable or enable PVT based on processor bus frequency
1. Read CG_PWRUP_STATUS register field bits 18,17,16 * 1. Read CG_PWRUP_STATUS register field bits 18,17,16
2. See if the value is < or > 133mhz (18:16 = 100) * 2. See if the value is < or > 133mhz (18:16 = 100)
3. If > enable PVT * 3. If > enable PVT
*/ */
LOAD_U32(r3,0xC0002234) LOAD_U32(r3,0xC0002234)
@ -293,9 +276,7 @@ do_tsi108_init:
sync sync
#endif #endif
/*--------------------------------------------------------------------------- /* Initialize SDRAM controller. */
Initialize SDRAM controller.
----------------------------------------------------------------------------*/
sdc_init: sdc_init:
@ -337,7 +318,8 @@ get_nsec:
#ifdef SDC_HARDCODED_INIT /* config sdram controller with hardcoded values */ #ifdef SDC_HARDCODED_INIT /* config sdram controller with hardcoded values */
/* First read the CG_PWRUP_STATUS register to get the /* First read the CG_PWRUP_STATUS register to get the
memory speed from bits 22,21,20 */ * memory speed from bits 22,21,20
*/
LOAD_U32(r3,0xC0002234) LOAD_U32(r3,0xC0002234)
lwz r3,0(r3) lwz r3,0(r3)
@ -348,9 +330,9 @@ get_nsec:
cmpi 0,0,r3,0x0005 cmpi 0,0,r3,0x0005
bne check_for_200mhz bne check_for_200mhz
/* set values for 166 Mhz memory speed */ /* set values for 166 Mhz memory speed
* Set refresh rate and timing parameters
/* Set refresh rate and timing parameters */ */
LOAD_U32(r5,0x00000515) LOAD_U32(r5,0x00000515)
stw r5,SD_REFRESH(r4) stw r5,SD_REFRESH(r4)
LOAD_U32(r5,0x03073368) LOAD_U32(r5,0x03073368)
@ -386,9 +368,9 @@ check_for_200mhz:
cmpi 0,0,r3,0x0006 cmpi 0,0,r3,0x0006
bne set_default_values bne set_default_values
/* set values for 200Mhz memory speed */ /* set values for 200Mhz memory speed
* Set refresh rate and timing parameters
/* Set refresh rate and timing parameters */ */
LOAD_U32(r5,0x0000061a) LOAD_U32(r5,0x0000061a)
stw r5,SD_REFRESH(r4) stw r5,SD_REFRESH(r4)
LOAD_U32(r5,0x03083348) LOAD_U32(r5,0x03083348)
@ -449,11 +431,8 @@ set_default_values:
LOAD_U32(r5,VAL_SD_D1_BAR) LOAD_U32(r5,VAL_SD_D1_BAR)
stw r5,SD_D1_BAR(r4) stw r5,SD_D1_BAR(r4)
sync sync
#else /* !SDC_HARDCODED_INIT */ #else /* !SDC_HARDCODED_INIT */
bl tsi108_sdram_spd /* automatically detect SDC settings */ bl tsi108_sdram_spd /* automatically detect SDC settings */
#endif /* SDC_HARDCODED_INIT */ #endif /* SDC_HARDCODED_INIT */
sdc_init_done: sdc_init_done:
@ -481,43 +460,47 @@ sdc_init_done:
wait_init_complete: wait_init_complete:
lwz r5,SD_STATUS(r4) lwz r5,SD_STATUS(r4)
andi. r5,r5,0x0001 andi. r5,r5,0x0001
beq wait_init_complete /* wait until SDRAM initialization is complete */ /* wait until SDRAM initialization is complete */
beq wait_init_complete
/*--------------------------------------------------------------------------- /* Map SDRAM into the processor bus address space */
Map SDRAM into the processor bus address space
---------------------------------------------------------------------------*/
ori r4,r29,TSI108_PB_REG_OFFSET ori r4,r29,TSI108_PB_REG_OFFSET
/* Setup BARs associated with direct path PB<->SDRAM */ /* Setup BARs associated with direct path PB<->SDRAM */
/* PB_SDRAM_BAR1: /* PB_SDRAM_BAR1:
provides a direct path to the main system memory (cacheable SDRAM) */ * provides a direct path to the main system memory (cacheable SDRAM)
*/
LOAD_U32(r5, 0x00000011) /* BA=0,Size=512MB, ENable, No Addr.Translation */ /* BA=0,Size=512MB, ENable, No Addr.Translation */
LOAD_U32(r5, 0x00000011)
stw r5,PB_SDRAM_BAR1(r4) stw r5,PB_SDRAM_BAR1(r4)
sync sync
/* Make sure that PB_SDRAM_BAR1 decoder is set /* Make sure that PB_SDRAM_BAR1 decoder is set
(to allow following immediate read from SDRAM) */ * (to allow following immediate read from SDRAM)
*/
lwz r5,PB_SDRAM_BAR1(r4) lwz r5,PB_SDRAM_BAR1(r4)
sync sync
/* PB_SDRAM_BAR2: /* PB_SDRAM_BAR2:
provides non-cacheable alias (via the direct path) to main system memory. * provides non-cacheable alias (via the direct path) to main
Size = 512MB, ENable, Addr.Translation - ON, * system memory.
BA = 0x0_40000000, TA = 0x0_00000000 */ * Size = 512MB, ENable, Addr.Translation - ON,
* BA = 0x0_40000000, TA = 0x0_00000000
*/
LOAD_U32(r5, 0x40010011) LOAD_U32(r5, 0x40010011)
stw r5,PB_SDRAM_BAR2(r4) stw r5,PB_SDRAM_BAR2(r4)
sync sync
/* Make sure that PB_SDRAM_BAR2 decoder is set /* Make sure that PB_SDRAM_BAR2 decoder is set
(to allow following immediate read from SDRAM) */ * (to allow following immediate read from SDRAM)
*/
lwz r5,PB_SDRAM_BAR2(r4) lwz r5,PB_SDRAM_BAR2(r4)
sync sync
init_done: init_done:
/* All done. Restore LR and return. */ /* All done. Restore LR and return. */
@ -525,11 +508,11 @@ init_done:
blr blr
#if (0) #if (0)
/*=========================================================================== /*
init_cpu1 * init_cpu1
* This routine enables CPU1 on the dual-processor system.
This routine enables CPU1 on the dual-processor system. * Now there is only one processor in the system
===========================================================================*/ */
.global enable_cpu1 .global enable_cpu1
enable_cpu1: enable_cpu1:
@ -545,11 +528,10 @@ enable_cpu1:
blr blr
#endif #endif
/*=========================================================================== /*
enable_EI * enable_EI
* Enable CPU core external interrupt
Enable CPU core external interrupt */
===========================================================================*/
.global enable_EI .global enable_EI
enable_EI: enable_EI:
@ -558,11 +540,10 @@ enable_EI:
mtmsr r3 mtmsr r3
blr blr
/*=========================================================================== /*
disable_EI * disable_EI
* Disable CPU core external interrupt
Disable CPU core external interrupt */
===========================================================================*/
.global disable_EI .global disable_EI
disable_EI: disable_EI:
@ -573,11 +554,7 @@ disable_EI:
blr blr
#ifdef ENABLE_SDRAM_ECC #ifdef ENABLE_SDRAM_ECC
/*=========================================================================== /* enables SDRAM ECC */
enable_ECC
enables SDRAM ECC
===========================================================================*/
.global enable_ECC .global enable_ECC
enable_ECC: enable_ECC:
@ -587,17 +564,15 @@ enable_ECC:
stw r3,SD_ECC_CTRL(r4) stw r3,SD_ECC_CTRL(r4)
blr blr
/*=========================================================================== /*
clear_ECC_err * clear_ECC_err
* Clears all pending SDRAM ECC errors
Clears all pending SDRAM ECC errors * (normally after SDRAM scrubbing/initialization)
(normally after SDRAM scrubbing/initialization) */
===========================================================================*/
.global clear_ECC_err .global clear_ECC_err
clear_ECC_err: clear_ECC_err:
ori r4,r29,TSI108_SD_REG_OFFSET ori r4,r29,TSI108_SD_REG_OFFSET
/* lwz r3,SD_INT_STATUS(r4) Read SDRAM ECC Control Register */
ori r3,r0,0x0030 /* ECC_UE_INT + ECC_CE_INT bits */ ori r3,r0,0x0030 /* ECC_UE_INT + ECC_CE_INT bits */
stw r3,SD_INT_STATUS(r4) stw r3,SD_INT_STATUS(r4)
blr blr
@ -606,10 +581,7 @@ clear_ECC_err:
#ifndef SDC_HARDCODED_INIT #ifndef SDC_HARDCODED_INIT
/******************************************************************** /* SDRAM SPD Support */
* SDRAM SPD Support
*/
#define SD_I2C_CTRL1 (0x400) #define SD_I2C_CTRL1 (0x400)
#define SD_I2C_CTRL2 (0x404) #define SD_I2C_CTRL2 (0x404)
#define SD_I2C_RD_DATA (0x408) #define SD_I2C_RD_DATA (0x408)
@ -682,14 +654,14 @@ refresh_rates: /* in nSec */
.long 62500 /* Extended 4x (0x84) */ .long 62500 /* Extended 4x (0x84) */
.long 125000 /* Extended 8x (0x85) */ .long 125000 /* Extended 8x (0x85) */
/*=========================================================================== /*
* tsi108_sdram_spd * tsi108_sdram_spd
* *
* Inittializes SDRAM Controller using DDR2 DIMM Serial Presence Detect data * Inittializes SDRAM Controller using DDR2 DIMM Serial Presence Detect data
* Uses registers: r4 - SDC base address (not changed) * Uses registers: r4 - SDC base address (not changed)
* r9 - SDC clocking period in nSec * r9 - SDC clocking period in nSec
* Changes registers: r3,r5,r6,r7,r8,r10,r11 * Changes registers: r3,r5,r6,r7,r8,r10,r11
*==========================================================================*/ */
tsi108_sdram_spd: tsi108_sdram_spd:
@ -698,9 +670,7 @@ tsi108_sdram_spd:
do_first_dimm: do_first_dimm:
/************************************** /* Program Refresh Rate Register */
* Program Refresh Rate Register
*/
READ_SPD(12) /* get Refresh Rate */ READ_SPD(12) /* get Refresh Rate */
beq check_next_slot beq check_next_slot
@ -718,9 +688,7 @@ do_first_dimm:
stw r5,SD_REFRESH(r4) /* Set refresh rate */ stw r5,SD_REFRESH(r4) /* Set refresh rate */
sync sync
/************************************** /* Program SD Timing Register */
* Program SD Timing Register
*/
li r7, 0 /* clear r7 prior parameter collection */ li r7, 0 /* clear r7 prior parameter collection */
@ -768,7 +736,8 @@ set_tras:
READ_SPD(29) /* Get tRCD */ READ_SPD(29) /* Get tRCD */
beq spd_read_fail beq spd_read_fail
rlwinm r3,r3,30,2,31/* right shift tRCD by 2 bits as per DDR2 spec */ /* right shift tRCD by 2 bits as per DDR2 spec */
rlwinm r3,r3,30,2,31
divwu r6,r3,r9 divwu r6,r3,r9
mullw r8,r6,r9 mullw r8,r6,r9
subf. r8,r8,r3 subf. r8,r8,r3
@ -829,17 +798,14 @@ set_trfc:
stw r7,SD_TIMING(r4) stw r7,SD_TIMING(r4)
sync sync
/*===================================================================== /*
* The following two registers are set on per-DIMM basis. * The following two registers are set on per-DIMM basis.
* The SD_REFRESH and SD_TIMING settings are common for both DIMMS * The SD_REFRESH and SD_TIMING settings are common for both DIMMS
*=====================================================================
*/ */
do_each_dimm: do_each_dimm:
/***************************************** /* Program SDRAM DIMM Control Register */
* Program SDRAM DIMM Control Register
*/
li r7, 0 /* clear r7 prior parameter collection */ li r7, 0 /* clear r7 prior parameter collection */
@ -897,9 +863,7 @@ set_dimm_ctrl:
sync sync
/******************************************** /* Program SDRAM DIMMx Base Address Register */
* Program SDRAM DIMMx Base Address Register
*/
set_dimm_bar: set_dimm_bar:
READ_SPD(5) /* get # of Ranks */ READ_SPD(5) /* get # of Ranks */
@ -952,4 +916,3 @@ err_hung: /* hang here for debugging */
b err_hung b err_hung
#endif /* !SDC_HARDCODED_INIT */ #endif /* !SDC_HARDCODED_INIT */

10
board/mpc7448hpc2/mpc7448hpc2.c
View File

@ -57,7 +57,6 @@ void after_reloc(ulong dest_addr)
/* /*
* Check Board Identity: * Check Board Identity:
*
* report board type * report board type
*/ */
@ -369,10 +368,9 @@ int mem_test_walk(void)
for (i = 0; i < 63; i++) { for (i = 0; i < 63; i++) {
printf ("Pass %2d", i + 2); printf ("Pass %2d", i + 2);
if (mem_march(pmem, size, mask, mask << 1, 1, 1) != 0) { if (mem_march(pmem, size, mask, mask << 1, 1, 1) != 0)
/*printf ("mask: 0x%x, pass: %d, ", mask, i); */ /*printf ("mask: 0x%x, pass: %d, ", mask, i); */
return 1; return 1;
}
mask = mask << 1; mask = mask << 1;
printf ("\b\b\b\b\b\b\b"); printf ("\b\b\b\b\b\b\b");
} }
@ -428,11 +426,10 @@ int testdram(void)
/* runaddress = 0; */ /* runaddress = 0; */
/* runwalk = 0; */ /* runwalk = 0; */
if ((rundata == 1) || (runaddress == 1) || (runwalk == 1)) { if ((rundata == 1) || (runaddress == 1) || (runwalk == 1))
printf ("Testing RAM from 0x%08x to 0x%08x ... \ printf ("Testing RAM from 0x%08x to 0x%08x ... \
(don't panic... that will take a moment !!!!)\n", \ (don't panic... that will take a moment !!!!)\n", \
CFG_MEMTEST_START, CFG_MEMTEST_END); CFG_MEMTEST_START, CFG_MEMTEST_END);
}
#ifdef CFG_DRAM_TEST_DATA #ifdef CFG_DRAM_TEST_DATA
if (rundata == 1) { if (rundata == 1) {
printf ("Test DATA ... "); printf ("Test DATA ... ");
@ -463,9 +460,8 @@ int testdram(void)
printf ("ok \n"); printf ("ok \n");
} }
#endif #endif
if ((rundata == 1) || (runaddress == 1) || (runwalk == 1)) { if ((rundata == 1) || (runaddress == 1) || (runwalk == 1))
printf ("passed\n"); printf ("passed\n");
}
return 0; return 0;
} }

43
board/mpc7448hpc2/tsi108_init.c
View File

@ -145,26 +145,27 @@ int board_early_init_f(void)
ulong i; ulong i;
gd->mem_clk = 0; gd->mem_clk = 0;
i = in32(CFG_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PWRUP_STATUS); i = in32 (CFG_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET +
i = (i >> 20) & 0x07; CG_PWRUP_STATUS);
i = (i >> 20) & 0x07; /* value of SW4[4:7] */
switch (i) { switch (i) {
case 0: case 0: /* external clock */
printf ("Using external clock\n"); printf ("Using external clock\n");
break; break;
case 1: case 1: /* system clock */
gd->mem_clk = gd->bus_clk; gd->mem_clk = gd->bus_clk;
break; break;
case 4: case 4: /* 133 MHz */
case 5: case 5: /* 166 MHz */
case 6: case 6: /* 200 MHz */
gd->mem_clk = pb_clk_sel[i] * 1000000; gd->mem_clk = pb_clk_sel[i] * 1000000;
break; break;
default: default:
printf ("Invalid DDR2 clock setting\n"); printf ("Invalid DDR2 clock setting\n");
return -1; return -1;
} }
printf("BUS! %d MHz\n", get_board_bus_clk() / 1000000); printf ("BUS: %d MHz\n", get_board_bus_clk() / 1000000);
printf("MEM! %d MHz\n", gd->mem_clk / 1000000); printf ("MEM: %d MHz\n", gd->mem_clk / 1000000);
return 0; return 0;
} }
@ -338,10 +339,9 @@ int board_early_init_r(void)
temp = get_cpu_type (); temp = get_cpu_type ();
if ((CPU_750FX == temp) || (CPU_750GX == temp)) { if ((CPU_750FX == temp) || (CPU_750GX == temp))
out32 (CFG_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + PB_MCMD, out32 (CFG_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + PB_MCMD,
0x00009955); 0x00009955);
}
#endif /* DISABLE_PBM */ #endif /* DISABLE_PBM */
#ifdef CONFIG_PCI #ifdef CONFIG_PCI
@ -350,8 +350,8 @@ int board_early_init_r(void)
*/ */
/* Map PCI/X Configuration Space (16MB @ 0x0_FE000000) */ /* Map PCI/X Configuration Space (16MB @ 0x0_FE000000) */
out32(CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_PFAB_BAR0_UPPER, out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET +
0); PCI_PFAB_BAR0_UPPER, 0);
__asm__ __volatile__ ("sync"); __asm__ __volatile__ ("sync");
out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_PFAB_BAR0, out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_PFAB_BAR0,
@ -360,8 +360,8 @@ int board_early_init_r(void)
/* Set Bus Number for the attached PCI/X bus (we will use 0 for NB) */ /* Set Bus Number for the attached PCI/X bus (we will use 0 for NB) */
temp = temp = in32(CFG_TSI108_CSR_BASE +
in32(CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_PCIX_STAT); TSI108_PCI_REG_OFFSET + PCI_PCIX_STAT);
temp &= ~0xFF00; /* Clear the BUS_NUM field */ temp &= ~0xFF00; /* Clear the BUS_NUM field */
@ -510,8 +510,8 @@ int board_early_init_r(void)
#ifdef ENABLE_PCI_CSR_BAR #ifdef ENABLE_PCI_CSR_BAR
/* open if required access to Tsi108 CSRs from the PCI/X bus */ /* open if required access to Tsi108 CSRs from the PCI/X bus */
/* enable BAR0 on the PCI/X bus */ /* enable BAR0 on the PCI/X bus */
reg_val = reg_val = in32(CFG_TSI108_CSR_BASE +
in32(CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_MISC_CSR); TSI108_PCI_REG_OFFSET + PCI_MISC_CSR);
reg_val |= 0x02; reg_val |= 0x02;
out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_MISC_CSR, out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_MISC_CSR,
reg_val); reg_val);
@ -595,8 +595,10 @@ int misc_init_r(void)
* Uses pre-calculated value for Fout = 800 MHz, Fs = 30 kHz, D = 0.5% * Uses pre-calculated value for Fout = 800 MHz, Fs = 30 kHz, D = 0.5%
*/ */
out32(CFG_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PLL1_CTRL0, 0x002e0044); /* D = 0.25% */ out32 (CFG_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PLL1_CTRL0,
out32(CFG_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PLL1_CTRL1, 0x00000039); /* BWADJ */ 0x002e0044); /* D = 0.25% */
out32 (CFG_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PLL1_CTRL1,
0x00000039); /* BWADJ */
/* Initialize PLL0: CG_PB_CLKO */ /* Initialize PLL0: CG_PB_CLKO */
/* Detect PB clock freq. */ /* Detect PB clock freq. */
@ -610,7 +612,8 @@ int misc_init_r(void)
/* Wait and set SSEN for both PLL0 and 1 */ /* Wait and set SSEN for both PLL0 and 1 */
udelay (1000); udelay (1000);
out32(CFG_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PLL1_CTRL0, 0x802e0044); /* D=0.25% */ out32 (CFG_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PLL1_CTRL0,
0x802e0044); /* D=0.25% */
out32 (CFG_TSI108_CSR_BASE + out32 (CFG_TSI108_CSR_BASE +
TSI108_CLK_REG_OFFSET + CG_PLL0_CTRL0, TSI108_CLK_REG_OFFSET + CG_PLL0_CTRL0,
0x80000000 | pll0_config[i].ctrl0); 0x80000000 | pll0_config[i].ctrl0);

16
cpu/74xx_7xx/speed.c
View File

@ -127,16 +127,17 @@ int get_clocks (void)
ulong clock = 0; ulong clock = 0;
#ifdef CFG_CONFIG_BUS_CLK #ifdef CFG_CONFIG_BUS_CLK
gd->bus_clk = get_board_bus_clk(); gd->bus_clk = get_board_bus_clk (); /* bus clock is configurable */
#else #else
gd->bus_clk = CFG_BUS_CLK; gd->bus_clk = CFG_BUS_CLK; /* bus clock is a fixed frequency */
#endif #endif
/* calculate the clock frequency based upon the CPU type */ /* calculate the clock frequency based upon the CPU type */
switch (get_cpu_type()) { switch (get_cpu_type()) {
case CPU_7447A: case CPU_7447A:
case CPU_7448: case CPU_7448:
clock = (gd->bus_clk / 10) * hid1_7447A_multipliers_x_10[(get_hid1 () >> 12) & 0x1F]; clock = (gd->bus_clk / 10) *
hid1_7447A_multipliers_x_10[(get_hid1 () >> 12) & 0x1F];
break; break;
case CPU_7455: case CPU_7455:
@ -146,12 +147,14 @@ int get_clocks (void)
* Make sure division is done before multiplication to prevent 32-bit * Make sure division is done before multiplication to prevent 32-bit
* arithmetic overflows which will cause a negative number * arithmetic overflows which will cause a negative number
*/ */
clock = (gd->bus_clk / 10) * hid1_multipliers_x_10[(get_hid1 () >> 13) & 0xF]; clock = (gd->bus_clk / 10) *
hid1_multipliers_x_10[(get_hid1 () >> 13) & 0xF];
break; break;
case CPU_750GX: case CPU_750GX:
case CPU_750FX: case CPU_750FX:
clock = gd->bus_clk * hid1_fx_multipliers_x_10[get_hid1 () >> 27] / 10; clock = gd->bus_clk *
hid1_fx_multipliers_x_10[get_hid1 () >> 27] / 10;
break; break;
case CPU_7450: case CPU_7450:
@ -168,7 +171,8 @@ int get_clocks (void)
* Make sure division is done before multiplication to prevent 32-bit * Make sure division is done before multiplication to prevent 32-bit
* arithmetic overflows which will cause a negative number * arithmetic overflows which will cause a negative number
*/ */
clock = (gd->bus_clk / 10) * hid1_multipliers_x_10[get_hid1 () >> 28]; clock = (gd->bus_clk / 10) *
hid1_multipliers_x_10[get_hid1 () >> 28];
break; break;
case CPU_UNKNOWN: case CPU_UNKNOWN:

8
doc/README.mpc7448hpc2
View File

@ -39,7 +39,6 @@ The mapping is:
0xff00_0000 0xff80_0000 FLASH (boot flash) 8M 0xff00_0000 0xff80_0000 FLASH (boot flash) 8M
0xff80_0000 0xffff_ffff FLASH (second half flash) 8M 0xff80_0000 0xffff_ffff FLASH (second half flash) 8M
Using Flash Using Flash
----------- -----------
@ -67,16 +66,13 @@ it into the secondary bank:
erase ff000000 ff080000 erase ff000000 ff080000
cp.b 10000 ff000000 80000 cp.b 10000 ff000000 80000
After copying the image into the second bank of flash, be sure to toggle After copying the image into the second bank of flash, be sure to toggle
SW3[4] on board before resetting the board in order to set the SW3[4] on board before resetting the board in order to set the
secondary bank as the boot-bank. secondary bank as the boot-bank.
Board Switches Board Switches
---------------------- ----------------------
Most switches on the board should not be changed. The most frequent Most switches on the board should not be changed. The most frequent
user-settable switches on the board are used to configure user-settable switches on the board are used to configure
the flash banks and determining the PCI frequency. the flash banks and determining the PCI frequency.
@ -111,7 +107,6 @@ SW2[1-6]: CPU core frequency
This table shows only a subset of available frequency options; see the CPU This table shows only a subset of available frequency options; see the CPU
hardware specifications for more information. hardware specifications for more information.
SW2[7-8]: Bus Protocol and CPU Reset Option SW2[7-8]: Bus Protocol and CPU Reset Option
7 7
@ -124,7 +119,6 @@ SW2[7-8]: Bus Protocol and CPU Reset Option
SW2=0 TSI108 can cause CPU reset SW2=0 TSI108 can cause CPU reset
SW2=1 TSI108 can not cause CPU reset SW2=1 TSI108 can not cause CPU reset
SW3[1-8] system options SW3[1-8] system options
123 123
@ -167,7 +161,6 @@ SW4[1-3]: System bus frequency
SW4=110 200 only for MPC7448 SW4=110 200 only for MPC7448
others reserved others reserved
SW4[4-6]: DDR2 SDRAM frequency SW4[4-6]: DDR2 SDRAM frequency
Bus Frequency (MHz) Bus Frequency (MHz)
@ -179,7 +172,6 @@ SW4[4-6]: DDR2 SDRAM frequency
SW4=110 200 SW4=110 200
others reserved others reserved
SW4[7-8]: PCI/PCI-X frequency control SW4[7-8]: PCI/PCI-X frequency control
7 7
- -

37
drivers/tsi108_eth.c
View File

@ -46,7 +46,9 @@
#endif #endif
#if TSI108_ETH_DEBUG > 0 #if TSI108_ETH_DEBUG > 0
#define debug_lev(lev, fmt, args...) if (lev <= TSI108_ETH_DEBUG) printf("%s %d: " fmt, __FUNCTION__, __LINE__, ##args) #define debug_lev(lev, fmt, args...) \
if (lev <= TSI108_ETH_DEBUG) \
printf ("%s %d: " fmt, __FUNCTION__, __LINE__, ##args)
#else #else
#define debug_lev(lev, fmt, args...) do{}while(0) #define debug_lev(lev, fmt, args...) do{}while(0)
#endif #endif
@ -658,9 +660,8 @@ static int marvell_88e_phy_config(struct eth_device *dev, int *speed,
} }
} while ((phy_status & PHY_STAT_LINK_UP) == 0); } while ((phy_status & PHY_STAT_LINK_UP) == 0);
if ((phy_status & PHY_STAT_LINK_UP) == 0) { if ((phy_status & PHY_STAT_LINK_UP) == 0)
return 0; return 0;
}
value = 0; value = 0;
phy_spec_status = read_phy (ETH_BASE, phy_addr, MV1111_SPEC_STAT_REG); phy_spec_status = read_phy (ETH_BASE, phy_addr, MV1111_SPEC_STAT_REG);
@ -681,10 +682,9 @@ static int marvell_88e_phy_config(struct eth_device *dev, int *speed,
if (phy_spec_status & SPEC_STAT_FULL_DUP) { if (phy_spec_status & SPEC_STAT_FULL_DUP) {
phy_duplex = LINK_DUPLEX_FULL; phy_duplex = LINK_DUPLEX_FULL;
value |= PHY_CTRL_FULL_DUPLEX; value |= PHY_CTRL_FULL_DUPLEX;
} else { } else
phy_duplex = LINK_DUPLEX_HALF; phy_duplex = LINK_DUPLEX_HALF;
} }
}
/* set TBI speed */ /* set TBI speed */
write_phy (base, TBI_ADDR, PHY_CTRL_REG, value); write_phy (base, TBI_ADDR, PHY_CTRL_REG, value);
write_phy (base, TBI_ADDR, PHY_AN_ADV_REG, 0x0060); write_phy (base, TBI_ADDR, PHY_AN_ADV_REG, 0x0060);
@ -704,22 +704,19 @@ static int marvell_88e_phy_config(struct eth_device *dev, int *speed,
printf (", 10 Mbps"); printf (", 10 Mbps");
break; break;
} }
if (phy_duplex == LINK_DUPLEX_FULL) { if (phy_duplex == LINK_DUPLEX_FULL)
printf (", Full duplex"); printf (", Full duplex");
} else { else
printf (", Half duplex"); printf (", Half duplex");
} }
}
printf ("\n"); printf ("\n");
#endif #endif
dump_phy_regs (TBI_ADDR); dump_phy_regs (TBI_ADDR);
if (speed) { if (speed)
*speed = phy_speed; *speed = phy_speed;
} if (duplex)
if (duplex) {
*duplex = phy_duplex; *duplex = phy_duplex;
}
return 1; return 1;
} }
@ -794,25 +791,23 @@ static int tsi108_eth_probe(struct eth_device *dev, bd_t * bis)
reg_STATION_ADDRESS_2(base) = (dev->enetaddr[1] << 24) | reg_STATION_ADDRESS_2(base) = (dev->enetaddr[1] << 24) |
(dev->enetaddr[0] << 16); (dev->enetaddr[0] << 16);
if (marvell_88e_phy_config(dev, &speed, &duplex) == 0) { if (marvell_88e_phy_config(dev, &speed, &duplex) == 0)
return 0; return 0;
}
value = value =
MAC_CONFIG_2_PREAMBLE_LENGTH(7) | MAC_CONFIG_2_PAD_CRC | MAC_CONFIG_2_PREAMBLE_LENGTH(7) | MAC_CONFIG_2_PAD_CRC |
MAC_CONFIG_2_CRC_ENABLE; MAC_CONFIG_2_CRC_ENABLE;
if (speed == LINK_SPEED_1000) { if (speed == LINK_SPEED_1000)
value |= MAC_CONFIG_2_INTERFACE_MODE(INTERFACE_MODE_BYTE); value |= MAC_CONFIG_2_INTERFACE_MODE(INTERFACE_MODE_BYTE);
} else { else {
value |= MAC_CONFIG_2_INTERFACE_MODE(INTERFACE_MODE_NIBBLE); value |= MAC_CONFIG_2_INTERFACE_MODE(INTERFACE_MODE_NIBBLE);
reg_PORT_CONTROL(base) |= PORT_CONTROL_SPD; reg_PORT_CONTROL(base) |= PORT_CONTROL_SPD;
} }
if (duplex == LINK_DUPLEX_FULL) { if (duplex == LINK_DUPLEX_FULL) {
value |= MAC_CONFIG_2_FULL_DUPLEX; value |= MAC_CONFIG_2_FULL_DUPLEX;
reg_PORT_CONTROL(base) &= ~PORT_CONTROL_BPT; reg_PORT_CONTROL(base) &= ~PORT_CONTROL_BPT;
} else { } else
reg_PORT_CONTROL(base) |= PORT_CONTROL_BPT; reg_PORT_CONTROL(base) |= PORT_CONTROL_BPT;
}
reg_MAC_CONFIG_2(base) = value; reg_MAC_CONFIG_2(base) = value;
reg_RX_CONFIG(base) = RX_CONFIG_SE; reg_RX_CONFIG(base) = RX_CONFIG_SE;
@ -894,9 +889,8 @@ static int tsi108_eth_send(struct eth_device *dev,
(unsigned long)tx_descr + (unsigned long)tx_descr +
sizeof(struct dma_descriptor)); sizeof(struct dma_descriptor));
if (timeout != 0) { if (timeout != 0)
udelay (15); udelay (15);
}
if (++timeout > 10000) { if (++timeout > 10000) {
tx_diag_regs(base); tx_diag_regs(base);
debug_lev(1, debug_lev(1,
@ -1004,10 +998,9 @@ static int tsi108_eth_recv(struct eth_device *dev)
rx_descr = rx_descr =
(struct dma_descriptor (struct dma_descriptor
*)(le32_to_cpu (rx_descr->next_descr_addr0)); *)(le32_to_cpu (rx_descr->next_descr_addr0));
if (rx_descr == 0) { if (rx_descr == 0)
rx_descr = &rx_descr_array[0]; rx_descr = &rx_descr_array[0];
} }
}
/* remember where we are for next time */ /* remember where we are for next time */
rx_descr_current = rx_descr; rx_descr_current = rx_descr;

14
drivers/tsi108_i2c.c
View File

@ -23,10 +23,9 @@
*/ */
#include <config.h> #include <config.h>
#include <common.h>
#ifdef CONFIG_TSI108_I2C #ifdef CONFIG_TSI108_I2C
#include <common.h>
#include <tsi108.h> #include <tsi108.h>
#if (CONFIG_COMMANDS & CFG_CMD_I2C) #if (CONFIG_COMMANDS & CFG_CMD_I2C)
@ -58,16 +57,14 @@ static int i2c_read_byte(
DPRINT (("I2C read_byte() %d 0x%02x 0x%02x\n", DPRINT (("I2C read_byte() %d 0x%02x 0x%02x\n",
i2c_chan, chip_addr, byte_addr)); i2c_chan, chip_addr, byte_addr));
if (0 != i2c_chan) { if (0 != i2c_chan)
chan_offset = TSI108_I2C_SDRAM_OFFSET; chan_offset = TSI108_I2C_SDRAM_OFFSET;
}
/* Check if I2C operation is in progress */ /* Check if I2C operation is in progress */
temp = *(u32 *) (CFG_TSI108_CSR_BASE + chan_offset + I2C_CNTRL2); temp = *(u32 *) (CFG_TSI108_CSR_BASE + chan_offset + I2C_CNTRL2);
if (0 == (temp & (I2C_CNTRL2_RD_STATUS | I2C_CNTRL2_WR_STATUS | if (0 == (temp & (I2C_CNTRL2_RD_STATUS | I2C_CNTRL2_WR_STATUS |
I2C_CNTRL2_START)) I2C_CNTRL2_START))) {
) {
/* Set device address and operation (read = 0) */ /* Set device address and operation (read = 0) */
temp = (byte_addr << 16) | ((chip_addr & 0x07) << 8) | temp = (byte_addr << 16) | ((chip_addr & 0x07) << 8) |
((chip_addr >> 3) & 0x0F); ((chip_addr >> 3) & 0x0F);
@ -141,7 +138,8 @@ static int i2c_read_byte(
* Returns: 0 on success, not 0 on failure * Returns: 0 on success, not 0 on failure
*/ */
int i2c_read(uchar chip_addr, uint byte_addr, int alen, uchar * buffer, int len) int i2c_read (uchar chip_addr, uint byte_addr, int alen,
uchar * buffer, int len)
{ {
u32 op_status = TSI108_I2C_PARAM_ERR; u32 op_status = TSI108_I2C_PARAM_ERR;
u32 i2c_if = 0; u32 i2c_if = 0;
@ -210,7 +208,7 @@ static int i2c_write_byte(uchar chip_addr,/* I2C device address on the bus */
/* Wait until operation completed */ /* Wait until operation completed */
do { do {
// Read I2C operation status /* Read I2C operation status */
temp = temp =
*(u32 *) (CFG_TSI108_CSR_BASE + TSI108_I2C_OFFSET + *(u32 *) (CFG_TSI108_CSR_BASE + TSI108_I2C_OFFSET +
I2C_CNTRL2); I2C_CNTRL2);

26
include/configs/mpc7448hpc2.h
View File

@ -24,12 +24,11 @@
* MA 02111-1307 USA * MA 02111-1307 USA
*/ */
/**************************************************************** /*
*
* board specific configuration options for Freescale * board specific configuration options for Freescale
* MPC7448HPC2 (High-Performance Computing II) (Taiga) board * MPC7448HPC2 (High-Performance Computing II) (Taiga) board
* *
****************************************************************/ */
#ifndef __CONFIG_H #ifndef __CONFIG_H
#define __CONFIG_H #define __CONFIG_H
@ -99,8 +98,8 @@
* for your console driver. * for your console driver.
* *
* what to do: * what to do:
* If you have hacked a serial cable onto the second DUART channel, change the CFG_DUART port from 1 * If you have hacked a serial cable onto the second DUART channel,
* to 0 below. * change the CFG_DUART port from 1 to 0 below.
* *
*/ */
@ -118,7 +117,8 @@
#define CONFIG_ZERO_BOOTDELAY_CHECK #define CONFIG_ZERO_BOOTDELAY_CHECK
#undef CONFIG_BOOTARGS #undef CONFIG_BOOTARGS
/*#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo" */ /* #define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\"
* to mount root filesystem over NFS;echo" */
#if (CONFIG_BOOTDELAY >= 0) #if (CONFIG_BOOTDELAY >= 0)
#define CONFIG_BOOTCOMMAND "tftpboot 0x400000 zImage.initrd.elf;\ #define CONFIG_BOOTCOMMAND "tftpboot 0x400000 zImage.initrd.elf;\
@ -211,8 +211,8 @@
* CFG_DRAM_TEST_DATA - Enables test for shorted or open data lines * CFG_DRAM_TEST_DATA - Enables test for shorted or open data lines
* Environment variable 'test_dram_data' must be * Environment variable 'test_dram_data' must be
* set to 'y'. * set to 'y'.
* CFG_DRAM_TEST_ADDRESS - Enables test to verify that each word is uniquely * CFG_DRAM_TEST_ADDRESS - Enables test to verify that each word
* addressable. Environment variable * is uniquely addressable. Environment variable
* 'test_dram_address' must be set to 'y'. * 'test_dram_address' must be set to 'y'.
* CFG_DRAM_TEST_WALK - Enables test a 64-bit walking ones pattern test. * CFG_DRAM_TEST_WALK - Enables test a 64-bit walking ones pattern test.
* This test takes about 6 minutes to test 64 MB. * This test takes about 6 minutes to test 64 MB.
@ -286,9 +286,9 @@
/* Peripheral Device section */ /* Peripheral Device section */
/******************************************************* /*
* Resources on the Tsi108 * Resources on the Tsi108
*******************************************************/ */
#define CFG_TSI108_CSR_RST_BASE 0xC0000000 /* Tsi108 CSR base after reset */ #define CFG_TSI108_CSR_RST_BASE 0xC0000000 /* Tsi108 CSR base after reset */
#define CFG_TSI108_CSR_BASE CFG_TSI108_CSR_RST_BASE /* Runtime Tsi108 CSR base */ #define CFG_TSI108_CSR_BASE CFG_TSI108_CSR_RST_BASE /* Runtime Tsi108 CSR base */
@ -297,9 +297,9 @@
#undef DISABLE_PBM #undef DISABLE_PBM
/*----------------------------------------------------------------------- /*
* PCI stuff * PCI stuff
*----------------------------------------------------------------------- *
*/ */
#define CONFIG_PCI /* include pci support */ #define CONFIG_PCI /* include pci support */
@ -321,7 +321,7 @@
/* PCI Memory Space */ /* PCI Memory Space */
#define CFG_PCI_MEM_BUS (CFG_PCI_MEM_PHYS) #define CFG_PCI_MEM_BUS (CFG_PCI_MEM_PHYS)
#define CFG_PCI_MEM_PHYS (CFG_PCI_MEM32_BASE) //CFG_PCI_MEM32_BASE = 0xE0000000 #define CFG_PCI_MEM_PHYS (CFG_PCI_MEM32_BASE) /* 0xE0000000 */
#define CFG_PCI_MEM_SIZE 0x10000000 /* 256 MB space for PCI/X Mem + SDRAM OCN */ #define CFG_PCI_MEM_SIZE 0x10000000 /* 256 MB space for PCI/X Mem + SDRAM OCN */
/* PCI I/O Space */ /* PCI I/O Space */

4
include/tsi108.h
View File

@ -205,8 +205,8 @@
/* I2C_TX_DATA : Unused/Reserved bits Definition */ /* I2C_TX_DATA : Unused/Reserved bits Definition */
#define I2C_TX_DATA_RESERVED (0x00000000) #define I2C_TX_DATA_RESERVED (0x00000000)
#define TSI108_I2C_OFFSET 0x7000 /* register block offset for general use I2C channel */ #define TSI108_I2C_OFFSET 0x7000 /* offset for general use I2C channel */
#define TSI108_I2C_SDRAM_OFFSET 0x4400 /* register block offset for SPD I2C channel */ #define TSI108_I2C_SDRAM_OFFSET 0x4400 /* offset for SPD I2C channel */
#define I2C_EEPROM_DEVCODE 0xA /* standard I2C EEPROM device code */ #define I2C_EEPROM_DEVCODE 0xA /* standard I2C EEPROM device code */