liliana/r-link-uboot
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

Merge branch 'denx'

Browse Source
This commit is contained in:
Andy Fleming 2007-10-19 11:24:22 -05:00 committed by Andrew Fleming-AFLEMING
commit d4d1e9bee7
181 changed files with 6684 additions and 1134 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1419
CHANGELOG
View File

File diff suppressed because it is too large Load Diff

4
MAKEALL
View File

@ -301,10 +301,12 @@ LIST_83xx=" \
MPC8313ERDB_66 \
MPC8323ERDB \
MPC832XEMDS \
MPC832XEMDS_ATM \
MPC8349EMDS \
MPC8349ITX \
MPC8349ITXGP \
MPC8360EMDS \
MPC8360EMDS_ATM \
sbc8349 \
TQM834x \
"
@ -341,7 +343,7 @@ LIST_85xx=" \
LIST_86xx=" \
MPC8641HPCN \
SBC8641D \
sbc8641d \
"
#########################################################################

42
Makefile
View File

@ -1,5 +1,5 @@
#
# (C) Copyright 2000-2006
# (C) Copyright 2000-2007
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
@ -22,9 +22,9 @@
#
VERSION = 1
PATCHLEVEL = 2
PATCHLEVEL = 3
SUBLEVEL = 0
EXTRAVERSION =
EXTRAVERSION = -rc3
U_BOOT_VERSION = $(VERSION).$(PATCHLEVEL).$(SUBLEVEL)$(EXTRAVERSION)
VERSION_FILE = $(obj)include/version_autogenerated.h
@ -211,6 +211,7 @@ LIBS += drivers/libdrivers.a
LIBS += drivers/bios_emulator/libatibiosemu.a
LIBS += drivers/nand/libnand.a
LIBS += drivers/nand_legacy/libnand_legacy.a
LIBS += drivers/onenand/libonenand.a
LIBS += drivers/net/libnet.a
ifeq ($(CPU),mpc83xx)
LIBS += drivers/qe/qe.a
@ -319,7 +320,7 @@ updater:
env:
$(MAKE) -C tools/env all || exit 1
depend dep:
depend dep: version
for dir in $(SUBDIRS) ; do $(MAKE) -C $$dir _depend ; done
tags ctags:
@ -1765,7 +1766,8 @@ MPC8323ERDB_config: unconfig
MPC832XEMDS_config \
MPC832XEMDS_HOST_33_config \
MPC832XEMDS_HOST_66_config \
MPC832XEMDS_SLAVE_config: unconfig
MPC832XEMDS_SLAVE_config \
MPC832XEMDS_ATM_config: unconfig
@mkdir -p $(obj)include
@echo "" >$(obj)include/config.h ; \
if [ "$(findstring _HOST_,$@)" ] ; then \
@ -1780,11 +1782,18 @@ MPC832XEMDS_SLAVE_config: unconfig
if [ "$(findstring _33_,$@)" ] ; then \
echo -n "...33M ..." ; \
echo "#define PCI_33M" >>$(obj)include/config.h ; \
echo "#define CONFIG_PQ_MDS_PIB 1" >>$(obj)include/config.h ; \
fi ; \
if [ "$(findstring _66_,$@)" ] ; then \
echo -n "...66M..." ; \
echo "#define PCI_66M" >>$(obj)include/config.h ; \
fi ;
echo "#define CONFIG_PQ_MDS_PIB 1" >>$(obj)include/config.h ; \
fi ; \
if [ "$(findstring _ATM_,$@)" ] ; then \
echo -n "...ATM..." ; \
echo "#define CONFIG_PQ_MDS_PIB 1" >>$(obj)include/config.h ; \
echo "#define CONFIG_PQ_MDS_PIB_ATM 1" >>$(obj)include/config.h ; \
fi ;
@$(MKCONFIG) -a MPC832XEMDS ppc mpc83xx mpc832xemds freescale
MPC8349EMDS_config: unconfig
@ -1794,20 +1803,21 @@ MPC8349ITX_config \
MPC8349ITX_LOWBOOT_config \
MPC8349ITXGP_config: unconfig
@mkdir -p $(obj)include
@mkdir -p $(obj)board/mpc8349itx
@mkdir -p $(obj)board/freescale/mpc8349itx
@echo "#define CONFIG_$(subst _LOWBOOT,,$(@:_config=))" >> $(obj)include/config.h
@if [ "$(findstring GP,$@)" ] ; then \
echo "TEXT_BASE = 0xFE000000" >$(obj)board/mpc8349itx/config.tmp ; \
echo "TEXT_BASE = 0xFE000000" >$(obj)board/freescale/mpc8349itx/config.tmp ; \
fi
@if [ "$(findstring LOWBOOT,$@)" ] ; then \
echo "TEXT_BASE = 0xFE000000" >$(obj)board/mpc8349itx/config.tmp ; \
echo "TEXT_BASE = 0xFE000000" >$(obj)board/freescale/mpc8349itx/config.tmp ; \
fi
@$(MKCONFIG) -a -n $(@:_config=) MPC8349ITX ppc mpc83xx mpc8349itx freescale
MPC8360EMDS_config \
MPC8360EMDS_HOST_33_config \
MPC8360EMDS_HOST_66_config \
MPC8360EMDS_SLAVE_config: unconfig
MPC8360EMDS_SLAVE_config \
MPC8360EMDS_ATM_config: unconfig
@mkdir -p $(obj)include
@echo "" >$(obj)include/config.h ; \
if [ "$(findstring _HOST_,$@)" ] ; then \
@ -1822,10 +1832,17 @@ MPC8360EMDS_SLAVE_config: unconfig
if [ "$(findstring _33_,$@)" ] ; then \
echo -n "...33M ..." ; \
echo "#define PCI_33M" >>$(obj)include/config.h ; \
echo "#define CONFIG_PQ_MDS_PIB 1" >>$(obj)include/config.h ; \
fi ; \
if [ "$(findstring _66_,$@)" ] ; then \
echo -n "...66M..." ; \
echo "#define PCI_66M" >>$(obj)include/config.h ; \
echo "#define CONFIG_PQ_MDS_PIB 1" >>$(obj)include/config.h ; \
fi ; \
if [ "$(findstring _ATM_,$@)" ] ; then \
echo -n "...ATM..." ; \
echo "#define CONFIG_PQ_MDS_PIB 1" >>$(obj)include/config.h ; \
echo "#define CONFIG_PQ_MDS_PIB_ATM 1" >>$(obj)include/config.h ; \
fi ;
@$(MKCONFIG) -a MPC8360EMDS ppc mpc83xx mpc8360emds freescale
@ -1961,7 +1978,7 @@ TQM8560_config: unconfig
echo "#define CONFIG_TQM$${CTYPE}">>$(obj)include/config.h; \
echo "#define CONFIG_HOSTNAME tqm$${CTYPE}">>$(obj)include/config.h; \
echo "#define CONFIG_BOARDNAME \"TQM$${CTYPE}\"">>$(obj)include/config.h; \
echo "#define CFG_BOOTFILE \"bootfile=/tftpboot/tqm$${CTYPE}/uImage\0\"">>$(obj)include/config.h
echo "#define CFG_BOOTFILE_PATH \"/tftpboot/tqm$${CTYPE}/uImage\"">>$(obj)include/config.h
@$(MKCONFIG) -a TQM85xx ppc mpc85xx tqm85xx
#########################################################################
@ -2334,6 +2351,9 @@ scpu_config: unconfig
pxa255_idp_config: unconfig
@$(MKCONFIG) $(@:_config=) arm pxa pxa255_idp
trizepsiv_config : unconfig
@$(MKCONFIG) $(@:_config=) arm pxa trizepsiv
wepep250_config : unconfig
@$(MKCONFIG) $(@:_config=) arm pxa wepep250

1
board/ads5121/u-boot.lds
View File

@ -51,7 +51,6 @@ SECTIONS
{
cpu/mpc512x/start.o (.text)
*(.text)
*(.fixup)
*(.got1)
. = ALIGN(16);
*(.rodata)

12
board/amcc/katmai/init.S
View File

@ -67,9 +67,9 @@ tlbtabA:
tlbentry(CFG_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xD, AC_R|AC_W|SA_G|SA_I)
tlbentry(CFG_PCIE_BASE, SZ_16K, 0x20000000, 0xC, AC_R|AC_W|SA_G|SA_I)
tlbentry(CFG_PCIE0_CFGBASE, SZ_1K, 0x40000000, 0xC, AC_R|AC_W|SA_G|SA_I)
tlbentry(CFG_PCIE1_CFGBASE, SZ_1K, 0x80000000, 0xC, AC_R|AC_W|SA_G|SA_I)
tlbentry(CFG_PCIE2_CFGBASE, SZ_1K, 0xC0000000, 0xC, AC_R|AC_W|SA_G|SA_I)
tlbentry(CFG_PCIE0_CFGBASE, SZ_16M, 0x40000000, 0xC, AC_R|AC_W|SA_G|SA_I)
tlbentry(CFG_PCIE1_CFGBASE, SZ_16M, 0x80000000, 0xC, AC_R|AC_W|SA_G|SA_I)
tlbentry(CFG_PCIE2_CFGBASE, SZ_16M, 0xC0000000, 0xC, AC_R|AC_W|SA_G|SA_I)
tlbentry(CFG_PCIE0_XCFGBASE, SZ_1K, 0x50000000, 0xC, AC_R|AC_W|SA_G|SA_I)
tlbentry(CFG_PCIE1_XCFGBASE, SZ_1K, 0x90000000, 0xC, AC_R|AC_W|SA_G|SA_I)
tlbentry(CFG_PCIE2_XCFGBASE, SZ_1K, 0xD0000000, 0xC, AC_R|AC_W|SA_G|SA_I)
@ -109,9 +109,9 @@ tlbtabB:
tlbentry(CFG_PCI_MEMBASE, SZ_256M, 0x10000000, 0xC, AC_R|AC_W|SA_G|SA_I)
tlbentry(CFG_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xD, AC_R|AC_W|SA_G|SA_I)
tlbentry(CFG_PCIE0_CFGBASE, SZ_1K, 0x00100000, 0xD, AC_R|AC_W|SA_G|SA_I)
tlbentry(CFG_PCIE1_CFGBASE, SZ_1K, 0x20100000, 0xD, AC_R|AC_W|SA_G|SA_I)
tlbentry(CFG_PCIE2_CFGBASE, SZ_1K, 0x40100000, 0xD, AC_R|AC_W|SA_G|SA_I)
tlbentry(CFG_PCIE0_CFGBASE, SZ_16M, 0x00000000, 0xD, AC_R|AC_W|SA_G|SA_I)
tlbentry(CFG_PCIE1_CFGBASE, SZ_16M, 0x20000000, 0xD, AC_R|AC_W|SA_G|SA_I)
tlbentry(CFG_PCIE2_CFGBASE, SZ_16M, 0x40000000, 0xD, AC_R|AC_W|SA_G|SA_I)
tlbentry(CFG_PCIE0_XCFGBASE, SZ_1K, 0x10000000, 0xD, AC_R|AC_W|SA_G|SA_I)
tlbentry(CFG_PCIE1_XCFGBASE, SZ_1K, 0x30000000, 0xD, AC_R|AC_W|SA_G|SA_I)
tlbentry(CFG_PCIE2_XCFGBASE, SZ_1K, 0x50000000, 0xD, AC_R|AC_W|SA_G|SA_I)

25
board/amcc/katmai/katmai.c
View File

@ -34,6 +34,8 @@
#undef PCIE_ENDPOINT
/* #define PCIE_ENDPOINT 1 */
DECLARE_GLOBAL_DATA_PTR;
int ppc440spe_init_pcie_rootport(int port);
void ppc440spe_setup_pcie(struct pci_controller *hose, int port);
@ -322,8 +324,6 @@ int pci_pre_init(struct pci_controller * hose )
#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
void pci_target_init(struct pci_controller * hose )
{
DECLARE_GLOBAL_DATA_PTR;
/*-------------------------------------------------------------------+
* Disable everything
*-------------------------------------------------------------------*/
@ -392,16 +392,18 @@ int katmai_pcie_card_present(int port)
static struct pci_controller pcie_hose[3] = {{0},{0},{0}};
void pcie_setup_hoses(void)
void pcie_setup_hoses(int busno)
{
struct pci_controller *hose;
int i, bus;
char *env;
unsigned int delay;
/*
* assume we're called after the PCIX hose is initialized, which takes
* bus ID 0 and therefore start numbering PCIe's from 1.
*/
bus = 1;
bus = busno;
for (i = 0; i <= 2; i++) {
/* Check for katmai card presence */
if (!katmai_pcie_card_present(i))
@ -418,8 +420,8 @@ void pcie_setup_hoses(void)
hose = &pcie_hose[i];
hose->first_busno = bus;
hose->last_busno = bus;
bus++;
hose->last_busno = bus;
hose->current_busno = bus;
/* setup mem resource */
pci_set_region(hose->regions + 0,
@ -439,10 +441,21 @@ void pcie_setup_hoses(void)
*/
#else
ppc440spe_setup_pcie_rootpoint(hose, i);
env = getenv ("pciscandelay");
if (env != NULL) {
delay = simple_strtoul (env, NULL, 10);
if (delay > 5)
printf ("Warning, expect noticable delay before PCIe"
"scan due to 'pciscandelay' value!\n");
mdelay (delay * 1000);
}
/*
* Config access can only go down stream
*/
hose->last_busno = pci_hose_scan(hose);
bus = hose->last_busno + 1;
#endif
}
}

17
board/amcc/luan/luan.c
View File

@ -39,8 +39,6 @@ extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
************************************************************************/
int board_early_init_f(void)
{
volatile epld_t *x = (epld_t *) CFG_EPLD_BASE;
mtebc( pb0ap, 0x03800000 ); /* set chip selects */
mtebc( pb0cr, 0xffc58000 ); /* ebc0_b0cr, 4MB at 0xffc00000 CS0 */
mtebc( pb1ap, 0x03800000 );
@ -66,8 +64,6 @@ int board_early_init_f(void)
mtdcr( uic0sr, 0x00000000 ); /* clear all interrupts */
mtdcr( uic0sr, 0xffffffff );
x->ethuart &= ~EPLD2_RESET_ETH_N; /* put Ethernet+PHY in reset */
return 0;
}
@ -79,7 +75,18 @@ int board_early_init_f(void)
int misc_init_r(void)
{
volatile epld_t *x = (epld_t *) CFG_EPLD_BASE;
x->ethuart |= EPLD2_RESET_ETH_N; /* take Ethernet+PHY out of reset */
/* set modes of operation */
x->ethuart |= EPLD2_ETH_MODE_10 | EPLD2_ETH_MODE_100 |
EPLD2_ETH_MODE_1000 | EPLD2_ETH_DUPLEX_MODE;
/* clear ETHERNET_AUTO_NEGO bit to turn on autonegotiation */
x->ethuart &= ~EPLD2_ETH_AUTO_NEGO;
/* put Ethernet+PHY in reset */
x->ethuart &= ~EPLD2_RESET_ETH_N;
udelay(10000);
/* take Ethernet+PHY out of reset */
x->ethuart |= EPLD2_RESET_ETH_N;
return 0;
}

17
board/amcc/sequoia/cmd_sequoia.c
View File

@ -25,6 +25,7 @@
#include <common.h>
#include <command.h>
#include <i2c.h>
#include <asm/io.h>
/*
* There are 2 versions of production Sequoia & Rainier platforms.
@ -39,7 +40,7 @@
* All Sequoias & Rainiers select from two possible EEPROMs in Boot
* Config F. One for 33MHz PCI, one for 66MHz PCI. The following
* values are for the 33MHz PCI configuration. Byte 5 (0 base) is
* the only value affected for a 66MHz PCI and simply needs a +0x10.
* the only value affected for a 33MHz PCI and simply needs a | 0x08.
*/
#define NAND_COMPATIBLE 0x01
@ -56,6 +57,7 @@ static char *config_labels[] = {
"CPU: 416 PLB: 166 OPB: 83 EBC: 55",
"CPU: 500 PLB: 166 OPB: 83 EBC: 55",
"CPU: 533 PLB: 133 OPB: 66 EBC: 66",
"CPU: 667 PLB: 133 OPB: 66 EBC: 66",
"CPU: 667 PLB: 166 OPB: 83 EBC: 55",
NULL
};
@ -96,6 +98,11 @@ static u8 boot_configs[][17] = {
0x87, 0x78, 0x82, 0x52, 0x09, 0x57, 0xa0, 0x30, 0x40,
0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
},
{
(NOR_COMPATIBLE),
0x87, 0x78, 0xa2, 0x56, 0x09, 0x57, 0xa0, 0x30, 0x40,
0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
},
{
(NAND_COMPATIBLE | NOR_COMPATIBLE),
0x87, 0x78, 0xa2, 0x52, 0x09, 0xd7, 0xa0, 0x30, 0x40,
@ -200,8 +207,12 @@ static int do_bootstrap(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
}
/* check CPLD register +5 for PCI 66MHz flag */
if (in8(CFG_BCSR_BASE + 5) & 0x01)
buf[5] += 0x10;
if ((in_8((void *)(CFG_BCSR_BASE + 5)) & CFG_BCSR5_PCI66EN) == 0)
/*
* PLB-to-PCI divisor = 3 for 33MHz sync PCI
* instead of 2 for 66MHz systems
*/
buf[5] |= 0x08;
if (i2c_write(I2C_EEPROM_ADDR, 0, 1, buf, 16) != 0)
printf("Error writing to EEPROM at address 0x%x\n", I2C_EEPROM_ADDR);

3
board/amcc/sequoia/init.S
View File

@ -126,6 +126,9 @@ tlbtab:
/* TLB-entry for peripherals */
tlbentry( 0xEF000000, SZ_16M, 0xEF000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I)
/* TLB-entry PCI IO Space - from sr@denx.de */
tlbentry(0xE8000000, SZ_64K, 0xE8000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I)
tlbtab_end
#if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)

7
board/amcc/sequoia/sequoia.c
View File

@ -1,5 +1,5 @@
/*
* (C) Copyright 2006
* (C) Copyright 2006-2007
* Stefan Roese, DENX Software Engineering, sr@denx.de.
*
* (C) Copyright 2006
@ -24,6 +24,7 @@
#include <common.h>
#include <asm/processor.h>
#include <asm/io.h>
#include <ppc440.h>
DECLARE_GLOBAL_DATA_PTR;
@ -362,8 +363,8 @@ int checkboard(void)
printf("Board: Rainier - AMCC PPC440GRx Evaluation Board");
#endif
rev = in8(CFG_BCSR_BASE + 0);
val = in8(CFG_BCSR_BASE + 5) & 0x01;
rev = in_8((void *)(CFG_BCSR_BASE + 0));
val = in_8((void *)(CFG_BCSR_BASE + 5)) & CFG_BCSR5_PCI66EN;
printf(", Rev. %X, PCI=%d MHz", rev, val ? 66 : 33);
if (s != NULL) {

4
board/amcc/taishan/taishan.c
View File

@ -32,6 +32,8 @@
void show_reset_reg(void);
#endif
DECLARE_GLOBAL_DATA_PTR;
int lcd_init(void);
int board_early_init_f (void)
@ -266,8 +268,6 @@ int pci_pre_init(struct pci_controller * hose )
#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
void pci_target_init(struct pci_controller * hose )
{
DECLARE_GLOBAL_DATA_PTR;
/*--------------------------------------------------------------------------+
* Disable everything
*--------------------------------------------------------------------------*/

7
board/amcc/yosemite/yosemite.c
View File

@ -1,4 +1,6 @@
/*
* (C) Copyright 2006-2007
* Stefan Roese, DENX Software Engineering, sr@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
@ -22,6 +24,7 @@
#include <common.h>
#include <ppc4xx.h>
#include <asm/processor.h>
#include <asm/io.h>
#include <spd_sdram.h>
DECLARE_GLOBAL_DATA_PTR;
@ -181,8 +184,8 @@ int checkboard(void)
printf("Board: Yellowstone - AMCC PPC440GR Evaluation Board");
#endif
rev = *(u8 *)(CFG_CPLD + 0);
val = *(u8 *)(CFG_CPLD + 5) & 0x01;
rev = in_8((void *)(CFG_BCSR_BASE + 0));
val = in_8((void *)(CFG_BCSR_BASE + 5)) & CFG_BCSR5_PCI66EN;
printf(", Rev. %X, PCI=%d MHz", rev, val ? 66 : 33);
if (s != NULL) {

12
board/amcc/yucca/init.S
View File

@ -70,9 +70,9 @@ tlbtabA:
tlbentry(CFG_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xD, AC_R|AC_W|SA_G|SA_I)
tlbentry(CFG_PCIE_BASE, SZ_16K, 0x20000000, 0xC, AC_R|AC_W|SA_G|SA_I)
tlbentry(CFG_PCIE0_CFGBASE, SZ_1K, 0x40000000, 0xC, AC_R|AC_W|SA_G|SA_I)
tlbentry(CFG_PCIE1_CFGBASE, SZ_1K, 0x80000000, 0xC, AC_R|AC_W|SA_G|SA_I)
tlbentry(CFG_PCIE2_CFGBASE, SZ_1K, 0xC0000000, 0xC, AC_R|AC_W|SA_G|SA_I)
tlbentry(CFG_PCIE0_CFGBASE, SZ_16M, 0x40000000, 0xC, AC_R|AC_W|SA_G|SA_I)
tlbentry(CFG_PCIE1_CFGBASE, SZ_16M, 0x80000000, 0xC, AC_R|AC_W|SA_G|SA_I)
tlbentry(CFG_PCIE2_CFGBASE, SZ_16M, 0xC0000000, 0xC, AC_R|AC_W|SA_G|SA_I)
tlbentry(CFG_PCIE0_XCFGBASE, SZ_1K, 0x50000000, 0xC, AC_R|AC_W|SA_G|SA_I)
tlbentry(CFG_PCIE1_XCFGBASE, SZ_1K, 0x90000000, 0xC, AC_R|AC_W|SA_G|SA_I)
tlbentry(CFG_PCIE2_XCFGBASE, SZ_1K, 0xD0000000, 0xC, AC_R|AC_W|SA_G|SA_I)
@ -112,9 +112,9 @@ tlbtabB:
tlbentry(CFG_PCI_MEMBASE, SZ_256M, 0x10000000, 0xC, AC_R|AC_W|SA_G|SA_I)
tlbentry(CFG_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xD, AC_R|AC_W|SA_G|SA_I)
tlbentry(CFG_PCIE0_CFGBASE, SZ_1K, 0x00100000, 0xD, AC_R|AC_W|SA_G|SA_I)
tlbentry(CFG_PCIE1_CFGBASE, SZ_1K, 0x20100000, 0xD, AC_R|AC_W|SA_G|SA_I)
tlbentry(CFG_PCIE2_CFGBASE, SZ_1K, 0x40100000, 0xD, AC_R|AC_W|SA_G|SA_I)
tlbentry(CFG_PCIE0_CFGBASE, SZ_16M, 0x00000000, 0xD, AC_R|AC_W|SA_G|SA_I)
tlbentry(CFG_PCIE1_CFGBASE, SZ_16M, 0x20000000, 0xD, AC_R|AC_W|SA_G|SA_I)
tlbentry(CFG_PCIE2_CFGBASE, SZ_16M, 0x40000000, 0xD, AC_R|AC_W|SA_G|SA_I)
tlbentry(CFG_PCIE0_XCFGBASE, SZ_1K, 0x10000000, 0xD, AC_R|AC_W|SA_G|SA_I)
tlbentry(CFG_PCIE1_XCFGBASE, SZ_1K, 0x30000000, 0xD, AC_R|AC_W|SA_G|SA_I)
tlbentry(CFG_PCIE2_XCFGBASE, SZ_1K, 0x50000000, 0xD, AC_R|AC_W|SA_G|SA_I)

25
board/amcc/yucca/yucca.c
View File

@ -34,6 +34,8 @@
#include "yucca.h"
#include "../cpu/ppc4xx/440spe_pcie.h"
DECLARE_GLOBAL_DATA_PTR;
#undef PCIE_ENDPOINT
/* #define PCIE_ENDPOINT 1 */
@ -668,8 +670,6 @@ int pci_pre_init(struct pci_controller * hose )
#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
void pci_target_init(struct pci_controller * hose )
{
DECLARE_GLOBAL_DATA_PTR;
/*-------------------------------------------------------------------+
* Disable everything
*-------------------------------------------------------------------*/
@ -846,16 +846,18 @@ void yucca_setup_pcie_fpga_endpoint(int port)
static struct pci_controller pcie_hose[3] = {{0},{0},{0}};
void pcie_setup_hoses(void)
void pcie_setup_hoses(int busno)
{
struct pci_controller *hose;
int i, bus;
char *env;
unsigned int delay;
/*
* assume we're called after the PCIX hose is initialized, which takes
* bus ID 0 and therefore start numbering PCIe's from 1.
*/
bus = 1;
bus = busno;
for (i = 0; i <= 2; i++) {
/* Check for yucca card presence */
if (!yucca_pcie_card_present(i))
@ -874,8 +876,8 @@ void pcie_setup_hoses(void)
hose = &pcie_hose[i];
hose->first_busno = bus;
hose->last_busno = bus;
bus++;
hose->last_busno = bus;
hose->current_busno = bus;
/* setup mem resource */
pci_set_region(hose->regions + 0,
@ -895,10 +897,21 @@ void pcie_setup_hoses(void)
*/
#else
ppc440spe_setup_pcie_rootpoint(hose, i);
env = getenv ("pciscandelay");
if (env != NULL) {
delay = simple_strtoul (env, NULL, 10);
if (delay > 5)
printf ("Warning, expect noticable delay before PCIe"
"scan due to 'pciscandelay' value!\n");
mdelay (delay * 1000);
}
/*
* Config access can only go down stream
*/
hose->last_busno = pci_hose_scan(hose);
bus = hose->last_busno + 1;
#endif
}
}

2
board/at91rm9200dk/led.c
View File

@ -66,7 +66,7 @@ void red_LED_off(void)
}
void LED_init (void)
void coloured_LED_init (void)
{
AT91PS_PIO PIOB = AT91C_BASE_PIOB;
AT91PS_PMC PMC = AT91C_BASE_PMC;

4
board/atmel/atstk1000/flash.c
View File

@ -55,10 +55,6 @@ unsigned long flash_init(void)
unsigned long addr;
unsigned int i;
gd->bd->bi_flashstart = CFG_FLASH_BASE;
gd->bd->bi_flashsize = CFG_FLASH_SIZE;
gd->bd->bi_flashoffset = _edata - _text;
flash_info[0].size = CFG_FLASH_SIZE;
flash_info[0].sector_count = 135;

3
board/bf533-ezkit/bf533-ezkit.c
View File

@ -30,6 +30,8 @@
#include "psd4256.h"
#endif
DECLARE_GLOBAL_DATA_PTR;
int checkboard(void)
{
#if (BFIN_CPU == ADSP_BF531)
@ -46,7 +48,6 @@ int checkboard(void)
long int initdram(int board_type)
{
DECLARE_GLOBAL_DATA_PTR;
#ifdef DEBUG
int brate;
char *tmp = getenv("baudrate");

3
board/bf533-stamp/bf533-stamp.c
View File

@ -30,6 +30,8 @@
#include <asm/io.h>
#include "bf533-stamp.h"
DECLARE_GLOBAL_DATA_PTR;
#define STATUS_LED_OFF 0
#define STATUS_LED_ON 1
@ -55,7 +57,6 @@ int checkboard(void)
long int initdram(int board_type)
{
DECLARE_GLOBAL_DATA_PTR;
#ifdef DEBUG
printf("SDRAM attributes:\n");
printf

3
board/bf537-stamp/bf537-stamp.c
View File

@ -32,6 +32,8 @@
#include <asm/io.h>
#include "ether_bf537.h"
DECLARE_GLOBAL_DATA_PTR;
#define POST_WORD_ADDR 0xFF903FFC
/*
@ -132,7 +134,6 @@ void cf_outsw(unsigned short *addr, unsigned short *sect_buf, int words)
long int initdram(int board_type)
{
DECLARE_GLOBAL_DATA_PTR;
#ifdef DEBUG
int brate;
char *tmp = getenv("baudrate");

3
board/bf561-ezkit/bf561-ezkit.c
View File

@ -29,6 +29,8 @@
#include <common.h>
#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR;
int checkboard(void)
{
printf("CPU: ADSP BF561\n");
@ -39,7 +41,6 @@ int checkboard(void)
long int initdram(int board_type)
{
DECLARE_GLOBAL_DATA_PTR;
#ifdef DEBUG
int brate;
char *tmp = getenv("baudrate");

1
board/cm5200/cm5200.c
View File

@ -397,6 +397,7 @@ int misc_init_r(void)
"operational\n");
/* set the hostname appropriate to the module we're running on */
hostname[0] = 0x00;
compose_hostname(hw_id, hostname);
setenv("hostname", hostname);

2
board/cm5200/cmd_cm5200.c
View File

@ -27,7 +27,7 @@
#include <i2c.h>
#include <usb.h>
#ifdef CONFIG_CMD_BSB
#ifdef CONFIG_CMD_BSP
int do_i2c(char *argv[])
{

6
board/davinci/dv-evm/dv_board.c
View File

@ -31,6 +31,8 @@
#define MACH_TYPE_DAVINCI_EVM 901
DECLARE_GLOBAL_DATA_PTR;
extern void i2c_init(int speed, int slaveaddr);
extern void timer_init(void);
extern int eth_hw_init(void);
@ -115,8 +117,6 @@ void dsp_on(void)
int board_init(void)
{
DECLARE_GLOBAL_DATA_PTR;
/* arch number of the board */
gd->bd->bi_arch_number = MACH_TYPE_DAVINCI_EVM;
@ -202,8 +202,6 @@ int misc_init_r (void)
int dram_init(void)
{
DECLARE_GLOBAL_DATA_PTR;
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;

6
board/davinci/schmoogie/dv_board.c
View File

@ -31,6 +31,8 @@
#define MACH_TYPE_SCHMOOGIE 1255
DECLARE_GLOBAL_DATA_PTR;
extern void i2c_init(int speed, int slaveaddr);
extern void timer_init(void);
extern int eth_hw_init(void);
@ -115,8 +117,6 @@ void dsp_on(void)
int board_init(void)
{
DECLARE_GLOBAL_DATA_PTR;
/* arch number of the board */
gd->bd->bi_arch_number = MACH_TYPE_SCHMOOGIE;
@ -244,8 +244,6 @@ int misc_init_r (void)
int dram_init(void)
{
DECLARE_GLOBAL_DATA_PTR;
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;

6
board/davinci/sonata/dv_board.c
View File

@ -31,6 +31,8 @@
#define MACH_TYPE_SONATA 1254
DECLARE_GLOBAL_DATA_PTR;
extern void i2c_init(int speed, int slaveaddr);
extern void timer_init(void);
extern int eth_hw_init(void);
@ -115,8 +117,6 @@ void dsp_on(void)
int board_init(void)
{
DECLARE_GLOBAL_DATA_PTR;
/* arch number of the board */
gd->bd->bi_arch_number = MACH_TYPE_SONATA;
@ -199,8 +199,6 @@ int misc_init_r (void)
int dram_init(void)
{
DECLARE_GLOBAL_DATA_PTR;
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;

1
board/fads/fads.h
View File

@ -229,6 +229,7 @@
#define CFG_ENV_SECT_SIZE 0x40000 /* see README - env sector total size */
#define CFG_ENV_OFFSET CFG_ENV_SECT_SIZE
#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment */
#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */
#define CFG_DIRECT_FLASH_TFTP

3
board/freescale/common/pixis.c
View File

@ -25,10 +25,9 @@
#include <common.h>
#include <command.h>
#include <watchdog.h>
#include <asm/cache.h>
#ifdef CONFIG_FSL_PIXIS
#include <asm/cache.h>
#include "pixis.h"

22
board/freescale/common/pq-mds-pib.c
View File

@ -79,19 +79,19 @@ int pib_init(void)
printf("QOC3 ATM card on PMC0\n");
#elif defined(CONFIG_MPC832XEMDS)
val = 0;
i2c_write(0x26, 0x7, 1, &val, 1);
val = 0xf7;
i2c_write(0x26, 0x3, 1, &val, 1);
val8 = 0;
i2c_write(0x26, 0x7, 1, &val8, 1);
val8 = 0xf7;
i2c_write(0x26, 0x3, 1, &val8, 1);
val = 0;
i2c_write(0x21, 0x6, 1, &val, 1);
i2c_write(0x21, 0x7, 1, &val, 1);
val8 = 0;
i2c_write(0x21, 0x6, 1, &val8, 1);
i2c_write(0x21, 0x7, 1, &val8, 1);
val = 0xdf;
i2c_write(0x21, 0x2, 1, &val, 1);
val = 0xef;
i2c_write(0x21, 0x3, 1, &val, 1);
val8 = 0xdf;
i2c_write(0x21, 0x2, 1, &val8, 1);
val8 = 0xef;
i2c_write(0x21, 0x3, 1, &val8, 1);
eieio();

2
board/freescale/m5235evb/mii.c
View File

@ -204,7 +204,7 @@ int mii_discover_phy(struct eth_device *dev)
}
#endif /* CFG_DISCOVER_PHY */
int mii_init(void) __attribute__((weak,alias("__mii_init")));
void mii_init(void) __attribute__((weak,alias("__mii_init")));
void __mii_init(void)
{

2
board/freescale/m5329evb/mii.c
View File

@ -203,7 +203,7 @@ int mii_discover_phy(struct eth_device *dev)
}
#endif /* CFG_DISCOVER_PHY */
int mii_init(void) __attribute__((weak,alias("__mii_init")));
void mii_init(void) __attribute__((weak,alias("__mii_init")));
void __mii_init(void)
{

2
board/freescale/m54455evb/mii.c
View File

@ -221,7 +221,7 @@ int mii_discover_phy(struct eth_device *dev)
}
#endif /* CFG_DISCOVER_PHY */
int mii_init(void) __attribute__((weak,alias("__mii_init")));
void mii_init(void) __attribute__((weak,alias("__mii_init")));
void __mii_init(void)
{

3
board/freescale/mpc8313erdb/sdram.c
View File

@ -33,10 +33,11 @@
#include <asm/processor.h>
DECLARE_GLOBAL_DATA_PTR;
#ifndef CFG_8313ERDB_BROKEN_PMC
static void resume_from_sleep(void)
{
DECLARE_GLOBAL_DATA_PTR;
u32 magic = *(u32 *)0;
typedef void (*func_t)(void);

7
board/icecube/icecube.c
View File

@ -28,10 +28,7 @@
#include <mpc5xxx.h>
#include <pci.h>
#include <asm/processor.h>
#if defined(CONFIG_OF_FLAT_TREE)
#include <ft_build.h>
#endif
#include <libfdt.h>
#if defined(CONFIG_LITE5200B)
#include "mt46v32m16.h"
@ -386,7 +383,7 @@ void ide_set_reset (int idereset)
}
#endif
#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP)
#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
void
ft_board_setup(void *blob, bd_t *bd)
{

8
board/jupiter/jupiter.c
View File

@ -28,11 +28,7 @@
#include <mpc5xxx.h>
#include <pci.h>
#include <asm/processor.h>
#if defined(CONFIG_OF_FLAT_TREE)
#include <ft_build.h>
#endif
#include <libfdt.h>
#define SDRAM_DDR 0
#if 1
@ -308,7 +304,7 @@ void ide_set_reset (int idereset)
}
#endif
#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP)
#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
void
ft_board_setup(void *blob, bd_t *bd)
{

7
board/lpc2292sodimm/lpc2292sodimm.c
View File

@ -28,8 +28,7 @@
#include <common.h>
#include <clps7111.h>
/* ------------------------------------------------------------------------- */
DECLARE_GLOBAL_DATA_PTR;
/*
* Miscelaneous platform dependent initialisations
@ -37,8 +36,6 @@
int board_init (void)
{
DECLARE_GLOBAL_DATA_PTR;
/* Activate LED flasher */
IO_LEDFLSH = 0x40;
@ -53,8 +50,6 @@ int board_init (void)
int dram_init (void)
{
DECLARE_GLOBAL_DATA_PTR;
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;

2
board/m5271evb/mii.c
View File

@ -200,7 +200,7 @@ int mii_discover_phy(struct eth_device *dev)
}
#endif /* CFG_DISCOVER_PHY */
int mii_init(void) __attribute__((weak,alias("__mii_init")));
void mii_init(void) __attribute__((weak,alias("__mii_init")));
void __mii_init(void)
{

2
board/m5272c3/mii.c
View File

@ -200,7 +200,7 @@ int mii_discover_phy(struct eth_device *dev)
}
#endif /* CFG_DISCOVER_PHY */
int mii_init(void) __attribute__((weak,alias("__mii_init")));
void mii_init(void) __attribute__((weak,alias("__mii_init")));
void __mii_init(void)
{

2
board/m5282evb/mii.c
View File

@ -201,7 +201,7 @@ int mii_discover_phy(struct eth_device *dev)
}
#endif /* CFG_DISCOVER_PHY */
int mii_init(void) __attribute__((weak,alias("__mii_init")));
void mii_init(void) __attribute__((weak,alias("__mii_init")));
void __mii_init(void)
{

8
board/motionpro/motionpro.c
View File

@ -29,9 +29,7 @@
#include <common.h>
#include <mpc5xxx.h>
#include <miiphy.h>
#if defined(CONFIG_OF_FLAT_TREE)
#include <ft_build.h>
#endif
#include <libfdt.h>
#if defined(CONFIG_STATUS_LED)
#include <status_led.h>
@ -196,12 +194,12 @@ int checkboard(void)
}
#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP)
#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
void ft_board_setup(void *blob, bd_t *bd)
{
ft_cpu_setup(blob, bd);
}
#endif /* defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP) */
#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
#if defined(CONFIG_STATUS_LED)

4
board/mpc7448hpc2/mpc7448hpc2.c
View File

@ -38,6 +38,8 @@ extern void ft_cpu_setup (void *blob, bd_t *bd);
#undef DEBUG
DECLARE_GLOBAL_DATA_PTR;
extern void flush_data_cache (void);
extern void invalidate_l1_instruction_cache (void);
extern void tsi108_init_f (void);
@ -46,8 +48,6 @@ int display_mem_map (void);
void after_reloc (ulong dest_addr)
{
DECLARE_GLOBAL_DATA_PTR;
/*
* Jump to the main U-Boot board init code
*/

4
board/mpc7448hpc2/tsi108_init.c
View File

@ -33,6 +33,8 @@
#include <asm/processor.h>
#include <tsi108.h>
DECLARE_GLOBAL_DATA_PTR;
extern void mpicInit (int verbose);
/*
@ -141,7 +143,6 @@ unsigned long get_board_bus_clk (void)
int board_early_init_f (void)
{
DECLARE_GLOBAL_DATA_PTR;
ulong i;
gd->mem_clk = 0;
@ -583,7 +584,6 @@ unsigned long get_l2cr (void)
int misc_init_r (void)
{
DECLARE_GLOBAL_DATA_PTR;
#ifdef CFG_CLK_SPREAD /* Initialize Spread-Spectrum Clock generation */
ulong i;

4
board/mpl/vcma9/cmd_vcma9.c
View File

@ -40,6 +40,8 @@ static uchar cs8900_chksum(ushort data)
#endif
DECLARE_GLOBAL_DATA_PTR;
extern void print_vcma9_info(void);
extern int vcma9_cantest(int);
extern int vcma9_nandtest(void);
@ -53,8 +55,6 @@ extern int do_mplcommon(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
int do_vcma9(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
DECLARE_GLOBAL_DATA_PTR;
if (strcmp(argv[1], "info") == 0)
{
print_vcma9_info();

4
board/mpl/vcma9/vcma9.c
View File

@ -288,7 +288,7 @@ int dram_init(void)
int checkboard(void)
{
unsigned char s[50];
char s[50];
int i;
backup_t *b = (backup_t *) s;
@ -337,7 +337,7 @@ int overwrite_console(void)
************************************************************************/
void print_vcma9_info(void)
{
unsigned char s[50];
char s[50];
int i;
if ((i = getenv_r("serial#", s, 32)) < 0) {

5
board/sbc2410x/sbc2410x.c
View File

@ -35,7 +35,7 @@
#include <linux/mtd/nand.h>
#endif
/* ------------------------------------------------------------------------- */
DECLARE_GLOBAL_DATA_PTR;
#define FCLK_SPEED 1
@ -74,7 +74,6 @@ static inline void delay (unsigned long loops)
int board_init (void)
{
DECLARE_GLOBAL_DATA_PTR;
S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER();
S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
@ -128,8 +127,6 @@ int board_init (void)
int dram_init (void)
{
DECLARE_GLOBAL_DATA_PTR;
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;

7
board/siemens/SMN42/smn42.c
View File

@ -31,8 +31,7 @@
#include <common.h>
#include <clps7111.h>
/* ------------------------------------------------------------------------- */
DECLARE_GLOBAL_DATA_PTR;
/*
* Miscellaneous platform dependent initialisations
@ -40,8 +39,6 @@
int board_init (void)
{
DECLARE_GLOBAL_DATA_PTR;
/* arch number MACH_TYPE_ARMADILLO - not official*/
gd->bd->bi_arch_number = 83;
@ -53,8 +50,6 @@ int board_init (void)
int dram_init (void)
{
DECLARE_GLOBAL_DATA_PTR;
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;

11
board/stxssa/stxssa.c
View File

@ -378,9 +378,14 @@ static struct pci_config_table pci_stxgp3_config_table[] = {
#endif
static struct pci_controller hose = {
static struct pci_controller hose[] = {
#ifndef CONFIG_PCI_PNP
config_table: pci_stxgp3_config_table,
{ config_table: pci_stxgp3_config_table,},
#else
{},
#endif
#ifdef CONFIG_MPC85XX_PCI2
{},
#endif
};
@ -393,6 +398,6 @@ pci_init_board(void)
#ifdef CONFIG_PCI
extern void pci_mpc85xx_init(struct pci_controller *hose);
pci_mpc85xx_init(&hose);
pci_mpc85xx_init(hose);
#endif /* CONFIG_PCI */
}

1
board/stxssa/u-boot.lds
View File

@ -145,6 +145,7 @@ SECTIONS
. = ALIGN(256);
__init_end = .;
. = .;
__bss_start = .;
.bss :
{

13
board/tqm5200/tqm5200.c
View File

@ -31,10 +31,7 @@
#include <mpc5xxx.h>
#include <pci.h>
#include <asm/processor.h>
#if defined(CONFIG_OF_FLAT_TREE)
#include <ft_build.h>
#endif
#include <libfdt.h>
#ifdef CONFIG_VIDEO_SM501
#include <sm501.h>
@ -46,6 +43,8 @@
#include "mt48lc16m16a2-75.h"
#endif
DECLARE_GLOBAL_DATA_PTR;
#ifdef CONFIG_PS2MULT
void ps2mult_early_init(void);
#endif
@ -480,8 +479,6 @@ int silent_boot (void)
int board_early_init_f (void)
{
DECLARE_GLOBAL_DATA_PTR;
if (silent_boot())
gd->flags |= GD_FLG_SILENT;
@ -780,9 +777,9 @@ int board_get_height (void)
#endif /* CONFIG_VIDEO_SM501 */
#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP)
#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
void ft_board_setup(void *blob, bd_t *bd)
{
ft_cpu_setup(blob, bd);
}
#endif /* defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP) */
#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */

51
board/trizepsiv/Makefile Normal file
View File

@ -0,0 +1,51 @@
#
# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a
COBJS := conxs.o eeprom.o
SOBJS := lowlevel_init.o pxavoltage.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
clean:
rm -f $(SOBJS) $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak .depend
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################

3
board/trizepsiv/config.mk Normal file
View File

@ -0,0 +1,3 @@
TEXT_BASE =0xa1f00000
# 0xa1700000
#TEXT_BASE = 0

146
board/trizepsiv/conxs.c Normal file
View File

@ -0,0 +1,146 @@
/*
* (C) Copyright 2007
* Stefano Babic, DENX Gmbh, sbabic@denx.de
*
* (C) Copyright 2004
* Robert Whaley, Applied Data Systems, Inc. rwhaley@applieddata.net
*
* (C) Copyright 2002
* Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
*
* (C) Copyright 2002
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
* Marius Groeger <mgroeger@sysgo.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/arch/pxa-regs.h>
DECLARE_GLOBAL_DATA_PTR;
#define RH_A_PSM (1 << 8) /* power switching mode */
#define RH_A_NPS (1 << 9) /* no power switching */
extern struct serial_device serial_ffuart_device;
extern struct serial_device serial_btuart_device;
extern struct serial_device serial_stuart_device;
/* ------------------------------------------------------------------------- */
/*
* Miscelaneous platform dependent initialisations
*/
void usb_board_init(void)
{
UHCHR = (UHCHR | UHCHR_PCPL | UHCHR_PSPL) &
~(UHCHR_SSEP0 | UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSE);
UHCHR |= UHCHR_FSBIR;
while (UHCHR & UHCHR_FSBIR);
UHCHR &= ~UHCHR_SSE;
UHCHIE = (UHCHIE_UPRIE | UHCHIE_RWIE);
/* Clear any OTG Pin Hold */
if (PSSR & PSSR_OTGPH)
PSSR |= PSSR_OTGPH;
UHCRHDA &= ~(RH_A_NPS);
UHCRHDA |= RH_A_PSM;
/* Set port power control mask bits, only 3 ports. */
UHCRHDB |= (0x7<<17);
}
void usb_board_init_fail(void)
{
return;
}
void usb_board_stop(void)
{
UHCHR |= UHCHR_FHR;
udelay(11);
UHCHR &= ~UHCHR_FHR;
UHCCOMS |= 1;
udelay(10);
CKEN &= ~CKEN10_USBHOST;
puts("Called USB STOP\n");
return;
}
int board_init (void)
{
/* memory and cpu-speed are setup before relocation */
/* so we do _nothing_ here */
/* arch number of ConXS Board */
gd->bd->bi_arch_number = 776;
/* adress of boot parameters */
gd->bd->bi_boot_params = 0xa000003c;
return 0;
}
int board_late_init(void)
{
#if defined(CONFIG_SERIAL_MULTI)
char *console=getenv("boot_console");
if ((strcmp(console,"serial_btuart") == 0) ||
(strcmp(console,"serial_stuart") == 0) ||
(strcmp(console,"serial_ffuart") == 0)) {
setenv("stdout",console);
setenv("stdin", console);
setenv("stderr",console);
} else {
setenv("stdout", "serial");
setenv("stdin", "serial");
setenv("stderr", "serial");
}
#endif
return 0;
}
struct serial_device *default_serial_console (void)
{
return &serial_ffuart_device;
}
int dram_init (void)
{
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE;
gd->bd->bi_dram[3].start = PHYS_SDRAM_4;
gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE;
return 0;
}

85
board/trizepsiv/eeprom.c Normal file
View File

@ -0,0 +1,85 @@
/*
* (C) Copyright 2007
* Stefano Babic, DENX Software Engineering, sbabic@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <command.h>
static unsigned char srom[128];
extern u16 read_srom_word(int);
extern void write_srom_word(int offset, u16 val);
static int do_read_dm9000_eeprom ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) {
int i;
for (i=0; i < 0x40; i++) {
if (!(i % 0x10))
printf("\n%08lx:", i);
printf(" %04x", read_srom_word(i));
}
printf ("\n");
return (0);
}
static int do_write_dm9000_eeprom ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) {
int offset,value;
if (argc < 4) {
printf ("Usage:\n%s\n", cmdtp->usage);
return 1;
}
offset=simple_strtoul(argv[2],NULL,16);
value=simple_strtoul(argv[3],NULL,16);
if (offset > 0x40) {
printf("Wrong offset : 0x%x\n",offset);
printf ("Usage:\n%s\n", cmdtp->usage);
return 1;
}
write_srom_word(offset, value);
return (0);
}
int do_dm9000_eeprom ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) {
if (argc < 2) {
printf ("Usage:\n%s\n", cmdtp->usage);
return 1;
}
if (strcmp (argv[1],"read") == 0) {
return (do_read_dm9000_eeprom(cmdtp,flag,argc,argv));
} else if (strcmp (argv[1],"write") == 0) {
return (do_write_dm9000_eeprom(cmdtp,flag,argc,argv));
} else {
printf ("Usage:\n%s\n", cmdtp->usage);
return 1;
}
}
U_BOOT_CMD(
dm9000ee,4,1,do_dm9000_eeprom,
"dm9000ee- Read/Write eeprom connected to Ethernet Controller\n",
"\ndm9000ee write <word offset> <value> \n"
"\tdm9000ee read \n"
"\tword:\t\t00-02 : MAC Address\n"
"\t\t\t03-07 : DM9000 Configuration\n"
"\t\t\t08-63 : User data\n");

503
board/trizepsiv/lowlevel_init.S Normal file
View File

@ -0,0 +1,503 @@
/*
* This was originally from the Lubbock u-boot port.
*
* Most of this taken from Redboot hal_platform_setup.h with cleanup
*
* NOTE: I haven't clean this up considerably, just enough to get it
* running. See hal_platform_setup.h for the source. See
* board/cradle/lowlevel_init.S for another PXA250 setup that is
* much cleaner.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <config.h>
#include <version.h>
#include <asm/arch/pxa-regs.h>
/* wait for coprocessor write complete */
.macro CPWAIT reg
mrc p15,0,\reg,c2,c0,0
mov \reg,\reg
sub pc,pc,#4
.endm
/*
* Memory setup
*/
.globl lowlevel_init
lowlevel_init:
/* Set up GPIO pins first ----------------------------------------- */
ldr r0, =GPSR0
ldr r1, =CFG_GPSR0_VAL
str r1, [r0]
ldr r0, =GPSR1
ldr r1, =CFG_GPSR1_VAL
str r1, [r0]
ldr r0, =GPSR2
ldr r1, =CFG_GPSR2_VAL
str r1, [r0]
ldr r0, =GPSR3
ldr r1, =CFG_GPSR3_VAL
str r1, [r0]
ldr r0, =GPCR0
ldr r1, =CFG_GPCR0_VAL
str r1, [r0]
ldr r0, =GPCR1
ldr r1, =CFG_GPCR1_VAL
str r1, [r0]
ldr r0, =GPCR2
ldr r1, =CFG_GPCR2_VAL
str r1, [r0]
ldr r0, =GPCR3
ldr r1, =CFG_GPCR3_VAL
str r1, [r0]
ldr r0, =GRER0
ldr r1, =CFG_GRER0_VAL
str r1, [r0]
ldr r0, =GRER1
ldr r1, =CFG_GRER1_VAL
str r1, [r0]
ldr r0, =GRER2
ldr r1, =CFG_GRER2_VAL
str r1, [r0]
ldr r0, =GRER3
ldr r1, =CFG_GRER3_VAL
str r1, [r0]
ldr r0, =GFER0
ldr r1, =CFG_GFER0_VAL
str r1, [r0]
ldr r0, =GFER1
ldr r1, =CFG_GFER1_VAL
str r1, [r0]
ldr r0, =GFER2
ldr r1, =CFG_GFER2_VAL
str r1, [r0]
ldr r0, =GFER3
ldr r1, =CFG_GFER3_VAL
str r1, [r0]
ldr r0, =GPDR0
ldr r1, =CFG_GPDR0_VAL
str r1, [r0]
ldr r0, =GPDR1
ldr r1, =CFG_GPDR1_VAL
str r1, [r0]
ldr r0, =GPDR2
ldr r1, =CFG_GPDR2_VAL
str r1, [r0]
ldr r0, =GPDR3
ldr r1, =CFG_GPDR3_VAL
str r1, [r0]
ldr r0, =GAFR0_L
ldr r1, =CFG_GAFR0_L_VAL
str r1, [r0]
ldr r0, =GAFR0_U
ldr r1, =CFG_GAFR0_U_VAL
str r1, [r0]
ldr r0, =GAFR1_L
ldr r1, =CFG_GAFR1_L_VAL
str r1, [r0]
ldr r0, =GAFR1_U
ldr r1, =CFG_GAFR1_U_VAL
str r1, [r0]
ldr r0, =GAFR2_L
ldr r1, =CFG_GAFR2_L_VAL
str r1, [r0]
ldr r0, =GAFR2_U
ldr r1, =CFG_GAFR2_U_VAL
str r1, [r0]
ldr r0, =GAFR3_L
ldr r1, =CFG_GAFR3_L_VAL
str r1, [r0]
ldr r0, =GAFR3_U
ldr r1, =CFG_GAFR3_U_VAL
str r1, [r0]
ldr r0, =PSSR /* enable GPIO pins */
ldr r1, =CFG_PSSR_VAL
str r1, [r0]
/* ---------------------------------------------------------------- */
/* Enable memory interface */
/* */
/* The sequence below is based on the recommended init steps */
/* detailed in the Intel PXA250 Operating Systems Developers Guide, */
/* Chapter 10. */
/* ---------------------------------------------------------------- */
/* ---------------------------------------------------------------- */
/* Step 1: Wait for at least 200 microsedonds to allow internal */
/* clocks to settle. Only necessary after hard reset... */
/* FIXME: can be optimized later */
/* ---------------------------------------------------------------- */
ldr r3, =OSCR /* reset the OS Timer Count to zero */
mov r2, #0
str r2, [r3]
ldr r4, =0x300 /* really 0x2E1 is about 200usec, */
/* so 0x300 should be plenty */
1:
ldr r2, [r3]
cmp r4, r2
bgt 1b
mem_init:
ldr r1, =MEMC_BASE /* get memory controller base addr. */
/* ---------------------------------------------------------------- */
/* Step 2a: Initialize Asynchronous static memory controller */
/* ---------------------------------------------------------------- */
/* MSC registers: timing, bus width, mem type */
/* MSC0: nCS(0,1) */
ldr r2, =CFG_MSC0_VAL
str r2, [r1, #MSC0_OFFSET]
ldr r2, [r1, #MSC0_OFFSET] /* read back to ensure */
/* that data latches */
/* MSC1: nCS(2,3) */
ldr r2, =CFG_MSC1_VAL
str r2, [r1, #MSC1_OFFSET]
ldr r2, [r1, #MSC1_OFFSET]
/* MSC2: nCS(4,5) */
ldr r2, =CFG_MSC2_VAL
str r2, [r1, #MSC2_OFFSET]
ldr r2, [r1, #MSC2_OFFSET]
/* ---------------------------------------------------------------- */
/* Step 2b: Initialize Card Interface */
/* ---------------------------------------------------------------- */
/* MECR: Memory Expansion Card Register */
ldr r2, =CFG_MECR_VAL
str r2, [r1, #MECR_OFFSET]
ldr r2, [r1, #MECR_OFFSET]
/* MCMEM0: Card Interface slot 0 timing */
ldr r2, =CFG_MCMEM0_VAL
str r2, [r1, #MCMEM0_OFFSET]
ldr r2, [r1, #MCMEM0_OFFSET]
/* MCMEM1: Card Interface slot 1 timing */
ldr r2, =CFG_MCMEM1_VAL
str r2, [r1, #MCMEM1_OFFSET]
ldr r2, [r1, #MCMEM1_OFFSET]
/* MCATT0: Card Interface Attribute Space Timing, slot 0 */
ldr r2, =CFG_MCATT0_VAL
str r2, [r1, #MCATT0_OFFSET]
ldr r2, [r1, #MCATT0_OFFSET]
/* MCATT1: Card Interface Attribute Space Timing, slot 1 */
ldr r2, =CFG_MCATT1_VAL
str r2, [r1, #MCATT1_OFFSET]
ldr r2, [r1, #MCATT1_OFFSET]
/* MCIO0: Card Interface I/O Space Timing, slot 0 */
ldr r2, =CFG_MCIO0_VAL
str r2, [r1, #MCIO0_OFFSET]
ldr r2, [r1, #MCIO0_OFFSET]
/* MCIO1: Card Interface I/O Space Timing, slot 1 */
ldr r2, =CFG_MCIO1_VAL
str r2, [r1, #MCIO1_OFFSET]
ldr r2, [r1, #MCIO1_OFFSET]
/* ---------------------------------------------------------------- */
/* Step 2c: Write FLYCNFG FIXME: what's that??? */
/* ---------------------------------------------------------------- */
ldr r2, =CFG_FLYCNFG_VAL
str r2, [r1, #FLYCNFG_OFFSET]
str r2, [r1, #FLYCNFG_OFFSET]
/* ---------------------------------------------------------------- */
/* Step 2d: Initialize Timing for Sync Memory (SDCLK0) */
/* ---------------------------------------------------------------- */
/* Before accessing MDREFR we need a valid DRI field, so we set */
/* this to power on defaults + DRI field. */
ldr r4, [r1, #MDREFR_OFFSET]
ldr r2, =0xFFF
bic r4, r4, r2
ldr r3, =CFG_MDREFR_VAL
and r3, r3, r2
orr r4, r4, r3
str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */
orr r4, r4, #MDREFR_K0RUN
orr r4, r4, #MDREFR_K0DB4
orr r4, r4, #MDREFR_K0FREE
orr r4, r4, #MDREFR_K0DB2
orr r4, r4, #MDREFR_K1DB2
bic r4, r4, #MDREFR_K1FREE
bic r4, r4, #MDREFR_K2FREE
str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */
ldr r4, [r1, #MDREFR_OFFSET]
/* Note: preserve the mdrefr value in r4 */
/* ---------------------------------------------------------------- */
/* Step 3: Initialize Synchronous Static Memory (Flash/Peripherals) */
/* ---------------------------------------------------------------- */
/* Initialize SXCNFG register. Assert the enable bits */
/* Write SXMRS to cause an MRS command to all enabled banks of */
/* synchronous static memory. Note that SXLCR need not be written */
/* at this time. */
ldr r2, =CFG_SXCNFG_VAL
str r2, [r1, #SXCNFG_OFFSET]
/* ---------------------------------------------------------------- */
/* Step 4: Initialize SDRAM */
/* ---------------------------------------------------------------- */
bic r4, r4, #(MDREFR_K2FREE |MDREFR_K1FREE | MDREFR_K0FREE)
orr r4, r4, #MDREFR_K1RUN
bic r4, r4, #MDREFR_K2DB2
str r4, [r1, #MDREFR_OFFSET]
ldr r4, [r1, #MDREFR_OFFSET]
bic r4, r4, #MDREFR_SLFRSH
str r4, [r1, #MDREFR_OFFSET]
ldr r4, [r1, #MDREFR_OFFSET]
orr r4, r4, #MDREFR_E1PIN
str r4, [r1, #MDREFR_OFFSET]
ldr r4, [r1, #MDREFR_OFFSET]
nop
nop
/* Step 4d: write MDCNFG with MDCNFG:DEx deasserted (set to 0), to */
/* configure but not enable each SDRAM partition pair. */
ldr r4, =CFG_MDCNFG_VAL
bic r4, r4, #(MDCNFG_DE0|MDCNFG_DE1)
bic r4, r4, #(MDCNFG_DE2|MDCNFG_DE3)
str r4, [r1, #MDCNFG_OFFSET] /* write back MDCNFG */
ldr r4, [r1, #MDCNFG_OFFSET]
/* Step 4e: Wait for the clock to the SDRAMs to stabilize, */
/* 100..200 µsec. */
ldr r3, =OSCR /* reset the OS Timer Count to zero */
mov r2, #0
str r2, [r3]
ldr r4, =0x300 /* really 0x2E1 is about 200usec, */
/* so 0x300 should be plenty */
1:
ldr r2, [r3]
cmp r4, r2
bgt 1b
/* Step 4f: Trigger a number (usually 8) refresh cycles by */
/* attempting non-burst read or write accesses to disabled */
/* SDRAM, as commonly specified in the power up sequence */
/* documented in SDRAM data sheets. The address(es) used */
/* for this purpose must not be cacheable. */
ldr r3, =CFG_DRAM_BASE
str r2, [r3]
str r2, [r3]
str r2, [r3]
str r2, [r3]
str r2, [r3]
str r2, [r3]
str r2, [r3]
str r2, [r3]
/* Step 4g: Write MDCNFG with enable bits asserted */
/* (MDCNFG:DEx set to 1). */
ldr r3, [r1, #MDCNFG_OFFSET]
mov r4, r3
orr r3, r3, #MDCNFG_DE0
str r3, [r1, #MDCNFG_OFFSET]
mov r0, r3
/* Step 4h: Write MDMRS. */
ldr r2, =CFG_MDMRS_VAL
str r2, [r1, #MDMRS_OFFSET]
/* enable APD */
ldr r3, [r1, #MDREFR_OFFSET]
orr r3, r3, #MDREFR_APD
str r3, [r1, #MDREFR_OFFSET]
/* We are finished with Intel's memory controller initialisation */
setvoltage:
mov r10, lr
bl initPXAvoltage /* In case the board is rebooting with a */
mov lr, r10 /* low voltage raise it up to a good one. */
#if 1
b initirqs
#endif
wakeup:
/* Are we waking from sleep? */
ldr r0, =RCSR
ldr r1, [r0]
and r1, r1, #(RCSR_GPR | RCSR_SMR | RCSR_WDR | RCSR_HWR)
str r1, [r0]
teq r1, #RCSR_SMR
bne initirqs
ldr r0, =PSSR
mov r1, #PSSR_PH
str r1, [r0]
/* if so, resume at PSPR */
ldr r0, =PSPR
ldr r1, [r0]
mov pc, r1
/* ---------------------------------------------------------------- */
/* Disable (mask) all interrupts at interrupt controller */
/* ---------------------------------------------------------------- */
initirqs:
mov r1, #0 /* clear int. level register (IRQ, not FIQ) */
ldr r2, =ICLR
str r1, [r2]
ldr r2, =ICMR /* mask all interrupts at the controller */
str r1, [r2]
/* ---------------------------------------------------------------- */
/* Clock initialisation */
/* ---------------------------------------------------------------- */
initclks:
/* Disable the peripheral clocks, and set the core clock frequency */
/* Turn Off on-chip peripheral clocks (except for memory) */
/* for re-configuration. */
ldr r1, =CKEN
ldr r2, =CFG_CKEN
str r2, [r1]
/* ... and write the core clock config register */
ldr r2, =CFG_CCCR
ldr r1, =CCCR
str r2, [r1]
/* Turn on turbo mode */
mrc p14, 0, r2, c6, c0, 0
orr r2, r2, #0xB /* Turbo, Fast-Bus, Freq change**/
mcr p14, 0, r2, c6, c0, 0
/* Re-write MDREFR */
ldr r1, =MEMC_BASE
ldr r2, [r1, #MDREFR_OFFSET]
str r2, [r1, #MDREFR_OFFSET]
#ifdef RTC
/* enable the 32Khz oscillator for RTC and PowerManager */
ldr r1, =OSCC
mov r2, #OSCC_OON
str r2, [r1]
/* NOTE: spin here until OSCC.OOK get set, meaning the PLL */
/* has settled. */
60:
ldr r2, [r1]
ands r2, r2, #1
beq 60b
#else
#error "RTC not defined"
#endif
/* Interrupt init: Mask all interrupts */
ldr r0, =ICMR /* enable no sources */
mov r1, #0
str r1, [r0]
/* FIXME */
#ifdef NODEBUG
/*Disable software and data breakpoints */
mov r0,#0
mcr p15,0,r0,c14,c8,0 /* ibcr0 */
mcr p15,0,r0,c14,c9,0 /* ibcr1 */
mcr p15,0,r0,c14,c4,0 /* dbcon */
/*Enable all debug functionality */
mov r0,#0x80000000
mcr p14,0,r0,c10,c0,0 /* dcsr */
#endif
/* ---------------------------------------------------------------- */
/* End lowlevel_init */
/* ---------------------------------------------------------------- */
endlowlevel_init:
mov pc, lr

30
include/led.h → board/trizepsiv/pxavoltage.S
View File

@ -1,7 +1,6 @@
/*
* (C) Copyright 2006
* Atmel Nordic AB <www.atmel.com>
* Ulf Samuelsson <ulf@atmel.com>
* (C) Copyright 2007
* Stefano Babic, DENX Gmbh, sbabic@denx.de
*
* See file CREDITS for list of people who contributed to this
* project.
@ -22,24 +21,9 @@
* MA 02111-1307 USA
*/
#ifndef __LED_H
#define __LED_H
#include <asm/arch/pxa-regs.h>
#ifndef __ASSEMBLY__
extern void LED_init (void);
extern void red_LED_on(void);
extern void red_LED_off(void);
extern void green_LED_on(void);
extern void green_LED_off(void);
extern void yellow_LED_on(void);
extern void yellow_LED_off(void);
#else
.extern LED_init
.extern red_LED_on
.extern red_LED_off
.extern yellow_LED_on
.extern yellow_LED_off
.extern green_LED_on
.extern green_LED_off
#endif
#endif
.global initPXAvoltage
initPXAvoltage:
mov pc, lr

56
board/trizepsiv/u-boot.lds Normal file
View File

@ -0,0 +1,56 @@
/*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
OUTPUT_ARCH(arm)
ENTRY(_start)
SECTIONS
{
. = 0x00000000;
. = ALIGN(4);
.text :
{
cpu/pxa/start.o (.text)
*(.text)
}
. = ALIGN(4);
.rodata : { *(.rodata) }
. = ALIGN(4);
.data : { *(.data) }
. = ALIGN(4);
.got : { *(.got) }
. = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
. = ALIGN(4);
__bss_start = .;
.bss : { *(.bss) }
_end = .;
}

3
common/Makefile
View File

@ -37,13 +37,14 @@ COBJS = main.o ACEX1K.o altera.o bedbug.o circbuf.o cmd_autoscript.o \
cmd_load.o cmd_log.o \
cmd_mem.o cmd_mii.o cmd_misc.o cmd_mmc.o \
cmd_nand.o cmd_net.o cmd_nvedit.o \
cmd_onenand.o \
cmd_pci.o cmd_pcmcia.o cmd_portio.o \
cmd_reginfo.o cmd_reiser.o cmd_sata.o cmd_scsi.o cmd_spi.o \
cmd_universe.o cmd_usb.o cmd_vfd.o \
command.o console.o cyclon2.o devices.o dlmalloc.o docecc.o \
environment.o env_common.o \
env_nand.o env_dataflash.o env_flash.o env_eeprom.o \
env_nvram.o env_nowhere.o \
env_onenand.o env_nvram.o env_nowhere.o \
exports.o \
fdt_support.o flash.o fpga.o ft_build.o \
hush.o kgdb.o lcd.o lists.o lynxkdi.o \

67
common/cmd_bootm.c
View File

@ -817,27 +817,34 @@ do_bootm_linux (cmd_tbl_t *cmdtp, int flag,
int i;
/* skip kernel length, initrd length, and terminator */
of_data = (ulong)(&len_ptr[3]);
of_flat_tree = (char *)(&len_ptr[3]);
/* skip any additional image length fields */
for (i=2; len_ptr[i]; ++i)
of_data += 4;
of_flat_tree += 4;
/* add kernel length, and align */
of_data += ntohl(len_ptr[0]);
of_flat_tree += ntohl(len_ptr[0]);
if (tail) {
of_data += 4 - tail;
of_flat_tree += 4 - tail;
}
/* add initrd length, and align */
tail = ntohl(len_ptr[1]) % 4;
of_data += ntohl(len_ptr[1]);
of_flat_tree += ntohl(len_ptr[1]);
if (tail) {
of_data += 4 - tail;
of_flat_tree += 4 - tail;
}
#ifndef CFG_NO_FLASH
/* move the blob if it is in flash (set of_data to !null) */
if (addr2info ((ulong)of_flat_tree) != NULL)
of_data = (ulong)of_flat_tree;
#endif
#if defined(CONFIG_OF_FLAT_TREE)
if (*((ulong *)(of_flat_tree + sizeof(image_header_t))) != OF_DT_HEADER) {
if (*((ulong *)(of_flat_tree)) != OF_DT_HEADER) {
#else
if (fdt_check_header(of_flat_tree + sizeof(image_header_t)) != 0) {
if (fdt_check_header (of_flat_tree) != 0) {
#endif
puts ("ERROR: image is not a fdt - "
"must RESET the board to recover.\n");
@ -845,9 +852,11 @@ do_bootm_linux (cmd_tbl_t *cmdtp, int flag,
}
#if defined(CONFIG_OF_FLAT_TREE)
if (((struct boot_param_header *)of_data)->totalsize != ntohl(len_ptr[2])) {
if (((struct boot_param_header *)of_flat_tree)->totalsize !=
ntohl (len_ptr[2])) {
#else
if (be32_to_cpu(fdt_totalsize(of_data)) != ntohl(len_ptr[2])) {
if (be32_to_cpu (fdt_totalsize (of_flat_tree)) !=
ntohl(len_ptr[2])) {
#endif
puts ("ERROR: fdt size != image size - "
"must RESET the board to recover.\n");
@ -957,34 +966,37 @@ do_bootm_linux (cmd_tbl_t *cmdtp, int flag,
"must RESET the board to recover.\n");
do_reset (cmdtp, flag, argc, argv);
}
puts ("OK\n");
}
/*
* Add the chosen node if it doesn't exist, add the env and bd_t
* if the user wants it (the logic is in the subroutines).
*/
if (fdt_chosen(of_flat_tree, initrd_start, initrd_end, 0) < 0) {
puts ("ERROR: /chosen node create failed - "
"must RESET the board to recover.\n");
do_reset (cmdtp, flag, argc, argv);
}
if (of_flat_tree) {
if (fdt_chosen(of_flat_tree, initrd_start, initrd_end, 0) < 0) {
puts ("ERROR: /chosen node create failed - "
"must RESET the board to recover.\n");
do_reset (cmdtp, flag, argc, argv);
}
#ifdef CONFIG_OF_HAS_UBOOT_ENV
if (fdt_env(of_flat_tree) < 0) {
puts ("ERROR: /u-boot-env node create failed - "
"must RESET the board to recover.\n");
do_reset (cmdtp, flag, argc, argv);
}
if (fdt_env(of_flat_tree) < 0) {
puts ("ERROR: /u-boot-env node create failed - "
"must RESET the board to recover.\n");
do_reset (cmdtp, flag, argc, argv);
}
#endif
#ifdef CONFIG_OF_HAS_BD_T
if (fdt_bd_t(of_flat_tree) < 0) {
puts ("ERROR: /bd_t node create failed - "
"must RESET the board to recover.\n");
do_reset (cmdtp, flag, argc, argv);
}
if (fdt_bd_t(of_flat_tree) < 0) {
puts ("ERROR: /bd_t node create failed - "
"must RESET the board to recover.\n");
do_reset (cmdtp, flag, argc, argv);
}
#endif
#ifdef CONFIG_OF_BOARD_SETUP
/* Call the board-specific fixup routine */
ft_board_setup(of_flat_tree, gd->bd);
/* Call the board-specific fixup routine */
ft_board_setup(of_flat_tree, gd->bd);
#endif
}
#endif /* CONFIG_OF_LIBFDT */
#if defined(CONFIG_OF_FLAT_TREE)
#ifdef CFG_BOOTMAPSZ
@ -1011,6 +1023,7 @@ do_bootm_linux (cmd_tbl_t *cmdtp, int flag,
printf (" Loading Device Tree to %08lx, end %08lx ... ",
of_start, of_start + of_len - 1);
memmove ((void *)of_start, (void *)of_data, of_len);
puts ("OK\n");
}
/*
* Create the /chosen node and modify the blob with board specific

2
common/cmd_fpga.c
View File

@ -60,6 +60,7 @@ static int fpga_get_op (char *opstr);
/* Convert bitstream data and load into the fpga */
int fpga_loadbitstream(unsigned long dev, char* fpgadata, size_t size)
{
#if (CONFIG_FPGA & CFG_FPGA_XILINX)
unsigned int length;
unsigned char* swapdata;
unsigned int swapsize;
@ -72,7 +73,6 @@ int fpga_loadbitstream(unsigned long dev, char* fpgadata, size_t size)
dataptr = (unsigned char *)fpgadata;
#if CFG_FPGA_XILINX
/* skip the first bytes of the bitsteam, their meaning is unknown */
length = (*dataptr << 8) + *(dataptr+1);
dataptr+=2;

16
common/cmd_mfsl.c
View File

@ -355,19 +355,18 @@ int do_rspr (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
unsigned int reg = 0;
unsigned int val = 0;
reg = (unsigned int)simple_strtoul (argv[1], NULL, 16);
val = (unsigned int)simple_strtoul (argv[2], NULL, 16);
if (argc < 1) {
if (argc < 2) {
printf ("Usage:\n%s\n", cmdtp->usage);
return 1;
}
reg = (unsigned int)simple_strtoul (argv[1], NULL, 16);
val = (unsigned int)simple_strtoul (argv[2], NULL, 16);
switch (reg) {
case 0x1:
if (argc > 2) {
MTS (val, rmsr);
NOP;
MFS (val, rmsr);
} else {
MFS (val, rmsr);
}
@ -382,6 +381,7 @@ int do_rspr (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
puts ("ESR");
break;
default:
puts ("Unsupported register\n");
return 1;
}
printf (": 0x%08lx\n", val);
@ -408,10 +408,10 @@ U_BOOT_CMD (fwr, 4, 1, do_fwr,
" 3 - blocking control write\n");
U_BOOT_CMD (rspr, 3, 1, do_rspr,
"rmsr - read/write special purpose register\n",
"rspr - read/write special purpose register\n",
"- reg_num [write value] read/write special purpose register\n"
" 0 - MSR - Machine status register\n"
" 1 - EAR - Exception address register\n"
" 2 - ESR - Exception status register\n");
" 1 - MSR - Machine status register\n"
" 3 - EAR - Exception address register\n"
" 5 - ESR - Exception status register\n");
#endif

6
common/cmd_nand.c
View File

@ -161,7 +161,11 @@ int do_nand(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
ulong addr, off, size;
char *cmd, *s;
nand_info_t *nand;
#ifdef CFG_NAND_QUIET
int quiet = CFG_NAND_QUIET;
#else
int quiet = 0;
#endif
const char *quiet_str = getenv("quiet");
/* at least two arguments please */
@ -452,7 +456,7 @@ U_BOOT_CMD(nand, 5, 1, do_nand,
"info - show available NAND devices\n"
"nand device [dev] - show or set current device\n"
"nand read[.jffs2] - addr off|partition size\n"
"nand write[.jffs2] - addr off|partiton size - read/write `size' bytes starting\n"
"nand write[.jffs2] - addr off|partition size - read/write `size' bytes starting\n"
" at offset `off' to/from memory address `addr'\n"
"nand erase [clean] [off size] - erase `size' bytes from\n"
" offset `off' (entire device if not specified)\n"

9
common/cmd_nvedit.c
View File

@ -57,8 +57,9 @@ DECLARE_GLOBAL_DATA_PTR;
!defined(CFG_ENV_IS_IN_FLASH) && \
!defined(CFG_ENV_IS_IN_DATAFLASH) && \
!defined(CFG_ENV_IS_IN_NAND) && \
!defined(CFG_ENV_IS_IN_ONENAND) && \
!defined(CFG_ENV_IS_NOWHERE)
# error Define one of CFG_ENV_IS_IN_{NVRAM|EEPROM|FLASH|DATAFLASH|NOWHERE}
# error Define one of CFG_ENV_IS_IN_{NVRAM|EEPROM|FLASH|DATAFLASH|ONENAND|NOWHERE}
#endif
#define XMK_STR(x) #x
@ -553,7 +554,8 @@ int getenv_r (char *name, char *buf, unsigned len)
#if defined(CFG_ENV_IS_IN_NVRAM) || defined(CFG_ENV_IS_IN_EEPROM) \
|| (defined(CONFIG_CMD_ENV) && defined(CONFIG_CMD_FLASH)) \
|| (defined(CONFIG_CMD_ENV) && defined(CONFIG_CMD_NAND))
|| (defined(CONFIG_CMD_ENV) && defined(CONFIG_CMD_NAND)) \
|| (defined(CONFIG_CMD_ENV) && defined(CONFIG_CMD_ONENAND))
int do_saveenv (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
extern char * env_name_spec;
@ -608,7 +610,8 @@ U_BOOT_CMD(
#if defined(CFG_ENV_IS_IN_NVRAM) || defined(CFG_ENV_IS_IN_EEPROM) \
|| (defined(CONFIG_CMD_ENV) && defined(CONFIG_CMD_FLASH)) \
|| (defined(CONFIG_CMD_ENV) && defined(CONFIG_CMD_NAND))
|| (defined(CONFIG_CMD_ENV) && defined(CONFIG_CMD_NAND)) \
|| (defined(CONFIG_CMD_ENV) && defined(CONFIG_CMD_ONENAND))
U_BOOT_CMD(
saveenv, 1, 0, do_saveenv,
"saveenv - save environment variables to persistent storage\n",

155
common/cmd_onenand.c Normal file
View File

@ -0,0 +1,155 @@
/*
* U-Boot command for OneNAND support
*
* Copyright (C) 2005-2007 Samsung Electronics
* Kyungmin Park <kyungmin.park@samsung.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <common.h>
#include <command.h>
#ifdef CONFIG_CMD_ONENAND
#include <linux/mtd/compat.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/onenand.h>
#include <asm/io.h>
extern struct mtd_info onenand_mtd;
extern struct onenand_chip onenand_chip;
int do_onenand(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
{
int ret = 0;
switch (argc) {
case 0:
case 1:
printf("Usage:\n%s\n", cmdtp->usage);
return 1;
case 2:
if (strncmp(argv[1], "open", 4) == 0) {
onenand_init();
return 0;
}
onenand_print_device_info(onenand_chip.device_id, 1);
return 0;
default:
/* At least 4 args */
if (strncmp(argv[1], "erase", 5) == 0) {
struct erase_info instr;
ulong start, end;
ulong block;
start = simple_strtoul(argv[2], NULL, 10);
end = simple_strtoul(argv[3], NULL, 10);
start -= (unsigned long)onenand_chip.base;
end -= (unsigned long)onenand_chip.base;
if (!end || end < 0)
end = start;
printf("Erase block from %d to %d\n", start, end);
for (block = start; block <= end; block++) {
instr.addr = block << onenand_chip.erase_shift;
instr.len = 1 << onenand_chip.erase_shift;
ret = onenand_erase(&onenand_mtd, &instr);
if (ret) {
printf("erase failed %d\n", block);
break;
}
}
return 0;
}
if (strncmp(argv[1], "read", 4) == 0) {
ulong addr = simple_strtoul(argv[2], NULL, 16);
ulong ofs = simple_strtoul(argv[3], NULL, 16);
size_t len = simple_strtoul(argv[4], NULL, 16);
size_t retlen = 0;
int oob = strncmp(argv[1], "read.oob", 8) ? 0 : 1;
ofs -= (unsigned long)onenand_chip.base;
if (oob)
onenand_read_oob(&onenand_mtd, ofs, len,
&retlen, (u_char *) addr);
else
onenand_read(&onenand_mtd, ofs, len, &retlen,
(u_char *) addr);
printf("Done\n");
return 0;
}
if (strncmp(argv[1], "write", 5) == 0) {
ulong addr = simple_strtoul(argv[2], NULL, 16);
ulong ofs = simple_strtoul(argv[3], NULL, 16);
size_t len = simple_strtoul(argv[4], NULL, 16);
size_t retlen = 0;
ofs -= (unsigned long)onenand_chip.base;
onenand_write(&onenand_mtd, ofs, len, &retlen,
(u_char *) addr);
printf("Done\n");
return 0;
}
if (strncmp(argv[1], "block", 5) == 0) {
ulong addr = simple_strtoul(argv[2], NULL, 16);
ulong block = simple_strtoul(argv[3], NULL, 10);
ulong page = simple_strtoul(argv[4], NULL, 10);
size_t len = simple_strtol(argv[5], NULL, 10);
size_t retlen = 0;
ulong ofs;
int oob = strncmp(argv[1], "block.oob", 9) ? 0 : 1;
ofs = block << onenand_chip.erase_shift;
if (page)
ofs += page << onenand_chip.page_shift;
if (!len) {
if (oob)
len = 64;
else
len = 512;
}
if (oob)
onenand_read_oob(&onenand_mtd, ofs, len,
&retlen, (u_char *) addr);
else
onenand_read(&onenand_mtd, ofs, len, &retlen,
(u_char *) addr);
return 0;
}
break;
}
return 0;
}
U_BOOT_CMD(
onenand, 6, 1, do_onenand,
"onenand - OneNAND sub-system\n",
"info - show available OneNAND devices\n"
"onenand read[.oob] addr ofs len - read data at ofs with len to addr\n"
"onenand write addr ofs len - write data at ofs with len from addr\n"
"onenand erase saddr eaddr - erase block start addr to end addr\n"
"onenand block[.oob] addr block [page] [len] - "
"read data with (block [, page]) to addr"
);
#endif /* CONFIG_CMD_ONENAND */

134
common/env_onenand.c Normal file
View File

@ -0,0 +1,134 @@
/*
* (C) Copyright 2005-2007 Samsung Electronics
* Kyungmin Park <kyungmin.park@samsung.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#if defined(CFG_ENV_IS_IN_ONENAND) /* Environment is in OneNAND */
#include <command.h>
#include <environment.h>
#include <linux/stddef.h>
#include <malloc.h>
#include <linux/mtd/compat.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/onenand.h>
extern struct mtd_info onenand_mtd;
extern struct onenand_chip onenand_chip;
/* References to names in env_common.c */
extern uchar default_environment[];
#define ONENAND_ENV_SIZE(mtd) (mtd.oobblock - ENV_HEADER_SIZE)
char *env_name_spec = "OneNAND";
#ifdef ENV_IS_EMBEDDED
extern uchar environment[];
env_t *env_ptr = (env_t *) (&environment[0]);
#else /* ! ENV_IS_EMBEDDED */
static unsigned char onenand_env[MAX_ONENAND_PAGESIZE];
env_t *env_ptr = (env_t *) onenand_env;
#endif /* ENV_IS_EMBEDDED */
uchar env_get_char_spec(int index)
{
DECLARE_GLOBAL_DATA_PTR;
return (*((uchar *) (gd->env_addr + index)));
}
void env_relocate_spec(void)
{
DECLARE_GLOBAL_DATA_PTR;
unsigned long env_addr;
int use_default = 0;
int retlen;
env_addr = CFG_ENV_ADDR;
env_addr -= (unsigned long)onenand_chip.base;
/* Check OneNAND exist */
if (onenand_mtd.oobblock)
/* Ignore read fail */
onenand_read(&onenand_mtd, env_addr, onenand_mtd.oobblock,
&retlen, (u_char *) env_ptr);
else
onenand_mtd.oobblock = MAX_ONENAND_PAGESIZE;
if (crc32(0, env_ptr->data, ONENAND_ENV_SIZE(onenand_mtd)) !=
env_ptr->crc)
use_default = 1;
if (use_default) {
memcpy(env_ptr->data, default_environment,
ONENAND_ENV_SIZE(onenand_mtd));
env_ptr->crc =
crc32(0, env_ptr->data, ONENAND_ENV_SIZE(onenand_mtd));
}
gd->env_addr = (ulong) & env_ptr->data;
gd->env_valid = 1;
}
int saveenv(void)
{
unsigned long env_addr = CFG_ENV_ADDR;
struct erase_info instr;
int retlen;
instr.len = CFG_ENV_SIZE;
instr.addr = env_addr;
instr.addr -= (unsigned long)onenand_chip.base;
if (onenand_erase(&onenand_mtd, &instr)) {
printf("OneNAND: erase failed at 0x%08x\n", env_addr);
return 1;
}
/* update crc */
env_ptr->crc =
crc32(0, env_ptr->data, onenand_mtd.oobblock - ENV_HEADER_SIZE);
env_addr -= (unsigned long)onenand_chip.base;
if (onenand_write(&onenand_mtd, env_addr, onenand_mtd.oobblock, &retlen,
(u_char *) env_ptr)) {
printf("OneNAND: write failed at 0x%08x\n", instr.addr);
return 2;
}
return 0;
}
int env_init(void)
{
DECLARE_GLOBAL_DATA_PTR;
/* use default */
gd->env_addr = (ulong) & default_environment[0];
gd->env_valid = 1;
return 0;
}
#endif /* CFG_ENV_IS_IN_ONENAND */

13
common/environment.c
View File

@ -51,18 +51,7 @@
* a seperate section. Note that ENV_CRC is only defined when building
* U-Boot itself.
*/
#if (defined(CONFIG_CMI) || \
defined(CONFIG_FADS) || \
defined(CONFIG_HYMOD) || \
defined(CONFIG_ICU862) || \
defined(CONFIG_R360MPI) || \
defined(CONFIG_TQM8xxL) || \
defined(CONFIG_RRVISION) || \
defined(CONFIG_TRAB) || \
defined(CONFIG_PPCHAMELEONEVB) || \
defined(CONFIG_M5271EVB) || \
defined(CONFIG_IDMR) || \
defined(CONFIG_NAND_U_BOOT)) && \
#if (defined(CFG_USE_PPCENV) || defined(CONFIG_NAND_U_BOOT)) && \
defined(ENV_CRC) /* Environment embedded in U-Boot .ppcenv section */
/* XXX - This only works with GNU C */
# define __PPCENV__ __attribute__ ((section(".ppcenv")))

13
common/serial.c
View File

@ -32,7 +32,7 @@ DECLARE_GLOBAL_DATA_PTR;
static struct serial_device *serial_devices = NULL;
static struct serial_device *serial_current = NULL;
#ifndef CONFIG_LWMON
#if !defined(CONFIG_LWMON) && !defined(CONFIG_PXA27X)
struct serial_device *default_serial_console (void)
{
#if defined(CONFIG_8xx_CONS_SMC1) || defined(CONFIG_8xx_CONS_SMC2)
@ -65,7 +65,7 @@ struct serial_device *default_serial_console (void)
}
#endif
static int serial_register (struct serial_device *dev)
int serial_register (struct serial_device *dev)
{
dev->init += gd->reloc_off;
dev->setbrg += gd->reloc_off;
@ -110,6 +110,15 @@ void serial_initialize (void)
serial_register(&eserial4_device);
#endif
#endif /* CFG_NS16550_SERIAL */
#if defined (CONFIG_FFUART)
serial_register(&serial_ffuart_device);
#endif
#if defined (CONFIG_BTUART)
serial_register(&serial_btuart_device);
#endif
#if defined (CONFIG_STUART)
serial_register(&serial_stuart_device);
#endif
serial_assign (default_serial_console ()->name);
}

1
cpu/arm1136/config.mk
View File

@ -31,4 +31,5 @@ PLATFORM_CPPFLAGS += -march=armv5
#
# =========================================================================
PLATFORM_CPPFLAGS +=$(call cc-option,-mapcs-32,-mabi=apcs-gnu)
PLATFORM_CPPFLAGS +=$(call cc-option,-mno-thumb-interwork,)
PLATFORM_RELFLAGS +=$(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,))

4
cpu/arm720t/serial.c
View File

@ -125,12 +125,12 @@ serial_puts (const char *s)
#elif defined(CONFIG_LPC2292)
DECLARE_GLOBAL_DATA_PTR;
#include <asm/arch/hardware.h>
void serial_setbrg (void)
{
DECLARE_GLOBAL_DATA_PTR;
unsigned short divisor = 0;
switch (gd->baudrate) {

128
cpu/arm920t/start.S
View File

@ -27,9 +27,7 @@
#include <config.h>
#include <version.h>
#if defined(CONFIG_AT91RM9200DK) || defined(CONFIG_AT91RM9200EK) || defined(CONFIG_AT91RM9200DF)
#include <led.h>
#endif
#include <status_led.h>
/*
*************************************************************************
@ -41,7 +39,7 @@
.globl _start
_start: b reset
_start: b start_code
ldr pc, _undefined_instruction
ldr pc, _software_interrupt
ldr pc, _prefetch_abort
@ -64,7 +62,7 @@ _fiq: .word fiq
/*
*************************************************************************
*
* Startup Code (reset vector)
* Startup Code (called from the ARM reset exception vector)
*
* do important init only if we don't start from memory!
* relocate armboot to ram
@ -106,10 +104,10 @@ FIQ_STACK_START:
/*
* the actual reset code
* the actual start code
*/
reset:
start_code:
/*
* set the cpu to SVC32 mode
*/
@ -118,58 +116,12 @@ reset:
orr r0,r0,#0xd3
msr cpsr,r0
#if CONFIG_AT91RM9200
#if defined(CONFIG_AT91RM9200DK) || defined(CONFIG_AT91RM9200EK) || defined(CONFIG_AT91RM9200DF)
bl LED_init
bl coloured_LED_init
bl red_LED_on
#endif
#ifdef CONFIG_BOOTBINFUNC
/* code based on entry.S from ATMEL */
#define AT91C_BASE_CKGR 0xFFFFFC20
#define CKGR_MOR 0
/* Get the CKGR Base Address */
ldr r1, =AT91C_BASE_CKGR
/* Main oscillator Enable register APMC_MOR : Enable main oscillator , OSCOUNT = 0xFF */
/* ldr r0, = AT91C_CKGR_MOSCEN:OR:AT91C_CKGR_OSCOUNT */
ldr r0, =0x0000FF01
str r0, [r1, #CKGR_MOR]
/* Add loop to compensate Main Oscillator startup time */
ldr r0, =0x00000010
LoopOsc:
subs r0, r0, #1
bhi LoopOsc
/* scratch stack */
ldr r1, =0x00204000
/* Insure word alignment */
bic r1, r1, #3
/* Init stack SYS */
mov sp, r1
#if defined(CONFIG_AT91RM9200DK) || defined(CONFIG_AT91RM9200EK) || defined(CONFIG_AT91RM9200DF)
/*
* This does a lot more than just set up the memory, which
* is why it's called lowlevelinit
*/
bl lowlevelinit /* in memsetup.S */
bl icache_enable;
/* ------------------------------------
* Read/modify/write CP15 control register
* -------------------------------------
* read cp15 control register (cp15 r1) in r0
* ------------------------------------
*/
mrc p15, 0, r0, c1, c0, 0
/* Reset bit :Little Endian end fast bus mode */
ldr r3, =0xC0000080
/* Set bit :Asynchronous clock mode, Not Fast Bus */
ldr r4, =0xC0000000
bic r0, r0, r3
orr r0, r0, r4
/* write r0 in cp15 control register (cp15 r1) */
mcr p15, 0, r0, c1, c0, 0
#endif /* CONFIG_BOOTBINFUNC */
/*
* relocate exeception table
* relocate exception table
*/
ldr r0, =_start
ldr r1, =0x0
@ -181,19 +133,20 @@ copyex:
bne copyex
#endif
/* turn off the watchdog */
#if defined(CONFIG_S3C2400)
# define pWTCON 0x15300000
# define INTMSK 0x14400008 /* Interupt-Controller base addresses */
# define CLKDIVN 0x14800014 /* clock divisor register */
#elif defined(CONFIG_S3C2410)
# define pWTCON 0x53000000
# define INTMSK 0x4A000008 /* Interupt-Controller base addresses */
# define INTSUBMSK 0x4A00001C
# define CLKDIVN 0x4C000014 /* clock divisor register */
#endif
#if defined(CONFIG_S3C2400) || defined(CONFIG_S3C2410)
/* turn off the watchdog */
# if defined(CONFIG_S3C2400)
# define pWTCON 0x15300000
# define INTMSK 0x14400008 /* Interupt-Controller base addresses */
# define CLKDIVN 0x14800014 /* clock divisor register */
#else
# define pWTCON 0x53000000
# define INTMSK 0x4A000008 /* Interupt-Controller base addresses */
# define INTSUBMSK 0x4A00001C
# define CLKDIVN 0x4C000014 /* clock divisor register */
# endif
ldr r0, =pWTCON
mov r1, #0x0
str r1, [r0]
@ -226,25 +179,7 @@ copyex:
#endif
#ifdef CONFIG_AT91RM9200
#ifdef CONFIG_BOOTBINFUNC
relocate: /* relocate U-Boot to RAM */
adr r0, _start /* r0 <- current position of code */
ldr r1, _TEXT_BASE /* test if we run from flash or RAM */
cmp r0, r1 /* don't reloc during debug */
beq stack_setup
ldr r2, _armboot_start
ldr r3, _bss_start
sub r2, r3, r2 /* r2 <- size of armboot */
add r2, r0, r2 /* r2 <- source end address */
copy_loop:
ldmia r0!, {r3-r10} /* copy from source address [r0] */
stmia r1!, {r3-r10} /* copy to target address [r1] */
cmp r0, r2 /* until source end addreee [r2] */
ble copy_loop
#endif /* CONFIG_BOOTBINFUNC */
#else
#ifndef CONFIG_SKIP_RELOCATE_UBOOT
relocate: /* relocate U-Boot to RAM */
adr r0, _start /* r0 <- current position of code */
@ -284,27 +219,6 @@ clbss_l:str r2, [r0] /* clear loop... */
cmp r0, r1
ble clbss_l
#if 0
/* try doing this stuff after the relocation */
ldr r0, =pWTCON
mov r1, #0x0
str r1, [r0]
/*
* mask all IRQs by setting all bits in the INTMR - default
*/
mov r1, #0xffffffff
ldr r0, =INTMR
str r1, [r0]
/* FCLK:HCLK:PCLK = 1:2:4 */
/* default FCLK is 120 MHz ! */
ldr r0, =CLKDIVN
mov r1, #3
str r1, [r0]
/* END stuff after relocation */
#endif
ldr pc, _start_armboot
_start_armboot: .word start_armboot

1
cpu/bf533/serial.c
View File

@ -76,7 +76,6 @@ void calc_baud(void)
void serial_setbrg(void)
{
int i;
DECLARE_GLOBAL_DATA_PTR;
calc_baud();

3
cpu/bf537/i2c.c
View File

@ -22,6 +22,8 @@
#include <i2c.h>
#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR;
#define bfin_read16(addr) ({ unsigned __v; \
__asm__ __volatile__ (\
"%0 = w[%1] (z);\n\t"\
@ -68,7 +70,6 @@
#ifdef DEBUG_I2C
#define PRINTD(fmt,args...) do { \
DECLARE_GLOBAL_DATA_PTR; \
if (gd->have_console) \
printf(fmt ,##args); \
} while (0)

3
cpu/bf537/serial.c
View File

@ -52,6 +52,8 @@
#include <asm/io.h>
#include "serial.h"
DECLARE_GLOBAL_DATA_PTR;
unsigned long pll_div_fact;
void calc_baud(void)
@ -74,7 +76,6 @@ void calc_baud(void)
void serial_setbrg(void)
{
int i;
DECLARE_GLOBAL_DATA_PTR;
calc_baud();

3
cpu/bf561/serial.c
View File

@ -52,6 +52,8 @@
#include "serial.h"
#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR;
unsigned long pll_div_fact;
void calc_baud(void)
@ -74,7 +76,6 @@ void calc_baud(void)
void serial_setbrg(void)
{
int i;
DECLARE_GLOBAL_DATA_PTR;
calc_baud();

4
cpu/mcf532x/cpu.c
View File

@ -31,6 +31,8 @@
#include <asm/immap.h>
DECLARE_GLOBAL_DATA_PTR;
int do_reset(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char *argv[])
{
volatile wdog_t *wdp = (wdog_t *) (MMAP_WDOG);
@ -48,8 +50,6 @@ int do_reset(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char *argv[])
int checkcpu(void)
{
DECLARE_GLOBAL_DATA_PTR;
volatile ccm_t *ccm = (ccm_t *) MMAP_CCM;
u16 msk;
u16 id = 0;

4
cpu/mcf532x/speed.c
View File

@ -30,6 +30,8 @@
#include <asm/immap.h>
DECLARE_GLOBAL_DATA_PTR;
/* PLL min/max specifications */
#define MAX_FVCO 500000 /* KHz */
#define MAX_FSYS 80000 /* KHz */
@ -208,8 +210,6 @@ int clock_pll(int fsys, int flags)
*/
int get_clocks(void)
{
DECLARE_GLOBAL_DATA_PTR;
gd->bus_clk = clock_pll(CFG_CLK / 1000, 0) * 1000;
gd->cpu_clk = (gd->bus_clk * 3);
return (0);

2
cpu/microblaze/cache.c
View File

@ -1,7 +1,7 @@
/*
* (C) Copyright 2007 Michal Simek
*
* Michal SIMEK <moonstr@monstr.eu>
* Michal SIMEK <monstr@monstr.eu>
*
* See file CREDITS for list of people who contributed to this
* project.

6
cpu/microblaze/start.S
View File

@ -33,15 +33,13 @@ _start:
addi r1, r0, CFG_INIT_SP_OFFSET
addi r1, r1, -4 /* Decrement SP to top of memory */
/* add opcode instruction for 32bit jump - 2 instruction imm & brai*/
addi r6, r0, 0xb000 /* hex b000 opcode imm */
bslli r6, r6, 16 /* shift */
addi r6, r0, 0xb0000000 /* hex b000 opcode imm */
swi r6, r0, 0x0 /* reset address */
swi r6, r0, 0x8 /* user vector exception */
swi r6, r0, 0x10 /* interrupt */
swi r6, r0, 0x20 /* hardware exception */
addi r6, r0, 0xb808 /* hew b808 opcode brai*/
bslli r6, r6, 16
addi r6, r0, 0xb8080000 /* hew b808 opcode brai*/
swi r6, r0, 0x4 /* reset address */
swi r6, r0, 0xC /* user vector exception */
swi r6, r0, 0x14 /* interrupt */

7
cpu/microblaze/timer.c
View File

@ -33,10 +33,17 @@ void reset_timer (void)
timestamp = 0;
}
#ifdef CFG_TIMER_0
ulong get_timer (ulong base)
{
return (timestamp - base);
}
#else
ulong get_timer (ulong base)
{
return (timestamp++ - base);
}
#endif
void set_timer (ulong t)
{

2
cpu/mpc512x/config.mk
View File

@ -19,7 +19,7 @@
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi
PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi -mrelocatable
PLATFORM_CPPFLAGS += -DCONFIG_MPC512X -DCONFIG_E300 \
-ffixed-r2 -ffixed-r29 -msoft-float -mcpu=603e

38
cpu/mpc512x/fec.c
View File

@ -32,6 +32,9 @@ int fec512x_miiphy_read(char *devname, uint8 phyAddr, uint8 regAddr, uint16 * re
int fec512x_miiphy_write(char *devname, uint8 phyAddr, uint8 regAddr, uint16 data);
int mpc512x_fec_init_phy(struct eth_device *dev, bd_t * bis);
static uchar rx_buff[FEC_BUFFER_SIZE];
static int rx_buff_idx = 0;
/********************************************************************/
#if (DEBUG & 0x2)
static void mpc512x_fec_phydump (char *devname)
@ -234,8 +237,8 @@ static int mpc512x_fec_init (struct eth_device *dev, bd_t * bis)
/* Set Opcode/Pause Duration Register */
fec->eth->op_pause = 0x00010020;
/* Frame length=1518; MII mode */
fec->eth->r_cntrl = 0x05ee000c;
/* Frame length=1522; MII mode */
fec->eth->r_cntrl = (FEC_MAX_FRAME_LEN << 16) | 0x24;
/* Half-duplex, heartbeat disabled */
fec->eth->x_cntrl = 0x00000000;
@ -245,7 +248,7 @@ static int mpc512x_fec_init (struct eth_device *dev, bd_t * bis)
/* Setup recv fifo start and buff size */
fec->eth->r_fstart = 0x500;
fec->eth->r_buff_size = 0x5e0;
fec->eth->r_buff_size = FEC_BUFFER_SIZE;
/* Setup BD base addresses */
fec->eth->r_des_start = (uint32)fec->bdBase->rbd;
@ -520,8 +523,7 @@ static int mpc512x_fec_recv (struct eth_device *dev)
mpc512x_fec_priv *fec = (mpc512x_fec_priv *)dev->priv;
volatile FEC_RBD *pRbd = &fec->bdBase->rbd[fec->rbdIndex];
unsigned long ievent;
int frame_length, len = 0;
uchar buff[FEC_MAX_PKT_SIZE];
int frame_length = 0;
#if (DEBUG & 0x1)
printf ("mpc512x_fec_recv %d Start...\n", fec->rbdIndex);
@ -555,31 +557,37 @@ static int mpc512x_fec_recv (struct eth_device *dev)
}
if (!(pRbd->status & FEC_RBD_EMPTY)) {
if ((pRbd->status & FEC_RBD_LAST) &&
!(pRbd->status & FEC_RBD_ERR) &&
if (!(pRbd->status & FEC_RBD_ERR) &&
((pRbd->dataLength - 4) > 14)) {
/*
* Get buffer size
*/
frame_length = pRbd->dataLength - 4;
if (pRbd->status & FEC_RBD_LAST)
frame_length = pRbd->dataLength - 4;
else
frame_length = pRbd->dataLength;
#if (DEBUG & 0x20)
{
int i;
printf ("recv data hdr:");
printf ("recv data length 0x%08x data hdr: ",
pRbd->dataLength);
for (i = 0; i < 14; i++)
printf ("%x ", *((uint8*)pRbd->dataPointer + i));
printf("\n");
}
#endif
/*
* Fill the buffer and pass it to upper layers
*/
memcpy (buff, (void*)pRbd->dataPointer, frame_length);
NetReceive ((uchar*)buff, frame_length);
len = frame_length;
memcpy (&rx_buff[rx_buff_idx], (void*)pRbd->dataPointer,
frame_length - rx_buff_idx);
rx_buff_idx = frame_length;
if (pRbd->status & FEC_RBD_LAST) {
NetReceive ((uchar*)rx_buff, frame_length);
rx_buff_idx = 0;
}
}
/*
@ -590,7 +598,7 @@ static int mpc512x_fec_recv (struct eth_device *dev)
/* Try to fill Buffer Descriptors */
fec->eth->r_des_active = 0x01000000; /* Descriptor polling active */
return len;
return frame_length;
}
/********************************************************************/

7
cpu/mpc512x/fec.h
View File

@ -164,10 +164,13 @@ typedef enum {
#define FEC_RBD_NUM 32 /* The user can adjust this value */
/* packet size limit */
#define FEC_MAX_PKT_SIZE 1536
#define FEC_MAX_FRAME_LEN 1522 /* recommended default value */
/* Buffer size must be evenly divisible by 16 */
#define FEC_BUFFER_SIZE ((FEC_MAX_FRAME_LEN + 0x10) & (~0xf))
typedef struct {
uint8 frame[FEC_MAX_PKT_SIZE];
uint8 frame[FEC_BUFFER_SIZE];
} mpc512x_frame;
typedef struct {

60
cpu/mpc5xxx/cpu.c
View File

@ -29,10 +29,12 @@
#include <watchdog.h>
#include <command.h>
#include <mpc5xxx.h>
#include <asm/io.h>
#include <asm/processor.h>
#if defined(CONFIG_OF_FLAT_TREE)
#include <ft_build.h>
#if defined(CONFIG_OF_LIBFDT)
#include <libfdt.h>
#include <libfdt_env.h>
#endif
DECLARE_GLOBAL_DATA_PTR;
@ -111,29 +113,43 @@ unsigned long get_tbclk (void)
/* ------------------------------------------------------------------------- */
#ifdef CONFIG_OF_FLAT_TREE
void
ft_cpu_setup(void *blob, bd_t *bd)
#ifdef CONFIG_OF_LIBFDT
static void do_fixup(void *fdt, const char *node, const char *prop,
const void *val, int len, int create)
{
u32 *p;
int len;
#if defined(DEBUG)
int i;
debug("Updating property '%s/%s' = ", node, prop);
for (i = 0; i < len; i++)
debug(" %.2x", *(u8*)(val+i));
debug("\n");
#endif
int rc = fdt_find_and_setprop(fdt, node, prop, val, len, create);
if (rc)
printf("Unable to update property %s:%s, err=%s\n",
node, prop, fdt_strerror(rc));
}
/* Core XLB bus frequency */
p = ft_get_prop(blob, "/cpus/" OF_CPU "/bus-frequency", &len);
if (p != NULL)
*p = cpu_to_be32(bd->bi_busfreq);
static void do_fixup_u32(void *fdt, const char *node, const char *prop,
u32 val, int create)
{
val = cpu_to_fdt32(val);
do_fixup(fdt, node, prop, &val, sizeof(val), create);
}
/* SOC peripherals use the IPB bus frequency */
p = ft_get_prop(blob, "/" OF_SOC "/bus-frequency", &len);
if (p != NULL)
*p = cpu_to_be32(bd->bi_ipbfreq);
void ft_cpu_setup(void *blob, bd_t *bd)
{
int div = in_8((void*)CFG_MBAR + 0x204) & 0x0020 ? 8 : 4;
char * cpu_path = "/cpus/" OF_CPU;
char * eth_path = "/" OF_SOC "/ethernet@3000";
p = ft_get_prop(blob, "/" OF_SOC "/ethernet@3000/mac-address", &len);
if (p != NULL)
memcpy(p, bd->bi_enetaddr, 6);
p = ft_get_prop(blob, "/" OF_SOC "/ethernet@3000/local-mac-address", &len);
if (p != NULL)
memcpy(p, bd->bi_enetaddr, 6);
do_fixup_u32(blob, cpu_path, "timebase-frequency", OF_TBCLK, 1);
do_fixup_u32(blob, cpu_path, "bus-frequency", bd->bi_busfreq, 1);
do_fixup_u32(blob, cpu_path, "clock-frequency", bd->bi_intfreq, 1);
do_fixup_u32(blob, "/" OF_SOC, "bus-frequency", bd->bi_ipbfreq, 1);
do_fixup_u32(blob, "/" OF_SOC, "system-frequency",
bd->bi_busfreq*div, 1);
do_fixup(blob, eth_path, "mac-address", bd->bi_enetaddr, 6, 0);
do_fixup(blob, eth_path, "local-mac-address", bd->bi_enetaddr, 6, 0);
}
#endif

3
cpu/mpc86xx/cpu_init.c
View File

@ -29,6 +29,8 @@
#include <common.h>
#include <mpc86xx.h>
DECLARE_GLOBAL_DATA_PTR;
/*
* Breathe some life into the CPU...
*
@ -38,7 +40,6 @@
void cpu_init_f(void)
{
DECLARE_GLOBAL_DATA_PTR;
volatile immap_t *immap = (immap_t *)CFG_IMMR;
volatile ccsr_lbc_t *memctl = &immap->im_lbc;

30
cpu/mpc86xx/spd_sdram.c
View File

@ -948,19 +948,25 @@ unsigned int enable_ddr(unsigned int ddr_num)
* Read both dimm slots and decide whether
* or not to enable this controller.
*/
memset((void *)&spd1,0,sizeof(spd1));
memset((void *)&spd2,0,sizeof(spd2));
memset((void *)&spd1, 0, sizeof(spd1));
memset((void *)&spd2, 0, sizeof(spd2));
if (ddr_num == 1) {
CFG_READ_SPD(SPD_EEPROM_ADDRESS1,
0, 1, (uchar *) &spd1, sizeof(spd1));
#if defined(SPD_EEPROM_ADDRESS2)
CFG_READ_SPD(SPD_EEPROM_ADDRESS2,
0, 1, (uchar *) &spd2, sizeof(spd2));
#endif
} else {
#if defined(SPD_EEPROM_ADDRESS3)
CFG_READ_SPD(SPD_EEPROM_ADDRESS3,
0, 1, (uchar *) &spd1, sizeof(spd1));
#endif
#if defined(SPD_EEPROM_ADDRESS4)
CFG_READ_SPD(SPD_EEPROM_ADDRESS4,
0, 1, (uchar *) &spd2, sizeof(spd2));
#endif
}
/*
@ -1105,21 +1111,25 @@ spd_sdram(void)
{
int memsize_ddr1_dimm1 = 0;
int memsize_ddr1_dimm2 = 0;
int memsize_ddr1 = 0;
unsigned int law_size_ddr1;
volatile immap_t *immap = (immap_t *)CFG_IMMR;
volatile ccsr_ddr_t *ddr1 = &immap->im_ddr1;
volatile ccsr_local_mcm_t *mcm = &immap->im_local_mcm;
#if (CONFIG_NUM_DDR_CONTROLLERS > 1)
int memsize_ddr2_dimm1 = 0;
int memsize_ddr2_dimm2 = 0;
int memsize_total = 0;
int memsize_ddr1 = 0;
int memsize_ddr2 = 0;
unsigned int law_size_ddr2;
#endif
unsigned int ddr1_enabled = 0;
unsigned int ddr2_enabled = 0;
unsigned int law_size_ddr1;
unsigned int law_size_ddr2;
volatile immap_t *immap = (immap_t *)CFG_IMMR;
volatile ccsr_local_mcm_t *mcm = &immap->im_local_mcm;
int memsize_total = 0;
#ifdef CONFIG_DDR_INTERLEAVE
unsigned int law_size_interleaved;
volatile ccsr_ddr_t *ddr1 = &immap->im_ddr1;
volatile ccsr_ddr_t *ddr2 = &immap->im_ddr2;
memsize_ddr1_dimm1 = spd_init(SPD_EEPROM_ADDRESS1,
@ -1194,9 +1204,11 @@ spd_sdram(void)
(unsigned int)memsize_total * 1024*1024);
memsize_total += memsize_ddr1_dimm1;
#if defined(SPD_EEPROM_ADDRESS2)
memsize_ddr1_dimm2 = spd_init(SPD_EEPROM_ADDRESS2,
1, 2,
(unsigned int)memsize_total * 1024*1024);
#endif
memsize_total += memsize_ddr1_dimm2;
/*

2
cpu/mpc86xx/speed.c
View File

@ -29,6 +29,7 @@
#include <mpc86xx.h>
#include <asm/processor.h>
DECLARE_GLOBAL_DATA_PTR;
void get_sys_info(sys_info_t *sysInfo)
{
@ -96,7 +97,6 @@ void get_sys_info(sys_info_t *sysInfo)
int get_clocks(void)
{
DECLARE_GLOBAL_DATA_PTR;
sys_info_t sys_info;
get_sys_info(&sys_info);

4
cpu/mpc86xx/traps.c
View File

@ -34,6 +34,8 @@
#include <command.h>
#include <asm/processor.h>
DECLARE_GLOBAL_DATA_PTR;
#if defined(CONFIG_CMD_KGDB)
int (*debugger_exception_handler)(struct pt_regs *) = 0;
#endif
@ -50,8 +52,6 @@ extern unsigned long search_exception_table(unsigned long);
void
print_backtrace(unsigned long *sp)
{
DECLARE_GLOBAL_DATA_PTR;
int cnt = 0;
unsigned long i;

17
cpu/ppc4xx/405gp_pci.c
View File

@ -443,7 +443,7 @@ void pci_init_board(void)
static struct pci_controller ppc440_hose = {0};
void pci_440_init (struct pci_controller *hose)
int pci_440_init (struct pci_controller *hose)
{
int reg_num = 0;
@ -459,7 +459,7 @@ void pci_440_init (struct pci_controller *hose)
if ((strap & SDR0_SDSTP1_PISE_MASK) == 0) {
printf("PCI: SDR0_STRP1[PISE] not set.\n");
printf("PCI: Configuration aborted.\n");
return;
return -1;
}
#elif defined(CONFIG_440GP)
unsigned long strap;
@ -468,7 +468,7 @@ void pci_440_init (struct pci_controller *hose)
if ((strap & CPC0_STRP1_PISE_MASK) == 0) {
printf("PCI: CPC0_STRP1[PISE] not set.\n");
printf("PCI: Configuration aborted.\n");
return;
return -1;
}
#endif
#endif /* CONFIG_DISABLE_PISE_TEST */
@ -477,7 +477,7 @@ void pci_440_init (struct pci_controller *hose)
* PCI controller init
*--------------------------------------------------------------------------*/
hose->first_busno = 0;
hose->last_busno = 0xff;
hose->last_busno = 0;
/* PCI I/O space */
pci_set_region(hose->regions + reg_num++,
@ -515,7 +515,7 @@ void pci_440_init (struct pci_controller *hose)
if (pci_pre_init (hose) == 0) {
printf("PCI: Board-specific initialization failed.\n");
printf("PCI: Configuration aborted.\n");
return;
return -1;
}
pci_register_hose( hose );
@ -578,13 +578,16 @@ void pci_440_init (struct pci_controller *hose)
#endif
hose->last_busno = pci_hose_scan(hose);
}
return hose->last_busno;
}
void pci_init_board(void)
{
pci_440_init (&ppc440_hose);
int busno;
busno = pci_440_init (&ppc440_hose);
#if defined(CONFIG_440SPE)
pcie_setup_hoses();
pcie_setup_hoses(busno + 1);
#endif
}

160
cpu/ppc4xx/440spe_pcie.c
View File

@ -40,73 +40,126 @@ enum {
LNKW_X8 = 0x8
};
static inline int pcie_in_8(const volatile unsigned char __iomem *addr)
static u8* pcie_get_base(struct pci_controller *hose, unsigned int devfn)
{
int ret;
u8 *base = (u8*)hose->cfg_data;
PCIE_IN(lbzx, ret, addr);
/* use local configuration space for the first bus */
if (PCI_BUS(devfn) == 0) {
if (hose->cfg_data == (u8*)CFG_PCIE0_CFGBASE)
base = (u8*)CFG_PCIE0_XCFGBASE;
if (hose->cfg_data == (u8*)CFG_PCIE1_CFGBASE)
base = (u8*)CFG_PCIE1_XCFGBASE;
if (hose->cfg_data == (u8*)CFG_PCIE2_CFGBASE)
base = (u8*)CFG_PCIE2_XCFGBASE;
}
return ret;
return base;
}
static inline int pcie_in_le16(const volatile unsigned short __iomem *addr)
static void pcie_dmer_disable(void)
{
int ret;
PCIE_IN(lhbrx, ret, addr)
return ret;
mtdcr (DCRN_PEGPL_CFG(DCRN_PCIE0_BASE),
mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE0_BASE)) | GPL_DMER_MASK_DISA);
mtdcr (DCRN_PEGPL_CFG(DCRN_PCIE1_BASE),
mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE1_BASE)) | GPL_DMER_MASK_DISA);
mtdcr (DCRN_PEGPL_CFG(DCRN_PCIE2_BASE),
mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE2_BASE)) | GPL_DMER_MASK_DISA);
}
static inline unsigned pcie_in_le32(const volatile unsigned __iomem *addr)
static void pcie_dmer_enable(void)
{
unsigned ret;
PCIE_IN(lwbrx, ret, addr);
return ret;
mtdcr (DCRN_PEGPL_CFG (DCRN_PCIE0_BASE),
mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE0_BASE)) & ~GPL_DMER_MASK_DISA);
mtdcr (DCRN_PEGPL_CFG (DCRN_PCIE1_BASE),
mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE1_BASE)) & ~GPL_DMER_MASK_DISA);
mtdcr (DCRN_PEGPL_CFG (DCRN_PCIE2_BASE),
mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE2_BASE)) & ~GPL_DMER_MASK_DISA);
}
static int pcie_read_config(struct pci_controller *hose, unsigned int devfn,
int offset, int len, u32 *val) {
u8 *address;
*val = 0;
/*
* 440SPE implements only one function per port
* Bus numbers are relative to hose->first_busno
*/
if (!((PCI_FUNC(devfn) == 0) && (PCI_DEV(devfn) == 1)))
devfn -= PCI_BDF(hose->first_busno, 0, 0);
/*
* NOTICE: configuration space ranges are currenlty mapped only for
* the first 16 buses, so such limit must be imposed. In case more
* buses are required the TLB settings in board/amcc/<board>/init.S
* need to be altered accordingly (one bus takes 1 MB of memory space).
*/
if (PCI_BUS(devfn) >= 16)
return 0;
devfn = PCI_BDF(0,0,0);
/*
* Only single device/single function is supported for the primary and
* secondary buses of the 440SPe host bridge.
*/
if ((!((PCI_FUNC(devfn) == 0) && (PCI_DEV(devfn) == 0))) &&
((PCI_BUS(devfn) == 0) || (PCI_BUS(devfn) == 1)))
return 0;
address = pcie_get_base(hose, devfn);
offset += devfn << 4;
/*
* Reading from configuration space of non-existing device can
* generate transaction errors. For the read duration we suppress
* assertion of machine check exceptions to avoid those.
*/
pcie_dmer_disable ();
switch (len) {
case 1:
*val = pcie_in_8(hose->cfg_data + offset);
*val = in_8(hose->cfg_data + offset);
break;
case 2:
*val = pcie_in_le16((u16 *)(hose->cfg_data + offset));
*val = in_le16((u16 *)(hose->cfg_data + offset));
break;
default:
*val = pcie_in_le32((u32*)(hose->cfg_data + offset));
*val = in_le32((u32*)(hose->cfg_data + offset));
break;
}
pcie_dmer_enable ();
return 0;
}
static int pcie_write_config(struct pci_controller *hose, unsigned int devfn,
int offset, int len, u32 val) {
u8 *address;
/*
* 440SPE implements only one function per port
* Bus numbers are relative to hose->first_busno
*/
if (!((PCI_FUNC(devfn) == 0) && (PCI_DEV(devfn) == 1)))
devfn -= PCI_BDF(hose->first_busno, 0, 0);
/*
* Same constraints as in pcie_read_config().
*/
if (PCI_BUS(devfn) >= 16)
return 0;
devfn = PCI_BDF(0,0,0);
if ((!((PCI_FUNC(devfn) == 0) && (PCI_DEV(devfn) == 0))) &&
((PCI_BUS(devfn) == 0) || (PCI_BUS(devfn) == 1)))
return 0;
address = pcie_get_base(hose, devfn);
offset += devfn << 4;
/*
* Suppress MCK exceptions, similar to pcie_read_config()
*/
pcie_dmer_disable ();
switch (len) {
case 1:
out_8(hose->cfg_data + offset, val);
@ -118,6 +171,9 @@ static int pcie_write_config(struct pci_controller *hose, unsigned int devfn,
out_le32((u32 *)(hose->cfg_data + offset), val);
break;
}
pcie_dmer_enable ();
return 0;
}
@ -126,7 +182,7 @@ int pcie_read_config_byte(struct pci_controller *hose,pci_dev_t dev,int offset,u
u32 v;
int rv;
rv = pcie_read_config(hose, dev, offset, 1, &v);
rv = pcie_read_config(hose, dev, offset, 1, &v);
*val = (u8)v;
return rv;
}
@ -783,12 +839,12 @@ void ppc440spe_setup_pcie_rootpoint(struct pci_controller *hose, int port)
volatile void *rmbase = NULL;
pci_set_ops(hose,
pcie_read_config_byte,
pcie_read_config_word,
pcie_read_config_dword,
pcie_write_config_byte,
pcie_write_config_word,
pcie_write_config_dword);
pcie_read_config_byte,
pcie_read_config_word,
pcie_read_config_dword,
pcie_write_config_byte,
pcie_write_config_word,
pcie_write_config_dword);
switch (port) {
case 0:
@ -811,14 +867,9 @@ void ppc440spe_setup_pcie_rootpoint(struct pci_controller *hose, int port)
/*
* Set bus numbers on our root port
*/
if (ppc440spe_revB()) {
out_8((u8 *)mbase + PCI_PRIMARY_BUS, 0);
out_8((u8 *)mbase + PCI_SECONDARY_BUS, 1);
out_8((u8 *)mbase + PCI_SUBORDINATE_BUS, 1);
} else {
out_8((u8 *)mbase + PCI_PRIMARY_BUS, 0);
out_8((u8 *)mbase + PCI_SECONDARY_BUS, 0);
}
out_8((u8 *)mbase + PCI_PRIMARY_BUS, 0);
out_8((u8 *)mbase + PCI_SECONDARY_BUS, 1);
out_8((u8 *)mbase + PCI_SUBORDINATE_BUS, 1);
/*
* Set up outbound translation to hose->mem_space from PLB
@ -875,6 +926,29 @@ void ppc440spe_setup_pcie_rootpoint(struct pci_controller *hose, int port)
in_le16((u16 *)(mbase + PCI_COMMAND)) |
PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
printf("PCIE:%d successfully set as rootpoint\n",port);
/* Set Device and Vendor Id */
switch (port) {
case 0:
out_le16(mbase + 0x200, 0xaaa0);
out_le16(mbase + 0x202, 0xbed0);
break;
case 1:
out_le16(mbase + 0x200, 0xaaa1);
out_le16(mbase + 0x202, 0xbed1);
break;
case 2:
out_le16(mbase + 0x200, 0xaaa2);
out_le16(mbase + 0x202, 0xbed2);
break;
default:
out_le16(mbase + 0x200, 0xaaa3);
out_le16(mbase + 0x202, 0xbed3);
}
/* Set Class Code to PCI-PCI bridge and Revision Id to 1 */
out_le32(mbase + 0x208, 0x06040001);
}
int ppc440spe_setup_pcie_endpoint(struct pci_controller *hose, int port)
@ -952,8 +1026,8 @@ int ppc440spe_setup_pcie_endpoint(struct pci_controller *hose, int port)
/* Enable I/O, Mem, and Busmaster cycles */
out_le16((u16 *)(mbase + PCI_COMMAND),
in_le16((u16 *)(mbase + PCI_COMMAND)) |
PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
in_le16((u16 *)(mbase + PCI_COMMAND)) |
PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
out_le16(mbase + 0x200,0xcaad); /* Setting vendor ID */
out_le16(mbase + 0x202,0xfeed); /* Setting device ID */
attempts = 10;

16
cpu/ppc4xx/440spe_pcie.h
View File

@ -38,6 +38,7 @@
#define DCRN_PEGPL_REGBAL(base) (base + 0x13)
#define DCRN_PEGPL_REGMSK(base) (base + 0x14)
#define DCRN_PEGPL_SPECIAL(base) (base + 0x15)
#define DCRN_PEGPL_CFG(base) (base + 0x16)
/*
* System DCRs (SDRs)
@ -161,20 +162,7 @@
mtdcr(DCRN_SDR0_CFGADDR, offset); \
mtdcr(DCRN_SDR0_CFGDATA,data);})
#define PCIE_IN(opcode, ret, addr) \
__asm__ __volatile__( \
"sync\n" \
#opcode " %0,0,%1\n" \
"1: twi 0,%0,0\n" \
"isync\n" \
"b 3f\n" \
"2: li %0,-1\n" \
"3:\n" \
".section __ex_table,\"a\"\n" \
".balign 4\n" \
".long 1b,2b\n" \
".previous\n" \
: "=r" (ret) : "r" (addr), "m" (*addr));
#define GPL_DMER_MASK_DISA 0x02000000
int ppc440spe_init_pcie(void);
int ppc440spe_init_pcie_rootport(int port);

16
cpu/ppc4xx/4xx_enet.c
View File

@ -138,7 +138,8 @@
#define BI_PHYMODE_MII 7
#endif
#if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
#if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || \
defined(CONFIG_440GRX) || defined(CONFIG_440SP)
#define SDR0_MFR_ETH_CLK_SEL_V(n) ((0x01<<27) / (n+1))
#endif
@ -408,7 +409,8 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
int ethgroup = -1;
#endif
#endif
#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || defined(CONFIG_440SPE)
#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
defined(CONFIG_440SP) || defined(CONFIG_440SPE)
unsigned long mfr;
#endif
@ -500,7 +502,8 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
__asm__ volatile ("eieio");
/* reset emac so we have access to the phy */
#if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
defined(CONFIG_440SP) || defined(CONFIG_440SPE)
/* provide clocks for EMAC internal loopback */
mfsdr (sdr_mfr, mfr);
mfr |= SDR0_MFR_ETH_CLK_SEL_V(devnum);
@ -518,7 +521,8 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
if (failsafe <= 0)
printf("\nProblem resetting EMAC!\n");
#if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
defined(CONFIG_440SP) || defined(CONFIG_440SPE)
/* remove clocks for EMAC internal loopback */
mfsdr (sdr_mfr, mfr);
mfr &= ~SDR0_MFR_ETH_CLK_SEL_V(devnum);
@ -920,8 +924,8 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
/* set speed */
if (speed == _1000BASET) {
#if defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
defined(CONFIG_440SP) || defined(CONFIG_440SPE)
unsigned long pfc1;
mfsdr (sdr_pfc1, pfc1);

6
cpu/ppc4xx/traps.c
View File

@ -151,12 +151,6 @@ MachineCheckException(struct pt_regs *regs)
int uncorr_ecc = 0;
#endif
/* Probing PCI(E) using config cycles may cause this exception
* when a device is not present. To gracefully recover in such
* scenarios config read/write routines need to be instrumented in
* order to return via fixup handler. For examples refer to
* pcie_in_8(), pcie_in_le16() and pcie_in_le32()
*/
if ((fixup = search_exception_table(regs->nip)) != 0) {
regs->nip = fixup;
val = mfspr(MCSR);

6
cpu/pxa/mmc.c
View File

@ -438,11 +438,11 @@ mmc_init(int verbose)
/* FIXME fill in the correct size (is set to 32MByte) */
mmc_dev.blksz = 512;
mmc_dev.lba = 0x10000;
sprintf(mmc_dev.vendor,"Man %02x%02x%02x Snr %02x%02x%02x",
sprintf((char*)mmc_dev.vendor,"Man %02x%02x%02x Snr %02x%02x%02x",
cid->id[0], cid->id[1], cid->id[2],
cid->sn[0], cid->sn[1], cid->sn[2]);
sprintf(mmc_dev.product,"%s",cid->name);
sprintf(mmc_dev.revision,"%x %x",cid->hwrev, cid->fwrev);
sprintf((char*)mmc_dev.product,"%s",cid->name);
sprintf((char*)mmc_dev.revision,"%x %x",cid->hwrev, cid->fwrev);
mmc_dev.removable = 0;
mmc_dev.block_read = mmc_bread;

345
cpu/pxa/serial.c
View File

@ -30,11 +30,28 @@
#include <common.h>
#include <watchdog.h>
#include <serial.h>
#include <asm/arch/pxa-regs.h>
DECLARE_GLOBAL_DATA_PTR;
void serial_setbrg (void)
#define FFUART 0
#define BTUART 1
#define STUART 2
#ifndef CONFIG_SERIAL_MULTI
#if defined (CONFIG_FFUART)
#define UART_INDEX FFUART
#elif defined (CONFIG_BTUART)
#define UART_INDEX BTUART
#elif defined (CONFIG_STUART)
#define UART_INDEX STUART
#else
#error "Bad: you didn't configure serial ..."
#endif
#endif
void pxa_setbrg_dev (unsigned int uart_index)
{
unsigned int quot = 0;
@ -53,63 +70,68 @@ void serial_setbrg (void)
else
hang ();
#ifdef CONFIG_FFUART
switch (uart_index) {
case FFUART:
#ifdef CONFIG_CPU_MONAHANS
CKENA |= CKENA_22_FFUART;
CKENA |= CKENA_22_FFUART;
#else
CKEN |= CKEN6_FFUART;
CKEN |= CKEN6_FFUART;
#endif /* CONFIG_CPU_MONAHANS */
FFIER = 0; /* Disable for now */
FFFCR = 0; /* No fifos enabled */
FFIER = 0; /* Disable for now */
FFFCR = 0; /* No fifos enabled */
/* set baud rate */
FFLCR = LCR_WLS0 | LCR_WLS1 | LCR_DLAB;
FFDLL = quot & 0xff;
FFDLH = quot >> 8;
FFLCR = LCR_WLS0 | LCR_WLS1;
/* set baud rate */
FFLCR = LCR_WLS0 | LCR_WLS1 | LCR_DLAB;
FFDLL = quot & 0xff;
FFDLH = quot >> 8;
FFLCR = LCR_WLS0 | LCR_WLS1;
FFIER = IER_UUE; /* Enable FFUART */
FFIER = IER_UUE; /* Enable FFUART */
break;
#elif defined(CONFIG_BTUART)
case BTUART:
#ifdef CONFIG_CPU_MONAHANS
CKENA |= CKENA_21_BTUART;
CKENA |= CKENA_21_BTUART;
#else
CKEN |= CKEN7_BTUART;
CKEN |= CKEN7_BTUART;
#endif /* CONFIG_CPU_MONAHANS */
BTIER = 0;
BTFCR = 0;
BTIER = 0;
BTFCR = 0;
/* set baud rate */
BTLCR = LCR_DLAB;
BTDLL = quot & 0xff;
BTDLH = quot >> 8;
BTLCR = LCR_WLS0 | LCR_WLS1;
/* set baud rate */
BTLCR = LCR_DLAB;
BTDLL = quot & 0xff;
BTDLH = quot >> 8;
BTLCR = LCR_WLS0 | LCR_WLS1;
BTIER = IER_UUE; /* Enable BFUART */
BTIER = IER_UUE; /* Enable BFUART */
#elif defined(CONFIG_STUART)
break;
case STUART:
#ifdef CONFIG_CPU_MONAHANS
CKENA |= CKENA_23_STUART;
CKENA |= CKENA_23_STUART;
#else
CKEN |= CKEN5_STUART;
CKEN |= CKEN5_STUART;
#endif /* CONFIG_CPU_MONAHANS */
STIER = 0;
STFCR = 0;
STIER = 0;
STFCR = 0;
/* set baud rate */
STLCR = LCR_DLAB;
STDLL = quot & 0xff;
STDLH = quot >> 8;
STLCR = LCR_WLS0 | LCR_WLS1;
/* set baud rate */
STLCR = LCR_DLAB;
STDLL = quot & 0xff;
STDLH = quot >> 8;
STLCR = LCR_WLS0 | LCR_WLS1;
STIER = IER_UUE; /* Enable STUART */
STIER = IER_UUE; /* Enable STUART */
break;
#else
#error "Bad: you didn't configure serial ..."
#endif
default:
hang();
}
}
@ -118,9 +140,9 @@ void serial_setbrg (void)
* are always 8 data bits, no parity, 1 stop bit, no start bits.
*
*/
int serial_init (void)
int pxa_init_dev (unsigned int uart_index)
{
serial_setbrg ();
pxa_setbrg_dev (uart_index);
return (0);
}
@ -129,26 +151,32 @@ int serial_init (void)
/*
* Output a single byte to the serial port.
*/
void serial_putc (const char c)
void pxa_putc_dev (unsigned int uart_index,const char c)
{
#ifdef CONFIG_FFUART
/* wait for room in the tx FIFO on FFUART */
while ((FFLSR & LSR_TEMT) == 0)
WATCHDOG_RESET (); /* Reset HW Watchdog, if needed */
FFTHR = c;
#elif defined(CONFIG_BTUART)
while ((BTLSR & LSR_TEMT ) == 0 )
WATCHDOG_RESET (); /* Reset HW Watchdog, if needed */
BTTHR = c;
#elif defined(CONFIG_STUART)
while ((STLSR & LSR_TEMT ) == 0 )
WATCHDOG_RESET (); /* Reset HW Watchdog, if needed */
STTHR = c;
#endif
switch (uart_index) {
case FFUART:
/* wait for room in the tx FIFO on FFUART */
while ((FFLSR & LSR_TEMT) == 0)
WATCHDOG_RESET (); /* Reset HW Watchdog, if needed */
FFTHR = c;
break;
case BTUART:
while ((BTLSR & LSR_TEMT ) == 0 )
WATCHDOG_RESET (); /* Reset HW Watchdog, if needed */
BTTHR = c;
break;
case STUART:
while ((STLSR & LSR_TEMT ) == 0 )
WATCHDOG_RESET (); /* Reset HW Watchdog, if needed */
STTHR = c;
break;
}
/* If \n, also do \r */
if (c == '\n')
serial_putc ('\r');
pxa_putc_dev (uart_index,'\r');
}
/*
@ -156,15 +184,17 @@ void serial_putc (const char c)
* otherwise. When the function is succesfull, the character read is
* written into its argument c.
*/
int serial_tstc (void)
int pxa_tstc_dev (unsigned int uart_index)
{
#ifdef CONFIG_FFUART
return FFLSR & LSR_DR;
#elif defined(CONFIG_BTUART)
return BTLSR & LSR_DR;
#elif defined(CONFIG_STUART)
return STLSR & LSR_DR;
#endif
switch (uart_index) {
case FFUART:
return FFLSR & LSR_DR;
case BTUART:
return BTLSR & LSR_DR;
case STUART:
return STLSR & LSR_DR;
}
return -1;
}
/*
@ -172,27 +202,184 @@ int serial_tstc (void)
* otherwise. When the function is succesfull, the character read is
* written into its argument c.
*/
int serial_getc (void)
int pxa_getc_dev (unsigned int uart_index)
{
#ifdef CONFIG_FFUART
while (!(FFLSR & LSR_DR))
WATCHDOG_RESET (); /* Reset HW Watchdog, if needed */
return (char) FFRBR & 0xff;
#elif defined(CONFIG_BTUART)
while (!(BTLSR & LSR_DR))
WATCHDOG_RESET (); /* Reset HW Watchdog, if needed */
return (char) BTRBR & 0xff;
#elif defined(CONFIG_STUART)
while (!(STLSR & LSR_DR))
WATCHDOG_RESET (); /* Reset HW Watchdog, if needed */
return (char) STRBR & 0xff;
#endif
switch (uart_index) {
case FFUART:
while (!(FFLSR & LSR_DR))
WATCHDOG_RESET (); /* Reset HW Watchdog, if needed */
return (char) FFRBR & 0xff;
case BTUART:
while (!(BTLSR & LSR_DR))
WATCHDOG_RESET (); /* Reset HW Watchdog, if needed */
return (char) BTRBR & 0xff;
case STUART:
while (!(STLSR & LSR_DR))
WATCHDOG_RESET (); /* Reset HW Watchdog, if needed */
return (char) STRBR & 0xff;
}
return -1;
}
void
serial_puts (const char *s)
pxa_puts_dev (unsigned int uart_index,const char *s)
{
while (*s) {
serial_putc (*s++);
pxa_putc_dev (uart_index,*s++);
}
}
#if defined (CONFIG_FFUART)
static int ffuart_init(void)
{
return pxa_init_dev(FFUART);
}
static void ffuart_setbrg(void)
{
return pxa_setbrg_dev(FFUART);
}
static void ffuart_putc(const char c)
{
return pxa_putc_dev(FFUART,c);
}
static void ffuart_puts(const char *s)
{
return pxa_puts_dev(FFUART,s);
}
static int ffuart_getc(void)
{
return pxa_getc_dev(FFUART);
}
static int ffuart_tstc(void)
{
return pxa_tstc_dev(FFUART);
}
struct serial_device serial_ffuart_device =
{
"serial_ffuart",
"PXA",
ffuart_init,
ffuart_setbrg,
ffuart_getc,
ffuart_tstc,
ffuart_putc,
ffuart_puts,
};
#endif
#if defined (CONFIG_BTUART)
static int btuart_init(void)
{
return pxa_init_dev(BTUART);
}
static void btuart_setbrg(void)
{
return pxa_setbrg_dev(BTUART);
}
static void btuart_putc(const char c)
{
return pxa_putc_dev(BTUART,c);
}
static void btuart_puts(const char *s)
{
return pxa_puts_dev(BTUART,s);
}
static int btuart_getc(void)
{
return pxa_getc_dev(BTUART);
}
static int btuart_tstc(void)
{
return pxa_tstc_dev(BTUART);
}
struct serial_device serial_btuart_device =
{
"serial_btuart",
"PXA",
btuart_init,
btuart_setbrg,
btuart_getc,
btuart_tstc,
btuart_putc,
btuart_puts,
};
#endif
#if defined (CONFIG_STUART)
static int stuart_init(void)
{
return pxa_init_dev(STUART);
}
static void stuart_setbrg(void)
{
return pxa_setbrg_dev(STUART);
}
static void stuart_putc(const char c)
{
return pxa_putc_dev(STUART,c);
}
static void stuart_puts(const char *s)
{
return pxa_puts_dev(STUART,s);
}
static int stuart_getc(void)
{
return pxa_getc_dev(STUART);
}
static int stuart_tstc(void)
{
return pxa_tstc_dev(STUART);
}
struct serial_device serial_stuart_device =
{
"serial_stuart",
"PXA",
stuart_init,
stuart_setbrg,
stuart_getc,
stuart_tstc,
stuart_putc,
stuart_puts,
};
#endif
#ifndef CONFIG_SERIAL_MULTI
inline int serial_init(void) {
return (pxa_init_dev(UART_INDEX));
}
void serial_setbrg(void) {
pxa_setbrg_dev(UART_INDEX);
}
int serial_getc(void) {
return(pxa_getc_dev(UART_INDEX));
}
int serial_tstc(void) {
return(pxa_tstc_dev(UART_INDEX));
}
void serial_putc(const char c) {
pxa_putc_dev(UART_INDEX,c);
}
void serial_puts(const char *s) {
pxa_puts_dev(UART_INDEX,s);
}
#endif /* CONFIG_SERIAL_MULTI */

16
cpu/pxa/usb.c
View File

@ -67,6 +67,22 @@ int usb_cpu_init()
int usb_cpu_stop()
{
UHCHR |= UHCHR_FHR;
udelay(11);
UHCHR &= ~UHCHR_FHR;
UHCCOMS |= 1;
udelay(10);
#if defined(CONFIG_CPU_MONAHANS)
UHCHR |= UHCHR_SSEP0;
#endif
#if defined(CONFIG_PXA27X)
UHCHR |= UHCHR_SSEP2;
#endif
UHCHR |= UHCHR_SSEP1;
UHCHR |= UHCHR_SSE;
return 0;
}

2
drivers/Makefile
View File

@ -43,7 +43,7 @@ COBJS = 3c589.o 5701rls.o ali512x.o at45.o ata_piix.o atmel_usart.o \
sed13806.o sed156x.o \
serial.o serial_max3100.o \
serial_pl010.o serial_pl011.o serial_xuartlite.o \
sl811_usb.o sm501.o smc91111.o smiLynxEM.o \
sil680.o sl811_usb.o sm501.o smc91111.o smiLynxEM.o \
status_led.o sym53c8xx.o systemace.o ahci.o \
ti_pci1410a.o tigon3.o tsec.o \
tsi108_eth.o tsi108_i2c.o tsi108_pci.o \

316
drivers/at45.c Executable file → Normal file
View File

@ -27,33 +27,31 @@
/*
* spi.c API
*/
extern unsigned int AT91F_SpiWrite (AT91PS_DataflashDesc pDesc);
extern void AT91F_SpiEnable(int cs);
extern unsigned int AT91F_SpiWrite(AT91PS_DataflashDesc pDesc);
extern void AT91F_SpiEnable(int cs);
#define AT91C_TIMEOUT_WRDY 200000
/*----------------------------------------------------------------------*/
/* \fn AT91F_DataFlashSendCommand */
/* \brief Generic function to send a command to the dataflash */
/*----------------------------------------------------------------------*/
AT91S_DataFlashStatus AT91F_DataFlashSendCommand(
AT91PS_DataFlash pDataFlash,
unsigned char OpCode,
unsigned int CmdSize,
unsigned int DataflashAddress)
AT91S_DataFlashStatus AT91F_DataFlashSendCommand(AT91PS_DataFlash pDataFlash,
unsigned char OpCode,
unsigned int CmdSize,
unsigned int DataflashAddress)
{
unsigned int adr;
if ( (pDataFlash->pDataFlashDesc->state) != IDLE)
if ((pDataFlash->pDataFlashDesc->state) != IDLE)
return DATAFLASH_BUSY;
/* process the address to obtain page address and byte address */
adr = ((DataflashAddress / (pDataFlash->pDevice->pages_size)) <<
pDataFlash->pDevice->page_offset) + (DataflashAddress %
(pDataFlash->pDevice->pages_size));
pDataFlash->pDevice->page_offset) +
(DataflashAddress % (pDataFlash->pDevice->pages_size));
/* fill the command buffer */
/* fill the command buffer */
pDataFlash->pDataFlashDesc->command[0] = OpCode;
if (pDataFlash->pDevice->pages_number >= 16384) {
pDataFlash->pDataFlashDesc->command[1] =
@ -78,16 +76,16 @@ AT91S_DataFlashStatus AT91F_DataFlashSendCommand(
pDataFlash->pDataFlashDesc->command[7] = 0;
/* Initialize the SpiData structure for the spi write fuction */
pDataFlash->pDataFlashDesc->tx_cmd_pt =
pDataFlash->pDataFlashDesc->tx_cmd_pt =
pDataFlash->pDataFlashDesc->command;
pDataFlash->pDataFlashDesc->tx_cmd_size = CmdSize;
pDataFlash->pDataFlashDesc->rx_cmd_pt =
pDataFlash->pDataFlashDesc->tx_cmd_size = CmdSize;
pDataFlash->pDataFlashDesc->rx_cmd_pt =
pDataFlash->pDataFlashDesc->command;
pDataFlash->pDataFlashDesc->rx_cmd_size = CmdSize;
pDataFlash->pDataFlashDesc->rx_cmd_size = CmdSize;
/* send the command and read the data */
return AT91F_SpiWrite (pDataFlash->pDataFlashDesc); }
return AT91F_SpiWrite(pDataFlash->pDataFlashDesc);
}
/*----------------------------------------------------------------------*/
/* \fn AT91F_DataFlashGetStatus */
@ -98,50 +96,49 @@ AT91S_DataFlashStatus AT91F_DataFlashGetStatus(AT91PS_DataflashDesc pDesc)
AT91S_DataFlashStatus status;
/* if a transfert is in progress ==> return 0 */
if( (pDesc->state) != IDLE)
if ((pDesc->state) != IDLE)
return DATAFLASH_BUSY;
/* first send the read status command (D7H) */
pDesc->command[0] = DB_STATUS;
pDesc->command[1] = 0;
pDesc->DataFlash_state = GET_STATUS;
pDesc->tx_data_size = 0; /* Transmit the command */
/* and receive response */
pDesc->tx_cmd_pt = pDesc->command;
pDesc->rx_cmd_pt = pDesc->command;
pDesc->rx_cmd_size = 2;
pDesc->tx_cmd_size = 2;
status = AT91F_SpiWrite (pDesc);
pDesc->DataFlash_state = GET_STATUS;
pDesc->tx_data_size = 0; /* Transmit the command */
/* and receive response */
pDesc->tx_cmd_pt = pDesc->command;
pDesc->rx_cmd_pt = pDesc->command;
pDesc->rx_cmd_size = 2;
pDesc->tx_cmd_size = 2;
status = AT91F_SpiWrite(pDesc);
pDesc->DataFlash_state = *( (unsigned char *) (pDesc->rx_cmd_pt) +1);
pDesc->DataFlash_state = *((unsigned char *)(pDesc->rx_cmd_pt) + 1);
return status;
}
/*----------------------------------------------------------------------*/
/* \fn AT91F_DataFlashWaitReady */
/* \brief wait for dataflash ready (bit7 of the status register == 1) */
/*----------------------------------------------------------------------*/
AT91S_DataFlashStatus AT91F_DataFlashWaitReady(AT91PS_DataflashDesc
pDataFlashDesc, unsigned int timeout)
pDataFlashDesc,
unsigned int timeout)
{
pDataFlashDesc->DataFlash_state = IDLE;
do {
AT91F_DataFlashGetStatus(pDataFlashDesc);
timeout--;
} while( ((pDataFlashDesc->DataFlash_state & 0x80) != 0x80) &&
(timeout > 0) );
} while (((pDataFlashDesc->DataFlash_state & 0x80) != 0x80) &&
(timeout > 0));
if((pDataFlashDesc->DataFlash_state & 0x80) != 0x80)
if ((pDataFlashDesc->DataFlash_state & 0x80) != 0x80)
return DATAFLASH_ERROR;
return DATAFLASH_OK;
}
/*--------------------------------------------------------------------------*/
/* Function Name : AT91F_DataFlashContinuousRead */
/* Object : Continuous stream Read */
@ -151,17 +148,17 @@ pDataFlashDesc, unsigned int timeout)
/* : <sizeToRead> = data buffer size */
/* Return value : State of the dataflash */
/*--------------------------------------------------------------------------*/
AT91S_DataFlashStatus AT91F_DataFlashContinuousRead (
AT91PS_DataFlash pDataFlash,
int src,
unsigned char *dataBuffer,
int sizeToRead )
AT91S_DataFlashStatus AT91F_DataFlashContinuousRead(
AT91PS_DataFlash pDataFlash,
int src,
unsigned char *dataBuffer,
int sizeToRead)
{
AT91S_DataFlashStatus status;
/* Test the size to read in the device */
if ( (src + sizeToRead) >
(pDataFlash->pDevice->pages_size *
(pDataFlash->pDevice->pages_number)))
if ((src + sizeToRead) >
(pDataFlash->pDevice->pages_size *
(pDataFlash->pDevice->pages_number)))
return DATAFLASH_MEMORY_OVERFLOW;
pDataFlash->pDataFlashDesc->rx_data_pt = dataBuffer;
@ -169,13 +166,12 @@ AT91S_DataFlashStatus AT91F_DataFlashContinuousRead (
pDataFlash->pDataFlashDesc->tx_data_pt = dataBuffer;
pDataFlash->pDataFlashDesc->tx_data_size = sizeToRead;
status = AT91F_DataFlashSendCommand
(pDataFlash, DB_CONTINUOUS_ARRAY_READ, 8, src);
status = AT91F_DataFlashSendCommand(
pDataFlash, DB_CONTINUOUS_ARRAY_READ, 8, src);
/* Send the command to the dataflash */
return(status);
return (status);
}
/*---------------------------------------------------------------------------*/
/* Function Name : AT91F_DataFlashPagePgmBuf */
/* Object : Main memory page program thru buffer 1 or buffer 2 */
@ -185,11 +181,10 @@ AT91S_DataFlashStatus AT91F_DataFlashContinuousRead (
/* : <SizeToWrite> = data buffer size */
/* Return value : State of the dataflash */
/*---------------------------------------------------------------------------*/
AT91S_DataFlashStatus AT91F_DataFlashPagePgmBuf(
AT91PS_DataFlash pDataFlash,
unsigned char *src,
unsigned int dest,
unsigned int SizeToWrite)
AT91S_DataFlashStatus AT91F_DataFlashPagePgmBuf(AT91PS_DataFlash pDataFlash,
unsigned char *src,
unsigned int dest,
unsigned int SizeToWrite)
{
int cmdsize;
pDataFlash->pDataFlashDesc->tx_data_pt = src;
@ -201,9 +196,9 @@ AT91S_DataFlashStatus AT91F_DataFlashPagePgmBuf(
/* Send the command to the dataflash */
if (pDataFlash->pDevice->pages_number >= 16384)
cmdsize = 5;
return(AT91F_DataFlashSendCommand (pDataFlash, DB_PAGE_PGM_BUF1,
cmdsize, dest)); }
return (AT91F_DataFlashSendCommand(
pDataFlash, DB_PAGE_PGM_BUF1, cmdsize, dest));
}
/*---------------------------------------------------------------------------*/
/* Function Name : AT91F_MainMemoryToBufferTransfert */
@ -214,26 +209,29 @@ cmdsize, dest)); }
/* Return value : State of the dataflash */
/*---------------------------------------------------------------------------*/
AT91S_DataFlashStatus AT91F_MainMemoryToBufferTransfert(
AT91PS_DataFlash pDataFlash,
unsigned char BufferCommand,
unsigned int page)
AT91PS_DataFlash
pDataFlash,
unsigned char
BufferCommand,
unsigned int page)
{
int cmdsize;
/* Test if the buffer command is legal */
if ((BufferCommand != DB_PAGE_2_BUF1_TRF)
&& (BufferCommand != DB_PAGE_2_BUF2_TRF))
if ((BufferCommand != DB_PAGE_2_BUF1_TRF) &&
(BufferCommand != DB_PAGE_2_BUF2_TRF)) {
return DATAFLASH_BAD_COMMAND;
}
/* no data to transmit or receive */
pDataFlash->pDataFlashDesc->tx_data_size = 0;
cmdsize = 4;
if (pDataFlash->pDevice->pages_number >= 16384)
cmdsize = 5;
return(AT91F_DataFlashSendCommand (pDataFlash, BufferCommand, cmdsize,
page*pDataFlash->pDevice->pages_size));
return (AT91F_DataFlashSendCommand(
pDataFlash, BufferCommand, cmdsize,
page * pDataFlash->pDevice->pages_size));
}
/*-------------------------------------------------------------------------- */
/* Function Name : AT91F_DataFlashWriteBuffer */
/* Object : Write data to the internal sram buffer 1 or 2 */
@ -244,58 +242,61 @@ page*pDataFlash->pDevice->pages_size));
/* : <SizeToWrite> = data buffer size */
/* Return value : State of the dataflash */
/*---------------------------------------------------------------------------*/
AT91S_DataFlashStatus AT91F_DataFlashWriteBuffer (
AT91PS_DataFlash pDataFlash,
unsigned char BufferCommand,
unsigned char *dataBuffer,
unsigned int bufferAddress,
int SizeToWrite )
AT91S_DataFlashStatus AT91F_DataFlashWriteBuffer(
AT91PS_DataFlash pDataFlash,
unsigned char BufferCommand,
unsigned char *dataBuffer,
unsigned int bufferAddress,
int SizeToWrite)
{
int cmdsize;
/* Test if the buffer command is legal */
if ((BufferCommand != DB_BUF1_WRITE)
&& (BufferCommand != DB_BUF2_WRITE))
if ((BufferCommand != DB_BUF1_WRITE) &&
(BufferCommand != DB_BUF2_WRITE)) {
return DATAFLASH_BAD_COMMAND;
}
/* buffer address must be lower than page size */
if (bufferAddress > pDataFlash->pDevice->pages_size)
return DATAFLASH_BAD_ADDRESS;
if ( (pDataFlash->pDataFlashDesc->state) != IDLE)
if ((pDataFlash->pDataFlashDesc->state) != IDLE)
return DATAFLASH_BUSY;
/* Send first Write Command */
pDataFlash->pDataFlashDesc->command[0] = BufferCommand;
pDataFlash->pDataFlashDesc->command[1] = 0;
if (pDataFlash->pDevice->pages_number >= 16384) {
pDataFlash->pDataFlashDesc->command[2] = 0;
pDataFlash->pDataFlashDesc->command[3] =
pDataFlash->pDataFlashDesc->command[2] = 0;
pDataFlash->pDataFlashDesc->command[3] =
(unsigned char)(((unsigned int)(bufferAddress &
pDataFlash->pDevice->byte_mask)) >> 8);
pDataFlash->pDataFlashDesc->command[4] =
(unsigned char)((unsigned int)bufferAddress & 0x00FF);
pDataFlash->pDevice->
byte_mask)) >> 8);
pDataFlash->pDataFlashDesc->command[4] =
(unsigned char)((unsigned int)bufferAddress & 0x00FF);
cmdsize = 5;
} else {
pDataFlash->pDataFlashDesc->command[2] =
pDataFlash->pDataFlashDesc->command[2] =
(unsigned char)(((unsigned int)(bufferAddress &
pDataFlash->pDevice->byte_mask)) >> 8);
pDataFlash->pDataFlashDesc->command[3] =
(unsigned char)((unsigned int)bufferAddress & 0x00FF);
pDataFlash->pDataFlashDesc->command[4] = 0;
pDataFlash->pDevice->
byte_mask)) >> 8);
pDataFlash->pDataFlashDesc->command[3] =
(unsigned char)((unsigned int)bufferAddress & 0x00FF);
pDataFlash->pDataFlashDesc->command[4] = 0;
cmdsize = 4;
}
pDataFlash->pDataFlashDesc->tx_cmd_pt =
pDataFlash->pDataFlashDesc->tx_cmd_pt =
pDataFlash->pDataFlashDesc->command;
pDataFlash->pDataFlashDesc->tx_cmd_size = cmdsize;
pDataFlash->pDataFlashDesc->rx_cmd_pt =
pDataFlash->pDataFlashDesc->rx_cmd_pt =
pDataFlash->pDataFlashDesc->command;
pDataFlash->pDataFlashDesc->rx_cmd_size = cmdsize;
pDataFlash->pDataFlashDesc->rx_data_pt = dataBuffer;
pDataFlash->pDataFlashDesc->tx_data_pt = dataBuffer;
pDataFlash->pDataFlashDesc->rx_data_size = SizeToWrite;
pDataFlash->pDataFlashDesc->tx_data_size = SizeToWrite;
pDataFlash->pDataFlashDesc->rx_data_pt = dataBuffer;
pDataFlash->pDataFlashDesc->tx_data_pt = dataBuffer;
pDataFlash->pDataFlashDesc->rx_data_size = SizeToWrite;
pDataFlash->pDataFlashDesc->tx_data_size = SizeToWrite;
return AT91F_SpiWrite(pDataFlash->pDataFlashDesc);
}
@ -309,22 +310,22 @@ AT91S_DataFlashStatus AT91F_DataFlashWriteBuffer (
/* Return value : State of the dataflash */
/*---------------------------------------------------------------------------*/
AT91S_DataFlashStatus AT91F_PageErase(
AT91PS_DataFlash pDataFlash,
unsigned int page)
AT91PS_DataFlash pDataFlash,
unsigned int page)
{
int cmdsize;
/* Test if the buffer command is legal */
/* no data to transmit or receive */
pDataFlash->pDataFlashDesc->tx_data_size = 0;
pDataFlash->pDataFlashDesc->tx_data_size = 0;
cmdsize = 4;
if (pDataFlash->pDevice->pages_number >= 16384)
cmdsize = 5;
return(AT91F_DataFlashSendCommand (pDataFlash, DB_PAGE_ERASE, cmdsize,
page*pDataFlash->pDevice->pages_size));
return (AT91F_DataFlashSendCommand(pDataFlash,
DB_PAGE_ERASE, cmdsize,
page * pDataFlash->pDevice->pages_size));
}
/*---------------------------------------------------------------------------*/
/* Function Name : AT91F_BlockErase */
/* Object : Erase a Block */
@ -334,18 +335,19 @@ page*pDataFlash->pDevice->pages_size));
/* Return value : State of the dataflash */
/*---------------------------------------------------------------------------*/
AT91S_DataFlashStatus AT91F_BlockErase(
AT91PS_DataFlash pDataFlash,
unsigned int block)
AT91PS_DataFlash pDataFlash,
unsigned int block)
{
int cmdsize;
/* Test if the buffer command is legal */
/* no data to transmit or receive */
pDataFlash->pDataFlashDesc->tx_data_size = 0;
pDataFlash->pDataFlashDesc->tx_data_size = 0;
cmdsize = 4;
if (pDataFlash->pDevice->pages_number >= 16384)
cmdsize = 5;
return(AT91F_DataFlashSendCommand (pDataFlash, DB_BLOCK_ERASE,cmdsize,
block*8*pDataFlash->pDevice->pages_size));
return (AT91F_DataFlashSendCommand(pDataFlash, DB_BLOCK_ERASE, cmdsize,
block * 8 *
pDataFlash->pDevice->pages_size));
}
/*---------------------------------------------------------------------------*/
@ -356,17 +358,16 @@ block*8*pDataFlash->pDevice->pages_size));
/* : <dest> = main memory address */
/* Return value : State of the dataflash */
/*---------------------------------------------------------------------------*/
AT91S_DataFlashStatus AT91F_WriteBufferToMain (
AT91PS_DataFlash pDataFlash,
unsigned char BufferCommand,
unsigned int dest )
AT91S_DataFlashStatus AT91F_WriteBufferToMain(AT91PS_DataFlash pDataFlash,
unsigned char BufferCommand,
unsigned int dest)
{
int cmdsize;
/* Test if the buffer command is correct */
if ((BufferCommand != DB_BUF1_PAGE_PGM) &&
(BufferCommand != DB_BUF1_PAGE_ERASE_PGM) &&
(BufferCommand != DB_BUF2_PAGE_PGM) &&
(BufferCommand != DB_BUF2_PAGE_ERASE_PGM) )
(BufferCommand != DB_BUF1_PAGE_ERASE_PGM) &&
(BufferCommand != DB_BUF2_PAGE_PGM) &&
(BufferCommand != DB_BUF2_PAGE_ERASE_PGM))
return DATAFLASH_BAD_COMMAND;
/* no data to transmit or receive */
@ -376,9 +377,9 @@ AT91S_DataFlashStatus AT91F_WriteBufferToMain (
if (pDataFlash->pDevice->pages_number >= 16384)
cmdsize = 5;
/* Send the command to the dataflash */
return(AT91F_DataFlashSendCommand (pDataFlash, BufferCommand, cmdsize,
dest)); }
return (AT91F_DataFlashSendCommand(pDataFlash, BufferCommand,
cmdsize, dest));
}
/*---------------------------------------------------------------------------*/
/* Function Name : AT91F_PartialPageWrite */
@ -387,11 +388,10 @@ AT91S_DataFlashStatus AT91F_WriteBufferToMain (
/* : <AdrInpage> = adr to begin the fading */
/* : <length> = Number of bytes to erase */
/*---------------------------------------------------------------------------*/
AT91S_DataFlashStatus AT91F_PartialPageWrite (
AT91PS_DataFlash pDataFlash,
unsigned char *src,
unsigned int dest,
unsigned int size)
AT91S_DataFlashStatus AT91F_PartialPageWrite(AT91PS_DataFlash pDataFlash,
unsigned char *src,
unsigned int dest,
unsigned int size)
{
unsigned int page;
unsigned int AdrInPage;
@ -400,10 +400,9 @@ AT91S_DataFlashStatus AT91F_PartialPageWrite (
AdrInPage = dest % (pDataFlash->pDevice->pages_size);
/* Read the contents of the page in the Sram Buffer */
AT91F_MainMemoryToBufferTransfert(pDataFlash,
DB_PAGE_2_BUF1_TRF, page);
AT91F_MainMemoryToBufferTransfert(pDataFlash, DB_PAGE_2_BUF1_TRF, page);
AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc,
AT91C_TIMEOUT_WRDY);
AT91C_TIMEOUT_WRDY);
/*Update the SRAM buffer */
AT91F_DataFlashWriteBuffer(pDataFlash, DB_BUF1_WRITE, src,
AdrInPage, size);
@ -416,12 +415,13 @@ AT91S_DataFlashStatus AT91F_PartialPageWrite (
AT91F_PageErase(pDataFlash, page);
/* Rewrite the modified Sram Buffer in the main memory */
AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc,
AT91C_TIMEOUT_WRDY);
AT91C_TIMEOUT_WRDY);
}
/* Rewrite the modified Sram Buffer in the main memory */
return(AT91F_WriteBufferToMain(pDataFlash, DB_BUF1_PAGE_ERASE_PGM,
(page*pDataFlash->pDevice->pages_size)));
return (AT91F_WriteBufferToMain(pDataFlash, DB_BUF1_PAGE_ERASE_PGM,
(page *
pDataFlash->pDevice->pages_size)));
}
/*---------------------------------------------------------------------------*/
@ -431,11 +431,9 @@ AT91S_DataFlashStatus AT91F_PartialPageWrite (
/* : <dest> = dataflash adress */
/* : <size> = data buffer size */
/*---------------------------------------------------------------------------*/
AT91S_DataFlashStatus AT91F_DataFlashWrite(
AT91PS_DataFlash pDataFlash,
unsigned char *src,
int dest,
int size )
AT91S_DataFlashStatus AT91F_DataFlashWrite(AT91PS_DataFlash pDataFlash,
unsigned char *src,
int dest, int size)
{
unsigned int length;
unsigned int page;
@ -443,26 +441,24 @@ AT91S_DataFlashStatus AT91F_DataFlashWrite(
AT91F_SpiEnable(pDataFlash->pDevice->cs);
if ( (dest + size) > (pDataFlash->pDevice->pages_size *
(pDataFlash->pDevice->pages_number)))
if ((dest + size) > (pDataFlash->pDevice->pages_size *
(pDataFlash->pDevice->pages_number)))
return DATAFLASH_MEMORY_OVERFLOW;
/* If destination does not fit a page start address */
if ((dest % ((unsigned int)(pDataFlash->pDevice->pages_size))) != 0 )
{
length = pDataFlash->pDevice->pages_size -
(dest %
((unsigned int)
(pDataFlash->pDevice->pages_size)));
if ((dest % ((unsigned int)(pDataFlash->pDevice->pages_size))) != 0) {
length =
pDataFlash->pDevice->pages_size -
(dest % ((unsigned int)(pDataFlash->pDevice->pages_size)));
if (size < length)
length = size;
if(!AT91F_PartialPageWrite(pDataFlash,src, dest, length))
if (!AT91F_PartialPageWrite(pDataFlash, src, dest, length))
return DATAFLASH_ERROR;
AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc,
AT91C_TIMEOUT_WRDY);
AT91C_TIMEOUT_WRDY);
/* Update size, source and destination pointers */
size -= length;
@ -470,78 +466,77 @@ AT91S_DataFlashStatus AT91F_DataFlashWrite(
src += length;
}
while (( size - pDataFlash->pDevice->pages_size ) >= 0 ) {
while ((size - pDataFlash->pDevice->pages_size) >= 0) {
/* program dataflash page */
page = (unsigned int)dest / (pDataFlash->pDevice->pages_size);
status = AT91F_DataFlashWriteBuffer(pDataFlash,
DB_BUF1_WRITE, src, 0,
pDataFlash->pDevice->pages_size);
DB_BUF1_WRITE, src, 0,
pDataFlash->pDevice->
pages_size);
AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc,
AT91C_TIMEOUT_WRDY);
AT91C_TIMEOUT_WRDY);
status = AT91F_PageErase(pDataFlash, page);
AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc,
AT91C_TIMEOUT_WRDY);
AT91C_TIMEOUT_WRDY);
if (!status)
return DATAFLASH_ERROR;
status = AT91F_WriteBufferToMain (pDataFlash,
DB_BUF1_PAGE_PGM, dest);
if(!status)
status = AT91F_WriteBufferToMain(pDataFlash,
DB_BUF1_PAGE_PGM, dest);
if (!status)
return DATAFLASH_ERROR;
AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc,
AT91C_TIMEOUT_WRDY);
AT91C_TIMEOUT_WRDY);
/* Update size, source and destination pointers */
size -= pDataFlash->pDevice->pages_size;
dest += pDataFlash->pDevice->pages_size;
src += pDataFlash->pDevice->pages_size;
src += pDataFlash->pDevice->pages_size;
}
/* If still some bytes to read */
if ( size > 0 ) {
if (size > 0) {
/* program dataflash page */
if(!AT91F_PartialPageWrite(pDataFlash, src, dest, size) )
if (!AT91F_PartialPageWrite(pDataFlash, src, dest, size))
return DATAFLASH_ERROR;
AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc,
AT91C_TIMEOUT_WRDY);
AT91C_TIMEOUT_WRDY);
}
return DATAFLASH_OK;
}
/*---------------------------------------------------------------------------*/
/* Function Name : AT91F_DataFlashRead */
/* Object : Read a block in dataflash */
/* Input Parameters : */
/* Return value : */
/*---------------------------------------------------------------------------*/
int AT91F_DataFlashRead(
AT91PS_DataFlash pDataFlash,
unsigned long addr,
unsigned long size,
char *buffer)
int AT91F_DataFlashRead(AT91PS_DataFlash pDataFlash,
unsigned long addr, unsigned long size, char *buffer)
{
unsigned long SizeToRead;
AT91F_SpiEnable(pDataFlash->pDevice->cs);
if(AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc,
if (AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc,
AT91C_TIMEOUT_WRDY) != DATAFLASH_OK)
return -1;
while (size) {
SizeToRead = (size < 0x8000)? size:0x8000;
SizeToRead = (size < 0x8000) ? size : 0x8000;
if (AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc,
AT91C_TIMEOUT_WRDY) != DATAFLASH_OK)
AT91C_TIMEOUT_WRDY) !=
DATAFLASH_OK)
return -1;
if (AT91F_DataFlashContinuousRead (pDataFlash, addr,
(uchar *) buffer, SizeToRead) != DATAFLASH_OK)
if (AT91F_DataFlashContinuousRead(pDataFlash, addr,
(uchar *) buffer,
SizeToRead) != DATAFLASH_OK)
return -1;
size -= SizeToRead;
@ -558,9 +553,10 @@ int AT91F_DataFlashRead(
/* Input Parameters : */
/* Return value : Dataflash status register */
/*---------------------------------------------------------------------------*/
int AT91F_DataflashProbe(int cs, AT91PS_DataflashDesc pDesc) {
int AT91F_DataflashProbe(int cs, AT91PS_DataflashDesc pDesc)
{
AT91F_SpiEnable(cs);
AT91F_DataFlashGetStatus(pDesc);
return((pDesc->command[1] == 0xFF)? 0: pDesc->command[1] & 0x3C);
return ((pDesc->command[1] == 0xFF) ? 0 : pDesc->command[1] & 0x3C);
}
#endif

23
drivers/bios_emulator/Makefile
View File

@ -2,9 +2,11 @@ include $(TOPDIR)/config.mk
LIB := $(obj)libatibiosemu.a
X86DIR = ./x86emu
X86DIR = x86emu
OBJS = atibios.o biosemu.o besys.o bios.o \
$(shell mkdir -p $(obj)$(X86DIR))
COBJS = atibios.o biosemu.o besys.o bios.o \
$(X86DIR)/decode.o \
$(X86DIR)/ops2.o \
$(X86DIR)/ops.o \
@ -12,19 +14,24 @@ OBJS = atibios.o biosemu.o besys.o bios.o \
$(X86DIR)/sys.o \
$(X86DIR)/debug.o
CFLAGS += -I. -I./include -I$(X86DIR) -I$(TOPDIR)/include \
SRCS := $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
EXTRA_CFLAGS += -I. -I./include -I$(TOPDIR)/include \
-D__PPC__ -D__BIG_ENDIAN__
CFLAGS += $(EXTRA_CFLAGS)
HOST_CFLAGS += $(EXTRA_CFLAGS)
all: $(LIB)
$(LIB): $(OBJS)
$(AR) crv $@ $(OBJS)
$(LIB): $(obj).depend $(OBJS)
$(AR) $(ARFLAGS) $@ $(OBJS)
#########################################################################
.depend: Makefile $(OBJS:.o=.c)
$(CC) -M $(CFLAGS) $(OBJS:.o=.c) > $@
include $(SRCTREE)/rules.mk
sinclude .depend
sinclude $(obj).depend
#########################################################################

16
drivers/dm9000x.c
View File

@ -99,7 +99,7 @@ void eth_halt(void);
static int dm9000_probe(void);
static u16 phy_read(int);
static void phy_write(int, u16);
static u16 read_srom_word(int);
u16 read_srom_word(int);
static u8 DM9000_ior(int);
static void DM9000_iow(int reg, u8 value);
@ -537,7 +537,7 @@ eth_rx(void)
/*
Read a word data from SROM
*/
static u16
u16
read_srom_word(int offset)
{
DM9000_iow(DM9000_EPAR, offset);
@ -547,6 +547,18 @@ read_srom_word(int offset)
return (DM9000_ior(DM9000_EPDRL) + (DM9000_ior(DM9000_EPDRH) << 8));
}
void
write_srom_word(int offset, u16 val)
{
DM9000_iow(DM9000_EPAR, offset);
DM9000_iow(DM9000_EPDRH, ((val >> 8) & 0xff));
DM9000_iow(DM9000_EPDRL, (val & 0xff));
DM9000_iow(DM9000_EPCR, 0x12);
udelay(8000);
DM9000_iow(DM9000_EPCR, 0);
}
/*
Read a byte from I/O port
*/

112
drivers/isp116x-hcd.c
View File

@ -113,9 +113,9 @@ static const char hcd_name[] = "isp116x-hcd";
struct isp116x isp116x_dev;
struct isp116x_platform_data isp116x_board;
int got_rhsc = 0; /* root hub status change */
static int got_rhsc; /* root hub status change */
struct usb_device *devgone; /* device which was disconnected */
int rh_devnum = 0; /* address of Root Hub endpoint */
static int rh_devnum; /* address of Root Hub endpoint */
/* ------------------------------------------------------------------------- */
@ -522,11 +522,13 @@ static int unpack_fifo(struct isp116x *isp116x, struct usb_device *dev,
done += PTD_GET_LEN(&ptd[i]);
cc = PTD_GET_CC(&ptd[i]);
if (cc == TD_DATAUNDERRUN) { /* underrun is no error... */
DBG("allowed data underrun");
cc = TD_CC_NOERROR;
}
if (cc != TD_CC_NOERROR && ret == TD_CC_NOERROR)
/* Data underrun means basically that we had more buffer space than
* the function had data. It is perfectly normal but upper levels have
* to know how much we actually transferred.
*/
if (cc == TD_NOTACCESSED ||
(cc != TD_CC_NOERROR && (ret == TD_CC_NOERROR || ret == TD_DATAUNDERRUN)))
ret = cc;
}
@ -592,11 +594,19 @@ static int isp116x_interrupt(struct isp116x *isp116x)
return ret;
}
#define PTD_NUM 64 /* it should be enougth... */
struct ptd ptd[PTD_NUM];
/* With one PTD we can transfer almost 1K in one go;
* HC does the splitting into endpoint digestible transactions
*/
struct ptd ptd[1];
static inline int max_transfer_len(struct usb_device *dev, unsigned long pipe)
{
return min(PTD_NUM * usb_maxpacket(dev, pipe), PTD_NUM * 16);
unsigned mpck = usb_maxpacket(dev, pipe);
/* One PTD can transfer 1023 bytes but try to always
* transfer multiples of endpoint buffer size
*/
return 1023 / mpck * mpck;
}
/* Do an USB transfer
@ -610,13 +620,21 @@ static int isp116x_submit_job(struct usb_device *dev, unsigned long pipe,
int max = usb_maxpacket(dev, pipe);
int dir_out = usb_pipeout(pipe);
int speed_low = usb_pipeslow(pipe);
int i, done, stat, timeout, cc;
int retries = 10;
int i, done = 0, stat, timeout, cc;
/* 500 frames or 0.5s timeout when function is busy and NAKs transactions for a while */
int retries = 500;
DBG("------------------------------------------------");
dump_msg(dev, pipe, buffer, len, "SUBMIT");
DBG("------------------------------------------------");
if (len >= 1024) {
ERR("Too big job");
dev->status = USB_ST_CRC_ERR;
return -1;
}
if (isp116x->disabled) {
ERR("EPIPE");
dev->status = USB_ST_CRC_ERR;
@ -653,29 +671,15 @@ static int isp116x_submit_job(struct usb_device *dev, unsigned long pipe,
isp116x_write_reg32(isp116x, HCINTSTAT, 0xff);
/* Prepare the PTD data */
done = 0;
i = 0;
do {
ptd[i].count = PTD_CC_MSK | PTD_ACTIVE_MSK |
PTD_TOGGLE(usb_gettoggle(dev, epnum, dir_out));
ptd[i].mps = PTD_MPS(max) | PTD_SPD(speed_low) | PTD_EP(epnum);
ptd[i].len = PTD_LEN(max > len - done ? len - done : max) |
PTD_DIR(dir);
ptd[i].faddr = PTD_FA(usb_pipedevice(pipe));
usb_dotoggle(dev, epnum, dir_out);
done += PTD_GET_LEN(&ptd[i]);
i++;
if (i >= PTD_NUM) {
ERR("****** Cannot pack buffer! ******");
dev->status = USB_ST_BUF_ERR;
return -1;
}
} while (done < len);
ptd[i - 1].mps |= PTD_LAST_MSK;
ptd->count = PTD_CC_MSK | PTD_ACTIVE_MSK |
PTD_TOGGLE(usb_gettoggle(dev, epnum, dir_out));
ptd->mps = PTD_MPS(max) | PTD_SPD(speed_low) | PTD_EP(epnum) | PTD_LAST_MSK;
ptd->len = PTD_LEN(len) | PTD_DIR(dir);
ptd->faddr = PTD_FA(usb_pipedevice(pipe));
retry_same:
/* Pack data into FIFO ram */
pack_fifo(isp116x, dev, pipe, ptd, i, buffer, len);
pack_fifo(isp116x, dev, pipe, ptd, 1, buffer, len);
#ifdef EXTRA_DELAY
wait_ms(EXTRA_DELAY);
#endif
@ -738,17 +742,42 @@ static int isp116x_submit_job(struct usb_device *dev, unsigned long pipe,
}
/* Unpack data from FIFO ram */
cc = unpack_fifo(isp116x, dev, pipe, ptd, i, buffer, len);
cc = unpack_fifo(isp116x, dev, pipe, ptd, 1, buffer, len);
/* Mmm... sometime we get 0x0f as cc which is a non sense!
* Just retry the transfer...
i = PTD_GET_COUNT(ptd);
done += i;
buffer += i;
len -= i;
/* There was some kind of real problem; Prepare the PTD again
* and retry from the failed transaction on
*/
if (cc == 0x0f && retries-- > 0) {
usb_dotoggle(dev, epnum, dir_out);
goto retry;
if (cc && cc != TD_NOTACCESSED && cc != TD_DATAUNDERRUN) {
if (retries >= 100) {
retries -= 100;
/* The chip will have toggled the toggle bit for the failed
* transaction too. We have to toggle it back.
*/
usb_settoggle(dev, epnum, dir_out, !PTD_GET_TOGGLE(ptd));
goto retry;
}
}
/* "Normal" errors; TD_NOTACCESSED would mean in effect that the function have NAKed
* the transactions from the first on for the whole frame. It may be busy and we retry
* with the same PTD. PTD_ACTIVE (and not TD_NOTACCESSED) would mean that some of the
* PTD didn't make it because the function was busy or the frame ended before the PTD
* finished. We prepare the rest of the data and try again.
*/
else if (cc == TD_NOTACCESSED || PTD_GET_ACTIVE(ptd) || (cc != TD_DATAUNDERRUN && PTD_GET_COUNT(ptd) < PTD_GET_LEN(ptd))) {
if (retries) {
--retries;
if (cc == TD_NOTACCESSED && PTD_GET_ACTIVE(ptd) && !PTD_GET_COUNT(ptd)) goto retry_same;
usb_settoggle(dev, epnum, dir_out, PTD_GET_TOGGLE(ptd));
goto retry;
}
}
if (cc != TD_CC_NOERROR) {
if (cc != TD_CC_NOERROR && cc != TD_DATAUNDERRUN) {
DBG("****** completition code error %x ******", cc);
switch (cc) {
case TD_CC_BITSTUFFING:
@ -766,6 +795,7 @@ static int isp116x_submit_job(struct usb_device *dev, unsigned long pipe,
}
return -cc;
}
else usb_settoggle(dev, epnum, dir_out, PTD_GET_TOGGLE(ptd));
dump_msg(dev, pipe, buffer, len, "SUBMIT(ret)");
@ -1369,6 +1399,8 @@ int usb_lowlevel_init(void)
DBG("");
got_rhsc = rh_devnum = 0;
/* Init device registers addr */
isp116x->addr_reg = (u16 *) ISP116X_HCD_ADDR;
isp116x->data_reg = (u16 *) ISP116X_HCD_DATA;

21
drivers/nand/nand_util.c
View File

@ -210,9 +210,12 @@ int nand_erase_opts(nand_info_t *meminfo, const nand_erase_options_t *opts)
if (!opts->quiet) {
unsigned long long n =(unsigned long long)
(erase.addr+meminfo->erasesize-opts->offset)
* 100;
int percent = (int)do_div(n, erase_length);
(erase.addr + meminfo->erasesize - opts->offset)
* 100;
int percent;
do_div(n, erase_length);
percent = (int)n;
/* output progress message only at whole percent
* steps to reduce the number of messages printed
@ -478,7 +481,11 @@ int nand_write_opts(nand_info_t *meminfo, const nand_write_options_t *opts)
if (!opts->quiet) {
unsigned long long n = (unsigned long long)
(opts->length-imglen) * 100;
int percent = (int)do_div(n, opts->length);
int percent;
do_div(n, opts->length);
percent = (int)n;
/* output progress message only at whole percent
* steps to reduce the number of messages printed
* on (slow) serial consoles
@ -653,7 +660,11 @@ int nand_read_opts(nand_info_t *meminfo, const nand_read_options_t *opts)
if (!opts->quiet) {
unsigned long long n = (unsigned long long)
(opts->length-imglen) * 100;
int percent = (int)do_div(n ,opts->length);
int percent;
do_div(n, opts->length);
percent = (int)n;
/* output progress message only at whole percent
* steps to reduce the number of messages printed
* on (slow) serial consoles

44
drivers/onenand/Makefile Normal file
View File

@ -0,0 +1,44 @@
#
# Copyright (C) 2005-2007 Samsung Electronics.
# Kyungmin Park <kyungmin.park@samsung.com>
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB := $(obj)libonenand.a
COBJS := onenand_base.o onenand_bbt.o
SRCS := $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
all: $(LIB)
$(LIB): $(obj).depend $(OBJS)
$(AR) $(ARFLAGS) $@ $(OBJS)
#########################################################################
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################

Some files were not shown because too many files have changed in this diff Show More