From 7ebb4479b07ff294eb4d76e420753a0349f7c93b Mon Sep 17 00:00:00 2001 From: Ulf Samuelsson Date: Thu, 24 May 2007 12:12:47 +0200 Subject: [PATCH 001/259] [PATCH][NAND] Define the Vendor Id for Micron NAND Flash Signed-off-by: Ulf Samuelsson Signed-off-by: Ladislav Michl Signed-off-by: Stefan Roese --- drivers/nand/nand_ids.c | 1 + include/linux/mtd/nand.h | 1 + 2 files changed, 2 insertions(+) diff --git a/drivers/nand/nand_ids.c b/drivers/nand/nand_ids.c index 8b58736bc..70fdfd3f5 100644 --- a/drivers/nand/nand_ids.c +++ b/drivers/nand/nand_ids.c @@ -123,6 +123,7 @@ struct nand_manufacturers nand_manuf_ids[] = { {NAND_MFR_NATIONAL, "National"}, {NAND_MFR_RENESAS, "Renesas"}, {NAND_MFR_STMICRO, "ST Micro"}, + {NAND_MFR_MICRON, "Micron"}, {0x0, "Unknown"} }; #endif diff --git a/include/linux/mtd/nand.h b/include/linux/mtd/nand.h index 4b485643a..49ff80fd3 100644 --- a/include/linux/mtd/nand.h +++ b/include/linux/mtd/nand.h @@ -348,6 +348,7 @@ struct nand_chip { #define NAND_MFR_NATIONAL 0x8f #define NAND_MFR_RENESAS 0x07 #define NAND_MFR_STMICRO 0x20 +#define NAND_MFR_MICRON 0x2c /** * struct nand_flash_dev - NAND Flash Device ID Structure From f539edc076cfe52bff919dd512ba8d7af0e22092 Mon Sep 17 00:00:00 2001 From: Vadim Bendebury Date: Thu, 24 May 2007 15:52:25 -0700 Subject: [PATCH 002/259] cosmetic changes to bcm570x driver This is a cosmetic only changes submission. It affects files relevant to bcm570x driver. the commands used to generate this change was cd drivers Lindent -pcs -l80 bcm570x.c bcm570x_lm.h bcm570x_mm.h tigon3.c tigon3.h The BMW target (the only one using this chip so far) builds cleanly, the `before and after' generated object files for drivers/bcm570x.c and drivers/tigon3.o are identical as reported by objdump -d Signed-off-by: Vadim Bendebury Signed-off-by: Ben Warren --- drivers/bcm570x.c | 2358 +++++----- drivers/bcm570x_lm.h | 199 +- drivers/bcm570x_mm.h | 58 +- drivers/tigon3.c | 9816 ++++++++++++++++++++---------------------- drivers/tigon3.h | 3359 +++++++-------- 5 files changed, 7545 insertions(+), 8245 deletions(-) diff --git a/drivers/bcm570x.c b/drivers/bcm570x.c index 5f632a646..7aeb5474b 100644 --- a/drivers/bcm570x.c +++ b/drivers/bcm570x.c @@ -18,7 +18,6 @@ #include #include - /* * PCI Registers and definitions. */ @@ -31,7 +30,6 @@ #define BCM570X_MBAR 0x80100000 #define BCM570X_ILINE 1 - #define SECOND_USEC 1000000 #define MAX_PACKET_SIZE 1600 #define MAX_UNITS 4 @@ -39,62 +37,61 @@ /* Globals to this module */ int initialized = 0; unsigned int ioBase = 0; -volatile PLM_DEVICE_BLOCK pDevice = NULL; /* 570x softc */ -volatile PUM_DEVICE_BLOCK pUmDevice = NULL; +volatile PLM_DEVICE_BLOCK pDevice = NULL; /* 570x softc */ +volatile PUM_DEVICE_BLOCK pUmDevice = NULL; /* Used to pass the full-duplex flag, etc. */ -int line_speed[MAX_UNITS] = {0,0,0,0}; -static int full_duplex[MAX_UNITS] = {1,1,1,1}; -static int rx_flow_control[MAX_UNITS] = {0,0,0,0}; -static int tx_flow_control[MAX_UNITS] = {0,0,0,0}; -static int auto_flow_control[MAX_UNITS] = {0,0,0,0}; -static int tx_checksum[MAX_UNITS] = {1,1,1,1}; -static int rx_checksum[MAX_UNITS] = {1,1,1,1}; -static int auto_speed[MAX_UNITS] = {1,1,1,1}; +int line_speed[MAX_UNITS] = { 0, 0, 0, 0 }; +static int full_duplex[MAX_UNITS] = { 1, 1, 1, 1 }; +static int rx_flow_control[MAX_UNITS] = { 0, 0, 0, 0 }; +static int tx_flow_control[MAX_UNITS] = { 0, 0, 0, 0 }; +static int auto_flow_control[MAX_UNITS] = { 0, 0, 0, 0 }; +static int tx_checksum[MAX_UNITS] = { 1, 1, 1, 1 }; +static int rx_checksum[MAX_UNITS] = { 1, 1, 1, 1 }; +static int auto_speed[MAX_UNITS] = { 1, 1, 1, 1 }; #if JUMBO_FRAMES /* Jumbo MTU for interfaces. */ -static int mtu[MAX_UNITS] = {0,0,0,0}; +static int mtu[MAX_UNITS] = { 0, 0, 0, 0 }; #endif /* Turn on Wake-on lan for a device unit */ -static int enable_wol[MAX_UNITS] = {0,0,0,0}; +static int enable_wol[MAX_UNITS] = { 0, 0, 0, 0 }; #define TX_DESC_CNT DEFAULT_TX_PACKET_DESC_COUNT static unsigned int tx_pkt_desc_cnt[MAX_UNITS] = - {TX_DESC_CNT,TX_DESC_CNT,TX_DESC_CNT, TX_DESC_CNT}; + { TX_DESC_CNT, TX_DESC_CNT, TX_DESC_CNT, TX_DESC_CNT }; #define RX_DESC_CNT DEFAULT_STD_RCV_DESC_COUNT static unsigned int rx_std_desc_cnt[MAX_UNITS] = - {RX_DESC_CNT,RX_DESC_CNT,RX_DESC_CNT,RX_DESC_CNT}; + { RX_DESC_CNT, RX_DESC_CNT, RX_DESC_CNT, RX_DESC_CNT }; -static unsigned int rx_adaptive_coalesce[MAX_UNITS] = {1,1,1,1}; +static unsigned int rx_adaptive_coalesce[MAX_UNITS] = { 1, 1, 1, 1 }; #if T3_JUMBO_RCV_RCB_ENTRY_COUNT #define JBO_DESC_CNT DEFAULT_JUMBO_RCV_DESC_COUNT static unsigned int rx_jumbo_desc_cnt[MAX_UNITS] = - {JBO_DESC_CNT, JBO_DESC_CNT, JBO_DESC_CNT, JBO_DESC_CNT}; + { JBO_DESC_CNT, JBO_DESC_CNT, JBO_DESC_CNT, JBO_DESC_CNT }; #endif #define RX_COAL_TK DEFAULT_RX_COALESCING_TICKS static unsigned int rx_coalesce_ticks[MAX_UNITS] = - {RX_COAL_TK, RX_COAL_TK, RX_COAL_TK, RX_COAL_TK}; + { RX_COAL_TK, RX_COAL_TK, RX_COAL_TK, RX_COAL_TK }; #define RX_COAL_FM DEFAULT_RX_MAX_COALESCED_FRAMES static unsigned int rx_max_coalesce_frames[MAX_UNITS] = - {RX_COAL_FM, RX_COAL_FM, RX_COAL_FM, RX_COAL_FM}; + { RX_COAL_FM, RX_COAL_FM, RX_COAL_FM, RX_COAL_FM }; #define TX_COAL_TK DEFAULT_TX_COALESCING_TICKS static unsigned int tx_coalesce_ticks[MAX_UNITS] = - {TX_COAL_TK, TX_COAL_TK, TX_COAL_TK, TX_COAL_TK}; + { TX_COAL_TK, TX_COAL_TK, TX_COAL_TK, TX_COAL_TK }; #define TX_COAL_FM DEFAULT_TX_MAX_COALESCED_FRAMES static unsigned int tx_max_coalesce_frames[MAX_UNITS] = - {TX_COAL_FM, TX_COAL_FM, TX_COAL_FM, TX_COAL_FM}; + { TX_COAL_FM, TX_COAL_FM, TX_COAL_FM, TX_COAL_FM }; #define ST_COAL_TK DEFAULT_STATS_COALESCING_TICKS static unsigned int stats_coalesce_ticks[MAX_UNITS] = - {ST_COAL_TK, ST_COAL_TK, ST_COAL_TK, ST_COAL_TK}; - + { ST_COAL_TK, ST_COAL_TK, ST_COAL_TK, ST_COAL_TK }; /* * Legitimate values for BCM570x device types @@ -134,707 +131,701 @@ typedef enum { /* Chip-Rev names for each device-type */ static struct { - char* name; + char *name; } chip_rev[] = { - {"BCM5700VIGIL"}, - {"BCM5700A6"}, - {"BCM5700T6"}, - {"BCM5700A9"}, - {"BCM5700T9"}, - {"BCM5700"}, - {"BCM5701A5"}, - {"BCM5701T1"}, - {"BCM5701T8"}, - {"BCM5701A7"}, - {"BCM5701A10"}, - {"BCM5701A12"}, - {"BCM5701"}, - {"BCM5702"}, - {"BCM5703"}, - {"BCM5703A31"}, - {"TC996T"}, - {"TC996ST"}, - {"TC996SSX"}, - {"TC996SX"}, - {"TC996BT"}, - {"TC997T"}, - {"TC997SX"}, - {"TC1000T"}, - {"TC940BR01"}, - {"TC942BR01"}, - {"NC6770"}, - {"NC7760"}, - {"NC7770"}, - {"NC7780"}, - {0} + { + "BCM5700VIGIL"}, { + "BCM5700A6"}, { + "BCM5700T6"}, { + "BCM5700A9"}, { + "BCM5700T9"}, { + "BCM5700"}, { + "BCM5701A5"}, { + "BCM5701T1"}, { + "BCM5701T8"}, { + "BCM5701A7"}, { + "BCM5701A10"}, { + "BCM5701A12"}, { + "BCM5701"}, { + "BCM5702"}, { + "BCM5703"}, { + "BCM5703A31"}, { + "TC996T"}, { + "TC996ST"}, { + "TC996SSX"}, { + "TC996SX"}, { + "TC996BT"}, { + "TC997T"}, { + "TC997SX"}, { + "TC1000T"}, { + "TC940BR01"}, { + "TC942BR01"}, { + "NC6770"}, { + "NC7760"}, { + "NC7770"}, { + "NC7780"}, { + 0} }; - /* indexed by board_t, above */ static struct { - char *name; + char *name; } board_info[] = { - { "Broadcom Vigil B5700 1000Base-T" }, - { "Broadcom BCM5700 1000Base-T" }, - { "Broadcom BCM5700 1000Base-SX" }, - { "Broadcom BCM5700 1000Base-SX" }, - { "Broadcom BCM5700 1000Base-T" }, - { "Broadcom BCM5700" }, - { "Broadcom BCM5701 1000Base-T" }, - { "Broadcom BCM5701 1000Base-T" }, - { "Broadcom BCM5701 1000Base-T" }, - { "Broadcom BCM5701 1000Base-SX" }, - { "Broadcom BCM5701 1000Base-T" }, - { "Broadcom BCM5701 1000Base-T" }, - { "Broadcom BCM5701" }, - { "Broadcom BCM5702 1000Base-T" }, - { "Broadcom BCM5703 1000Base-T" }, - { "Broadcom BCM5703 1000Base-SX" }, - { "3Com 3C996 10/100/1000 Server NIC" }, - { "3Com 3C996 10/100/1000 Server NIC" }, - { "3Com 3C996 Gigabit Fiber-SX Server NIC" }, - { "3Com 3C996 Gigabit Fiber-SX Server NIC" }, - { "3Com 3C996B Gigabit Server NIC" }, - { "3Com 3C997 Gigabit Server NIC" }, - { "3Com 3C997 Gigabit Fiber-SX Server NIC" }, - { "3Com 3C1000 Gigabit NIC" }, - { "3Com 3C940 Gigabit LOM (21X21)" }, - { "3Com 3C942 Gigabit LOM (31X31)" }, - { "Compaq NC6770 Gigabit Server Adapter" }, - { "Compaq NC7760 Gigabit Server Adapter" }, - { "Compaq NC7770 Gigabit Server Adapter" }, - { "Compaq NC7780 Gigabit Server Adapter" }, - { 0 }, -}; + { + "Broadcom Vigil B5700 1000Base-T"}, { + "Broadcom BCM5700 1000Base-T"}, { + "Broadcom BCM5700 1000Base-SX"}, { + "Broadcom BCM5700 1000Base-SX"}, { + "Broadcom BCM5700 1000Base-T"}, { + "Broadcom BCM5700"}, { + "Broadcom BCM5701 1000Base-T"}, { + "Broadcom BCM5701 1000Base-T"}, { + "Broadcom BCM5701 1000Base-T"}, { + "Broadcom BCM5701 1000Base-SX"}, { + "Broadcom BCM5701 1000Base-T"}, { + "Broadcom BCM5701 1000Base-T"}, { + "Broadcom BCM5701"}, { + "Broadcom BCM5702 1000Base-T"}, { + "Broadcom BCM5703 1000Base-T"}, { + "Broadcom BCM5703 1000Base-SX"}, { + "3Com 3C996 10/100/1000 Server NIC"}, { + "3Com 3C996 10/100/1000 Server NIC"}, { + "3Com 3C996 Gigabit Fiber-SX Server NIC"}, { + "3Com 3C996 Gigabit Fiber-SX Server NIC"}, { + "3Com 3C996B Gigabit Server NIC"}, { + "3Com 3C997 Gigabit Server NIC"}, { + "3Com 3C997 Gigabit Fiber-SX Server NIC"}, { + "3Com 3C1000 Gigabit NIC"}, { + "3Com 3C940 Gigabit LOM (21X21)"}, { + "3Com 3C942 Gigabit LOM (31X31)"}, { + "Compaq NC6770 Gigabit Server Adapter"}, { + "Compaq NC7760 Gigabit Server Adapter"}, { + "Compaq NC7770 Gigabit Server Adapter"}, { + "Compaq NC7780 Gigabit Server Adapter"}, { +0},}; /* PCI Devices which use the 570x chipset */ struct pci_device_table { - unsigned short vendor_id, device_id; /* Vendor/DeviceID */ - unsigned short subvendor, subdevice; /* Subsystem ID's or PCI_ANY_ID */ - unsigned int class, class_mask; /* (class,subclass,prog-if) triplet */ - unsigned long board_id; /* Data private to the driver */ - int io_size, min_latency; + unsigned short vendor_id, device_id; /* Vendor/DeviceID */ + unsigned short subvendor, subdevice; /* Subsystem ID's or PCI_ANY_ID */ + unsigned int class, class_mask; /* (class,subclass,prog-if) triplet */ + unsigned long board_id; /* Data private to the driver */ + int io_size, min_latency; } bcm570xDevices[] = { - {0x14e4, 0x1644, 0x1014, 0x0277, 0, 0, BCM5700VIGIL ,128,32}, - {0x14e4, 0x1644, 0x14e4, 0x1644, 0, 0, BCM5700A6 ,128,32}, - {0x14e4, 0x1644, 0x14e4, 0x2, 0, 0, BCM5700T6 ,128,32}, - {0x14e4, 0x1644, 0x14e4, 0x3, 0, 0, BCM5700A9 ,128,32}, - {0x14e4, 0x1644, 0x14e4, 0x4, 0, 0, BCM5700T9 ,128,32}, - {0x14e4, 0x1644, 0x1028, 0xd1, 0, 0, BCM5700 ,128,32}, - {0x14e4, 0x1644, 0x1028, 0x0106, 0, 0, BCM5700 ,128,32}, - {0x14e4, 0x1644, 0x1028, 0x0109, 0, 0, BCM5700 ,128,32}, - {0x14e4, 0x1644, 0x1028, 0x010a, 0, 0, BCM5700 ,128,32}, - {0x14e4, 0x1644, 0x10b7, 0x1000, 0, 0, TC996T ,128,32}, - {0x14e4, 0x1644, 0x10b7, 0x1001, 0, 0, TC996ST ,128,32}, - {0x14e4, 0x1644, 0x10b7, 0x1002, 0, 0, TC996SSX ,128,32}, - {0x14e4, 0x1644, 0x10b7, 0x1003, 0, 0, TC997T ,128,32}, - {0x14e4, 0x1644, 0x10b7, 0x1005, 0, 0, TC997SX ,128,32}, - {0x14e4, 0x1644, 0x10b7, 0x1008, 0, 0, TC942BR01 ,128,32}, - {0x14e4, 0x1644, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5700 ,128,32}, - {0x14e4, 0x1645, 0x14e4, 1, 0, 0, BCM5701A5 ,128,32}, - {0x14e4, 0x1645, 0x14e4, 5, 0, 0, BCM5701T1 ,128,32}, - {0x14e4, 0x1645, 0x14e4, 6, 0, 0, BCM5701T8 ,128,32}, - {0x14e4, 0x1645, 0x14e4, 7, 0, 0, BCM5701A7 ,128,32}, - {0x14e4, 0x1645, 0x14e4, 8, 0, 0, BCM5701A10 ,128,32}, - {0x14e4, 0x1645, 0x14e4, 0x8008, 0, 0, BCM5701A12 ,128,32}, - {0x14e4, 0x1645, 0x0e11, 0xc1, 0, 0, NC6770 ,128,32}, - {0x14e4, 0x1645, 0x0e11, 0x7c, 0, 0, NC7770 ,128,32}, - {0x14e4, 0x1645, 0x0e11, 0x85, 0, 0, NC7780 ,128,32}, - {0x14e4, 0x1645, 0x1028, 0x0121, 0, 0, BCM5701 ,128,32}, - {0x14e4, 0x1645, 0x10b7, 0x1004, 0, 0, TC996SX ,128,32}, - {0x14e4, 0x1645, 0x10b7, 0x1006, 0, 0, TC996BT ,128,32}, - {0x14e4, 0x1645, 0x10b7, 0x1007, 0, 0, TC1000T ,128,32}, - {0x14e4, 0x1645, 0x10b7, 0x1008, 0, 0, TC940BR01 ,128,32}, - {0x14e4, 0x1645, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5701 ,128,32}, - {0x14e4, 0x1646, 0x14e4, 0x8009, 0, 0, BCM5702 ,128,32}, - {0x14e4, 0x1646, 0x0e11, 0xbb, 0, 0, NC7760 ,128,32}, - {0x14e4, 0x1646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5702 ,128,32}, - {0x14e4, 0x16a6, 0x14e4, 0x8009, 0, 0, BCM5702 ,128,32}, - {0x14e4, 0x16a6, 0x0e11, 0xbb, 0, 0, NC7760 ,128,32}, - {0x14e4, 0x16a6, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5702 ,128,32}, - {0x14e4, 0x1647, 0x14e4, 0x0009, 0, 0, BCM5703 ,128,32}, - {0x14e4, 0x1647, 0x14e4, 0x000a, 0, 0, BCM5703A31 ,128,32}, - {0x14e4, 0x1647, 0x14e4, 0x000b, 0, 0, BCM5703 ,128,32}, - {0x14e4, 0x1647, 0x14e4, 0x800a, 0, 0, BCM5703 ,128,32}, - {0x14e4, 0x1647, 0x0e11, 0x9a, 0, 0, NC7770 ,128,32}, - {0x14e4, 0x1647, 0x0e11, 0x99, 0, 0, NC7780 ,128,32}, - {0x14e4, 0x1647, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5703 ,128,32}, - {0x14e4, 0x16a7, 0x14e4, 0x0009, 0, 0, BCM5703 ,128,32}, - {0x14e4, 0x16a7, 0x14e4, 0x000a, 0, 0, BCM5703A31 ,128,32}, - {0x14e4, 0x16a7, 0x14e4, 0x000b, 0, 0, BCM5703 ,128,32}, - {0x14e4, 0x16a7, 0x14e4, 0x800a, 0, 0, BCM5703 ,128,32}, - {0x14e4, 0x16a7, 0x0e11, 0x9a, 0, 0, NC7770 ,128,32}, - {0x14e4, 0x16a7, 0x0e11, 0x99, 0, 0, NC7780 ,128,32}, - {0x14e4, 0x16a7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5703 ,128,32} + { + 0x14e4, 0x1644, 0x1014, 0x0277, 0, 0, BCM5700VIGIL, 128, 32}, { + 0x14e4, 0x1644, 0x14e4, 0x1644, 0, 0, BCM5700A6, 128, 32}, { + 0x14e4, 0x1644, 0x14e4, 0x2, 0, 0, BCM5700T6, 128, 32}, { + 0x14e4, 0x1644, 0x14e4, 0x3, 0, 0, BCM5700A9, 128, 32}, { + 0x14e4, 0x1644, 0x14e4, 0x4, 0, 0, BCM5700T9, 128, 32}, { + 0x14e4, 0x1644, 0x1028, 0xd1, 0, 0, BCM5700, 128, 32}, { + 0x14e4, 0x1644, 0x1028, 0x0106, 0, 0, BCM5700, 128, 32}, { + 0x14e4, 0x1644, 0x1028, 0x0109, 0, 0, BCM5700, 128, 32}, { + 0x14e4, 0x1644, 0x1028, 0x010a, 0, 0, BCM5700, 128, 32}, { + 0x14e4, 0x1644, 0x10b7, 0x1000, 0, 0, TC996T, 128, 32}, { + 0x14e4, 0x1644, 0x10b7, 0x1001, 0, 0, TC996ST, 128, 32}, { + 0x14e4, 0x1644, 0x10b7, 0x1002, 0, 0, TC996SSX, 128, 32}, { + 0x14e4, 0x1644, 0x10b7, 0x1003, 0, 0, TC997T, 128, 32}, { + 0x14e4, 0x1644, 0x10b7, 0x1005, 0, 0, TC997SX, 128, 32}, { + 0x14e4, 0x1644, 0x10b7, 0x1008, 0, 0, TC942BR01, 128, 32}, { + 0x14e4, 0x1644, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5700, 128, 32}, { + 0x14e4, 0x1645, 0x14e4, 1, 0, 0, BCM5701A5, 128, 32}, { + 0x14e4, 0x1645, 0x14e4, 5, 0, 0, BCM5701T1, 128, 32}, { + 0x14e4, 0x1645, 0x14e4, 6, 0, 0, BCM5701T8, 128, 32}, { + 0x14e4, 0x1645, 0x14e4, 7, 0, 0, BCM5701A7, 128, 32}, { + 0x14e4, 0x1645, 0x14e4, 8, 0, 0, BCM5701A10, 128, 32}, { + 0x14e4, 0x1645, 0x14e4, 0x8008, 0, 0, BCM5701A12, 128, 32}, { + 0x14e4, 0x1645, 0x0e11, 0xc1, 0, 0, NC6770, 128, 32}, { + 0x14e4, 0x1645, 0x0e11, 0x7c, 0, 0, NC7770, 128, 32}, { + 0x14e4, 0x1645, 0x0e11, 0x85, 0, 0, NC7780, 128, 32}, { + 0x14e4, 0x1645, 0x1028, 0x0121, 0, 0, BCM5701, 128, 32}, { + 0x14e4, 0x1645, 0x10b7, 0x1004, 0, 0, TC996SX, 128, 32}, { + 0x14e4, 0x1645, 0x10b7, 0x1006, 0, 0, TC996BT, 128, 32}, { + 0x14e4, 0x1645, 0x10b7, 0x1007, 0, 0, TC1000T, 128, 32}, { + 0x14e4, 0x1645, 0x10b7, 0x1008, 0, 0, TC940BR01, 128, 32}, { + 0x14e4, 0x1645, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5701, 128, 32}, { + 0x14e4, 0x1646, 0x14e4, 0x8009, 0, 0, BCM5702, 128, 32}, { + 0x14e4, 0x1646, 0x0e11, 0xbb, 0, 0, NC7760, 128, 32}, { + 0x14e4, 0x1646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5702, 128, 32}, { + 0x14e4, 0x16a6, 0x14e4, 0x8009, 0, 0, BCM5702, 128, 32}, { + 0x14e4, 0x16a6, 0x0e11, 0xbb, 0, 0, NC7760, 128, 32}, { + 0x14e4, 0x16a6, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5702, 128, 32}, { + 0x14e4, 0x1647, 0x14e4, 0x0009, 0, 0, BCM5703, 128, 32}, { + 0x14e4, 0x1647, 0x14e4, 0x000a, 0, 0, BCM5703A31, 128, 32}, { + 0x14e4, 0x1647, 0x14e4, 0x000b, 0, 0, BCM5703, 128, 32}, { + 0x14e4, 0x1647, 0x14e4, 0x800a, 0, 0, BCM5703, 128, 32}, { + 0x14e4, 0x1647, 0x0e11, 0x9a, 0, 0, NC7770, 128, 32}, { + 0x14e4, 0x1647, 0x0e11, 0x99, 0, 0, NC7780, 128, 32}, { + 0x14e4, 0x1647, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5703, 128, 32}, { + 0x14e4, 0x16a7, 0x14e4, 0x0009, 0, 0, BCM5703, 128, 32}, { + 0x14e4, 0x16a7, 0x14e4, 0x000a, 0, 0, BCM5703A31, 128, 32}, { + 0x14e4, 0x16a7, 0x14e4, 0x000b, 0, 0, BCM5703, 128, 32}, { + 0x14e4, 0x16a7, 0x14e4, 0x800a, 0, 0, BCM5703, 128, 32}, { + 0x14e4, 0x16a7, 0x0e11, 0x9a, 0, 0, NC7770, 128, 32}, { + 0x14e4, 0x16a7, 0x0e11, 0x99, 0, 0, NC7780, 128, 32}, { + 0x14e4, 0x16a7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5703, 128, 32} }; #define n570xDevices (sizeof(bcm570xDevices)/sizeof(bcm570xDevices[0])) - /* * Allocate a packet buffer from the bcm570x packet pool. */ -void * -bcm570xPktAlloc(int u, int pksize) +void *bcm570xPktAlloc (int u, int pksize) { - return malloc(pksize); + return malloc (pksize); } /* * Free a packet previously allocated from the bcm570x packet * buffer pool. */ -void -bcm570xPktFree(int u, void *p) +void bcm570xPktFree (int u, void *p) { - free(p); + free (p); } -int -bcm570xReplenishRxBuffers(PUM_DEVICE_BLOCK pUmDevice) +int bcm570xReplenishRxBuffers (PUM_DEVICE_BLOCK pUmDevice) { - PLM_PACKET pPacket; - PUM_PACKET pUmPacket; - void *skb; - int queue_rx = 0; - int ret = 0; + PLM_PACKET pPacket; + PUM_PACKET pUmPacket; + void *skb; + int queue_rx = 0; + int ret = 0; - while ((pUmPacket = (PUM_PACKET) - QQ_PopHead(&pUmDevice->rx_out_of_buf_q.Container)) != 0) { + while ((pUmPacket = (PUM_PACKET) + QQ_PopHead (&pUmDevice->rx_out_of_buf_q.Container)) != 0) { - pPacket = (PLM_PACKET) pUmPacket; + pPacket = (PLM_PACKET) pUmPacket; - /* reuse an old skb */ - if (pUmPacket->skbuff) { - QQ_PushTail(&pDevice->RxPacketFreeQ.Container, pPacket); - queue_rx = 1; - continue; - } - if ( ( skb = bcm570xPktAlloc(pUmDevice->index, - pPacket->u.Rx.RxBufferSize + 2)) == 0) { - QQ_PushHead(&pUmDevice->rx_out_of_buf_q.Container,pPacket); - printf("NOTICE: Out of RX memory.\n"); - ret = 1; - break; + /* reuse an old skb */ + if (pUmPacket->skbuff) { + QQ_PushTail (&pDevice->RxPacketFreeQ.Container, + pPacket); + queue_rx = 1; + continue; + } + if ((skb = bcm570xPktAlloc (pUmDevice->index, + pPacket->u.Rx.RxBufferSize + 2)) == + 0) { + QQ_PushHead (&pUmDevice->rx_out_of_buf_q.Container, + pPacket); + printf ("NOTICE: Out of RX memory.\n"); + ret = 1; + break; + } + + pUmPacket->skbuff = skb; + QQ_PushTail (&pDevice->RxPacketFreeQ.Container, pPacket); + queue_rx = 1; } - pUmPacket->skbuff = skb; - QQ_PushTail(&pDevice->RxPacketFreeQ.Container, pPacket); - queue_rx = 1; - } + if (queue_rx) { + LM_QueueRxPackets (pDevice); + } - if (queue_rx) { - LM_QueueRxPackets(pDevice); - } - - return ret; + return ret; } /* * Probe, Map, and Init 570x device. */ -int eth_init(bd_t *bis) +int eth_init (bd_t * bis) { - int i, rv, devFound = FALSE; - pci_dev_t devbusfn; - unsigned short status; + int i, rv, devFound = FALSE; + pci_dev_t devbusfn; + unsigned short status; - /* Find PCI device, if it exists, configure ... */ - for( i = 0; i < n570xDevices; i++){ - devbusfn = pci_find_device(bcm570xDevices[i].vendor_id, - bcm570xDevices[i].device_id, 0); - if(devbusfn == -1) { - continue; /* No device of that vendor/device ID */ + /* Find PCI device, if it exists, configure ... */ + for (i = 0; i < n570xDevices; i++) { + devbusfn = pci_find_device (bcm570xDevices[i].vendor_id, + bcm570xDevices[i].device_id, 0); + if (devbusfn == -1) { + continue; /* No device of that vendor/device ID */ + } else { + + /* Set ILINE */ + pci_write_config_byte (devbusfn, + PCI_INTERRUPT_LINE, + BCM570X_ILINE); + + /* + * 0x10 - 0x14 define one 64-bit MBAR. + * 0x14 is the higher-order address bits of the BAR. + */ + pci_write_config_dword (devbusfn, + PCI_BASE_ADDRESS_1, 0); + + ioBase = BCM570X_MBAR; + + pci_write_config_dword (devbusfn, + PCI_BASE_ADDRESS_0, ioBase); + + /* + * Enable PCI memory, IO, and Master -- don't + * reset any status bits in doing so. + */ + pci_read_config_word (devbusfn, PCI_COMMAND, &status); + + status |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER; + + pci_write_config_word (devbusfn, PCI_COMMAND, status); + + printf + ("\n%s: bus %d, device %d, function %d: MBAR=0x%x\n", + board_info[bcm570xDevices[i].board_id].name, + PCI_BUS (devbusfn), PCI_DEV (devbusfn), + PCI_FUNC (devbusfn), ioBase); + + /* Allocate once, but always clear on init */ + if (!pDevice) { + pDevice = malloc (sizeof (UM_DEVICE_BLOCK)); + pUmDevice = (PUM_DEVICE_BLOCK) pDevice; + memset (pDevice, 0x0, sizeof (UM_DEVICE_BLOCK)); + } + + /* Configure pci dev structure */ + pUmDevice->pdev = devbusfn; + pUmDevice->index = 0; + pUmDevice->tx_pkt = 0; + pUmDevice->rx_pkt = 0; + devFound = TRUE; + break; + } + } + + if (!devFound) { + printf + ("eth_init: FAILURE: no BCM570x Ethernet devices found.\n"); + return -1; + } + + /* Setup defaults for chip */ + pDevice->TaskToOffload = LM_TASK_OFFLOAD_NONE; + + if (pDevice->ChipRevId == T3_CHIP_ID_5700_B0) { + pDevice->TaskToOffload = LM_TASK_OFFLOAD_NONE; } else { - /* Set ILINE */ - pci_write_config_byte(devbusfn, - PCI_INTERRUPT_LINE, BCM570X_ILINE); + if (rx_checksum[i]) { + pDevice->TaskToOffload |= + LM_TASK_OFFLOAD_RX_TCP_CHECKSUM | + LM_TASK_OFFLOAD_RX_UDP_CHECKSUM; + } - /* - * 0x10 - 0x14 define one 64-bit MBAR. - * 0x14 is the higher-order address bits of the BAR. - */ - pci_write_config_dword(devbusfn, - PCI_BASE_ADDRESS_1, 0); - - ioBase = BCM570X_MBAR; - - pci_write_config_dword(devbusfn, - PCI_BASE_ADDRESS_0, ioBase); - - /* - * Enable PCI memory, IO, and Master -- don't - * reset any status bits in doing so. - */ - pci_read_config_word(devbusfn, - PCI_COMMAND, &status); - - status |= PCI_COMMAND_MEMORY|PCI_COMMAND_MASTER; - - pci_write_config_word(devbusfn, - PCI_COMMAND, status); - - printf("\n%s: bus %d, device %d, function %d: MBAR=0x%x\n", - board_info[bcm570xDevices[i].board_id].name, - PCI_BUS(devbusfn), - PCI_DEV(devbusfn), - PCI_FUNC(devbusfn), - ioBase); - - /* Allocate once, but always clear on init */ - if (!pDevice) { - pDevice = malloc(sizeof(UM_DEVICE_BLOCK)); - pUmDevice = (PUM_DEVICE_BLOCK)pDevice; - memset(pDevice, 0x0, sizeof(UM_DEVICE_BLOCK)); - } - - /* Configure pci dev structure */ - pUmDevice->pdev = devbusfn; - pUmDevice->index = 0; - pUmDevice->tx_pkt = 0; - pUmDevice->rx_pkt = 0; - devFound = TRUE; - break; - } - } - - if(!devFound){ - printf("eth_init: FAILURE: no BCM570x Ethernet devices found.\n"); - return -1; - } - - /* Setup defaults for chip */ - pDevice->TaskToOffload = LM_TASK_OFFLOAD_NONE; - - if (pDevice->ChipRevId == T3_CHIP_ID_5700_B0) { - pDevice->TaskToOffload = LM_TASK_OFFLOAD_NONE; - } else { - - if (rx_checksum[i]) { - pDevice->TaskToOffload |= - LM_TASK_OFFLOAD_RX_TCP_CHECKSUM | - LM_TASK_OFFLOAD_RX_UDP_CHECKSUM; + if (tx_checksum[i]) { + pDevice->TaskToOffload |= + LM_TASK_OFFLOAD_TX_TCP_CHECKSUM | + LM_TASK_OFFLOAD_TX_UDP_CHECKSUM; + pDevice->NoTxPseudoHdrChksum = TRUE; + } } - if (tx_checksum[i]) { - pDevice->TaskToOffload |= - LM_TASK_OFFLOAD_TX_TCP_CHECKSUM | - LM_TASK_OFFLOAD_TX_UDP_CHECKSUM; - pDevice->NoTxPseudoHdrChksum = TRUE; + /* Set Device PCI Memory base address */ + pDevice->pMappedMemBase = (PLM_UINT8) ioBase; + + /* Pull down adapter info */ + if ((rv = LM_GetAdapterInfo (pDevice)) != LM_STATUS_SUCCESS) { + printf ("bcm570xEnd: LM_GetAdapterInfo failed: rv=%d!\n", rv); + return -2; } - } - /* Set Device PCI Memory base address */ - pDevice->pMappedMemBase = (PLM_UINT8) ioBase; + /* Lock not needed */ + pUmDevice->do_global_lock = 0; - /* Pull down adapter info */ - if ((rv = LM_GetAdapterInfo(pDevice)) != LM_STATUS_SUCCESS) { - printf("bcm570xEnd: LM_GetAdapterInfo failed: rv=%d!\n", rv ); - return -2; - } + if (T3_ASIC_REV (pUmDevice->lm_dev.ChipRevId) == T3_ASIC_REV_5700) { + /* The 5700 chip works best without interleaved register */ + /* accesses on certain machines. */ + pUmDevice->do_global_lock = 1; + } - /* Lock not needed */ - pUmDevice->do_global_lock = 0; + /* Setup timer delays */ + if (T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5701) { + pDevice->UseTaggedStatus = TRUE; + pUmDevice->timer_interval = CFG_HZ; + } else { + pUmDevice->timer_interval = CFG_HZ / 50; + } - if (T3_ASIC_REV(pUmDevice->lm_dev.ChipRevId) == T3_ASIC_REV_5700) { - /* The 5700 chip works best without interleaved register */ - /* accesses on certain machines. */ - pUmDevice->do_global_lock = 1; - } + /* Grab name .... */ + pUmDevice->name = + (char *)malloc (strlen (board_info[bcm570xDevices[i].board_id].name) + + 1); + strcpy (pUmDevice->name, board_info[bcm570xDevices[i].board_id].name); - /* Setup timer delays */ - if (T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5701) { - pDevice->UseTaggedStatus = TRUE; - pUmDevice->timer_interval = CFG_HZ; - } - else { - pUmDevice->timer_interval = CFG_HZ / 50; - } + memcpy (pDevice->NodeAddress, bis->bi_enetaddr, 6); + LM_SetMacAddress (pDevice, bis->bi_enetaddr); + /* Init queues .. */ + QQ_InitQueue (&pUmDevice->rx_out_of_buf_q.Container, + MAX_RX_PACKET_DESC_COUNT); + pUmDevice->rx_last_cnt = pUmDevice->tx_last_cnt = 0; - /* Grab name .... */ - pUmDevice->name = - (char*)malloc(strlen(board_info[bcm570xDevices[i].board_id].name)+1); - strcpy(pUmDevice->name,board_info[bcm570xDevices[i].board_id].name); + /* delay for 4 seconds */ + pUmDevice->delayed_link_ind = (4 * CFG_HZ) / pUmDevice->timer_interval; - memcpy(pDevice->NodeAddress, bis->bi_enetaddr, 6); - LM_SetMacAddress(pDevice, bis->bi_enetaddr); - /* Init queues .. */ - QQ_InitQueue(&pUmDevice->rx_out_of_buf_q.Container, - MAX_RX_PACKET_DESC_COUNT); - pUmDevice->rx_last_cnt = pUmDevice->tx_last_cnt = 0; + pUmDevice->adaptive_expiry = CFG_HZ / pUmDevice->timer_interval; - /* delay for 4 seconds */ - pUmDevice->delayed_link_ind = - (4 * CFG_HZ) / pUmDevice->timer_interval; + /* Sometimes we get spurious ints. after reset when link is down. */ + /* This field tells the isr to service the int. even if there is */ + /* no status block update. */ + pUmDevice->adapter_just_inited = + (3 * CFG_HZ) / pUmDevice->timer_interval; - pUmDevice->adaptive_expiry = - CFG_HZ / pUmDevice->timer_interval; + /* Initialize 570x */ + if (LM_InitializeAdapter (pDevice) != LM_STATUS_SUCCESS) { + printf ("ERROR: Adapter initialization failed.\n"); + return ERROR; + } - /* Sometimes we get spurious ints. after reset when link is down. */ - /* This field tells the isr to service the int. even if there is */ - /* no status block update. */ - pUmDevice->adapter_just_inited = - (3 * CFG_HZ) / pUmDevice->timer_interval; + /* Enable chip ISR */ + LM_EnableInterrupt (pDevice); - /* Initialize 570x */ - if (LM_InitializeAdapter(pDevice) != LM_STATUS_SUCCESS) { - printf("ERROR: Adapter initialization failed.\n"); - return ERROR; - } + /* Clear MC table */ + LM_MulticastClear (pDevice); - /* Enable chip ISR */ - LM_EnableInterrupt(pDevice); + /* Enable Multicast */ + LM_SetReceiveMask (pDevice, + pDevice->ReceiveMask | LM_ACCEPT_ALL_MULTICAST); - /* Clear MC table */ - LM_MulticastClear(pDevice); + pUmDevice->opened = 1; + pUmDevice->tx_full = 0; + pUmDevice->tx_pkt = 0; + pUmDevice->rx_pkt = 0; + printf ("eth%d: %s @0x%lx,", + pDevice->index, pUmDevice->name, (unsigned long)ioBase); + printf ("node addr "); + for (i = 0; i < 6; i++) { + printf ("%2.2x", pDevice->NodeAddress[i]); + } + printf ("\n"); - /* Enable Multicast */ - LM_SetReceiveMask(pDevice, - pDevice->ReceiveMask | LM_ACCEPT_ALL_MULTICAST); + printf ("eth%d: ", pDevice->index); + printf ("%s with ", chip_rev[bcm570xDevices[i].board_id].name); - pUmDevice->opened = 1; - pUmDevice->tx_full = 0; - pUmDevice->tx_pkt = 0; - pUmDevice->rx_pkt = 0; - printf("eth%d: %s @0x%lx,", - pDevice->index, pUmDevice->name, (unsigned long)ioBase); - printf( "node addr "); - for (i = 0; i < 6; i++) { - printf("%2.2x", pDevice->NodeAddress[i]); - } - printf("\n"); + if ((pDevice->PhyId & PHY_ID_MASK) == PHY_BCM5400_PHY_ID) + printf ("Broadcom BCM5400 Copper "); + else if ((pDevice->PhyId & PHY_ID_MASK) == PHY_BCM5401_PHY_ID) + printf ("Broadcom BCM5401 Copper "); + else if ((pDevice->PhyId & PHY_ID_MASK) == PHY_BCM5411_PHY_ID) + printf ("Broadcom BCM5411 Copper "); + else if ((pDevice->PhyId & PHY_ID_MASK) == PHY_BCM5701_PHY_ID) + printf ("Broadcom BCM5701 Integrated Copper "); + else if ((pDevice->PhyId & PHY_ID_MASK) == PHY_BCM5703_PHY_ID) + printf ("Broadcom BCM5703 Integrated Copper "); + else if ((pDevice->PhyId & PHY_ID_MASK) == PHY_BCM8002_PHY_ID) + printf ("Broadcom BCM8002 SerDes "); + else if (pDevice->EnableTbi) + printf ("Agilent HDMP-1636 SerDes "); + else + printf ("Unknown "); + printf ("transceiver found\n"); - printf("eth%d: ", pDevice->index); - printf("%s with ", - chip_rev[bcm570xDevices[i].board_id].name); + printf ("eth%d: %s, MTU: %d,", + pDevice->index, pDevice->BusSpeedStr, 1500); - if ((pDevice->PhyId & PHY_ID_MASK) == PHY_BCM5400_PHY_ID) - printf("Broadcom BCM5400 Copper "); - else if ((pDevice->PhyId & PHY_ID_MASK) == PHY_BCM5401_PHY_ID) - printf("Broadcom BCM5401 Copper "); - else if ((pDevice->PhyId & PHY_ID_MASK) == PHY_BCM5411_PHY_ID) - printf("Broadcom BCM5411 Copper "); - else if ((pDevice->PhyId & PHY_ID_MASK) == PHY_BCM5701_PHY_ID) - printf("Broadcom BCM5701 Integrated Copper "); - else if ((pDevice->PhyId & PHY_ID_MASK) == PHY_BCM5703_PHY_ID) - printf("Broadcom BCM5703 Integrated Copper "); - else if ((pDevice->PhyId & PHY_ID_MASK) == PHY_BCM8002_PHY_ID) - printf("Broadcom BCM8002 SerDes "); - else if (pDevice->EnableTbi) - printf("Agilent HDMP-1636 SerDes "); - else - printf("Unknown "); - printf("transceiver found\n"); + if ((pDevice->ChipRevId != T3_CHIP_ID_5700_B0) && rx_checksum[i]) + printf ("Rx Checksum ON\n"); + else + printf ("Rx Checksum OFF\n"); + initialized++; - printf("eth%d: %s, MTU: %d,", - pDevice->index, pDevice->BusSpeedStr, 1500); - - if ((pDevice->ChipRevId != T3_CHIP_ID_5700_B0) && - rx_checksum[i]) - printf("Rx Checksum ON\n"); - else - printf("Rx Checksum OFF\n"); - initialized++; - - return 0; + return 0; } /* Ethernet Interrupt service routine */ -void -eth_isr(void) +void eth_isr (void) { - LM_UINT32 oldtag, newtag; - int i; + LM_UINT32 oldtag, newtag; + int i; - pUmDevice->interrupt = 1; + pUmDevice->interrupt = 1; - if (pDevice->UseTaggedStatus) { - if ((pDevice->pStatusBlkVirt->Status & STATUS_BLOCK_UPDATED) || - pUmDevice->adapter_just_inited) { - MB_REG_WR(pDevice, Mailbox.Interrupt[0].Low, 1); - oldtag = pDevice->pStatusBlkVirt->StatusTag; + if (pDevice->UseTaggedStatus) { + if ((pDevice->pStatusBlkVirt->Status & STATUS_BLOCK_UPDATED) || + pUmDevice->adapter_just_inited) { + MB_REG_WR (pDevice, Mailbox.Interrupt[0].Low, 1); + oldtag = pDevice->pStatusBlkVirt->StatusTag; - for (i = 0; ; i++) { - pDevice->pStatusBlkVirt->Status &= ~STATUS_BLOCK_UPDATED; - LM_ServiceInterrupts(pDevice); - newtag = pDevice->pStatusBlkVirt->StatusTag; - if ((newtag == oldtag) || (i > 50)) { - MB_REG_WR(pDevice, Mailbox.Interrupt[0].Low, newtag << 24); - if (pDevice->UndiFix) { - REG_WR(pDevice, Grc.LocalCtrl, - pDevice->GrcLocalCtrl | 0x2); - } - break; - } - oldtag = newtag; - } + for (i = 0;; i++) { + pDevice->pStatusBlkVirt->Status &= + ~STATUS_BLOCK_UPDATED; + LM_ServiceInterrupts (pDevice); + newtag = pDevice->pStatusBlkVirt->StatusTag; + if ((newtag == oldtag) || (i > 50)) { + MB_REG_WR (pDevice, + Mailbox.Interrupt[0].Low, + newtag << 24); + if (pDevice->UndiFix) { + REG_WR (pDevice, Grc.LocalCtrl, + pDevice-> + GrcLocalCtrl | 0x2); + } + break; + } + oldtag = newtag; + } + } + } else { + while (pDevice->pStatusBlkVirt->Status & STATUS_BLOCK_UPDATED) { + unsigned int dummy; + + pDevice->pMemView->Mailbox.Interrupt[0].Low = 1; + pDevice->pStatusBlkVirt->Status &= + ~STATUS_BLOCK_UPDATED; + LM_ServiceInterrupts (pDevice); + pDevice->pMemView->Mailbox.Interrupt[0].Low = 0; + dummy = pDevice->pMemView->Mailbox.Interrupt[0].Low; + } } - } - else { - while (pDevice->pStatusBlkVirt->Status & STATUS_BLOCK_UPDATED) { - unsigned int dummy; - pDevice->pMemView->Mailbox.Interrupt[0].Low = 1; - pDevice->pStatusBlkVirt->Status &= ~STATUS_BLOCK_UPDATED; - LM_ServiceInterrupts(pDevice); - pDevice->pMemView->Mailbox.Interrupt[0].Low = 0; - dummy = pDevice->pMemView->Mailbox.Interrupt[0].Low; + /* Allocate new RX buffers */ + if (QQ_GetEntryCnt (&pUmDevice->rx_out_of_buf_q.Container)) { + bcm570xReplenishRxBuffers (pUmDevice); } - } - /* Allocate new RX buffers */ - if (QQ_GetEntryCnt(&pUmDevice->rx_out_of_buf_q.Container)) { - bcm570xReplenishRxBuffers(pUmDevice); - } - - /* Queue packets */ - if (QQ_GetEntryCnt(&pDevice->RxPacketFreeQ.Container)) { - LM_QueueRxPackets(pDevice); - } - - if (pUmDevice->tx_queued) { - pUmDevice->tx_queued = 0; - } - - if(pUmDevice->tx_full){ - if(pDevice->LinkStatus != LM_STATUS_LINK_DOWN){ - printf("NOTICE: tx was previously blocked, restarting MUX\n"); - pUmDevice->tx_full = 0; + /* Queue packets */ + if (QQ_GetEntryCnt (&pDevice->RxPacketFreeQ.Container)) { + LM_QueueRxPackets (pDevice); } - } - pUmDevice->interrupt = 0; + if (pUmDevice->tx_queued) { + pUmDevice->tx_queued = 0; + } + + if (pUmDevice->tx_full) { + if (pDevice->LinkStatus != LM_STATUS_LINK_DOWN) { + printf + ("NOTICE: tx was previously blocked, restarting MUX\n"); + pUmDevice->tx_full = 0; + } + } + + pUmDevice->interrupt = 0; } -int -eth_send(volatile void *packet, int length) +int eth_send (volatile void *packet, int length) { - int status = 0; + int status = 0; #if ET_DEBUG - unsigned char* ptr = (unsigned char*)packet; + unsigned char *ptr = (unsigned char *)packet; #endif - PLM_PACKET pPacket; - PUM_PACKET pUmPacket; + PLM_PACKET pPacket; + PUM_PACKET pUmPacket; - /* Link down, return */ - while(pDevice->LinkStatus == LM_STATUS_LINK_DOWN) { + /* Link down, return */ + while (pDevice->LinkStatus == LM_STATUS_LINK_DOWN) { #if 0 - printf("eth%d: link down - check cable or link partner.\n", - pUmDevice->index); + printf ("eth%d: link down - check cable or link partner.\n", + pUmDevice->index); #endif - eth_isr(); + eth_isr (); - /* Wait to see link for one-half a second before sending ... */ - udelay(1500000); + /* Wait to see link for one-half a second before sending ... */ + udelay (1500000); - } - - /* Clear sent flag */ - pUmDevice->tx_pkt = 0; - - /* Previously blocked */ - if(pUmDevice->tx_full){ - printf("eth%d: tx blocked.\n", pUmDevice->index); - return 0; - } - - pPacket = (PLM_PACKET) - QQ_PopHead(&pDevice->TxPacketFreeQ.Container); - - if (pPacket == 0) { - pUmDevice->tx_full = 1; - printf("bcm570xEndSend: TX full!\n"); - return 0; - } - - if (pDevice->SendBdLeft.counter == 0) { - pUmDevice->tx_full = 1; - printf("bcm570xEndSend: no more TX descriptors!\n"); - QQ_PushHead(&pDevice->TxPacketFreeQ.Container, pPacket); - return 0; - } - - if (length <= 0){ - printf("eth: bad packet size: %d\n", length); - goto out; - } - - /* Get packet buffers and fragment list */ - pUmPacket = (PUM_PACKET) pPacket; - /* Single DMA Descriptor transmit. - * Fragments may be provided, but one DMA descriptor max is - * used to send the packet. - */ - if (MM_CoalesceTxBuffer (pDevice, pPacket) != LM_STATUS_SUCCESS) { - if (pUmPacket->skbuff == NULL){ - /* Packet was discarded */ - printf("TX: failed (1)\n"); - status = 1; - } else{ - printf("TX: failed (2)\n"); - status = 2; - } - QQ_PushHead (&pDevice->TxPacketFreeQ.Container, pPacket); - return status; - } - - /* Copy packet to DMA buffer */ - memset(pUmPacket->skbuff, 0x0, MAX_PACKET_SIZE); - memcpy((void*)pUmPacket->skbuff, (void*)packet, length); - pPacket->PacketSize = length; - pPacket->Flags |= SND_BD_FLAG_END|SND_BD_FLAG_COAL_NOW; - pPacket->u.Tx.FragCount = 1; - /* We've already provided a frame ready for transmission */ - pPacket->Flags &= ~SND_BD_FLAG_TCP_UDP_CKSUM; - - if ( LM_SendPacket(pDevice, pPacket) == LM_STATUS_FAILURE){ - /* - * A lower level send failure will push the packet descriptor back - * in the free queue, so just deal with the VxWorks clusters. - */ - if (pUmPacket->skbuff == NULL){ - printf("TX failed (1)!\n"); - /* Packet was discarded */ - status = 3; - } else { - /* A resource problem ... */ - printf("TX failed (2)!\n"); - status = 4; } - if (QQ_GetEntryCnt(&pDevice->TxPacketFreeQ.Container) == 0) { - printf("TX: emptyQ!\n"); - pUmDevice->tx_full = 1; - } - } + /* Clear sent flag */ + pUmDevice->tx_pkt = 0; - while(pUmDevice->tx_pkt == 0){ - /* Service TX */ - eth_isr(); - } -#if ET_DEBUG - printf("eth_send: 0x%x, %d bytes\n" - "[%x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x] ...\n", - (int)pPacket, length, - ptr[0],ptr[1],ptr[2],ptr[3],ptr[4],ptr[5], - ptr[6],ptr[7],ptr[8],ptr[9],ptr[10],ptr[11],ptr[12], - ptr[13],ptr[14],ptr[15]); -#endif - pUmDevice->tx_pkt = 0; - QQ_PushHead(&pDevice->TxPacketFreeQ.Container, pPacket); - - /* Done with send */ - out: - return status; -} - - -/* Ethernet receive */ -int -eth_rx(void) -{ - PLM_PACKET pPacket = NULL; - PUM_PACKET pUmPacket = NULL; - void *skb; - int size=0; - - while(TRUE) { - - bcm570x_service_isr: - /* Pull down packet if it is there */ - eth_isr(); - - /* Indicate RX packets called */ - if(pUmDevice->rx_pkt){ - /* printf("eth_rx: got a packet...\n"); */ - pUmDevice->rx_pkt = 0; - } else { - /* printf("eth_rx: waiting for packet...\n"); */ - goto bcm570x_service_isr; + /* Previously blocked */ + if (pUmDevice->tx_full) { + printf ("eth%d: tx blocked.\n", pUmDevice->index); + return 0; } pPacket = (PLM_PACKET) - QQ_PopHead(&pDevice->RxPacketReceivedQ.Container); + QQ_PopHead (&pDevice->TxPacketFreeQ.Container); - if (pPacket == 0){ - printf("eth_rx: empty packet!\n"); - goto bcm570x_service_isr; + if (pPacket == 0) { + pUmDevice->tx_full = 1; + printf ("bcm570xEndSend: TX full!\n"); + return 0; } + if (pDevice->SendBdLeft.counter == 0) { + pUmDevice->tx_full = 1; + printf ("bcm570xEndSend: no more TX descriptors!\n"); + QQ_PushHead (&pDevice->TxPacketFreeQ.Container, pPacket); + return 0; + } + + if (length <= 0) { + printf ("eth: bad packet size: %d\n", length); + goto out; + } + + /* Get packet buffers and fragment list */ pUmPacket = (PUM_PACKET) pPacket; -#if ET_DEBUG - printf("eth_rx: packet @0x%x\n", - (int)pPacket); -#endif - /* If the packet generated an error, reuse buffer */ - if ((pPacket->PacketStatus != LM_STATUS_SUCCESS) || - ((size = pPacket->PacketSize) > pDevice->RxMtu)) { - - /* reuse skb */ - QQ_PushTail(&pDevice->RxPacketFreeQ.Container, pPacket); - printf("eth_rx: error in packet dma!\n"); - goto bcm570x_service_isr; + /* Single DMA Descriptor transmit. + * Fragments may be provided, but one DMA descriptor max is + * used to send the packet. + */ + if (MM_CoalesceTxBuffer (pDevice, pPacket) != LM_STATUS_SUCCESS) { + if (pUmPacket->skbuff == NULL) { + /* Packet was discarded */ + printf ("TX: failed (1)\n"); + status = 1; + } else { + printf ("TX: failed (2)\n"); + status = 2; + } + QQ_PushHead (&pDevice->TxPacketFreeQ.Container, pPacket); + return status; } - /* Set size and address */ - skb = pUmPacket->skbuff; - size = pPacket->PacketSize; + /* Copy packet to DMA buffer */ + memset (pUmPacket->skbuff, 0x0, MAX_PACKET_SIZE); + memcpy ((void *)pUmPacket->skbuff, (void *)packet, length); + pPacket->PacketSize = length; + pPacket->Flags |= SND_BD_FLAG_END | SND_BD_FLAG_COAL_NOW; + pPacket->u.Tx.FragCount = 1; + /* We've already provided a frame ready for transmission */ + pPacket->Flags &= ~SND_BD_FLAG_TCP_UDP_CKSUM; - /* Pass the packet up to the protocol - * layers. - */ - NetReceive(skb, size); + if (LM_SendPacket (pDevice, pPacket) == LM_STATUS_FAILURE) { + /* + * A lower level send failure will push the packet descriptor back + * in the free queue, so just deal with the VxWorks clusters. + */ + if (pUmPacket->skbuff == NULL) { + printf ("TX failed (1)!\n"); + /* Packet was discarded */ + status = 3; + } else { + /* A resource problem ... */ + printf ("TX failed (2)!\n"); + status = 4; + } - /* Free packet buffer */ - bcm570xPktFree (pUmDevice->index, skb); - pUmPacket->skbuff = NULL; + if (QQ_GetEntryCnt (&pDevice->TxPacketFreeQ.Container) == 0) { + printf ("TX: emptyQ!\n"); + pUmDevice->tx_full = 1; + } + } - /* Reuse SKB */ - QQ_PushTail(&pDevice->RxPacketFreeQ.Container, pPacket); + while (pUmDevice->tx_pkt == 0) { + /* Service TX */ + eth_isr (); + } +#if ET_DEBUG + printf ("eth_send: 0x%x, %d bytes\n" + "[%x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x] ...\n", + (int)pPacket, length, + ptr[0], ptr[1], ptr[2], ptr[3], ptr[4], ptr[5], + ptr[6], ptr[7], ptr[8], ptr[9], ptr[10], ptr[11], ptr[12], + ptr[13], ptr[14], ptr[15]); +#endif + pUmDevice->tx_pkt = 0; + QQ_PushHead (&pDevice->TxPacketFreeQ.Container, pPacket); - return 0; /* Got a packet, bail ... */ - } - return size; + /* Done with send */ + out: + return status; } +/* Ethernet receive */ +int eth_rx (void) +{ + PLM_PACKET pPacket = NULL; + PUM_PACKET pUmPacket = NULL; + void *skb; + int size = 0; + + while (TRUE) { + + bcm570x_service_isr: + /* Pull down packet if it is there */ + eth_isr (); + + /* Indicate RX packets called */ + if (pUmDevice->rx_pkt) { + /* printf("eth_rx: got a packet...\n"); */ + pUmDevice->rx_pkt = 0; + } else { + /* printf("eth_rx: waiting for packet...\n"); */ + goto bcm570x_service_isr; + } + + pPacket = (PLM_PACKET) + QQ_PopHead (&pDevice->RxPacketReceivedQ.Container); + + if (pPacket == 0) { + printf ("eth_rx: empty packet!\n"); + goto bcm570x_service_isr; + } + + pUmPacket = (PUM_PACKET) pPacket; +#if ET_DEBUG + printf ("eth_rx: packet @0x%x\n", (int)pPacket); +#endif + /* If the packet generated an error, reuse buffer */ + if ((pPacket->PacketStatus != LM_STATUS_SUCCESS) || + ((size = pPacket->PacketSize) > pDevice->RxMtu)) { + + /* reuse skb */ + QQ_PushTail (&pDevice->RxPacketFreeQ.Container, + pPacket); + printf ("eth_rx: error in packet dma!\n"); + goto bcm570x_service_isr; + } + + /* Set size and address */ + skb = pUmPacket->skbuff; + size = pPacket->PacketSize; + + /* Pass the packet up to the protocol + * layers. + */ + NetReceive (skb, size); + + /* Free packet buffer */ + bcm570xPktFree (pUmDevice->index, skb); + pUmPacket->skbuff = NULL; + + /* Reuse SKB */ + QQ_PushTail (&pDevice->RxPacketFreeQ.Container, pPacket); + + return 0; /* Got a packet, bail ... */ + } + return size; +} /* Shut down device */ -void -eth_halt(void) +void eth_halt (void) { - int i; - if ( initialized) - if (pDevice && pUmDevice && pUmDevice->opened){ - printf("\neth%d:%s,", pUmDevice->index, pUmDevice->name); - printf("HALT,"); - /* stop device */ - LM_Halt(pDevice); - printf("POWER DOWN,"); - LM_SetPowerState(pDevice, LM_POWER_STATE_D3); + int i; + if (initialized) + if (pDevice && pUmDevice && pUmDevice->opened) { + printf ("\neth%d:%s,", pUmDevice->index, + pUmDevice->name); + printf ("HALT,"); + /* stop device */ + LM_Halt (pDevice); + printf ("POWER DOWN,"); + LM_SetPowerState (pDevice, LM_POWER_STATE_D3); - /* Free the memory allocated by the device in tigon3 */ - for (i = 0; i < pUmDevice->mem_list_num; i++) { - if (pUmDevice->mem_list[i]) { - /* sanity check */ - if (pUmDevice->dma_list[i]) { /* cache-safe memory */ - free(pUmDevice->mem_list[i]); - } else { - free(pUmDevice->mem_list[i]); /* normal memory */ + /* Free the memory allocated by the device in tigon3 */ + for (i = 0; i < pUmDevice->mem_list_num; i++) { + if (pUmDevice->mem_list[i]) { + /* sanity check */ + if (pUmDevice->dma_list[i]) { /* cache-safe memory */ + free (pUmDevice->mem_list[i]); + } else { + free (pUmDevice->mem_list[i]); /* normal memory */ + } + } + } + pUmDevice->opened = 0; + free (pDevice); + pDevice = NULL; + pUmDevice = NULL; + initialized = 0; + printf ("done - offline.\n"); } - } - } - pUmDevice->opened = 0; - free(pDevice); - pDevice = NULL; - pUmDevice = NULL; - initialized = 0; - printf("done - offline.\n"); - } } - /* * * Middle Module: Interface between the HW driver (tigon3 modules) and @@ -843,409 +834,380 @@ eth_halt(void) */ /* Middle module dependency - size of a packet descriptor */ -int MM_Packet_Desc_Size = sizeof(UM_PACKET); - +int MM_Packet_Desc_Size = sizeof (UM_PACKET); LM_STATUS -MM_ReadConfig32(PLM_DEVICE_BLOCK pDevice, - LM_UINT32 Offset, - LM_UINT32 *pValue32) +MM_ReadConfig32 (PLM_DEVICE_BLOCK pDevice, + LM_UINT32 Offset, LM_UINT32 * pValue32) { - UM_DEVICE_BLOCK *pUmDevice; - pUmDevice = (UM_DEVICE_BLOCK *) pDevice; - pci_read_config_dword(pUmDevice->pdev, - Offset, (u32 *) pValue32); - return LM_STATUS_SUCCESS; -} - - -LM_STATUS -MM_WriteConfig32(PLM_DEVICE_BLOCK pDevice, - LM_UINT32 Offset, - LM_UINT32 Value32) -{ - UM_DEVICE_BLOCK *pUmDevice; - pUmDevice = (UM_DEVICE_BLOCK *) pDevice; - pci_write_config_dword(pUmDevice->pdev, - Offset, Value32); - return LM_STATUS_SUCCESS; -} - - -LM_STATUS -MM_ReadConfig16(PLM_DEVICE_BLOCK pDevice, - LM_UINT32 Offset, - LM_UINT16 *pValue16) -{ - UM_DEVICE_BLOCK *pUmDevice; - pUmDevice = (UM_DEVICE_BLOCK *) pDevice; - pci_read_config_word(pUmDevice->pdev, - Offset, (u16*) pValue16); - return LM_STATUS_SUCCESS; + UM_DEVICE_BLOCK *pUmDevice; + pUmDevice = (UM_DEVICE_BLOCK *) pDevice; + pci_read_config_dword (pUmDevice->pdev, Offset, (u32 *) pValue32); + return LM_STATUS_SUCCESS; } LM_STATUS -MM_WriteConfig16(PLM_DEVICE_BLOCK pDevice, - LM_UINT32 Offset, - LM_UINT16 Value16) +MM_WriteConfig32 (PLM_DEVICE_BLOCK pDevice, LM_UINT32 Offset, LM_UINT32 Value32) { - UM_DEVICE_BLOCK *pUmDevice; - pUmDevice = (UM_DEVICE_BLOCK *) pDevice; - pci_write_config_word(pUmDevice->pdev, - Offset, Value16); - return LM_STATUS_SUCCESS; -} - - -LM_STATUS -MM_AllocateSharedMemory(PLM_DEVICE_BLOCK pDevice, LM_UINT32 BlockSize, - PLM_VOID *pMemoryBlockVirt, - PLM_PHYSICAL_ADDRESS pMemoryBlockPhy, - LM_BOOL Cached) -{ - PLM_VOID pvirt; - PUM_DEVICE_BLOCK pUmDevice = (PUM_DEVICE_BLOCK) pDevice; - dma_addr_t mapping; - - pvirt = malloc(BlockSize); - mapping = (dma_addr_t)(pvirt); - if (!pvirt) - return LM_STATUS_FAILURE; - - pUmDevice->mem_list[pUmDevice->mem_list_num] = pvirt; - pUmDevice->dma_list[pUmDevice->mem_list_num] = mapping; - pUmDevice->mem_size_list[pUmDevice->mem_list_num++] = BlockSize; - memset(pvirt, 0, BlockSize); - - *pMemoryBlockVirt = (PLM_VOID) pvirt; - MM_SetAddr (pMemoryBlockPhy, (dma_addr_t) mapping); - - return LM_STATUS_SUCCESS; -} - - -LM_STATUS -MM_AllocateMemory(PLM_DEVICE_BLOCK pDevice, LM_UINT32 BlockSize, - PLM_VOID *pMemoryBlockVirt) -{ - PLM_VOID pvirt; - PUM_DEVICE_BLOCK pUmDevice = (PUM_DEVICE_BLOCK) pDevice; - - pvirt = malloc(BlockSize); - - if (!pvirt) - return LM_STATUS_FAILURE; - - pUmDevice->mem_list[pUmDevice->mem_list_num] = pvirt; - pUmDevice->dma_list[pUmDevice->mem_list_num] = 0; - pUmDevice->mem_size_list[pUmDevice->mem_list_num++] = BlockSize; - memset(pvirt, 0, BlockSize); - *pMemoryBlockVirt = pvirt; - - return LM_STATUS_SUCCESS; + UM_DEVICE_BLOCK *pUmDevice; + pUmDevice = (UM_DEVICE_BLOCK *) pDevice; + pci_write_config_dword (pUmDevice->pdev, Offset, Value32); + return LM_STATUS_SUCCESS; } LM_STATUS -MM_MapMemBase(PLM_DEVICE_BLOCK pDevice) +MM_ReadConfig16 (PLM_DEVICE_BLOCK pDevice, + LM_UINT32 Offset, LM_UINT16 * pValue16) { - printf("BCM570x PCI Memory base address @0x%x\n", - (unsigned int)pDevice->pMappedMemBase); - return LM_STATUS_SUCCESS; + UM_DEVICE_BLOCK *pUmDevice; + pUmDevice = (UM_DEVICE_BLOCK *) pDevice; + pci_read_config_word (pUmDevice->pdev, Offset, (u16 *) pValue16); + return LM_STATUS_SUCCESS; } LM_STATUS -MM_InitializeUmPackets(PLM_DEVICE_BLOCK pDevice) +MM_WriteConfig16 (PLM_DEVICE_BLOCK pDevice, LM_UINT32 Offset, LM_UINT16 Value16) { - int i; - void* skb; - PUM_DEVICE_BLOCK pUmDevice = (PUM_DEVICE_BLOCK) pDevice; - PUM_PACKET pUmPacket = NULL; - PLM_PACKET pPacket = NULL; + UM_DEVICE_BLOCK *pUmDevice; + pUmDevice = (UM_DEVICE_BLOCK *) pDevice; + pci_write_config_word (pUmDevice->pdev, Offset, Value16); + return LM_STATUS_SUCCESS; +} - for (i = 0; i < pDevice->RxPacketDescCnt; i++) { - pPacket = QQ_PopHead(&pDevice->RxPacketFreeQ.Container); - pUmPacket = (PUM_PACKET) pPacket; +LM_STATUS +MM_AllocateSharedMemory (PLM_DEVICE_BLOCK pDevice, LM_UINT32 BlockSize, + PLM_VOID * pMemoryBlockVirt, + PLM_PHYSICAL_ADDRESS pMemoryBlockPhy, LM_BOOL Cached) +{ + PLM_VOID pvirt; + PUM_DEVICE_BLOCK pUmDevice = (PUM_DEVICE_BLOCK) pDevice; + dma_addr_t mapping; - if (pPacket == 0) { - printf("MM_InitializeUmPackets: Bad RxPacketFreeQ\n"); + pvirt = malloc (BlockSize); + mapping = (dma_addr_t) (pvirt); + if (!pvirt) + return LM_STATUS_FAILURE; + + pUmDevice->mem_list[pUmDevice->mem_list_num] = pvirt; + pUmDevice->dma_list[pUmDevice->mem_list_num] = mapping; + pUmDevice->mem_size_list[pUmDevice->mem_list_num++] = BlockSize; + memset (pvirt, 0, BlockSize); + + *pMemoryBlockVirt = (PLM_VOID) pvirt; + MM_SetAddr (pMemoryBlockPhy, (dma_addr_t) mapping); + + return LM_STATUS_SUCCESS; +} + +LM_STATUS +MM_AllocateMemory (PLM_DEVICE_BLOCK pDevice, LM_UINT32 BlockSize, + PLM_VOID * pMemoryBlockVirt) +{ + PLM_VOID pvirt; + PUM_DEVICE_BLOCK pUmDevice = (PUM_DEVICE_BLOCK) pDevice; + + pvirt = malloc (BlockSize); + + if (!pvirt) + return LM_STATUS_FAILURE; + + pUmDevice->mem_list[pUmDevice->mem_list_num] = pvirt; + pUmDevice->dma_list[pUmDevice->mem_list_num] = 0; + pUmDevice->mem_size_list[pUmDevice->mem_list_num++] = BlockSize; + memset (pvirt, 0, BlockSize); + *pMemoryBlockVirt = pvirt; + + return LM_STATUS_SUCCESS; +} + +LM_STATUS MM_MapMemBase (PLM_DEVICE_BLOCK pDevice) +{ + printf ("BCM570x PCI Memory base address @0x%x\n", + (unsigned int)pDevice->pMappedMemBase); + return LM_STATUS_SUCCESS; +} + +LM_STATUS MM_InitializeUmPackets (PLM_DEVICE_BLOCK pDevice) +{ + int i; + void *skb; + PUM_DEVICE_BLOCK pUmDevice = (PUM_DEVICE_BLOCK) pDevice; + PUM_PACKET pUmPacket = NULL; + PLM_PACKET pPacket = NULL; + + for (i = 0; i < pDevice->RxPacketDescCnt; i++) { + pPacket = QQ_PopHead (&pDevice->RxPacketFreeQ.Container); + pUmPacket = (PUM_PACKET) pPacket; + + if (pPacket == 0) { + printf ("MM_InitializeUmPackets: Bad RxPacketFreeQ\n"); + } + + skb = bcm570xPktAlloc (pUmDevice->index, + pPacket->u.Rx.RxBufferSize + 2); + + if (skb == 0) { + pUmPacket->skbuff = 0; + QQ_PushTail (&pUmDevice->rx_out_of_buf_q.Container, + pPacket); + printf ("MM_InitializeUmPackets: out of buffer.\n"); + continue; + } + + pUmPacket->skbuff = skb; + QQ_PushTail (&pDevice->RxPacketFreeQ.Container, pPacket); } - skb = bcm570xPktAlloc(pUmDevice->index, - pPacket->u.Rx.RxBufferSize + 2); + pUmDevice->rx_low_buf_thresh = pDevice->RxPacketDescCnt / 8; - if (skb == 0) { - pUmPacket->skbuff = 0; - QQ_PushTail(&pUmDevice->rx_out_of_buf_q.Container, pPacket); - printf("MM_InitializeUmPackets: out of buffer.\n"); - continue; - } - - pUmPacket->skbuff = skb; - QQ_PushTail(&pDevice->RxPacketFreeQ.Container, pPacket); - } - - pUmDevice->rx_low_buf_thresh = pDevice->RxPacketDescCnt / 8; - - return LM_STATUS_SUCCESS; + return LM_STATUS_SUCCESS; } -LM_STATUS -MM_GetConfig(PLM_DEVICE_BLOCK pDevice) +LM_STATUS MM_GetConfig (PLM_DEVICE_BLOCK pDevice) { - PUM_DEVICE_BLOCK pUmDevice = (PUM_DEVICE_BLOCK) pDevice; - int index = pDevice->index; + PUM_DEVICE_BLOCK pUmDevice = (PUM_DEVICE_BLOCK) pDevice; + int index = pDevice->index; - if (auto_speed[index] == 0) - pDevice->DisableAutoNeg = TRUE; - else - pDevice->DisableAutoNeg = FALSE; - - if (line_speed[index] == 0) { - pDevice->RequestedMediaType = - LM_REQUESTED_MEDIA_TYPE_AUTO; - pDevice->DisableAutoNeg = FALSE; - } - else { - if (line_speed[index] == 1000) { - if (pDevice->EnableTbi) { - pDevice->RequestedMediaType = - LM_REQUESTED_MEDIA_TYPE_FIBER_1000MBPS_FULL_DUPLEX; - } - else if (full_duplex[index]) { - pDevice->RequestedMediaType = - LM_REQUESTED_MEDIA_TYPE_UTP_1000MBPS_FULL_DUPLEX; - } - else { - pDevice->RequestedMediaType = - LM_REQUESTED_MEDIA_TYPE_UTP_1000MBPS; - } - if (!pDevice->EnableTbi) + if (auto_speed[index] == 0) + pDevice->DisableAutoNeg = TRUE; + else pDevice->DisableAutoNeg = FALSE; + + if (line_speed[index] == 0) { + pDevice->RequestedMediaType = LM_REQUESTED_MEDIA_TYPE_AUTO; + pDevice->DisableAutoNeg = FALSE; + } else { + if (line_speed[index] == 1000) { + if (pDevice->EnableTbi) { + pDevice->RequestedMediaType = + LM_REQUESTED_MEDIA_TYPE_FIBER_1000MBPS_FULL_DUPLEX; + } else if (full_duplex[index]) { + pDevice->RequestedMediaType = + LM_REQUESTED_MEDIA_TYPE_UTP_1000MBPS_FULL_DUPLEX; + } else { + pDevice->RequestedMediaType = + LM_REQUESTED_MEDIA_TYPE_UTP_1000MBPS; + } + if (!pDevice->EnableTbi) + pDevice->DisableAutoNeg = FALSE; + } else if (line_speed[index] == 100) { + if (full_duplex[index]) { + pDevice->RequestedMediaType = + LM_REQUESTED_MEDIA_TYPE_UTP_100MBPS_FULL_DUPLEX; + } else { + pDevice->RequestedMediaType = + LM_REQUESTED_MEDIA_TYPE_UTP_100MBPS; + } + } else if (line_speed[index] == 10) { + if (full_duplex[index]) { + pDevice->RequestedMediaType = + LM_REQUESTED_MEDIA_TYPE_UTP_10MBPS_FULL_DUPLEX; + } else { + pDevice->RequestedMediaType = + LM_REQUESTED_MEDIA_TYPE_UTP_10MBPS; + } + } else { + pDevice->RequestedMediaType = + LM_REQUESTED_MEDIA_TYPE_AUTO; + pDevice->DisableAutoNeg = FALSE; + } + } - else if (line_speed[index] == 100) { - if (full_duplex[index]) { - pDevice->RequestedMediaType = - LM_REQUESTED_MEDIA_TYPE_UTP_100MBPS_FULL_DUPLEX; - } - else { - pDevice->RequestedMediaType = - LM_REQUESTED_MEDIA_TYPE_UTP_100MBPS; - } + pDevice->FlowControlCap = 0; + if (rx_flow_control[index] != 0) { + pDevice->FlowControlCap |= LM_FLOW_CONTROL_RECEIVE_PAUSE; } - else if (line_speed[index] == 10) { - if (full_duplex[index]) { - pDevice->RequestedMediaType = - LM_REQUESTED_MEDIA_TYPE_UTP_10MBPS_FULL_DUPLEX; - } - else { - pDevice->RequestedMediaType = - LM_REQUESTED_MEDIA_TYPE_UTP_10MBPS; - } + if (tx_flow_control[index] != 0) { + pDevice->FlowControlCap |= LM_FLOW_CONTROL_TRANSMIT_PAUSE; } - else { - pDevice->RequestedMediaType = - LM_REQUESTED_MEDIA_TYPE_AUTO; - pDevice->DisableAutoNeg = FALSE; + if ((auto_flow_control[index] != 0) && + (pDevice->DisableAutoNeg == FALSE)) { + + pDevice->FlowControlCap |= LM_FLOW_CONTROL_AUTO_PAUSE; + if ((tx_flow_control[index] == 0) && + (rx_flow_control[index] == 0)) { + pDevice->FlowControlCap |= + LM_FLOW_CONTROL_TRANSMIT_PAUSE | + LM_FLOW_CONTROL_RECEIVE_PAUSE; + } } - } - pDevice->FlowControlCap = 0; - if (rx_flow_control[index] != 0) { - pDevice->FlowControlCap |= LM_FLOW_CONTROL_RECEIVE_PAUSE; - } - if (tx_flow_control[index] != 0) { - pDevice->FlowControlCap |= LM_FLOW_CONTROL_TRANSMIT_PAUSE; - } - if ((auto_flow_control[index] != 0) && - (pDevice->DisableAutoNeg == FALSE)) { - - pDevice->FlowControlCap |= LM_FLOW_CONTROL_AUTO_PAUSE; - if ((tx_flow_control[index] == 0) && - (rx_flow_control[index] == 0)) { - pDevice->FlowControlCap |= - LM_FLOW_CONTROL_TRANSMIT_PAUSE | - LM_FLOW_CONTROL_RECEIVE_PAUSE; - } - } - - /* Default MTU for now */ - pUmDevice->mtu = 1500; + /* Default MTU for now */ + pUmDevice->mtu = 1500; #if T3_JUMBO_RCV_RCB_ENTRY_COUNT - if (pUmDevice->mtu > 1500) { - pDevice->RxMtu = pUmDevice->mtu; - pDevice->RxJumboDescCnt = DEFAULT_JUMBO_RCV_DESC_COUNT; - } - else { - pDevice->RxJumboDescCnt = 0; - } - pDevice->RxJumboDescCnt = rx_jumbo_desc_cnt[index]; + if (pUmDevice->mtu > 1500) { + pDevice->RxMtu = pUmDevice->mtu; + pDevice->RxJumboDescCnt = DEFAULT_JUMBO_RCV_DESC_COUNT; + } else { + pDevice->RxJumboDescCnt = 0; + } + pDevice->RxJumboDescCnt = rx_jumbo_desc_cnt[index]; #else - pDevice->RxMtu = pUmDevice->mtu; + pDevice->RxMtu = pUmDevice->mtu; #endif - if (T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5701) { - pDevice->UseTaggedStatus = TRUE; - pUmDevice->timer_interval = CFG_HZ; - } - else { - pUmDevice->timer_interval = CFG_HZ/50; - } - - pDevice->TxPacketDescCnt = tx_pkt_desc_cnt[index]; - pDevice->RxStdDescCnt = rx_std_desc_cnt[index]; - /* Note: adaptive coalescence really isn't adaptive in this driver */ - pUmDevice->rx_adaptive_coalesce = rx_adaptive_coalesce[index]; - if (!pUmDevice->rx_adaptive_coalesce) { - pDevice->RxCoalescingTicks = rx_coalesce_ticks[index]; - if (pDevice->RxCoalescingTicks > MAX_RX_COALESCING_TICKS) - pDevice->RxCoalescingTicks = MAX_RX_COALESCING_TICKS; - pUmDevice->rx_curr_coalesce_ticks =pDevice->RxCoalescingTicks; - - pDevice->RxMaxCoalescedFrames = rx_max_coalesce_frames[index]; - if (pDevice->RxMaxCoalescedFrames>MAX_RX_MAX_COALESCED_FRAMES) - pDevice->RxMaxCoalescedFrames = - MAX_RX_MAX_COALESCED_FRAMES; - pUmDevice->rx_curr_coalesce_frames = - pDevice->RxMaxCoalescedFrames; - pDevice->StatsCoalescingTicks = stats_coalesce_ticks[index]; - if (pDevice->StatsCoalescingTicks>MAX_STATS_COALESCING_TICKS) - pDevice->StatsCoalescingTicks= - MAX_STATS_COALESCING_TICKS; - } - else { - pUmDevice->rx_curr_coalesce_frames = - DEFAULT_RX_MAX_COALESCED_FRAMES; - pUmDevice->rx_curr_coalesce_ticks = - DEFAULT_RX_COALESCING_TICKS; - } - pDevice->TxCoalescingTicks = tx_coalesce_ticks[index]; - if (pDevice->TxCoalescingTicks > MAX_TX_COALESCING_TICKS) - pDevice->TxCoalescingTicks = MAX_TX_COALESCING_TICKS; - pDevice->TxMaxCoalescedFrames = tx_max_coalesce_frames[index]; - if (pDevice->TxMaxCoalescedFrames > MAX_TX_MAX_COALESCED_FRAMES) - pDevice->TxMaxCoalescedFrames = MAX_TX_MAX_COALESCED_FRAMES; - - if (enable_wol[index]) { - pDevice->WakeUpModeCap = LM_WAKE_UP_MODE_MAGIC_PACKET; - pDevice->WakeUpMode = LM_WAKE_UP_MODE_MAGIC_PACKET; - } - pDevice->NicSendBd = TRUE; - - /* Don't update status blocks during interrupt */ - pDevice->RxCoalescingTicksDuringInt = 0; - pDevice->TxCoalescingTicksDuringInt = 0; - - return LM_STATUS_SUCCESS; - -} - - -LM_STATUS -MM_StartTxDma(PLM_DEVICE_BLOCK pDevice, PLM_PACKET pPacket) -{ - PUM_DEVICE_BLOCK pUmDevice = (PUM_DEVICE_BLOCK) pDevice; - printf("Start TX DMA: dev=%d packet @0x%x\n", - (int)pUmDevice->index, (unsigned int)pPacket); - - return LM_STATUS_SUCCESS; -} - -LM_STATUS -MM_CompleteTxDma(PLM_DEVICE_BLOCK pDevice, PLM_PACKET pPacket) -{ - PUM_DEVICE_BLOCK pUmDevice = (PUM_DEVICE_BLOCK) pDevice; - printf("Complete TX DMA: dev=%d packet @0x%x\n", - (int)pUmDevice->index, (unsigned int)pPacket); - return LM_STATUS_SUCCESS; -} - - -LM_STATUS -MM_IndicateStatus(PLM_DEVICE_BLOCK pDevice, LM_STATUS Status) -{ - char buf[128]; - char lcd[4]; - PUM_DEVICE_BLOCK pUmDevice = (PUM_DEVICE_BLOCK) pDevice; - LM_FLOW_CONTROL flow_control; - - pUmDevice->delayed_link_ind = 0; - memset(lcd, 0x0, 4); - - if (Status == LM_STATUS_LINK_DOWN) { - sprintf(buf,"eth%d: %s: NIC Link is down\n", - pUmDevice->index,pUmDevice->name); - lcd[0] = 'L';lcd[1]='N';lcd[2]='K';lcd[3] = '?'; - } else if (Status == LM_STATUS_LINK_ACTIVE) { - sprintf(buf,"eth%d:%s: ", pUmDevice->index, pUmDevice->name); - - if (pDevice->LineSpeed == LM_LINE_SPEED_1000MBPS){ - strcat(buf,"1000 Mbps "); - lcd[0] = '1';lcd[1]='G';lcd[2]='B'; - } else if (pDevice->LineSpeed == LM_LINE_SPEED_100MBPS){ - strcat(buf,"100 Mbps "); - lcd[0] = '1';lcd[1]='0';lcd[2]='0'; - } else if (pDevice->LineSpeed == LM_LINE_SPEED_10MBPS){ - strcat(buf,"10 Mbps "); - lcd[0] = '1';lcd[1]='0';lcd[2]=' '; - } - if (pDevice->DuplexMode == LM_DUPLEX_MODE_FULL){ - strcat(buf, "full duplex"); - lcd[3] = 'F'; + if (T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5701) { + pDevice->UseTaggedStatus = TRUE; + pUmDevice->timer_interval = CFG_HZ; } else { - strcat(buf, "half duplex"); - lcd[3] = 'H'; + pUmDevice->timer_interval = CFG_HZ / 50; } - strcat(buf, " link up"); - flow_control = pDevice->FlowControl & - (LM_FLOW_CONTROL_RECEIVE_PAUSE | - LM_FLOW_CONTROL_TRANSMIT_PAUSE); + pDevice->TxPacketDescCnt = tx_pkt_desc_cnt[index]; + pDevice->RxStdDescCnt = rx_std_desc_cnt[index]; + /* Note: adaptive coalescence really isn't adaptive in this driver */ + pUmDevice->rx_adaptive_coalesce = rx_adaptive_coalesce[index]; + if (!pUmDevice->rx_adaptive_coalesce) { + pDevice->RxCoalescingTicks = rx_coalesce_ticks[index]; + if (pDevice->RxCoalescingTicks > MAX_RX_COALESCING_TICKS) + pDevice->RxCoalescingTicks = MAX_RX_COALESCING_TICKS; + pUmDevice->rx_curr_coalesce_ticks = pDevice->RxCoalescingTicks; - if (flow_control) { - if (flow_control & LM_FLOW_CONTROL_RECEIVE_PAUSE) { - strcat(buf,", receive "); - if (flow_control & LM_FLOW_CONTROL_TRANSMIT_PAUSE) - strcat(buf," & transmit "); - } - else { - strcat(buf,", transmit "); - } - strcat(buf,"flow control ON"); + pDevice->RxMaxCoalescedFrames = rx_max_coalesce_frames[index]; + if (pDevice->RxMaxCoalescedFrames > MAX_RX_MAX_COALESCED_FRAMES) + pDevice->RxMaxCoalescedFrames = + MAX_RX_MAX_COALESCED_FRAMES; + pUmDevice->rx_curr_coalesce_frames = + pDevice->RxMaxCoalescedFrames; + pDevice->StatsCoalescingTicks = stats_coalesce_ticks[index]; + if (pDevice->StatsCoalescingTicks > MAX_STATS_COALESCING_TICKS) + pDevice->StatsCoalescingTicks = + MAX_STATS_COALESCING_TICKS; } else { - strcat(buf, ", flow control OFF"); + pUmDevice->rx_curr_coalesce_frames = + DEFAULT_RX_MAX_COALESCED_FRAMES; + pUmDevice->rx_curr_coalesce_ticks = DEFAULT_RX_COALESCING_TICKS; + } + pDevice->TxCoalescingTicks = tx_coalesce_ticks[index]; + if (pDevice->TxCoalescingTicks > MAX_TX_COALESCING_TICKS) + pDevice->TxCoalescingTicks = MAX_TX_COALESCING_TICKS; + pDevice->TxMaxCoalescedFrames = tx_max_coalesce_frames[index]; + if (pDevice->TxMaxCoalescedFrames > MAX_TX_MAX_COALESCED_FRAMES) + pDevice->TxMaxCoalescedFrames = MAX_TX_MAX_COALESCED_FRAMES; + + if (enable_wol[index]) { + pDevice->WakeUpModeCap = LM_WAKE_UP_MODE_MAGIC_PACKET; + pDevice->WakeUpMode = LM_WAKE_UP_MODE_MAGIC_PACKET; + } + pDevice->NicSendBd = TRUE; + + /* Don't update status blocks during interrupt */ + pDevice->RxCoalescingTicksDuringInt = 0; + pDevice->TxCoalescingTicksDuringInt = 0; + + return LM_STATUS_SUCCESS; + +} + +LM_STATUS MM_StartTxDma (PLM_DEVICE_BLOCK pDevice, PLM_PACKET pPacket) +{ + PUM_DEVICE_BLOCK pUmDevice = (PUM_DEVICE_BLOCK) pDevice; + printf ("Start TX DMA: dev=%d packet @0x%x\n", + (int)pUmDevice->index, (unsigned int)pPacket); + + return LM_STATUS_SUCCESS; +} + +LM_STATUS MM_CompleteTxDma (PLM_DEVICE_BLOCK pDevice, PLM_PACKET pPacket) +{ + PUM_DEVICE_BLOCK pUmDevice = (PUM_DEVICE_BLOCK) pDevice; + printf ("Complete TX DMA: dev=%d packet @0x%x\n", + (int)pUmDevice->index, (unsigned int)pPacket); + return LM_STATUS_SUCCESS; +} + +LM_STATUS MM_IndicateStatus (PLM_DEVICE_BLOCK pDevice, LM_STATUS Status) +{ + char buf[128]; + char lcd[4]; + PUM_DEVICE_BLOCK pUmDevice = (PUM_DEVICE_BLOCK) pDevice; + LM_FLOW_CONTROL flow_control; + + pUmDevice->delayed_link_ind = 0; + memset (lcd, 0x0, 4); + + if (Status == LM_STATUS_LINK_DOWN) { + sprintf (buf, "eth%d: %s: NIC Link is down\n", + pUmDevice->index, pUmDevice->name); + lcd[0] = 'L'; + lcd[1] = 'N'; + lcd[2] = 'K'; + lcd[3] = '?'; + } else if (Status == LM_STATUS_LINK_ACTIVE) { + sprintf (buf, "eth%d:%s: ", pUmDevice->index, pUmDevice->name); + + if (pDevice->LineSpeed == LM_LINE_SPEED_1000MBPS) { + strcat (buf, "1000 Mbps "); + lcd[0] = '1'; + lcd[1] = 'G'; + lcd[2] = 'B'; + } else if (pDevice->LineSpeed == LM_LINE_SPEED_100MBPS) { + strcat (buf, "100 Mbps "); + lcd[0] = '1'; + lcd[1] = '0'; + lcd[2] = '0'; + } else if (pDevice->LineSpeed == LM_LINE_SPEED_10MBPS) { + strcat (buf, "10 Mbps "); + lcd[0] = '1'; + lcd[1] = '0'; + lcd[2] = ' '; + } + if (pDevice->DuplexMode == LM_DUPLEX_MODE_FULL) { + strcat (buf, "full duplex"); + lcd[3] = 'F'; + } else { + strcat (buf, "half duplex"); + lcd[3] = 'H'; + } + strcat (buf, " link up"); + + flow_control = pDevice->FlowControl & + (LM_FLOW_CONTROL_RECEIVE_PAUSE | + LM_FLOW_CONTROL_TRANSMIT_PAUSE); + + if (flow_control) { + if (flow_control & LM_FLOW_CONTROL_RECEIVE_PAUSE) { + strcat (buf, ", receive "); + if (flow_control & + LM_FLOW_CONTROL_TRANSMIT_PAUSE) + strcat (buf, " & transmit "); + } else { + strcat (buf, ", transmit "); + } + strcat (buf, "flow control ON"); + } else { + strcat (buf, ", flow control OFF"); + } + strcat (buf, "\n"); + printf ("%s", buf); } - strcat(buf,"\n"); - printf("%s",buf); - } #if 0 - sysLedDsply(lcd[0],lcd[1],lcd[2],lcd[3]); + sysLedDsply (lcd[0], lcd[1], lcd[2], lcd[3]); #endif - return LM_STATUS_SUCCESS; + return LM_STATUS_SUCCESS; } -LM_STATUS -MM_FreeRxBuffer(PLM_DEVICE_BLOCK pDevice, PLM_PACKET pPacket) +LM_STATUS MM_FreeRxBuffer (PLM_DEVICE_BLOCK pDevice, PLM_PACKET pPacket) { - PUM_DEVICE_BLOCK pUmDevice = (PUM_DEVICE_BLOCK) pDevice; - PUM_PACKET pUmPacket; - void *skb; + PUM_DEVICE_BLOCK pUmDevice = (PUM_DEVICE_BLOCK) pDevice; + PUM_PACKET pUmPacket; + void *skb; - pUmPacket = (PUM_PACKET) pPacket; + pUmPacket = (PUM_PACKET) pPacket; - if ((skb = pUmPacket->skbuff)) - bcm570xPktFree(pUmDevice->index, skb); + if ((skb = pUmPacket->skbuff)) + bcm570xPktFree (pUmDevice->index, skb); - pUmPacket->skbuff = 0; + pUmPacket->skbuff = 0; - return LM_STATUS_SUCCESS; + return LM_STATUS_SUCCESS; } -unsigned long -MM_AnGetCurrentTime_us(PAN_STATE_INFO pAnInfo) +unsigned long MM_AnGetCurrentTime_us (PAN_STATE_INFO pAnInfo) { - return get_timer(0); + return get_timer (0); } /* @@ -1258,86 +1220,82 @@ MM_AnGetCurrentTime_us(PAN_STATE_INFO pAnInfo) * non-fatal. The incoming cluster chain is not freed, giving * the caller the choice of whether to try a retransmit later. */ -LM_STATUS -MM_CoalesceTxBuffer(PLM_DEVICE_BLOCK pDevice, PLM_PACKET pPacket) +LM_STATUS MM_CoalesceTxBuffer (PLM_DEVICE_BLOCK pDevice, PLM_PACKET pPacket) { - PUM_PACKET pUmPacket = (PUM_PACKET) pPacket; - PUM_DEVICE_BLOCK pUmDevice = (PUM_DEVICE_BLOCK) pDevice; - void *skbnew; - int len = 0; + PUM_PACKET pUmPacket = (PUM_PACKET) pPacket; + PUM_DEVICE_BLOCK pUmDevice = (PUM_DEVICE_BLOCK) pDevice; + void *skbnew; + int len = 0; + + if (len == 0) + return (LM_STATUS_SUCCESS); + + if (len > MAX_PACKET_SIZE) { + printf ("eth%d: xmit frame discarded, too big!, size = %d\n", + pUmDevice->index, len); + return (LM_STATUS_FAILURE); + } + + skbnew = bcm570xPktAlloc (pUmDevice->index, MAX_PACKET_SIZE); + + if (skbnew == NULL) { + pUmDevice->tx_full = 1; + printf ("eth%d: out of transmit buffers", pUmDevice->index); + return (LM_STATUS_FAILURE); + } + + /* New packet values */ + pUmPacket->skbuff = skbnew; + pUmPacket->lm_packet.u.Tx.FragCount = 1; - if (len == 0) return (LM_STATUS_SUCCESS); - - if (len > MAX_PACKET_SIZE){ - printf ("eth%d: xmit frame discarded, too big!, size = %d\n", - pUmDevice->index, len); - return (LM_STATUS_FAILURE); - } - - skbnew = bcm570xPktAlloc(pUmDevice->index, MAX_PACKET_SIZE); - - if (skbnew == NULL) { - pUmDevice->tx_full = 1; - printf ("eth%d: out of transmit buffers", pUmDevice->index); - return (LM_STATUS_FAILURE); - } - - /* New packet values */ - pUmPacket->skbuff = skbnew; - pUmPacket->lm_packet.u.Tx.FragCount = 1; - - return (LM_STATUS_SUCCESS); } - -LM_STATUS -MM_IndicateRxPackets(PLM_DEVICE_BLOCK pDevice) +LM_STATUS MM_IndicateRxPackets (PLM_DEVICE_BLOCK pDevice) { - PUM_DEVICE_BLOCK pUmDevice = (PUM_DEVICE_BLOCK) pDevice; - pUmDevice->rx_pkt = 1; - return LM_STATUS_SUCCESS; + PUM_DEVICE_BLOCK pUmDevice = (PUM_DEVICE_BLOCK) pDevice; + pUmDevice->rx_pkt = 1; + return LM_STATUS_SUCCESS; } -LM_STATUS -MM_IndicateTxPackets(PLM_DEVICE_BLOCK pDevice) +LM_STATUS MM_IndicateTxPackets (PLM_DEVICE_BLOCK pDevice) { - PUM_DEVICE_BLOCK pUmDevice = (PUM_DEVICE_BLOCK) pDevice; - PLM_PACKET pPacket; - PUM_PACKET pUmPacket; - void *skb; - while ( TRUE ) { + PUM_DEVICE_BLOCK pUmDevice = (PUM_DEVICE_BLOCK) pDevice; + PLM_PACKET pPacket; + PUM_PACKET pUmPacket; + void *skb; + while (TRUE) { - pPacket = (PLM_PACKET) - QQ_PopHead(&pDevice->TxPacketXmittedQ.Container); + pPacket = (PLM_PACKET) + QQ_PopHead (&pDevice->TxPacketXmittedQ.Container); - if (pPacket == 0) - break; + if (pPacket == 0) + break; - pUmPacket = (PUM_PACKET) pPacket; - skb = (void*)pUmPacket->skbuff; + pUmPacket = (PUM_PACKET) pPacket; + skb = (void *)pUmPacket->skbuff; - /* - * Free MBLK if we transmitted a fragmented packet or a - * non-fragmented packet straight from the VxWorks - * buffer pool. If packet was copied to a local transmit - * buffer, then there's no MBUF to free, just free - * the transmit buffer back to the cluster pool. - */ + /* + * Free MBLK if we transmitted a fragmented packet or a + * non-fragmented packet straight from the VxWorks + * buffer pool. If packet was copied to a local transmit + * buffer, then there's no MBUF to free, just free + * the transmit buffer back to the cluster pool. + */ - if (skb) - bcm570xPktFree (pUmDevice->index, skb); + if (skb) + bcm570xPktFree (pUmDevice->index, skb); - pUmPacket->skbuff = 0; - QQ_PushTail(&pDevice->TxPacketFreeQ.Container, pPacket); - pUmDevice->tx_pkt = 1; - } - if (pUmDevice->tx_full) { - if (QQ_GetEntryCnt(&pDevice->TxPacketFreeQ.Container) >= - (QQ_GetSize(&pDevice->TxPacketFreeQ.Container) >> 1)) - pUmDevice->tx_full = 0; - } - return LM_STATUS_SUCCESS; + pUmPacket->skbuff = 0; + QQ_PushTail (&pDevice->TxPacketFreeQ.Container, pPacket); + pUmDevice->tx_pkt = 1; + } + if (pUmDevice->tx_full) { + if (QQ_GetEntryCnt (&pDevice->TxPacketFreeQ.Container) >= + (QQ_GetSize (&pDevice->TxPacketFreeQ.Container) >> 1)) + pUmDevice->tx_full = 0; + } + return LM_STATUS_SUCCESS; } /* @@ -1345,16 +1303,12 @@ MM_IndicateTxPackets(PLM_DEVICE_BLOCK pDevice) * Return its length and physical address. */ void MM_MapTxDma - ( - PLM_DEVICE_BLOCK pDevice, - struct _LM_PACKET *pPacket, - T3_64BIT_HOST_ADDR *paddr, - LM_UINT32 *len, - int frag) -{ - PUM_PACKET pUmPacket = (PUM_PACKET) pPacket; - *len = pPacket->PacketSize; - MM_SetT3Addr(paddr, (dma_addr_t) pUmPacket->skbuff); + (PLM_DEVICE_BLOCK pDevice, + struct _LM_PACKET *pPacket, + T3_64BIT_HOST_ADDR * paddr, LM_UINT32 * len, int frag) { + PUM_PACKET pUmPacket = (PUM_PACKET) pPacket; + *len = pPacket->PacketSize; + MM_SetT3Addr (paddr, (dma_addr_t) pUmPacket->skbuff); } /* @@ -1362,35 +1316,31 @@ void MM_MapTxDma * to a physical address as seen from a PCI device. Store the * result at paddr. */ -void MM_MapRxDma( - PLM_DEVICE_BLOCK pDevice, - struct _LM_PACKET *pPacket, - T3_64BIT_HOST_ADDR *paddr) +void MM_MapRxDma (PLM_DEVICE_BLOCK pDevice, + struct _LM_PACKET *pPacket, T3_64BIT_HOST_ADDR * paddr) { - PUM_PACKET pUmPacket = (PUM_PACKET) pPacket; - MM_SetT3Addr(paddr, (dma_addr_t) pUmPacket->skbuff); + PUM_PACKET pUmPacket = (PUM_PACKET) pPacket; + MM_SetT3Addr (paddr, (dma_addr_t) pUmPacket->skbuff); } -void -MM_SetAddr (LM_PHYSICAL_ADDRESS *paddr, dma_addr_t addr) +void MM_SetAddr (LM_PHYSICAL_ADDRESS * paddr, dma_addr_t addr) { #if (BITS_PER_LONG == 64) - paddr->High = ((unsigned long) addr) >> 32; - paddr->Low = ((unsigned long) addr) & 0xffffffff; + paddr->High = ((unsigned long)addr) >> 32; + paddr->Low = ((unsigned long)addr) & 0xffffffff; #else paddr->High = 0; - paddr->Low = (unsigned long) addr; + paddr->Low = (unsigned long)addr; #endif } -void -MM_SetT3Addr(T3_64BIT_HOST_ADDR *paddr, dma_addr_t addr) +void MM_SetT3Addr (T3_64BIT_HOST_ADDR * paddr, dma_addr_t addr) { - unsigned long baddr = (unsigned long) addr; + unsigned long baddr = (unsigned long)addr; #if (BITS_PER_LONG == 64) - set_64bit_addr(paddr, baddr & 0xffffffff, baddr >> 32); + set_64bit_addr (paddr, baddr & 0xffffffff, baddr >> 32); #else - set_64bit_addr(paddr, baddr, 0); + set_64bit_addr (paddr, baddr, 0); #endif } @@ -1403,42 +1353,38 @@ MM_SetT3Addr(T3_64BIT_HOST_ADDR *paddr, dma_addr_t addr) * If any uses of the function remain, they will refer to the single copy * in the library. */ -void -atomic_set(atomic_t* entry, int val) +void atomic_set (atomic_t * entry, int val) { - entry->counter = val; -} -int -atomic_read(atomic_t* entry) -{ - return entry->counter; -} -void -atomic_inc(atomic_t* entry) -{ - if(entry) - entry->counter++; + entry->counter = val; } -void -atomic_dec(atomic_t* entry) +int atomic_read (atomic_t * entry) { - if(entry) - entry->counter--; + return entry->counter; } -void -atomic_sub(int a, atomic_t* entry) +void atomic_inc (atomic_t * entry) { - if(entry) - entry->counter -= a; + if (entry) + entry->counter++; } -void -atomic_add(int a, atomic_t* entry) +void atomic_dec (atomic_t * entry) { - if(entry) - entry->counter += a; + if (entry) + entry->counter--; +} + +void atomic_sub (int a, atomic_t * entry) +{ + if (entry) + entry->counter -= a; +} + +void atomic_add (int a, atomic_t * entry) +{ + if (entry) + entry->counter += a; } /******************************************************************************/ @@ -1446,68 +1392,57 @@ atomic_add(int a, atomic_t* entry) /* */ /* Return: */ /******************************************************************************/ -void -QQ_InitQueue( -PQQ_CONTAINER pQueue, -unsigned int QueueSize) { - pQueue->Head = 0; - pQueue->Tail = 0; - pQueue->Size = QueueSize+1; - atomic_set(&pQueue->EntryCnt, 0); -} /* QQ_InitQueue */ - +void QQ_InitQueue (PQQ_CONTAINER pQueue, unsigned int QueueSize) +{ + pQueue->Head = 0; + pQueue->Tail = 0; + pQueue->Size = QueueSize + 1; + atomic_set (&pQueue->EntryCnt, 0); +} /* QQ_InitQueue */ /******************************************************************************/ /* Description: */ /* */ /* Return: */ /******************************************************************************/ -char -QQ_Full( -PQQ_CONTAINER pQueue) { - unsigned int NewHead; +char QQ_Full (PQQ_CONTAINER pQueue) +{ + unsigned int NewHead; - NewHead = (pQueue->Head + 1) % pQueue->Size; - - return(NewHead == pQueue->Tail); -} /* QQ_Full */ + NewHead = (pQueue->Head + 1) % pQueue->Size; + return (NewHead == pQueue->Tail); +} /* QQ_Full */ /******************************************************************************/ /* Description: */ /* */ /* Return: */ /******************************************************************************/ -char -QQ_Empty( -PQQ_CONTAINER pQueue) { - return(pQueue->Head == pQueue->Tail); -} /* QQ_Empty */ - +char QQ_Empty (PQQ_CONTAINER pQueue) +{ + return (pQueue->Head == pQueue->Tail); +} /* QQ_Empty */ /******************************************************************************/ /* Description: */ /* */ /* Return: */ /******************************************************************************/ -unsigned int -QQ_GetSize( -PQQ_CONTAINER pQueue) { - return pQueue->Size; -} /* QQ_GetSize */ - +unsigned int QQ_GetSize (PQQ_CONTAINER pQueue) +{ + return pQueue->Size; +} /* QQ_GetSize */ /******************************************************************************/ /* Description: */ /* */ /* Return: */ /******************************************************************************/ -unsigned int -QQ_GetEntryCnt( -PQQ_CONTAINER pQueue) { - return atomic_read(&pQueue->EntryCnt); -} /* QQ_GetEntryCnt */ - +unsigned int QQ_GetEntryCnt (PQQ_CONTAINER pQueue) +{ + return atomic_read (&pQueue->EntryCnt); +} /* QQ_GetEntryCnt */ /******************************************************************************/ /* Description: */ @@ -1516,28 +1451,25 @@ PQQ_CONTAINER pQueue) { /* TRUE entry was added successfully. */ /* FALSE queue is full. */ /******************************************************************************/ -char -QQ_PushHead( -PQQ_CONTAINER pQueue, -PQQ_ENTRY pEntry) { - unsigned int Head; +char QQ_PushHead (PQQ_CONTAINER pQueue, PQQ_ENTRY pEntry) +{ + unsigned int Head; - Head = (pQueue->Head + 1) % pQueue->Size; + Head = (pQueue->Head + 1) % pQueue->Size; #if !defined(QQ_NO_OVERFLOW_CHECK) - if(Head == pQueue->Tail) { - return 0; - } /* if */ -#endif /* QQ_NO_OVERFLOW_CHECK */ + if (Head == pQueue->Tail) { + return 0; + } /* if */ +#endif /* QQ_NO_OVERFLOW_CHECK */ - pQueue->Array[pQueue->Head] = pEntry; - wmb(); - pQueue->Head = Head; - atomic_inc(&pQueue->EntryCnt); - - return -1; -} /* QQ_PushHead */ + pQueue->Array[pQueue->Head] = pEntry; + wmb (); + pQueue->Head = Head; + atomic_inc (&pQueue->EntryCnt); + return -1; +} /* QQ_PushHead */ /******************************************************************************/ /* Description: */ @@ -1546,146 +1478,126 @@ PQQ_ENTRY pEntry) { /* TRUE entry was added successfully. */ /* FALSE queue is full. */ /******************************************************************************/ -char -QQ_PushTail( -PQQ_CONTAINER pQueue, -PQQ_ENTRY pEntry) { - unsigned int Tail; +char QQ_PushTail (PQQ_CONTAINER pQueue, PQQ_ENTRY pEntry) +{ + unsigned int Tail; - Tail = pQueue->Tail; - if(Tail == 0) { - Tail = pQueue->Size; - } /* if */ - Tail--; + Tail = pQueue->Tail; + if (Tail == 0) { + Tail = pQueue->Size; + } /* if */ + Tail--; #if !defined(QQ_NO_OVERFLOW_CHECK) - if(Tail == pQueue->Head) { - return 0; - } /* if */ -#endif /* QQ_NO_OVERFLOW_CHECK */ + if (Tail == pQueue->Head) { + return 0; + } /* if */ +#endif /* QQ_NO_OVERFLOW_CHECK */ - pQueue->Array[Tail] = pEntry; - wmb(); - pQueue->Tail = Tail; - atomic_inc(&pQueue->EntryCnt); - - return -1; -} /* QQ_PushTail */ + pQueue->Array[Tail] = pEntry; + wmb (); + pQueue->Tail = Tail; + atomic_inc (&pQueue->EntryCnt); + return -1; +} /* QQ_PushTail */ /******************************************************************************/ /* Description: */ /* */ /* Return: */ /******************************************************************************/ -PQQ_ENTRY -QQ_PopHead( -PQQ_CONTAINER pQueue) { - unsigned int Head; - PQQ_ENTRY Entry; +PQQ_ENTRY QQ_PopHead (PQQ_CONTAINER pQueue) +{ + unsigned int Head; + PQQ_ENTRY Entry; - Head = pQueue->Head; + Head = pQueue->Head; #if !defined(QQ_NO_UNDERFLOW_CHECK) - if(Head == pQueue->Tail) { - return (PQQ_ENTRY) 0; - } /* if */ -#endif /* QQ_NO_UNDERFLOW_CHECK */ + if (Head == pQueue->Tail) { + return (PQQ_ENTRY) 0; + } /* if */ +#endif /* QQ_NO_UNDERFLOW_CHECK */ - if(Head == 0) { - Head = pQueue->Size; - } /* if */ - Head--; + if (Head == 0) { + Head = pQueue->Size; + } /* if */ + Head--; - Entry = pQueue->Array[Head]; - membar(); + Entry = pQueue->Array[Head]; + membar (); - pQueue->Head = Head; - atomic_dec(&pQueue->EntryCnt); - - return Entry; -} /* QQ_PopHead */ + pQueue->Head = Head; + atomic_dec (&pQueue->EntryCnt); + return Entry; +} /* QQ_PopHead */ /******************************************************************************/ /* Description: */ /* */ /* Return: */ /******************************************************************************/ -PQQ_ENTRY -QQ_PopTail( -PQQ_CONTAINER pQueue) { - unsigned int Tail; - PQQ_ENTRY Entry; +PQQ_ENTRY QQ_PopTail (PQQ_CONTAINER pQueue) +{ + unsigned int Tail; + PQQ_ENTRY Entry; - Tail = pQueue->Tail; + Tail = pQueue->Tail; #if !defined(QQ_NO_UNDERFLOW_CHECK) - if(Tail == pQueue->Head) { - return (PQQ_ENTRY) 0; - } /* if */ -#endif /* QQ_NO_UNDERFLOW_CHECK */ + if (Tail == pQueue->Head) { + return (PQQ_ENTRY) 0; + } /* if */ +#endif /* QQ_NO_UNDERFLOW_CHECK */ - Entry = pQueue->Array[Tail]; - membar(); - pQueue->Tail = (Tail + 1) % pQueue->Size; - atomic_dec(&pQueue->EntryCnt); - - return Entry; -} /* QQ_PopTail */ + Entry = pQueue->Array[Tail]; + membar (); + pQueue->Tail = (Tail + 1) % pQueue->Size; + atomic_dec (&pQueue->EntryCnt); + return Entry; +} /* QQ_PopTail */ /******************************************************************************/ /* Description: */ /* */ /* Return: */ /******************************************************************************/ -PQQ_ENTRY -QQ_GetHead( - PQQ_CONTAINER pQueue, - unsigned int Idx) +PQQ_ENTRY QQ_GetHead (PQQ_CONTAINER pQueue, unsigned int Idx) { - if(Idx >= atomic_read(&pQueue->EntryCnt)) - { - return (PQQ_ENTRY) 0; - } + if (Idx >= atomic_read (&pQueue->EntryCnt)) { + return (PQQ_ENTRY) 0; + } - if(pQueue->Head > Idx) - { - Idx = pQueue->Head - Idx; - } - else - { - Idx = pQueue->Size - (Idx - pQueue->Head); - } - Idx--; + if (pQueue->Head > Idx) { + Idx = pQueue->Head - Idx; + } else { + Idx = pQueue->Size - (Idx - pQueue->Head); + } + Idx--; - return pQueue->Array[Idx]; + return pQueue->Array[Idx]; } - /******************************************************************************/ /* Description: */ /* */ /* Return: */ /******************************************************************************/ -PQQ_ENTRY -QQ_GetTail( - PQQ_CONTAINER pQueue, - unsigned int Idx) +PQQ_ENTRY QQ_GetTail (PQQ_CONTAINER pQueue, unsigned int Idx) { - if(Idx >= atomic_read(&pQueue->EntryCnt)) - { - return (PQQ_ENTRY) 0; - } + if (Idx >= atomic_read (&pQueue->EntryCnt)) { + return (PQQ_ENTRY) 0; + } - Idx += pQueue->Tail; - if(Idx >= pQueue->Size) - { - Idx = Idx - pQueue->Size; - } + Idx += pQueue->Tail; + if (Idx >= pQueue->Size) { + Idx = Idx - pQueue->Size; + } - return pQueue->Array[Idx]; + return pQueue->Array[Idx]; } -#endif /* CFG_CMD_NET, !CONFIG_NET_MULTI, CONFIG_BCM570x */ +#endif /* CFG_CMD_NET, !CONFIG_NET_MULTI, CONFIG_BCM570x */ diff --git a/drivers/bcm570x_lm.h b/drivers/bcm570x_lm.h index 607f3fd06..2ea6ca8fa 100644 --- a/drivers/bcm570x_lm.h +++ b/drivers/bcm570x_lm.h @@ -19,29 +19,28 @@ #include "bcm570x_queue.h" #include "bcm570x_bits.h" - /******************************************************************************/ /* Basic types. */ /******************************************************************************/ -typedef char LM_CHAR, *PLM_CHAR; -typedef unsigned int LM_UINT, *PLM_UINT; -typedef unsigned char LM_UINT8, *PLM_UINT8; -typedef unsigned short LM_UINT16, *PLM_UINT16; -typedef unsigned int LM_UINT32, *PLM_UINT32; -typedef unsigned int LM_COUNTER, *PLM_COUNTER; -typedef void LM_VOID, *PLM_VOID; -typedef char LM_BOOL, *PLM_BOOL; +typedef char LM_CHAR, *PLM_CHAR; +typedef unsigned int LM_UINT, *PLM_UINT; +typedef unsigned char LM_UINT8, *PLM_UINT8; +typedef unsigned short LM_UINT16, *PLM_UINT16; +typedef unsigned int LM_UINT32, *PLM_UINT32; +typedef unsigned int LM_COUNTER, *PLM_COUNTER; +typedef void LM_VOID, *PLM_VOID; +typedef char LM_BOOL, *PLM_BOOL; /* 64bit value. */ typedef struct { #ifdef BIG_ENDIAN_HOST - LM_UINT32 High; - LM_UINT32 Low; -#else /* BIG_ENDIAN_HOST */ - LM_UINT32 Low; - LM_UINT32 High; -#endif /* !BIG_ENDIAN_HOST */ + LM_UINT32 High; + LM_UINT32 Low; +#else /* BIG_ENDIAN_HOST */ + LM_UINT32 Low; + LM_UINT32 High; +#endif /* !BIG_ENDIAN_HOST */ } LM_UINT64, *PLM_UINT64; typedef LM_UINT64 LM_PHYSICAL_ADDRESS, *PLM_PHYSICAL_ADDRESS; @@ -58,15 +57,13 @@ typedef LM_UINT64 LM_PHYSICAL_ADDRESS, *PLM_PHYSICAL_ADDRESS; } \ } - #ifndef NULL #define NULL ((void *) 0) -#endif /* NULL */ +#endif /* NULL */ #ifndef OFFSETOF #define OFFSETOF(_s, _m) (MM_UINT_PTR(&(((_s *) 0)->_m))) -#endif /* OFFSETOF */ - +#endif /* OFFSETOF */ /******************************************************************************/ /* Simple macros. */ @@ -100,26 +97,24 @@ typedef LM_UINT64 LM_PHYSICAL_ADDRESS, *PLM_PHYSICAL_ADDRESS; ((unsigned char *) (_Dst))[4] = ((unsigned char *) (_Src))[4]; \ ((unsigned char *) (_Dst))[5] = ((unsigned char *) (_Src))[5]; - /******************************************************************************/ /* Constants. */ /******************************************************************************/ #define ETHERNET_ADDRESS_SIZE 6 #define ETHERNET_PACKET_HEADER_SIZE 14 -#define MIN_ETHERNET_PACKET_SIZE 64 /* with 4 byte crc. */ -#define MAX_ETHERNET_PACKET_SIZE 1518 /* with 4 byte crc. */ +#define MIN_ETHERNET_PACKET_SIZE 64 /* with 4 byte crc. */ +#define MAX_ETHERNET_PACKET_SIZE 1518 /* with 4 byte crc. */ #define MIN_ETHERNET_PACKET_SIZE_NO_CRC 60 #define MAX_ETHERNET_PACKET_SIZE_NO_CRC 1514 -#define MAX_ETHERNET_PACKET_BUFFER_SIZE 1536 /* A nice even number. */ +#define MAX_ETHERNET_PACKET_BUFFER_SIZE 1536 /* A nice even number. */ #ifndef LM_MAX_MC_TABLE_SIZE #define LM_MAX_MC_TABLE_SIZE 32 -#endif /* LM_MAX_MC_TABLE_SIZE */ +#endif /* LM_MAX_MC_TABLE_SIZE */ #define LM_MC_ENTRY_SIZE (ETHERNET_ADDRESS_SIZE+1) #define LM_MC_INSTANCE_COUNT_INDEX (LM_MC_ENTRY_SIZE-1) - /* Receive filter masks. */ #define LM_ACCEPT_UNICAST 0x0001 #define LM_ACCEPT_MULTICAST 0x0002 @@ -129,7 +124,6 @@ typedef LM_UINT64 LM_PHYSICAL_ADDRESS, *PLM_PHYSICAL_ADDRESS; #define LM_PROMISCUOUS_MODE 0x10000 - /******************************************************************************/ /* PCI registers. */ /******************************************************************************/ @@ -169,20 +163,20 @@ typedef LM_UINT64 LM_PHYSICAL_ADDRESS, *PLM_PHYSICAL_ADDRESS; /******************************************************************************/ typedef struct { - LM_UINT32 FragSize; - LM_PHYSICAL_ADDRESS FragBuf; + LM_UINT32 FragSize; + LM_PHYSICAL_ADDRESS FragBuf; } LM_FRAG, *PLM_FRAG; typedef struct { - /* FragCount is initialized for the caller to the maximum array size, on */ - /* return FragCount is the number of the actual fragments in the array. */ - LM_UINT32 FragCount; + /* FragCount is initialized for the caller to the maximum array size, on */ + /* return FragCount is the number of the actual fragments in the array. */ + LM_UINT32 FragCount; - /* Total buffer size. */ - LM_UINT32 TotalSize; + /* Total buffer size. */ + LM_UINT32 TotalSize; - /* Fragment array buffer. */ - LM_FRAG Fragments[1]; + /* Fragment array buffer. */ + LM_FRAG Fragments[1]; } LM_FRAG_LIST, *PLM_FRAG_LIST; #define DECLARE_FRAG_LIST_BUFFER_TYPE(_FRAG_LIST_TYPE_NAME, _MAX_FRAG_COUNT) \ @@ -191,7 +185,6 @@ typedef struct { LM_FRAG FragListBuffer[_MAX_FRAG_COUNT-1]; \ } _FRAG_LIST_TYPE_NAME, *P##_FRAG_LIST_TYPE_NAME - /******************************************************************************/ /* Status codes. */ /******************************************************************************/ @@ -217,7 +210,6 @@ typedef struct { typedef LM_UINT LM_STATUS, *PLM_STATUS; - /******************************************************************************/ /* Requested media type. */ /******************************************************************************/ @@ -240,7 +232,6 @@ typedef LM_UINT LM_STATUS, *PLM_STATUS; typedef LM_UINT32 LM_REQUESTED_MEDIA_TYPE, *PLM_REQUESTED_MEDIA_TYPE; - /******************************************************************************/ /* Media type. */ /******************************************************************************/ @@ -254,7 +245,6 @@ typedef LM_UINT32 LM_REQUESTED_MEDIA_TYPE, *PLM_REQUESTED_MEDIA_TYPE; typedef LM_UINT32 LM_MEDIA_TYPE, *PLM_MEDIA_TYPE; - /******************************************************************************/ /* Line speed. */ /******************************************************************************/ @@ -266,7 +256,6 @@ typedef LM_UINT32 LM_MEDIA_TYPE, *PLM_MEDIA_TYPE; typedef LM_UINT32 LM_LINE_SPEED, *PLM_LINE_SPEED; - /******************************************************************************/ /* Duplex mode. */ /******************************************************************************/ @@ -277,7 +266,6 @@ typedef LM_UINT32 LM_LINE_SPEED, *PLM_LINE_SPEED; typedef LM_UINT32 LM_DUPLEX_MODE, *PLM_DUPLEX_MODE; - /******************************************************************************/ /* Power state. */ /******************************************************************************/ @@ -289,7 +277,6 @@ typedef LM_UINT32 LM_DUPLEX_MODE, *PLM_DUPLEX_MODE; typedef LM_UINT32 LM_POWER_STATE, *PLM_POWER_STATE; - /******************************************************************************/ /* Task offloading. */ /******************************************************************************/ @@ -305,7 +292,6 @@ typedef LM_UINT32 LM_POWER_STATE, *PLM_POWER_STATE; typedef LM_UINT32 LM_TASK_OFFLOAD, *PLM_TASK_OFFLOAD; - /******************************************************************************/ /* Flow control. */ /******************************************************************************/ @@ -324,7 +310,6 @@ typedef LM_UINT32 LM_TASK_OFFLOAD, *PLM_TASK_OFFLOAD; typedef LM_UINT32 LM_FLOW_CONTROL, *PLM_FLOW_CONTROL; - /******************************************************************************/ /* Wake up mode. */ /******************************************************************************/ @@ -336,7 +321,6 @@ typedef LM_UINT32 LM_FLOW_CONTROL, *PLM_FLOW_CONTROL; typedef LM_UINT32 LM_WAKE_UP_MODE, *PLM_WAKE_UP_MODE; - /******************************************************************************/ /* Counters. */ /******************************************************************************/ @@ -362,7 +346,6 @@ typedef LM_UINT32 LM_WAKE_UP_MODE, *PLM_WAKE_UP_MODE; typedef LM_UINT32 LM_COUNTER_TYPE, *PLM_COUNTER_TYPE; - /******************************************************************************/ /* Forward definition. */ /******************************************************************************/ @@ -370,82 +353,82 @@ typedef LM_UINT32 LM_COUNTER_TYPE, *PLM_COUNTER_TYPE; typedef struct _LM_DEVICE_BLOCK *PLM_DEVICE_BLOCK; typedef struct _LM_PACKET *PLM_PACKET; - /******************************************************************************/ /* Function prototypes. */ /******************************************************************************/ -LM_STATUS LM_GetAdapterInfo(PLM_DEVICE_BLOCK pDevice); -LM_STATUS LM_InitializeAdapter(PLM_DEVICE_BLOCK pDevice); -LM_STATUS LM_ResetAdapter(PLM_DEVICE_BLOCK pDevice); -LM_STATUS LM_DisableInterrupt(PLM_DEVICE_BLOCK pDevice); -LM_STATUS LM_EnableInterrupt(PLM_DEVICE_BLOCK pDevice); -LM_STATUS LM_SendPacket(PLM_DEVICE_BLOCK pDevice, PLM_PACKET pPacket); -LM_STATUS LM_ServiceInterrupts(PLM_DEVICE_BLOCK pDevice); -LM_STATUS LM_QueueRxPackets(PLM_DEVICE_BLOCK pDevice); -LM_STATUS LM_SetReceiveMask(PLM_DEVICE_BLOCK pDevice, LM_UINT32 Mask); -LM_STATUS LM_Halt(PLM_DEVICE_BLOCK pDevice); -LM_STATUS LM_Abort(PLM_DEVICE_BLOCK pDevice); -LM_STATUS LM_MulticastAdd(PLM_DEVICE_BLOCK pDevice, PLM_UINT8 pMcAddress); -LM_STATUS LM_MulticastDel(PLM_DEVICE_BLOCK pDevice, PLM_UINT8 pMcAddress); -LM_STATUS LM_MulticastClear(PLM_DEVICE_BLOCK pDevice); -LM_STATUS LM_SetMacAddress(PLM_DEVICE_BLOCK pDevice, PLM_UINT8 pMacAddress); -LM_STATUS LM_LoopbackAddress(PLM_DEVICE_BLOCK pDevice, PLM_UINT8 pAddress); +LM_STATUS LM_GetAdapterInfo (PLM_DEVICE_BLOCK pDevice); +LM_STATUS LM_InitializeAdapter (PLM_DEVICE_BLOCK pDevice); +LM_STATUS LM_ResetAdapter (PLM_DEVICE_BLOCK pDevice); +LM_STATUS LM_DisableInterrupt (PLM_DEVICE_BLOCK pDevice); +LM_STATUS LM_EnableInterrupt (PLM_DEVICE_BLOCK pDevice); +LM_STATUS LM_SendPacket (PLM_DEVICE_BLOCK pDevice, PLM_PACKET pPacket); +LM_STATUS LM_ServiceInterrupts (PLM_DEVICE_BLOCK pDevice); +LM_STATUS LM_QueueRxPackets (PLM_DEVICE_BLOCK pDevice); +LM_STATUS LM_SetReceiveMask (PLM_DEVICE_BLOCK pDevice, LM_UINT32 Mask); +LM_STATUS LM_Halt (PLM_DEVICE_BLOCK pDevice); +LM_STATUS LM_Abort (PLM_DEVICE_BLOCK pDevice); +LM_STATUS LM_MulticastAdd (PLM_DEVICE_BLOCK pDevice, PLM_UINT8 pMcAddress); +LM_STATUS LM_MulticastDel (PLM_DEVICE_BLOCK pDevice, PLM_UINT8 pMcAddress); +LM_STATUS LM_MulticastClear (PLM_DEVICE_BLOCK pDevice); +LM_STATUS LM_SetMacAddress (PLM_DEVICE_BLOCK pDevice, PLM_UINT8 pMacAddress); +LM_STATUS LM_LoopbackAddress (PLM_DEVICE_BLOCK pDevice, PLM_UINT8 pAddress); -LM_UINT32 LM_GetCrcCounter(PLM_DEVICE_BLOCK pDevice); +LM_UINT32 LM_GetCrcCounter (PLM_DEVICE_BLOCK pDevice); -LM_WAKE_UP_MODE LM_PMCapabilities(PLM_DEVICE_BLOCK pDevice); -LM_STATUS LM_NwufAdd(PLM_DEVICE_BLOCK pDevice, LM_UINT32 ByteMaskSize, - LM_UINT8 *pByteMask, LM_UINT8 *pPattern); -LM_STATUS LM_NwufRemove(PLM_DEVICE_BLOCK pDevice, LM_UINT32 ByteMaskSize, - LM_UINT8 *pByteMask, LM_UINT8 *pPattern); -LM_STATUS LM_SetPowerState(PLM_DEVICE_BLOCK pDevice, LM_POWER_STATE PowerLevel); +LM_WAKE_UP_MODE LM_PMCapabilities (PLM_DEVICE_BLOCK pDevice); +LM_STATUS LM_NwufAdd (PLM_DEVICE_BLOCK pDevice, LM_UINT32 ByteMaskSize, + LM_UINT8 * pByteMask, LM_UINT8 * pPattern); +LM_STATUS LM_NwufRemove (PLM_DEVICE_BLOCK pDevice, LM_UINT32 ByteMaskSize, + LM_UINT8 * pByteMask, LM_UINT8 * pPattern); +LM_STATUS LM_SetPowerState (PLM_DEVICE_BLOCK pDevice, + LM_POWER_STATE PowerLevel); -LM_VOID LM_ReadPhy(PLM_DEVICE_BLOCK pDevice, LM_UINT32 PhyReg, - PLM_UINT32 pData32); -LM_VOID LM_WritePhy(PLM_DEVICE_BLOCK pDevice, LM_UINT32 PhyReg, - LM_UINT32 Data32); - -LM_STATUS LM_ControlLoopBack(PLM_DEVICE_BLOCK pDevice, LM_UINT32 Control); -LM_STATUS LM_SetupPhy(PLM_DEVICE_BLOCK pDevice); -int LM_BlinkLED(PLM_DEVICE_BLOCK pDevice, LM_UINT32 BlinkDuration); +LM_VOID LM_ReadPhy (PLM_DEVICE_BLOCK pDevice, LM_UINT32 PhyReg, + PLM_UINT32 pData32); +LM_VOID LM_WritePhy (PLM_DEVICE_BLOCK pDevice, LM_UINT32 PhyReg, + LM_UINT32 Data32); +LM_STATUS LM_ControlLoopBack (PLM_DEVICE_BLOCK pDevice, LM_UINT32 Control); +LM_STATUS LM_SetupPhy (PLM_DEVICE_BLOCK pDevice); +int LM_BlinkLED (PLM_DEVICE_BLOCK pDevice, LM_UINT32 BlinkDuration); /******************************************************************************/ /* These are the OS specific functions called by LMAC. */ /******************************************************************************/ -LM_STATUS MM_ReadConfig16(PLM_DEVICE_BLOCK pDevice, LM_UINT32 Offset, - LM_UINT16 *pValue16); -LM_STATUS MM_WriteConfig16(PLM_DEVICE_BLOCK pDevice, LM_UINT32 Offset, - LM_UINT16 Value16); -LM_STATUS MM_ReadConfig32(PLM_DEVICE_BLOCK pDevice, LM_UINT32 Offset, - LM_UINT32 *pValue32); -LM_STATUS MM_WriteConfig32(PLM_DEVICE_BLOCK pDevice, LM_UINT32 Offset, - LM_UINT32 Value32); -LM_STATUS MM_MapMemBase(PLM_DEVICE_BLOCK pDevice); -LM_STATUS MM_MapIoBase(PLM_DEVICE_BLOCK pDevice); -LM_STATUS MM_IndicateRxPackets(PLM_DEVICE_BLOCK pDevice); -LM_STATUS MM_IndicateTxPackets(PLM_DEVICE_BLOCK pDevice); -LM_STATUS MM_StartTxDma(PLM_DEVICE_BLOCK pDevice, PLM_PACKET pPacket); -LM_STATUS MM_CompleteTxDma(PLM_DEVICE_BLOCK pDevice, PLM_PACKET pPacket); -LM_STATUS MM_AllocateMemory(PLM_DEVICE_BLOCK pDevice, LM_UINT32 BlockSize, - PLM_VOID *pMemoryBlockVirt); -LM_STATUS MM_AllocateSharedMemory(PLM_DEVICE_BLOCK pDevice, LM_UINT32 BlockSize, - PLM_VOID *pMemoryBlockVirt, PLM_PHYSICAL_ADDRESS pMemoryBlockPhy, - LM_BOOL Cached); -LM_STATUS MM_GetConfig(PLM_DEVICE_BLOCK pDevice); -LM_STATUS MM_IndicateStatus(PLM_DEVICE_BLOCK pDevice, LM_STATUS Status); -LM_STATUS MM_InitializeUmPackets(PLM_DEVICE_BLOCK pDevice); -LM_STATUS MM_FreeRxBuffer(PLM_DEVICE_BLOCK pDevice, PLM_PACKET pPacket); -LM_STATUS MM_CoalesceTxBuffer(PLM_DEVICE_BLOCK pDevice, PLM_PACKET pPacket); -LM_STATUS LM_MbufWorkAround(PLM_DEVICE_BLOCK pDevice); -LM_STATUS LM_SetLinkSpeed(PLM_DEVICE_BLOCK pDevice, - LM_REQUESTED_MEDIA_TYPE RequestedMediaType); +LM_STATUS MM_ReadConfig16 (PLM_DEVICE_BLOCK pDevice, LM_UINT32 Offset, + LM_UINT16 * pValue16); +LM_STATUS MM_WriteConfig16 (PLM_DEVICE_BLOCK pDevice, LM_UINT32 Offset, + LM_UINT16 Value16); +LM_STATUS MM_ReadConfig32 (PLM_DEVICE_BLOCK pDevice, LM_UINT32 Offset, + LM_UINT32 * pValue32); +LM_STATUS MM_WriteConfig32 (PLM_DEVICE_BLOCK pDevice, LM_UINT32 Offset, + LM_UINT32 Value32); +LM_STATUS MM_MapMemBase (PLM_DEVICE_BLOCK pDevice); +LM_STATUS MM_MapIoBase (PLM_DEVICE_BLOCK pDevice); +LM_STATUS MM_IndicateRxPackets (PLM_DEVICE_BLOCK pDevice); +LM_STATUS MM_IndicateTxPackets (PLM_DEVICE_BLOCK pDevice); +LM_STATUS MM_StartTxDma (PLM_DEVICE_BLOCK pDevice, PLM_PACKET pPacket); +LM_STATUS MM_CompleteTxDma (PLM_DEVICE_BLOCK pDevice, PLM_PACKET pPacket); +LM_STATUS MM_AllocateMemory (PLM_DEVICE_BLOCK pDevice, LM_UINT32 BlockSize, + PLM_VOID * pMemoryBlockVirt); +LM_STATUS MM_AllocateSharedMemory (PLM_DEVICE_BLOCK pDevice, + LM_UINT32 BlockSize, + PLM_VOID * pMemoryBlockVirt, + PLM_PHYSICAL_ADDRESS pMemoryBlockPhy, + LM_BOOL Cached); +LM_STATUS MM_GetConfig (PLM_DEVICE_BLOCK pDevice); +LM_STATUS MM_IndicateStatus (PLM_DEVICE_BLOCK pDevice, LM_STATUS Status); +LM_STATUS MM_InitializeUmPackets (PLM_DEVICE_BLOCK pDevice); +LM_STATUS MM_FreeRxBuffer (PLM_DEVICE_BLOCK pDevice, PLM_PACKET pPacket); +LM_STATUS MM_CoalesceTxBuffer (PLM_DEVICE_BLOCK pDevice, PLM_PACKET pPacket); +LM_STATUS LM_MbufWorkAround (PLM_DEVICE_BLOCK pDevice); +LM_STATUS LM_SetLinkSpeed (PLM_DEVICE_BLOCK pDevice, + LM_REQUESTED_MEDIA_TYPE RequestedMediaType); #if INCLUDE_5703_A0_FIX -LM_STATUS LM_Load5703DmaWFirmware(PLM_DEVICE_BLOCK pDevice); +LM_STATUS LM_Load5703DmaWFirmware (PLM_DEVICE_BLOCK pDevice); #endif - -#endif /* LM_H */ +#endif /* LM_H */ diff --git a/drivers/bcm570x_mm.h b/drivers/bcm570x_mm.h index b7cbf8abd..ff5302f47 100644 --- a/drivers/bcm570x_mm.h +++ b/drivers/bcm570x_mm.h @@ -45,7 +45,7 @@ extern int MM_Packet_Desc_Size; #define MM_PACKET_DESC_SIZE MM_Packet_Desc_Size -DECLARE_QUEUE_TYPE(UM_RX_PACKET_Q, MAX_RX_PACKET_DESC_COUNT+1); +DECLARE_QUEUE_TYPE (UM_RX_PACKET_Q, MAX_RX_PACKET_DESC_COUNT + 1); #define MAX_MEM 16 @@ -65,51 +65,50 @@ typedef struct _UM_DEVICE_BLOCK { int mtu; int index; int opened; - int delayed_link_ind; /* Delay link status during initial load */ - int adapter_just_inited; /* the first few seconds after init. */ - int spurious_int; /* new -- unsupported */ + int delayed_link_ind; /* Delay link status during initial load */ + int adapter_just_inited; /* the first few seconds after init. */ + int spurious_int; /* new -- unsupported */ int timer_interval; int adaptive_expiry; - int crc_counter_expiry; /* new -- unsupported */ - int poll_tib_expiry; /* new -- unsupported */ + int crc_counter_expiry; /* new -- unsupported */ + int poll_tib_expiry; /* new -- unsupported */ int tx_full; int tx_queued; int line_speed; /* in Mbps, 0 if link is down */ UM_RX_PACKET_Q rx_out_of_buf_q; int rx_out_of_buf; - int rx_low_buf_thresh; /* changed to rx_buf_repl_thresh */ + int rx_low_buf_thresh; /* changed to rx_buf_repl_thresh */ int rx_buf_repl_panic_thresh; - int rx_buf_align; /* new -- unsupported */ + int rx_buf_align; /* new -- unsupported */ int do_global_lock; mutex_t global_lock; mutex_t undi_lock; long undi_flags; volatile int interrupt; int tasklet_pending; - int tasklet_busy; /* new -- unsupported */ + int tasklet_busy; /* new -- unsupported */ int rx_pkt; int tx_pkt; -#ifdef NICE_SUPPORT /* unsupported, this is a linux ioctl */ - void (*nice_rx)(void*, void* ); - void* nice_ctx; -#endif /* NICE_SUPPORT */ +#ifdef NICE_SUPPORT /* unsupported, this is a linux ioctl */ + void (*nice_rx) (void *, void *); + void *nice_ctx; +#endif /* NICE_SUPPORT */ int rx_adaptive_coalesce; unsigned int rx_last_cnt; unsigned int tx_last_cnt; unsigned int rx_curr_coalesce_frames; unsigned int rx_curr_coalesce_ticks; - unsigned int tx_curr_coalesce_frames; /* new -- unsupported */ -#if TIGON3_DEBUG /* new -- unsupported */ + unsigned int tx_curr_coalesce_frames; /* new -- unsupported */ +#if TIGON3_DEBUG /* new -- unsupported */ uint tx_zc_count; uint tx_chksum_count; uint tx_himem_count; uint rx_good_chksum_count; #endif - unsigned int rx_bad_chksum_count; /* new -- unsupported */ - unsigned int rx_misc_errors; /* new -- unsupported */ + unsigned int rx_bad_chksum_count; /* new -- unsupported */ + unsigned int rx_misc_errors; /* new -- unsupported */ } UM_DEVICE_BLOCK, *PUM_DEVICE_BLOCK; - /* Physical/PCI DMA address */ typedef union { dma_addr_t dma_map; @@ -117,9 +116,9 @@ typedef union { /* Packet */ typedef struct -_UM_PACKET { - LM_PACKET lm_packet; - void* skbuff; /* Address of packet buffer */ + _UM_PACKET { + LM_PACKET lm_packet; + void *skbuff; /* Address of packet buffer */ } UM_PACKET, *PUM_PACKET; #define MM_ACQUIRE_UNDI_LOCK(_pDevice) @@ -137,15 +136,14 @@ _UM_PACKET { #define MEM_TO_PCI_PHYS(addr) (addr) -extern void MM_SetAddr (LM_PHYSICAL_ADDRESS *paddr, dma_addr_t addr); -extern void MM_SetT3Addr(T3_64BIT_HOST_ADDR *paddr, dma_addr_t addr); +extern void MM_SetAddr (LM_PHYSICAL_ADDRESS * paddr, dma_addr_t addr); +extern void MM_SetT3Addr (T3_64BIT_HOST_ADDR * paddr, dma_addr_t addr); extern void MM_MapTxDma (PLM_DEVICE_BLOCK pDevice, - struct _LM_PACKET *pPacket, T3_64BIT_HOST_ADDR *paddr, - LM_UINT32 *len, int frag); -extern void MM_MapRxDma ( PLM_DEVICE_BLOCK pDevice, - struct _LM_PACKET *pPacket, - T3_64BIT_HOST_ADDR *paddr); - + struct _LM_PACKET *pPacket, T3_64BIT_HOST_ADDR * paddr, + LM_UINT32 * len, int frag); +extern void MM_MapRxDma (PLM_DEVICE_BLOCK pDevice, + struct _LM_PACKET *pPacket, + T3_64BIT_HOST_ADDR * paddr); /* BSP needs to provide sysUsecDelay and sysSerialPrintString */ extern void sysSerialPrintString (char *s); @@ -157,4 +155,4 @@ extern void sysSerialPrintString (char *s); #if 0 #define cpu_to_le32(val) LONGSWAP(val) #endif -#endif /* MM_H */ +#endif /* MM_H */ diff --git a/drivers/tigon3.c b/drivers/tigon3.c index ec2cd2ac3..91e22ebd2 100644 --- a/drivers/tigon3.c +++ b/drivers/tigon3.c @@ -26,69 +26,70 @@ /* Local functions. */ /******************************************************************************/ -LM_STATUS LM_Abort(PLM_DEVICE_BLOCK pDevice); -LM_STATUS LM_QueueRxPackets(PLM_DEVICE_BLOCK pDevice); +LM_STATUS LM_Abort (PLM_DEVICE_BLOCK pDevice); +LM_STATUS LM_QueueRxPackets (PLM_DEVICE_BLOCK pDevice); -static LM_STATUS LM_TranslateRequestedMediaType( - LM_REQUESTED_MEDIA_TYPE RequestedMediaType, - PLM_MEDIA_TYPE pMediaType, PLM_LINE_SPEED pLineSpeed, - PLM_DUPLEX_MODE pDuplexMode); +static LM_STATUS LM_TranslateRequestedMediaType (LM_REQUESTED_MEDIA_TYPE + RequestedMediaType, + PLM_MEDIA_TYPE pMediaType, + PLM_LINE_SPEED pLineSpeed, + PLM_DUPLEX_MODE pDuplexMode); -static LM_STATUS LM_InitBcm540xPhy(PLM_DEVICE_BLOCK pDevice); +static LM_STATUS LM_InitBcm540xPhy (PLM_DEVICE_BLOCK pDevice); -__inline static LM_VOID LM_ServiceRxInterrupt(PLM_DEVICE_BLOCK pDevice); -__inline static LM_VOID LM_ServiceTxInterrupt(PLM_DEVICE_BLOCK pDevice); +__inline static LM_VOID LM_ServiceRxInterrupt (PLM_DEVICE_BLOCK pDevice); +__inline static LM_VOID LM_ServiceTxInterrupt (PLM_DEVICE_BLOCK pDevice); -static LM_STATUS LM_ForceAutoNegBcm540xPhy(PLM_DEVICE_BLOCK pDevice, - LM_REQUESTED_MEDIA_TYPE RequestedMediaType); -static LM_STATUS LM_ForceAutoNeg(PLM_DEVICE_BLOCK pDevice, - LM_REQUESTED_MEDIA_TYPE RequestedMediaType); -static LM_UINT32 GetPhyAdFlowCntrlSettings(PLM_DEVICE_BLOCK pDevice); -STATIC LM_STATUS LM_SetFlowControl(PLM_DEVICE_BLOCK pDevice, - LM_UINT32 LocalPhyAd, LM_UINT32 RemotePhyAd); +static LM_STATUS LM_ForceAutoNegBcm540xPhy (PLM_DEVICE_BLOCK pDevice, + LM_REQUESTED_MEDIA_TYPE + RequestedMediaType); +static LM_STATUS LM_ForceAutoNeg (PLM_DEVICE_BLOCK pDevice, + LM_REQUESTED_MEDIA_TYPE RequestedMediaType); +static LM_UINT32 GetPhyAdFlowCntrlSettings (PLM_DEVICE_BLOCK pDevice); +STATIC LM_STATUS LM_SetFlowControl (PLM_DEVICE_BLOCK pDevice, + LM_UINT32 LocalPhyAd, + LM_UINT32 RemotePhyAd); #if INCLUDE_TBI_SUPPORT -STATIC LM_STATUS LM_SetupFiberPhy(PLM_DEVICE_BLOCK pDevice); -STATIC LM_STATUS LM_InitBcm800xPhy(PLM_DEVICE_BLOCK pDevice); +STATIC LM_STATUS LM_SetupFiberPhy (PLM_DEVICE_BLOCK pDevice); +STATIC LM_STATUS LM_InitBcm800xPhy (PLM_DEVICE_BLOCK pDevice); #endif -STATIC LM_STATUS LM_SetupCopperPhy(PLM_DEVICE_BLOCK pDevice); -STATIC PLM_ADAPTER_INFO LM_GetAdapterInfoBySsid(LM_UINT16 Svid, LM_UINT16 Ssid); -STATIC LM_STATUS LM_DmaTest(PLM_DEVICE_BLOCK pDevice, PLM_UINT8 pBufferVirt, - LM_PHYSICAL_ADDRESS BufferPhy, LM_UINT32 BufferSize); -STATIC LM_STATUS LM_HaltCpu(PLM_DEVICE_BLOCK pDevice,LM_UINT32 cpu_number); -STATIC LM_STATUS LM_ResetChip(PLM_DEVICE_BLOCK pDevice); -STATIC LM_STATUS LM_Test4GBoundary(PLM_DEVICE_BLOCK pDevice, PLM_PACKET pPacket, - PT3_SND_BD pSendBd); +STATIC LM_STATUS LM_SetupCopperPhy (PLM_DEVICE_BLOCK pDevice); +STATIC PLM_ADAPTER_INFO LM_GetAdapterInfoBySsid (LM_UINT16 Svid, + LM_UINT16 Ssid); +STATIC LM_STATUS LM_DmaTest (PLM_DEVICE_BLOCK pDevice, PLM_UINT8 pBufferVirt, + LM_PHYSICAL_ADDRESS BufferPhy, + LM_UINT32 BufferSize); +STATIC LM_STATUS LM_HaltCpu (PLM_DEVICE_BLOCK pDevice, LM_UINT32 cpu_number); +STATIC LM_STATUS LM_ResetChip (PLM_DEVICE_BLOCK pDevice); +STATIC LM_STATUS LM_Test4GBoundary (PLM_DEVICE_BLOCK pDevice, + PLM_PACKET pPacket, PT3_SND_BD pSendBd); /******************************************************************************/ /* External functions. */ /******************************************************************************/ -LM_STATUS LM_LoadRlsFirmware(PLM_DEVICE_BLOCK pDevice); - +LM_STATUS LM_LoadRlsFirmware (PLM_DEVICE_BLOCK pDevice); /******************************************************************************/ /* Description: */ /* */ /* Return: */ /******************************************************************************/ -LM_UINT32 -LM_RegRdInd( -PLM_DEVICE_BLOCK pDevice, -LM_UINT32 Register) { - LM_UINT32 Value32; +LM_UINT32 LM_RegRdInd (PLM_DEVICE_BLOCK pDevice, LM_UINT32 Register) +{ + LM_UINT32 Value32; #if PCIX_TARGET_WORKAROUND - MM_ACQUIRE_UNDI_LOCK(pDevice); + MM_ACQUIRE_UNDI_LOCK (pDevice); #endif - MM_WriteConfig32(pDevice, T3_PCI_REG_ADDR_REG, Register); - MM_ReadConfig32(pDevice, T3_PCI_REG_DATA_REG, &Value32); + MM_WriteConfig32 (pDevice, T3_PCI_REG_ADDR_REG, Register); + MM_ReadConfig32 (pDevice, T3_PCI_REG_DATA_REG, &Value32); #if PCIX_TARGET_WORKAROUND - MM_RELEASE_UNDI_LOCK(pDevice); + MM_RELEASE_UNDI_LOCK (pDevice); #endif - return Value32; -} /* LM_RegRdInd */ - + return Value32; +} /* LM_RegRdInd */ /******************************************************************************/ /* Description: */ @@ -96,47 +97,41 @@ LM_UINT32 Register) { /* Return: */ /******************************************************************************/ LM_VOID -LM_RegWrInd( -PLM_DEVICE_BLOCK pDevice, -LM_UINT32 Register, -LM_UINT32 Value32) { +LM_RegWrInd (PLM_DEVICE_BLOCK pDevice, LM_UINT32 Register, LM_UINT32 Value32) +{ #if PCIX_TARGET_WORKAROUND - MM_ACQUIRE_UNDI_LOCK(pDevice); + MM_ACQUIRE_UNDI_LOCK (pDevice); #endif - MM_WriteConfig32(pDevice, T3_PCI_REG_ADDR_REG, Register); - MM_WriteConfig32(pDevice, T3_PCI_REG_DATA_REG, Value32); + MM_WriteConfig32 (pDevice, T3_PCI_REG_ADDR_REG, Register); + MM_WriteConfig32 (pDevice, T3_PCI_REG_DATA_REG, Value32); #if PCIX_TARGET_WORKAROUND - MM_RELEASE_UNDI_LOCK(pDevice); + MM_RELEASE_UNDI_LOCK (pDevice); #endif -} /* LM_RegWrInd */ - +} /* LM_RegWrInd */ /******************************************************************************/ /* Description: */ /* */ /* Return: */ /******************************************************************************/ -LM_UINT32 -LM_MemRdInd( -PLM_DEVICE_BLOCK pDevice, -LM_UINT32 MemAddr) { - LM_UINT32 Value32; +LM_UINT32 LM_MemRdInd (PLM_DEVICE_BLOCK pDevice, LM_UINT32 MemAddr) +{ + LM_UINT32 Value32; - MM_ACQUIRE_UNDI_LOCK(pDevice); + MM_ACQUIRE_UNDI_LOCK (pDevice); #ifdef BIG_ENDIAN_HOST - MM_WriteConfig32(pDevice, T3_PCI_MEM_WIN_ADDR_REG, MemAddr); - Value32 = REG_RD(pDevice, PciCfg.MemWindowData); - /* Value32 = REG_RD(pDevice,uIntMem.Mbuf[(MemAddr & 0x7fff)/4]); */ + MM_WriteConfig32 (pDevice, T3_PCI_MEM_WIN_ADDR_REG, MemAddr); + Value32 = REG_RD (pDevice, PciCfg.MemWindowData); + /* Value32 = REG_RD(pDevice,uIntMem.Mbuf[(MemAddr & 0x7fff)/4]); */ #else - MM_WriteConfig32(pDevice, T3_PCI_MEM_WIN_ADDR_REG, MemAddr); - MM_ReadConfig32(pDevice, T3_PCI_MEM_WIN_DATA_REG, &Value32); + MM_WriteConfig32 (pDevice, T3_PCI_MEM_WIN_ADDR_REG, MemAddr); + MM_ReadConfig32 (pDevice, T3_PCI_MEM_WIN_DATA_REG, &Value32); #endif - MM_RELEASE_UNDI_LOCK(pDevice); - - return Value32; -} /* LM_MemRdInd */ + MM_RELEASE_UNDI_LOCK (pDevice); + return Value32; +} /* LM_MemRdInd */ /******************************************************************************/ /* Description: */ @@ -144,512 +139,455 @@ LM_UINT32 MemAddr) { /* Return: */ /******************************************************************************/ LM_VOID -LM_MemWrInd( -PLM_DEVICE_BLOCK pDevice, -LM_UINT32 MemAddr, -LM_UINT32 Value32) { - MM_ACQUIRE_UNDI_LOCK(pDevice); +LM_MemWrInd (PLM_DEVICE_BLOCK pDevice, LM_UINT32 MemAddr, LM_UINT32 Value32) +{ + MM_ACQUIRE_UNDI_LOCK (pDevice); #ifdef BIG_ENDIAN_HOST - REG_WR(pDevice,PciCfg.MemWindowBaseAddr,MemAddr); - REG_WR(pDevice,uIntMem.Mbuf[(MemAddr & 0x7fff)/4],Value32); + REG_WR (pDevice, PciCfg.MemWindowBaseAddr, MemAddr); + REG_WR (pDevice, uIntMem.Mbuf[(MemAddr & 0x7fff) / 4], Value32); #else - MM_WriteConfig32(pDevice, T3_PCI_MEM_WIN_ADDR_REG, MemAddr); - MM_WriteConfig32(pDevice, T3_PCI_MEM_WIN_DATA_REG, Value32); + MM_WriteConfig32 (pDevice, T3_PCI_MEM_WIN_ADDR_REG, MemAddr); + MM_WriteConfig32 (pDevice, T3_PCI_MEM_WIN_DATA_REG, Value32); #endif - MM_RELEASE_UNDI_LOCK(pDevice); -} /* LM_MemWrInd */ - + MM_RELEASE_UNDI_LOCK (pDevice); +} /* LM_MemWrInd */ /******************************************************************************/ /* Description: */ /* */ /* Return: */ /******************************************************************************/ -LM_STATUS -LM_QueueRxPackets( -PLM_DEVICE_BLOCK pDevice) { - LM_STATUS Lmstatus; - PLM_PACKET pPacket; - PT3_RCV_BD pRcvBd; - LM_UINT32 StdBdAdded = 0; +LM_STATUS LM_QueueRxPackets (PLM_DEVICE_BLOCK pDevice) +{ + LM_STATUS Lmstatus; + PLM_PACKET pPacket; + PT3_RCV_BD pRcvBd; + LM_UINT32 StdBdAdded = 0; #if T3_JUMBO_RCV_RCB_ENTRY_COUNT - LM_UINT32 JumboBdAdded = 0; -#endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */ + LM_UINT32 JumboBdAdded = 0; +#endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */ - Lmstatus = LM_STATUS_SUCCESS; + Lmstatus = LM_STATUS_SUCCESS; - pPacket = (PLM_PACKET) QQ_PopHead(&pDevice->RxPacketFreeQ.Container); - while(pPacket) { - switch(pPacket->u.Rx.RcvProdRing) { + pPacket = (PLM_PACKET) QQ_PopHead (&pDevice->RxPacketFreeQ.Container); + while (pPacket) { + switch (pPacket->u.Rx.RcvProdRing) { #if T3_JUMBO_RCV_RCB_ENTRY_COUNT - case T3_JUMBO_RCV_PROD_RING: /* Jumbo Receive Ring. */ - /* Initialize the buffer descriptor. */ - pRcvBd = - &pDevice->pRxJumboBdVirt[pDevice->RxJumboProdIdx]; - pRcvBd->Flags = RCV_BD_FLAG_END | RCV_BD_FLAG_JUMBO_RING; - pRcvBd->Len = (LM_UINT16) pDevice->RxJumboBufferSize; + case T3_JUMBO_RCV_PROD_RING: /* Jumbo Receive Ring. */ + /* Initialize the buffer descriptor. */ + pRcvBd = + &pDevice->pRxJumboBdVirt[pDevice->RxJumboProdIdx]; + pRcvBd->Flags = + RCV_BD_FLAG_END | RCV_BD_FLAG_JUMBO_RING; + pRcvBd->Len = (LM_UINT16) pDevice->RxJumboBufferSize; - /* Initialize the receive buffer pointer */ -#if 0 /* Jimmy, deleted in new */ - pRcvBd->HostAddr.Low = pPacket->u.Rx.RxBufferPhy.Low; - pRcvBd->HostAddr.High = pPacket->u.Rx.RxBufferPhy.High; + /* Initialize the receive buffer pointer */ +#if 0 /* Jimmy, deleted in new */ + pRcvBd->HostAddr.Low = pPacket->u.Rx.RxBufferPhy.Low; + pRcvBd->HostAddr.High = pPacket->u.Rx.RxBufferPhy.High; #endif - MM_MapRxDma(pDevice, pPacket, &pRcvBd->HostAddr); + MM_MapRxDma (pDevice, pPacket, &pRcvBd->HostAddr); - /* The opaque field may point to an offset from a fix addr. */ - pRcvBd->Opaque = (LM_UINT32) (MM_UINT_PTR(pPacket) - - MM_UINT_PTR(pDevice->pPacketDescBase)); + /* The opaque field may point to an offset from a fix addr. */ + pRcvBd->Opaque = (LM_UINT32) (MM_UINT_PTR (pPacket) - + MM_UINT_PTR (pDevice-> + pPacketDescBase)); - /* Update the producer index. */ - pDevice->RxJumboProdIdx = (pDevice->RxJumboProdIdx + 1) & - T3_JUMBO_RCV_RCB_ENTRY_COUNT_MASK; + /* Update the producer index. */ + pDevice->RxJumboProdIdx = + (pDevice->RxJumboProdIdx + + 1) & T3_JUMBO_RCV_RCB_ENTRY_COUNT_MASK; - JumboBdAdded++; - break; -#endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */ - - case T3_STD_RCV_PROD_RING: /* Standard Receive Ring. */ - /* Initialize the buffer descriptor. */ - pRcvBd = &pDevice->pRxStdBdVirt[pDevice->RxStdProdIdx]; - pRcvBd->Flags = RCV_BD_FLAG_END; - pRcvBd->Len = MAX_STD_RCV_BUFFER_SIZE; - - /* Initialize the receive buffer pointer */ -#if 0 /* Jimmy, deleted in new replaced with MM_MapRxDma */ - pRcvBd->HostAddr.Low = pPacket->u.Rx.RxBufferPhy.Low; - pRcvBd->HostAddr.High = pPacket->u.Rx.RxBufferPhy.High; -#endif - MM_MapRxDma(pDevice, pPacket, &pRcvBd->HostAddr); - - /* The opaque field may point to an offset from a fix addr. */ - pRcvBd->Opaque = (LM_UINT32) (MM_UINT_PTR(pPacket) - - MM_UINT_PTR(pDevice->pPacketDescBase)); - - /* Update the producer index. */ - pDevice->RxStdProdIdx = (pDevice->RxStdProdIdx + 1) & - T3_STD_RCV_RCB_ENTRY_COUNT_MASK; - - StdBdAdded++; - break; - - case T3_UNKNOWN_RCV_PROD_RING: - default: - Lmstatus = LM_STATUS_FAILURE; - break; - } /* switch */ - - /* Bail out if there is any error. */ - if(Lmstatus != LM_STATUS_SUCCESS) - { - break; - } - - pPacket = (PLM_PACKET) QQ_PopHead(&pDevice->RxPacketFreeQ.Container); - } /* while */ - - wmb(); - /* Update the procedure index. */ - if(StdBdAdded) - { - MB_REG_WR(pDevice, Mailbox.RcvStdProdIdx.Low, pDevice->RxStdProdIdx); - } -#if T3_JUMBO_RCV_RCB_ENTRY_COUNT - if(JumboBdAdded) - { - MB_REG_WR(pDevice, Mailbox.RcvJumboProdIdx.Low, - pDevice->RxJumboProdIdx); - } -#endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */ - - return Lmstatus; -} /* LM_QueueRxPackets */ - - -/******************************************************************************/ -/* Description: */ -/* */ -/* Return: */ -/******************************************************************************/ -STATIC LM_VOID -LM_NvramInit( - PLM_DEVICE_BLOCK pDevice) -{ - LM_UINT32 Value32; - LM_UINT32 j; - - /* Intialize clock period and state machine. */ - Value32 = SEEPROM_ADDR_CLK_PERD(SEEPROM_CLOCK_PERIOD) | - SEEPROM_ADDR_FSM_RESET; - REG_WR(pDevice, Grc.EepromAddr, Value32); - - for(j = 0; j < 100; j++) - { - MM_Wait(10); - } - - /* Serial eeprom access using the Grc.EepromAddr/EepromData registers. */ - Value32 = REG_RD(pDevice, Grc.LocalCtrl); - REG_WR(pDevice, Grc.LocalCtrl, Value32 | GRC_MISC_LOCAL_CTRL_AUTO_SEEPROM); - - /* Set the 5701 compatibility mode if we are using EEPROM. */ - if(T3_ASIC_REV(pDevice->ChipRevId) != T3_ASIC_REV_5700 && - T3_ASIC_REV(pDevice->ChipRevId) != T3_ASIC_REV_5701) - { - Value32 = REG_RD(pDevice, Nvram.Config1); - if((Value32 & FLASH_INTERFACE_ENABLE) == 0) - { - /* Use the new interface to read EEPROM. */ - Value32 &= ~FLASH_COMPAT_BYPASS; - - REG_WR(pDevice, Nvram.Config1, Value32); - } - } -} /* LM_NvRamInit */ - - -/******************************************************************************/ -/* Description: */ -/* */ -/* Return: */ -/******************************************************************************/ -STATIC LM_STATUS -LM_EepromRead( - PLM_DEVICE_BLOCK pDevice, - LM_UINT32 Offset, - LM_UINT32 *pData) -{ - LM_UINT32 Value32; - LM_UINT32 Addr; - LM_UINT32 Dev; - LM_UINT32 j; - - if(Offset > SEEPROM_CHIP_SIZE) - { - return LM_STATUS_FAILURE; - } - - Dev = Offset / SEEPROM_CHIP_SIZE; - Addr = Offset % SEEPROM_CHIP_SIZE; - - Value32 = REG_RD(pDevice, Grc.EepromAddr); - Value32 &= ~(SEEPROM_ADDR_ADDRESS_MASK | SEEPROM_ADDR_DEV_ID_MASK | - SEEPROM_ADDR_RW_MASK); - REG_WR(pDevice, Grc.EepromAddr, Value32 | SEEPROM_ADDR_DEV_ID(Dev) | - SEEPROM_ADDR_ADDRESS(Addr) | SEEPROM_ADDR_START | SEEPROM_ADDR_READ); - - for(j = 0; j < 1000; j++) - { - Value32 = REG_RD(pDevice, Grc.EepromAddr); - if(Value32 & SEEPROM_ADDR_COMPLETE) - { - break; - } - MM_Wait(10); - } - - if(Value32 & SEEPROM_ADDR_COMPLETE) - { - Value32 = REG_RD(pDevice, Grc.EepromData); - *pData = Value32; - - return LM_STATUS_SUCCESS; - } - - return LM_STATUS_FAILURE; -} /* LM_EepromRead */ - - -/******************************************************************************/ -/* Description: */ -/* */ -/* Return: */ -/******************************************************************************/ -STATIC LM_STATUS -LM_NvramRead( - PLM_DEVICE_BLOCK pDevice, - LM_UINT32 Offset, - LM_UINT32 *pData) -{ - LM_UINT32 Value32; - LM_STATUS Status; - LM_UINT32 j; - - if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700 || - T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5701) - { - Status = LM_EepromRead(pDevice, Offset, pData); - } - else - { - /* Determine if we have flash or EEPROM. */ - Value32 = REG_RD(pDevice, Nvram.Config1); - if(Value32 & FLASH_INTERFACE_ENABLE) - { - if(Value32 & FLASH_SSRAM_BUFFERRED_MODE) - { - Offset = ((Offset/BUFFERED_FLASH_PAGE_SIZE) << - BUFFERED_FLASH_PAGE_POS) + - (Offset % BUFFERED_FLASH_PAGE_SIZE); - } - } - - REG_WR(pDevice, Nvram.SwArb, SW_ARB_REQ_SET1); - for (j = 0; j < 1000; j++) - { - if (REG_RD(pDevice, Nvram.SwArb) & SW_ARB_GNT1) - { - break; - } - MM_Wait(20); - } - if (j == 1000) - { - return LM_STATUS_FAILURE; - } - - /* Read from flash or EEPROM with the new 5703/02 interface. */ - REG_WR(pDevice, Nvram.Addr, Offset & NVRAM_ADDRESS_MASK); - - REG_WR(pDevice, Nvram.Cmd, NVRAM_CMD_RD | NVRAM_CMD_DO_IT | - NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE); - - /* Wait for the done bit to clear. */ - for(j = 0; j < 500; j++) - { - MM_Wait(10); - - Value32 = REG_RD(pDevice, Nvram.Cmd); - if(!(Value32 & NVRAM_CMD_DONE)) - { - break; - } - } - - /* Wait for the done bit. */ - if(!(Value32 & NVRAM_CMD_DONE)) - { - for(j = 0; j < 500; j++) - { - MM_Wait(10); - - Value32 = REG_RD(pDevice, Nvram.Cmd); - if(Value32 & NVRAM_CMD_DONE) - { - MM_Wait(10); - - *pData = REG_RD(pDevice, Nvram.ReadData); - - /* Change the endianess. */ - *pData = ((*pData & 0xff) << 24)| ((*pData & 0xff00) << 8)| - ((*pData & 0xff0000) >> 8) | ((*pData >> 24) & 0xff); - - break; - } - } - } - - REG_WR(pDevice, Nvram.SwArb, SW_ARB_REQ_CLR1); - if(Value32 & NVRAM_CMD_DONE) - { - Status = LM_STATUS_SUCCESS; - } - else - { - Status = LM_STATUS_FAILURE; - } - } - - return Status; -} /* LM_NvramRead */ - - -STATIC void -LM_ReadVPD(PLM_DEVICE_BLOCK pDevice) -{ - LM_UINT32 Vpd_arr[256/4]; - LM_UINT8 *Vpd = (LM_UINT8 *) &Vpd_arr[0]; - LM_UINT32 *Vpd_dptr = &Vpd_arr[0]; - LM_UINT32 Value32; - unsigned int j; - - /* Read PN from VPD */ - for (j = 0; j < 256; j += 4, Vpd_dptr++ ) - { - if (LM_NvramRead(pDevice, 0x100 + j, &Value32) != LM_STATUS_SUCCESS) { - printf("BCM570x: LM_ReadVPD: VPD read failed" - " (no EEPROM onboard)\n"); - return; - } - *Vpd_dptr = cpu_to_le32(Value32); - } - for (j = 0; j < 256; ) - { - unsigned int Vpd_r_len; - unsigned int Vpd_r_end; - - if ((Vpd[j] == 0x82) || (Vpd[j] == 0x91)) - { - j = j + 3 + Vpd[j + 1] + (Vpd[j + 2] << 8); - } - else if (Vpd[j] == 0x90) - { - Vpd_r_len = Vpd[j + 1] + (Vpd[j + 2] << 8); - j += 3; - Vpd_r_end = Vpd_r_len + j; - while (j < Vpd_r_end) - { - if ((Vpd[j] == 'P') && (Vpd[j + 1] == 'N')) - { - unsigned int len = Vpd[j + 2]; - - if (len <= 24) - { - memcpy(pDevice->PartNo, &Vpd[j + 3], len); - } - break; - } - else - { - if (Vpd[j + 2] == 0) - { + JumboBdAdded++; + break; +#endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */ + + case T3_STD_RCV_PROD_RING: /* Standard Receive Ring. */ + /* Initialize the buffer descriptor. */ + pRcvBd = &pDevice->pRxStdBdVirt[pDevice->RxStdProdIdx]; + pRcvBd->Flags = RCV_BD_FLAG_END; + pRcvBd->Len = MAX_STD_RCV_BUFFER_SIZE; + + /* Initialize the receive buffer pointer */ +#if 0 /* Jimmy, deleted in new replaced with MM_MapRxDma */ + pRcvBd->HostAddr.Low = pPacket->u.Rx.RxBufferPhy.Low; + pRcvBd->HostAddr.High = pPacket->u.Rx.RxBufferPhy.High; +#endif + MM_MapRxDma (pDevice, pPacket, &pRcvBd->HostAddr); + + /* The opaque field may point to an offset from a fix addr. */ + pRcvBd->Opaque = (LM_UINT32) (MM_UINT_PTR (pPacket) - + MM_UINT_PTR (pDevice-> + pPacketDescBase)); + + /* Update the producer index. */ + pDevice->RxStdProdIdx = (pDevice->RxStdProdIdx + 1) & + T3_STD_RCV_RCB_ENTRY_COUNT_MASK; + + StdBdAdded++; + break; + + case T3_UNKNOWN_RCV_PROD_RING: + default: + Lmstatus = LM_STATUS_FAILURE; + break; + } /* switch */ + + /* Bail out if there is any error. */ + if (Lmstatus != LM_STATUS_SUCCESS) { break; - } - j = j + Vpd[j + 2]; } - } - break; + + pPacket = + (PLM_PACKET) QQ_PopHead (&pDevice->RxPacketFreeQ.Container); + } /* while */ + + wmb (); + /* Update the procedure index. */ + if (StdBdAdded) { + MB_REG_WR (pDevice, Mailbox.RcvStdProdIdx.Low, + pDevice->RxStdProdIdx); } - else { - break; +#if T3_JUMBO_RCV_RCB_ENTRY_COUNT + if (JumboBdAdded) { + MB_REG_WR (pDevice, Mailbox.RcvJumboProdIdx.Low, + pDevice->RxJumboProdIdx); + } +#endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */ + + return Lmstatus; +} /* LM_QueueRxPackets */ + +/******************************************************************************/ +/* Description: */ +/* */ +/* Return: */ +/******************************************************************************/ +STATIC LM_VOID LM_NvramInit (PLM_DEVICE_BLOCK pDevice) +{ + LM_UINT32 Value32; + LM_UINT32 j; + + /* Intialize clock period and state machine. */ + Value32 = SEEPROM_ADDR_CLK_PERD (SEEPROM_CLOCK_PERIOD) | + SEEPROM_ADDR_FSM_RESET; + REG_WR (pDevice, Grc.EepromAddr, Value32); + + for (j = 0; j < 100; j++) { + MM_Wait (10); + } + + /* Serial eeprom access using the Grc.EepromAddr/EepromData registers. */ + Value32 = REG_RD (pDevice, Grc.LocalCtrl); + REG_WR (pDevice, Grc.LocalCtrl, + Value32 | GRC_MISC_LOCAL_CTRL_AUTO_SEEPROM); + + /* Set the 5701 compatibility mode if we are using EEPROM. */ + if (T3_ASIC_REV (pDevice->ChipRevId) != T3_ASIC_REV_5700 && + T3_ASIC_REV (pDevice->ChipRevId) != T3_ASIC_REV_5701) { + Value32 = REG_RD (pDevice, Nvram.Config1); + if ((Value32 & FLASH_INTERFACE_ENABLE) == 0) { + /* Use the new interface to read EEPROM. */ + Value32 &= ~FLASH_COMPAT_BYPASS; + + REG_WR (pDevice, Nvram.Config1, Value32); + } + } +} /* LM_NvRamInit */ + +/******************************************************************************/ +/* Description: */ +/* */ +/* Return: */ +/******************************************************************************/ +STATIC LM_STATUS +LM_EepromRead (PLM_DEVICE_BLOCK pDevice, LM_UINT32 Offset, LM_UINT32 * pData) +{ + LM_UINT32 Value32; + LM_UINT32 Addr; + LM_UINT32 Dev; + LM_UINT32 j; + + if (Offset > SEEPROM_CHIP_SIZE) { + return LM_STATUS_FAILURE; + } + + Dev = Offset / SEEPROM_CHIP_SIZE; + Addr = Offset % SEEPROM_CHIP_SIZE; + + Value32 = REG_RD (pDevice, Grc.EepromAddr); + Value32 &= ~(SEEPROM_ADDR_ADDRESS_MASK | SEEPROM_ADDR_DEV_ID_MASK | + SEEPROM_ADDR_RW_MASK); + REG_WR (pDevice, Grc.EepromAddr, Value32 | SEEPROM_ADDR_DEV_ID (Dev) | + SEEPROM_ADDR_ADDRESS (Addr) | SEEPROM_ADDR_START | + SEEPROM_ADDR_READ); + + for (j = 0; j < 1000; j++) { + Value32 = REG_RD (pDevice, Grc.EepromAddr); + if (Value32 & SEEPROM_ADDR_COMPLETE) { + break; + } + MM_Wait (10); + } + + if (Value32 & SEEPROM_ADDR_COMPLETE) { + Value32 = REG_RD (pDevice, Grc.EepromData); + *pData = Value32; + + return LM_STATUS_SUCCESS; + } + + return LM_STATUS_FAILURE; +} /* LM_EepromRead */ + +/******************************************************************************/ +/* Description: */ +/* */ +/* Return: */ +/******************************************************************************/ +STATIC LM_STATUS +LM_NvramRead (PLM_DEVICE_BLOCK pDevice, LM_UINT32 Offset, LM_UINT32 * pData) +{ + LM_UINT32 Value32; + LM_STATUS Status; + LM_UINT32 j; + + if (T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5700 || + T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5701) { + Status = LM_EepromRead (pDevice, Offset, pData); + } else { + /* Determine if we have flash or EEPROM. */ + Value32 = REG_RD (pDevice, Nvram.Config1); + if (Value32 & FLASH_INTERFACE_ENABLE) { + if (Value32 & FLASH_SSRAM_BUFFERRED_MODE) { + Offset = ((Offset / BUFFERED_FLASH_PAGE_SIZE) << + BUFFERED_FLASH_PAGE_POS) + + (Offset % BUFFERED_FLASH_PAGE_SIZE); + } + } + + REG_WR (pDevice, Nvram.SwArb, SW_ARB_REQ_SET1); + for (j = 0; j < 1000; j++) { + if (REG_RD (pDevice, Nvram.SwArb) & SW_ARB_GNT1) { + break; + } + MM_Wait (20); + } + if (j == 1000) { + return LM_STATUS_FAILURE; + } + + /* Read from flash or EEPROM with the new 5703/02 interface. */ + REG_WR (pDevice, Nvram.Addr, Offset & NVRAM_ADDRESS_MASK); + + REG_WR (pDevice, Nvram.Cmd, NVRAM_CMD_RD | NVRAM_CMD_DO_IT | + NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE); + + /* Wait for the done bit to clear. */ + for (j = 0; j < 500; j++) { + MM_Wait (10); + + Value32 = REG_RD (pDevice, Nvram.Cmd); + if (!(Value32 & NVRAM_CMD_DONE)) { + break; + } + } + + /* Wait for the done bit. */ + if (!(Value32 & NVRAM_CMD_DONE)) { + for (j = 0; j < 500; j++) { + MM_Wait (10); + + Value32 = REG_RD (pDevice, Nvram.Cmd); + if (Value32 & NVRAM_CMD_DONE) { + MM_Wait (10); + + *pData = + REG_RD (pDevice, Nvram.ReadData); + + /* Change the endianess. */ + *pData = + ((*pData & 0xff) << 24) | + ((*pData & 0xff00) << 8) | + ((*pData & 0xff0000) >> 8) | + ((*pData >> 24) & 0xff); + + break; + } + } + } + + REG_WR (pDevice, Nvram.SwArb, SW_ARB_REQ_CLR1); + if (Value32 & NVRAM_CMD_DONE) { + Status = LM_STATUS_SUCCESS; + } else { + Status = LM_STATUS_FAILURE; + } + } + + return Status; +} /* LM_NvramRead */ + +STATIC void LM_ReadVPD (PLM_DEVICE_BLOCK pDevice) +{ + LM_UINT32 Vpd_arr[256 / 4]; + LM_UINT8 *Vpd = (LM_UINT8 *) & Vpd_arr[0]; + LM_UINT32 *Vpd_dptr = &Vpd_arr[0]; + LM_UINT32 Value32; + unsigned int j; + + /* Read PN from VPD */ + for (j = 0; j < 256; j += 4, Vpd_dptr++) { + if (LM_NvramRead (pDevice, 0x100 + j, &Value32) != + LM_STATUS_SUCCESS) { + printf ("BCM570x: LM_ReadVPD: VPD read failed" + " (no EEPROM onboard)\n"); + return; + } + *Vpd_dptr = cpu_to_le32 (Value32); + } + for (j = 0; j < 256;) { + unsigned int Vpd_r_len; + unsigned int Vpd_r_end; + + if ((Vpd[j] == 0x82) || (Vpd[j] == 0x91)) { + j = j + 3 + Vpd[j + 1] + (Vpd[j + 2] << 8); + } else if (Vpd[j] == 0x90) { + Vpd_r_len = Vpd[j + 1] + (Vpd[j + 2] << 8); + j += 3; + Vpd_r_end = Vpd_r_len + j; + while (j < Vpd_r_end) { + if ((Vpd[j] == 'P') && (Vpd[j + 1] == 'N')) { + unsigned int len = Vpd[j + 2]; + + if (len <= 24) { + memcpy (pDevice->PartNo, + &Vpd[j + 3], len); + } + break; + } else { + if (Vpd[j + 2] == 0) { + break; + } + j = j + Vpd[j + 2]; + } + } + break; + } else { + break; + } } - } } -STATIC void -LM_ReadBootCodeVersion(PLM_DEVICE_BLOCK pDevice) +STATIC void LM_ReadBootCodeVersion (PLM_DEVICE_BLOCK pDevice) { - LM_UINT32 Value32, offset, ver_offset; - int i; + LM_UINT32 Value32, offset, ver_offset; + int i; - if (LM_NvramRead(pDevice, 0x0, &Value32) != LM_STATUS_SUCCESS) - return; - if (Value32 != 0xaa559966) - return; - if (LM_NvramRead(pDevice, 0xc, &offset) != LM_STATUS_SUCCESS) - return; - - offset = ((offset & 0xff) << 24)| ((offset & 0xff00) << 8)| - ((offset & 0xff0000) >> 8) | ((offset >> 24) & 0xff); - if (LM_NvramRead(pDevice, offset, &Value32) != LM_STATUS_SUCCESS) - return; - if ((Value32 == 0x0300000e) && - (LM_NvramRead(pDevice, offset + 4, &Value32) == LM_STATUS_SUCCESS) && - (Value32 == 0)) { - - if (LM_NvramRead(pDevice, offset + 8, &ver_offset) != LM_STATUS_SUCCESS) - return; - ver_offset = ((ver_offset & 0xff0000) >> 8) | - ((ver_offset >> 24) & 0xff); - for (i = 0; i < 16; i += 4) { - if (LM_NvramRead(pDevice, offset + ver_offset + i, &Value32) != - LM_STATUS_SUCCESS) - { + if (LM_NvramRead (pDevice, 0x0, &Value32) != LM_STATUS_SUCCESS) + return; + if (Value32 != 0xaa559966) + return; + if (LM_NvramRead (pDevice, 0xc, &offset) != LM_STATUS_SUCCESS) return; - } - *((LM_UINT32 *) &pDevice->BootCodeVer[i]) = cpu_to_le32(Value32); - } - } - else { - char c; - if (LM_NvramRead(pDevice, 0x94, &Value32) != LM_STATUS_SUCCESS) - return; + offset = ((offset & 0xff) << 24) | ((offset & 0xff00) << 8) | + ((offset & 0xff0000) >> 8) | ((offset >> 24) & 0xff); + if (LM_NvramRead (pDevice, offset, &Value32) != LM_STATUS_SUCCESS) + return; + if ((Value32 == 0x0300000e) && + (LM_NvramRead (pDevice, offset + 4, &Value32) == LM_STATUS_SUCCESS) + && (Value32 == 0)) { - i = 0; - c = ((Value32 & 0xff0000) >> 16); + if (LM_NvramRead (pDevice, offset + 8, &ver_offset) != + LM_STATUS_SUCCESS) + return; + ver_offset = ((ver_offset & 0xff0000) >> 8) | + ((ver_offset >> 24) & 0xff); + for (i = 0; i < 16; i += 4) { + if (LM_NvramRead + (pDevice, offset + ver_offset + i, + &Value32) != LM_STATUS_SUCCESS) { + return; + } + *((LM_UINT32 *) & pDevice->BootCodeVer[i]) = + cpu_to_le32 (Value32); + } + } else { + char c; - if (c < 10) { - pDevice->BootCodeVer[i++] = c + '0'; + if (LM_NvramRead (pDevice, 0x94, &Value32) != LM_STATUS_SUCCESS) + return; + + i = 0; + c = ((Value32 & 0xff0000) >> 16); + + if (c < 10) { + pDevice->BootCodeVer[i++] = c + '0'; + } else { + pDevice->BootCodeVer[i++] = (c / 10) + '0'; + pDevice->BootCodeVer[i++] = (c % 10) + '0'; + } + pDevice->BootCodeVer[i++] = '.'; + c = (Value32 & 0xff000000) >> 24; + if (c < 10) { + pDevice->BootCodeVer[i++] = c + '0'; + } else { + pDevice->BootCodeVer[i++] = (c / 10) + '0'; + pDevice->BootCodeVer[i++] = (c % 10) + '0'; + } + pDevice->BootCodeVer[i] = 0; } - else { - pDevice->BootCodeVer[i++] = (c / 10) + '0'; - pDevice->BootCodeVer[i++] = (c % 10) + '0'; - } - pDevice->BootCodeVer[i++] = '.'; - c = (Value32 & 0xff000000) >> 24; - if (c < 10) { - pDevice->BootCodeVer[i++] = c + '0'; - } - else { - pDevice->BootCodeVer[i++] = (c / 10) + '0'; - pDevice->BootCodeVer[i++] = (c % 10) + '0'; - } - pDevice->BootCodeVer[i] = 0; - } } -STATIC void -LM_GetBusSpeed(PLM_DEVICE_BLOCK pDevice) +STATIC void LM_GetBusSpeed (PLM_DEVICE_BLOCK pDevice) { - LM_UINT32 PciState = pDevice->PciState; - LM_UINT32 ClockCtrl; - char *SpeedStr = ""; + LM_UINT32 PciState = pDevice->PciState; + LM_UINT32 ClockCtrl; + char *SpeedStr = ""; - if (PciState & T3_PCI_STATE_32BIT_PCI_BUS) - { - strcpy(pDevice->BusSpeedStr, "32-bit "); - } - else - { - strcpy(pDevice->BusSpeedStr, "64-bit "); - } - if (PciState & T3_PCI_STATE_CONVENTIONAL_PCI_MODE) - { - strcat(pDevice->BusSpeedStr, "PCI "); - if (PciState & T3_PCI_STATE_HIGH_BUS_SPEED) - { - SpeedStr = "66MHz"; + if (PciState & T3_PCI_STATE_32BIT_PCI_BUS) { + strcpy (pDevice->BusSpeedStr, "32-bit "); + } else { + strcpy (pDevice->BusSpeedStr, "64-bit "); } - else - { - SpeedStr = "33MHz"; + if (PciState & T3_PCI_STATE_CONVENTIONAL_PCI_MODE) { + strcat (pDevice->BusSpeedStr, "PCI "); + if (PciState & T3_PCI_STATE_HIGH_BUS_SPEED) { + SpeedStr = "66MHz"; + } else { + SpeedStr = "33MHz"; + } + } else { + strcat (pDevice->BusSpeedStr, "PCIX "); + if (pDevice->BondId == GRC_MISC_BD_ID_5704CIOBE) { + SpeedStr = "133MHz"; + } else { + ClockCtrl = REG_RD (pDevice, PciCfg.ClockCtrl) & 0x1f; + switch (ClockCtrl) { + case 0: + SpeedStr = "33MHz"; + break; + + case 2: + SpeedStr = "50MHz"; + break; + + case 4: + SpeedStr = "66MHz"; + break; + + case 6: + SpeedStr = "100MHz"; + break; + + case 7: + SpeedStr = "133MHz"; + break; + } + } } - } - else - { - strcat(pDevice->BusSpeedStr, "PCIX "); - if (pDevice->BondId == GRC_MISC_BD_ID_5704CIOBE) - { - SpeedStr = "133MHz"; - } - else - { - ClockCtrl = REG_RD(pDevice, PciCfg.ClockCtrl) & 0x1f; - switch (ClockCtrl) - { - case 0: - SpeedStr = "33MHz"; - break; - - case 2: - SpeedStr = "50MHz"; - break; - - case 4: - SpeedStr = "66MHz"; - break; - - case 6: - SpeedStr = "100MHz"; - break; - - case 7: - SpeedStr = "133MHz"; - break; - } - } - } - strcat(pDevice->BusSpeedStr, SpeedStr); + strcat (pDevice->BusSpeedStr, SpeedStr); } /******************************************************************************/ @@ -660,977 +598,890 @@ LM_GetBusSpeed(PLM_DEVICE_BLOCK pDevice) /* Return: */ /* LM_STATUS_SUCCESS */ /******************************************************************************/ -LM_STATUS -LM_GetAdapterInfo( -PLM_DEVICE_BLOCK pDevice) +LM_STATUS LM_GetAdapterInfo (PLM_DEVICE_BLOCK pDevice) { - PLM_ADAPTER_INFO pAdapterInfo; - LM_UINT32 Value32; - LM_STATUS Status; - LM_UINT32 j; - LM_UINT32 EeSigFound; - LM_UINT32 EePhyTypeSerdes = 0; - LM_UINT32 EePhyLedMode = 0; - LM_UINT32 EePhyId = 0; + PLM_ADAPTER_INFO pAdapterInfo; + LM_UINT32 Value32; + LM_STATUS Status; + LM_UINT32 j; + LM_UINT32 EeSigFound; + LM_UINT32 EePhyTypeSerdes = 0; + LM_UINT32 EePhyLedMode = 0; + LM_UINT32 EePhyId = 0; - /* Get Device Id and Vendor Id */ - Status = MM_ReadConfig32(pDevice, PCI_VENDOR_ID_REG, &Value32); - if(Status != LM_STATUS_SUCCESS) - { - return Status; - } - pDevice->PciVendorId = (LM_UINT16) Value32; - pDevice->PciDeviceId = (LM_UINT16) (Value32 >> 16); + /* Get Device Id and Vendor Id */ + Status = MM_ReadConfig32 (pDevice, PCI_VENDOR_ID_REG, &Value32); + if (Status != LM_STATUS_SUCCESS) { + return Status; + } + pDevice->PciVendorId = (LM_UINT16) Value32; + pDevice->PciDeviceId = (LM_UINT16) (Value32 >> 16); - /* If we are not getting the write adapter, exit. */ - if((Value32 != T3_PCI_ID_BCM5700) && - (Value32 != T3_PCI_ID_BCM5701) && - (Value32 != T3_PCI_ID_BCM5702) && - (Value32 != T3_PCI_ID_BCM5702x) && - (Value32 != T3_PCI_ID_BCM5702FE) && - (Value32 != T3_PCI_ID_BCM5703) && - (Value32 != T3_PCI_ID_BCM5703x) && - (Value32 != T3_PCI_ID_BCM5704)) - { - return LM_STATUS_FAILURE; - } + /* If we are not getting the write adapter, exit. */ + if ((Value32 != T3_PCI_ID_BCM5700) && + (Value32 != T3_PCI_ID_BCM5701) && + (Value32 != T3_PCI_ID_BCM5702) && + (Value32 != T3_PCI_ID_BCM5702x) && + (Value32 != T3_PCI_ID_BCM5702FE) && + (Value32 != T3_PCI_ID_BCM5703) && + (Value32 != T3_PCI_ID_BCM5703x) && (Value32 != T3_PCI_ID_BCM5704)) { + return LM_STATUS_FAILURE; + } - Status = MM_ReadConfig32(pDevice, PCI_REV_ID_REG, &Value32); - if(Status != LM_STATUS_SUCCESS) - { - return Status; - } - pDevice->PciRevId = (LM_UINT8) Value32; + Status = MM_ReadConfig32 (pDevice, PCI_REV_ID_REG, &Value32); + if (Status != LM_STATUS_SUCCESS) { + return Status; + } + pDevice->PciRevId = (LM_UINT8) Value32; - /* Get IRQ. */ - Status = MM_ReadConfig32(pDevice, PCI_INT_LINE_REG, &Value32); - if(Status != LM_STATUS_SUCCESS) - { - return Status; - } - pDevice->Irq = (LM_UINT8) Value32; + /* Get IRQ. */ + Status = MM_ReadConfig32 (pDevice, PCI_INT_LINE_REG, &Value32); + if (Status != LM_STATUS_SUCCESS) { + return Status; + } + pDevice->Irq = (LM_UINT8) Value32; - /* Get interrupt pin. */ - pDevice->IntPin = (LM_UINT8) (Value32 >> 8); + /* Get interrupt pin. */ + pDevice->IntPin = (LM_UINT8) (Value32 >> 8); - /* Get chip revision id. */ - Status = MM_ReadConfig32(pDevice, T3_PCI_MISC_HOST_CTRL_REG, &Value32); - pDevice->ChipRevId = Value32 >> 16; + /* Get chip revision id. */ + Status = MM_ReadConfig32 (pDevice, T3_PCI_MISC_HOST_CTRL_REG, &Value32); + pDevice->ChipRevId = Value32 >> 16; - /* Get subsystem vendor. */ - Status = MM_ReadConfig32(pDevice, PCI_SUBSYSTEM_VENDOR_ID_REG, &Value32); - if(Status != LM_STATUS_SUCCESS) - { - return Status; - } - pDevice->SubsystemVendorId = (LM_UINT16) Value32; + /* Get subsystem vendor. */ + Status = + MM_ReadConfig32 (pDevice, PCI_SUBSYSTEM_VENDOR_ID_REG, &Value32); + if (Status != LM_STATUS_SUCCESS) { + return Status; + } + pDevice->SubsystemVendorId = (LM_UINT16) Value32; - /* Get PCI subsystem id. */ - pDevice->SubsystemId = (LM_UINT16) (Value32 >> 16); + /* Get PCI subsystem id. */ + pDevice->SubsystemId = (LM_UINT16) (Value32 >> 16); - /* Get the cache line size. */ - MM_ReadConfig32(pDevice, PCI_CACHE_LINE_SIZE_REG, &Value32); - pDevice->CacheLineSize = (LM_UINT8) Value32; - pDevice->SavedCacheLineReg = Value32; + /* Get the cache line size. */ + MM_ReadConfig32 (pDevice, PCI_CACHE_LINE_SIZE_REG, &Value32); + pDevice->CacheLineSize = (LM_UINT8) Value32; + pDevice->SavedCacheLineReg = Value32; - if(pDevice->ChipRevId != T3_CHIP_ID_5703_A1 && - pDevice->ChipRevId != T3_CHIP_ID_5703_A2 && - pDevice->ChipRevId != T3_CHIP_ID_5704_A0) - { - pDevice->UndiFix = FALSE; - } + if (pDevice->ChipRevId != T3_CHIP_ID_5703_A1 && + pDevice->ChipRevId != T3_CHIP_ID_5703_A2 && + pDevice->ChipRevId != T3_CHIP_ID_5704_A0) { + pDevice->UndiFix = FALSE; + } #if !PCIX_TARGET_WORKAROUND - pDevice->UndiFix = FALSE; + pDevice->UndiFix = FALSE; #endif - /* Map the memory base to system address space. */ - if (!pDevice->UndiFix) - { - Status = MM_MapMemBase(pDevice); - if(Status != LM_STATUS_SUCCESS) - { - return Status; + /* Map the memory base to system address space. */ + if (!pDevice->UndiFix) { + Status = MM_MapMemBase (pDevice); + if (Status != LM_STATUS_SUCCESS) { + return Status; + } + /* Initialize the memory view pointer. */ + pDevice->pMemView = (PT3_STD_MEM_MAP) pDevice->pMappedMemBase; } - /* Initialize the memory view pointer. */ - pDevice->pMemView = (PT3_STD_MEM_MAP) pDevice->pMappedMemBase; - } +#if PCIX_TARGET_WORKAROUND + /* store whether we are in PCI are PCI-X mode */ + pDevice->EnablePciXFix = FALSE; + + MM_ReadConfig32 (pDevice, T3_PCI_STATE_REG, &Value32); + if ((Value32 & T3_PCI_STATE_CONVENTIONAL_PCI_MODE) == 0) { + /* Enable PCI-X workaround only if we are running on 5700 BX. */ + if (T3_CHIP_REV (pDevice->ChipRevId) == T3_CHIP_REV_5700_BX) { + pDevice->EnablePciXFix = TRUE; + } + } + if (pDevice->UndiFix) { + pDevice->EnablePciXFix = TRUE; + } +#endif + /* Bx bug: due to the "byte_enable bug" in PCI-X mode, the power */ + /* management register may be clobbered which may cause the */ + /* BCM5700 to go into D3 state. While in this state, we will */ + /* not have memory mapped register access. As a workaround, we */ + /* need to restore the device to D0 state. */ + MM_ReadConfig32 (pDevice, T3_PCI_PM_STATUS_CTRL_REG, &Value32); + Value32 |= T3_PM_PME_ASSERTED; + Value32 &= ~T3_PM_POWER_STATE_MASK; + Value32 |= T3_PM_POWER_STATE_D0; + MM_WriteConfig32 (pDevice, T3_PCI_PM_STATUS_CTRL_REG, Value32); + + /* read the current PCI command word */ + MM_ReadConfig32 (pDevice, PCI_COMMAND_REG, &Value32); + + /* Make sure bus-mastering is enabled. */ + Value32 |= PCI_BUSMASTER_ENABLE; #if PCIX_TARGET_WORKAROUND - /* store whether we are in PCI are PCI-X mode */ - pDevice->EnablePciXFix = FALSE; - - MM_ReadConfig32(pDevice, T3_PCI_STATE_REG, &Value32); - if((Value32 & T3_PCI_STATE_CONVENTIONAL_PCI_MODE) == 0) - { - /* Enable PCI-X workaround only if we are running on 5700 BX. */ - if(T3_CHIP_REV(pDevice->ChipRevId) == T3_CHIP_REV_5700_BX) - { - pDevice->EnablePciXFix = TRUE; + /* if we are in PCI-X mode, also make sure mem-mapping and SERR#/PERR# + are enabled */ + if (pDevice->EnablePciXFix == TRUE) { + Value32 |= (PCI_MEM_SPACE_ENABLE | PCI_SYSTEM_ERROR_ENABLE | + PCI_PARITY_ERROR_ENABLE); + } + if (pDevice->UndiFix) { + Value32 &= ~PCI_MEM_SPACE_ENABLE; } - } - if (pDevice->UndiFix) - { - pDevice->EnablePciXFix = TRUE; - } -#endif - /* Bx bug: due to the "byte_enable bug" in PCI-X mode, the power */ - /* management register may be clobbered which may cause the */ - /* BCM5700 to go into D3 state. While in this state, we will */ - /* not have memory mapped register access. As a workaround, we */ - /* need to restore the device to D0 state. */ - MM_ReadConfig32(pDevice, T3_PCI_PM_STATUS_CTRL_REG, &Value32); - Value32 |= T3_PM_PME_ASSERTED; - Value32 &= ~T3_PM_POWER_STATE_MASK; - Value32 |= T3_PM_POWER_STATE_D0; - MM_WriteConfig32(pDevice, T3_PCI_PM_STATUS_CTRL_REG, Value32); - - /* read the current PCI command word */ - MM_ReadConfig32(pDevice, PCI_COMMAND_REG, &Value32); - - /* Make sure bus-mastering is enabled. */ - Value32 |= PCI_BUSMASTER_ENABLE; - -#if PCIX_TARGET_WORKAROUND - /* if we are in PCI-X mode, also make sure mem-mapping and SERR#/PERR# - are enabled */ - if (pDevice->EnablePciXFix == TRUE) { - Value32 |= (PCI_MEM_SPACE_ENABLE | PCI_SYSTEM_ERROR_ENABLE | - PCI_PARITY_ERROR_ENABLE); - } - if (pDevice->UndiFix) - { - Value32 &= ~PCI_MEM_SPACE_ENABLE; - } - #endif - if(pDevice->EnableMWI) - { - Value32 |= PCI_MEMORY_WRITE_INVALIDATE; - } - else { - Value32 &= (~PCI_MEMORY_WRITE_INVALIDATE); - } + if (pDevice->EnableMWI) { + Value32 |= PCI_MEMORY_WRITE_INVALIDATE; + } else { + Value32 &= (~PCI_MEMORY_WRITE_INVALIDATE); + } - /* Error out if mem-mapping is NOT enabled for PCI systems */ - if (!(Value32 | PCI_MEM_SPACE_ENABLE)) - { - return LM_STATUS_FAILURE; - } + /* Error out if mem-mapping is NOT enabled for PCI systems */ + if (!(Value32 | PCI_MEM_SPACE_ENABLE)) { + return LM_STATUS_FAILURE; + } - /* save the value we are going to write into the PCI command word */ - pDevice->PciCommandStatusWords = Value32; + /* save the value we are going to write into the PCI command word */ + pDevice->PciCommandStatusWords = Value32; - Status = MM_WriteConfig32(pDevice, PCI_COMMAND_REG, Value32); - if(Status != LM_STATUS_SUCCESS) - { - return Status; - } + Status = MM_WriteConfig32 (pDevice, PCI_COMMAND_REG, Value32); + if (Status != LM_STATUS_SUCCESS) { + return Status; + } - /* Set power state to D0. */ - LM_SetPowerState(pDevice, LM_POWER_STATE_D0); + /* Set power state to D0. */ + LM_SetPowerState (pDevice, LM_POWER_STATE_D0); #ifdef BIG_ENDIAN_PCI - pDevice->MiscHostCtrl = - MISC_HOST_CTRL_MASK_PCI_INT | - MISC_HOST_CTRL_ENABLE_INDIRECT_ACCESS | - MISC_HOST_CTRL_ENABLE_ENDIAN_WORD_SWAP | - MISC_HOST_CTRL_ENABLE_PCI_STATE_REG_RW; -#else /* No CPU Swap modes for PCI IO */ + pDevice->MiscHostCtrl = + MISC_HOST_CTRL_MASK_PCI_INT | + MISC_HOST_CTRL_ENABLE_INDIRECT_ACCESS | + MISC_HOST_CTRL_ENABLE_ENDIAN_WORD_SWAP | + MISC_HOST_CTRL_ENABLE_PCI_STATE_REG_RW; +#else /* No CPU Swap modes for PCI IO */ - /* Setup the mode registers. */ - pDevice->MiscHostCtrl = - MISC_HOST_CTRL_MASK_PCI_INT | - MISC_HOST_CTRL_ENABLE_ENDIAN_WORD_SWAP | + /* Setup the mode registers. */ + pDevice->MiscHostCtrl = + MISC_HOST_CTRL_MASK_PCI_INT | + MISC_HOST_CTRL_ENABLE_ENDIAN_WORD_SWAP | #ifdef BIG_ENDIAN_HOST - MISC_HOST_CTRL_ENABLE_ENDIAN_BYTE_SWAP | -#endif /* BIG_ENDIAN_HOST */ - MISC_HOST_CTRL_ENABLE_INDIRECT_ACCESS | - MISC_HOST_CTRL_ENABLE_PCI_STATE_REG_RW; -#endif /* !BIG_ENDIAN_PCI */ + MISC_HOST_CTRL_ENABLE_ENDIAN_BYTE_SWAP | +#endif /* BIG_ENDIAN_HOST */ + MISC_HOST_CTRL_ENABLE_INDIRECT_ACCESS | + MISC_HOST_CTRL_ENABLE_PCI_STATE_REG_RW; +#endif /* !BIG_ENDIAN_PCI */ - /* write to PCI misc host ctr first in order to enable indirect accesses */ - MM_WriteConfig32(pDevice, T3_PCI_MISC_HOST_CTRL_REG, pDevice->MiscHostCtrl); + /* write to PCI misc host ctr first in order to enable indirect accesses */ + MM_WriteConfig32 (pDevice, T3_PCI_MISC_HOST_CTRL_REG, + pDevice->MiscHostCtrl); - REG_WR(pDevice, PciCfg.MiscHostCtrl, pDevice->MiscHostCtrl); + REG_WR (pDevice, PciCfg.MiscHostCtrl, pDevice->MiscHostCtrl); #ifdef BIG_ENDIAN_PCI - Value32 = GRC_MODE_WORD_SWAP_DATA| - GRC_MODE_WORD_SWAP_NON_FRAME_DATA; + Value32 = GRC_MODE_WORD_SWAP_DATA | GRC_MODE_WORD_SWAP_NON_FRAME_DATA; #else /* No CPU Swap modes for PCI IO */ #ifdef BIG_ENDIAN_HOST - Value32 = GRC_MODE_BYTE_SWAP_NON_FRAME_DATA | - GRC_MODE_WORD_SWAP_NON_FRAME_DATA; + Value32 = GRC_MODE_BYTE_SWAP_NON_FRAME_DATA | + GRC_MODE_WORD_SWAP_NON_FRAME_DATA; #else - Value32 = GRC_MODE_BYTE_SWAP_NON_FRAME_DATA | GRC_MODE_BYTE_SWAP_DATA; + Value32 = GRC_MODE_BYTE_SWAP_NON_FRAME_DATA | GRC_MODE_BYTE_SWAP_DATA; #endif -#endif /* !BIG_ENDIAN_PCI */ +#endif /* !BIG_ENDIAN_PCI */ - REG_WR(pDevice, Grc.Mode, Value32); + REG_WR (pDevice, Grc.Mode, Value32); - if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700) - { - REG_WR(pDevice, Grc.LocalCtrl, GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT1 | - GRC_MISC_LOCAL_CTRL_GPIO_OE1); - } - MM_Wait(40); + if (T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5700) { + REG_WR (pDevice, Grc.LocalCtrl, + GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT1 | + GRC_MISC_LOCAL_CTRL_GPIO_OE1); + } + MM_Wait (40); - /* Enable indirect memory access */ - REG_WR(pDevice, MemArbiter.Mode, T3_MEM_ARBITER_MODE_ENABLE); + /* Enable indirect memory access */ + REG_WR (pDevice, MemArbiter.Mode, T3_MEM_ARBITER_MODE_ENABLE); - if (REG_RD(pDevice, PciCfg.ClockCtrl) & T3_PCI_44MHZ_CORE_CLOCK) - { - REG_WR(pDevice, PciCfg.ClockCtrl, T3_PCI_44MHZ_CORE_CLOCK | - T3_PCI_SELECT_ALTERNATE_CLOCK); - REG_WR(pDevice, PciCfg.ClockCtrl, T3_PCI_SELECT_ALTERNATE_CLOCK); - MM_Wait(40); /* required delay is 27usec */ - } - REG_WR(pDevice, PciCfg.ClockCtrl, 0); - REG_WR(pDevice, PciCfg.MemWindowBaseAddr, 0); + if (REG_RD (pDevice, PciCfg.ClockCtrl) & T3_PCI_44MHZ_CORE_CLOCK) { + REG_WR (pDevice, PciCfg.ClockCtrl, T3_PCI_44MHZ_CORE_CLOCK | + T3_PCI_SELECT_ALTERNATE_CLOCK); + REG_WR (pDevice, PciCfg.ClockCtrl, + T3_PCI_SELECT_ALTERNATE_CLOCK); + MM_Wait (40); /* required delay is 27usec */ + } + REG_WR (pDevice, PciCfg.ClockCtrl, 0); + REG_WR (pDevice, PciCfg.MemWindowBaseAddr, 0); #if PCIX_TARGET_WORKAROUND - MM_ReadConfig32(pDevice, T3_PCI_STATE_REG, &Value32); - if ((pDevice->EnablePciXFix == FALSE) && - ((Value32 & T3_PCI_STATE_CONVENTIONAL_PCI_MODE) == 0)) - { - if (pDevice->ChipRevId == T3_CHIP_ID_5701_A0 || - pDevice->ChipRevId == T3_CHIP_ID_5701_B0 || - pDevice->ChipRevId == T3_CHIP_ID_5701_B2 || - pDevice->ChipRevId == T3_CHIP_ID_5701_B5) - { - __raw_writel(0, &(pDevice->pMemView->uIntMem.MemBlock32K[0x300])); - __raw_writel(0, &(pDevice->pMemView->uIntMem.MemBlock32K[0x301])); - __raw_writel(0xffffffff, &(pDevice->pMemView->uIntMem.MemBlock32K[0x301])); - if (__raw_readl(&(pDevice->pMemView->uIntMem.MemBlock32K[0x300]))) - { - pDevice->EnablePciXFix = TRUE; - } + MM_ReadConfig32 (pDevice, T3_PCI_STATE_REG, &Value32); + if ((pDevice->EnablePciXFix == FALSE) && + ((Value32 & T3_PCI_STATE_CONVENTIONAL_PCI_MODE) == 0)) { + if (pDevice->ChipRevId == T3_CHIP_ID_5701_A0 || + pDevice->ChipRevId == T3_CHIP_ID_5701_B0 || + pDevice->ChipRevId == T3_CHIP_ID_5701_B2 || + pDevice->ChipRevId == T3_CHIP_ID_5701_B5) { + __raw_writel (0, + &(pDevice->pMemView->uIntMem. + MemBlock32K[0x300])); + __raw_writel (0, + &(pDevice->pMemView->uIntMem. + MemBlock32K[0x301])); + __raw_writel (0xffffffff, + &(pDevice->pMemView->uIntMem. + MemBlock32K[0x301])); + if (__raw_readl + (&(pDevice->pMemView->uIntMem.MemBlock32K[0x300]))) + { + pDevice->EnablePciXFix = TRUE; + } + } } - } #endif #if 1 - /* - * This code was at the beginning of else block below, but that's - * a bug if node address in shared memory. - */ - MM_Wait(50); - LM_NvramInit(pDevice); + /* + * This code was at the beginning of else block below, but that's + * a bug if node address in shared memory. + */ + MM_Wait (50); + LM_NvramInit (pDevice); #endif - /* Get the node address. First try to get in from the shared memory. */ - /* If the signature is not present, then get it from the NVRAM. */ - Value32 = MEM_RD_OFFSET(pDevice, T3_MAC_ADDR_HIGH_MAILBOX); - if((Value32 >> 16) == 0x484b) - { + /* Get the node address. First try to get in from the shared memory. */ + /* If the signature is not present, then get it from the NVRAM. */ + Value32 = MEM_RD_OFFSET (pDevice, T3_MAC_ADDR_HIGH_MAILBOX); + if ((Value32 >> 16) == 0x484b) { - pDevice->NodeAddress[0] = (LM_UINT8) (Value32 >> 8); - pDevice->NodeAddress[1] = (LM_UINT8) Value32; + pDevice->NodeAddress[0] = (LM_UINT8) (Value32 >> 8); + pDevice->NodeAddress[1] = (LM_UINT8) Value32; - Value32 = MEM_RD_OFFSET(pDevice, T3_MAC_ADDR_LOW_MAILBOX); + Value32 = MEM_RD_OFFSET (pDevice, T3_MAC_ADDR_LOW_MAILBOX); - pDevice->NodeAddress[2] = (LM_UINT8) (Value32 >> 24); - pDevice->NodeAddress[3] = (LM_UINT8) (Value32 >> 16); - pDevice->NodeAddress[4] = (LM_UINT8) (Value32 >> 8); - pDevice->NodeAddress[5] = (LM_UINT8) Value32; + pDevice->NodeAddress[2] = (LM_UINT8) (Value32 >> 24); + pDevice->NodeAddress[3] = (LM_UINT8) (Value32 >> 16); + pDevice->NodeAddress[4] = (LM_UINT8) (Value32 >> 8); + pDevice->NodeAddress[5] = (LM_UINT8) Value32; - Status = LM_STATUS_SUCCESS; - } - else - { - Status = LM_NvramRead(pDevice, 0x7c, &Value32); - if(Status == LM_STATUS_SUCCESS) - { - pDevice->NodeAddress[0] = (LM_UINT8) (Value32 >> 16); - pDevice->NodeAddress[1] = (LM_UINT8) (Value32 >> 24); + Status = LM_STATUS_SUCCESS; + } else { + Status = LM_NvramRead (pDevice, 0x7c, &Value32); + if (Status == LM_STATUS_SUCCESS) { + pDevice->NodeAddress[0] = (LM_UINT8) (Value32 >> 16); + pDevice->NodeAddress[1] = (LM_UINT8) (Value32 >> 24); - Status = LM_NvramRead(pDevice, 0x80, &Value32); + Status = LM_NvramRead (pDevice, 0x80, &Value32); - pDevice->NodeAddress[2] = (LM_UINT8) Value32; - pDevice->NodeAddress[3] = (LM_UINT8) (Value32 >> 8); - pDevice->NodeAddress[4] = (LM_UINT8) (Value32 >> 16); - pDevice->NodeAddress[5] = (LM_UINT8) (Value32 >> 24); + pDevice->NodeAddress[2] = (LM_UINT8) Value32; + pDevice->NodeAddress[3] = (LM_UINT8) (Value32 >> 8); + pDevice->NodeAddress[4] = (LM_UINT8) (Value32 >> 16); + pDevice->NodeAddress[5] = (LM_UINT8) (Value32 >> 24); + } } - } - /* Assign a default address. */ - if(Status != LM_STATUS_SUCCESS) - { + /* Assign a default address. */ + if (Status != LM_STATUS_SUCCESS) { #ifndef EMBEDDED - printk(KERN_ERR "Cannot get MAC addr from NVRAM. Using default.\n"); + printk (KERN_ERR + "Cannot get MAC addr from NVRAM. Using default.\n"); #endif - pDevice->NodeAddress[0] = 0x00; pDevice->NodeAddress[1] = 0x10; - pDevice->NodeAddress[2] = 0x18; pDevice->NodeAddress[3] = 0x68; - pDevice->NodeAddress[4] = 0x61; pDevice->NodeAddress[5] = 0x76; - } + pDevice->NodeAddress[0] = 0x00; + pDevice->NodeAddress[1] = 0x10; + pDevice->NodeAddress[2] = 0x18; + pDevice->NodeAddress[3] = 0x68; + pDevice->NodeAddress[4] = 0x61; + pDevice->NodeAddress[5] = 0x76; + } - pDevice->PermanentNodeAddress[0] = pDevice->NodeAddress[0]; - pDevice->PermanentNodeAddress[1] = pDevice->NodeAddress[1]; - pDevice->PermanentNodeAddress[2] = pDevice->NodeAddress[2]; - pDevice->PermanentNodeAddress[3] = pDevice->NodeAddress[3]; - pDevice->PermanentNodeAddress[4] = pDevice->NodeAddress[4]; - pDevice->PermanentNodeAddress[5] = pDevice->NodeAddress[5]; + pDevice->PermanentNodeAddress[0] = pDevice->NodeAddress[0]; + pDevice->PermanentNodeAddress[1] = pDevice->NodeAddress[1]; + pDevice->PermanentNodeAddress[2] = pDevice->NodeAddress[2]; + pDevice->PermanentNodeAddress[3] = pDevice->NodeAddress[3]; + pDevice->PermanentNodeAddress[4] = pDevice->NodeAddress[4]; + pDevice->PermanentNodeAddress[5] = pDevice->NodeAddress[5]; - /* Initialize the default values. */ - pDevice->NoTxPseudoHdrChksum = FALSE; - pDevice->NoRxPseudoHdrChksum = FALSE; - pDevice->NicSendBd = FALSE; - pDevice->TxPacketDescCnt = DEFAULT_TX_PACKET_DESC_COUNT; - pDevice->RxStdDescCnt = DEFAULT_STD_RCV_DESC_COUNT; - pDevice->RxCoalescingTicks = DEFAULT_RX_COALESCING_TICKS; - pDevice->TxCoalescingTicks = DEFAULT_TX_COALESCING_TICKS; - pDevice->RxMaxCoalescedFrames = DEFAULT_RX_MAX_COALESCED_FRAMES; - pDevice->TxMaxCoalescedFrames = DEFAULT_TX_MAX_COALESCED_FRAMES; - pDevice->RxCoalescingTicksDuringInt = BAD_DEFAULT_VALUE; - pDevice->TxCoalescingTicksDuringInt = BAD_DEFAULT_VALUE; - pDevice->RxMaxCoalescedFramesDuringInt = BAD_DEFAULT_VALUE; - pDevice->TxMaxCoalescedFramesDuringInt = BAD_DEFAULT_VALUE; - pDevice->StatsCoalescingTicks = DEFAULT_STATS_COALESCING_TICKS; - pDevice->EnableMWI = FALSE; - pDevice->TxMtu = MAX_ETHERNET_PACKET_SIZE_NO_CRC; - pDevice->RxMtu = MAX_ETHERNET_PACKET_SIZE_NO_CRC; - pDevice->DisableAutoNeg = FALSE; - pDevice->PhyIntMode = T3_PHY_INT_MODE_AUTO; - pDevice->LinkChngMode = T3_LINK_CHNG_MODE_AUTO; - pDevice->LedMode = LED_MODE_AUTO; - pDevice->ResetPhyOnInit = TRUE; - pDevice->DelayPciGrant = TRUE; - pDevice->UseTaggedStatus = FALSE; - pDevice->OneDmaAtOnce = BAD_DEFAULT_VALUE; + /* Initialize the default values. */ + pDevice->NoTxPseudoHdrChksum = FALSE; + pDevice->NoRxPseudoHdrChksum = FALSE; + pDevice->NicSendBd = FALSE; + pDevice->TxPacketDescCnt = DEFAULT_TX_PACKET_DESC_COUNT; + pDevice->RxStdDescCnt = DEFAULT_STD_RCV_DESC_COUNT; + pDevice->RxCoalescingTicks = DEFAULT_RX_COALESCING_TICKS; + pDevice->TxCoalescingTicks = DEFAULT_TX_COALESCING_TICKS; + pDevice->RxMaxCoalescedFrames = DEFAULT_RX_MAX_COALESCED_FRAMES; + pDevice->TxMaxCoalescedFrames = DEFAULT_TX_MAX_COALESCED_FRAMES; + pDevice->RxCoalescingTicksDuringInt = BAD_DEFAULT_VALUE; + pDevice->TxCoalescingTicksDuringInt = BAD_DEFAULT_VALUE; + pDevice->RxMaxCoalescedFramesDuringInt = BAD_DEFAULT_VALUE; + pDevice->TxMaxCoalescedFramesDuringInt = BAD_DEFAULT_VALUE; + pDevice->StatsCoalescingTicks = DEFAULT_STATS_COALESCING_TICKS; + pDevice->EnableMWI = FALSE; + pDevice->TxMtu = MAX_ETHERNET_PACKET_SIZE_NO_CRC; + pDevice->RxMtu = MAX_ETHERNET_PACKET_SIZE_NO_CRC; + pDevice->DisableAutoNeg = FALSE; + pDevice->PhyIntMode = T3_PHY_INT_MODE_AUTO; + pDevice->LinkChngMode = T3_LINK_CHNG_MODE_AUTO; + pDevice->LedMode = LED_MODE_AUTO; + pDevice->ResetPhyOnInit = TRUE; + pDevice->DelayPciGrant = TRUE; + pDevice->UseTaggedStatus = FALSE; + pDevice->OneDmaAtOnce = BAD_DEFAULT_VALUE; - pDevice->DmaMbufLowMark = T3_DEF_DMA_MBUF_LOW_WMARK_JUMBO; - pDevice->RxMacMbufLowMark = T3_DEF_RX_MAC_MBUF_LOW_WMARK_JUMBO; - pDevice->MbufHighMark = T3_DEF_MBUF_HIGH_WMARK_JUMBO; + pDevice->DmaMbufLowMark = T3_DEF_DMA_MBUF_LOW_WMARK_JUMBO; + pDevice->RxMacMbufLowMark = T3_DEF_RX_MAC_MBUF_LOW_WMARK_JUMBO; + pDevice->MbufHighMark = T3_DEF_MBUF_HIGH_WMARK_JUMBO; - pDevice->RequestedMediaType = LM_REQUESTED_MEDIA_TYPE_AUTO; - pDevice->TaskOffloadCap = LM_TASK_OFFLOAD_NONE; - pDevice->FlowControlCap = LM_FLOW_CONTROL_AUTO_PAUSE; - pDevice->EnableTbi = FALSE; + pDevice->RequestedMediaType = LM_REQUESTED_MEDIA_TYPE_AUTO; + pDevice->TaskOffloadCap = LM_TASK_OFFLOAD_NONE; + pDevice->FlowControlCap = LM_FLOW_CONTROL_AUTO_PAUSE; + pDevice->EnableTbi = FALSE; #if INCLUDE_TBI_SUPPORT - pDevice->PollTbiLink = BAD_DEFAULT_VALUE; + pDevice->PollTbiLink = BAD_DEFAULT_VALUE; #endif - switch (T3_ASIC_REV(pDevice->ChipRevId)) - { - case T3_ASIC_REV_5704: - pDevice->MbufBase = T3_NIC_MBUF_POOL_ADDR; - pDevice->MbufSize = T3_NIC_MBUF_POOL_SIZE64; - break; - default: - pDevice->MbufBase = T3_NIC_MBUF_POOL_ADDR; - pDevice->MbufSize = T3_NIC_MBUF_POOL_SIZE96; - break; - } + switch (T3_ASIC_REV (pDevice->ChipRevId)) { + case T3_ASIC_REV_5704: + pDevice->MbufBase = T3_NIC_MBUF_POOL_ADDR; + pDevice->MbufSize = T3_NIC_MBUF_POOL_SIZE64; + break; + default: + pDevice->MbufBase = T3_NIC_MBUF_POOL_ADDR; + pDevice->MbufSize = T3_NIC_MBUF_POOL_SIZE96; + break; + } - pDevice->LinkStatus = LM_STATUS_LINK_DOWN; - pDevice->QueueRxPackets = TRUE; + pDevice->LinkStatus = LM_STATUS_LINK_DOWN; + pDevice->QueueRxPackets = TRUE; - pDevice->EnableWireSpeed = TRUE; + pDevice->EnableWireSpeed = TRUE; #if T3_JUMBO_RCV_RCB_ENTRY_COUNT - pDevice->RxJumboDescCnt = DEFAULT_JUMBO_RCV_DESC_COUNT; -#endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */ + pDevice->RxJumboDescCnt = DEFAULT_JUMBO_RCV_DESC_COUNT; +#endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */ - /* Make this is a known adapter. */ - pAdapterInfo = LM_GetAdapterInfoBySsid(pDevice->SubsystemVendorId, - pDevice->SubsystemId); + /* Make this is a known adapter. */ + pAdapterInfo = LM_GetAdapterInfoBySsid (pDevice->SubsystemVendorId, + pDevice->SubsystemId); - pDevice->BondId = REG_RD(pDevice, Grc.MiscCfg) & GRC_MISC_BD_ID_MASK; - if (pDevice->BondId != GRC_MISC_BD_ID_5700 && - pDevice->BondId != GRC_MISC_BD_ID_5701 && - pDevice->BondId != GRC_MISC_BD_ID_5702FE && - pDevice->BondId != GRC_MISC_BD_ID_5703 && - pDevice->BondId != GRC_MISC_BD_ID_5703S && - pDevice->BondId != GRC_MISC_BD_ID_5704 && - pDevice->BondId != GRC_MISC_BD_ID_5704CIOBE) - { - return LM_STATUS_UNKNOWN_ADAPTER; - } - - pDevice->SplitModeEnable = SPLIT_MODE_DISABLE; - if ((pDevice->ChipRevId == T3_CHIP_ID_5704_A0) && - (pDevice->BondId == GRC_MISC_BD_ID_5704CIOBE)) - { - pDevice->SplitModeEnable = SPLIT_MODE_ENABLE; - pDevice->SplitModeMaxReq = SPLIT_MODE_5704_MAX_REQ; - } - - /* Get Eeprom info. */ - Value32 = MEM_RD_OFFSET(pDevice, T3_NIC_DATA_SIG_ADDR); - if (Value32 == T3_NIC_DATA_SIG) - { - EeSigFound = TRUE; - Value32 = MEM_RD_OFFSET(pDevice, T3_NIC_DATA_NIC_CFG_ADDR); - - /* Determine PHY type. */ - switch (Value32 & T3_NIC_CFG_PHY_TYPE_MASK) - { - case T3_NIC_CFG_PHY_TYPE_COPPER: - EePhyTypeSerdes = FALSE; - break; - - case T3_NIC_CFG_PHY_TYPE_FIBER: - EePhyTypeSerdes = TRUE; - break; - - default: - EePhyTypeSerdes = FALSE; - break; + pDevice->BondId = REG_RD (pDevice, Grc.MiscCfg) & GRC_MISC_BD_ID_MASK; + if (pDevice->BondId != GRC_MISC_BD_ID_5700 && + pDevice->BondId != GRC_MISC_BD_ID_5701 && + pDevice->BondId != GRC_MISC_BD_ID_5702FE && + pDevice->BondId != GRC_MISC_BD_ID_5703 && + pDevice->BondId != GRC_MISC_BD_ID_5703S && + pDevice->BondId != GRC_MISC_BD_ID_5704 && + pDevice->BondId != GRC_MISC_BD_ID_5704CIOBE) { + return LM_STATUS_UNKNOWN_ADAPTER; } - /* Determine PHY led mode. */ - if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700 || - T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5701) - { - switch(Value32 & T3_NIC_CFG_LED_MODE_MASK) - { - case T3_NIC_CFG_LED_MODE_TRIPLE_SPEED: - EePhyLedMode = LED_MODE_THREE_LINK; - break; + pDevice->SplitModeEnable = SPLIT_MODE_DISABLE; + if ((pDevice->ChipRevId == T3_CHIP_ID_5704_A0) && + (pDevice->BondId == GRC_MISC_BD_ID_5704CIOBE)) { + pDevice->SplitModeEnable = SPLIT_MODE_ENABLE; + pDevice->SplitModeMaxReq = SPLIT_MODE_5704_MAX_REQ; + } - case T3_NIC_CFG_LED_MODE_LINK_SPEED: - EePhyLedMode = LED_MODE_LINK10; - break; + /* Get Eeprom info. */ + Value32 = MEM_RD_OFFSET (pDevice, T3_NIC_DATA_SIG_ADDR); + if (Value32 == T3_NIC_DATA_SIG) { + EeSigFound = TRUE; + Value32 = MEM_RD_OFFSET (pDevice, T3_NIC_DATA_NIC_CFG_ADDR); + + /* Determine PHY type. */ + switch (Value32 & T3_NIC_CFG_PHY_TYPE_MASK) { + case T3_NIC_CFG_PHY_TYPE_COPPER: + EePhyTypeSerdes = FALSE; + break; + + case T3_NIC_CFG_PHY_TYPE_FIBER: + EePhyTypeSerdes = TRUE; + break; default: - EePhyLedMode = LED_MODE_AUTO; - break; - } - } - else - { - switch(Value32 & T3_NIC_CFG_LED_MODE_MASK) - { - case T3_NIC_CFG_LED_MODE_OPEN_DRAIN: - EePhyLedMode = LED_MODE_OPEN_DRAIN; - break; + EePhyTypeSerdes = FALSE; + break; + } - case T3_NIC_CFG_LED_MODE_OUTPUT: - EePhyLedMode = LED_MODE_OUTPUT; - break; + /* Determine PHY led mode. */ + if (T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5700 || + T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5701) { + switch (Value32 & T3_NIC_CFG_LED_MODE_MASK) { + case T3_NIC_CFG_LED_MODE_TRIPLE_SPEED: + EePhyLedMode = LED_MODE_THREE_LINK; + break; - default: - EePhyLedMode = LED_MODE_AUTO; - break; - } - } - if(pDevice->ChipRevId == T3_CHIP_ID_5703_A1 || - pDevice->ChipRevId == T3_CHIP_ID_5703_A2) - { - /* Enable EEPROM write protection. */ - if(Value32 & T3_NIC_EEPROM_WP) - { - pDevice->EepromWp = TRUE; - } + case T3_NIC_CFG_LED_MODE_LINK_SPEED: + EePhyLedMode = LED_MODE_LINK10; + break; + + default: + EePhyLedMode = LED_MODE_AUTO; + break; + } + } else { + switch (Value32 & T3_NIC_CFG_LED_MODE_MASK) { + case T3_NIC_CFG_LED_MODE_OPEN_DRAIN: + EePhyLedMode = LED_MODE_OPEN_DRAIN; + break; + + case T3_NIC_CFG_LED_MODE_OUTPUT: + EePhyLedMode = LED_MODE_OUTPUT; + break; + + default: + EePhyLedMode = LED_MODE_AUTO; + break; + } + } + if (pDevice->ChipRevId == T3_CHIP_ID_5703_A1 || + pDevice->ChipRevId == T3_CHIP_ID_5703_A2) { + /* Enable EEPROM write protection. */ + if (Value32 & T3_NIC_EEPROM_WP) { + pDevice->EepromWp = TRUE; + } + } + + /* Get the PHY Id. */ + Value32 = MEM_RD_OFFSET (pDevice, T3_NIC_DATA_PHY_ID_ADDR); + if (Value32) { + EePhyId = (((Value32 & T3_NIC_PHY_ID1_MASK) >> 16) & + PHY_ID1_OUI_MASK) << 10; + + Value32 = Value32 & T3_NIC_PHY_ID2_MASK; + + EePhyId |= ((Value32 & PHY_ID2_OUI_MASK) << 16) | + (Value32 & PHY_ID2_MODEL_MASK) | (Value32 & + PHY_ID2_REV_MASK); + } else { + EePhyId = 0; + } + } else { + EeSigFound = FALSE; } - /* Get the PHY Id. */ - Value32 = MEM_RD_OFFSET(pDevice, T3_NIC_DATA_PHY_ID_ADDR); - if (Value32) - { - EePhyId = (((Value32 & T3_NIC_PHY_ID1_MASK) >> 16) & - PHY_ID1_OUI_MASK) << 10; + /* Set the PHY address. */ + pDevice->PhyAddr = PHY_DEVICE_ID; - Value32 = Value32 & T3_NIC_PHY_ID2_MASK; + /* Disable auto polling. */ + pDevice->MiMode = 0xc0000; + REG_WR (pDevice, MacCtrl.MiMode, pDevice->MiMode); + MM_Wait (40); - EePhyId |= ((Value32 & PHY_ID2_OUI_MASK) << 16) | - (Value32 & PHY_ID2_MODEL_MASK) | (Value32 & PHY_ID2_REV_MASK); - } - else - { - EePhyId = 0; - } - } - else - { - EeSigFound = FALSE; - } + /* Get the PHY id. */ + LM_ReadPhy (pDevice, PHY_ID1_REG, &Value32); + pDevice->PhyId = (Value32 & PHY_ID1_OUI_MASK) << 10; - /* Set the PHY address. */ - pDevice->PhyAddr = PHY_DEVICE_ID; + LM_ReadPhy (pDevice, PHY_ID2_REG, &Value32); + pDevice->PhyId |= ((Value32 & PHY_ID2_OUI_MASK) << 16) | + (Value32 & PHY_ID2_MODEL_MASK) | (Value32 & PHY_ID2_REV_MASK); - /* Disable auto polling. */ - pDevice->MiMode = 0xc0000; - REG_WR(pDevice, MacCtrl.MiMode, pDevice->MiMode); - MM_Wait(40); - - /* Get the PHY id. */ - LM_ReadPhy(pDevice, PHY_ID1_REG, &Value32); - pDevice->PhyId = (Value32 & PHY_ID1_OUI_MASK) << 10; - - LM_ReadPhy(pDevice, PHY_ID2_REG, &Value32); - pDevice->PhyId |= ((Value32 & PHY_ID2_OUI_MASK) << 16) | - (Value32 & PHY_ID2_MODEL_MASK) | (Value32 & PHY_ID2_REV_MASK); - - /* Set the EnableTbi flag to false if we have a copper PHY. */ - switch(pDevice->PhyId & PHY_ID_MASK) - { + /* Set the EnableTbi flag to false if we have a copper PHY. */ + switch (pDevice->PhyId & PHY_ID_MASK) { case PHY_BCM5400_PHY_ID: - pDevice->EnableTbi = FALSE; - break; + pDevice->EnableTbi = FALSE; + break; case PHY_BCM5401_PHY_ID: - pDevice->EnableTbi = FALSE; - break; + pDevice->EnableTbi = FALSE; + break; case PHY_BCM5411_PHY_ID: - pDevice->EnableTbi = FALSE; - break; + pDevice->EnableTbi = FALSE; + break; case PHY_BCM5701_PHY_ID: - pDevice->EnableTbi = FALSE; - break; + pDevice->EnableTbi = FALSE; + break; case PHY_BCM5703_PHY_ID: - pDevice->EnableTbi = FALSE; - break; + pDevice->EnableTbi = FALSE; + break; case PHY_BCM5704_PHY_ID: - pDevice->EnableTbi = FALSE; - break; + pDevice->EnableTbi = FALSE; + break; case PHY_BCM8002_PHY_ID: - pDevice->EnableTbi = TRUE; - break; + pDevice->EnableTbi = TRUE; + break; default: - if (pAdapterInfo) - { - pDevice->PhyId = pAdapterInfo->PhyId; - pDevice->EnableTbi = pAdapterInfo->Serdes; - } - else if (EeSigFound) - { - pDevice->PhyId = EePhyId; - pDevice->EnableTbi = EePhyTypeSerdes; - } - break; - } - - /* Bail out if we don't know the copper PHY id. */ - if(UNKNOWN_PHY_ID(pDevice->PhyId) && !pDevice->EnableTbi) - { - return LM_STATUS_FAILURE; - } - - if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5703) - { - if((pDevice->SavedCacheLineReg & 0xff00) < 0x4000) - { - pDevice->SavedCacheLineReg &= 0xffff00ff; - pDevice->SavedCacheLineReg |= 0x4000; - } - } - /* Change driver parameters. */ - Status = MM_GetConfig(pDevice); - if(Status != LM_STATUS_SUCCESS) - { - return Status; - } - -#if INCLUDE_5701_AX_FIX - if (pDevice->ChipRevId == T3_CHIP_ID_5701_A0 || - pDevice->ChipRevId == T3_CHIP_ID_5701_B0) - { - pDevice->ResetPhyOnInit = TRUE; - } -#endif - - /* Save the current phy link status. */ - if(!pDevice->EnableTbi) - { - LM_ReadPhy(pDevice, PHY_STATUS_REG, &Value32); - LM_ReadPhy(pDevice, PHY_STATUS_REG, &Value32); - - /* If we don't have link reset the PHY. */ - if(!(Value32 & PHY_STATUS_LINK_PASS) || pDevice->ResetPhyOnInit) - { - - LM_WritePhy(pDevice, PHY_CTRL_REG, PHY_CTRL_PHY_RESET); - - for(j = 0; j < 100; j++) - { - MM_Wait(10); - - LM_ReadPhy(pDevice, PHY_CTRL_REG, &Value32); - if(Value32 && !(Value32 & PHY_CTRL_PHY_RESET)) - { - MM_Wait(40); - break; + if (pAdapterInfo) { + pDevice->PhyId = pAdapterInfo->PhyId; + pDevice->EnableTbi = pAdapterInfo->Serdes; + } else if (EeSigFound) { + pDevice->PhyId = EePhyId; + pDevice->EnableTbi = EePhyTypeSerdes; } - } + break; + } + /* Bail out if we don't know the copper PHY id. */ + if (UNKNOWN_PHY_ID (pDevice->PhyId) && !pDevice->EnableTbi) { + return LM_STATUS_FAILURE; + } + + if (T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5703) { + if ((pDevice->SavedCacheLineReg & 0xff00) < 0x4000) { + pDevice->SavedCacheLineReg &= 0xffff00ff; + pDevice->SavedCacheLineReg |= 0x4000; + } + } + /* Change driver parameters. */ + Status = MM_GetConfig (pDevice); + if (Status != LM_STATUS_SUCCESS) { + return Status; + } +#if INCLUDE_5701_AX_FIX + if (pDevice->ChipRevId == T3_CHIP_ID_5701_A0 || + pDevice->ChipRevId == T3_CHIP_ID_5701_B0) { + pDevice->ResetPhyOnInit = TRUE; + } +#endif + + /* Save the current phy link status. */ + if (!pDevice->EnableTbi) { + LM_ReadPhy (pDevice, PHY_STATUS_REG, &Value32); + LM_ReadPhy (pDevice, PHY_STATUS_REG, &Value32); + + /* If we don't have link reset the PHY. */ + if (!(Value32 & PHY_STATUS_LINK_PASS) + || pDevice->ResetPhyOnInit) { + + LM_WritePhy (pDevice, PHY_CTRL_REG, PHY_CTRL_PHY_RESET); + + for (j = 0; j < 100; j++) { + MM_Wait (10); + + LM_ReadPhy (pDevice, PHY_CTRL_REG, &Value32); + if (Value32 && !(Value32 & PHY_CTRL_PHY_RESET)) { + MM_Wait (40); + break; + } + } #if INCLUDE_5701_AX_FIX - /* 5701_AX_BX bug: only advertises 10mb speed. */ - if(pDevice->ChipRevId == T3_CHIP_ID_5701_A0 || - pDevice->ChipRevId == T3_CHIP_ID_5701_B0) - { + /* 5701_AX_BX bug: only advertises 10mb speed. */ + if (pDevice->ChipRevId == T3_CHIP_ID_5701_A0 || + pDevice->ChipRevId == T3_CHIP_ID_5701_B0) { - Value32 = PHY_AN_AD_PROTOCOL_802_3_CSMA_CD | - PHY_AN_AD_10BASET_HALF | PHY_AN_AD_10BASET_FULL | - PHY_AN_AD_100BASETX_FULL | PHY_AN_AD_100BASETX_HALF; - Value32 |= GetPhyAdFlowCntrlSettings(pDevice); - LM_WritePhy(pDevice, PHY_AN_AD_REG, Value32); - pDevice->advertising = Value32; + Value32 = PHY_AN_AD_PROTOCOL_802_3_CSMA_CD | + PHY_AN_AD_10BASET_HALF | + PHY_AN_AD_10BASET_FULL | + PHY_AN_AD_100BASETX_FULL | + PHY_AN_AD_100BASETX_HALF; + Value32 |= GetPhyAdFlowCntrlSettings (pDevice); + LM_WritePhy (pDevice, PHY_AN_AD_REG, Value32); + pDevice->advertising = Value32; - Value32 = BCM540X_AN_AD_1000BASET_HALF | - BCM540X_AN_AD_1000BASET_FULL | BCM540X_CONFIG_AS_MASTER | - BCM540X_ENABLE_CONFIG_AS_MASTER; - LM_WritePhy(pDevice, BCM540X_1000BASET_CTRL_REG, Value32); - pDevice->advertising1000 = Value32; + Value32 = BCM540X_AN_AD_1000BASET_HALF | + BCM540X_AN_AD_1000BASET_FULL | + BCM540X_CONFIG_AS_MASTER | + BCM540X_ENABLE_CONFIG_AS_MASTER; + LM_WritePhy (pDevice, + BCM540X_1000BASET_CTRL_REG, + Value32); + pDevice->advertising1000 = Value32; - LM_WritePhy(pDevice, PHY_CTRL_REG, PHY_CTRL_AUTO_NEG_ENABLE | - PHY_CTRL_RESTART_AUTO_NEG); - } + LM_WritePhy (pDevice, PHY_CTRL_REG, + PHY_CTRL_AUTO_NEG_ENABLE | + PHY_CTRL_RESTART_AUTO_NEG); + } #endif - if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5703) - { - LM_WritePhy(pDevice, 0x18, 0x0c00); - LM_WritePhy(pDevice, 0x17, 0x201f); - LM_WritePhy(pDevice, 0x15, 0x2aaa); - } - if(pDevice->ChipRevId == T3_CHIP_ID_5704_A0) - { - LM_WritePhy(pDevice, 0x1c, 0x8d68); - LM_WritePhy(pDevice, 0x1c, 0x8d68); - } - /* Enable Ethernet@WireSpeed. */ - if(pDevice->EnableWireSpeed) - { - LM_WritePhy(pDevice, 0x18, 0x7007); - LM_ReadPhy(pDevice, 0x18, &Value32); - LM_WritePhy(pDevice, 0x18, Value32 | BIT_15 | BIT_4); - } + if (T3_ASIC_REV (pDevice->ChipRevId) == + T3_ASIC_REV_5703) { + LM_WritePhy (pDevice, 0x18, 0x0c00); + LM_WritePhy (pDevice, 0x17, 0x201f); + LM_WritePhy (pDevice, 0x15, 0x2aaa); + } + if (pDevice->ChipRevId == T3_CHIP_ID_5704_A0) { + LM_WritePhy (pDevice, 0x1c, 0x8d68); + LM_WritePhy (pDevice, 0x1c, 0x8d68); + } + /* Enable Ethernet@WireSpeed. */ + if (pDevice->EnableWireSpeed) { + LM_WritePhy (pDevice, 0x18, 0x7007); + LM_ReadPhy (pDevice, 0x18, &Value32); + LM_WritePhy (pDevice, 0x18, + Value32 | BIT_15 | BIT_4); + } + } } - } - /* Turn off tap power management. */ - if((pDevice->PhyId & PHY_ID_MASK) == PHY_BCM5401_PHY_ID) - { - LM_WritePhy(pDevice, BCM5401_AUX_CTRL, 0x0c20); - LM_WritePhy(pDevice, BCM540X_DSP_ADDRESS_REG, 0x0012); - LM_WritePhy(pDevice, BCM540X_DSP_RW_PORT, 0x1804); - LM_WritePhy(pDevice, BCM540X_DSP_ADDRESS_REG, 0x0013); - LM_WritePhy(pDevice, BCM540X_DSP_RW_PORT, 0x1204); - LM_WritePhy(pDevice, BCM540X_DSP_ADDRESS_REG, 0x8006); - LM_WritePhy(pDevice, BCM540X_DSP_RW_PORT, 0x0132); - LM_WritePhy(pDevice, BCM540X_DSP_ADDRESS_REG, 0x8006); - LM_WritePhy(pDevice, BCM540X_DSP_RW_PORT, 0x0232); - LM_WritePhy(pDevice, BCM540X_DSP_ADDRESS_REG, 0x201f); - LM_WritePhy(pDevice, BCM540X_DSP_RW_PORT, 0x0a20); - - MM_Wait(40); - } + /* Turn off tap power management. */ + if ((pDevice->PhyId & PHY_ID_MASK) == PHY_BCM5401_PHY_ID) { + LM_WritePhy (pDevice, BCM5401_AUX_CTRL, 0x0c20); + LM_WritePhy (pDevice, BCM540X_DSP_ADDRESS_REG, 0x0012); + LM_WritePhy (pDevice, BCM540X_DSP_RW_PORT, 0x1804); + LM_WritePhy (pDevice, BCM540X_DSP_ADDRESS_REG, 0x0013); + LM_WritePhy (pDevice, BCM540X_DSP_RW_PORT, 0x1204); + LM_WritePhy (pDevice, BCM540X_DSP_ADDRESS_REG, 0x8006); + LM_WritePhy (pDevice, BCM540X_DSP_RW_PORT, 0x0132); + LM_WritePhy (pDevice, BCM540X_DSP_ADDRESS_REG, 0x8006); + LM_WritePhy (pDevice, BCM540X_DSP_RW_PORT, 0x0232); + LM_WritePhy (pDevice, BCM540X_DSP_ADDRESS_REG, 0x201f); + LM_WritePhy (pDevice, BCM540X_DSP_RW_PORT, 0x0a20); + MM_Wait (40); + } #if INCLUDE_TBI_SUPPORT - pDevice->IgnoreTbiLinkChange = FALSE; + pDevice->IgnoreTbiLinkChange = FALSE; - if(pDevice->EnableTbi) - { - pDevice->WakeUpModeCap = LM_WAKE_UP_MODE_NONE; - pDevice->PhyIntMode = T3_PHY_INT_MODE_LINK_READY; - if ((pDevice->PollTbiLink == BAD_DEFAULT_VALUE) || - pDevice->DisableAutoNeg) - { - pDevice->PollTbiLink = FALSE; + if (pDevice->EnableTbi) { + pDevice->WakeUpModeCap = LM_WAKE_UP_MODE_NONE; + pDevice->PhyIntMode = T3_PHY_INT_MODE_LINK_READY; + if ((pDevice->PollTbiLink == BAD_DEFAULT_VALUE) || + pDevice->DisableAutoNeg) { + pDevice->PollTbiLink = FALSE; + } + } else { + pDevice->PollTbiLink = FALSE; } - } - else - { - pDevice->PollTbiLink = FALSE; - } -#endif /* INCLUDE_TBI_SUPPORT */ +#endif /* INCLUDE_TBI_SUPPORT */ - /* UseTaggedStatus is only valid for 5701 and later. */ - if (T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700) - { - pDevice->UseTaggedStatus = FALSE; + /* UseTaggedStatus is only valid for 5701 and later. */ + if (T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5700) { + pDevice->UseTaggedStatus = FALSE; - pDevice->CoalesceMode = 0; - } - else - { - pDevice->CoalesceMode = HOST_COALESCE_CLEAR_TICKS_ON_RX_BD_EVENT | - HOST_COALESCE_CLEAR_TICKS_ON_TX_BD_EVENT; - } - - /* Set the status block size. */ - if(T3_CHIP_REV(pDevice->ChipRevId) != T3_CHIP_REV_5700_AX && - T3_CHIP_REV(pDevice->ChipRevId) != T3_CHIP_REV_5700_BX) - { - pDevice->CoalesceMode |= HOST_COALESCE_32_BYTE_STATUS_MODE; - } - - /* Check the DURING_INT coalescing ticks parameters. */ - if(pDevice->UseTaggedStatus) - { - if(pDevice->RxCoalescingTicksDuringInt == BAD_DEFAULT_VALUE) - { - pDevice->RxCoalescingTicksDuringInt = - DEFAULT_RX_COALESCING_TICKS_DURING_INT; + pDevice->CoalesceMode = 0; + } else { + pDevice->CoalesceMode = + HOST_COALESCE_CLEAR_TICKS_ON_RX_BD_EVENT | + HOST_COALESCE_CLEAR_TICKS_ON_TX_BD_EVENT; } - if(pDevice->TxCoalescingTicksDuringInt == BAD_DEFAULT_VALUE) - { - pDevice->TxCoalescingTicksDuringInt = - DEFAULT_TX_COALESCING_TICKS_DURING_INT; + /* Set the status block size. */ + if (T3_CHIP_REV (pDevice->ChipRevId) != T3_CHIP_REV_5700_AX && + T3_CHIP_REV (pDevice->ChipRevId) != T3_CHIP_REV_5700_BX) { + pDevice->CoalesceMode |= HOST_COALESCE_32_BYTE_STATUS_MODE; } - if(pDevice->RxMaxCoalescedFramesDuringInt == BAD_DEFAULT_VALUE) - { - pDevice->RxMaxCoalescedFramesDuringInt = - DEFAULT_RX_MAX_COALESCED_FRAMES_DURING_INT; - } + /* Check the DURING_INT coalescing ticks parameters. */ + if (pDevice->UseTaggedStatus) { + if (pDevice->RxCoalescingTicksDuringInt == BAD_DEFAULT_VALUE) { + pDevice->RxCoalescingTicksDuringInt = + DEFAULT_RX_COALESCING_TICKS_DURING_INT; + } - if(pDevice->TxMaxCoalescedFramesDuringInt == BAD_DEFAULT_VALUE) - { - pDevice->TxMaxCoalescedFramesDuringInt = - DEFAULT_TX_MAX_COALESCED_FRAMES_DURING_INT; - } - } - else - { - if(pDevice->RxCoalescingTicksDuringInt == BAD_DEFAULT_VALUE) - { - pDevice->RxCoalescingTicksDuringInt = 0; - } + if (pDevice->TxCoalescingTicksDuringInt == BAD_DEFAULT_VALUE) { + pDevice->TxCoalescingTicksDuringInt = + DEFAULT_TX_COALESCING_TICKS_DURING_INT; + } - if(pDevice->TxCoalescingTicksDuringInt == BAD_DEFAULT_VALUE) - { - pDevice->TxCoalescingTicksDuringInt = 0; - } + if (pDevice->RxMaxCoalescedFramesDuringInt == BAD_DEFAULT_VALUE) { + pDevice->RxMaxCoalescedFramesDuringInt = + DEFAULT_RX_MAX_COALESCED_FRAMES_DURING_INT; + } - if(pDevice->RxMaxCoalescedFramesDuringInt == BAD_DEFAULT_VALUE) - { - pDevice->RxMaxCoalescedFramesDuringInt = 0; - } + if (pDevice->TxMaxCoalescedFramesDuringInt == BAD_DEFAULT_VALUE) { + pDevice->TxMaxCoalescedFramesDuringInt = + DEFAULT_TX_MAX_COALESCED_FRAMES_DURING_INT; + } + } else { + if (pDevice->RxCoalescingTicksDuringInt == BAD_DEFAULT_VALUE) { + pDevice->RxCoalescingTicksDuringInt = 0; + } - if(pDevice->TxMaxCoalescedFramesDuringInt == BAD_DEFAULT_VALUE) - { - pDevice->TxMaxCoalescedFramesDuringInt = 0; + if (pDevice->TxCoalescingTicksDuringInt == BAD_DEFAULT_VALUE) { + pDevice->TxCoalescingTicksDuringInt = 0; + } + + if (pDevice->RxMaxCoalescedFramesDuringInt == BAD_DEFAULT_VALUE) { + pDevice->RxMaxCoalescedFramesDuringInt = 0; + } + + if (pDevice->TxMaxCoalescedFramesDuringInt == BAD_DEFAULT_VALUE) { + pDevice->TxMaxCoalescedFramesDuringInt = 0; + } } - } #if T3_JUMBO_RCV_RCB_ENTRY_COUNT - if(pDevice->RxMtu <= (MAX_STD_RCV_BUFFER_SIZE - 8 /* CRC */)) - { - pDevice->RxJumboDescCnt = 0; - if(pDevice->RxMtu <= MAX_ETHERNET_PACKET_SIZE_NO_CRC) - { - pDevice->RxMtu = MAX_ETHERNET_PACKET_SIZE_NO_CRC; - } - } - else - { - pDevice->RxJumboBufferSize = (pDevice->RxMtu + 8 /* CRC + VLAN */ + - COMMON_CACHE_LINE_SIZE-1) & ~COMMON_CACHE_LINE_MASK; + if (pDevice->RxMtu <= (MAX_STD_RCV_BUFFER_SIZE - 8 /* CRC */ )) { + pDevice->RxJumboDescCnt = 0; + if (pDevice->RxMtu <= MAX_ETHERNET_PACKET_SIZE_NO_CRC) { + pDevice->RxMtu = MAX_ETHERNET_PACKET_SIZE_NO_CRC; + } + } else { + pDevice->RxJumboBufferSize = + (pDevice->RxMtu + 8 /* CRC + VLAN */ + + COMMON_CACHE_LINE_SIZE - 1) & ~COMMON_CACHE_LINE_MASK; - if(pDevice->RxJumboBufferSize > MAX_JUMBO_RCV_BUFFER_SIZE) - { - pDevice->RxJumboBufferSize = DEFAULT_JUMBO_RCV_BUFFER_SIZE; - pDevice->RxMtu = pDevice->RxJumboBufferSize - 8 /* CRC + VLAN */; - } - pDevice->TxMtu = pDevice->RxMtu; + if (pDevice->RxJumboBufferSize > MAX_JUMBO_RCV_BUFFER_SIZE) { + pDevice->RxJumboBufferSize = + DEFAULT_JUMBO_RCV_BUFFER_SIZE; + pDevice->RxMtu = + pDevice->RxJumboBufferSize - 8 /* CRC + VLAN */ ; + } + pDevice->TxMtu = pDevice->RxMtu; - } + } #else - pDevice->RxMtu = MAX_ETHERNET_PACKET_SIZE_NO_CRC; -#endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */ + pDevice->RxMtu = MAX_ETHERNET_PACKET_SIZE_NO_CRC; +#endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */ - pDevice->RxPacketDescCnt = + pDevice->RxPacketDescCnt = #if T3_JUMBO_RCV_RCB_ENTRY_COUNT - pDevice->RxJumboDescCnt + -#endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */ - pDevice->RxStdDescCnt; + pDevice->RxJumboDescCnt + +#endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */ + pDevice->RxStdDescCnt; - if(pDevice->TxMtu < MAX_ETHERNET_PACKET_SIZE_NO_CRC) - { - pDevice->TxMtu = MAX_ETHERNET_PACKET_SIZE_NO_CRC; - } - - if(pDevice->TxMtu > MAX_JUMBO_TX_BUFFER_SIZE) - { - pDevice->TxMtu = MAX_JUMBO_TX_BUFFER_SIZE; - } - - /* Configure the proper ways to get link change interrupt. */ - if(pDevice->PhyIntMode == T3_PHY_INT_MODE_AUTO) - { - if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700) - { - pDevice->PhyIntMode = T3_PHY_INT_MODE_MI_INTERRUPT; + if (pDevice->TxMtu < MAX_ETHERNET_PACKET_SIZE_NO_CRC) { + pDevice->TxMtu = MAX_ETHERNET_PACKET_SIZE_NO_CRC; } - else - { - pDevice->PhyIntMode = T3_PHY_INT_MODE_LINK_READY; - } - } - else if(pDevice->PhyIntMode == T3_PHY_INT_MODE_AUTO_POLLING) - { - /* Auto-polling does not work on 5700_AX and 5700_BX. */ - if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700) - { - pDevice->PhyIntMode = T3_PHY_INT_MODE_MI_INTERRUPT; - } - } - /* Determine the method to get link change status. */ - if(pDevice->LinkChngMode == T3_LINK_CHNG_MODE_AUTO) - { - /* The link status bit in the status block does not work on 5700_AX */ - /* and 5700_BX chips. */ - if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700) - { - pDevice->LinkChngMode = T3_LINK_CHNG_MODE_USE_STATUS_REG; + if (pDevice->TxMtu > MAX_JUMBO_TX_BUFFER_SIZE) { + pDevice->TxMtu = MAX_JUMBO_TX_BUFFER_SIZE; } - else - { - pDevice->LinkChngMode = T3_LINK_CHNG_MODE_USE_STATUS_BLOCK; - } - } - if(pDevice->PhyIntMode == T3_PHY_INT_MODE_MI_INTERRUPT || - T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700) - { - pDevice->LinkChngMode = T3_LINK_CHNG_MODE_USE_STATUS_REG; - } - - /* Configure PHY led mode. */ - if(pDevice->LedMode == LED_MODE_AUTO) - { - if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700 || - T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5701) - { - if(pDevice->SubsystemVendorId == T3_SVID_DELL) - { - pDevice->LedMode = LED_MODE_LINK10; - } - else - { - pDevice->LedMode = LED_MODE_THREE_LINK; - - if(EeSigFound && EePhyLedMode != LED_MODE_AUTO) - { - pDevice->LedMode = EePhyLedMode; + /* Configure the proper ways to get link change interrupt. */ + if (pDevice->PhyIntMode == T3_PHY_INT_MODE_AUTO) { + if (T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5700) { + pDevice->PhyIntMode = T3_PHY_INT_MODE_MI_INTERRUPT; + } else { + pDevice->PhyIntMode = T3_PHY_INT_MODE_LINK_READY; } - } + } else if (pDevice->PhyIntMode == T3_PHY_INT_MODE_AUTO_POLLING) { + /* Auto-polling does not work on 5700_AX and 5700_BX. */ + if (T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5700) { + pDevice->PhyIntMode = T3_PHY_INT_MODE_MI_INTERRUPT; + } + } - /* bug? 5701 in LINK10 mode does not seem to work when */ - /* PhyIntMode is LINK_READY. */ - if(T3_ASIC_REV(pDevice->ChipRevId) != T3_ASIC_REV_5700 && -#if INCLUDE_TBI_SUPPORT - pDevice->EnableTbi == FALSE && -#endif - pDevice->LedMode == LED_MODE_LINK10) - { - pDevice->PhyIntMode = T3_PHY_INT_MODE_MI_INTERRUPT; + /* Determine the method to get link change status. */ + if (pDevice->LinkChngMode == T3_LINK_CHNG_MODE_AUTO) { + /* The link status bit in the status block does not work on 5700_AX */ + /* and 5700_BX chips. */ + if (T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5700) { + pDevice->LinkChngMode = + T3_LINK_CHNG_MODE_USE_STATUS_REG; + } else { + pDevice->LinkChngMode = + T3_LINK_CHNG_MODE_USE_STATUS_BLOCK; + } + } + + if (pDevice->PhyIntMode == T3_PHY_INT_MODE_MI_INTERRUPT || + T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5700) { pDevice->LinkChngMode = T3_LINK_CHNG_MODE_USE_STATUS_REG; - } - - if(pDevice->EnableTbi) - { - pDevice->LedMode = LED_MODE_THREE_LINK; - } } - else - { - if(EeSigFound && EePhyLedMode != LED_MODE_AUTO) - { - pDevice->LedMode = EePhyLedMode; - } - else - { - pDevice->LedMode = LED_MODE_OPEN_DRAIN; - } + + /* Configure PHY led mode. */ + if (pDevice->LedMode == LED_MODE_AUTO) { + if (T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5700 || + T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5701) { + if (pDevice->SubsystemVendorId == T3_SVID_DELL) { + pDevice->LedMode = LED_MODE_LINK10; + } else { + pDevice->LedMode = LED_MODE_THREE_LINK; + + if (EeSigFound && EePhyLedMode != LED_MODE_AUTO) { + pDevice->LedMode = EePhyLedMode; + } + } + + /* bug? 5701 in LINK10 mode does not seem to work when */ + /* PhyIntMode is LINK_READY. */ + if (T3_ASIC_REV (pDevice->ChipRevId) != T3_ASIC_REV_5700 + && +#if INCLUDE_TBI_SUPPORT + pDevice->EnableTbi == FALSE && +#endif + pDevice->LedMode == LED_MODE_LINK10) { + pDevice->PhyIntMode = + T3_PHY_INT_MODE_MI_INTERRUPT; + pDevice->LinkChngMode = + T3_LINK_CHNG_MODE_USE_STATUS_REG; + } + + if (pDevice->EnableTbi) { + pDevice->LedMode = LED_MODE_THREE_LINK; + } + } else { + if (EeSigFound && EePhyLedMode != LED_MODE_AUTO) { + pDevice->LedMode = EePhyLedMode; + } else { + pDevice->LedMode = LED_MODE_OPEN_DRAIN; + } + } } - } - /* Enable OneDmaAtOnce. */ - if(pDevice->OneDmaAtOnce == BAD_DEFAULT_VALUE) - { - pDevice->OneDmaAtOnce = FALSE; - } + /* Enable OneDmaAtOnce. */ + if (pDevice->OneDmaAtOnce == BAD_DEFAULT_VALUE) { + pDevice->OneDmaAtOnce = FALSE; + } - if (T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700 || - pDevice->ChipRevId == T3_CHIP_ID_5701_A0 || - pDevice->ChipRevId == T3_CHIP_ID_5701_B0 || - pDevice->ChipRevId == T3_CHIP_ID_5701_B2) - { - pDevice->WolSpeed = WOL_SPEED_10MB; - } - else - { - pDevice->WolSpeed = WOL_SPEED_100MB; - } + if (T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5700 || + pDevice->ChipRevId == T3_CHIP_ID_5701_A0 || + pDevice->ChipRevId == T3_CHIP_ID_5701_B0 || + pDevice->ChipRevId == T3_CHIP_ID_5701_B2) { + pDevice->WolSpeed = WOL_SPEED_10MB; + } else { + pDevice->WolSpeed = WOL_SPEED_100MB; + } - /* Offloadings. */ - pDevice->TaskToOffload = LM_TASK_OFFLOAD_NONE; + /* Offloadings. */ + pDevice->TaskToOffload = LM_TASK_OFFLOAD_NONE; - /* Turn off task offloading on Ax. */ - if(pDevice->ChipRevId == T3_CHIP_ID_5700_B0) - { - pDevice->TaskOffloadCap &= ~(LM_TASK_OFFLOAD_TX_TCP_CHECKSUM | - LM_TASK_OFFLOAD_TX_UDP_CHECKSUM); - } - pDevice->PciState = REG_RD(pDevice, PciCfg.PciState); - LM_ReadVPD(pDevice); - LM_ReadBootCodeVersion(pDevice); - LM_GetBusSpeed(pDevice); + /* Turn off task offloading on Ax. */ + if (pDevice->ChipRevId == T3_CHIP_ID_5700_B0) { + pDevice->TaskOffloadCap &= ~(LM_TASK_OFFLOAD_TX_TCP_CHECKSUM | + LM_TASK_OFFLOAD_TX_UDP_CHECKSUM); + } + pDevice->PciState = REG_RD (pDevice, PciCfg.PciState); + LM_ReadVPD (pDevice); + LM_ReadBootCodeVersion (pDevice); + LM_GetBusSpeed (pDevice); - return LM_STATUS_SUCCESS; -} /* LM_GetAdapterInfo */ + return LM_STATUS_SUCCESS; +} /* LM_GetAdapterInfo */ -STATIC PLM_ADAPTER_INFO -LM_GetAdapterInfoBySsid( - LM_UINT16 Svid, - LM_UINT16 Ssid) +STATIC PLM_ADAPTER_INFO LM_GetAdapterInfoBySsid (LM_UINT16 Svid, LM_UINT16 Ssid) { - static LM_ADAPTER_INFO AdapterArr[] = - { - { T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95700A6, PHY_BCM5401_PHY_ID, 0}, - { T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95701A5, PHY_BCM5701_PHY_ID, 0}, - { T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95700T6, PHY_BCM8002_PHY_ID, 1}, - { T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95700A9, 0, 1 }, - { T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95701T1, PHY_BCM5701_PHY_ID, 0}, - { T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95701T8, PHY_BCM5701_PHY_ID, 0}, - { T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95701A7, 0, 1}, - { T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95701A10, PHY_BCM5701_PHY_ID, 0}, - { T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95701A12, PHY_BCM5701_PHY_ID, 0}, - { T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95703Ax1, PHY_BCM5701_PHY_ID, 0}, - { T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95703Ax2, PHY_BCM5701_PHY_ID, 0}, + static LM_ADAPTER_INFO AdapterArr[] = { + {T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95700A6, + PHY_BCM5401_PHY_ID, 0}, + {T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95701A5, + PHY_BCM5701_PHY_ID, 0}, + {T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95700T6, + PHY_BCM8002_PHY_ID, 1}, + {T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95700A9, 0, 1}, + {T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95701T1, + PHY_BCM5701_PHY_ID, 0}, + {T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95701T8, + PHY_BCM5701_PHY_ID, 0}, + {T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95701A7, 0, 1}, + {T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95701A10, + PHY_BCM5701_PHY_ID, 0}, + {T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95701A12, + PHY_BCM5701_PHY_ID, 0}, + {T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95703Ax1, + PHY_BCM5701_PHY_ID, 0}, + {T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95703Ax2, + PHY_BCM5701_PHY_ID, 0}, - { T3_SVID_3COM, T3_SSID_3COM_3C996T, PHY_BCM5401_PHY_ID, 0 }, - { T3_SVID_3COM, T3_SSID_3COM_3C996BT, PHY_BCM5701_PHY_ID, 0 }, - { T3_SVID_3COM, T3_SSID_3COM_3C996SX, 0, 1 }, - { T3_SVID_3COM, T3_SSID_3COM_3C1000T, PHY_BCM5701_PHY_ID, 0 }, - { T3_SVID_3COM, T3_SSID_3COM_3C940BR01, PHY_BCM5701_PHY_ID, 0 }, + {T3_SVID_3COM, T3_SSID_3COM_3C996T, PHY_BCM5401_PHY_ID, 0}, + {T3_SVID_3COM, T3_SSID_3COM_3C996BT, PHY_BCM5701_PHY_ID, 0}, + {T3_SVID_3COM, T3_SSID_3COM_3C996SX, 0, 1}, + {T3_SVID_3COM, T3_SSID_3COM_3C1000T, PHY_BCM5701_PHY_ID, 0}, + {T3_SVID_3COM, T3_SSID_3COM_3C940BR01, PHY_BCM5701_PHY_ID, 0}, - { T3_SVID_DELL, T3_SSID_DELL_VIPER, PHY_BCM5401_PHY_ID, 0 }, - { T3_SVID_DELL, T3_SSID_DELL_JAGUAR, PHY_BCM5401_PHY_ID, 0 }, - { T3_SVID_DELL, T3_SSID_DELL_MERLOT, PHY_BCM5411_PHY_ID, 0 }, - { T3_SVID_DELL, T3_SSID_DELL_SLIM_MERLOT, PHY_BCM5411_PHY_ID, 0 }, + {T3_SVID_DELL, T3_SSID_DELL_VIPER, PHY_BCM5401_PHY_ID, 0}, + {T3_SVID_DELL, T3_SSID_DELL_JAGUAR, PHY_BCM5401_PHY_ID, 0}, + {T3_SVID_DELL, T3_SSID_DELL_MERLOT, PHY_BCM5411_PHY_ID, 0}, + {T3_SVID_DELL, T3_SSID_DELL_SLIM_MERLOT, PHY_BCM5411_PHY_ID, 0}, - { T3_SVID_COMPAQ, T3_SSID_COMPAQ_BANSHEE, PHY_BCM5701_PHY_ID, 0 }, - { T3_SVID_COMPAQ, T3_SSID_COMPAQ_BANSHEE_2, PHY_BCM5701_PHY_ID, 0 }, - { T3_SVID_COMPAQ, T3_SSID_COMPAQ_CHANGELING, 0, 1 }, - { T3_SVID_COMPAQ, T3_SSID_COMPAQ_NC7780, PHY_BCM5701_PHY_ID, 0 }, - { T3_SVID_COMPAQ, T3_SSID_COMPAQ_NC7780_2, PHY_BCM5701_PHY_ID, 0 }, + {T3_SVID_COMPAQ, T3_SSID_COMPAQ_BANSHEE, PHY_BCM5701_PHY_ID, 0}, + {T3_SVID_COMPAQ, T3_SSID_COMPAQ_BANSHEE_2, PHY_BCM5701_PHY_ID, + 0}, + {T3_SVID_COMPAQ, T3_SSID_COMPAQ_CHANGELING, 0, 1}, + {T3_SVID_COMPAQ, T3_SSID_COMPAQ_NC7780, PHY_BCM5701_PHY_ID, 0}, + {T3_SVID_COMPAQ, T3_SSID_COMPAQ_NC7780_2, PHY_BCM5701_PHY_ID, + 0}, - }; - LM_UINT32 j; + }; + LM_UINT32 j; - for(j = 0; j < sizeof(AdapterArr)/sizeof(LM_ADAPTER_INFO); j++) - { - if(AdapterArr[j].Svid == Svid && AdapterArr[j].Ssid == Ssid) - { - return &AdapterArr[j]; + for (j = 0; j < sizeof (AdapterArr) / sizeof (LM_ADAPTER_INFO); j++) { + if (AdapterArr[j].Svid == Svid && AdapterArr[j].Ssid == Ssid) { + return &AdapterArr[j]; + } } - } - return NULL; + return NULL; } - /******************************************************************************/ /* Description: */ /* This routine sets up receive/transmit buffer descriptions queues. */ @@ -1638,237 +1489,226 @@ LM_GetAdapterInfoBySsid( /* Return: */ /* LM_STATUS_SUCCESS */ /******************************************************************************/ -LM_STATUS -LM_InitializeAdapter( -PLM_DEVICE_BLOCK pDevice) +LM_STATUS LM_InitializeAdapter (PLM_DEVICE_BLOCK pDevice) { - LM_PHYSICAL_ADDRESS MemPhy; - PLM_UINT8 pMemVirt; - PLM_PACKET pPacket; - LM_STATUS Status; - LM_UINT32 Size; - LM_UINT32 j; + LM_PHYSICAL_ADDRESS MemPhy; + PLM_UINT8 pMemVirt; + PLM_PACKET pPacket; + LM_STATUS Status; + LM_UINT32 Size; + LM_UINT32 j; - /* Set power state to D0. */ - LM_SetPowerState(pDevice, LM_POWER_STATE_D0); + /* Set power state to D0. */ + LM_SetPowerState (pDevice, LM_POWER_STATE_D0); - /* Intialize the queues. */ - QQ_InitQueue(&pDevice->RxPacketReceivedQ.Container, - MAX_RX_PACKET_DESC_COUNT); - QQ_InitQueue(&pDevice->RxPacketFreeQ.Container, - MAX_RX_PACKET_DESC_COUNT); + /* Intialize the queues. */ + QQ_InitQueue (&pDevice->RxPacketReceivedQ.Container, + MAX_RX_PACKET_DESC_COUNT); + QQ_InitQueue (&pDevice->RxPacketFreeQ.Container, + MAX_RX_PACKET_DESC_COUNT); - QQ_InitQueue(&pDevice->TxPacketFreeQ.Container,MAX_TX_PACKET_DESC_COUNT); - QQ_InitQueue(&pDevice->TxPacketActiveQ.Container,MAX_TX_PACKET_DESC_COUNT); - QQ_InitQueue(&pDevice->TxPacketXmittedQ.Container,MAX_TX_PACKET_DESC_COUNT); + QQ_InitQueue (&pDevice->TxPacketFreeQ.Container, + MAX_TX_PACKET_DESC_COUNT); + QQ_InitQueue (&pDevice->TxPacketActiveQ.Container, + MAX_TX_PACKET_DESC_COUNT); + QQ_InitQueue (&pDevice->TxPacketXmittedQ.Container, + MAX_TX_PACKET_DESC_COUNT); - /* Allocate shared memory for: status block, the buffers for receive */ - /* rings -- standard, mini, jumbo, and return rings. */ - Size = T3_STATUS_BLOCK_SIZE + sizeof(T3_STATS_BLOCK) + - T3_STD_RCV_RCB_ENTRY_COUNT * sizeof(T3_RCV_BD) + + /* Allocate shared memory for: status block, the buffers for receive */ + /* rings -- standard, mini, jumbo, and return rings. */ + Size = T3_STATUS_BLOCK_SIZE + sizeof (T3_STATS_BLOCK) + + T3_STD_RCV_RCB_ENTRY_COUNT * sizeof (T3_RCV_BD) + #if T3_JUMBO_RCV_RCB_ENTRY_COUNT - T3_JUMBO_RCV_RCB_ENTRY_COUNT * sizeof(T3_RCV_BD) + -#endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */ - T3_RCV_RETURN_RCB_ENTRY_COUNT * sizeof(T3_RCV_BD); + T3_JUMBO_RCV_RCB_ENTRY_COUNT * sizeof (T3_RCV_BD) + +#endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */ + T3_RCV_RETURN_RCB_ENTRY_COUNT * sizeof (T3_RCV_BD); - /* Memory for host based Send BD. */ - if(pDevice->NicSendBd == FALSE) - { - Size += sizeof(T3_SND_BD) * T3_SEND_RCB_ENTRY_COUNT; - } - - /* Allocate the memory block. */ - Status = MM_AllocateSharedMemory(pDevice, Size, (PLM_VOID) &pMemVirt, &MemPhy, FALSE); - if(Status != LM_STATUS_SUCCESS) - { - return Status; - } - - /* Program DMA Read/Write */ - if (pDevice->PciState & T3_PCI_STATE_NOT_PCI_X_BUS) - { - pDevice->DmaReadWriteCtrl = 0x763f000f; - } - else - { - if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5704) - { - pDevice->DmaReadWriteCtrl = 0x761f0000; + /* Memory for host based Send BD. */ + if (pDevice->NicSendBd == FALSE) { + Size += sizeof (T3_SND_BD) * T3_SEND_RCB_ENTRY_COUNT; } - else - { - pDevice->DmaReadWriteCtrl = 0x761b000f; + + /* Allocate the memory block. */ + Status = + MM_AllocateSharedMemory (pDevice, Size, (PLM_VOID) & pMemVirt, + &MemPhy, FALSE); + if (Status != LM_STATUS_SUCCESS) { + return Status; } - if(pDevice->ChipRevId == T3_CHIP_ID_5703_A1 || - pDevice->ChipRevId == T3_CHIP_ID_5703_A2) - { - pDevice->OneDmaAtOnce = TRUE; + + /* Program DMA Read/Write */ + if (pDevice->PciState & T3_PCI_STATE_NOT_PCI_X_BUS) { + pDevice->DmaReadWriteCtrl = 0x763f000f; + } else { + if (T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5704) { + pDevice->DmaReadWriteCtrl = 0x761f0000; + } else { + pDevice->DmaReadWriteCtrl = 0x761b000f; + } + if (pDevice->ChipRevId == T3_CHIP_ID_5703_A1 || + pDevice->ChipRevId == T3_CHIP_ID_5703_A2) { + pDevice->OneDmaAtOnce = TRUE; + } + } + if (T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5703) { + pDevice->DmaReadWriteCtrl &= 0xfffffff0; } - } - if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5703) - { - pDevice->DmaReadWriteCtrl &= 0xfffffff0; - } - if(pDevice->OneDmaAtOnce) - { - pDevice->DmaReadWriteCtrl |= DMA_CTRL_WRITE_ONE_DMA_AT_ONCE; - } - REG_WR(pDevice, PciCfg.DmaReadWriteCtrl, pDevice->DmaReadWriteCtrl); + if (pDevice->OneDmaAtOnce) { + pDevice->DmaReadWriteCtrl |= DMA_CTRL_WRITE_ONE_DMA_AT_ONCE; + } + REG_WR (pDevice, PciCfg.DmaReadWriteCtrl, pDevice->DmaReadWriteCtrl); - if (LM_DmaTest(pDevice, pMemVirt, MemPhy, 0x400) != LM_STATUS_SUCCESS) - { - return LM_STATUS_FAILURE; - } + if (LM_DmaTest (pDevice, pMemVirt, MemPhy, 0x400) != LM_STATUS_SUCCESS) { + return LM_STATUS_FAILURE; + } - /* Status block. */ - pDevice->pStatusBlkVirt = (PT3_STATUS_BLOCK) pMemVirt; - pDevice->StatusBlkPhy = MemPhy; - pMemVirt += T3_STATUS_BLOCK_SIZE; - LM_INC_PHYSICAL_ADDRESS(&MemPhy, T3_STATUS_BLOCK_SIZE); + /* Status block. */ + pDevice->pStatusBlkVirt = (PT3_STATUS_BLOCK) pMemVirt; + pDevice->StatusBlkPhy = MemPhy; + pMemVirt += T3_STATUS_BLOCK_SIZE; + LM_INC_PHYSICAL_ADDRESS (&MemPhy, T3_STATUS_BLOCK_SIZE); - /* Statistics block. */ - pDevice->pStatsBlkVirt = (PT3_STATS_BLOCK) pMemVirt; - pDevice->StatsBlkPhy = MemPhy; - pMemVirt += sizeof(T3_STATS_BLOCK); - LM_INC_PHYSICAL_ADDRESS(&MemPhy, sizeof(T3_STATS_BLOCK)); + /* Statistics block. */ + pDevice->pStatsBlkVirt = (PT3_STATS_BLOCK) pMemVirt; + pDevice->StatsBlkPhy = MemPhy; + pMemVirt += sizeof (T3_STATS_BLOCK); + LM_INC_PHYSICAL_ADDRESS (&MemPhy, sizeof (T3_STATS_BLOCK)); - /* Receive standard BD buffer. */ - pDevice->pRxStdBdVirt = (PT3_RCV_BD) pMemVirt; - pDevice->RxStdBdPhy = MemPhy; + /* Receive standard BD buffer. */ + pDevice->pRxStdBdVirt = (PT3_RCV_BD) pMemVirt; + pDevice->RxStdBdPhy = MemPhy; - pMemVirt += T3_STD_RCV_RCB_ENTRY_COUNT * sizeof(T3_RCV_BD); - LM_INC_PHYSICAL_ADDRESS(&MemPhy, - T3_STD_RCV_RCB_ENTRY_COUNT * sizeof(T3_RCV_BD)); + pMemVirt += T3_STD_RCV_RCB_ENTRY_COUNT * sizeof (T3_RCV_BD); + LM_INC_PHYSICAL_ADDRESS (&MemPhy, + T3_STD_RCV_RCB_ENTRY_COUNT * + sizeof (T3_RCV_BD)); #if T3_JUMBO_RCV_RCB_ENTRY_COUNT - /* Receive jumbo BD buffer. */ - pDevice->pRxJumboBdVirt = (PT3_RCV_BD) pMemVirt; - pDevice->RxJumboBdPhy = MemPhy; + /* Receive jumbo BD buffer. */ + pDevice->pRxJumboBdVirt = (PT3_RCV_BD) pMemVirt; + pDevice->RxJumboBdPhy = MemPhy; - pMemVirt += T3_JUMBO_RCV_RCB_ENTRY_COUNT * sizeof(T3_RCV_BD); - LM_INC_PHYSICAL_ADDRESS(&MemPhy, - T3_JUMBO_RCV_RCB_ENTRY_COUNT * sizeof(T3_RCV_BD)); -#endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */ + pMemVirt += T3_JUMBO_RCV_RCB_ENTRY_COUNT * sizeof (T3_RCV_BD); + LM_INC_PHYSICAL_ADDRESS (&MemPhy, + T3_JUMBO_RCV_RCB_ENTRY_COUNT * + sizeof (T3_RCV_BD)); +#endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */ - /* Receive return BD buffer. */ - pDevice->pRcvRetBdVirt = (PT3_RCV_BD) pMemVirt; - pDevice->RcvRetBdPhy = MemPhy; + /* Receive return BD buffer. */ + pDevice->pRcvRetBdVirt = (PT3_RCV_BD) pMemVirt; + pDevice->RcvRetBdPhy = MemPhy; - pMemVirt += T3_RCV_RETURN_RCB_ENTRY_COUNT * sizeof(T3_RCV_BD); - LM_INC_PHYSICAL_ADDRESS(&MemPhy, - T3_RCV_RETURN_RCB_ENTRY_COUNT * sizeof(T3_RCV_BD)); + pMemVirt += T3_RCV_RETURN_RCB_ENTRY_COUNT * sizeof (T3_RCV_BD); + LM_INC_PHYSICAL_ADDRESS (&MemPhy, + T3_RCV_RETURN_RCB_ENTRY_COUNT * + sizeof (T3_RCV_BD)); - /* Set up Send BD. */ - if(pDevice->NicSendBd == FALSE) - { - pDevice->pSendBdVirt = (PT3_SND_BD) pMemVirt; - pDevice->SendBdPhy = MemPhy; + /* Set up Send BD. */ + if (pDevice->NicSendBd == FALSE) { + pDevice->pSendBdVirt = (PT3_SND_BD) pMemVirt; + pDevice->SendBdPhy = MemPhy; - pMemVirt += sizeof(T3_SND_BD) * T3_SEND_RCB_ENTRY_COUNT; - LM_INC_PHYSICAL_ADDRESS(&MemPhy, - sizeof(T3_SND_BD) * T3_SEND_RCB_ENTRY_COUNT); - } - else - { - pDevice->pSendBdVirt = (PT3_SND_BD) - pDevice->pMemView->uIntMem.First32k.BufferDesc; - pDevice->SendBdPhy.High = 0; - pDevice->SendBdPhy.Low = T3_NIC_SND_BUFFER_DESC_ADDR; - } + pMemVirt += sizeof (T3_SND_BD) * T3_SEND_RCB_ENTRY_COUNT; + LM_INC_PHYSICAL_ADDRESS (&MemPhy, + sizeof (T3_SND_BD) * + T3_SEND_RCB_ENTRY_COUNT); + } else { + pDevice->pSendBdVirt = (PT3_SND_BD) + pDevice->pMemView->uIntMem.First32k.BufferDesc; + pDevice->SendBdPhy.High = 0; + pDevice->SendBdPhy.Low = T3_NIC_SND_BUFFER_DESC_ADDR; + } - /* Allocate memory for packet descriptors. */ - Size = (pDevice->RxPacketDescCnt + - pDevice->TxPacketDescCnt) * MM_PACKET_DESC_SIZE; - Status = MM_AllocateMemory(pDevice, Size, (PLM_VOID *) &pPacket); - if(Status != LM_STATUS_SUCCESS) - { - return Status; - } - pDevice->pPacketDescBase = (PLM_VOID) pPacket; + /* Allocate memory for packet descriptors. */ + Size = (pDevice->RxPacketDescCnt + + pDevice->TxPacketDescCnt) * MM_PACKET_DESC_SIZE; + Status = MM_AllocateMemory (pDevice, Size, (PLM_VOID *) & pPacket); + if (Status != LM_STATUS_SUCCESS) { + return Status; + } + pDevice->pPacketDescBase = (PLM_VOID) pPacket; - /* Create transmit packet descriptors from the memory block and add them */ - /* to the TxPacketFreeQ for each send ring. */ - for(j = 0; j < pDevice->TxPacketDescCnt; j++) - { - /* Ring index. */ - pPacket->Flags = 0; + /* Create transmit packet descriptors from the memory block and add them */ + /* to the TxPacketFreeQ for each send ring. */ + for (j = 0; j < pDevice->TxPacketDescCnt; j++) { + /* Ring index. */ + pPacket->Flags = 0; - /* Queue the descriptor in the TxPacketFreeQ of the 'k' ring. */ - QQ_PushTail(&pDevice->TxPacketFreeQ.Container, pPacket); + /* Queue the descriptor in the TxPacketFreeQ of the 'k' ring. */ + QQ_PushTail (&pDevice->TxPacketFreeQ.Container, pPacket); - /* Get the pointer to the next descriptor. MM_PACKET_DESC_SIZE */ - /* is the total size of the packet descriptor including the */ - /* os-specific extensions in the UM_PACKET structure. */ - pPacket = (PLM_PACKET) ((PLM_UINT8) pPacket + MM_PACKET_DESC_SIZE); - } /* for(j.. */ + /* Get the pointer to the next descriptor. MM_PACKET_DESC_SIZE */ + /* is the total size of the packet descriptor including the */ + /* os-specific extensions in the UM_PACKET structure. */ + pPacket = + (PLM_PACKET) ((PLM_UINT8) pPacket + MM_PACKET_DESC_SIZE); + } /* for(j.. */ - /* Create receive packet descriptors from the memory block and add them */ - /* to the RxPacketFreeQ. Create the Standard packet descriptors. */ - for(j = 0; j < pDevice->RxStdDescCnt; j++) - { - /* Receive producer ring. */ - pPacket->u.Rx.RcvProdRing = T3_STD_RCV_PROD_RING; + /* Create receive packet descriptors from the memory block and add them */ + /* to the RxPacketFreeQ. Create the Standard packet descriptors. */ + for (j = 0; j < pDevice->RxStdDescCnt; j++) { + /* Receive producer ring. */ + pPacket->u.Rx.RcvProdRing = T3_STD_RCV_PROD_RING; - /* Receive buffer size. */ - pPacket->u.Rx.RxBufferSize = MAX_STD_RCV_BUFFER_SIZE; + /* Receive buffer size. */ + pPacket->u.Rx.RxBufferSize = MAX_STD_RCV_BUFFER_SIZE; - /* Add the descriptor to RxPacketFreeQ. */ - QQ_PushTail(&pDevice->RxPacketFreeQ.Container, pPacket); + /* Add the descriptor to RxPacketFreeQ. */ + QQ_PushTail (&pDevice->RxPacketFreeQ.Container, pPacket); - /* Get the pointer to the next descriptor. MM_PACKET_DESC_SIZE */ - /* is the total size of the packet descriptor including the */ - /* os-specific extensions in the UM_PACKET structure. */ - pPacket = (PLM_PACKET) ((PLM_UINT8) pPacket + MM_PACKET_DESC_SIZE); - } /* for */ + /* Get the pointer to the next descriptor. MM_PACKET_DESC_SIZE */ + /* is the total size of the packet descriptor including the */ + /* os-specific extensions in the UM_PACKET structure. */ + pPacket = + (PLM_PACKET) ((PLM_UINT8) pPacket + MM_PACKET_DESC_SIZE); + } /* for */ #if T3_JUMBO_RCV_RCB_ENTRY_COUNT - /* Create the Jumbo packet descriptors. */ - for(j = 0; j < pDevice->RxJumboDescCnt; j++) - { - /* Receive producer ring. */ - pPacket->u.Rx.RcvProdRing = T3_JUMBO_RCV_PROD_RING; + /* Create the Jumbo packet descriptors. */ + for (j = 0; j < pDevice->RxJumboDescCnt; j++) { + /* Receive producer ring. */ + pPacket->u.Rx.RcvProdRing = T3_JUMBO_RCV_PROD_RING; - /* Receive buffer size. */ - pPacket->u.Rx.RxBufferSize = pDevice->RxJumboBufferSize; + /* Receive buffer size. */ + pPacket->u.Rx.RxBufferSize = pDevice->RxJumboBufferSize; - /* Add the descriptor to RxPacketFreeQ. */ - QQ_PushTail(&pDevice->RxPacketFreeQ.Container, pPacket); + /* Add the descriptor to RxPacketFreeQ. */ + QQ_PushTail (&pDevice->RxPacketFreeQ.Container, pPacket); - /* Get the pointer to the next descriptor. MM_PACKET_DESC_SIZE */ - /* is the total size of the packet descriptor including the */ - /* os-specific extensions in the UM_PACKET structure. */ - pPacket = (PLM_PACKET) ((PLM_UINT8) pPacket + MM_PACKET_DESC_SIZE); - } /* for */ -#endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */ + /* Get the pointer to the next descriptor. MM_PACKET_DESC_SIZE */ + /* is the total size of the packet descriptor including the */ + /* os-specific extensions in the UM_PACKET structure. */ + pPacket = + (PLM_PACKET) ((PLM_UINT8) pPacket + MM_PACKET_DESC_SIZE); + } /* for */ +#endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */ - /* Initialize the rest of the packet descriptors. */ - Status = MM_InitializeUmPackets(pDevice); - if(Status != LM_STATUS_SUCCESS) - { - return Status; - } /* if */ + /* Initialize the rest of the packet descriptors. */ + Status = MM_InitializeUmPackets (pDevice); + if (Status != LM_STATUS_SUCCESS) { + return Status; + } - /* Default receive mask. */ - pDevice->ReceiveMask = LM_ACCEPT_MULTICAST | LM_ACCEPT_BROADCAST | - LM_ACCEPT_UNICAST; + /* if */ + /* Default receive mask. */ + pDevice->ReceiveMask = LM_ACCEPT_MULTICAST | LM_ACCEPT_BROADCAST | + LM_ACCEPT_UNICAST; - /* Make sure we are in the first 32k memory window or NicSendBd. */ - REG_WR(pDevice, PciCfg.MemWindowBaseAddr, 0); + /* Make sure we are in the first 32k memory window or NicSendBd. */ + REG_WR (pDevice, PciCfg.MemWindowBaseAddr, 0); - /* Initialize the hardware. */ - Status = LM_ResetAdapter(pDevice); - if(Status != LM_STATUS_SUCCESS) - { - return Status; - } + /* Initialize the hardware. */ + Status = LM_ResetAdapter (pDevice); + if (Status != LM_STATUS_SUCCESS) { + return Status; + } - /* We are done with initialization. */ - pDevice->InitDone = TRUE; - - return LM_STATUS_SUCCESS; -} /* LM_InitializeAdapter */ + /* We are done with initialization. */ + pDevice->InitDone = TRUE; + return LM_STATUS_SUCCESS; +} /* LM_InitializeAdapter */ /******************************************************************************/ /* Description: */ @@ -1878,414 +1718,408 @@ PLM_DEVICE_BLOCK pDevice) /* LM_STATUS_SUCCESS */ /******************************************************************************/ LM_STATUS -LM_CntrlBlock( -PLM_DEVICE_BLOCK pDevice, -LM_UINT32 mask,LM_UINT32 cntrl) +LM_CntrlBlock (PLM_DEVICE_BLOCK pDevice, LM_UINT32 mask, LM_UINT32 cntrl) { - LM_UINT32 j,i,data; - LM_UINT32 MaxWaitCnt; + LM_UINT32 j, i, data; + LM_UINT32 MaxWaitCnt; - MaxWaitCnt = 2; - j = 0; + MaxWaitCnt = 2; + j = 0; - for(i = 0 ; i < 32; i++) - { - if(!(mask & (1 << i))) - continue; + for (i = 0; i < 32; i++) { + if (!(mask & (1 << i))) + continue; - switch (1 << i) - { - case T3_BLOCK_DMA_RD: - data = REG_RD(pDevice, DmaRead.Mode); - if (cntrl == LM_DISABLE) - { - data &= ~DMA_READ_MODE_ENABLE; - REG_WR(pDevice, DmaRead.Mode, data); - for(j = 0; j < MaxWaitCnt; j++) - { - if(!(REG_RD(pDevice, DmaRead.Mode) & DMA_READ_MODE_ENABLE)) - break; - MM_Wait(10); - } - } - else - REG_WR(pDevice, DmaRead.Mode, data | DMA_READ_MODE_ENABLE); - break; + switch (1 << i) { + case T3_BLOCK_DMA_RD: + data = REG_RD (pDevice, DmaRead.Mode); + if (cntrl == LM_DISABLE) { + data &= ~DMA_READ_MODE_ENABLE; + REG_WR (pDevice, DmaRead.Mode, data); + for (j = 0; j < MaxWaitCnt; j++) { + if (! + (REG_RD (pDevice, DmaRead.Mode) & + DMA_READ_MODE_ENABLE)) + break; + MM_Wait (10); + } + } else + REG_WR (pDevice, DmaRead.Mode, + data | DMA_READ_MODE_ENABLE); + break; - case T3_BLOCK_DMA_COMP: - data = REG_RD(pDevice,DmaComp.Mode); - if (cntrl == LM_DISABLE) - { - data &= ~DMA_COMP_MODE_ENABLE; - REG_WR(pDevice, DmaComp.Mode, data); - for(j = 0; j < MaxWaitCnt; j++) - { - if(!(REG_RD(pDevice, DmaComp.Mode) & DMA_COMP_MODE_ENABLE)) - break; - MM_Wait(10); - } - } - else - REG_WR(pDevice, DmaComp.Mode, data | DMA_COMP_MODE_ENABLE); - break; + case T3_BLOCK_DMA_COMP: + data = REG_RD (pDevice, DmaComp.Mode); + if (cntrl == LM_DISABLE) { + data &= ~DMA_COMP_MODE_ENABLE; + REG_WR (pDevice, DmaComp.Mode, data); + for (j = 0; j < MaxWaitCnt; j++) { + if (! + (REG_RD (pDevice, DmaComp.Mode) & + DMA_COMP_MODE_ENABLE)) + break; + MM_Wait (10); + } + } else + REG_WR (pDevice, DmaComp.Mode, + data | DMA_COMP_MODE_ENABLE); + break; - case T3_BLOCK_RX_BD_INITIATOR: - data = REG_RD(pDevice, RcvBdIn.Mode); - if (cntrl == LM_DISABLE) - { - data &= ~RCV_BD_IN_MODE_ENABLE; - REG_WR(pDevice, RcvBdIn.Mode,data); - for(j = 0; j < MaxWaitCnt; j++) - { - if(!(REG_RD(pDevice, RcvBdIn.Mode) & RCV_BD_IN_MODE_ENABLE)) - break; - MM_Wait(10); - } - } - else - REG_WR(pDevice, RcvBdIn.Mode,data | RCV_BD_IN_MODE_ENABLE); - break; + case T3_BLOCK_RX_BD_INITIATOR: + data = REG_RD (pDevice, RcvBdIn.Mode); + if (cntrl == LM_DISABLE) { + data &= ~RCV_BD_IN_MODE_ENABLE; + REG_WR (pDevice, RcvBdIn.Mode, data); + for (j = 0; j < MaxWaitCnt; j++) { + if (! + (REG_RD (pDevice, RcvBdIn.Mode) & + RCV_BD_IN_MODE_ENABLE)) + break; + MM_Wait (10); + } + } else + REG_WR (pDevice, RcvBdIn.Mode, + data | RCV_BD_IN_MODE_ENABLE); + break; - case T3_BLOCK_RX_BD_COMP: - data = REG_RD(pDevice, RcvBdComp.Mode); - if (cntrl == LM_DISABLE) - { - data &= ~RCV_BD_COMP_MODE_ENABLE; - REG_WR(pDevice, RcvBdComp.Mode,data); - for(j = 0; j < MaxWaitCnt; j++) - { - if(!(REG_RD(pDevice, RcvBdComp.Mode) & RCV_BD_COMP_MODE_ENABLE)) - break; - MM_Wait(10); - } - } - else - REG_WR(pDevice, RcvBdComp.Mode,data | RCV_BD_COMP_MODE_ENABLE); - break; + case T3_BLOCK_RX_BD_COMP: + data = REG_RD (pDevice, RcvBdComp.Mode); + if (cntrl == LM_DISABLE) { + data &= ~RCV_BD_COMP_MODE_ENABLE; + REG_WR (pDevice, RcvBdComp.Mode, data); + for (j = 0; j < MaxWaitCnt; j++) { + if (! + (REG_RD (pDevice, RcvBdComp.Mode) & + RCV_BD_COMP_MODE_ENABLE)) + break; + MM_Wait (10); + } + } else + REG_WR (pDevice, RcvBdComp.Mode, + data | RCV_BD_COMP_MODE_ENABLE); + break; - case T3_BLOCK_DMA_WR: - data = REG_RD(pDevice, DmaWrite.Mode); - if (cntrl == LM_DISABLE) - { - data &= ~DMA_WRITE_MODE_ENABLE; - REG_WR(pDevice, DmaWrite.Mode,data); + case T3_BLOCK_DMA_WR: + data = REG_RD (pDevice, DmaWrite.Mode); + if (cntrl == LM_DISABLE) { + data &= ~DMA_WRITE_MODE_ENABLE; + REG_WR (pDevice, DmaWrite.Mode, data); - for(j = 0; j < MaxWaitCnt; j++) - { - if(!(REG_RD(pDevice, DmaWrite.Mode) & DMA_WRITE_MODE_ENABLE)) - break; - MM_Wait(10); - } - } - else - REG_WR(pDevice, DmaWrite.Mode,data | DMA_WRITE_MODE_ENABLE); - break; + for (j = 0; j < MaxWaitCnt; j++) { + if (! + (REG_RD (pDevice, DmaWrite.Mode) & + DMA_WRITE_MODE_ENABLE)) + break; + MM_Wait (10); + } + } else + REG_WR (pDevice, DmaWrite.Mode, + data | DMA_WRITE_MODE_ENABLE); + break; - case T3_BLOCK_MSI_HANDLER: - data = REG_RD(pDevice, Msi.Mode); - if (cntrl == LM_DISABLE) - { - data &= ~MSI_MODE_ENABLE; - REG_WR(pDevice, Msi.Mode, data); - for(j = 0; j < MaxWaitCnt; j++) - { - if(!(REG_RD(pDevice, Msi.Mode) & MSI_MODE_ENABLE)) - break; - MM_Wait(10); - } - } - else - REG_WR(pDevice, Msi.Mode, data |MSI_MODE_ENABLE); - break; + case T3_BLOCK_MSI_HANDLER: + data = REG_RD (pDevice, Msi.Mode); + if (cntrl == LM_DISABLE) { + data &= ~MSI_MODE_ENABLE; + REG_WR (pDevice, Msi.Mode, data); + for (j = 0; j < MaxWaitCnt; j++) { + if (! + (REG_RD (pDevice, Msi.Mode) & + MSI_MODE_ENABLE)) + break; + MM_Wait (10); + } + } else + REG_WR (pDevice, Msi.Mode, + data | MSI_MODE_ENABLE); + break; - case T3_BLOCK_RX_LIST_PLMT: - data = REG_RD(pDevice, RcvListPlmt.Mode); - if (cntrl == LM_DISABLE) - { - data &= ~RCV_LIST_PLMT_MODE_ENABLE; - REG_WR(pDevice, RcvListPlmt.Mode,data); - for(j = 0; j < MaxWaitCnt; j++) - { - if(!(REG_RD(pDevice, RcvListPlmt.Mode) & RCV_LIST_PLMT_MODE_ENABLE)) - break; - MM_Wait(10); - } - } - else - REG_WR(pDevice, RcvListPlmt.Mode,data | RCV_LIST_PLMT_MODE_ENABLE); - break; + case T3_BLOCK_RX_LIST_PLMT: + data = REG_RD (pDevice, RcvListPlmt.Mode); + if (cntrl == LM_DISABLE) { + data &= ~RCV_LIST_PLMT_MODE_ENABLE; + REG_WR (pDevice, RcvListPlmt.Mode, data); + for (j = 0; j < MaxWaitCnt; j++) { + if (! + (REG_RD (pDevice, RcvListPlmt.Mode) + & RCV_LIST_PLMT_MODE_ENABLE)) + break; + MM_Wait (10); + } + } else + REG_WR (pDevice, RcvListPlmt.Mode, + data | RCV_LIST_PLMT_MODE_ENABLE); + break; - case T3_BLOCK_RX_LIST_SELECTOR: - data = REG_RD(pDevice, RcvListSel.Mode); - if (cntrl == LM_DISABLE) - { - data &= ~RCV_LIST_SEL_MODE_ENABLE; - REG_WR(pDevice, RcvListSel.Mode,data); - for(j = 0; j < MaxWaitCnt; j++) - { - if(!(REG_RD(pDevice, RcvListSel.Mode) & RCV_LIST_SEL_MODE_ENABLE)) - break; - MM_Wait(10); - } - } - else - REG_WR(pDevice, RcvListSel.Mode,data |RCV_LIST_SEL_MODE_ENABLE); - break; + case T3_BLOCK_RX_LIST_SELECTOR: + data = REG_RD (pDevice, RcvListSel.Mode); + if (cntrl == LM_DISABLE) { + data &= ~RCV_LIST_SEL_MODE_ENABLE; + REG_WR (pDevice, RcvListSel.Mode, data); + for (j = 0; j < MaxWaitCnt; j++) { + if (! + (REG_RD (pDevice, RcvListSel.Mode) & + RCV_LIST_SEL_MODE_ENABLE)) + break; + MM_Wait (10); + } + } else + REG_WR (pDevice, RcvListSel.Mode, + data | RCV_LIST_SEL_MODE_ENABLE); + break; - case T3_BLOCK_RX_DATA_INITIATOR: - data = REG_RD(pDevice, RcvDataBdIn.Mode); - if (cntrl == LM_DISABLE) - { - data &= ~RCV_DATA_BD_IN_MODE_ENABLE; - REG_WR(pDevice, RcvDataBdIn.Mode,data); - for(j = 0; j < MaxWaitCnt; j++) - { - if(!(REG_RD(pDevice, RcvDataBdIn.Mode) & RCV_DATA_BD_IN_MODE_ENABLE)) - break; - MM_Wait(10); - } - } - else - REG_WR(pDevice, RcvDataBdIn.Mode, data | RCV_DATA_BD_IN_MODE_ENABLE); - break; + case T3_BLOCK_RX_DATA_INITIATOR: + data = REG_RD (pDevice, RcvDataBdIn.Mode); + if (cntrl == LM_DISABLE) { + data &= ~RCV_DATA_BD_IN_MODE_ENABLE; + REG_WR (pDevice, RcvDataBdIn.Mode, data); + for (j = 0; j < MaxWaitCnt; j++) { + if (! + (REG_RD (pDevice, RcvDataBdIn.Mode) + & RCV_DATA_BD_IN_MODE_ENABLE)) + break; + MM_Wait (10); + } + } else + REG_WR (pDevice, RcvDataBdIn.Mode, + data | RCV_DATA_BD_IN_MODE_ENABLE); + break; - case T3_BLOCK_RX_DATA_COMP: - data = REG_RD(pDevice, RcvDataComp.Mode); - if (cntrl == LM_DISABLE) - { - data &= ~RCV_DATA_COMP_MODE_ENABLE; - REG_WR(pDevice, RcvDataComp.Mode,data); - for(j = 0; j < MaxWaitCnt; j++) - { - if(!(REG_RD(pDevice, RcvDataBdIn.Mode) & RCV_DATA_COMP_MODE_ENABLE)) - break; - MM_Wait(10); - } - } - else - REG_WR(pDevice, RcvDataComp.Mode,data | RCV_DATA_COMP_MODE_ENABLE); - break; + case T3_BLOCK_RX_DATA_COMP: + data = REG_RD (pDevice, RcvDataComp.Mode); + if (cntrl == LM_DISABLE) { + data &= ~RCV_DATA_COMP_MODE_ENABLE; + REG_WR (pDevice, RcvDataComp.Mode, data); + for (j = 0; j < MaxWaitCnt; j++) { + if (! + (REG_RD (pDevice, RcvDataBdIn.Mode) + & RCV_DATA_COMP_MODE_ENABLE)) + break; + MM_Wait (10); + } + } else + REG_WR (pDevice, RcvDataComp.Mode, + data | RCV_DATA_COMP_MODE_ENABLE); + break; - case T3_BLOCK_HOST_COALESING: - data = REG_RD(pDevice, HostCoalesce.Mode); - if (cntrl == LM_DISABLE) - { - data &= ~HOST_COALESCE_ENABLE; - REG_WR(pDevice, HostCoalesce.Mode, data); - for(j = 0; j < MaxWaitCnt; j++) - { - if(!(REG_RD(pDevice, SndBdIn.Mode) & HOST_COALESCE_ENABLE)) - break; - MM_Wait(10); - } - } - else - REG_WR(pDevice, HostCoalesce.Mode, data | HOST_COALESCE_ENABLE); - break; + case T3_BLOCK_HOST_COALESING: + data = REG_RD (pDevice, HostCoalesce.Mode); + if (cntrl == LM_DISABLE) { + data &= ~HOST_COALESCE_ENABLE; + REG_WR (pDevice, HostCoalesce.Mode, data); + for (j = 0; j < MaxWaitCnt; j++) { + if (! + (REG_RD (pDevice, SndBdIn.Mode) & + HOST_COALESCE_ENABLE)) + break; + MM_Wait (10); + } + } else + REG_WR (pDevice, HostCoalesce.Mode, + data | HOST_COALESCE_ENABLE); + break; - case T3_BLOCK_MAC_RX_ENGINE: - if(cntrl == LM_DISABLE) - { - pDevice->RxMode &= ~RX_MODE_ENABLE; - REG_WR(pDevice, MacCtrl.RxMode, pDevice->RxMode); - for(j = 0; j < MaxWaitCnt; j++) - { - if(!(REG_RD(pDevice, MacCtrl.RxMode) & RX_MODE_ENABLE)) - { - break; + case T3_BLOCK_MAC_RX_ENGINE: + if (cntrl == LM_DISABLE) { + pDevice->RxMode &= ~RX_MODE_ENABLE; + REG_WR (pDevice, MacCtrl.RxMode, + pDevice->RxMode); + for (j = 0; j < MaxWaitCnt; j++) { + if (! + (REG_RD (pDevice, MacCtrl.RxMode) & + RX_MODE_ENABLE)) { + break; + } + MM_Wait (10); + } + } else { + pDevice->RxMode |= RX_MODE_ENABLE; + REG_WR (pDevice, MacCtrl.RxMode, + pDevice->RxMode); } - MM_Wait(10); - } - } - else - { - pDevice->RxMode |= RX_MODE_ENABLE; - REG_WR(pDevice, MacCtrl.RxMode, pDevice->RxMode); - } - break; + break; - case T3_BLOCK_MBUF_CLUSTER_FREE: - data = REG_RD(pDevice, MbufClusterFree.Mode); - if (cntrl == LM_DISABLE) - { - data &= ~MBUF_CLUSTER_FREE_MODE_ENABLE; - REG_WR(pDevice, MbufClusterFree.Mode,data); - for(j = 0; j < MaxWaitCnt; j++) - { - if(!(REG_RD(pDevice, MbufClusterFree.Mode) & MBUF_CLUSTER_FREE_MODE_ENABLE)) - break; - MM_Wait(10); - } - } - else - REG_WR(pDevice, MbufClusterFree.Mode, data | MBUF_CLUSTER_FREE_MODE_ENABLE); - break; + case T3_BLOCK_MBUF_CLUSTER_FREE: + data = REG_RD (pDevice, MbufClusterFree.Mode); + if (cntrl == LM_DISABLE) { + data &= ~MBUF_CLUSTER_FREE_MODE_ENABLE; + REG_WR (pDevice, MbufClusterFree.Mode, data); + for (j = 0; j < MaxWaitCnt; j++) { + if (! + (REG_RD + (pDevice, + MbufClusterFree. + Mode) & + MBUF_CLUSTER_FREE_MODE_ENABLE)) + break; + MM_Wait (10); + } + } else + REG_WR (pDevice, MbufClusterFree.Mode, + data | MBUF_CLUSTER_FREE_MODE_ENABLE); + break; - case T3_BLOCK_SEND_BD_INITIATOR: - data = REG_RD(pDevice, SndBdIn.Mode); - if (cntrl == LM_DISABLE) - { - data &= ~SND_BD_IN_MODE_ENABLE; - REG_WR(pDevice, SndBdIn.Mode, data); - for(j = 0; j < MaxWaitCnt; j++) - { - if(!(REG_RD(pDevice, SndBdIn.Mode) & SND_BD_IN_MODE_ENABLE)) - break; - MM_Wait(10); - } - } - else - REG_WR(pDevice, SndBdIn.Mode, data | SND_BD_IN_MODE_ENABLE); - break; + case T3_BLOCK_SEND_BD_INITIATOR: + data = REG_RD (pDevice, SndBdIn.Mode); + if (cntrl == LM_DISABLE) { + data &= ~SND_BD_IN_MODE_ENABLE; + REG_WR (pDevice, SndBdIn.Mode, data); + for (j = 0; j < MaxWaitCnt; j++) { + if (! + (REG_RD (pDevice, SndBdIn.Mode) & + SND_BD_IN_MODE_ENABLE)) + break; + MM_Wait (10); + } + } else + REG_WR (pDevice, SndBdIn.Mode, + data | SND_BD_IN_MODE_ENABLE); + break; - case T3_BLOCK_SEND_BD_COMP: - data = REG_RD(pDevice, SndBdComp.Mode); - if (cntrl == LM_DISABLE) - { - data &= ~SND_BD_COMP_MODE_ENABLE; - REG_WR(pDevice, SndBdComp.Mode, data); - for(j = 0; j < MaxWaitCnt; j++) - { - if(!(REG_RD(pDevice, SndBdComp.Mode) & SND_BD_COMP_MODE_ENABLE)) - break; - MM_Wait(10); - } - } - else - REG_WR(pDevice, SndBdComp.Mode, data | SND_BD_COMP_MODE_ENABLE); - break; + case T3_BLOCK_SEND_BD_COMP: + data = REG_RD (pDevice, SndBdComp.Mode); + if (cntrl == LM_DISABLE) { + data &= ~SND_BD_COMP_MODE_ENABLE; + REG_WR (pDevice, SndBdComp.Mode, data); + for (j = 0; j < MaxWaitCnt; j++) { + if (! + (REG_RD (pDevice, SndBdComp.Mode) & + SND_BD_COMP_MODE_ENABLE)) + break; + MM_Wait (10); + } + } else + REG_WR (pDevice, SndBdComp.Mode, + data | SND_BD_COMP_MODE_ENABLE); + break; - case T3_BLOCK_SEND_BD_SELECTOR: - data = REG_RD(pDevice, SndBdSel.Mode); - if (cntrl == LM_DISABLE) - { - data &= ~SND_BD_SEL_MODE_ENABLE; - REG_WR(pDevice, SndBdSel.Mode, data); - for(j = 0; j < MaxWaitCnt; j++) - { - if(!(REG_RD(pDevice, SndBdSel.Mode) & SND_BD_SEL_MODE_ENABLE)) - break; - MM_Wait(10); - } - } - else - REG_WR(pDevice, SndBdSel.Mode, data | SND_BD_SEL_MODE_ENABLE); - break; + case T3_BLOCK_SEND_BD_SELECTOR: + data = REG_RD (pDevice, SndBdSel.Mode); + if (cntrl == LM_DISABLE) { + data &= ~SND_BD_SEL_MODE_ENABLE; + REG_WR (pDevice, SndBdSel.Mode, data); + for (j = 0; j < MaxWaitCnt; j++) { + if (! + (REG_RD (pDevice, SndBdSel.Mode) & + SND_BD_SEL_MODE_ENABLE)) + break; + MM_Wait (10); + } + } else + REG_WR (pDevice, SndBdSel.Mode, + data | SND_BD_SEL_MODE_ENABLE); + break; - case T3_BLOCK_SEND_DATA_INITIATOR: - data = REG_RD(pDevice, SndDataIn.Mode); - if (cntrl == LM_DISABLE) - { - data &= ~T3_SND_DATA_IN_MODE_ENABLE; - REG_WR(pDevice, SndDataIn.Mode,data); - for(j = 0; j < MaxWaitCnt; j++) - { - if(!(REG_RD(pDevice, SndDataIn.Mode) & T3_SND_DATA_IN_MODE_ENABLE)) - break; - MM_Wait(10); - } - } - else - REG_WR(pDevice, SndDataIn.Mode,data | T3_SND_DATA_IN_MODE_ENABLE); - break; + case T3_BLOCK_SEND_DATA_INITIATOR: + data = REG_RD (pDevice, SndDataIn.Mode); + if (cntrl == LM_DISABLE) { + data &= ~T3_SND_DATA_IN_MODE_ENABLE; + REG_WR (pDevice, SndDataIn.Mode, data); + for (j = 0; j < MaxWaitCnt; j++) { + if (! + (REG_RD (pDevice, SndDataIn.Mode) & + T3_SND_DATA_IN_MODE_ENABLE)) + break; + MM_Wait (10); + } + } else + REG_WR (pDevice, SndDataIn.Mode, + data | T3_SND_DATA_IN_MODE_ENABLE); + break; - case T3_BLOCK_SEND_DATA_COMP: - data = REG_RD(pDevice, SndDataComp.Mode); - if (cntrl == LM_DISABLE) - { - data &= ~SND_DATA_COMP_MODE_ENABLE; - REG_WR(pDevice, SndDataComp.Mode, data); - for(j = 0; j < MaxWaitCnt; j++) - { - if(!(REG_RD(pDevice, SndDataComp.Mode) & SND_DATA_COMP_MODE_ENABLE)) - break; - MM_Wait(10); - } - } - else - REG_WR(pDevice, SndDataComp.Mode,data | SND_DATA_COMP_MODE_ENABLE); - break; + case T3_BLOCK_SEND_DATA_COMP: + data = REG_RD (pDevice, SndDataComp.Mode); + if (cntrl == LM_DISABLE) { + data &= ~SND_DATA_COMP_MODE_ENABLE; + REG_WR (pDevice, SndDataComp.Mode, data); + for (j = 0; j < MaxWaitCnt; j++) { + if (! + (REG_RD (pDevice, SndDataComp.Mode) + & SND_DATA_COMP_MODE_ENABLE)) + break; + MM_Wait (10); + } + } else + REG_WR (pDevice, SndDataComp.Mode, + data | SND_DATA_COMP_MODE_ENABLE); + break; - case T3_BLOCK_MAC_TX_ENGINE: - if(cntrl == LM_DISABLE) - { - pDevice->TxMode &= ~TX_MODE_ENABLE; - REG_WR(pDevice, MacCtrl.TxMode, pDevice->TxMode); - for(j = 0; j < MaxWaitCnt; j++) - { - if(!(REG_RD(pDevice, MacCtrl.TxMode) & TX_MODE_ENABLE)) - break; - MM_Wait(10); - } - } - else - { - pDevice->TxMode |= TX_MODE_ENABLE; - REG_WR(pDevice, MacCtrl.TxMode, pDevice->TxMode); - } - break; + case T3_BLOCK_MAC_TX_ENGINE: + if (cntrl == LM_DISABLE) { + pDevice->TxMode &= ~TX_MODE_ENABLE; + REG_WR (pDevice, MacCtrl.TxMode, + pDevice->TxMode); + for (j = 0; j < MaxWaitCnt; j++) { + if (! + (REG_RD (pDevice, MacCtrl.TxMode) & + TX_MODE_ENABLE)) + break; + MM_Wait (10); + } + } else { + pDevice->TxMode |= TX_MODE_ENABLE; + REG_WR (pDevice, MacCtrl.TxMode, + pDevice->TxMode); + } + break; - case T3_BLOCK_MEM_ARBITOR: - data = REG_RD(pDevice, MemArbiter.Mode); - if (cntrl == LM_DISABLE) - { - data &= ~T3_MEM_ARBITER_MODE_ENABLE; - REG_WR(pDevice, MemArbiter.Mode, data); - for(j = 0; j < MaxWaitCnt; j++) - { - if(!(REG_RD(pDevice, MemArbiter.Mode) & T3_MEM_ARBITER_MODE_ENABLE)) - break; - MM_Wait(10); - } - } - else - REG_WR(pDevice, MemArbiter.Mode,data|T3_MEM_ARBITER_MODE_ENABLE); - break; + case T3_BLOCK_MEM_ARBITOR: + data = REG_RD (pDevice, MemArbiter.Mode); + if (cntrl == LM_DISABLE) { + data &= ~T3_MEM_ARBITER_MODE_ENABLE; + REG_WR (pDevice, MemArbiter.Mode, data); + for (j = 0; j < MaxWaitCnt; j++) { + if (! + (REG_RD (pDevice, MemArbiter.Mode) & + T3_MEM_ARBITER_MODE_ENABLE)) + break; + MM_Wait (10); + } + } else + REG_WR (pDevice, MemArbiter.Mode, + data | T3_MEM_ARBITER_MODE_ENABLE); + break; - case T3_BLOCK_MBUF_MANAGER: - data = REG_RD(pDevice, BufMgr.Mode); - if (cntrl == LM_DISABLE) - { - data &= ~BUFMGR_MODE_ENABLE; - REG_WR(pDevice, BufMgr.Mode,data); - for(j = 0; j < MaxWaitCnt; j++) - { - if(!(REG_RD(pDevice, BufMgr.Mode) & BUFMGR_MODE_ENABLE)) - break; - MM_Wait(10); - } - } - else - REG_WR(pDevice, BufMgr.Mode,data | BUFMGR_MODE_ENABLE); - break; + case T3_BLOCK_MBUF_MANAGER: + data = REG_RD (pDevice, BufMgr.Mode); + if (cntrl == LM_DISABLE) { + data &= ~BUFMGR_MODE_ENABLE; + REG_WR (pDevice, BufMgr.Mode, data); + for (j = 0; j < MaxWaitCnt; j++) { + if (! + (REG_RD (pDevice, BufMgr.Mode) & + BUFMGR_MODE_ENABLE)) + break; + MM_Wait (10); + } + } else + REG_WR (pDevice, BufMgr.Mode, + data | BUFMGR_MODE_ENABLE); + break; - case T3_BLOCK_MAC_GLOBAL: - if(cntrl == LM_DISABLE) - { - pDevice->MacMode &= ~(MAC_MODE_ENABLE_TDE | - MAC_MODE_ENABLE_RDE | - MAC_MODE_ENABLE_FHDE); - } - else - { - pDevice->MacMode |= (MAC_MODE_ENABLE_TDE | - MAC_MODE_ENABLE_RDE | - MAC_MODE_ENABLE_FHDE); - } - REG_WR(pDevice, MacCtrl.Mode, pDevice->MacMode); - break; + case T3_BLOCK_MAC_GLOBAL: + if (cntrl == LM_DISABLE) { + pDevice->MacMode &= ~(MAC_MODE_ENABLE_TDE | + MAC_MODE_ENABLE_RDE | + MAC_MODE_ENABLE_FHDE); + } else { + pDevice->MacMode |= (MAC_MODE_ENABLE_TDE | + MAC_MODE_ENABLE_RDE | + MAC_MODE_ENABLE_FHDE); + } + REG_WR (pDevice, MacCtrl.Mode, pDevice->MacMode); + break; - default: - return LM_STATUS_FAILURE; - } /* switch */ + default: + return LM_STATUS_FAILURE; + } /* switch */ - if(j >= MaxWaitCnt) - { - return LM_STATUS_FAILURE; + if (j >= MaxWaitCnt) { + return LM_STATUS_FAILURE; + } } - } - return LM_STATUS_SUCCESS; + return LM_STATUS_SUCCESS; } /******************************************************************************/ @@ -2295,682 +2129,631 @@ LM_UINT32 mask,LM_UINT32 cntrl) /* Return: */ /* LM_STATUS_SUCCESS */ /******************************************************************************/ -LM_STATUS -LM_ResetAdapter( -PLM_DEVICE_BLOCK pDevice) +LM_STATUS LM_ResetAdapter (PLM_DEVICE_BLOCK pDevice) { - LM_UINT32 Value32; - LM_UINT16 Value16; - LM_UINT32 j, k; + LM_UINT32 Value32; + LM_UINT16 Value16; + LM_UINT32 j, k; - /* Disable interrupt. */ - LM_DisableInterrupt(pDevice); + /* Disable interrupt. */ + LM_DisableInterrupt (pDevice); - /* May get a spurious interrupt */ - pDevice->pStatusBlkVirt->Status = STATUS_BLOCK_UPDATED; + /* May get a spurious interrupt */ + pDevice->pStatusBlkVirt->Status = STATUS_BLOCK_UPDATED; - /* Disable transmit and receive DMA engines. Abort all pending requests. */ - if(pDevice->InitDone) - { - LM_Abort(pDevice); - } - - pDevice->ShuttingDown = FALSE; - - LM_ResetChip(pDevice); - - /* Bug: Athlon fix for B3 silicon only. This bit does not do anything */ - /* in other chip revisions. */ - if(pDevice->DelayPciGrant) - { - Value32 = REG_RD(pDevice, PciCfg.ClockCtrl); - REG_WR(pDevice, PciCfg.ClockCtrl, Value32 | BIT_31); - } - - if(pDevice->ChipRevId == T3_CHIP_ID_5704_A0) - { - if (!(pDevice->PciState & T3_PCI_STATE_CONVENTIONAL_PCI_MODE)) - { - Value32 = REG_RD(pDevice, PciCfg.PciState); - Value32 |= T3_PCI_STATE_RETRY_SAME_DMA; - REG_WR(pDevice, PciCfg.PciState, Value32); + /* Disable transmit and receive DMA engines. Abort all pending requests. */ + if (pDevice->InitDone) { + LM_Abort (pDevice); } - } - /* Enable TaggedStatus mode. */ - if(pDevice->UseTaggedStatus) - { - pDevice->MiscHostCtrl |= MISC_HOST_CTRL_ENABLE_TAGGED_STATUS_MODE; - } + pDevice->ShuttingDown = FALSE; - /* Restore PCI configuration registers. */ - MM_WriteConfig32(pDevice, PCI_CACHE_LINE_SIZE_REG, - pDevice->SavedCacheLineReg); - MM_WriteConfig32(pDevice, PCI_SUBSYSTEM_VENDOR_ID_REG, - (pDevice->SubsystemId << 16) | pDevice->SubsystemVendorId); + LM_ResetChip (pDevice); - /* Clear the statistics block. */ - for(j = 0x0300; j < 0x0b00; j++) - { - MEM_WR_OFFSET(pDevice, j, 0); - } + /* Bug: Athlon fix for B3 silicon only. This bit does not do anything */ + /* in other chip revisions. */ + if (pDevice->DelayPciGrant) { + Value32 = REG_RD (pDevice, PciCfg.ClockCtrl); + REG_WR (pDevice, PciCfg.ClockCtrl, Value32 | BIT_31); + } - /* Initialize the statistis Block */ - pDevice->pStatusBlkVirt->Status = 0; - pDevice->pStatusBlkVirt->RcvStdConIdx = 0; - pDevice->pStatusBlkVirt->RcvJumboConIdx = 0; - pDevice->pStatusBlkVirt->RcvMiniConIdx = 0; + if (pDevice->ChipRevId == T3_CHIP_ID_5704_A0) { + if (!(pDevice->PciState & T3_PCI_STATE_CONVENTIONAL_PCI_MODE)) { + Value32 = REG_RD (pDevice, PciCfg.PciState); + Value32 |= T3_PCI_STATE_RETRY_SAME_DMA; + REG_WR (pDevice, PciCfg.PciState, Value32); + } + } - for(j = 0; j < 16; j++) - { - pDevice->pStatusBlkVirt->Idx[j].RcvProdIdx = 0; - pDevice->pStatusBlkVirt->Idx[j].SendConIdx = 0; - } + /* Enable TaggedStatus mode. */ + if (pDevice->UseTaggedStatus) { + pDevice->MiscHostCtrl |= + MISC_HOST_CTRL_ENABLE_TAGGED_STATUS_MODE; + } - for(k = 0; k < T3_STD_RCV_RCB_ENTRY_COUNT ;k++) - { - pDevice->pRxStdBdVirt[k].HostAddr.High = 0; - pDevice->pRxStdBdVirt[k].HostAddr.Low = 0; - } + /* Restore PCI configuration registers. */ + MM_WriteConfig32 (pDevice, PCI_CACHE_LINE_SIZE_REG, + pDevice->SavedCacheLineReg); + MM_WriteConfig32 (pDevice, PCI_SUBSYSTEM_VENDOR_ID_REG, + (pDevice->SubsystemId << 16) | pDevice-> + SubsystemVendorId); + + /* Clear the statistics block. */ + for (j = 0x0300; j < 0x0b00; j++) { + MEM_WR_OFFSET (pDevice, j, 0); + } + + /* Initialize the statistis Block */ + pDevice->pStatusBlkVirt->Status = 0; + pDevice->pStatusBlkVirt->RcvStdConIdx = 0; + pDevice->pStatusBlkVirt->RcvJumboConIdx = 0; + pDevice->pStatusBlkVirt->RcvMiniConIdx = 0; + + for (j = 0; j < 16; j++) { + pDevice->pStatusBlkVirt->Idx[j].RcvProdIdx = 0; + pDevice->pStatusBlkVirt->Idx[j].SendConIdx = 0; + } + + for (k = 0; k < T3_STD_RCV_RCB_ENTRY_COUNT; k++) { + pDevice->pRxStdBdVirt[k].HostAddr.High = 0; + pDevice->pRxStdBdVirt[k].HostAddr.Low = 0; + } #if T3_JUMBO_RCV_RCB_ENTRY_COUNT - /* Receive jumbo BD buffer. */ - for(k = 0; k < T3_JUMBO_RCV_RCB_ENTRY_COUNT; k++) - { - pDevice->pRxJumboBdVirt[k].HostAddr.High = 0; - pDevice->pRxJumboBdVirt[k].HostAddr.Low = 0; - } + /* Receive jumbo BD buffer. */ + for (k = 0; k < T3_JUMBO_RCV_RCB_ENTRY_COUNT; k++) { + pDevice->pRxJumboBdVirt[k].HostAddr.High = 0; + pDevice->pRxJumboBdVirt[k].HostAddr.Low = 0; + } #endif - REG_WR(pDevice, PciCfg.DmaReadWriteCtrl, pDevice->DmaReadWriteCtrl); + REG_WR (pDevice, PciCfg.DmaReadWriteCtrl, pDevice->DmaReadWriteCtrl); - /* GRC mode control register. */ -#ifdef BIG_ENDIAN_PCI /* Jimmy, this ifdef block deleted in new code! */ - Value32 = - GRC_MODE_WORD_SWAP_DATA | - GRC_MODE_WORD_SWAP_NON_FRAME_DATA | - GRC_MODE_INT_ON_MAC_ATTN | - GRC_MODE_HOST_STACK_UP; + /* GRC mode control register. */ +#ifdef BIG_ENDIAN_PCI /* Jimmy, this ifdef block deleted in new code! */ + Value32 = + GRC_MODE_WORD_SWAP_DATA | + GRC_MODE_WORD_SWAP_NON_FRAME_DATA | + GRC_MODE_INT_ON_MAC_ATTN | GRC_MODE_HOST_STACK_UP; #else - /* No CPU Swap modes for PCI IO */ - Value32 = + /* No CPU Swap modes for PCI IO */ + Value32 = #ifdef BIG_ENDIAN_HOST - GRC_MODE_BYTE_SWAP_NON_FRAME_DATA | - GRC_MODE_WORD_SWAP_NON_FRAME_DATA | - GRC_MODE_BYTE_SWAP_DATA | - GRC_MODE_WORD_SWAP_DATA | + GRC_MODE_BYTE_SWAP_NON_FRAME_DATA | + GRC_MODE_WORD_SWAP_NON_FRAME_DATA | + GRC_MODE_BYTE_SWAP_DATA | GRC_MODE_WORD_SWAP_DATA | #else - GRC_MODE_WORD_SWAP_NON_FRAME_DATA | - GRC_MODE_BYTE_SWAP_DATA | - GRC_MODE_WORD_SWAP_DATA | + GRC_MODE_WORD_SWAP_NON_FRAME_DATA | + GRC_MODE_BYTE_SWAP_DATA | GRC_MODE_WORD_SWAP_DATA | #endif - GRC_MODE_INT_ON_MAC_ATTN | - GRC_MODE_HOST_STACK_UP; -#endif /* !BIG_ENDIAN_PCI */ + GRC_MODE_INT_ON_MAC_ATTN | GRC_MODE_HOST_STACK_UP; +#endif /* !BIG_ENDIAN_PCI */ - /* Configure send BD mode. */ - if(pDevice->NicSendBd == FALSE) - { - Value32 |= GRC_MODE_HOST_SEND_BDS; - } - else - { - Value32 |= GRC_MODE_4X_NIC_BASED_SEND_RINGS; - } - - /* Configure pseudo checksum mode. */ - if(pDevice->NoTxPseudoHdrChksum) - { - Value32 |= GRC_MODE_TX_NO_PSEUDO_HEADER_CHKSUM; - } - - if(pDevice->NoRxPseudoHdrChksum) - { - Value32 |= GRC_MODE_RX_NO_PSEUDO_HEADER_CHKSUM; - } - - REG_WR(pDevice, Grc.Mode, Value32); - - /* Setup the timer prescalar register. */ - REG_WR(pDevice, Grc.MiscCfg, 65 << 1); /* Clock is alwasy 66Mhz. */ - - /* Set up the MBUF pool base address and size. */ - REG_WR(pDevice, BufMgr.MbufPoolAddr, pDevice->MbufBase); - REG_WR(pDevice, BufMgr.MbufPoolSize, pDevice->MbufSize); - - /* Set up the DMA descriptor pool base address and size. */ - REG_WR(pDevice, BufMgr.DmaDescPoolAddr, T3_NIC_DMA_DESC_POOL_ADDR); - REG_WR(pDevice, BufMgr.DmaDescPoolSize, T3_NIC_DMA_DESC_POOL_SIZE); - - /* Configure MBUF and Threshold watermarks */ - /* Configure the DMA read MBUF low water mark. */ - if(pDevice->DmaMbufLowMark) - { - REG_WR(pDevice, BufMgr.MbufReadDmaLowWaterMark, - pDevice->DmaMbufLowMark); - } - else - { - if(pDevice->TxMtu < MAX_ETHERNET_PACKET_BUFFER_SIZE) - { - REG_WR(pDevice, BufMgr.MbufReadDmaLowWaterMark, - T3_DEF_DMA_MBUF_LOW_WMARK); + /* Configure send BD mode. */ + if (pDevice->NicSendBd == FALSE) { + Value32 |= GRC_MODE_HOST_SEND_BDS; + } else { + Value32 |= GRC_MODE_4X_NIC_BASED_SEND_RINGS; } - else - { - REG_WR(pDevice, BufMgr.MbufReadDmaLowWaterMark, - T3_DEF_DMA_MBUF_LOW_WMARK_JUMBO); + + /* Configure pseudo checksum mode. */ + if (pDevice->NoTxPseudoHdrChksum) { + Value32 |= GRC_MODE_TX_NO_PSEUDO_HEADER_CHKSUM; } - } - /* Configure the MAC Rx MBUF low water mark. */ - if(pDevice->RxMacMbufLowMark) - { - REG_WR(pDevice, BufMgr.MbufMacRxLowWaterMark, - pDevice->RxMacMbufLowMark); - } - else - { - if(pDevice->TxMtu < MAX_ETHERNET_PACKET_BUFFER_SIZE) - { - REG_WR(pDevice, BufMgr.MbufMacRxLowWaterMark, - T3_DEF_RX_MAC_MBUF_LOW_WMARK); + if (pDevice->NoRxPseudoHdrChksum) { + Value32 |= GRC_MODE_RX_NO_PSEUDO_HEADER_CHKSUM; } - else - { - REG_WR(pDevice, BufMgr.MbufMacRxLowWaterMark, - T3_DEF_RX_MAC_MBUF_LOW_WMARK_JUMBO); + + REG_WR (pDevice, Grc.Mode, Value32); + + /* Setup the timer prescalar register. */ + REG_WR (pDevice, Grc.MiscCfg, 65 << 1); /* Clock is alwasy 66Mhz. */ + + /* Set up the MBUF pool base address and size. */ + REG_WR (pDevice, BufMgr.MbufPoolAddr, pDevice->MbufBase); + REG_WR (pDevice, BufMgr.MbufPoolSize, pDevice->MbufSize); + + /* Set up the DMA descriptor pool base address and size. */ + REG_WR (pDevice, BufMgr.DmaDescPoolAddr, T3_NIC_DMA_DESC_POOL_ADDR); + REG_WR (pDevice, BufMgr.DmaDescPoolSize, T3_NIC_DMA_DESC_POOL_SIZE); + + /* Configure MBUF and Threshold watermarks */ + /* Configure the DMA read MBUF low water mark. */ + if (pDevice->DmaMbufLowMark) { + REG_WR (pDevice, BufMgr.MbufReadDmaLowWaterMark, + pDevice->DmaMbufLowMark); + } else { + if (pDevice->TxMtu < MAX_ETHERNET_PACKET_BUFFER_SIZE) { + REG_WR (pDevice, BufMgr.MbufReadDmaLowWaterMark, + T3_DEF_DMA_MBUF_LOW_WMARK); + } else { + REG_WR (pDevice, BufMgr.MbufReadDmaLowWaterMark, + T3_DEF_DMA_MBUF_LOW_WMARK_JUMBO); + } } - } - /* Configure the MBUF high water mark. */ - if(pDevice->MbufHighMark) - { - REG_WR(pDevice, BufMgr.MbufHighWaterMark, pDevice->MbufHighMark); - } - else - { - if(pDevice->TxMtu < MAX_ETHERNET_PACKET_BUFFER_SIZE) - { - REG_WR(pDevice, BufMgr.MbufHighWaterMark, - T3_DEF_MBUF_HIGH_WMARK); + /* Configure the MAC Rx MBUF low water mark. */ + if (pDevice->RxMacMbufLowMark) { + REG_WR (pDevice, BufMgr.MbufMacRxLowWaterMark, + pDevice->RxMacMbufLowMark); + } else { + if (pDevice->TxMtu < MAX_ETHERNET_PACKET_BUFFER_SIZE) { + REG_WR (pDevice, BufMgr.MbufMacRxLowWaterMark, + T3_DEF_RX_MAC_MBUF_LOW_WMARK); + } else { + REG_WR (pDevice, BufMgr.MbufMacRxLowWaterMark, + T3_DEF_RX_MAC_MBUF_LOW_WMARK_JUMBO); + } } - else - { - REG_WR(pDevice, BufMgr.MbufHighWaterMark, - T3_DEF_MBUF_HIGH_WMARK_JUMBO); + + /* Configure the MBUF high water mark. */ + if (pDevice->MbufHighMark) { + REG_WR (pDevice, BufMgr.MbufHighWaterMark, + pDevice->MbufHighMark); + } else { + if (pDevice->TxMtu < MAX_ETHERNET_PACKET_BUFFER_SIZE) { + REG_WR (pDevice, BufMgr.MbufHighWaterMark, + T3_DEF_MBUF_HIGH_WMARK); + } else { + REG_WR (pDevice, BufMgr.MbufHighWaterMark, + T3_DEF_MBUF_HIGH_WMARK_JUMBO); + } } - } - REG_WR(pDevice, BufMgr.DmaLowWaterMark, T3_DEF_DMA_DESC_LOW_WMARK); - REG_WR(pDevice, BufMgr.DmaHighWaterMark, T3_DEF_DMA_DESC_HIGH_WMARK); + REG_WR (pDevice, BufMgr.DmaLowWaterMark, T3_DEF_DMA_DESC_LOW_WMARK); + REG_WR (pDevice, BufMgr.DmaHighWaterMark, T3_DEF_DMA_DESC_HIGH_WMARK); - /* Enable buffer manager. */ - REG_WR(pDevice, BufMgr.Mode, BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE); + /* Enable buffer manager. */ + REG_WR (pDevice, BufMgr.Mode, + BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE); - for(j = 0 ;j < 2000; j++) - { - if(REG_RD(pDevice, BufMgr.Mode) & BUFMGR_MODE_ENABLE) - break; - MM_Wait(10); - } + for (j = 0; j < 2000; j++) { + if (REG_RD (pDevice, BufMgr.Mode) & BUFMGR_MODE_ENABLE) + break; + MM_Wait (10); + } - if(j >= 2000) - { - return LM_STATUS_FAILURE; - } + if (j >= 2000) { + return LM_STATUS_FAILURE; + } - /* Enable the FTQs. */ - REG_WR(pDevice, Ftq.Reset, 0xffffffff); - REG_WR(pDevice, Ftq.Reset, 0); + /* Enable the FTQs. */ + REG_WR (pDevice, Ftq.Reset, 0xffffffff); + REG_WR (pDevice, Ftq.Reset, 0); - /* Wait until FTQ is ready */ - for(j = 0; j < 2000; j++) - { - if(REG_RD(pDevice, Ftq.Reset) == 0) - break; - MM_Wait(10); - } + /* Wait until FTQ is ready */ + for (j = 0; j < 2000; j++) { + if (REG_RD (pDevice, Ftq.Reset) == 0) + break; + MM_Wait (10); + } - if(j >= 2000) - { - return LM_STATUS_FAILURE; - } + if (j >= 2000) { + return LM_STATUS_FAILURE; + } - /* Initialize the Standard Receive RCB. */ - REG_WR(pDevice, RcvDataBdIn.StdRcvRcb.HostRingAddr.High, - pDevice->RxStdBdPhy.High); - REG_WR(pDevice, RcvDataBdIn.StdRcvRcb.HostRingAddr.Low, - pDevice->RxStdBdPhy.Low); - REG_WR(pDevice, RcvDataBdIn.StdRcvRcb.u.MaxLen_Flags, - MAX_STD_RCV_BUFFER_SIZE << 16); + /* Initialize the Standard Receive RCB. */ + REG_WR (pDevice, RcvDataBdIn.StdRcvRcb.HostRingAddr.High, + pDevice->RxStdBdPhy.High); + REG_WR (pDevice, RcvDataBdIn.StdRcvRcb.HostRingAddr.Low, + pDevice->RxStdBdPhy.Low); + REG_WR (pDevice, RcvDataBdIn.StdRcvRcb.u.MaxLen_Flags, + MAX_STD_RCV_BUFFER_SIZE << 16); - /* Initialize the Jumbo Receive RCB. */ - REG_WR(pDevice, RcvDataBdIn.JumboRcvRcb.u.MaxLen_Flags, - T3_RCB_FLAG_RING_DISABLED); + /* Initialize the Jumbo Receive RCB. */ + REG_WR (pDevice, RcvDataBdIn.JumboRcvRcb.u.MaxLen_Flags, + T3_RCB_FLAG_RING_DISABLED); #if T3_JUMBO_RCV_RCB_ENTRY_COUNT - REG_WR(pDevice, RcvDataBdIn.JumboRcvRcb.HostRingAddr.High, - pDevice->RxJumboBdPhy.High); - REG_WR(pDevice, RcvDataBdIn.JumboRcvRcb.HostRingAddr.Low, - pDevice->RxJumboBdPhy.Low); + REG_WR (pDevice, RcvDataBdIn.JumboRcvRcb.HostRingAddr.High, + pDevice->RxJumboBdPhy.High); + REG_WR (pDevice, RcvDataBdIn.JumboRcvRcb.HostRingAddr.Low, + pDevice->RxJumboBdPhy.Low); - REG_WR(pDevice, RcvDataBdIn.JumboRcvRcb.u.MaxLen_Flags, 0); + REG_WR (pDevice, RcvDataBdIn.JumboRcvRcb.u.MaxLen_Flags, 0); -#endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */ +#endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */ - /* Initialize the Mini Receive RCB. */ - REG_WR(pDevice, RcvDataBdIn.MiniRcvRcb.u.MaxLen_Flags, - T3_RCB_FLAG_RING_DISABLED); + /* Initialize the Mini Receive RCB. */ + REG_WR (pDevice, RcvDataBdIn.MiniRcvRcb.u.MaxLen_Flags, + T3_RCB_FLAG_RING_DISABLED); - { - REG_WR(pDevice, RcvDataBdIn.StdRcvRcb.NicRingAddr, - (LM_UINT32) T3_NIC_STD_RCV_BUFFER_DESC_ADDR); - REG_WR(pDevice, RcvDataBdIn.JumboRcvRcb.NicRingAddr, - (LM_UINT32) T3_NIC_JUMBO_RCV_BUFFER_DESC_ADDR); - } + { + REG_WR (pDevice, RcvDataBdIn.StdRcvRcb.NicRingAddr, + (LM_UINT32) T3_NIC_STD_RCV_BUFFER_DESC_ADDR); + REG_WR (pDevice, RcvDataBdIn.JumboRcvRcb.NicRingAddr, + (LM_UINT32) T3_NIC_JUMBO_RCV_BUFFER_DESC_ADDR); + } - /* Receive BD Ring replenish threshold. */ - REG_WR(pDevice, RcvBdIn.StdRcvThreshold, pDevice->RxStdDescCnt/8); + /* Receive BD Ring replenish threshold. */ + REG_WR (pDevice, RcvBdIn.StdRcvThreshold, pDevice->RxStdDescCnt / 8); #if T3_JUMBO_RCV_RCB_ENTRY_COUNT - REG_WR(pDevice, RcvBdIn.JumboRcvThreshold, pDevice->RxJumboDescCnt/8); -#endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */ + REG_WR (pDevice, RcvBdIn.JumboRcvThreshold, + pDevice->RxJumboDescCnt / 8); +#endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */ - /* Disable all the unused rings. */ - for(j = 0; j < T3_MAX_SEND_RCB_COUNT; j++) { - MEM_WR(pDevice, SendRcb[j].u.MaxLen_Flags, T3_RCB_FLAG_RING_DISABLED); - } /* for */ + /* Disable all the unused rings. */ + for (j = 0; j < T3_MAX_SEND_RCB_COUNT; j++) { + MEM_WR (pDevice, SendRcb[j].u.MaxLen_Flags, + T3_RCB_FLAG_RING_DISABLED); + } /* for */ - /* Initialize the indices. */ - pDevice->SendProdIdx = 0; - pDevice->SendConIdx = 0; + /* Initialize the indices. */ + pDevice->SendProdIdx = 0; + pDevice->SendConIdx = 0; - MB_REG_WR(pDevice, Mailbox.SendHostProdIdx[0].Low, 0); - MB_REG_WR(pDevice, Mailbox.SendNicProdIdx[0].Low, 0); + MB_REG_WR (pDevice, Mailbox.SendHostProdIdx[0].Low, 0); + MB_REG_WR (pDevice, Mailbox.SendNicProdIdx[0].Low, 0); - /* Set up host or NIC based send RCB. */ - if(pDevice->NicSendBd == FALSE) - { - MEM_WR(pDevice, SendRcb[0].HostRingAddr.High, - pDevice->SendBdPhy.High); - MEM_WR(pDevice, SendRcb[0].HostRingAddr.Low, - pDevice->SendBdPhy.Low); + /* Set up host or NIC based send RCB. */ + if (pDevice->NicSendBd == FALSE) { + MEM_WR (pDevice, SendRcb[0].HostRingAddr.High, + pDevice->SendBdPhy.High); + MEM_WR (pDevice, SendRcb[0].HostRingAddr.Low, + pDevice->SendBdPhy.Low); + + /* Set up the NIC ring address in the RCB. */ + MEM_WR (pDevice, SendRcb[0].NicRingAddr, + T3_NIC_SND_BUFFER_DESC_ADDR); + + /* Setup the RCB. */ + MEM_WR (pDevice, SendRcb[0].u.MaxLen_Flags, + T3_SEND_RCB_ENTRY_COUNT << 16); + + for (k = 0; k < T3_SEND_RCB_ENTRY_COUNT; k++) { + pDevice->pSendBdVirt[k].HostAddr.High = 0; + pDevice->pSendBdVirt[k].HostAddr.Low = 0; + } + } else { + MEM_WR (pDevice, SendRcb[0].HostRingAddr.High, 0); + MEM_WR (pDevice, SendRcb[0].HostRingAddr.Low, 0); + MEM_WR (pDevice, SendRcb[0].NicRingAddr, + pDevice->SendBdPhy.Low); + + for (k = 0; k < T3_SEND_RCB_ENTRY_COUNT; k++) { + __raw_writel (0, + &(pDevice->pSendBdVirt[k].HostAddr.High)); + __raw_writel (0, + &(pDevice->pSendBdVirt[k].HostAddr.Low)); + __raw_writel (0, + &(pDevice->pSendBdVirt[k].u1.Len_Flags)); + pDevice->ShadowSendBd[k].HostAddr.High = 0; + pDevice->ShadowSendBd[k].u1.Len_Flags = 0; + } + } + atomic_set (&pDevice->SendBdLeft, T3_SEND_RCB_ENTRY_COUNT - 1); + + /* Configure the receive return rings. */ + for (j = 0; j < T3_MAX_RCV_RETURN_RCB_COUNT; j++) { + MEM_WR (pDevice, RcvRetRcb[j].u.MaxLen_Flags, + T3_RCB_FLAG_RING_DISABLED); + } + + pDevice->RcvRetConIdx = 0; + + MEM_WR (pDevice, RcvRetRcb[0].HostRingAddr.High, + pDevice->RcvRetBdPhy.High); + MEM_WR (pDevice, RcvRetRcb[0].HostRingAddr.Low, + pDevice->RcvRetBdPhy.Low); /* Set up the NIC ring address in the RCB. */ - MEM_WR(pDevice, SendRcb[0].NicRingAddr,T3_NIC_SND_BUFFER_DESC_ADDR); + /* Not very clear from the spec. I am guessing that for Receive */ + /* Return Ring, NicRingAddr is not used. */ + MEM_WR (pDevice, RcvRetRcb[0].NicRingAddr, 0); /* Setup the RCB. */ - MEM_WR(pDevice, SendRcb[0].u.MaxLen_Flags, - T3_SEND_RCB_ENTRY_COUNT << 16); + MEM_WR (pDevice, RcvRetRcb[0].u.MaxLen_Flags, + T3_RCV_RETURN_RCB_ENTRY_COUNT << 16); - for(k = 0; k < T3_SEND_RCB_ENTRY_COUNT; k++) - { - pDevice->pSendBdVirt[k].HostAddr.High = 0; - pDevice->pSendBdVirt[k].HostAddr.Low = 0; - } - } - else - { - MEM_WR(pDevice, SendRcb[0].HostRingAddr.High, 0); - MEM_WR(pDevice, SendRcb[0].HostRingAddr.Low, 0); - MEM_WR(pDevice, SendRcb[0].NicRingAddr, - pDevice->SendBdPhy.Low); - - for(k = 0; k < T3_SEND_RCB_ENTRY_COUNT; k++) - { - __raw_writel(0, &(pDevice->pSendBdVirt[k].HostAddr.High)); - __raw_writel(0, &(pDevice->pSendBdVirt[k].HostAddr.Low)); - __raw_writel(0, &(pDevice->pSendBdVirt[k].u1.Len_Flags)); - pDevice->ShadowSendBd[k].HostAddr.High = 0; - pDevice->ShadowSendBd[k].u1.Len_Flags = 0; - } - } - atomic_set(&pDevice->SendBdLeft, T3_SEND_RCB_ENTRY_COUNT-1); - - /* Configure the receive return rings. */ - for(j = 0; j < T3_MAX_RCV_RETURN_RCB_COUNT; j++) - { - MEM_WR(pDevice, RcvRetRcb[j].u.MaxLen_Flags, T3_RCB_FLAG_RING_DISABLED); - } - - pDevice->RcvRetConIdx = 0; - - MEM_WR(pDevice, RcvRetRcb[0].HostRingAddr.High, - pDevice->RcvRetBdPhy.High); - MEM_WR(pDevice, RcvRetRcb[0].HostRingAddr.Low, - pDevice->RcvRetBdPhy.Low); - - /* Set up the NIC ring address in the RCB. */ - /* Not very clear from the spec. I am guessing that for Receive */ - /* Return Ring, NicRingAddr is not used. */ - MEM_WR(pDevice, RcvRetRcb[0].NicRingAddr, 0); - - /* Setup the RCB. */ - MEM_WR(pDevice, RcvRetRcb[0].u.MaxLen_Flags, - T3_RCV_RETURN_RCB_ENTRY_COUNT << 16); - - /* Reinitialize RX ring producer index */ - MB_REG_WR(pDevice, Mailbox.RcvStdProdIdx.Low, 0); - MB_REG_WR(pDevice, Mailbox.RcvJumboProdIdx.Low, 0); - MB_REG_WR(pDevice, Mailbox.RcvMiniProdIdx.Low, 0); + /* Reinitialize RX ring producer index */ + MB_REG_WR (pDevice, Mailbox.RcvStdProdIdx.Low, 0); + MB_REG_WR (pDevice, Mailbox.RcvJumboProdIdx.Low, 0); + MB_REG_WR (pDevice, Mailbox.RcvMiniProdIdx.Low, 0); #if T3_JUMBO_RCV_RCB_ENTRY_COUNT - pDevice->RxJumboProdIdx = 0; - pDevice->RxJumboQueuedCnt = 0; + pDevice->RxJumboProdIdx = 0; + pDevice->RxJumboQueuedCnt = 0; #endif - /* Reinitialize our copy of the indices. */ - pDevice->RxStdProdIdx = 0; - pDevice->RxStdQueuedCnt = 0; + /* Reinitialize our copy of the indices. */ + pDevice->RxStdProdIdx = 0; + pDevice->RxStdQueuedCnt = 0; #if T3_JUMBO_RCV_ENTRY_COUNT - pDevice->RxJumboProdIdx = 0; -#endif /* T3_JUMBO_RCV_ENTRY_COUNT */ + pDevice->RxJumboProdIdx = 0; +#endif /* T3_JUMBO_RCV_ENTRY_COUNT */ - /* Configure the MAC address. */ - LM_SetMacAddress(pDevice, pDevice->NodeAddress); + /* Configure the MAC address. */ + LM_SetMacAddress (pDevice, pDevice->NodeAddress); - /* Initialize the transmit random backoff seed. */ - Value32 = (pDevice->NodeAddress[0] + pDevice->NodeAddress[1] + - pDevice->NodeAddress[2] + pDevice->NodeAddress[3] + - pDevice->NodeAddress[4] + pDevice->NodeAddress[5]) & - MAC_TX_BACKOFF_SEED_MASK; - REG_WR(pDevice, MacCtrl.TxBackoffSeed, Value32); + /* Initialize the transmit random backoff seed. */ + Value32 = (pDevice->NodeAddress[0] + pDevice->NodeAddress[1] + + pDevice->NodeAddress[2] + pDevice->NodeAddress[3] + + pDevice->NodeAddress[4] + pDevice->NodeAddress[5]) & + MAC_TX_BACKOFF_SEED_MASK; + REG_WR (pDevice, MacCtrl.TxBackoffSeed, Value32); - /* Receive MTU. Frames larger than the MTU is marked as oversized. */ - REG_WR(pDevice, MacCtrl.MtuSize, pDevice->RxMtu + 8); /* CRC + VLAN. */ + /* Receive MTU. Frames larger than the MTU is marked as oversized. */ + REG_WR (pDevice, MacCtrl.MtuSize, pDevice->RxMtu + 8); /* CRC + VLAN. */ - /* Configure Time slot/IPG per 802.3 */ - REG_WR(pDevice, MacCtrl.TxLengths, 0x2620); + /* Configure Time slot/IPG per 802.3 */ + REG_WR (pDevice, MacCtrl.TxLengths, 0x2620); - /* - * Configure Receive Rules so that packets don't match - * Programmble rule will be queued to Return Ring 1 - */ - REG_WR(pDevice, MacCtrl.RcvRuleCfg, RX_RULE_DEFAULT_CLASS); + /* + * Configure Receive Rules so that packets don't match + * Programmble rule will be queued to Return Ring 1 + */ + REG_WR (pDevice, MacCtrl.RcvRuleCfg, RX_RULE_DEFAULT_CLASS); - /* - * Configure to have 16 Classes of Services (COS) and one - * queue per class. Bad frames are queued to RRR#1. - * And frames don't match rules are also queued to COS#1. - */ - REG_WR(pDevice, RcvListPlmt.Config, 0x181); + /* + * Configure to have 16 Classes of Services (COS) and one + * queue per class. Bad frames are queued to RRR#1. + * And frames don't match rules are also queued to COS#1. + */ + REG_WR (pDevice, RcvListPlmt.Config, 0x181); - /* Enable Receive Placement Statistics */ - REG_WR(pDevice, RcvListPlmt.StatsEnableMask,0xffffff); - REG_WR(pDevice, RcvListPlmt.StatsCtrl, RCV_LIST_STATS_ENABLE); + /* Enable Receive Placement Statistics */ + REG_WR (pDevice, RcvListPlmt.StatsEnableMask, 0xffffff); + REG_WR (pDevice, RcvListPlmt.StatsCtrl, RCV_LIST_STATS_ENABLE); - /* Enable Send Data Initator Statistics */ - REG_WR(pDevice, SndDataIn.StatsEnableMask,0xffffff); - REG_WR(pDevice, SndDataIn.StatsCtrl, - T3_SND_DATA_IN_STATS_CTRL_ENABLE | \ - T3_SND_DATA_IN_STATS_CTRL_FASTER_UPDATE); + /* Enable Send Data Initator Statistics */ + REG_WR (pDevice, SndDataIn.StatsEnableMask, 0xffffff); + REG_WR (pDevice, SndDataIn.StatsCtrl, + T3_SND_DATA_IN_STATS_CTRL_ENABLE | + T3_SND_DATA_IN_STATS_CTRL_FASTER_UPDATE); - /* Disable the host coalescing state machine before configuring it's */ - /* parameters. */ - REG_WR(pDevice, HostCoalesce.Mode, 0); - for(j = 0; j < 2000; j++) - { - Value32 = REG_RD(pDevice, HostCoalesce.Mode); - if(!(Value32 & HOST_COALESCE_ENABLE)) - { - break; + /* Disable the host coalescing state machine before configuring it's */ + /* parameters. */ + REG_WR (pDevice, HostCoalesce.Mode, 0); + for (j = 0; j < 2000; j++) { + Value32 = REG_RD (pDevice, HostCoalesce.Mode); + if (!(Value32 & HOST_COALESCE_ENABLE)) { + break; + } + MM_Wait (10); } - MM_Wait(10); - } - /* Host coalescing configurations. */ - REG_WR(pDevice, HostCoalesce.RxCoalescingTicks, pDevice->RxCoalescingTicks); - REG_WR(pDevice, HostCoalesce.TxCoalescingTicks, pDevice->TxCoalescingTicks); - REG_WR(pDevice, HostCoalesce.RxMaxCoalescedFrames, - pDevice->RxMaxCoalescedFrames); - REG_WR(pDevice, HostCoalesce.TxMaxCoalescedFrames, - pDevice->TxMaxCoalescedFrames); - REG_WR(pDevice, HostCoalesce.RxCoalescedTickDuringInt, - pDevice->RxCoalescingTicksDuringInt); - REG_WR(pDevice, HostCoalesce.TxCoalescedTickDuringInt, - pDevice->TxCoalescingTicksDuringInt); - REG_WR(pDevice, HostCoalesce.RxMaxCoalescedFramesDuringInt, - pDevice->RxMaxCoalescedFramesDuringInt); - REG_WR(pDevice, HostCoalesce.TxMaxCoalescedFramesDuringInt, - pDevice->TxMaxCoalescedFramesDuringInt); + /* Host coalescing configurations. */ + REG_WR (pDevice, HostCoalesce.RxCoalescingTicks, + pDevice->RxCoalescingTicks); + REG_WR (pDevice, HostCoalesce.TxCoalescingTicks, + pDevice->TxCoalescingTicks); + REG_WR (pDevice, HostCoalesce.RxMaxCoalescedFrames, + pDevice->RxMaxCoalescedFrames); + REG_WR (pDevice, HostCoalesce.TxMaxCoalescedFrames, + pDevice->TxMaxCoalescedFrames); + REG_WR (pDevice, HostCoalesce.RxCoalescedTickDuringInt, + pDevice->RxCoalescingTicksDuringInt); + REG_WR (pDevice, HostCoalesce.TxCoalescedTickDuringInt, + pDevice->TxCoalescingTicksDuringInt); + REG_WR (pDevice, HostCoalesce.RxMaxCoalescedFramesDuringInt, + pDevice->RxMaxCoalescedFramesDuringInt); + REG_WR (pDevice, HostCoalesce.TxMaxCoalescedFramesDuringInt, + pDevice->TxMaxCoalescedFramesDuringInt); - /* Initialize the address of the status block. The NIC will DMA */ - /* the status block to this memory which resides on the host. */ - REG_WR(pDevice, HostCoalesce.StatusBlkHostAddr.High, - pDevice->StatusBlkPhy.High); - REG_WR(pDevice, HostCoalesce.StatusBlkHostAddr.Low, - pDevice->StatusBlkPhy.Low); + /* Initialize the address of the status block. The NIC will DMA */ + /* the status block to this memory which resides on the host. */ + REG_WR (pDevice, HostCoalesce.StatusBlkHostAddr.High, + pDevice->StatusBlkPhy.High); + REG_WR (pDevice, HostCoalesce.StatusBlkHostAddr.Low, + pDevice->StatusBlkPhy.Low); - /* Initialize the address of the statistics block. The NIC will DMA */ - /* the statistics to this block of memory. */ - REG_WR(pDevice, HostCoalesce.StatsBlkHostAddr.High, - pDevice->StatsBlkPhy.High); - REG_WR(pDevice, HostCoalesce.StatsBlkHostAddr.Low, - pDevice->StatsBlkPhy.Low); + /* Initialize the address of the statistics block. The NIC will DMA */ + /* the statistics to this block of memory. */ + REG_WR (pDevice, HostCoalesce.StatsBlkHostAddr.High, + pDevice->StatsBlkPhy.High); + REG_WR (pDevice, HostCoalesce.StatsBlkHostAddr.Low, + pDevice->StatsBlkPhy.Low); - REG_WR(pDevice, HostCoalesce.StatsCoalescingTicks, - pDevice->StatsCoalescingTicks); + REG_WR (pDevice, HostCoalesce.StatsCoalescingTicks, + pDevice->StatsCoalescingTicks); - REG_WR(pDevice, HostCoalesce.StatsBlkNicAddr, 0x300); - REG_WR(pDevice, HostCoalesce.StatusBlkNicAddr,0xb00); + REG_WR (pDevice, HostCoalesce.StatsBlkNicAddr, 0x300); + REG_WR (pDevice, HostCoalesce.StatusBlkNicAddr, 0xb00); - /* Enable Host Coalesing state machine */ - REG_WR(pDevice, HostCoalesce.Mode, HOST_COALESCE_ENABLE | - pDevice->CoalesceMode); + /* Enable Host Coalesing state machine */ + REG_WR (pDevice, HostCoalesce.Mode, HOST_COALESCE_ENABLE | + pDevice->CoalesceMode); - /* Enable the Receive BD Completion state machine. */ - REG_WR(pDevice, RcvBdComp.Mode, RCV_BD_COMP_MODE_ENABLE | - RCV_BD_COMP_MODE_ATTN_ENABLE); + /* Enable the Receive BD Completion state machine. */ + REG_WR (pDevice, RcvBdComp.Mode, RCV_BD_COMP_MODE_ENABLE | + RCV_BD_COMP_MODE_ATTN_ENABLE); - /* Enable the Receive List Placement state machine. */ - REG_WR(pDevice, RcvListPlmt.Mode, RCV_LIST_PLMT_MODE_ENABLE); + /* Enable the Receive List Placement state machine. */ + REG_WR (pDevice, RcvListPlmt.Mode, RCV_LIST_PLMT_MODE_ENABLE); - /* Enable the Receive List Selector state machine. */ - REG_WR(pDevice, RcvListSel.Mode, RCV_LIST_SEL_MODE_ENABLE | - RCV_LIST_SEL_MODE_ATTN_ENABLE); + /* Enable the Receive List Selector state machine. */ + REG_WR (pDevice, RcvListSel.Mode, RCV_LIST_SEL_MODE_ENABLE | + RCV_LIST_SEL_MODE_ATTN_ENABLE); - /* Enable transmit DMA, clear statistics. */ - pDevice->MacMode = MAC_MODE_ENABLE_TX_STATISTICS | - MAC_MODE_ENABLE_RX_STATISTICS | MAC_MODE_ENABLE_TDE | - MAC_MODE_ENABLE_RDE | MAC_MODE_ENABLE_FHDE; - REG_WR(pDevice, MacCtrl.Mode, pDevice->MacMode | - MAC_MODE_CLEAR_RX_STATISTICS | MAC_MODE_CLEAR_TX_STATISTICS); + /* Enable transmit DMA, clear statistics. */ + pDevice->MacMode = MAC_MODE_ENABLE_TX_STATISTICS | + MAC_MODE_ENABLE_RX_STATISTICS | MAC_MODE_ENABLE_TDE | + MAC_MODE_ENABLE_RDE | MAC_MODE_ENABLE_FHDE; + REG_WR (pDevice, MacCtrl.Mode, pDevice->MacMode | + MAC_MODE_CLEAR_RX_STATISTICS | MAC_MODE_CLEAR_TX_STATISTICS); - /* GRC miscellaneous local control register. */ - pDevice->GrcLocalCtrl = GRC_MISC_LOCAL_CTRL_INT_ON_ATTN | - GRC_MISC_LOCAL_CTRL_AUTO_SEEPROM; + /* GRC miscellaneous local control register. */ + pDevice->GrcLocalCtrl = GRC_MISC_LOCAL_CTRL_INT_ON_ATTN | + GRC_MISC_LOCAL_CTRL_AUTO_SEEPROM; - if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700) - { - pDevice->GrcLocalCtrl |= GRC_MISC_LOCAL_CTRL_GPIO_OE1 | - GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT1; - } - - REG_WR(pDevice, Grc.LocalCtrl, pDevice->GrcLocalCtrl); - MM_Wait(40); - - /* Reset RX counters. */ - for(j = 0; j < sizeof(LM_RX_COUNTERS); j++) - { - ((PLM_UINT8) &pDevice->RxCounters)[j] = 0; - } - - /* Reset TX counters. */ - for(j = 0; j < sizeof(LM_TX_COUNTERS); j++) - { - ((PLM_UINT8) &pDevice->TxCounters)[j] = 0; - } - - MB_REG_WR(pDevice, Mailbox.Interrupt[0].Low, 0); - - /* Enable the DMA Completion state machine. */ - REG_WR(pDevice, DmaComp.Mode, DMA_COMP_MODE_ENABLE); - - /* Enable the DMA Write state machine. */ - Value32 = DMA_WRITE_MODE_ENABLE | - DMA_WRITE_MODE_TARGET_ABORT_ATTN_ENABLE | - DMA_WRITE_MODE_MASTER_ABORT_ATTN_ENABLE | - DMA_WRITE_MODE_PARITY_ERROR_ATTN_ENABLE | - DMA_WRITE_MODE_ADDR_OVERFLOW_ATTN_ENABLE | - DMA_WRITE_MODE_FIFO_OVERRUN_ATTN_ENABLE | - DMA_WRITE_MODE_FIFO_UNDERRUN_ATTN_ENABLE | - DMA_WRITE_MODE_FIFO_OVERREAD_ATTN_ENABLE | - DMA_WRITE_MODE_LONG_READ_ATTN_ENABLE; - REG_WR(pDevice, DmaWrite.Mode, Value32); - - if (!(pDevice->PciState & T3_PCI_STATE_CONVENTIONAL_PCI_MODE)) - { - if (pDevice->ChipRevId == T3_CHIP_ID_5704_A0) - { - Value16 = REG_RD(pDevice, PciCfg.PciXCommand); - Value16 &= ~(PCIX_CMD_MAX_SPLIT_MASK | PCIX_CMD_MAX_BURST_MASK); - Value16 |= ((PCIX_CMD_MAX_BURST_CPIOB << PCIX_CMD_MAX_BURST_SHL) & - PCIX_CMD_MAX_BURST_MASK); - if (pDevice->SplitModeEnable == SPLIT_MODE_ENABLE) - { - Value16 |= (pDevice->SplitModeMaxReq << PCIX_CMD_MAX_SPLIT_SHL) - & PCIX_CMD_MAX_SPLIT_MASK; - } - REG_WR(pDevice, PciCfg.PciXCommand, Value16); + if (T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5700) { + pDevice->GrcLocalCtrl |= GRC_MISC_LOCAL_CTRL_GPIO_OE1 | + GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT1; } - } - /* Enable the Read DMA state machine. */ - Value32 = DMA_READ_MODE_ENABLE | - DMA_READ_MODE_TARGET_ABORT_ATTN_ENABLE | - DMA_READ_MODE_MASTER_ABORT_ATTN_ENABLE | - DMA_READ_MODE_PARITY_ERROR_ATTN_ENABLE | - DMA_READ_MODE_ADDR_OVERFLOW_ATTN_ENABLE | - DMA_READ_MODE_FIFO_OVERRUN_ATTN_ENABLE | - DMA_READ_MODE_FIFO_UNDERRUN_ATTN_ENABLE | - DMA_READ_MODE_FIFO_OVERREAD_ATTN_ENABLE | - DMA_READ_MODE_LONG_READ_ATTN_ENABLE; + REG_WR (pDevice, Grc.LocalCtrl, pDevice->GrcLocalCtrl); + MM_Wait (40); - if (pDevice->SplitModeEnable == SPLIT_MODE_ENABLE) - { - Value32 |= DMA_READ_MODE_SPLIT_ENABLE; - } - REG_WR(pDevice, DmaRead.Mode, Value32); + /* Reset RX counters. */ + for (j = 0; j < sizeof (LM_RX_COUNTERS); j++) { + ((PLM_UINT8) & pDevice->RxCounters)[j] = 0; + } - /* Enable the Receive Data Completion state machine. */ - REG_WR(pDevice, RcvDataComp.Mode, RCV_DATA_COMP_MODE_ENABLE | - RCV_DATA_COMP_MODE_ATTN_ENABLE); + /* Reset TX counters. */ + for (j = 0; j < sizeof (LM_TX_COUNTERS); j++) { + ((PLM_UINT8) & pDevice->TxCounters)[j] = 0; + } - /* Enable the Mbuf Cluster Free state machine. */ - REG_WR(pDevice, MbufClusterFree.Mode, MBUF_CLUSTER_FREE_MODE_ENABLE); + MB_REG_WR (pDevice, Mailbox.Interrupt[0].Low, 0); - /* Enable the Send Data Completion state machine. */ - REG_WR(pDevice, SndDataComp.Mode, SND_DATA_COMP_MODE_ENABLE); + /* Enable the DMA Completion state machine. */ + REG_WR (pDevice, DmaComp.Mode, DMA_COMP_MODE_ENABLE); - /* Enable the Send BD Completion state machine. */ - REG_WR(pDevice, SndBdComp.Mode, SND_BD_COMP_MODE_ENABLE | - SND_BD_COMP_MODE_ATTN_ENABLE); + /* Enable the DMA Write state machine. */ + Value32 = DMA_WRITE_MODE_ENABLE | + DMA_WRITE_MODE_TARGET_ABORT_ATTN_ENABLE | + DMA_WRITE_MODE_MASTER_ABORT_ATTN_ENABLE | + DMA_WRITE_MODE_PARITY_ERROR_ATTN_ENABLE | + DMA_WRITE_MODE_ADDR_OVERFLOW_ATTN_ENABLE | + DMA_WRITE_MODE_FIFO_OVERRUN_ATTN_ENABLE | + DMA_WRITE_MODE_FIFO_UNDERRUN_ATTN_ENABLE | + DMA_WRITE_MODE_FIFO_OVERREAD_ATTN_ENABLE | + DMA_WRITE_MODE_LONG_READ_ATTN_ENABLE; + REG_WR (pDevice, DmaWrite.Mode, Value32); - /* Enable the Receive BD Initiator state machine. */ - REG_WR(pDevice, RcvBdIn.Mode, RCV_BD_IN_MODE_ENABLE | - RCV_BD_IN_MODE_BD_IN_DIABLED_RCB_ATTN_ENABLE); + if (!(pDevice->PciState & T3_PCI_STATE_CONVENTIONAL_PCI_MODE)) { + if (pDevice->ChipRevId == T3_CHIP_ID_5704_A0) { + Value16 = REG_RD (pDevice, PciCfg.PciXCommand); + Value16 &= + ~(PCIX_CMD_MAX_SPLIT_MASK | + PCIX_CMD_MAX_BURST_MASK); + Value16 |= + ((PCIX_CMD_MAX_BURST_CPIOB << + PCIX_CMD_MAX_BURST_SHL) & + PCIX_CMD_MAX_BURST_MASK); + if (pDevice->SplitModeEnable == SPLIT_MODE_ENABLE) { + Value16 |= + (pDevice-> + SplitModeMaxReq << PCIX_CMD_MAX_SPLIT_SHL) + & PCIX_CMD_MAX_SPLIT_MASK; + } + REG_WR (pDevice, PciCfg.PciXCommand, Value16); + } + } - /* Enable the Receive Data and Receive BD Initiator state machine. */ - REG_WR(pDevice, RcvDataBdIn.Mode, RCV_DATA_BD_IN_MODE_ENABLE | - RCV_DATA_BD_IN_MODE_INVALID_RING_SIZE); + /* Enable the Read DMA state machine. */ + Value32 = DMA_READ_MODE_ENABLE | + DMA_READ_MODE_TARGET_ABORT_ATTN_ENABLE | + DMA_READ_MODE_MASTER_ABORT_ATTN_ENABLE | + DMA_READ_MODE_PARITY_ERROR_ATTN_ENABLE | + DMA_READ_MODE_ADDR_OVERFLOW_ATTN_ENABLE | + DMA_READ_MODE_FIFO_OVERRUN_ATTN_ENABLE | + DMA_READ_MODE_FIFO_UNDERRUN_ATTN_ENABLE | + DMA_READ_MODE_FIFO_OVERREAD_ATTN_ENABLE | + DMA_READ_MODE_LONG_READ_ATTN_ENABLE; - /* Enable the Send Data Initiator state machine. */ - REG_WR(pDevice, SndDataIn.Mode, T3_SND_DATA_IN_MODE_ENABLE); + if (pDevice->SplitModeEnable == SPLIT_MODE_ENABLE) { + Value32 |= DMA_READ_MODE_SPLIT_ENABLE; + } + REG_WR (pDevice, DmaRead.Mode, Value32); - /* Enable the Send BD Initiator state machine. */ - REG_WR(pDevice, SndBdIn.Mode, SND_BD_IN_MODE_ENABLE | - SND_BD_IN_MODE_ATTN_ENABLE); + /* Enable the Receive Data Completion state machine. */ + REG_WR (pDevice, RcvDataComp.Mode, RCV_DATA_COMP_MODE_ENABLE | + RCV_DATA_COMP_MODE_ATTN_ENABLE); - /* Enable the Send BD Selector state machine. */ - REG_WR(pDevice, SndBdSel.Mode, SND_BD_SEL_MODE_ENABLE | - SND_BD_SEL_MODE_ATTN_ENABLE); + /* Enable the Mbuf Cluster Free state machine. */ + REG_WR (pDevice, MbufClusterFree.Mode, MBUF_CLUSTER_FREE_MODE_ENABLE); + + /* Enable the Send Data Completion state machine. */ + REG_WR (pDevice, SndDataComp.Mode, SND_DATA_COMP_MODE_ENABLE); + + /* Enable the Send BD Completion state machine. */ + REG_WR (pDevice, SndBdComp.Mode, SND_BD_COMP_MODE_ENABLE | + SND_BD_COMP_MODE_ATTN_ENABLE); + + /* Enable the Receive BD Initiator state machine. */ + REG_WR (pDevice, RcvBdIn.Mode, RCV_BD_IN_MODE_ENABLE | + RCV_BD_IN_MODE_BD_IN_DIABLED_RCB_ATTN_ENABLE); + + /* Enable the Receive Data and Receive BD Initiator state machine. */ + REG_WR (pDevice, RcvDataBdIn.Mode, RCV_DATA_BD_IN_MODE_ENABLE | + RCV_DATA_BD_IN_MODE_INVALID_RING_SIZE); + + /* Enable the Send Data Initiator state machine. */ + REG_WR (pDevice, SndDataIn.Mode, T3_SND_DATA_IN_MODE_ENABLE); + + /* Enable the Send BD Initiator state machine. */ + REG_WR (pDevice, SndBdIn.Mode, SND_BD_IN_MODE_ENABLE | + SND_BD_IN_MODE_ATTN_ENABLE); + + /* Enable the Send BD Selector state machine. */ + REG_WR (pDevice, SndBdSel.Mode, SND_BD_SEL_MODE_ENABLE | + SND_BD_SEL_MODE_ATTN_ENABLE); #if INCLUDE_5701_AX_FIX - /* Load the firmware for the 5701_A0 workaround. */ - if(pDevice->ChipRevId == T3_CHIP_ID_5701_A0) - { - LM_LoadRlsFirmware(pDevice); - } + /* Load the firmware for the 5701_A0 workaround. */ + if (pDevice->ChipRevId == T3_CHIP_ID_5701_A0) { + LM_LoadRlsFirmware (pDevice); + } #endif - /* Enable the transmitter. */ - pDevice->TxMode = TX_MODE_ENABLE; - REG_WR(pDevice, MacCtrl.TxMode, pDevice->TxMode); + /* Enable the transmitter. */ + pDevice->TxMode = TX_MODE_ENABLE; + REG_WR (pDevice, MacCtrl.TxMode, pDevice->TxMode); - /* Enable the receiver. */ - pDevice->RxMode = RX_MODE_ENABLE; - REG_WR(pDevice, MacCtrl.RxMode, pDevice->RxMode); + /* Enable the receiver. */ + pDevice->RxMode = RX_MODE_ENABLE; + REG_WR (pDevice, MacCtrl.RxMode, pDevice->RxMode); - if (pDevice->RestoreOnWakeUp) - { - pDevice->RestoreOnWakeUp = FALSE; - pDevice->DisableAutoNeg = pDevice->WakeUpDisableAutoNeg; - pDevice->RequestedMediaType = pDevice->WakeUpRequestedMediaType; - } - - /* Disable auto polling. */ - pDevice->MiMode = 0xc0000; - REG_WR(pDevice, MacCtrl.MiMode, pDevice->MiMode); - - if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700 || - T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5701) - { - Value32 = LED_CTRL_PHY_MODE_1; - } - else - { - if(pDevice->LedMode == LED_MODE_OUTPUT) - { - Value32 = LED_CTRL_PHY_MODE_2; + if (pDevice->RestoreOnWakeUp) { + pDevice->RestoreOnWakeUp = FALSE; + pDevice->DisableAutoNeg = pDevice->WakeUpDisableAutoNeg; + pDevice->RequestedMediaType = pDevice->WakeUpRequestedMediaType; } - else - { - Value32 = LED_CTRL_PHY_MODE_1; + + /* Disable auto polling. */ + pDevice->MiMode = 0xc0000; + REG_WR (pDevice, MacCtrl.MiMode, pDevice->MiMode); + + if (T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5700 || + T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5701) { + Value32 = LED_CTRL_PHY_MODE_1; + } else { + if (pDevice->LedMode == LED_MODE_OUTPUT) { + Value32 = LED_CTRL_PHY_MODE_2; + } else { + Value32 = LED_CTRL_PHY_MODE_1; + } } - } - REG_WR(pDevice, MacCtrl.LedCtrl, Value32); + REG_WR (pDevice, MacCtrl.LedCtrl, Value32); - /* Activate Link to enable MAC state machine */ - REG_WR(pDevice, MacCtrl.MiStatus, MI_STATUS_ENABLE_LINK_STATUS_ATTN); + /* Activate Link to enable MAC state machine */ + REG_WR (pDevice, MacCtrl.MiStatus, MI_STATUS_ENABLE_LINK_STATUS_ATTN); - if (pDevice->EnableTbi) - { - REG_WR(pDevice, MacCtrl.RxMode, RX_MODE_RESET); - MM_Wait(10); - REG_WR(pDevice, MacCtrl.RxMode, pDevice->RxMode); - if (pDevice->ChipRevId == T3_CHIP_ID_5703_A1) - { - REG_WR(pDevice, MacCtrl.SerdesCfg, 0x616000); + if (pDevice->EnableTbi) { + REG_WR (pDevice, MacCtrl.RxMode, RX_MODE_RESET); + MM_Wait (10); + REG_WR (pDevice, MacCtrl.RxMode, pDevice->RxMode); + if (pDevice->ChipRevId == T3_CHIP_ID_5703_A1) { + REG_WR (pDevice, MacCtrl.SerdesCfg, 0x616000); + } } - } - /* Setup the phy chip. */ - LM_SetupPhy(pDevice); + /* Setup the phy chip. */ + LM_SetupPhy (pDevice); - if (!pDevice->EnableTbi) { - /* Clear CRC stats */ - LM_ReadPhy(pDevice, 0x1e, &Value32); - LM_WritePhy(pDevice, 0x1e, Value32 | 0x8000); - LM_ReadPhy(pDevice, 0x14, &Value32); - } + if (!pDevice->EnableTbi) { + /* Clear CRC stats */ + LM_ReadPhy (pDevice, 0x1e, &Value32); + LM_WritePhy (pDevice, 0x1e, Value32 | 0x8000); + LM_ReadPhy (pDevice, 0x14, &Value32); + } - /* Set up the receive mask. */ - LM_SetReceiveMask(pDevice, pDevice->ReceiveMask); + /* Set up the receive mask. */ + LM_SetReceiveMask (pDevice, pDevice->ReceiveMask); - /* Queue Rx packet buffers. */ - if(pDevice->QueueRxPackets) - { - LM_QueueRxPackets(pDevice); - } + /* Queue Rx packet buffers. */ + if (pDevice->QueueRxPackets) { + LM_QueueRxPackets (pDevice); + } - /* Enable interrupt to the host. */ - if(pDevice->InitDone) - { - LM_EnableInterrupt(pDevice); - } - - return LM_STATUS_SUCCESS; -} /* LM_ResetAdapter */ + /* Enable interrupt to the host. */ + if (pDevice->InitDone) { + LM_EnableInterrupt (pDevice); + } + return LM_STATUS_SUCCESS; +} /* LM_ResetAdapter */ /******************************************************************************/ /* Description: */ @@ -2979,18 +2762,15 @@ PLM_DEVICE_BLOCK pDevice) /* Return: */ /* LM_STATUS_SUCCESS */ /******************************************************************************/ -LM_STATUS -LM_DisableInterrupt( - PLM_DEVICE_BLOCK pDevice) +LM_STATUS LM_DisableInterrupt (PLM_DEVICE_BLOCK pDevice) { - REG_WR(pDevice, PciCfg.MiscHostCtrl, pDevice->MiscHostCtrl | - MISC_HOST_CTRL_MASK_PCI_INT); - MB_REG_WR(pDevice, Mailbox.Interrupt[0].Low, 1); + REG_WR (pDevice, PciCfg.MiscHostCtrl, pDevice->MiscHostCtrl | + MISC_HOST_CTRL_MASK_PCI_INT); + MB_REG_WR (pDevice, Mailbox.Interrupt[0].Low, 1); - return LM_STATUS_SUCCESS; + return LM_STATUS_SUCCESS; } - /******************************************************************************/ /* Description: */ /* This routine enables the adapter to generate interrupts. */ @@ -2998,24 +2778,20 @@ LM_DisableInterrupt( /* Return: */ /* LM_STATUS_SUCCESS */ /******************************************************************************/ -LM_STATUS -LM_EnableInterrupt( - PLM_DEVICE_BLOCK pDevice) +LM_STATUS LM_EnableInterrupt (PLM_DEVICE_BLOCK pDevice) { - REG_WR(pDevice, PciCfg.MiscHostCtrl, pDevice->MiscHostCtrl & - ~MISC_HOST_CTRL_MASK_PCI_INT); - MB_REG_WR(pDevice, Mailbox.Interrupt[0].Low, 0); + REG_WR (pDevice, PciCfg.MiscHostCtrl, pDevice->MiscHostCtrl & + ~MISC_HOST_CTRL_MASK_PCI_INT); + MB_REG_WR (pDevice, Mailbox.Interrupt[0].Low, 0); - if(pDevice->pStatusBlkVirt->Status & STATUS_BLOCK_UPDATED) - { - REG_WR(pDevice, Grc.LocalCtrl, pDevice->GrcLocalCtrl | - GRC_MISC_LOCAL_CTRL_SET_INT); - } + if (pDevice->pStatusBlkVirt->Status & STATUS_BLOCK_UPDATED) { + REG_WR (pDevice, Grc.LocalCtrl, pDevice->GrcLocalCtrl | + GRC_MISC_LOCAL_CTRL_SET_INT); + } - return LM_STATUS_SUCCESS; + return LM_STATUS_SUCCESS; } - /******************************************************************************/ /* Description: */ /* This routine puts a packet on the wire if there is a transmit DMA */ @@ -3027,306 +2803,279 @@ LM_EnableInterrupt( /* LM_STATUS_SUCCESS */ /******************************************************************************/ #if 0 -LM_STATUS -LM_SendPacket(PLM_DEVICE_BLOCK pDevice, PLM_PACKET pPacket) +LM_STATUS LM_SendPacket (PLM_DEVICE_BLOCK pDevice, PLM_PACKET pPacket) { - LM_UINT32 FragCount; - PT3_SND_BD pSendBd; - PT3_SND_BD pShadowSendBd; - LM_UINT32 Value32, Len; - LM_UINT32 Idx; + LM_UINT32 FragCount; + PT3_SND_BD pSendBd; + PT3_SND_BD pShadowSendBd; + LM_UINT32 Value32, Len; + LM_UINT32 Idx; - if (T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700) { - return LM_5700SendPacket(pDevice, pPacket); - } + if (T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5700) { + return LM_5700SendPacket (pDevice, pPacket); + } - /* Update the SendBdLeft count. */ - atomic_sub(pPacket->u.Tx.FragCount, &pDevice->SendBdLeft); + /* Update the SendBdLeft count. */ + atomic_sub (pPacket->u.Tx.FragCount, &pDevice->SendBdLeft); - /* Initalize the send buffer descriptors. */ - Idx = pDevice->SendProdIdx; + /* Initalize the send buffer descriptors. */ + Idx = pDevice->SendProdIdx; - pSendBd = &pDevice->pSendBdVirt[Idx]; + pSendBd = &pDevice->pSendBdVirt[Idx]; - /* Next producer index. */ - if (pDevice->NicSendBd == TRUE) - { - T3_64BIT_HOST_ADDR paddr; + /* Next producer index. */ + if (pDevice->NicSendBd == TRUE) { + T3_64BIT_HOST_ADDR paddr; - pShadowSendBd = &pDevice->ShadowSendBd[Idx]; - for(FragCount = 0; ; ) - { - MM_MapTxDma(pDevice, pPacket, &paddr, &Len, FragCount); - /* Initialize the pointer to the send buffer fragment. */ - if (paddr.High != pShadowSendBd->HostAddr.High) - { - __raw_writel(paddr.High, &(pSendBd->HostAddr.High)); - pShadowSendBd->HostAddr.High = paddr.High; - } - __raw_writel(paddr.Low, &(pSendBd->HostAddr.Low)); + pShadowSendBd = &pDevice->ShadowSendBd[Idx]; + for (FragCount = 0;;) { + MM_MapTxDma (pDevice, pPacket, &paddr, &Len, FragCount); + /* Initialize the pointer to the send buffer fragment. */ + if (paddr.High != pShadowSendBd->HostAddr.High) { + __raw_writel (paddr.High, + &(pSendBd->HostAddr.High)); + pShadowSendBd->HostAddr.High = paddr.High; + } + __raw_writel (paddr.Low, &(pSendBd->HostAddr.Low)); - /* Setup the control flags and send buffer size. */ - Value32 = (Len << 16) | pPacket->Flags; + /* Setup the control flags and send buffer size. */ + Value32 = (Len << 16) | pPacket->Flags; - Idx = (Idx + 1) & T3_SEND_RCB_ENTRY_COUNT_MASK; + Idx = (Idx + 1) & T3_SEND_RCB_ENTRY_COUNT_MASK; - FragCount++; - if (FragCount >= pPacket->u.Tx.FragCount) - { - Value32 |= SND_BD_FLAG_END; - if (Value32 != pShadowSendBd->u1.Len_Flags) - { - __raw_writel(Value32, &(pSendBd->u1.Len_Flags)); - pShadowSendBd->u1.Len_Flags = Value32; - } - if (pPacket->Flags & SND_BD_FLAG_VLAN_TAG) { - __raw_writel(pPacket->VlanTag, &(pSendBd->u2.VlanTag)); - } - break; - } - else - { - if (Value32 != pShadowSendBd->u1.Len_Flags) - { - __raw_writel(Value32, &(pSendBd->u1.Len_Flags)); - pShadowSendBd->u1.Len_Flags = Value32; - } - if (pPacket->Flags & SND_BD_FLAG_VLAN_TAG) { - __raw_writel(pPacket->VlanTag, &(pSendBd->u2.VlanTag)); - } - } + FragCount++; + if (FragCount >= pPacket->u.Tx.FragCount) { + Value32 |= SND_BD_FLAG_END; + if (Value32 != pShadowSendBd->u1.Len_Flags) { + __raw_writel (Value32, + &(pSendBd->u1.Len_Flags)); + pShadowSendBd->u1.Len_Flags = Value32; + } + if (pPacket->Flags & SND_BD_FLAG_VLAN_TAG) { + __raw_writel (pPacket->VlanTag, + &(pSendBd->u2.VlanTag)); + } + break; + } else { + if (Value32 != pShadowSendBd->u1.Len_Flags) { + __raw_writel (Value32, + &(pSendBd->u1.Len_Flags)); + pShadowSendBd->u1.Len_Flags = Value32; + } + if (pPacket->Flags & SND_BD_FLAG_VLAN_TAG) { + __raw_writel (pPacket->VlanTag, + &(pSendBd->u2.VlanTag)); + } + } - pSendBd++; - pShadowSendBd++; - if (Idx == 0) - { - pSendBd = &pDevice->pSendBdVirt[0]; - pShadowSendBd = &pDevice->ShadowSendBd[0]; - } - } /* for */ + pSendBd++; + pShadowSendBd++; + if (Idx == 0) { + pSendBd = &pDevice->pSendBdVirt[0]; + pShadowSendBd = &pDevice->ShadowSendBd[0]; + } + } /* for */ - /* Put the packet descriptor in the ActiveQ. */ - QQ_PushTail(&pDevice->TxPacketActiveQ.Container, pPacket); + /* Put the packet descriptor in the ActiveQ. */ + QQ_PushTail (&pDevice->TxPacketActiveQ.Container, pPacket); - wmb(); - MB_REG_WR(pDevice, Mailbox.SendNicProdIdx[0].Low, Idx); + wmb (); + MB_REG_WR (pDevice, Mailbox.SendNicProdIdx[0].Low, Idx); - } - else - { - for(FragCount = 0; ; ) - { - /* Initialize the pointer to the send buffer fragment. */ - MM_MapTxDma(pDevice, pPacket, &pSendBd->HostAddr, &Len, FragCount); + } else { + for (FragCount = 0;;) { + /* Initialize the pointer to the send buffer fragment. */ + MM_MapTxDma (pDevice, pPacket, &pSendBd->HostAddr, &Len, + FragCount); - pSendBd->u2.VlanTag = pPacket->VlanTag; + pSendBd->u2.VlanTag = pPacket->VlanTag; - /* Setup the control flags and send buffer size. */ - Value32 = (Len << 16) | pPacket->Flags; + /* Setup the control flags and send buffer size. */ + Value32 = (Len << 16) | pPacket->Flags; - Idx = (Idx + 1) & T3_SEND_RCB_ENTRY_COUNT_MASK; + Idx = (Idx + 1) & T3_SEND_RCB_ENTRY_COUNT_MASK; - FragCount++; - if (FragCount >= pPacket->u.Tx.FragCount) - { - pSendBd->u1.Len_Flags = Value32 | SND_BD_FLAG_END; - break; - } - else - { - pSendBd->u1.Len_Flags = Value32; - } - pSendBd++; - if (Idx == 0) - { - pSendBd = &pDevice->pSendBdVirt[0]; - } - } /* for */ + FragCount++; + if (FragCount >= pPacket->u.Tx.FragCount) { + pSendBd->u1.Len_Flags = + Value32 | SND_BD_FLAG_END; + break; + } else { + pSendBd->u1.Len_Flags = Value32; + } + pSendBd++; + if (Idx == 0) { + pSendBd = &pDevice->pSendBdVirt[0]; + } + } /* for */ - /* Put the packet descriptor in the ActiveQ. */ - QQ_PushTail(&pDevice->TxPacketActiveQ.Container, pPacket); + /* Put the packet descriptor in the ActiveQ. */ + QQ_PushTail (&pDevice->TxPacketActiveQ.Container, pPacket); - wmb(); - MB_REG_WR(pDevice, Mailbox.SendHostProdIdx[0].Low, Idx); + wmb (); + MB_REG_WR (pDevice, Mailbox.SendHostProdIdx[0].Low, Idx); - } + } - /* Update the producer index. */ - pDevice->SendProdIdx = Idx; + /* Update the producer index. */ + pDevice->SendProdIdx = Idx; - return LM_STATUS_SUCCESS; + return LM_STATUS_SUCCESS; } #endif -LM_STATUS -LM_SendPacket(PLM_DEVICE_BLOCK pDevice, PLM_PACKET pPacket) +LM_STATUS LM_SendPacket (PLM_DEVICE_BLOCK pDevice, PLM_PACKET pPacket) { - LM_UINT32 FragCount; - PT3_SND_BD pSendBd, pTmpSendBd, pShadowSendBd; - T3_SND_BD NicSendBdArr[MAX_FRAGMENT_COUNT]; - LM_UINT32 StartIdx, Idx; + LM_UINT32 FragCount; + PT3_SND_BD pSendBd, pTmpSendBd, pShadowSendBd; + T3_SND_BD NicSendBdArr[MAX_FRAGMENT_COUNT]; + LM_UINT32 StartIdx, Idx; - while (1) - { - /* Initalize the send buffer descriptors. */ - StartIdx = Idx = pDevice->SendProdIdx; + while (1) { + /* Initalize the send buffer descriptors. */ + StartIdx = Idx = pDevice->SendProdIdx; - if (pDevice->NicSendBd) - { - pTmpSendBd = pSendBd = &NicSendBdArr[0]; - } - else - { - pTmpSendBd = pSendBd = &pDevice->pSendBdVirt[Idx]; - } - - /* Next producer index. */ - for(FragCount = 0; ; ) - { - LM_UINT32 Value32, Len; - - /* Initialize the pointer to the send buffer fragment. */ - MM_MapTxDma(pDevice, pPacket, &pSendBd->HostAddr, &Len, FragCount); - - pSendBd->u2.VlanTag = pPacket->VlanTag; - - /* Setup the control flags and send buffer size. */ - Value32 = (Len << 16) | pPacket->Flags; - - Idx = (Idx + 1) & T3_SEND_RCB_ENTRY_COUNT_MASK; - - FragCount++; - if (FragCount >= pPacket->u.Tx.FragCount) - { - pSendBd->u1.Len_Flags = Value32 | SND_BD_FLAG_END; - break; - } - else - { - pSendBd->u1.Len_Flags = Value32; - } - pSendBd++; - if ((Idx == 0) && !pDevice->NicSendBd) - { - pSendBd = &pDevice->pSendBdVirt[0]; - } - } /* for */ - if (T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700) - { - if (LM_Test4GBoundary(pDevice, pPacket, pTmpSendBd) == - LM_STATUS_SUCCESS) - { - if (MM_CoalesceTxBuffer(pDevice, pPacket) != LM_STATUS_SUCCESS) - { - QQ_PushHead(&pDevice->TxPacketFreeQ.Container, pPacket); - return LM_STATUS_FAILURE; + if (pDevice->NicSendBd) { + pTmpSendBd = pSendBd = &NicSendBdArr[0]; + } else { + pTmpSendBd = pSendBd = &pDevice->pSendBdVirt[Idx]; } - continue; - } + + /* Next producer index. */ + for (FragCount = 0;;) { + LM_UINT32 Value32, Len; + + /* Initialize the pointer to the send buffer fragment. */ + MM_MapTxDma (pDevice, pPacket, &pSendBd->HostAddr, &Len, + FragCount); + + pSendBd->u2.VlanTag = pPacket->VlanTag; + + /* Setup the control flags and send buffer size. */ + Value32 = (Len << 16) | pPacket->Flags; + + Idx = (Idx + 1) & T3_SEND_RCB_ENTRY_COUNT_MASK; + + FragCount++; + if (FragCount >= pPacket->u.Tx.FragCount) { + pSendBd->u1.Len_Flags = + Value32 | SND_BD_FLAG_END; + break; + } else { + pSendBd->u1.Len_Flags = Value32; + } + pSendBd++; + if ((Idx == 0) && !pDevice->NicSendBd) { + pSendBd = &pDevice->pSendBdVirt[0]; + } + } /* for */ + if (T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5700) { + if (LM_Test4GBoundary (pDevice, pPacket, pTmpSendBd) == + LM_STATUS_SUCCESS) { + if (MM_CoalesceTxBuffer (pDevice, pPacket) != + LM_STATUS_SUCCESS) { + QQ_PushHead (&pDevice->TxPacketFreeQ. + Container, pPacket); + return LM_STATUS_FAILURE; + } + continue; + } + } + break; } - break; - } - /* Put the packet descriptor in the ActiveQ. */ - QQ_PushTail(&pDevice->TxPacketActiveQ.Container, pPacket); + /* Put the packet descriptor in the ActiveQ. */ + QQ_PushTail (&pDevice->TxPacketActiveQ.Container, pPacket); - if (pDevice->NicSendBd) - { - pSendBd = &pDevice->pSendBdVirt[StartIdx]; - pShadowSendBd = &pDevice->ShadowSendBd[StartIdx]; + if (pDevice->NicSendBd) { + pSendBd = &pDevice->pSendBdVirt[StartIdx]; + pShadowSendBd = &pDevice->ShadowSendBd[StartIdx]; - while (StartIdx != Idx) - { - LM_UINT32 Value32; + while (StartIdx != Idx) { + LM_UINT32 Value32; - if ((Value32 = pTmpSendBd->HostAddr.High) != - pShadowSendBd->HostAddr.High) - { - __raw_writel(Value32, &(pSendBd->HostAddr.High)); - pShadowSendBd->HostAddr.High = Value32; - } + if ((Value32 = pTmpSendBd->HostAddr.High) != + pShadowSendBd->HostAddr.High) { + __raw_writel (Value32, + &(pSendBd->HostAddr.High)); + pShadowSendBd->HostAddr.High = Value32; + } - __raw_writel(pTmpSendBd->HostAddr.Low, &(pSendBd->HostAddr.Low)); + __raw_writel (pTmpSendBd->HostAddr.Low, + &(pSendBd->HostAddr.Low)); - if ((Value32 = pTmpSendBd->u1.Len_Flags) != - pShadowSendBd->u1.Len_Flags) - { - __raw_writel(Value32, &(pSendBd->u1.Len_Flags)); - pShadowSendBd->u1.Len_Flags = Value32; - } + if ((Value32 = pTmpSendBd->u1.Len_Flags) != + pShadowSendBd->u1.Len_Flags) { + __raw_writel (Value32, + &(pSendBd->u1.Len_Flags)); + pShadowSendBd->u1.Len_Flags = Value32; + } - if (pPacket->Flags & SND_BD_FLAG_VLAN_TAG) - { - __raw_writel(pTmpSendBd->u2.VlanTag, &(pSendBd->u2.VlanTag)); - } + if (pPacket->Flags & SND_BD_FLAG_VLAN_TAG) { + __raw_writel (pTmpSendBd->u2.VlanTag, + &(pSendBd->u2.VlanTag)); + } - StartIdx = (StartIdx + 1) & T3_SEND_RCB_ENTRY_COUNT_MASK; - if (StartIdx == 0) - pSendBd = &pDevice->pSendBdVirt[0]; - else - pSendBd++; - pTmpSendBd++; + StartIdx = + (StartIdx + 1) & T3_SEND_RCB_ENTRY_COUNT_MASK; + if (StartIdx == 0) + pSendBd = &pDevice->pSendBdVirt[0]; + else + pSendBd++; + pTmpSendBd++; + } + wmb (); + MB_REG_WR (pDevice, Mailbox.SendNicProdIdx[0].Low, Idx); + + if (T3_CHIP_REV (pDevice->ChipRevId) == T3_CHIP_REV_5700_BX) { + MB_REG_WR (pDevice, Mailbox.SendNicProdIdx[0].Low, Idx); + } + } else { + wmb (); + MB_REG_WR (pDevice, Mailbox.SendHostProdIdx[0].Low, Idx); + + if (T3_CHIP_REV (pDevice->ChipRevId) == T3_CHIP_REV_5700_BX) { + MB_REG_WR (pDevice, Mailbox.SendHostProdIdx[0].Low, + Idx); + } } - wmb(); - MB_REG_WR(pDevice, Mailbox.SendNicProdIdx[0].Low, Idx); - if(T3_CHIP_REV(pDevice->ChipRevId) == T3_CHIP_REV_5700_BX) - { - MB_REG_WR(pDevice, Mailbox.SendNicProdIdx[0].Low, Idx); - } - } - else - { - wmb(); - MB_REG_WR(pDevice, Mailbox.SendHostProdIdx[0].Low, Idx); + /* Update the SendBdLeft count. */ + atomic_sub (pPacket->u.Tx.FragCount, &pDevice->SendBdLeft); - if(T3_CHIP_REV(pDevice->ChipRevId) == T3_CHIP_REV_5700_BX) - { - MB_REG_WR(pDevice, Mailbox.SendHostProdIdx[0].Low, Idx); - } - } + /* Update the producer index. */ + pDevice->SendProdIdx = Idx; - /* Update the SendBdLeft count. */ - atomic_sub(pPacket->u.Tx.FragCount, &pDevice->SendBdLeft); - - /* Update the producer index. */ - pDevice->SendProdIdx = Idx; - - return LM_STATUS_SUCCESS; + return LM_STATUS_SUCCESS; } STATIC LM_STATUS -LM_Test4GBoundary(PLM_DEVICE_BLOCK pDevice, PLM_PACKET pPacket, - PT3_SND_BD pSendBd) +LM_Test4GBoundary (PLM_DEVICE_BLOCK pDevice, PLM_PACKET pPacket, + PT3_SND_BD pSendBd) { - int FragCount; - LM_UINT32 Idx, Base, Len; + int FragCount; + LM_UINT32 Idx, Base, Len; - Idx = pDevice->SendProdIdx; - for(FragCount = 0; ; ) - { - Len = pSendBd->u1.Len_Flags >> 16; - if (((Base = pSendBd->HostAddr.Low) > 0xffffdcc0) && - (pSendBd->HostAddr.High == 0) && - ((Base + 8 + Len) < Base)) - { - return LM_STATUS_SUCCESS; + Idx = pDevice->SendProdIdx; + for (FragCount = 0;;) { + Len = pSendBd->u1.Len_Flags >> 16; + if (((Base = pSendBd->HostAddr.Low) > 0xffffdcc0) && + (pSendBd->HostAddr.High == 0) && + ((Base + 8 + Len) < Base)) { + return LM_STATUS_SUCCESS; + } + FragCount++; + if (FragCount >= pPacket->u.Tx.FragCount) { + break; + } + pSendBd++; + if (!pDevice->NicSendBd) { + Idx = (Idx + 1) & T3_SEND_RCB_ENTRY_COUNT_MASK; + if (Idx == 0) { + pSendBd = &pDevice->pSendBdVirt[0]; + } + } } - FragCount++; - if (FragCount >= pPacket->u.Tx.FragCount) - { - break; - } - pSendBd++; - if (!pDevice->NicSendBd) - { - Idx = (Idx + 1) & T3_SEND_RCB_ENTRY_COUNT_MASK; - if (Idx == 0) - { - pSendBd = &pDevice->pSendBdVirt[0]; - } - } - } - return LM_STATUS_FAILURE; + return LM_STATUS_FAILURE; } /******************************************************************************/ @@ -3335,35 +3084,30 @@ LM_Test4GBoundary(PLM_DEVICE_BLOCK pDevice, PLM_PACKET pPacket, /* Return: */ /******************************************************************************/ __inline static unsigned long -ComputeCrc32( -unsigned char *pBuffer, -unsigned long BufferSize) { - unsigned long Reg; - unsigned long Tmp; - unsigned long j, k; +ComputeCrc32 (unsigned char *pBuffer, unsigned long BufferSize) +{ + unsigned long Reg; + unsigned long Tmp; + unsigned long j, k; - Reg = 0xffffffff; + Reg = 0xffffffff; - for(j = 0; j < BufferSize; j++) - { - Reg ^= pBuffer[j]; + for (j = 0; j < BufferSize; j++) { + Reg ^= pBuffer[j]; - for(k = 0; k < 8; k++) - { - Tmp = Reg & 0x01; + for (k = 0; k < 8; k++) { + Tmp = Reg & 0x01; - Reg >>= 1; + Reg >>= 1; - if(Tmp) - { - Reg ^= 0xedb88320; - } + if (Tmp) { + Reg ^= 0xedb88320; + } + } } - } - - return ~Reg; -} /* ComputeCrc32 */ + return ~Reg; +} /* ComputeCrc32 */ /******************************************************************************/ /* Description: */ @@ -3372,149 +3116,139 @@ unsigned long BufferSize) { /* Return: */ /* LM_STATUS_SUCCESS */ /******************************************************************************/ -LM_STATUS -LM_SetReceiveMask( -PLM_DEVICE_BLOCK pDevice, -LM_UINT32 Mask) { - LM_UINT32 ReceiveMask; - LM_UINT32 RxMode; - LM_UINT32 j, k; +LM_STATUS LM_SetReceiveMask (PLM_DEVICE_BLOCK pDevice, LM_UINT32 Mask) +{ + LM_UINT32 ReceiveMask; + LM_UINT32 RxMode; + LM_UINT32 j, k; - ReceiveMask = Mask; + ReceiveMask = Mask; - RxMode = pDevice->RxMode; + RxMode = pDevice->RxMode; - if(Mask & LM_ACCEPT_UNICAST) - { - Mask &= ~LM_ACCEPT_UNICAST; - } - - if(Mask & LM_ACCEPT_MULTICAST) - { - Mask &= ~LM_ACCEPT_MULTICAST; - } - - if(Mask & LM_ACCEPT_ALL_MULTICAST) - { - Mask &= ~LM_ACCEPT_ALL_MULTICAST; - } - - if(Mask & LM_ACCEPT_BROADCAST) - { - Mask &= ~LM_ACCEPT_BROADCAST; - } - - RxMode &= ~RX_MODE_PROMISCUOUS_MODE; - if(Mask & LM_PROMISCUOUS_MODE) - { - RxMode |= RX_MODE_PROMISCUOUS_MODE; - Mask &= ~LM_PROMISCUOUS_MODE; - } - - RxMode &= ~(RX_MODE_ACCEPT_RUNTS | RX_MODE_ACCEPT_OVERSIZED); - if(Mask & LM_ACCEPT_ERROR_PACKET) - { - RxMode |= RX_MODE_ACCEPT_RUNTS | RX_MODE_ACCEPT_OVERSIZED; - Mask &= ~LM_ACCEPT_ERROR_PACKET; - } - - /* Make sure all the bits are valid before committing changes. */ - if(Mask) - { - return LM_STATUS_FAILURE; - } - - /* Commit the new filter. */ - pDevice->RxMode = RxMode; - REG_WR(pDevice, MacCtrl.RxMode, RxMode); - - pDevice->ReceiveMask = ReceiveMask; - - /* Set up the MC hash table. */ - if(ReceiveMask & LM_ACCEPT_ALL_MULTICAST) - { - for(k = 0; k < 4; k++) - { - REG_WR(pDevice, MacCtrl.HashReg[k], 0xffffffff); - } - } - else if(ReceiveMask & LM_ACCEPT_MULTICAST) - { - LM_UINT32 HashReg[4]; - - HashReg[0] = 0; HashReg[1] = 0; HashReg[2] = 0; HashReg[3] = 0; - for(j = 0; j < pDevice->McEntryCount; j++) - { - LM_UINT32 RegIndex; - LM_UINT32 Bitpos; - LM_UINT32 Crc32; - - Crc32 = ComputeCrc32(pDevice->McTable[j], ETHERNET_ADDRESS_SIZE); - - /* The most significant 7 bits of the CRC32 (no inversion), */ - /* are used to index into one of the possible 128 bit positions. */ - Bitpos = ~Crc32 & 0x7f; - - /* Hash register index. */ - RegIndex = (Bitpos & 0x60) >> 5; - - /* Bit to turn on within a hash register. */ - Bitpos &= 0x1f; - - /* Enable the multicast bit. */ - HashReg[RegIndex] |= (1 << Bitpos); + if (Mask & LM_ACCEPT_UNICAST) { + Mask &= ~LM_ACCEPT_UNICAST; } - /* REV_AX has problem with multicast filtering where it uses both */ - /* DA and SA to perform hashing. */ - for(k = 0; k < 4; k++) - { - REG_WR(pDevice, MacCtrl.HashReg[k], HashReg[k]); + if (Mask & LM_ACCEPT_MULTICAST) { + Mask &= ~LM_ACCEPT_MULTICAST; } - } - else - { - /* Reject all multicast frames. */ - for(j = 0; j < 4; j++) - { - REG_WR(pDevice, MacCtrl.HashReg[j], 0); + + if (Mask & LM_ACCEPT_ALL_MULTICAST) { + Mask &= ~LM_ACCEPT_ALL_MULTICAST; } - } - /* By default, Tigon3 will accept broadcast frames. We need to setup */ - if(ReceiveMask & LM_ACCEPT_BROADCAST) - { - REG_WR(pDevice, MacCtrl.RcvRules[RCV_RULE1_REJECT_BROADCAST_IDX].Rule, - REJECT_BROADCAST_RULE1_RULE & RCV_DISABLE_RULE_MASK); - REG_WR(pDevice, MacCtrl.RcvRules[RCV_RULE1_REJECT_BROADCAST_IDX].Value, - REJECT_BROADCAST_RULE1_VALUE & RCV_DISABLE_RULE_MASK); - REG_WR(pDevice, MacCtrl.RcvRules[RCV_RULE2_REJECT_BROADCAST_IDX].Rule, - REJECT_BROADCAST_RULE1_RULE & RCV_DISABLE_RULE_MASK); - REG_WR(pDevice, MacCtrl.RcvRules[RCV_RULE2_REJECT_BROADCAST_IDX].Value, - REJECT_BROADCAST_RULE1_VALUE & RCV_DISABLE_RULE_MASK); - } - else - { - REG_WR(pDevice, MacCtrl.RcvRules[RCV_RULE1_REJECT_BROADCAST_IDX].Rule, - REJECT_BROADCAST_RULE1_RULE); - REG_WR(pDevice, MacCtrl.RcvRules[RCV_RULE1_REJECT_BROADCAST_IDX].Value, - REJECT_BROADCAST_RULE1_VALUE); - REG_WR(pDevice, MacCtrl.RcvRules[RCV_RULE2_REJECT_BROADCAST_IDX].Rule, - REJECT_BROADCAST_RULE2_RULE); - REG_WR(pDevice, MacCtrl.RcvRules[RCV_RULE2_REJECT_BROADCAST_IDX].Value, - REJECT_BROADCAST_RULE2_VALUE); - } + if (Mask & LM_ACCEPT_BROADCAST) { + Mask &= ~LM_ACCEPT_BROADCAST; + } - /* disable the rest of the rules. */ - for(j = RCV_LAST_RULE_IDX; j < 16; j++) - { - REG_WR(pDevice, MacCtrl.RcvRules[j].Rule, 0); - REG_WR(pDevice, MacCtrl.RcvRules[j].Value, 0); - } + RxMode &= ~RX_MODE_PROMISCUOUS_MODE; + if (Mask & LM_PROMISCUOUS_MODE) { + RxMode |= RX_MODE_PROMISCUOUS_MODE; + Mask &= ~LM_PROMISCUOUS_MODE; + } - return LM_STATUS_SUCCESS; -} /* LM_SetReceiveMask */ + RxMode &= ~(RX_MODE_ACCEPT_RUNTS | RX_MODE_ACCEPT_OVERSIZED); + if (Mask & LM_ACCEPT_ERROR_PACKET) { + RxMode |= RX_MODE_ACCEPT_RUNTS | RX_MODE_ACCEPT_OVERSIZED; + Mask &= ~LM_ACCEPT_ERROR_PACKET; + } + /* Make sure all the bits are valid before committing changes. */ + if (Mask) { + return LM_STATUS_FAILURE; + } + + /* Commit the new filter. */ + pDevice->RxMode = RxMode; + REG_WR (pDevice, MacCtrl.RxMode, RxMode); + + pDevice->ReceiveMask = ReceiveMask; + + /* Set up the MC hash table. */ + if (ReceiveMask & LM_ACCEPT_ALL_MULTICAST) { + for (k = 0; k < 4; k++) { + REG_WR (pDevice, MacCtrl.HashReg[k], 0xffffffff); + } + } else if (ReceiveMask & LM_ACCEPT_MULTICAST) { + LM_UINT32 HashReg[4]; + + HashReg[0] = 0; + HashReg[1] = 0; + HashReg[2] = 0; + HashReg[3] = 0; + for (j = 0; j < pDevice->McEntryCount; j++) { + LM_UINT32 RegIndex; + LM_UINT32 Bitpos; + LM_UINT32 Crc32; + + Crc32 = + ComputeCrc32 (pDevice->McTable[j], + ETHERNET_ADDRESS_SIZE); + + /* The most significant 7 bits of the CRC32 (no inversion), */ + /* are used to index into one of the possible 128 bit positions. */ + Bitpos = ~Crc32 & 0x7f; + + /* Hash register index. */ + RegIndex = (Bitpos & 0x60) >> 5; + + /* Bit to turn on within a hash register. */ + Bitpos &= 0x1f; + + /* Enable the multicast bit. */ + HashReg[RegIndex] |= (1 << Bitpos); + } + + /* REV_AX has problem with multicast filtering where it uses both */ + /* DA and SA to perform hashing. */ + for (k = 0; k < 4; k++) { + REG_WR (pDevice, MacCtrl.HashReg[k], HashReg[k]); + } + } else { + /* Reject all multicast frames. */ + for (j = 0; j < 4; j++) { + REG_WR (pDevice, MacCtrl.HashReg[j], 0); + } + } + + /* By default, Tigon3 will accept broadcast frames. We need to setup */ + if (ReceiveMask & LM_ACCEPT_BROADCAST) { + REG_WR (pDevice, + MacCtrl.RcvRules[RCV_RULE1_REJECT_BROADCAST_IDX].Rule, + REJECT_BROADCAST_RULE1_RULE & RCV_DISABLE_RULE_MASK); + REG_WR (pDevice, + MacCtrl.RcvRules[RCV_RULE1_REJECT_BROADCAST_IDX].Value, + REJECT_BROADCAST_RULE1_VALUE & RCV_DISABLE_RULE_MASK); + REG_WR (pDevice, + MacCtrl.RcvRules[RCV_RULE2_REJECT_BROADCAST_IDX].Rule, + REJECT_BROADCAST_RULE1_RULE & RCV_DISABLE_RULE_MASK); + REG_WR (pDevice, + MacCtrl.RcvRules[RCV_RULE2_REJECT_BROADCAST_IDX].Value, + REJECT_BROADCAST_RULE1_VALUE & RCV_DISABLE_RULE_MASK); + } else { + REG_WR (pDevice, + MacCtrl.RcvRules[RCV_RULE1_REJECT_BROADCAST_IDX].Rule, + REJECT_BROADCAST_RULE1_RULE); + REG_WR (pDevice, + MacCtrl.RcvRules[RCV_RULE1_REJECT_BROADCAST_IDX].Value, + REJECT_BROADCAST_RULE1_VALUE); + REG_WR (pDevice, + MacCtrl.RcvRules[RCV_RULE2_REJECT_BROADCAST_IDX].Rule, + REJECT_BROADCAST_RULE2_RULE); + REG_WR (pDevice, + MacCtrl.RcvRules[RCV_RULE2_REJECT_BROADCAST_IDX].Value, + REJECT_BROADCAST_RULE2_VALUE); + } + + /* disable the rest of the rules. */ + for (j = RCV_LAST_RULE_IDX; j < 16; j++) { + REG_WR (pDevice, MacCtrl.RcvRules[j].Rule, 0); + REG_WR (pDevice, MacCtrl.RcvRules[j].Value, 0); + } + + return LM_STATUS_SUCCESS; +} /* LM_SetReceiveMask */ /******************************************************************************/ /* Description: */ @@ -3525,138 +3259,135 @@ LM_UINT32 Mask) { /* Return: */ /* LM_STATUS_SUCCESS */ /******************************************************************************/ -LM_STATUS -LM_Abort( -PLM_DEVICE_BLOCK pDevice) +LM_STATUS LM_Abort (PLM_DEVICE_BLOCK pDevice) { - PLM_PACKET pPacket; - LM_UINT Idx; + PLM_PACKET pPacket; + LM_UINT Idx; - LM_DisableInterrupt(pDevice); + LM_DisableInterrupt (pDevice); - /* Disable all the state machines. */ - LM_CntrlBlock(pDevice,T3_BLOCK_MAC_RX_ENGINE,LM_DISABLE); - LM_CntrlBlock(pDevice,T3_BLOCK_RX_BD_INITIATOR,LM_DISABLE); - LM_CntrlBlock(pDevice,T3_BLOCK_RX_LIST_PLMT,LM_DISABLE); - LM_CntrlBlock(pDevice,T3_BLOCK_RX_LIST_SELECTOR,LM_DISABLE); - LM_CntrlBlock(pDevice,T3_BLOCK_RX_DATA_INITIATOR,LM_DISABLE); - LM_CntrlBlock(pDevice,T3_BLOCK_RX_DATA_COMP,LM_DISABLE); - LM_CntrlBlock(pDevice,T3_BLOCK_RX_BD_COMP,LM_DISABLE); + /* Disable all the state machines. */ + LM_CntrlBlock (pDevice, T3_BLOCK_MAC_RX_ENGINE, LM_DISABLE); + LM_CntrlBlock (pDevice, T3_BLOCK_RX_BD_INITIATOR, LM_DISABLE); + LM_CntrlBlock (pDevice, T3_BLOCK_RX_LIST_PLMT, LM_DISABLE); + LM_CntrlBlock (pDevice, T3_BLOCK_RX_LIST_SELECTOR, LM_DISABLE); + LM_CntrlBlock (pDevice, T3_BLOCK_RX_DATA_INITIATOR, LM_DISABLE); + LM_CntrlBlock (pDevice, T3_BLOCK_RX_DATA_COMP, LM_DISABLE); + LM_CntrlBlock (pDevice, T3_BLOCK_RX_BD_COMP, LM_DISABLE); - LM_CntrlBlock(pDevice,T3_BLOCK_SEND_BD_SELECTOR,LM_DISABLE); - LM_CntrlBlock(pDevice,T3_BLOCK_SEND_BD_INITIATOR,LM_DISABLE); - LM_CntrlBlock(pDevice,T3_BLOCK_SEND_DATA_INITIATOR,LM_DISABLE); - LM_CntrlBlock(pDevice,T3_BLOCK_DMA_RD,LM_DISABLE); - LM_CntrlBlock(pDevice,T3_BLOCK_SEND_DATA_COMP,LM_DISABLE); - LM_CntrlBlock(pDevice,T3_BLOCK_DMA_COMP,LM_DISABLE); - LM_CntrlBlock(pDevice,T3_BLOCK_SEND_BD_COMP,LM_DISABLE); + LM_CntrlBlock (pDevice, T3_BLOCK_SEND_BD_SELECTOR, LM_DISABLE); + LM_CntrlBlock (pDevice, T3_BLOCK_SEND_BD_INITIATOR, LM_DISABLE); + LM_CntrlBlock (pDevice, T3_BLOCK_SEND_DATA_INITIATOR, LM_DISABLE); + LM_CntrlBlock (pDevice, T3_BLOCK_DMA_RD, LM_DISABLE); + LM_CntrlBlock (pDevice, T3_BLOCK_SEND_DATA_COMP, LM_DISABLE); + LM_CntrlBlock (pDevice, T3_BLOCK_DMA_COMP, LM_DISABLE); + LM_CntrlBlock (pDevice, T3_BLOCK_SEND_BD_COMP, LM_DISABLE); - /* Clear TDE bit */ - pDevice->MacMode &= ~MAC_MODE_ENABLE_TDE; - REG_WR(pDevice, MacCtrl.Mode, pDevice->MacMode); + /* Clear TDE bit */ + pDevice->MacMode &= ~MAC_MODE_ENABLE_TDE; + REG_WR (pDevice, MacCtrl.Mode, pDevice->MacMode); - LM_CntrlBlock(pDevice,T3_BLOCK_MAC_TX_ENGINE,LM_DISABLE); - LM_CntrlBlock(pDevice,T3_BLOCK_HOST_COALESING,LM_DISABLE); - LM_CntrlBlock(pDevice,T3_BLOCK_DMA_WR,LM_DISABLE); - LM_CntrlBlock(pDevice,T3_BLOCK_MBUF_CLUSTER_FREE,LM_DISABLE); + LM_CntrlBlock (pDevice, T3_BLOCK_MAC_TX_ENGINE, LM_DISABLE); + LM_CntrlBlock (pDevice, T3_BLOCK_HOST_COALESING, LM_DISABLE); + LM_CntrlBlock (pDevice, T3_BLOCK_DMA_WR, LM_DISABLE); + LM_CntrlBlock (pDevice, T3_BLOCK_MBUF_CLUSTER_FREE, LM_DISABLE); - /* Reset all FTQs */ - REG_WR(pDevice, Ftq.Reset, 0xffffffff); - REG_WR(pDevice, Ftq.Reset, 0x0); + /* Reset all FTQs */ + REG_WR (pDevice, Ftq.Reset, 0xffffffff); + REG_WR (pDevice, Ftq.Reset, 0x0); - LM_CntrlBlock(pDevice,T3_BLOCK_MBUF_MANAGER,LM_DISABLE); - LM_CntrlBlock(pDevice,T3_BLOCK_MEM_ARBITOR,LM_DISABLE); + LM_CntrlBlock (pDevice, T3_BLOCK_MBUF_MANAGER, LM_DISABLE); + LM_CntrlBlock (pDevice, T3_BLOCK_MEM_ARBITOR, LM_DISABLE); - MM_ACQUIRE_INT_LOCK(pDevice); + MM_ACQUIRE_INT_LOCK (pDevice); - /* Abort packets that have already queued to go out. */ - pPacket = (PLM_PACKET) QQ_PopHead(&pDevice->TxPacketActiveQ.Container); - while(pPacket) - { + /* Abort packets that have already queued to go out. */ + pPacket = (PLM_PACKET) QQ_PopHead (&pDevice->TxPacketActiveQ.Container); + while (pPacket) { - pPacket->PacketStatus = LM_STATUS_TRANSMIT_ABORTED; - pDevice->TxCounters.TxPacketAbortedCnt++; + pPacket->PacketStatus = LM_STATUS_TRANSMIT_ABORTED; + pDevice->TxCounters.TxPacketAbortedCnt++; - atomic_add(pPacket->u.Tx.FragCount, &pDevice->SendBdLeft); + atomic_add (pPacket->u.Tx.FragCount, &pDevice->SendBdLeft); - QQ_PushTail(&pDevice->TxPacketXmittedQ.Container, pPacket); + QQ_PushTail (&pDevice->TxPacketXmittedQ.Container, pPacket); - pPacket = (PLM_PACKET) - QQ_PopHead(&pDevice->TxPacketActiveQ.Container); - } - - /* Cleanup the receive return rings. */ - LM_ServiceRxInterrupt(pDevice); - - /* Don't want to indicate rx packets in Ndis miniport shutdown context. */ - /* Doing so may cause system crash. */ - if(!pDevice->ShuttingDown) - { - /* Indicate packets to the protocol. */ - MM_IndicateTxPackets(pDevice); - - /* Indicate received packets to the protocols. */ - MM_IndicateRxPackets(pDevice); - } - else - { - /* Move the receive packet descriptors in the ReceivedQ to the */ - /* free queue. */ - for(; ;) - { - pPacket = (PLM_PACKET) QQ_PopHead( - &pDevice->RxPacketReceivedQ.Container); - if(pPacket == NULL) - { - break; - } - QQ_PushTail(&pDevice->RxPacketFreeQ.Container, pPacket); + pPacket = (PLM_PACKET) + QQ_PopHead (&pDevice->TxPacketActiveQ.Container); } - } - /* Clean up the Std Receive Producer ring. */ - Idx = pDevice->pStatusBlkVirt->RcvStdConIdx; + /* Cleanup the receive return rings. */ + LM_ServiceRxInterrupt (pDevice); - while(Idx != pDevice->RxStdProdIdx) { - pPacket = (PLM_PACKET) (MM_UINT_PTR(pDevice->pPacketDescBase) + - MM_UINT_PTR(pDevice->pRxStdBdVirt[Idx].Opaque)); + /* Don't want to indicate rx packets in Ndis miniport shutdown context. */ + /* Doing so may cause system crash. */ + if (!pDevice->ShuttingDown) { + /* Indicate packets to the protocol. */ + MM_IndicateTxPackets (pDevice); - QQ_PushTail(&pDevice->RxPacketFreeQ.Container, pPacket); + /* Indicate received packets to the protocols. */ + MM_IndicateRxPackets (pDevice); + } else { + /* Move the receive packet descriptors in the ReceivedQ to the */ + /* free queue. */ + for (;;) { + pPacket = + (PLM_PACKET) QQ_PopHead (&pDevice-> + RxPacketReceivedQ. + Container); + if (pPacket == NULL) { + break; + } + QQ_PushTail (&pDevice->RxPacketFreeQ.Container, + pPacket); + } + } - Idx = (Idx + 1) & T3_STD_RCV_RCB_ENTRY_COUNT_MASK; - } /* while */ + /* Clean up the Std Receive Producer ring. */ + Idx = pDevice->pStatusBlkVirt->RcvStdConIdx; - /* Reinitialize our copy of the indices. */ - pDevice->RxStdProdIdx = 0; + while (Idx != pDevice->RxStdProdIdx) { + pPacket = (PLM_PACKET) (MM_UINT_PTR (pDevice->pPacketDescBase) + + MM_UINT_PTR (pDevice->pRxStdBdVirt[Idx]. + Opaque)); + + QQ_PushTail (&pDevice->RxPacketFreeQ.Container, pPacket); + + Idx = (Idx + 1) & T3_STD_RCV_RCB_ENTRY_COUNT_MASK; + } /* while */ + + /* Reinitialize our copy of the indices. */ + pDevice->RxStdProdIdx = 0; #if T3_JUMBO_RCV_RCB_ENTRY_COUNT - /* Clean up the Jumbo Receive Producer ring. */ - Idx = pDevice->pStatusBlkVirt->RcvJumboConIdx; + /* Clean up the Jumbo Receive Producer ring. */ + Idx = pDevice->pStatusBlkVirt->RcvJumboConIdx; - while(Idx != pDevice->RxJumboProdIdx) { - pPacket = (PLM_PACKET) (MM_UINT_PTR(pDevice->pPacketDescBase) + - MM_UINT_PTR(pDevice->pRxJumboBdVirt[Idx].Opaque)); + while (Idx != pDevice->RxJumboProdIdx) { + pPacket = (PLM_PACKET) (MM_UINT_PTR (pDevice->pPacketDescBase) + + MM_UINT_PTR (pDevice-> + pRxJumboBdVirt[Idx]. + Opaque)); - QQ_PushTail(&pDevice->RxPacketFreeQ.Container, pPacket); + QQ_PushTail (&pDevice->RxPacketFreeQ.Container, pPacket); - Idx = (Idx + 1) & T3_JUMBO_RCV_RCB_ENTRY_COUNT_MASK; - } /* while */ + Idx = (Idx + 1) & T3_JUMBO_RCV_RCB_ENTRY_COUNT_MASK; + } /* while */ - /* Reinitialize our copy of the indices. */ - pDevice->RxJumboProdIdx = 0; -#endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */ + /* Reinitialize our copy of the indices. */ + pDevice->RxJumboProdIdx = 0; +#endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */ - MM_RELEASE_INT_LOCK(pDevice); + MM_RELEASE_INT_LOCK (pDevice); - /* Initialize the statistis Block */ - pDevice->pStatusBlkVirt->Status = 0; - pDevice->pStatusBlkVirt->RcvStdConIdx = 0; - pDevice->pStatusBlkVirt->RcvJumboConIdx = 0; - pDevice->pStatusBlkVirt->RcvMiniConIdx = 0; - - return LM_STATUS_SUCCESS; -} /* LM_Abort */ + /* Initialize the statistis Block */ + pDevice->pStatusBlkVirt->Status = 0; + pDevice->pStatusBlkVirt->RcvStdConIdx = 0; + pDevice->pStatusBlkVirt->RcvJumboConIdx = 0; + pDevice->pStatusBlkVirt->RcvMiniConIdx = 0; + return LM_STATUS_SUCCESS; +} /* LM_Abort */ /******************************************************************************/ /* Description: */ @@ -3667,140 +3398,130 @@ PLM_DEVICE_BLOCK pDevice) /* Return: */ /* LM_STATUS_SUCCESS */ /******************************************************************************/ -LM_STATUS -LM_Halt( -PLM_DEVICE_BLOCK pDevice) { - PLM_PACKET pPacket; - LM_UINT32 EntryCnt; - - LM_Abort(pDevice); - - /* Get the number of entries in the queue. */ - EntryCnt = QQ_GetEntryCnt(&pDevice->RxPacketFreeQ.Container); - - /* Make sure all the packets have been accounted for. */ - for(EntryCnt = 0; EntryCnt < pDevice->RxPacketDescCnt; EntryCnt++) - { - pPacket = (PLM_PACKET) QQ_PopHead(&pDevice->RxPacketFreeQ.Container); - if (pPacket == 0) - break; - - MM_FreeRxBuffer(pDevice, pPacket); - - QQ_PushTail(&pDevice->RxPacketFreeQ.Container, pPacket); - } - - LM_ResetChip(pDevice); - - /* Restore PCI configuration registers. */ - MM_WriteConfig32(pDevice, PCI_CACHE_LINE_SIZE_REG, - pDevice->SavedCacheLineReg); - LM_RegWrInd(pDevice, PCI_SUBSYSTEM_VENDOR_ID_REG, - (pDevice->SubsystemId << 16) | pDevice->SubsystemVendorId); - - /* Reprogram the MAC address. */ - LM_SetMacAddress(pDevice, pDevice->NodeAddress); - - return LM_STATUS_SUCCESS; -} /* LM_Halt */ - - -STATIC LM_STATUS -LM_ResetChip(PLM_DEVICE_BLOCK pDevice) +LM_STATUS LM_Halt (PLM_DEVICE_BLOCK pDevice) { - LM_UINT32 Value32; - LM_UINT32 j; + PLM_PACKET pPacket; + LM_UINT32 EntryCnt; - /* Wait for access to the nvram interface before resetting. This is */ - /* a workaround to prevent EEPROM corruption. */ - if(T3_ASIC_REV(pDevice->ChipRevId) != T3_ASIC_REV_5700 && - T3_ASIC_REV(pDevice->ChipRevId) != T3_ASIC_REV_5701) - { - /* Request access to the flash interface. */ - REG_WR(pDevice, Nvram.SwArb, SW_ARB_REQ_SET1); + LM_Abort (pDevice); - for(j = 0; j < 100000; j++) - { - Value32 = REG_RD(pDevice, Nvram.SwArb); - if(Value32 & SW_ARB_GNT1) - { - break; - } - MM_Wait(10); + /* Get the number of entries in the queue. */ + EntryCnt = QQ_GetEntryCnt (&pDevice->RxPacketFreeQ.Container); + + /* Make sure all the packets have been accounted for. */ + for (EntryCnt = 0; EntryCnt < pDevice->RxPacketDescCnt; EntryCnt++) { + pPacket = + (PLM_PACKET) QQ_PopHead (&pDevice->RxPacketFreeQ.Container); + if (pPacket == 0) + break; + + MM_FreeRxBuffer (pDevice, pPacket); + + QQ_PushTail (&pDevice->RxPacketFreeQ.Container, pPacket); } - } - /* Global reset. */ - REG_WR(pDevice, Grc.MiscCfg, GRC_MISC_CFG_CORE_CLOCK_RESET); - MM_Wait(40); MM_Wait(40); MM_Wait(40); + LM_ResetChip (pDevice); - /* make sure we re-enable indirect accesses */ - MM_WriteConfig32(pDevice, T3_PCI_MISC_HOST_CTRL_REG, - pDevice->MiscHostCtrl); + /* Restore PCI configuration registers. */ + MM_WriteConfig32 (pDevice, PCI_CACHE_LINE_SIZE_REG, + pDevice->SavedCacheLineReg); + LM_RegWrInd (pDevice, PCI_SUBSYSTEM_VENDOR_ID_REG, + (pDevice->SubsystemId << 16) | pDevice->SubsystemVendorId); - /* Set MAX PCI retry to zero. */ - Value32 = T3_PCI_STATE_PCI_ROM_ENABLE | T3_PCI_STATE_PCI_ROM_RETRY_ENABLE; - if (pDevice->ChipRevId == T3_CHIP_ID_5704_A0) - { - if (!(pDevice->PciState & T3_PCI_STATE_CONVENTIONAL_PCI_MODE)) - { - Value32 |= T3_PCI_STATE_RETRY_SAME_DMA; + /* Reprogram the MAC address. */ + LM_SetMacAddress (pDevice, pDevice->NodeAddress); + + return LM_STATUS_SUCCESS; +} /* LM_Halt */ + +STATIC LM_STATUS LM_ResetChip (PLM_DEVICE_BLOCK pDevice) +{ + LM_UINT32 Value32; + LM_UINT32 j; + + /* Wait for access to the nvram interface before resetting. This is */ + /* a workaround to prevent EEPROM corruption. */ + if (T3_ASIC_REV (pDevice->ChipRevId) != T3_ASIC_REV_5700 && + T3_ASIC_REV (pDevice->ChipRevId) != T3_ASIC_REV_5701) { + /* Request access to the flash interface. */ + REG_WR (pDevice, Nvram.SwArb, SW_ARB_REQ_SET1); + + for (j = 0; j < 100000; j++) { + Value32 = REG_RD (pDevice, Nvram.SwArb); + if (Value32 & SW_ARB_GNT1) { + break; + } + MM_Wait (10); + } } - } - MM_WriteConfig32(pDevice, T3_PCI_STATE_REG, Value32); - /* Restore PCI command register. */ - MM_WriteConfig32(pDevice, PCI_COMMAND_REG, - pDevice->PciCommandStatusWords); + /* Global reset. */ + REG_WR (pDevice, Grc.MiscCfg, GRC_MISC_CFG_CORE_CLOCK_RESET); + MM_Wait (40); + MM_Wait (40); + MM_Wait (40); - /* Disable PCI-X relaxed ordering bit. */ - MM_ReadConfig32(pDevice, PCIX_CAP_REG, &Value32); - Value32 &= ~PCIX_ENABLE_RELAXED_ORDERING; - MM_WriteConfig32(pDevice, PCIX_CAP_REG, Value32); + /* make sure we re-enable indirect accesses */ + MM_WriteConfig32 (pDevice, T3_PCI_MISC_HOST_CTRL_REG, + pDevice->MiscHostCtrl); - /* Enable memory arbiter. */ - REG_WR(pDevice, MemArbiter.Mode, T3_MEM_ARBITER_MODE_ENABLE); + /* Set MAX PCI retry to zero. */ + Value32 = + T3_PCI_STATE_PCI_ROM_ENABLE | T3_PCI_STATE_PCI_ROM_RETRY_ENABLE; + if (pDevice->ChipRevId == T3_CHIP_ID_5704_A0) { + if (!(pDevice->PciState & T3_PCI_STATE_CONVENTIONAL_PCI_MODE)) { + Value32 |= T3_PCI_STATE_RETRY_SAME_DMA; + } + } + MM_WriteConfig32 (pDevice, T3_PCI_STATE_REG, Value32); -#ifdef BIG_ENDIAN_PCI /* This from jfd */ - Value32 = GRC_MODE_WORD_SWAP_DATA| - GRC_MODE_WORD_SWAP_NON_FRAME_DATA; + /* Restore PCI command register. */ + MM_WriteConfig32 (pDevice, PCI_COMMAND_REG, + pDevice->PciCommandStatusWords); + + /* Disable PCI-X relaxed ordering bit. */ + MM_ReadConfig32 (pDevice, PCIX_CAP_REG, &Value32); + Value32 &= ~PCIX_ENABLE_RELAXED_ORDERING; + MM_WriteConfig32 (pDevice, PCIX_CAP_REG, Value32); + + /* Enable memory arbiter. */ + REG_WR (pDevice, MemArbiter.Mode, T3_MEM_ARBITER_MODE_ENABLE); + +#ifdef BIG_ENDIAN_PCI /* This from jfd */ + Value32 = GRC_MODE_WORD_SWAP_DATA | GRC_MODE_WORD_SWAP_NON_FRAME_DATA; #else #ifdef BIG_ENDIAN_HOST - /* Reconfigure the mode register. */ - Value32 = GRC_MODE_BYTE_SWAP_NON_FRAME_DATA | - GRC_MODE_WORD_SWAP_NON_FRAME_DATA | - GRC_MODE_BYTE_SWAP_DATA | - GRC_MODE_WORD_SWAP_DATA; + /* Reconfigure the mode register. */ + Value32 = GRC_MODE_BYTE_SWAP_NON_FRAME_DATA | + GRC_MODE_WORD_SWAP_NON_FRAME_DATA | + GRC_MODE_BYTE_SWAP_DATA | GRC_MODE_WORD_SWAP_DATA; #else - /* Reconfigure the mode register. */ - Value32 = GRC_MODE_BYTE_SWAP_NON_FRAME_DATA | GRC_MODE_BYTE_SWAP_DATA; + /* Reconfigure the mode register. */ + Value32 = GRC_MODE_BYTE_SWAP_NON_FRAME_DATA | GRC_MODE_BYTE_SWAP_DATA; #endif #endif - REG_WR(pDevice, Grc.Mode, Value32); + REG_WR (pDevice, Grc.Mode, Value32); - /* Prevent PXE from restarting. */ - MEM_WR_OFFSET(pDevice, 0x0b50, T3_MAGIC_NUM); + /* Prevent PXE from restarting. */ + MEM_WR_OFFSET (pDevice, 0x0b50, T3_MAGIC_NUM); - if(pDevice->EnableTbi) { - pDevice->MacMode = MAC_MODE_PORT_MODE_TBI; - REG_WR(pDevice, MacCtrl.Mode, MAC_MODE_PORT_MODE_TBI); - } - else { - REG_WR(pDevice, MacCtrl.Mode, 0); - } - - /* Wait for the firmware to finish initialization. */ - for(j = 0; j < 100000; j++) - { - MM_Wait(10); - - Value32 = MEM_RD_OFFSET(pDevice, 0x0b50); - if(Value32 == ~T3_MAGIC_NUM) - { - break; + if (pDevice->EnableTbi) { + pDevice->MacMode = MAC_MODE_PORT_MODE_TBI; + REG_WR (pDevice, MacCtrl.Mode, MAC_MODE_PORT_MODE_TBI); + } else { + REG_WR (pDevice, MacCtrl.Mode, 0); } - } - return LM_STATUS_SUCCESS; + + /* Wait for the firmware to finish initialization. */ + for (j = 0; j < 100000; j++) { + MM_Wait (10); + + Value32 = MEM_RD_OFFSET (pDevice, 0x0b50); + if (Value32 == ~T3_MAGIC_NUM) { + break; + } + } + return LM_STATUS_SUCCESS; } /******************************************************************************/ @@ -3808,161 +3529,143 @@ LM_ResetChip(PLM_DEVICE_BLOCK pDevice) /* */ /* Return: */ /******************************************************************************/ -__inline static void -LM_ServiceTxInterrupt( -PLM_DEVICE_BLOCK pDevice) { - PLM_PACKET pPacket; - LM_UINT32 HwConIdx; - LM_UINT32 SwConIdx; +__inline static void LM_ServiceTxInterrupt (PLM_DEVICE_BLOCK pDevice) +{ + PLM_PACKET pPacket; + LM_UINT32 HwConIdx; + LM_UINT32 SwConIdx; - HwConIdx = pDevice->pStatusBlkVirt->Idx[0].SendConIdx; - - /* Get our copy of the consumer index. The buffer descriptors */ - /* that are in between the consumer indices are freed. */ - SwConIdx = pDevice->SendConIdx; - - /* Move the packets from the TxPacketActiveQ that are sent out to */ - /* the TxPacketXmittedQ. Packets that are sent use the */ - /* descriptors that are between SwConIdx and HwConIdx. */ - while(SwConIdx != HwConIdx) - { - /* Get the packet that was sent from the TxPacketActiveQ. */ - pPacket = (PLM_PACKET) QQ_PopHead( - &pDevice->TxPacketActiveQ.Container); - - /* Set the return status. */ - pPacket->PacketStatus = LM_STATUS_SUCCESS; - - /* Put the packet in the TxPacketXmittedQ for indication later. */ - QQ_PushTail(&pDevice->TxPacketXmittedQ.Container, pPacket); - - /* Move to the next packet's BD. */ - SwConIdx = (SwConIdx + pPacket->u.Tx.FragCount) & - T3_SEND_RCB_ENTRY_COUNT_MASK; - - /* Update the number of unused BDs. */ - atomic_add(pPacket->u.Tx.FragCount, &pDevice->SendBdLeft); - - /* Get the new updated HwConIdx. */ HwConIdx = pDevice->pStatusBlkVirt->Idx[0].SendConIdx; - } /* while */ - /* Save the new SwConIdx. */ - pDevice->SendConIdx = SwConIdx; + /* Get our copy of the consumer index. The buffer descriptors */ + /* that are in between the consumer indices are freed. */ + SwConIdx = pDevice->SendConIdx; -} /* LM_ServiceTxInterrupt */ + /* Move the packets from the TxPacketActiveQ that are sent out to */ + /* the TxPacketXmittedQ. Packets that are sent use the */ + /* descriptors that are between SwConIdx and HwConIdx. */ + while (SwConIdx != HwConIdx) { + /* Get the packet that was sent from the TxPacketActiveQ. */ + pPacket = + (PLM_PACKET) QQ_PopHead (&pDevice->TxPacketActiveQ. + Container); + /* Set the return status. */ + pPacket->PacketStatus = LM_STATUS_SUCCESS; + + /* Put the packet in the TxPacketXmittedQ for indication later. */ + QQ_PushTail (&pDevice->TxPacketXmittedQ.Container, pPacket); + + /* Move to the next packet's BD. */ + SwConIdx = (SwConIdx + pPacket->u.Tx.FragCount) & + T3_SEND_RCB_ENTRY_COUNT_MASK; + + /* Update the number of unused BDs. */ + atomic_add (pPacket->u.Tx.FragCount, &pDevice->SendBdLeft); + + /* Get the new updated HwConIdx. */ + HwConIdx = pDevice->pStatusBlkVirt->Idx[0].SendConIdx; + } /* while */ + + /* Save the new SwConIdx. */ + pDevice->SendConIdx = SwConIdx; + +} /* LM_ServiceTxInterrupt */ /******************************************************************************/ /* Description: */ /* */ /* Return: */ /******************************************************************************/ -__inline static void -LM_ServiceRxInterrupt( -PLM_DEVICE_BLOCK pDevice) { - PLM_PACKET pPacket; - PT3_RCV_BD pRcvBd; - LM_UINT32 HwRcvRetProdIdx; - LM_UINT32 SwRcvRetConIdx; +__inline static void LM_ServiceRxInterrupt (PLM_DEVICE_BLOCK pDevice) +{ + PLM_PACKET pPacket; + PT3_RCV_BD pRcvBd; + LM_UINT32 HwRcvRetProdIdx; + LM_UINT32 SwRcvRetConIdx; - /* Loop thru the receive return rings for received packets. */ - HwRcvRetProdIdx = pDevice->pStatusBlkVirt->Idx[0].RcvProdIdx; - - SwRcvRetConIdx = pDevice->RcvRetConIdx; - while(SwRcvRetConIdx != HwRcvRetProdIdx) - { - pRcvBd = &pDevice->pRcvRetBdVirt[SwRcvRetConIdx]; - - /* Get the received packet descriptor. */ - pPacket = (PLM_PACKET) (MM_UINT_PTR(pDevice->pPacketDescBase) + - MM_UINT_PTR(pRcvBd->Opaque)); - - /* Check the error flag. */ - if(pRcvBd->ErrorFlag && - pRcvBd->ErrorFlag != RCV_BD_ERR_ODD_NIBBLED_RCVD_MII) - { - pPacket->PacketStatus = LM_STATUS_FAILURE; - - pDevice->RxCounters.RxPacketErrCnt++; - - if(pRcvBd->ErrorFlag & RCV_BD_ERR_BAD_CRC) - { - pDevice->RxCounters.RxErrCrcCnt++; - } - - if(pRcvBd->ErrorFlag & RCV_BD_ERR_COLL_DETECT) - { - pDevice->RxCounters.RxErrCollCnt++; - } - - if(pRcvBd->ErrorFlag & RCV_BD_ERR_LINK_LOST_DURING_PKT) - { - pDevice->RxCounters.RxErrLinkLostCnt++; - } - - if(pRcvBd->ErrorFlag & RCV_BD_ERR_PHY_DECODE_ERR) - { - pDevice->RxCounters.RxErrPhyDecodeCnt++; - } - - if(pRcvBd->ErrorFlag & RCV_BD_ERR_ODD_NIBBLED_RCVD_MII) - { - pDevice->RxCounters.RxErrOddNibbleCnt++; - } - - if(pRcvBd->ErrorFlag & RCV_BD_ERR_MAC_ABORT) - { - pDevice->RxCounters.RxErrMacAbortCnt++; - } - - if(pRcvBd->ErrorFlag & RCV_BD_ERR_LEN_LT_64) - { - pDevice->RxCounters.RxErrShortPacketCnt++; - } - - if(pRcvBd->ErrorFlag & RCV_BD_ERR_TRUNC_NO_RESOURCES) - { - pDevice->RxCounters.RxErrNoResourceCnt++; - } - - if(pRcvBd->ErrorFlag & RCV_BD_ERR_GIANT_FRAME_RCVD) - { - pDevice->RxCounters.RxErrLargePacketCnt++; - } - } - else - { - pPacket->PacketStatus = LM_STATUS_SUCCESS; - pPacket->PacketSize = pRcvBd->Len - 4; - - pPacket->Flags = pRcvBd->Flags; - if(pRcvBd->Flags & RCV_BD_FLAG_VLAN_TAG) - { - pPacket->VlanTag = pRcvBd->VlanTag; - } - - pPacket->u.Rx.TcpUdpChecksum = pRcvBd->TcpUdpCksum; - } - - /* Put the packet descriptor containing the received packet */ - /* buffer in the RxPacketReceivedQ for indication later. */ - QQ_PushTail(&pDevice->RxPacketReceivedQ.Container, pPacket); - - /* Go to the next buffer descriptor. */ - SwRcvRetConIdx = (SwRcvRetConIdx + 1) & - T3_RCV_RETURN_RCB_ENTRY_COUNT_MASK; - - /* Get the updated HwRcvRetProdIdx. */ + /* Loop thru the receive return rings for received packets. */ HwRcvRetProdIdx = pDevice->pStatusBlkVirt->Idx[0].RcvProdIdx; - } /* while */ - pDevice->RcvRetConIdx = SwRcvRetConIdx; + SwRcvRetConIdx = pDevice->RcvRetConIdx; + while (SwRcvRetConIdx != HwRcvRetProdIdx) { + pRcvBd = &pDevice->pRcvRetBdVirt[SwRcvRetConIdx]; - /* Update the receive return ring consumer index. */ - MB_REG_WR(pDevice, Mailbox.RcvRetConIdx[0].Low, SwRcvRetConIdx); -} /* LM_ServiceRxInterrupt */ + /* Get the received packet descriptor. */ + pPacket = (PLM_PACKET) (MM_UINT_PTR (pDevice->pPacketDescBase) + + MM_UINT_PTR (pRcvBd->Opaque)); + /* Check the error flag. */ + if (pRcvBd->ErrorFlag && + pRcvBd->ErrorFlag != RCV_BD_ERR_ODD_NIBBLED_RCVD_MII) { + pPacket->PacketStatus = LM_STATUS_FAILURE; + + pDevice->RxCounters.RxPacketErrCnt++; + + if (pRcvBd->ErrorFlag & RCV_BD_ERR_BAD_CRC) { + pDevice->RxCounters.RxErrCrcCnt++; + } + + if (pRcvBd->ErrorFlag & RCV_BD_ERR_COLL_DETECT) { + pDevice->RxCounters.RxErrCollCnt++; + } + + if (pRcvBd->ErrorFlag & RCV_BD_ERR_LINK_LOST_DURING_PKT) { + pDevice->RxCounters.RxErrLinkLostCnt++; + } + + if (pRcvBd->ErrorFlag & RCV_BD_ERR_PHY_DECODE_ERR) { + pDevice->RxCounters.RxErrPhyDecodeCnt++; + } + + if (pRcvBd->ErrorFlag & RCV_BD_ERR_ODD_NIBBLED_RCVD_MII) { + pDevice->RxCounters.RxErrOddNibbleCnt++; + } + + if (pRcvBd->ErrorFlag & RCV_BD_ERR_MAC_ABORT) { + pDevice->RxCounters.RxErrMacAbortCnt++; + } + + if (pRcvBd->ErrorFlag & RCV_BD_ERR_LEN_LT_64) { + pDevice->RxCounters.RxErrShortPacketCnt++; + } + + if (pRcvBd->ErrorFlag & RCV_BD_ERR_TRUNC_NO_RESOURCES) { + pDevice->RxCounters.RxErrNoResourceCnt++; + } + + if (pRcvBd->ErrorFlag & RCV_BD_ERR_GIANT_FRAME_RCVD) { + pDevice->RxCounters.RxErrLargePacketCnt++; + } + } else { + pPacket->PacketStatus = LM_STATUS_SUCCESS; + pPacket->PacketSize = pRcvBd->Len - 4; + + pPacket->Flags = pRcvBd->Flags; + if (pRcvBd->Flags & RCV_BD_FLAG_VLAN_TAG) { + pPacket->VlanTag = pRcvBd->VlanTag; + } + + pPacket->u.Rx.TcpUdpChecksum = pRcvBd->TcpUdpCksum; + } + + /* Put the packet descriptor containing the received packet */ + /* buffer in the RxPacketReceivedQ for indication later. */ + QQ_PushTail (&pDevice->RxPacketReceivedQ.Container, pPacket); + + /* Go to the next buffer descriptor. */ + SwRcvRetConIdx = (SwRcvRetConIdx + 1) & + T3_RCV_RETURN_RCB_ENTRY_COUNT_MASK; + + /* Get the updated HwRcvRetProdIdx. */ + HwRcvRetProdIdx = pDevice->pStatusBlkVirt->Idx[0].RcvProdIdx; + } /* while */ + + pDevice->RcvRetConIdx = SwRcvRetConIdx; + + /* Update the receive return ring consumer index. */ + MB_REG_WR (pDevice, Mailbox.RcvRetConIdx[0].Low, SwRcvRetConIdx); +} /* LM_ServiceRxInterrupt */ /******************************************************************************/ /* Description: */ @@ -3972,207 +3675,180 @@ PLM_DEVICE_BLOCK pDevice) { /* Return: */ /* LM_STATUS_SUCCESS */ /******************************************************************************/ -LM_STATUS -LM_ServiceInterrupts( - PLM_DEVICE_BLOCK pDevice) +LM_STATUS LM_ServiceInterrupts (PLM_DEVICE_BLOCK pDevice) { - LM_UINT32 Value32; - int ServicePhyInt = FALSE; + LM_UINT32 Value32; + int ServicePhyInt = FALSE; - /* Setup the phy chip whenever the link status changes. */ - if(pDevice->LinkChngMode == T3_LINK_CHNG_MODE_USE_STATUS_REG) - { - Value32 = REG_RD(pDevice, MacCtrl.Status); - if(pDevice->PhyIntMode == T3_PHY_INT_MODE_MI_INTERRUPT) - { - if (Value32 & MAC_STATUS_MI_INTERRUPT) - { - ServicePhyInt = TRUE; - } + /* Setup the phy chip whenever the link status changes. */ + if (pDevice->LinkChngMode == T3_LINK_CHNG_MODE_USE_STATUS_REG) { + Value32 = REG_RD (pDevice, MacCtrl.Status); + if (pDevice->PhyIntMode == T3_PHY_INT_MODE_MI_INTERRUPT) { + if (Value32 & MAC_STATUS_MI_INTERRUPT) { + ServicePhyInt = TRUE; + } + } else if (Value32 & MAC_STATUS_LINK_STATE_CHANGED) { + ServicePhyInt = TRUE; + } + } else { + if (pDevice->pStatusBlkVirt-> + Status & STATUS_BLOCK_LINK_CHANGED_STATUS) { + pDevice->pStatusBlkVirt->Status = + STATUS_BLOCK_UPDATED | (pDevice->pStatusBlkVirt-> + Status & + ~STATUS_BLOCK_LINK_CHANGED_STATUS); + ServicePhyInt = TRUE; + } } - else if(Value32 & MAC_STATUS_LINK_STATE_CHANGED) - { - ServicePhyInt = TRUE; - } - } - else - { - if(pDevice->pStatusBlkVirt->Status & STATUS_BLOCK_LINK_CHANGED_STATUS) - { - pDevice->pStatusBlkVirt->Status = STATUS_BLOCK_UPDATED | - (pDevice->pStatusBlkVirt->Status & ~STATUS_BLOCK_LINK_CHANGED_STATUS); - ServicePhyInt = TRUE; - } - } #if INCLUDE_TBI_SUPPORT - if (pDevice->IgnoreTbiLinkChange == TRUE) - { - ServicePhyInt = FALSE; - } + if (pDevice->IgnoreTbiLinkChange == TRUE) { + ServicePhyInt = FALSE; + } #endif - if (ServicePhyInt == TRUE) - { - LM_SetupPhy(pDevice); - } - - /* Service receive and transmit interrupts. */ - LM_ServiceRxInterrupt(pDevice); - LM_ServiceTxInterrupt(pDevice); - - /* No spinlock for this queue since this routine is serialized. */ - if(!QQ_Empty(&pDevice->RxPacketReceivedQ.Container)) - { - /* Indicate receive packets. */ - MM_IndicateRxPackets(pDevice); - /* LM_QueueRxPackets(pDevice); */ - } - - /* No spinlock for this queue since this routine is serialized. */ - if(!QQ_Empty(&pDevice->TxPacketXmittedQ.Container)) - { - MM_IndicateTxPackets(pDevice); - } - - return LM_STATUS_SUCCESS; -} /* LM_ServiceInterrupts */ - - -/******************************************************************************/ -/* Description: */ -/* */ -/* Return: */ -/******************************************************************************/ -LM_STATUS -LM_MulticastAdd( -PLM_DEVICE_BLOCK pDevice, -PLM_UINT8 pMcAddress) { - PLM_UINT8 pEntry; - LM_UINT32 j; - - pEntry = pDevice->McTable[0]; - for(j = 0; j < pDevice->McEntryCount; j++) - { - if(IS_ETH_ADDRESS_EQUAL(pEntry, pMcAddress)) - { - /* Found a match, increment the instance count. */ - pEntry[LM_MC_INSTANCE_COUNT_INDEX] += 1; - - return LM_STATUS_SUCCESS; + if (ServicePhyInt == TRUE) { + LM_SetupPhy (pDevice); } - pEntry += LM_MC_ENTRY_SIZE; - } + /* Service receive and transmit interrupts. */ + LM_ServiceRxInterrupt (pDevice); + LM_ServiceTxInterrupt (pDevice); - if(pDevice->McEntryCount >= LM_MAX_MC_TABLE_SIZE) - { - return LM_STATUS_FAILURE; - } - - pEntry = pDevice->McTable[pDevice->McEntryCount]; - - COPY_ETH_ADDRESS(pMcAddress, pEntry); - pEntry[LM_MC_INSTANCE_COUNT_INDEX] = 1; - - pDevice->McEntryCount++; - - LM_SetReceiveMask(pDevice, pDevice->ReceiveMask | LM_ACCEPT_MULTICAST); - - return LM_STATUS_SUCCESS; -} /* LM_MulticastAdd */ - - -/******************************************************************************/ -/* Description: */ -/* */ -/* Return: */ -/******************************************************************************/ -LM_STATUS -LM_MulticastDel( -PLM_DEVICE_BLOCK pDevice, -PLM_UINT8 pMcAddress) { - PLM_UINT8 pEntry; - LM_UINT32 j; - - pEntry = pDevice->McTable[0]; - for(j = 0; j < pDevice->McEntryCount; j++) - { - if(IS_ETH_ADDRESS_EQUAL(pEntry, pMcAddress)) - { - /* Found a match, decrement the instance count. */ - pEntry[LM_MC_INSTANCE_COUNT_INDEX] -= 1; - - /* No more instance left, remove the address from the table. */ - /* Move the last entry in the table to the delete slot. */ - if(pEntry[LM_MC_INSTANCE_COUNT_INDEX] == 0 && - pDevice->McEntryCount > 1) - { - - COPY_ETH_ADDRESS( - pDevice->McTable[pDevice->McEntryCount-1], pEntry); - pEntry[LM_MC_INSTANCE_COUNT_INDEX] = - pDevice->McTable[pDevice->McEntryCount-1] - [LM_MC_INSTANCE_COUNT_INDEX]; - } - pDevice->McEntryCount--; - - /* Update the receive mask if the table is empty. */ - if(pDevice->McEntryCount == 0) - { - LM_SetReceiveMask(pDevice, - pDevice->ReceiveMask & ~LM_ACCEPT_MULTICAST); - } - - return LM_STATUS_SUCCESS; + /* No spinlock for this queue since this routine is serialized. */ + if (!QQ_Empty (&pDevice->RxPacketReceivedQ.Container)) { + /* Indicate receive packets. */ + MM_IndicateRxPackets (pDevice); + /* LM_QueueRxPackets(pDevice); */ } - pEntry += LM_MC_ENTRY_SIZE; - } - - return LM_STATUS_FAILURE; -} /* LM_MulticastDel */ + /* No spinlock for this queue since this routine is serialized. */ + if (!QQ_Empty (&pDevice->TxPacketXmittedQ.Container)) { + MM_IndicateTxPackets (pDevice); + } + return LM_STATUS_SUCCESS; +} /* LM_ServiceInterrupts */ /******************************************************************************/ /* Description: */ /* */ /* Return: */ /******************************************************************************/ -LM_STATUS -LM_MulticastClear( -PLM_DEVICE_BLOCK pDevice) { - pDevice->McEntryCount = 0; - - LM_SetReceiveMask(pDevice, pDevice->ReceiveMask & ~LM_ACCEPT_MULTICAST); - - return LM_STATUS_SUCCESS; -} /* LM_MulticastClear */ - - -/******************************************************************************/ -/* Description: */ -/* */ -/* Return: */ -/******************************************************************************/ -LM_STATUS -LM_SetMacAddress( - PLM_DEVICE_BLOCK pDevice, - PLM_UINT8 pMacAddress) +LM_STATUS LM_MulticastAdd (PLM_DEVICE_BLOCK pDevice, PLM_UINT8 pMcAddress) { - LM_UINT32 j; + PLM_UINT8 pEntry; + LM_UINT32 j; - for(j = 0; j < 4; j++) - { - REG_WR(pDevice, MacCtrl.MacAddr[j].High, - (pMacAddress[0] << 8) | pMacAddress[1]); - REG_WR(pDevice, MacCtrl.MacAddr[j].Low, - (pMacAddress[2] << 24) | (pMacAddress[3] << 16) | - (pMacAddress[4] << 8) | pMacAddress[5]); - } + pEntry = pDevice->McTable[0]; + for (j = 0; j < pDevice->McEntryCount; j++) { + if (IS_ETH_ADDRESS_EQUAL (pEntry, pMcAddress)) { + /* Found a match, increment the instance count. */ + pEntry[LM_MC_INSTANCE_COUNT_INDEX] += 1; - return LM_STATUS_SUCCESS; + return LM_STATUS_SUCCESS; + } + + pEntry += LM_MC_ENTRY_SIZE; + } + + if (pDevice->McEntryCount >= LM_MAX_MC_TABLE_SIZE) { + return LM_STATUS_FAILURE; + } + + pEntry = pDevice->McTable[pDevice->McEntryCount]; + + COPY_ETH_ADDRESS (pMcAddress, pEntry); + pEntry[LM_MC_INSTANCE_COUNT_INDEX] = 1; + + pDevice->McEntryCount++; + + LM_SetReceiveMask (pDevice, pDevice->ReceiveMask | LM_ACCEPT_MULTICAST); + + return LM_STATUS_SUCCESS; +} /* LM_MulticastAdd */ + +/******************************************************************************/ +/* Description: */ +/* */ +/* Return: */ +/******************************************************************************/ +LM_STATUS LM_MulticastDel (PLM_DEVICE_BLOCK pDevice, PLM_UINT8 pMcAddress) +{ + PLM_UINT8 pEntry; + LM_UINT32 j; + + pEntry = pDevice->McTable[0]; + for (j = 0; j < pDevice->McEntryCount; j++) { + if (IS_ETH_ADDRESS_EQUAL (pEntry, pMcAddress)) { + /* Found a match, decrement the instance count. */ + pEntry[LM_MC_INSTANCE_COUNT_INDEX] -= 1; + + /* No more instance left, remove the address from the table. */ + /* Move the last entry in the table to the delete slot. */ + if (pEntry[LM_MC_INSTANCE_COUNT_INDEX] == 0 && + pDevice->McEntryCount > 1) { + + COPY_ETH_ADDRESS (pDevice-> + McTable[pDevice-> + McEntryCount - 1], + pEntry); + pEntry[LM_MC_INSTANCE_COUNT_INDEX] = + pDevice->McTable[pDevice->McEntryCount - 1] + [LM_MC_INSTANCE_COUNT_INDEX]; + } + pDevice->McEntryCount--; + + /* Update the receive mask if the table is empty. */ + if (pDevice->McEntryCount == 0) { + LM_SetReceiveMask (pDevice, + pDevice-> + ReceiveMask & + ~LM_ACCEPT_MULTICAST); + } + + return LM_STATUS_SUCCESS; + } + + pEntry += LM_MC_ENTRY_SIZE; + } + + return LM_STATUS_FAILURE; +} /* LM_MulticastDel */ + +/******************************************************************************/ +/* Description: */ +/* */ +/* Return: */ +/******************************************************************************/ +LM_STATUS LM_MulticastClear (PLM_DEVICE_BLOCK pDevice) +{ + pDevice->McEntryCount = 0; + + LM_SetReceiveMask (pDevice, + pDevice->ReceiveMask & ~LM_ACCEPT_MULTICAST); + + return LM_STATUS_SUCCESS; +} /* LM_MulticastClear */ + +/******************************************************************************/ +/* Description: */ +/* */ +/* Return: */ +/******************************************************************************/ +LM_STATUS LM_SetMacAddress (PLM_DEVICE_BLOCK pDevice, PLM_UINT8 pMacAddress) +{ + LM_UINT32 j; + + for (j = 0; j < 4; j++) { + REG_WR (pDevice, MacCtrl.MacAddr[j].High, + (pMacAddress[0] << 8) | pMacAddress[1]); + REG_WR (pDevice, MacCtrl.MacAddr[j].Low, + (pMacAddress[2] << 24) | (pMacAddress[3] << 16) | + (pMacAddress[4] << 8) | pMacAddress[5]); + } + + return LM_STATUS_SUCCESS; } - /******************************************************************************/ /* Description: */ /* Sets up the default line speed, and duplex modes based on the requested */ @@ -4182,93 +3858,93 @@ LM_SetMacAddress( /* None. */ /******************************************************************************/ static LM_STATUS -LM_TranslateRequestedMediaType( -LM_REQUESTED_MEDIA_TYPE RequestedMediaType, -PLM_MEDIA_TYPE pMediaType, -PLM_LINE_SPEED pLineSpeed, -PLM_DUPLEX_MODE pDuplexMode) { - *pMediaType = LM_MEDIA_TYPE_AUTO; - *pLineSpeed = LM_LINE_SPEED_UNKNOWN; - *pDuplexMode = LM_DUPLEX_MODE_UNKNOWN; +LM_TranslateRequestedMediaType (LM_REQUESTED_MEDIA_TYPE RequestedMediaType, + PLM_MEDIA_TYPE pMediaType, + PLM_LINE_SPEED pLineSpeed, + PLM_DUPLEX_MODE pDuplexMode) +{ + *pMediaType = LM_MEDIA_TYPE_AUTO; + *pLineSpeed = LM_LINE_SPEED_UNKNOWN; + *pDuplexMode = LM_DUPLEX_MODE_UNKNOWN; - /* determine media type */ - switch(RequestedMediaType) { + /* determine media type */ + switch (RequestedMediaType) { case LM_REQUESTED_MEDIA_TYPE_BNC: - *pMediaType = LM_MEDIA_TYPE_BNC; - *pLineSpeed = LM_LINE_SPEED_10MBPS; - *pDuplexMode = LM_DUPLEX_MODE_HALF; - break; + *pMediaType = LM_MEDIA_TYPE_BNC; + *pLineSpeed = LM_LINE_SPEED_10MBPS; + *pDuplexMode = LM_DUPLEX_MODE_HALF; + break; case LM_REQUESTED_MEDIA_TYPE_UTP_AUTO: - *pMediaType = LM_MEDIA_TYPE_UTP; - break; + *pMediaType = LM_MEDIA_TYPE_UTP; + break; case LM_REQUESTED_MEDIA_TYPE_UTP_10MBPS: - *pMediaType = LM_MEDIA_TYPE_UTP; - *pLineSpeed = LM_LINE_SPEED_10MBPS; - *pDuplexMode = LM_DUPLEX_MODE_HALF; - break; + *pMediaType = LM_MEDIA_TYPE_UTP; + *pLineSpeed = LM_LINE_SPEED_10MBPS; + *pDuplexMode = LM_DUPLEX_MODE_HALF; + break; case LM_REQUESTED_MEDIA_TYPE_UTP_10MBPS_FULL_DUPLEX: - *pMediaType = LM_MEDIA_TYPE_UTP; - *pLineSpeed = LM_LINE_SPEED_10MBPS; - *pDuplexMode = LM_DUPLEX_MODE_FULL; - break; + *pMediaType = LM_MEDIA_TYPE_UTP; + *pLineSpeed = LM_LINE_SPEED_10MBPS; + *pDuplexMode = LM_DUPLEX_MODE_FULL; + break; case LM_REQUESTED_MEDIA_TYPE_UTP_100MBPS: - *pMediaType = LM_MEDIA_TYPE_UTP; - *pLineSpeed = LM_LINE_SPEED_100MBPS; - *pDuplexMode = LM_DUPLEX_MODE_HALF; - break; + *pMediaType = LM_MEDIA_TYPE_UTP; + *pLineSpeed = LM_LINE_SPEED_100MBPS; + *pDuplexMode = LM_DUPLEX_MODE_HALF; + break; case LM_REQUESTED_MEDIA_TYPE_UTP_100MBPS_FULL_DUPLEX: - *pMediaType = LM_MEDIA_TYPE_UTP; - *pLineSpeed = LM_LINE_SPEED_100MBPS; - *pDuplexMode = LM_DUPLEX_MODE_FULL; - break; + *pMediaType = LM_MEDIA_TYPE_UTP; + *pLineSpeed = LM_LINE_SPEED_100MBPS; + *pDuplexMode = LM_DUPLEX_MODE_FULL; + break; case LM_REQUESTED_MEDIA_TYPE_UTP_1000MBPS: - *pMediaType = LM_MEDIA_TYPE_UTP; - *pLineSpeed = LM_LINE_SPEED_1000MBPS; - *pDuplexMode = LM_DUPLEX_MODE_HALF; - break; + *pMediaType = LM_MEDIA_TYPE_UTP; + *pLineSpeed = LM_LINE_SPEED_1000MBPS; + *pDuplexMode = LM_DUPLEX_MODE_HALF; + break; case LM_REQUESTED_MEDIA_TYPE_UTP_1000MBPS_FULL_DUPLEX: - *pMediaType = LM_MEDIA_TYPE_UTP; - *pLineSpeed = LM_LINE_SPEED_1000MBPS; - *pDuplexMode = LM_DUPLEX_MODE_FULL; - break; + *pMediaType = LM_MEDIA_TYPE_UTP; + *pLineSpeed = LM_LINE_SPEED_1000MBPS; + *pDuplexMode = LM_DUPLEX_MODE_FULL; + break; case LM_REQUESTED_MEDIA_TYPE_FIBER_100MBPS: - *pMediaType = LM_MEDIA_TYPE_FIBER; - *pLineSpeed = LM_LINE_SPEED_100MBPS; - *pDuplexMode = LM_DUPLEX_MODE_HALF; - break; + *pMediaType = LM_MEDIA_TYPE_FIBER; + *pLineSpeed = LM_LINE_SPEED_100MBPS; + *pDuplexMode = LM_DUPLEX_MODE_HALF; + break; case LM_REQUESTED_MEDIA_TYPE_FIBER_100MBPS_FULL_DUPLEX: - *pMediaType = LM_MEDIA_TYPE_FIBER; - *pLineSpeed = LM_LINE_SPEED_100MBPS; - *pDuplexMode = LM_DUPLEX_MODE_FULL; - break; + *pMediaType = LM_MEDIA_TYPE_FIBER; + *pLineSpeed = LM_LINE_SPEED_100MBPS; + *pDuplexMode = LM_DUPLEX_MODE_FULL; + break; case LM_REQUESTED_MEDIA_TYPE_FIBER_1000MBPS: - *pMediaType = LM_MEDIA_TYPE_FIBER; - *pLineSpeed = LM_LINE_SPEED_1000MBPS; - *pDuplexMode = LM_DUPLEX_MODE_HALF; - break; + *pMediaType = LM_MEDIA_TYPE_FIBER; + *pLineSpeed = LM_LINE_SPEED_1000MBPS; + *pDuplexMode = LM_DUPLEX_MODE_HALF; + break; case LM_REQUESTED_MEDIA_TYPE_FIBER_1000MBPS_FULL_DUPLEX: - *pMediaType = LM_MEDIA_TYPE_FIBER; - *pLineSpeed = LM_LINE_SPEED_1000MBPS; - *pDuplexMode = LM_DUPLEX_MODE_FULL; - break; + *pMediaType = LM_MEDIA_TYPE_FIBER; + *pLineSpeed = LM_LINE_SPEED_1000MBPS; + *pDuplexMode = LM_DUPLEX_MODE_FULL; + break; default: - break; - } /* switch */ + break; + } /* switch */ - return LM_STATUS_SUCCESS; -} /* LM_TranslateRequestedMediaType */ + return LM_STATUS_SUCCESS; +} /* LM_TranslateRequestedMediaType */ /******************************************************************************/ /* Description: */ @@ -4277,285 +3953,284 @@ PLM_DUPLEX_MODE pDuplexMode) { /* LM_STATUS_LINK_ACTIVE */ /* LM_STATUS_LINK_DOWN */ /******************************************************************************/ -static LM_STATUS -LM_InitBcm540xPhy( -PLM_DEVICE_BLOCK pDevice) +static LM_STATUS LM_InitBcm540xPhy (PLM_DEVICE_BLOCK pDevice) { - LM_LINE_SPEED CurrentLineSpeed; - LM_DUPLEX_MODE CurrentDuplexMode; - LM_STATUS CurrentLinkStatus; - LM_UINT32 Value32; - LM_UINT32 j; + LM_LINE_SPEED CurrentLineSpeed; + LM_DUPLEX_MODE CurrentDuplexMode; + LM_STATUS CurrentLinkStatus; + LM_UINT32 Value32; + LM_UINT32 j; -#if 1 /* jmb: bugfix -- moved here, out of code that sets initial pwr state */ - LM_WritePhy(pDevice, BCM5401_AUX_CTRL, 0x2); +#if 1 /* jmb: bugfix -- moved here, out of code that sets initial pwr state */ + LM_WritePhy (pDevice, BCM5401_AUX_CTRL, 0x2); #endif - if((pDevice->PhyId & PHY_ID_MASK) == PHY_BCM5401_PHY_ID) - { - LM_ReadPhy(pDevice, PHY_STATUS_REG, &Value32); - LM_ReadPhy(pDevice, PHY_STATUS_REG, &Value32); + if ((pDevice->PhyId & PHY_ID_MASK) == PHY_BCM5401_PHY_ID) { + LM_ReadPhy (pDevice, PHY_STATUS_REG, &Value32); + LM_ReadPhy (pDevice, PHY_STATUS_REG, &Value32); - if(!pDevice->InitDone) - { - Value32 = 0; - } - - if(!(Value32 & PHY_STATUS_LINK_PASS)) - { - LM_WritePhy(pDevice, BCM5401_AUX_CTRL, 0x0c20); - - LM_WritePhy(pDevice, BCM540X_DSP_ADDRESS_REG, 0x0012); - LM_WritePhy(pDevice, BCM540X_DSP_RW_PORT, 0x1804); - - LM_WritePhy(pDevice, BCM540X_DSP_ADDRESS_REG, 0x0013); - LM_WritePhy(pDevice, BCM540X_DSP_RW_PORT, 0x1204); - - LM_WritePhy(pDevice, BCM540X_DSP_ADDRESS_REG, 0x8006); - LM_WritePhy(pDevice, BCM540X_DSP_RW_PORT, 0x0132); - - LM_WritePhy(pDevice, BCM540X_DSP_ADDRESS_REG, 0x8006); - LM_WritePhy(pDevice, BCM540X_DSP_RW_PORT, 0x0232); - - LM_WritePhy(pDevice, BCM540X_DSP_ADDRESS_REG, 0x201f); - LM_WritePhy(pDevice, BCM540X_DSP_RW_PORT, 0x0a20); - - LM_ReadPhy(pDevice, PHY_STATUS_REG, &Value32); - for(j = 0; j < 1000; j++) - { - MM_Wait(10); - - LM_ReadPhy(pDevice, PHY_STATUS_REG, &Value32); - if(Value32 & PHY_STATUS_LINK_PASS) - { - MM_Wait(40); - break; + if (!pDevice->InitDone) { + Value32 = 0; } - } - if((pDevice->PhyId & PHY_ID_REV_MASK) == PHY_BCM5401_B0_REV) - { - if(!(Value32 & PHY_STATUS_LINK_PASS) && - (pDevice->OldLineSpeed == LM_LINE_SPEED_1000MBPS)) - { - LM_WritePhy(pDevice, PHY_CTRL_REG, PHY_CTRL_PHY_RESET); - for(j = 0; j < 100; j++) - { - MM_Wait(10); + if (!(Value32 & PHY_STATUS_LINK_PASS)) { + LM_WritePhy (pDevice, BCM5401_AUX_CTRL, 0x0c20); - LM_ReadPhy(pDevice, PHY_CTRL_REG, &Value32); - if(!(Value32 & PHY_CTRL_PHY_RESET)) - { - MM_Wait(40); - break; + LM_WritePhy (pDevice, BCM540X_DSP_ADDRESS_REG, 0x0012); + LM_WritePhy (pDevice, BCM540X_DSP_RW_PORT, 0x1804); + + LM_WritePhy (pDevice, BCM540X_DSP_ADDRESS_REG, 0x0013); + LM_WritePhy (pDevice, BCM540X_DSP_RW_PORT, 0x1204); + + LM_WritePhy (pDevice, BCM540X_DSP_ADDRESS_REG, 0x8006); + LM_WritePhy (pDevice, BCM540X_DSP_RW_PORT, 0x0132); + + LM_WritePhy (pDevice, BCM540X_DSP_ADDRESS_REG, 0x8006); + LM_WritePhy (pDevice, BCM540X_DSP_RW_PORT, 0x0232); + + LM_WritePhy (pDevice, BCM540X_DSP_ADDRESS_REG, 0x201f); + LM_WritePhy (pDevice, BCM540X_DSP_RW_PORT, 0x0a20); + + LM_ReadPhy (pDevice, PHY_STATUS_REG, &Value32); + for (j = 0; j < 1000; j++) { + MM_Wait (10); + + LM_ReadPhy (pDevice, PHY_STATUS_REG, &Value32); + if (Value32 & PHY_STATUS_LINK_PASS) { + MM_Wait (40); + break; + } } - } - LM_WritePhy(pDevice, BCM5401_AUX_CTRL, 0x0c20); + if ((pDevice->PhyId & PHY_ID_REV_MASK) == + PHY_BCM5401_B0_REV) { + if (!(Value32 & PHY_STATUS_LINK_PASS) + && (pDevice->OldLineSpeed == + LM_LINE_SPEED_1000MBPS)) { + LM_WritePhy (pDevice, PHY_CTRL_REG, + PHY_CTRL_PHY_RESET); + for (j = 0; j < 100; j++) { + MM_Wait (10); - LM_WritePhy(pDevice, BCM540X_DSP_ADDRESS_REG, 0x0012); - LM_WritePhy(pDevice, BCM540X_DSP_RW_PORT, 0x1804); + LM_ReadPhy (pDevice, + PHY_CTRL_REG, + &Value32); + if (! + (Value32 & + PHY_CTRL_PHY_RESET)) { + MM_Wait (40); + break; + } + } - LM_WritePhy(pDevice, BCM540X_DSP_ADDRESS_REG, 0x0013); - LM_WritePhy(pDevice, BCM540X_DSP_RW_PORT, 0x1204); + LM_WritePhy (pDevice, BCM5401_AUX_CTRL, + 0x0c20); - LM_WritePhy(pDevice, BCM540X_DSP_ADDRESS_REG, 0x8006); - LM_WritePhy(pDevice, BCM540X_DSP_RW_PORT, 0x0132); + LM_WritePhy (pDevice, + BCM540X_DSP_ADDRESS_REG, + 0x0012); + LM_WritePhy (pDevice, + BCM540X_DSP_RW_PORT, + 0x1804); - LM_WritePhy(pDevice, BCM540X_DSP_ADDRESS_REG, 0x8006); - LM_WritePhy(pDevice, BCM540X_DSP_RW_PORT, 0x0232); + LM_WritePhy (pDevice, + BCM540X_DSP_ADDRESS_REG, + 0x0013); + LM_WritePhy (pDevice, + BCM540X_DSP_RW_PORT, + 0x1204); - LM_WritePhy(pDevice, BCM540X_DSP_ADDRESS_REG, 0x201f); - LM_WritePhy(pDevice, BCM540X_DSP_RW_PORT, 0x0a20); + LM_WritePhy (pDevice, + BCM540X_DSP_ADDRESS_REG, + 0x8006); + LM_WritePhy (pDevice, + BCM540X_DSP_RW_PORT, + 0x0132); + + LM_WritePhy (pDevice, + BCM540X_DSP_ADDRESS_REG, + 0x8006); + LM_WritePhy (pDevice, + BCM540X_DSP_RW_PORT, + 0x0232); + + LM_WritePhy (pDevice, + BCM540X_DSP_ADDRESS_REG, + 0x201f); + LM_WritePhy (pDevice, + BCM540X_DSP_RW_PORT, + 0x0a20); + } + } } - } - } - } - else if(pDevice->ChipRevId == T3_CHIP_ID_5701_A0 || - pDevice->ChipRevId == T3_CHIP_ID_5701_B0) - { - /* Bug: 5701 A0, B0 TX CRC workaround. */ - LM_WritePhy(pDevice, 0x15, 0x0a75); - LM_WritePhy(pDevice, 0x1c, 0x8c68); - LM_WritePhy(pDevice, 0x1c, 0x8d68); - LM_WritePhy(pDevice, 0x1c, 0x8c68); - } - - /* Acknowledge interrupts. */ - LM_ReadPhy(pDevice, BCM540X_INT_STATUS_REG, &Value32); - LM_ReadPhy(pDevice, BCM540X_INT_STATUS_REG, &Value32); - - /* Configure the interrupt mask. */ - if(pDevice->PhyIntMode == T3_PHY_INT_MODE_MI_INTERRUPT) - { - LM_WritePhy(pDevice, BCM540X_INT_MASK_REG, ~BCM540X_INT_LINK_CHANGE); - } - - /* Configure PHY led mode. */ - if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5701 || - (T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700)) - { - if(pDevice->LedMode == LED_MODE_THREE_LINK) - { - LM_WritePhy(pDevice, BCM540X_EXT_CTRL_REG, - BCM540X_EXT_CTRL_LINK3_LED_MODE); - } - else - { - LM_WritePhy(pDevice, BCM540X_EXT_CTRL_REG, 0); - } - } - - CurrentLinkStatus = LM_STATUS_LINK_DOWN; - - /* Get current link and duplex mode. */ - for(j = 0; j < 100; j++) - { - LM_ReadPhy(pDevice, PHY_STATUS_REG, &Value32); - LM_ReadPhy(pDevice, PHY_STATUS_REG, &Value32); - - if(Value32 & PHY_STATUS_LINK_PASS) - { - break; - } - MM_Wait(40); - } - - if(Value32 & PHY_STATUS_LINK_PASS) - { - - /* Determine the current line and duplex settings. */ - LM_ReadPhy(pDevice, BCM540X_AUX_STATUS_REG, &Value32); - for(j = 0; j < 2000; j++) - { - MM_Wait(10); - - LM_ReadPhy(pDevice, BCM540X_AUX_STATUS_REG, &Value32); - if(Value32) - { - break; - } + } else if (pDevice->ChipRevId == T3_CHIP_ID_5701_A0 || + pDevice->ChipRevId == T3_CHIP_ID_5701_B0) { + /* Bug: 5701 A0, B0 TX CRC workaround. */ + LM_WritePhy (pDevice, 0x15, 0x0a75); + LM_WritePhy (pDevice, 0x1c, 0x8c68); + LM_WritePhy (pDevice, 0x1c, 0x8d68); + LM_WritePhy (pDevice, 0x1c, 0x8c68); } - switch(Value32 & BCM540X_AUX_SPEED_MASK) - { - case BCM540X_AUX_10BASET_HD: - CurrentLineSpeed = LM_LINE_SPEED_10MBPS; - CurrentDuplexMode = LM_DUPLEX_MODE_HALF; - break; + /* Acknowledge interrupts. */ + LM_ReadPhy (pDevice, BCM540X_INT_STATUS_REG, &Value32); + LM_ReadPhy (pDevice, BCM540X_INT_STATUS_REG, &Value32); - case BCM540X_AUX_10BASET_FD: - CurrentLineSpeed = LM_LINE_SPEED_10MBPS; - CurrentDuplexMode = LM_DUPLEX_MODE_FULL; - break; - - case BCM540X_AUX_100BASETX_HD: - CurrentLineSpeed = LM_LINE_SPEED_100MBPS; - CurrentDuplexMode = LM_DUPLEX_MODE_HALF; - break; - - case BCM540X_AUX_100BASETX_FD: - CurrentLineSpeed = LM_LINE_SPEED_100MBPS; - CurrentDuplexMode = LM_DUPLEX_MODE_FULL; - break; - - case BCM540X_AUX_100BASET_HD: - CurrentLineSpeed = LM_LINE_SPEED_1000MBPS; - CurrentDuplexMode = LM_DUPLEX_MODE_HALF; - break; - - case BCM540X_AUX_100BASET_FD: - CurrentLineSpeed = LM_LINE_SPEED_1000MBPS; - CurrentDuplexMode = LM_DUPLEX_MODE_FULL; - break; - - default: - - CurrentLineSpeed = LM_LINE_SPEED_UNKNOWN; - CurrentDuplexMode = LM_DUPLEX_MODE_UNKNOWN; - break; + /* Configure the interrupt mask. */ + if (pDevice->PhyIntMode == T3_PHY_INT_MODE_MI_INTERRUPT) { + LM_WritePhy (pDevice, BCM540X_INT_MASK_REG, + ~BCM540X_INT_LINK_CHANGE); } - /* Make sure we are in auto-neg mode. */ - for (j = 0; j < 200; j++) - { - LM_ReadPhy(pDevice, PHY_CTRL_REG, &Value32); - if(Value32 && Value32 != 0x7fff) - { - break; - } - - if(Value32 == 0 && pDevice->RequestedMediaType == - LM_REQUESTED_MEDIA_TYPE_UTP_10MBPS) - { - break; - } - - MM_Wait(10); - } - - /* Use the current line settings for "auto" mode. */ - if(pDevice->RequestedMediaType == LM_REQUESTED_MEDIA_TYPE_AUTO || - pDevice->RequestedMediaType == LM_REQUESTED_MEDIA_TYPE_UTP_AUTO) - { - if(Value32 & PHY_CTRL_AUTO_NEG_ENABLE) - { - CurrentLinkStatus = LM_STATUS_LINK_ACTIVE; - - /* We may be exiting low power mode and the link is in */ - /* 10mb. In this case, we need to restart autoneg. */ - LM_ReadPhy(pDevice, BCM540X_1000BASET_CTRL_REG, &Value32); - pDevice->advertising1000 = Value32; - /* 5702FE supports 10/100Mb only. */ - if(T3_ASIC_REV(pDevice->ChipRevId) != T3_ASIC_REV_5703 || - pDevice->BondId != GRC_MISC_BD_ID_5702FE) - { - if(!(Value32 & (BCM540X_AN_AD_1000BASET_HALF | - BCM540X_AN_AD_1000BASET_FULL))) - { - CurrentLinkStatus = LM_STATUS_LINK_SETTING_MISMATCH; - } + /* Configure PHY led mode. */ + if (T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5701 || + (T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5700)) { + if (pDevice->LedMode == LED_MODE_THREE_LINK) { + LM_WritePhy (pDevice, BCM540X_EXT_CTRL_REG, + BCM540X_EXT_CTRL_LINK3_LED_MODE); + } else { + LM_WritePhy (pDevice, BCM540X_EXT_CTRL_REG, 0); } - } - else - { - CurrentLinkStatus = LM_STATUS_LINK_SETTING_MISMATCH; - } - } - else - { - /* Force line settings. */ - /* Use the current setting if it matches the user's requested */ - /* setting. */ - LM_ReadPhy(pDevice, PHY_CTRL_REG, &Value32); - if((pDevice->LineSpeed == CurrentLineSpeed) && - (pDevice->DuplexMode == CurrentDuplexMode)) - { - if ((pDevice->DisableAutoNeg && - !(Value32 & PHY_CTRL_AUTO_NEG_ENABLE)) || - (!pDevice->DisableAutoNeg && - (Value32 & PHY_CTRL_AUTO_NEG_ENABLE))) - { - CurrentLinkStatus = LM_STATUS_LINK_ACTIVE; - } - else - { - CurrentLinkStatus = LM_STATUS_LINK_SETTING_MISMATCH; - } - } - else - { - CurrentLinkStatus = LM_STATUS_LINK_SETTING_MISMATCH; - } } - /* Save line settings. */ - pDevice->LineSpeed = CurrentLineSpeed; - pDevice->DuplexMode = CurrentDuplexMode; - pDevice->MediaType = LM_MEDIA_TYPE_UTP; - } + CurrentLinkStatus = LM_STATUS_LINK_DOWN; - return CurrentLinkStatus; -} /* LM_InitBcm540xPhy */ + /* Get current link and duplex mode. */ + for (j = 0; j < 100; j++) { + LM_ReadPhy (pDevice, PHY_STATUS_REG, &Value32); + LM_ReadPhy (pDevice, PHY_STATUS_REG, &Value32); + + if (Value32 & PHY_STATUS_LINK_PASS) { + break; + } + MM_Wait (40); + } + + if (Value32 & PHY_STATUS_LINK_PASS) { + + /* Determine the current line and duplex settings. */ + LM_ReadPhy (pDevice, BCM540X_AUX_STATUS_REG, &Value32); + for (j = 0; j < 2000; j++) { + MM_Wait (10); + + LM_ReadPhy (pDevice, BCM540X_AUX_STATUS_REG, &Value32); + if (Value32) { + break; + } + } + + switch (Value32 & BCM540X_AUX_SPEED_MASK) { + case BCM540X_AUX_10BASET_HD: + CurrentLineSpeed = LM_LINE_SPEED_10MBPS; + CurrentDuplexMode = LM_DUPLEX_MODE_HALF; + break; + + case BCM540X_AUX_10BASET_FD: + CurrentLineSpeed = LM_LINE_SPEED_10MBPS; + CurrentDuplexMode = LM_DUPLEX_MODE_FULL; + break; + + case BCM540X_AUX_100BASETX_HD: + CurrentLineSpeed = LM_LINE_SPEED_100MBPS; + CurrentDuplexMode = LM_DUPLEX_MODE_HALF; + break; + + case BCM540X_AUX_100BASETX_FD: + CurrentLineSpeed = LM_LINE_SPEED_100MBPS; + CurrentDuplexMode = LM_DUPLEX_MODE_FULL; + break; + + case BCM540X_AUX_100BASET_HD: + CurrentLineSpeed = LM_LINE_SPEED_1000MBPS; + CurrentDuplexMode = LM_DUPLEX_MODE_HALF; + break; + + case BCM540X_AUX_100BASET_FD: + CurrentLineSpeed = LM_LINE_SPEED_1000MBPS; + CurrentDuplexMode = LM_DUPLEX_MODE_FULL; + break; + + default: + + CurrentLineSpeed = LM_LINE_SPEED_UNKNOWN; + CurrentDuplexMode = LM_DUPLEX_MODE_UNKNOWN; + break; + } + + /* Make sure we are in auto-neg mode. */ + for (j = 0; j < 200; j++) { + LM_ReadPhy (pDevice, PHY_CTRL_REG, &Value32); + if (Value32 && Value32 != 0x7fff) { + break; + } + + if (Value32 == 0 && pDevice->RequestedMediaType == + LM_REQUESTED_MEDIA_TYPE_UTP_10MBPS) { + break; + } + + MM_Wait (10); + } + + /* Use the current line settings for "auto" mode. */ + if (pDevice->RequestedMediaType == LM_REQUESTED_MEDIA_TYPE_AUTO + || pDevice->RequestedMediaType == + LM_REQUESTED_MEDIA_TYPE_UTP_AUTO) { + if (Value32 & PHY_CTRL_AUTO_NEG_ENABLE) { + CurrentLinkStatus = LM_STATUS_LINK_ACTIVE; + + /* We may be exiting low power mode and the link is in */ + /* 10mb. In this case, we need to restart autoneg. */ + LM_ReadPhy (pDevice, BCM540X_1000BASET_CTRL_REG, + &Value32); + pDevice->advertising1000 = Value32; + /* 5702FE supports 10/100Mb only. */ + if (T3_ASIC_REV (pDevice->ChipRevId) != + T3_ASIC_REV_5703 + || pDevice->BondId != + GRC_MISC_BD_ID_5702FE) { + if (! + (Value32 & + (BCM540X_AN_AD_1000BASET_HALF | + BCM540X_AN_AD_1000BASET_FULL))) { + CurrentLinkStatus = + LM_STATUS_LINK_SETTING_MISMATCH; + } + } + } else { + CurrentLinkStatus = + LM_STATUS_LINK_SETTING_MISMATCH; + } + } else { + /* Force line settings. */ + /* Use the current setting if it matches the user's requested */ + /* setting. */ + LM_ReadPhy (pDevice, PHY_CTRL_REG, &Value32); + if ((pDevice->LineSpeed == CurrentLineSpeed) && + (pDevice->DuplexMode == CurrentDuplexMode)) { + if ((pDevice->DisableAutoNeg && + !(Value32 & PHY_CTRL_AUTO_NEG_ENABLE)) || + (!pDevice->DisableAutoNeg && + (Value32 & PHY_CTRL_AUTO_NEG_ENABLE))) { + CurrentLinkStatus = + LM_STATUS_LINK_ACTIVE; + } else { + CurrentLinkStatus = + LM_STATUS_LINK_SETTING_MISMATCH; + } + } else { + CurrentLinkStatus = + LM_STATUS_LINK_SETTING_MISMATCH; + } + } + + /* Save line settings. */ + pDevice->LineSpeed = CurrentLineSpeed; + pDevice->DuplexMode = CurrentDuplexMode; + pDevice->MediaType = LM_MEDIA_TYPE_UTP; + } + + return CurrentLinkStatus; +} /* LM_InitBcm540xPhy */ /******************************************************************************/ /* Description: */ @@ -4563,1065 +4238,935 @@ PLM_DEVICE_BLOCK pDevice) /* Return: */ /******************************************************************************/ LM_STATUS -LM_SetFlowControl( - PLM_DEVICE_BLOCK pDevice, - LM_UINT32 LocalPhyAd, - LM_UINT32 RemotePhyAd) +LM_SetFlowControl (PLM_DEVICE_BLOCK pDevice, + LM_UINT32 LocalPhyAd, LM_UINT32 RemotePhyAd) { - LM_FLOW_CONTROL FlowCap; + LM_FLOW_CONTROL FlowCap; - /* Resolve flow control. */ - FlowCap = LM_FLOW_CONTROL_NONE; + /* Resolve flow control. */ + FlowCap = LM_FLOW_CONTROL_NONE; - /* See Table 28B-3 of 802.3ab-1999 spec. */ - if(pDevice->FlowControlCap & LM_FLOW_CONTROL_AUTO_PAUSE) - { - if(LocalPhyAd & PHY_AN_AD_PAUSE_CAPABLE) - { - if(LocalPhyAd & PHY_AN_AD_ASYM_PAUSE) - { - if(RemotePhyAd & PHY_LINK_PARTNER_PAUSE_CAPABLE) - { - FlowCap = LM_FLOW_CONTROL_TRANSMIT_PAUSE | - LM_FLOW_CONTROL_RECEIVE_PAUSE; + /* See Table 28B-3 of 802.3ab-1999 spec. */ + if (pDevice->FlowControlCap & LM_FLOW_CONTROL_AUTO_PAUSE) { + if (LocalPhyAd & PHY_AN_AD_PAUSE_CAPABLE) { + if (LocalPhyAd & PHY_AN_AD_ASYM_PAUSE) { + if (RemotePhyAd & + PHY_LINK_PARTNER_PAUSE_CAPABLE) { + FlowCap = + LM_FLOW_CONTROL_TRANSMIT_PAUSE | + LM_FLOW_CONTROL_RECEIVE_PAUSE; + } else if (RemotePhyAd & + PHY_LINK_PARTNER_ASYM_PAUSE) { + FlowCap = LM_FLOW_CONTROL_RECEIVE_PAUSE; + } + } else { + if (RemotePhyAd & + PHY_LINK_PARTNER_PAUSE_CAPABLE) { + FlowCap = + LM_FLOW_CONTROL_TRANSMIT_PAUSE | + LM_FLOW_CONTROL_RECEIVE_PAUSE; + } + } + } else if (LocalPhyAd & PHY_AN_AD_ASYM_PAUSE) { + if ((RemotePhyAd & PHY_LINK_PARTNER_PAUSE_CAPABLE) && + (RemotePhyAd & PHY_LINK_PARTNER_ASYM_PAUSE)) { + FlowCap = LM_FLOW_CONTROL_TRANSMIT_PAUSE; + } } - else if(RemotePhyAd & PHY_LINK_PARTNER_ASYM_PAUSE) - { - FlowCap = LM_FLOW_CONTROL_RECEIVE_PAUSE; - } - } - else - { - if(RemotePhyAd & PHY_LINK_PARTNER_PAUSE_CAPABLE) - { - FlowCap = LM_FLOW_CONTROL_TRANSMIT_PAUSE | - LM_FLOW_CONTROL_RECEIVE_PAUSE; - } - } + } else { + FlowCap = pDevice->FlowControlCap; } - else if(LocalPhyAd & PHY_AN_AD_ASYM_PAUSE) - { - if((RemotePhyAd & PHY_LINK_PARTNER_PAUSE_CAPABLE) && - (RemotePhyAd & PHY_LINK_PARTNER_ASYM_PAUSE)) - { - FlowCap = LM_FLOW_CONTROL_TRANSMIT_PAUSE; - } + + /* Enable/disable rx PAUSE. */ + pDevice->RxMode &= ~RX_MODE_ENABLE_FLOW_CONTROL; + if (FlowCap & LM_FLOW_CONTROL_RECEIVE_PAUSE && + (pDevice->FlowControlCap == LM_FLOW_CONTROL_AUTO_PAUSE || + pDevice->FlowControlCap & LM_FLOW_CONTROL_RECEIVE_PAUSE)) { + pDevice->FlowControl |= LM_FLOW_CONTROL_RECEIVE_PAUSE; + pDevice->RxMode |= RX_MODE_ENABLE_FLOW_CONTROL; + } - } - else - { - FlowCap = pDevice->FlowControlCap; - } + REG_WR (pDevice, MacCtrl.RxMode, pDevice->RxMode); - /* Enable/disable rx PAUSE. */ - pDevice->RxMode &= ~RX_MODE_ENABLE_FLOW_CONTROL; - if(FlowCap & LM_FLOW_CONTROL_RECEIVE_PAUSE && - (pDevice->FlowControlCap == LM_FLOW_CONTROL_AUTO_PAUSE || - pDevice->FlowControlCap & LM_FLOW_CONTROL_RECEIVE_PAUSE)) - { - pDevice->FlowControl |= LM_FLOW_CONTROL_RECEIVE_PAUSE; - pDevice->RxMode |= RX_MODE_ENABLE_FLOW_CONTROL; + /* Enable/disable tx PAUSE. */ + pDevice->TxMode &= ~TX_MODE_ENABLE_FLOW_CONTROL; + if (FlowCap & LM_FLOW_CONTROL_TRANSMIT_PAUSE && + (pDevice->FlowControlCap == LM_FLOW_CONTROL_AUTO_PAUSE || + pDevice->FlowControlCap & LM_FLOW_CONTROL_TRANSMIT_PAUSE)) { + pDevice->FlowControl |= LM_FLOW_CONTROL_TRANSMIT_PAUSE; + pDevice->TxMode |= TX_MODE_ENABLE_FLOW_CONTROL; - } - REG_WR(pDevice, MacCtrl.RxMode, pDevice->RxMode); + } + REG_WR (pDevice, MacCtrl.TxMode, pDevice->TxMode); - /* Enable/disable tx PAUSE. */ - pDevice->TxMode &= ~TX_MODE_ENABLE_FLOW_CONTROL; - if(FlowCap & LM_FLOW_CONTROL_TRANSMIT_PAUSE && - (pDevice->FlowControlCap == LM_FLOW_CONTROL_AUTO_PAUSE || - pDevice->FlowControlCap & LM_FLOW_CONTROL_TRANSMIT_PAUSE)) - { - pDevice->FlowControl |= LM_FLOW_CONTROL_TRANSMIT_PAUSE; - pDevice->TxMode |= TX_MODE_ENABLE_FLOW_CONTROL; - - } - REG_WR(pDevice, MacCtrl.TxMode, pDevice->TxMode); - - return LM_STATUS_SUCCESS; + return LM_STATUS_SUCCESS; } - #if INCLUDE_TBI_SUPPORT /******************************************************************************/ /* Description: */ /* */ /* Return: */ /******************************************************************************/ -STATIC LM_STATUS -LM_InitBcm800xPhy( - PLM_DEVICE_BLOCK pDevice) +STATIC LM_STATUS LM_InitBcm800xPhy (PLM_DEVICE_BLOCK pDevice) { - LM_UINT32 Value32; - LM_UINT32 j; + LM_UINT32 Value32; + LM_UINT32 j; - Value32 = REG_RD(pDevice, MacCtrl.Status); + Value32 = REG_RD (pDevice, MacCtrl.Status); - /* Reset the SERDES during init and when we have link. */ - if(!pDevice->InitDone || Value32 & MAC_STATUS_PCS_SYNCED) - { - /* Set PLL lock range. */ - LM_WritePhy(pDevice, 0x16, 0x8007); + /* Reset the SERDES during init and when we have link. */ + if (!pDevice->InitDone || Value32 & MAC_STATUS_PCS_SYNCED) { + /* Set PLL lock range. */ + LM_WritePhy (pDevice, 0x16, 0x8007); - /* Software reset. */ - LM_WritePhy(pDevice, 0x00, 0x8000); + /* Software reset. */ + LM_WritePhy (pDevice, 0x00, 0x8000); - /* Wait for reset to complete. */ - for(j = 0; j < 500; j++) - { - MM_Wait(10); + /* Wait for reset to complete. */ + for (j = 0; j < 500; j++) { + MM_Wait (10); + } + + /* Config mode; seletct PMA/Ch 1 regs. */ + LM_WritePhy (pDevice, 0x10, 0x8411); + + /* Enable auto-lock and comdet, select txclk for tx. */ + LM_WritePhy (pDevice, 0x11, 0x0a10); + + LM_WritePhy (pDevice, 0x18, 0x00a0); + LM_WritePhy (pDevice, 0x16, 0x41ff); + + /* Assert and deassert POR. */ + LM_WritePhy (pDevice, 0x13, 0x0400); + MM_Wait (40); + LM_WritePhy (pDevice, 0x13, 0x0000); + + LM_WritePhy (pDevice, 0x11, 0x0a50); + MM_Wait (40); + LM_WritePhy (pDevice, 0x11, 0x0a10); + + /* Delay for signal to stabilize. */ + for (j = 0; j < 15000; j++) { + MM_Wait (10); + } + + /* Deselect the channel register so we can read the PHY id later. */ + LM_WritePhy (pDevice, 0x10, 0x8011); } - /* Config mode; seletct PMA/Ch 1 regs. */ - LM_WritePhy(pDevice, 0x10, 0x8411); - - /* Enable auto-lock and comdet, select txclk for tx. */ - LM_WritePhy(pDevice, 0x11, 0x0a10); - - LM_WritePhy(pDevice, 0x18, 0x00a0); - LM_WritePhy(pDevice, 0x16, 0x41ff); - - /* Assert and deassert POR. */ - LM_WritePhy(pDevice, 0x13, 0x0400); - MM_Wait(40); - LM_WritePhy(pDevice, 0x13, 0x0000); - - LM_WritePhy(pDevice, 0x11, 0x0a50); - MM_Wait(40); - LM_WritePhy(pDevice, 0x11, 0x0a10); - - /* Delay for signal to stabilize. */ - for(j = 0; j < 15000; j++) - { - MM_Wait(10); - } - - /* Deselect the channel register so we can read the PHY id later. */ - LM_WritePhy(pDevice, 0x10, 0x8011); - } - - return LM_STATUS_SUCCESS; + return LM_STATUS_SUCCESS; } - /******************************************************************************/ /* Description: */ /* */ /* Return: */ /******************************************************************************/ -STATIC LM_STATUS -LM_SetupFiberPhy( - PLM_DEVICE_BLOCK pDevice) +STATIC LM_STATUS LM_SetupFiberPhy (PLM_DEVICE_BLOCK pDevice) { - LM_STATUS CurrentLinkStatus; - AUTONEG_STATUS AnStatus = 0; - LM_UINT32 Value32; - LM_UINT32 Cnt; - LM_UINT32 j, k; + LM_STATUS CurrentLinkStatus; + AUTONEG_STATUS AnStatus = 0; + LM_UINT32 Value32; + LM_UINT32 Cnt; + LM_UINT32 j, k; - pDevice->MacMode &= ~(MAC_MODE_HALF_DUPLEX | MAC_MODE_PORT_MODE_MASK); + pDevice->MacMode &= ~(MAC_MODE_HALF_DUPLEX | MAC_MODE_PORT_MODE_MASK); - /* Initialize the send_config register. */ - REG_WR(pDevice, MacCtrl.TxAutoNeg, 0); + /* Initialize the send_config register. */ + REG_WR (pDevice, MacCtrl.TxAutoNeg, 0); - /* Enable TBI and full duplex mode. */ - pDevice->MacMode |= MAC_MODE_PORT_MODE_TBI; - REG_WR(pDevice, MacCtrl.Mode, pDevice->MacMode); + /* Enable TBI and full duplex mode. */ + pDevice->MacMode |= MAC_MODE_PORT_MODE_TBI; + REG_WR (pDevice, MacCtrl.Mode, pDevice->MacMode); - /* Initialize the BCM8002 SERDES PHY. */ - switch(pDevice->PhyId & PHY_ID_MASK) - { + /* Initialize the BCM8002 SERDES PHY. */ + switch (pDevice->PhyId & PHY_ID_MASK) { case PHY_BCM8002_PHY_ID: - LM_InitBcm800xPhy(pDevice); - break; + LM_InitBcm800xPhy (pDevice); + break; default: - break; - } - - /* Enable link change interrupt. */ - REG_WR(pDevice, MacCtrl.MacEvent, MAC_EVENT_ENABLE_LINK_STATE_CHANGED_ATTN); - - /* Default to link down. */ - CurrentLinkStatus = LM_STATUS_LINK_DOWN; - - /* Get the link status. */ - Value32 = REG_RD(pDevice, MacCtrl.Status); - if(Value32 & MAC_STATUS_PCS_SYNCED) - { - if((pDevice->RequestedMediaType == LM_REQUESTED_MEDIA_TYPE_AUTO) || - (pDevice->DisableAutoNeg == FALSE)) - { - /* auto-negotiation mode. */ - /* Initialize the autoneg default capaiblities. */ - AutonegInit(&pDevice->AnInfo); - - /* Set the context pointer to point to the main device structure. */ - pDevice->AnInfo.pContext = pDevice; - - /* Setup flow control advertisement register. */ - Value32 = GetPhyAdFlowCntrlSettings(pDevice); - if(Value32 & PHY_AN_AD_PAUSE_CAPABLE) - { - pDevice->AnInfo.mr_adv_sym_pause = 1; - } - else - { - pDevice->AnInfo.mr_adv_sym_pause = 0; - } - - if(Value32 & PHY_AN_AD_ASYM_PAUSE) - { - pDevice->AnInfo.mr_adv_asym_pause = 1; - } - else - { - pDevice->AnInfo.mr_adv_asym_pause = 0; - } - - /* Try to autoneg up to six times. */ - if (pDevice->IgnoreTbiLinkChange) - { - Cnt = 1; - } - else - { - Cnt = 6; - } - for (j = 0; j < Cnt; j++) - { - REG_WR(pDevice, MacCtrl.TxAutoNeg, 0); - - Value32 = pDevice->MacMode & ~MAC_MODE_PORT_MODE_MASK; - REG_WR(pDevice, MacCtrl.Mode, Value32); - MM_Wait(20); - - REG_WR(pDevice, MacCtrl.Mode, pDevice->MacMode | - MAC_MODE_SEND_CONFIGS); - - MM_Wait(20); - - pDevice->AnInfo.State = AN_STATE_UNKNOWN; - pDevice->AnInfo.CurrentTime_us = 0; - - REG_WR(pDevice, Grc.Timer, 0); - for(k = 0; (pDevice->AnInfo.CurrentTime_us < 75000) && - (k < 75000); k++) - { - AnStatus = Autoneg8023z(&pDevice->AnInfo); - - if((AnStatus == AUTONEG_STATUS_DONE) || - (AnStatus == AUTONEG_STATUS_FAILED)) - { - break; - } - - pDevice->AnInfo.CurrentTime_us = REG_RD(pDevice, Grc.Timer); - - } - if((AnStatus == AUTONEG_STATUS_DONE) || - (AnStatus == AUTONEG_STATUS_FAILED)) - { - break; - } - if (j >= 1) - { - if (!(REG_RD(pDevice, MacCtrl.Status) & - MAC_STATUS_PCS_SYNCED)) { - break; - } - } - } - - /* Stop sending configs. */ - MM_AnTxIdle(&pDevice->AnInfo); - - /* Resolve flow control settings. */ - if((AnStatus == AUTONEG_STATUS_DONE) && - pDevice->AnInfo.mr_an_complete && pDevice->AnInfo.mr_link_ok && - pDevice->AnInfo.mr_lp_adv_full_duplex) - { - LM_UINT32 RemotePhyAd; - LM_UINT32 LocalPhyAd; - - LocalPhyAd = 0; - if(pDevice->AnInfo.mr_adv_sym_pause) - { - LocalPhyAd |= PHY_AN_AD_PAUSE_CAPABLE; - } - - if(pDevice->AnInfo.mr_adv_asym_pause) - { - LocalPhyAd |= PHY_AN_AD_ASYM_PAUSE; - } - - RemotePhyAd = 0; - if(pDevice->AnInfo.mr_lp_adv_sym_pause) - { - RemotePhyAd |= PHY_LINK_PARTNER_PAUSE_CAPABLE; - } - - if(pDevice->AnInfo.mr_lp_adv_asym_pause) - { - RemotePhyAd |= PHY_LINK_PARTNER_ASYM_PAUSE; - } - - LM_SetFlowControl(pDevice, LocalPhyAd, RemotePhyAd); - - CurrentLinkStatus = LM_STATUS_LINK_ACTIVE; - } - for (j = 0; j < 30; j++) - { - MM_Wait(20); - REG_WR(pDevice, MacCtrl.Status, MAC_STATUS_SYNC_CHANGED | - MAC_STATUS_CFG_CHANGED); - MM_Wait(20); - if ((REG_RD(pDevice, MacCtrl.Status) & - (MAC_STATUS_SYNC_CHANGED | MAC_STATUS_CFG_CHANGED)) == 0) - break; - } - if (pDevice->PollTbiLink) - { - Value32 = REG_RD(pDevice, MacCtrl.Status); - if (Value32 & MAC_STATUS_RECEIVING_CFG) - { - pDevice->IgnoreTbiLinkChange = TRUE; - } - else - { - pDevice->IgnoreTbiLinkChange = FALSE; - } - } - Value32 = REG_RD(pDevice, MacCtrl.Status); - if (CurrentLinkStatus == LM_STATUS_LINK_DOWN && - (Value32 & MAC_STATUS_PCS_SYNCED) && - ((Value32 & MAC_STATUS_RECEIVING_CFG) == 0)) - { - CurrentLinkStatus = LM_STATUS_LINK_ACTIVE; - } + break; } - else - { - /* We are forcing line speed. */ - pDevice->FlowControlCap &= ~LM_FLOW_CONTROL_AUTO_PAUSE; - LM_SetFlowControl(pDevice, 0, 0); - CurrentLinkStatus = LM_STATUS_LINK_ACTIVE; - REG_WR(pDevice, MacCtrl.Mode, pDevice->MacMode | - MAC_MODE_SEND_CONFIGS); - } - } - /* Set the link polarity bit. */ - pDevice->MacMode &= ~MAC_MODE_LINK_POLARITY; - REG_WR(pDevice, MacCtrl.Mode, pDevice->MacMode); + /* Enable link change interrupt. */ + REG_WR (pDevice, MacCtrl.MacEvent, + MAC_EVENT_ENABLE_LINK_STATE_CHANGED_ATTN); - pDevice->pStatusBlkVirt->Status = STATUS_BLOCK_UPDATED | - (pDevice->pStatusBlkVirt->Status & ~STATUS_BLOCK_LINK_CHANGED_STATUS); - - for (j = 0; j < 100; j++) - { - REG_WR(pDevice, MacCtrl.Status, MAC_STATUS_SYNC_CHANGED | - MAC_STATUS_CFG_CHANGED); - MM_Wait(5); - if ((REG_RD(pDevice, MacCtrl.Status) & - (MAC_STATUS_SYNC_CHANGED | MAC_STATUS_CFG_CHANGED)) == 0) - break; - } - - Value32 = REG_RD(pDevice, MacCtrl.Status); - if((Value32 & MAC_STATUS_PCS_SYNCED) == 0) - { + /* Default to link down. */ CurrentLinkStatus = LM_STATUS_LINK_DOWN; - if (pDevice->DisableAutoNeg == FALSE) - { - REG_WR(pDevice, MacCtrl.Mode, pDevice->MacMode | - MAC_MODE_SEND_CONFIGS); - MM_Wait(1); - REG_WR(pDevice, MacCtrl.Mode, pDevice->MacMode); + + /* Get the link status. */ + Value32 = REG_RD (pDevice, MacCtrl.Status); + if (Value32 & MAC_STATUS_PCS_SYNCED) { + if ((pDevice->RequestedMediaType == + LM_REQUESTED_MEDIA_TYPE_AUTO) + || (pDevice->DisableAutoNeg == FALSE)) { + /* auto-negotiation mode. */ + /* Initialize the autoneg default capaiblities. */ + AutonegInit (&pDevice->AnInfo); + + /* Set the context pointer to point to the main device structure. */ + pDevice->AnInfo.pContext = pDevice; + + /* Setup flow control advertisement register. */ + Value32 = GetPhyAdFlowCntrlSettings (pDevice); + if (Value32 & PHY_AN_AD_PAUSE_CAPABLE) { + pDevice->AnInfo.mr_adv_sym_pause = 1; + } else { + pDevice->AnInfo.mr_adv_sym_pause = 0; + } + + if (Value32 & PHY_AN_AD_ASYM_PAUSE) { + pDevice->AnInfo.mr_adv_asym_pause = 1; + } else { + pDevice->AnInfo.mr_adv_asym_pause = 0; + } + + /* Try to autoneg up to six times. */ + if (pDevice->IgnoreTbiLinkChange) { + Cnt = 1; + } else { + Cnt = 6; + } + for (j = 0; j < Cnt; j++) { + REG_WR (pDevice, MacCtrl.TxAutoNeg, 0); + + Value32 = + pDevice->MacMode & ~MAC_MODE_PORT_MODE_MASK; + REG_WR (pDevice, MacCtrl.Mode, Value32); + MM_Wait (20); + + REG_WR (pDevice, MacCtrl.Mode, + pDevice-> + MacMode | MAC_MODE_SEND_CONFIGS); + + MM_Wait (20); + + pDevice->AnInfo.State = AN_STATE_UNKNOWN; + pDevice->AnInfo.CurrentTime_us = 0; + + REG_WR (pDevice, Grc.Timer, 0); + for (k = 0; + (pDevice->AnInfo.CurrentTime_us < 75000) + && (k < 75000); k++) { + AnStatus = + Autoneg8023z (&pDevice->AnInfo); + + if ((AnStatus == AUTONEG_STATUS_DONE) || + (AnStatus == AUTONEG_STATUS_FAILED)) + { + break; + } + + pDevice->AnInfo.CurrentTime_us = + REG_RD (pDevice, Grc.Timer); + + } + if ((AnStatus == AUTONEG_STATUS_DONE) || + (AnStatus == AUTONEG_STATUS_FAILED)) { + break; + } + if (j >= 1) { + if (!(REG_RD (pDevice, MacCtrl.Status) & + MAC_STATUS_PCS_SYNCED)) { + break; + } + } + } + + /* Stop sending configs. */ + MM_AnTxIdle (&pDevice->AnInfo); + + /* Resolve flow control settings. */ + if ((AnStatus == AUTONEG_STATUS_DONE) && + pDevice->AnInfo.mr_an_complete + && pDevice->AnInfo.mr_link_ok + && pDevice->AnInfo.mr_lp_adv_full_duplex) { + LM_UINT32 RemotePhyAd; + LM_UINT32 LocalPhyAd; + + LocalPhyAd = 0; + if (pDevice->AnInfo.mr_adv_sym_pause) { + LocalPhyAd |= PHY_AN_AD_PAUSE_CAPABLE; + } + + if (pDevice->AnInfo.mr_adv_asym_pause) { + LocalPhyAd |= PHY_AN_AD_ASYM_PAUSE; + } + + RemotePhyAd = 0; + if (pDevice->AnInfo.mr_lp_adv_sym_pause) { + RemotePhyAd |= + PHY_LINK_PARTNER_PAUSE_CAPABLE; + } + + if (pDevice->AnInfo.mr_lp_adv_asym_pause) { + RemotePhyAd |= + PHY_LINK_PARTNER_ASYM_PAUSE; + } + + LM_SetFlowControl (pDevice, LocalPhyAd, + RemotePhyAd); + + CurrentLinkStatus = LM_STATUS_LINK_ACTIVE; + } + for (j = 0; j < 30; j++) { + MM_Wait (20); + REG_WR (pDevice, MacCtrl.Status, + MAC_STATUS_SYNC_CHANGED | + MAC_STATUS_CFG_CHANGED); + MM_Wait (20); + if ((REG_RD (pDevice, MacCtrl.Status) & + (MAC_STATUS_SYNC_CHANGED | + MAC_STATUS_CFG_CHANGED)) == 0) + break; + } + if (pDevice->PollTbiLink) { + Value32 = REG_RD (pDevice, MacCtrl.Status); + if (Value32 & MAC_STATUS_RECEIVING_CFG) { + pDevice->IgnoreTbiLinkChange = TRUE; + } else { + pDevice->IgnoreTbiLinkChange = FALSE; + } + } + Value32 = REG_RD (pDevice, MacCtrl.Status); + if (CurrentLinkStatus == LM_STATUS_LINK_DOWN && + (Value32 & MAC_STATUS_PCS_SYNCED) && + ((Value32 & MAC_STATUS_RECEIVING_CFG) == 0)) { + CurrentLinkStatus = LM_STATUS_LINK_ACTIVE; + } + } else { + /* We are forcing line speed. */ + pDevice->FlowControlCap &= ~LM_FLOW_CONTROL_AUTO_PAUSE; + LM_SetFlowControl (pDevice, 0, 0); + + CurrentLinkStatus = LM_STATUS_LINK_ACTIVE; + REG_WR (pDevice, MacCtrl.Mode, pDevice->MacMode | + MAC_MODE_SEND_CONFIGS); + } } - } + /* Set the link polarity bit. */ + pDevice->MacMode &= ~MAC_MODE_LINK_POLARITY; + REG_WR (pDevice, MacCtrl.Mode, pDevice->MacMode); - /* Initialize the current link status. */ - if(CurrentLinkStatus == LM_STATUS_LINK_ACTIVE) - { - pDevice->LineSpeed = LM_LINE_SPEED_1000MBPS; - pDevice->DuplexMode = LM_DUPLEX_MODE_FULL; - REG_WR(pDevice, MacCtrl.LedCtrl, LED_CTRL_OVERRIDE_LINK_LED | - LED_CTRL_1000MBPS_LED_ON); - } - else - { - pDevice->LineSpeed = LM_LINE_SPEED_UNKNOWN; - pDevice->DuplexMode = LM_DUPLEX_MODE_UNKNOWN; - REG_WR(pDevice, MacCtrl.LedCtrl, LED_CTRL_OVERRIDE_LINK_LED | - LED_CTRL_OVERRIDE_TRAFFIC_LED); - } + pDevice->pStatusBlkVirt->Status = STATUS_BLOCK_UPDATED | + (pDevice->pStatusBlkVirt-> + Status & ~STATUS_BLOCK_LINK_CHANGED_STATUS); - /* Indicate link status. */ - if (pDevice->LinkStatus != CurrentLinkStatus) { - pDevice->LinkStatus = CurrentLinkStatus; - MM_IndicateStatus(pDevice, CurrentLinkStatus); - } + for (j = 0; j < 100; j++) { + REG_WR (pDevice, MacCtrl.Status, MAC_STATUS_SYNC_CHANGED | + MAC_STATUS_CFG_CHANGED); + MM_Wait (5); + if ((REG_RD (pDevice, MacCtrl.Status) & + (MAC_STATUS_SYNC_CHANGED | MAC_STATUS_CFG_CHANGED)) == 0) + break; + } - return LM_STATUS_SUCCESS; + Value32 = REG_RD (pDevice, MacCtrl.Status); + if ((Value32 & MAC_STATUS_PCS_SYNCED) == 0) { + CurrentLinkStatus = LM_STATUS_LINK_DOWN; + if (pDevice->DisableAutoNeg == FALSE) { + REG_WR (pDevice, MacCtrl.Mode, pDevice->MacMode | + MAC_MODE_SEND_CONFIGS); + MM_Wait (1); + REG_WR (pDevice, MacCtrl.Mode, pDevice->MacMode); + } + } + + /* Initialize the current link status. */ + if (CurrentLinkStatus == LM_STATUS_LINK_ACTIVE) { + pDevice->LineSpeed = LM_LINE_SPEED_1000MBPS; + pDevice->DuplexMode = LM_DUPLEX_MODE_FULL; + REG_WR (pDevice, MacCtrl.LedCtrl, LED_CTRL_OVERRIDE_LINK_LED | + LED_CTRL_1000MBPS_LED_ON); + } else { + pDevice->LineSpeed = LM_LINE_SPEED_UNKNOWN; + pDevice->DuplexMode = LM_DUPLEX_MODE_UNKNOWN; + REG_WR (pDevice, MacCtrl.LedCtrl, LED_CTRL_OVERRIDE_LINK_LED | + LED_CTRL_OVERRIDE_TRAFFIC_LED); + } + + /* Indicate link status. */ + if (pDevice->LinkStatus != CurrentLinkStatus) { + pDevice->LinkStatus = CurrentLinkStatus; + MM_IndicateStatus (pDevice, CurrentLinkStatus); + } + + return LM_STATUS_SUCCESS; } -#endif /* INCLUDE_TBI_SUPPORT */ - +#endif /* INCLUDE_TBI_SUPPORT */ /******************************************************************************/ /* Description: */ /* */ /* Return: */ /******************************************************************************/ -LM_STATUS -LM_SetupCopperPhy( - PLM_DEVICE_BLOCK pDevice) +LM_STATUS LM_SetupCopperPhy (PLM_DEVICE_BLOCK pDevice) { - LM_STATUS CurrentLinkStatus; - LM_UINT32 Value32; + LM_STATUS CurrentLinkStatus; + LM_UINT32 Value32; - /* Assume there is not link first. */ - CurrentLinkStatus = LM_STATUS_LINK_DOWN; + /* Assume there is not link first. */ + CurrentLinkStatus = LM_STATUS_LINK_DOWN; - /* Disable phy link change attention. */ - REG_WR(pDevice, MacCtrl.MacEvent, 0); + /* Disable phy link change attention. */ + REG_WR (pDevice, MacCtrl.MacEvent, 0); - /* Clear link change attention. */ - REG_WR(pDevice, MacCtrl.Status, MAC_STATUS_SYNC_CHANGED | - MAC_STATUS_CFG_CHANGED); + /* Clear link change attention. */ + REG_WR (pDevice, MacCtrl.Status, MAC_STATUS_SYNC_CHANGED | + MAC_STATUS_CFG_CHANGED); - /* Disable auto-polling for the moment. */ - pDevice->MiMode = 0xc0000; - REG_WR(pDevice, MacCtrl.MiMode, pDevice->MiMode); - MM_Wait(40); + /* Disable auto-polling for the moment. */ + pDevice->MiMode = 0xc0000; + REG_WR (pDevice, MacCtrl.MiMode, pDevice->MiMode); + MM_Wait (40); - /* Determine the requested line speed and duplex. */ - pDevice->OldLineSpeed = pDevice->LineSpeed; - LM_TranslateRequestedMediaType(pDevice->RequestedMediaType, - &pDevice->MediaType, &pDevice->LineSpeed, &pDevice->DuplexMode); + /* Determine the requested line speed and duplex. */ + pDevice->OldLineSpeed = pDevice->LineSpeed; + LM_TranslateRequestedMediaType (pDevice->RequestedMediaType, + &pDevice->MediaType, + &pDevice->LineSpeed, + &pDevice->DuplexMode); - /* Initialize the phy chip. */ - switch(pDevice->PhyId & PHY_ID_MASK) - { + /* Initialize the phy chip. */ + switch (pDevice->PhyId & PHY_ID_MASK) { case PHY_BCM5400_PHY_ID: case PHY_BCM5401_PHY_ID: case PHY_BCM5411_PHY_ID: case PHY_BCM5701_PHY_ID: case PHY_BCM5703_PHY_ID: case PHY_BCM5704_PHY_ID: - CurrentLinkStatus = LM_InitBcm540xPhy(pDevice); - break; + CurrentLinkStatus = LM_InitBcm540xPhy (pDevice); + break; default: - break; - } + break; + } - if(CurrentLinkStatus == LM_STATUS_LINK_SETTING_MISMATCH) - { - CurrentLinkStatus = LM_STATUS_LINK_DOWN; - } + if (CurrentLinkStatus == LM_STATUS_LINK_SETTING_MISMATCH) { + CurrentLinkStatus = LM_STATUS_LINK_DOWN; + } - /* Setup flow control. */ - pDevice->FlowControl = LM_FLOW_CONTROL_NONE; - if(CurrentLinkStatus == LM_STATUS_LINK_ACTIVE) - { - LM_FLOW_CONTROL FlowCap; /* Flow control capability. */ + /* Setup flow control. */ + pDevice->FlowControl = LM_FLOW_CONTROL_NONE; + if (CurrentLinkStatus == LM_STATUS_LINK_ACTIVE) { + LM_FLOW_CONTROL FlowCap; /* Flow control capability. */ - FlowCap = LM_FLOW_CONTROL_NONE; + FlowCap = LM_FLOW_CONTROL_NONE; - if(pDevice->DuplexMode == LM_DUPLEX_MODE_FULL) - { - if(pDevice->DisableAutoNeg == FALSE || - pDevice->RequestedMediaType == LM_REQUESTED_MEDIA_TYPE_AUTO || - pDevice->RequestedMediaType == LM_REQUESTED_MEDIA_TYPE_UTP_AUTO) - { - LM_UINT32 ExpectedPhyAd; - LM_UINT32 LocalPhyAd; - LM_UINT32 RemotePhyAd; + if (pDevice->DuplexMode == LM_DUPLEX_MODE_FULL) { + if (pDevice->DisableAutoNeg == FALSE || + pDevice->RequestedMediaType == + LM_REQUESTED_MEDIA_TYPE_AUTO + || pDevice->RequestedMediaType == + LM_REQUESTED_MEDIA_TYPE_UTP_AUTO) { + LM_UINT32 ExpectedPhyAd; + LM_UINT32 LocalPhyAd; + LM_UINT32 RemotePhyAd; - LM_ReadPhy(pDevice, PHY_AN_AD_REG, &LocalPhyAd); - pDevice->advertising = LocalPhyAd; - LocalPhyAd &= (PHY_AN_AD_ASYM_PAUSE | PHY_AN_AD_PAUSE_CAPABLE); + LM_ReadPhy (pDevice, PHY_AN_AD_REG, + &LocalPhyAd); + pDevice->advertising = LocalPhyAd; + LocalPhyAd &= + (PHY_AN_AD_ASYM_PAUSE | + PHY_AN_AD_PAUSE_CAPABLE); - ExpectedPhyAd = GetPhyAdFlowCntrlSettings(pDevice); + ExpectedPhyAd = + GetPhyAdFlowCntrlSettings (pDevice); - if(LocalPhyAd != ExpectedPhyAd) - { - CurrentLinkStatus = LM_STATUS_LINK_DOWN; + if (LocalPhyAd != ExpectedPhyAd) { + CurrentLinkStatus = LM_STATUS_LINK_DOWN; + } else { + LM_ReadPhy (pDevice, + PHY_LINK_PARTNER_ABILITY_REG, + &RemotePhyAd); + + LM_SetFlowControl (pDevice, LocalPhyAd, + RemotePhyAd); + } + } else { + pDevice->FlowControlCap &= + ~LM_FLOW_CONTROL_AUTO_PAUSE; + LM_SetFlowControl (pDevice, 0, 0); + } } - else - { - LM_ReadPhy(pDevice, PHY_LINK_PARTNER_ABILITY_REG, - &RemotePhyAd); + } - LM_SetFlowControl(pDevice, LocalPhyAd, RemotePhyAd); + if (CurrentLinkStatus == LM_STATUS_LINK_DOWN) { + LM_ForceAutoNeg (pDevice, pDevice->RequestedMediaType); + + /* If we force line speed, we make get link right away. */ + LM_ReadPhy (pDevice, PHY_STATUS_REG, &Value32); + LM_ReadPhy (pDevice, PHY_STATUS_REG, &Value32); + if (Value32 & PHY_STATUS_LINK_PASS) { + CurrentLinkStatus = LM_STATUS_LINK_ACTIVE; } - } - else - { - pDevice->FlowControlCap &= ~LM_FLOW_CONTROL_AUTO_PAUSE; - LM_SetFlowControl(pDevice, 0, 0); - } - } - } - - if(CurrentLinkStatus == LM_STATUS_LINK_DOWN) - { - LM_ForceAutoNeg(pDevice, pDevice->RequestedMediaType); - - /* If we force line speed, we make get link right away. */ - LM_ReadPhy(pDevice, PHY_STATUS_REG, &Value32); - LM_ReadPhy(pDevice, PHY_STATUS_REG, &Value32); - if(Value32 & PHY_STATUS_LINK_PASS) - { - CurrentLinkStatus = LM_STATUS_LINK_ACTIVE; - } - } - - /* GMII interface. */ - pDevice->MacMode &= ~MAC_MODE_PORT_MODE_MASK; - if(CurrentLinkStatus == LM_STATUS_LINK_ACTIVE) - { - if(pDevice->LineSpeed == LM_LINE_SPEED_100MBPS || - pDevice->LineSpeed == LM_LINE_SPEED_10MBPS) - { - pDevice->MacMode |= MAC_MODE_PORT_MODE_MII; - } - else - { - pDevice->MacMode |= MAC_MODE_PORT_MODE_GMII; - } - } - else { - pDevice->MacMode |= MAC_MODE_PORT_MODE_GMII; - } - - /* Set the MAC to operate in the appropriate duplex mode. */ - pDevice->MacMode &= ~MAC_MODE_HALF_DUPLEX; - if(pDevice->DuplexMode == LM_DUPLEX_MODE_HALF) - { - pDevice->MacMode |= MAC_MODE_HALF_DUPLEX; - } - - /* Set the link polarity bit. */ - pDevice->MacMode &= ~MAC_MODE_LINK_POLARITY; - if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700) - { - if((pDevice->LedMode == LED_MODE_LINK10) || - (CurrentLinkStatus == LM_STATUS_LINK_ACTIVE && - pDevice->LineSpeed == LM_LINE_SPEED_10MBPS)) - { - pDevice->MacMode |= MAC_MODE_LINK_POLARITY; - } - } - else - { - if (CurrentLinkStatus == LM_STATUS_LINK_ACTIVE) - { - pDevice->MacMode |= MAC_MODE_LINK_POLARITY; } - /* Set LED mode. */ - if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700 || - T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5701) - { - Value32 = LED_CTRL_PHY_MODE_1; + /* GMII interface. */ + pDevice->MacMode &= ~MAC_MODE_PORT_MODE_MASK; + if (CurrentLinkStatus == LM_STATUS_LINK_ACTIVE) { + if (pDevice->LineSpeed == LM_LINE_SPEED_100MBPS || + pDevice->LineSpeed == LM_LINE_SPEED_10MBPS) { + pDevice->MacMode |= MAC_MODE_PORT_MODE_MII; + } else { + pDevice->MacMode |= MAC_MODE_PORT_MODE_GMII; + } + } else { + pDevice->MacMode |= MAC_MODE_PORT_MODE_GMII; } - else - { - if(pDevice->LedMode == LED_MODE_OUTPUT) - { - Value32 = LED_CTRL_PHY_MODE_2; - } - else - { - Value32 = LED_CTRL_PHY_MODE_1; - } + + /* Set the MAC to operate in the appropriate duplex mode. */ + pDevice->MacMode &= ~MAC_MODE_HALF_DUPLEX; + if (pDevice->DuplexMode == LM_DUPLEX_MODE_HALF) { + pDevice->MacMode |= MAC_MODE_HALF_DUPLEX; } - REG_WR(pDevice, MacCtrl.LedCtrl, Value32); - } - REG_WR(pDevice, MacCtrl.Mode, pDevice->MacMode); + /* Set the link polarity bit. */ + pDevice->MacMode &= ~MAC_MODE_LINK_POLARITY; + if (T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5700) { + if ((pDevice->LedMode == LED_MODE_LINK10) || + (CurrentLinkStatus == LM_STATUS_LINK_ACTIVE && + pDevice->LineSpeed == LM_LINE_SPEED_10MBPS)) { + pDevice->MacMode |= MAC_MODE_LINK_POLARITY; + } + } else { + if (CurrentLinkStatus == LM_STATUS_LINK_ACTIVE) { + pDevice->MacMode |= MAC_MODE_LINK_POLARITY; + } - /* Enable auto polling. */ - if(pDevice->PhyIntMode == T3_PHY_INT_MODE_AUTO_POLLING) - { - pDevice->MiMode |= MI_MODE_AUTO_POLLING_ENABLE; - REG_WR(pDevice, MacCtrl.MiMode, pDevice->MiMode); - } - - /* Enable phy link change attention. */ - if(pDevice->PhyIntMode == T3_PHY_INT_MODE_MI_INTERRUPT) - { - REG_WR(pDevice, MacCtrl.MacEvent, MAC_EVENT_ENABLE_MI_INTERRUPT); - } - else - { - REG_WR(pDevice, MacCtrl.MacEvent, - MAC_EVENT_ENABLE_LINK_STATE_CHANGED_ATTN); - } - if ((T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700) && - (CurrentLinkStatus == LM_STATUS_LINK_ACTIVE) && - (pDevice->LineSpeed == LM_LINE_SPEED_1000MBPS) && - (((pDevice->PciState & T3_PCI_STATE_CONVENTIONAL_PCI_MODE) && - (pDevice->PciState & T3_PCI_STATE_BUS_SPEED_HIGH)) || - !(pDevice->PciState & T3_PCI_STATE_CONVENTIONAL_PCI_MODE))) - { - MM_Wait(120); - REG_WR(pDevice, MacCtrl.Status, MAC_STATUS_SYNC_CHANGED | - MAC_STATUS_CFG_CHANGED); - MEM_WR_OFFSET(pDevice, T3_FIRMWARE_MAILBOX, - T3_MAGIC_NUM_DISABLE_DMAW_ON_LINK_CHANGE); - } - - /* Indicate link status. */ - if (pDevice->LinkStatus != CurrentLinkStatus) { - pDevice->LinkStatus = CurrentLinkStatus; - MM_IndicateStatus(pDevice, CurrentLinkStatus); - } - - return LM_STATUS_SUCCESS; -} /* LM_SetupCopperPhy */ - -/******************************************************************************/ -/* Description: */ -/* */ -/* Return: */ -/******************************************************************************/ -LM_STATUS -LM_SetupPhy( - PLM_DEVICE_BLOCK pDevice) -{ - LM_STATUS LmStatus; - LM_UINT32 Value32; - -#if INCLUDE_TBI_SUPPORT - if(pDevice->EnableTbi) - { - LmStatus = LM_SetupFiberPhy(pDevice); - } - else -#endif /* INCLUDE_TBI_SUPPORT */ - { - LmStatus = LM_SetupCopperPhy(pDevice); - } - if (pDevice->ChipRevId == T3_CHIP_ID_5704_A0) - { - if (!(pDevice->PciState & T3_PCI_STATE_CONVENTIONAL_PCI_MODE)) - { - Value32 = REG_RD(pDevice, PciCfg.PciState); - REG_WR(pDevice, PciCfg.PciState, - Value32 | T3_PCI_STATE_RETRY_SAME_DMA); + /* Set LED mode. */ + if (T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5700 || + T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5701) { + Value32 = LED_CTRL_PHY_MODE_1; + } else { + if (pDevice->LedMode == LED_MODE_OUTPUT) { + Value32 = LED_CTRL_PHY_MODE_2; + } else { + Value32 = LED_CTRL_PHY_MODE_1; + } + } + REG_WR (pDevice, MacCtrl.LedCtrl, Value32); } - } - if ((pDevice->LineSpeed == LM_LINE_SPEED_1000MBPS) && - (pDevice->DuplexMode == LM_DUPLEX_MODE_HALF)) - { - REG_WR(pDevice, MacCtrl.TxLengths, 0x26ff); - } - else - { - REG_WR(pDevice, MacCtrl.TxLengths, 0x2620); - } - return LmStatus; -} + REG_WR (pDevice, MacCtrl.Mode, pDevice->MacMode); -/******************************************************************************/ -/* Description: */ -/* */ -/* Return: */ -/******************************************************************************/ -LM_VOID -LM_ReadPhy( -PLM_DEVICE_BLOCK pDevice, -LM_UINT32 PhyReg, -PLM_UINT32 pData32) { - LM_UINT32 Value32; - LM_UINT32 j; - - if(pDevice->PhyIntMode == T3_PHY_INT_MODE_AUTO_POLLING) - { - REG_WR(pDevice, MacCtrl.MiMode, pDevice->MiMode & - ~MI_MODE_AUTO_POLLING_ENABLE); - MM_Wait(40); - } - - Value32 = (pDevice->PhyAddr << MI_COM_FIRST_PHY_ADDR_BIT) | - ((PhyReg & MI_COM_PHY_REG_ADDR_MASK) << MI_COM_FIRST_PHY_REG_ADDR_BIT) | - MI_COM_CMD_READ | MI_COM_START; - - REG_WR(pDevice, MacCtrl.MiCom, Value32); - - for(j = 0; j < 20; j++) - { - MM_Wait(25); - - Value32 = REG_RD(pDevice, MacCtrl.MiCom); - - if(!(Value32 & MI_COM_BUSY)) - { - MM_Wait(5); - Value32 = REG_RD(pDevice, MacCtrl.MiCom); - Value32 &= MI_COM_PHY_DATA_MASK; - break; + /* Enable auto polling. */ + if (pDevice->PhyIntMode == T3_PHY_INT_MODE_AUTO_POLLING) { + pDevice->MiMode |= MI_MODE_AUTO_POLLING_ENABLE; + REG_WR (pDevice, MacCtrl.MiMode, pDevice->MiMode); } - } - if(Value32 & MI_COM_BUSY) - { - Value32 = 0; - } - - *pData32 = Value32; - - if(pDevice->PhyIntMode == T3_PHY_INT_MODE_AUTO_POLLING) - { - REG_WR(pDevice, MacCtrl.MiMode, pDevice->MiMode); - MM_Wait(40); - } -} /* LM_ReadPhy */ - - -/******************************************************************************/ -/* Description: */ -/* */ -/* Return: */ -/******************************************************************************/ -LM_VOID -LM_WritePhy( -PLM_DEVICE_BLOCK pDevice, -LM_UINT32 PhyReg, -LM_UINT32 Data32) { - LM_UINT32 Value32; - LM_UINT32 j; - - if(pDevice->PhyIntMode == T3_PHY_INT_MODE_AUTO_POLLING) - { - REG_WR(pDevice, MacCtrl.MiMode, pDevice->MiMode & - ~MI_MODE_AUTO_POLLING_ENABLE); - MM_Wait(40); - } - - Value32 = (pDevice->PhyAddr << MI_COM_FIRST_PHY_ADDR_BIT) | - ((PhyReg & MI_COM_PHY_REG_ADDR_MASK) << MI_COM_FIRST_PHY_REG_ADDR_BIT) | - (Data32 & MI_COM_PHY_DATA_MASK) | MI_COM_CMD_WRITE | MI_COM_START; - - REG_WR(pDevice, MacCtrl.MiCom, Value32); - - for(j = 0; j < 20; j++) - { - MM_Wait(25); - - Value32 = REG_RD(pDevice, MacCtrl.MiCom); - - if(!(Value32 & MI_COM_BUSY)) - { - MM_Wait(5); - break; + /* Enable phy link change attention. */ + if (pDevice->PhyIntMode == T3_PHY_INT_MODE_MI_INTERRUPT) { + REG_WR (pDevice, MacCtrl.MacEvent, + MAC_EVENT_ENABLE_MI_INTERRUPT); + } else { + REG_WR (pDevice, MacCtrl.MacEvent, + MAC_EVENT_ENABLE_LINK_STATE_CHANGED_ATTN); + } + if ((T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5700) && + (CurrentLinkStatus == LM_STATUS_LINK_ACTIVE) && + (pDevice->LineSpeed == LM_LINE_SPEED_1000MBPS) && + (((pDevice->PciState & T3_PCI_STATE_CONVENTIONAL_PCI_MODE) && + (pDevice->PciState & T3_PCI_STATE_BUS_SPEED_HIGH)) || + !(pDevice->PciState & T3_PCI_STATE_CONVENTIONAL_PCI_MODE))) { + MM_Wait (120); + REG_WR (pDevice, MacCtrl.Status, MAC_STATUS_SYNC_CHANGED | + MAC_STATUS_CFG_CHANGED); + MEM_WR_OFFSET (pDevice, T3_FIRMWARE_MAILBOX, + T3_MAGIC_NUM_DISABLE_DMAW_ON_LINK_CHANGE); } - } - if(pDevice->PhyIntMode == T3_PHY_INT_MODE_AUTO_POLLING) - { - REG_WR(pDevice, MacCtrl.MiMode, pDevice->MiMode); - MM_Wait(40); - } -} /* LM_WritePhy */ - - -/******************************************************************************/ -/* Description: */ -/* */ -/* Return: */ -/******************************************************************************/ -LM_STATUS -LM_SetPowerState( -PLM_DEVICE_BLOCK pDevice, -LM_POWER_STATE PowerLevel) { - LM_UINT32 PmeSupport; - LM_UINT32 Value32; - LM_UINT32 PmCtrl; - - /* make sureindirect accesses are enabled*/ - MM_WriteConfig32(pDevice, T3_PCI_MISC_HOST_CTRL_REG, pDevice->MiscHostCtrl); - - /* Clear the PME_ASSERT bit and the power state bits. Also enable */ - /* the PME bit. */ - MM_ReadConfig32(pDevice, T3_PCI_PM_STATUS_CTRL_REG, &PmCtrl); - - PmCtrl |= T3_PM_PME_ASSERTED; - PmCtrl &= ~T3_PM_POWER_STATE_MASK; - - /* Set the appropriate power state. */ - if(PowerLevel == LM_POWER_STATE_D0) - { - - /* Bring the card out of low power mode. */ - PmCtrl |= T3_PM_POWER_STATE_D0; - MM_WriteConfig32(pDevice, T3_PCI_PM_STATUS_CTRL_REG, PmCtrl); - - REG_WR(pDevice, Grc.LocalCtrl, pDevice->GrcLocalCtrl); - MM_Wait (40); -#if 0 /* Bugfix by jmb...can't call WritePhy here because pDevice not fully initialized */ - LM_WritePhy(pDevice, BCM5401_AUX_CTRL, 0x02); -#endif + /* Indicate link status. */ + if (pDevice->LinkStatus != CurrentLinkStatus) { + pDevice->LinkStatus = CurrentLinkStatus; + MM_IndicateStatus (pDevice, CurrentLinkStatus); + } return LM_STATUS_SUCCESS; - } - else if(PowerLevel == LM_POWER_STATE_D1) - { - PmCtrl |= T3_PM_POWER_STATE_D1; - } - else if(PowerLevel == LM_POWER_STATE_D2) - { - PmCtrl |= T3_PM_POWER_STATE_D2; - } - else if(PowerLevel == LM_POWER_STATE_D3) - { - PmCtrl |= T3_PM_POWER_STATE_D3; - } - else - { - return LM_STATUS_FAILURE; - } - PmCtrl |= T3_PM_PME_ENABLE; - - /* Mask out all interrupts so LM_SetupPhy won't be called while we are */ - /* setting new line speed. */ - Value32 = REG_RD(pDevice, PciCfg.MiscHostCtrl); - REG_WR(pDevice, PciCfg.MiscHostCtrl, Value32 | MISC_HOST_CTRL_MASK_PCI_INT); - - if(!pDevice->RestoreOnWakeUp) - { - pDevice->RestoreOnWakeUp = TRUE; - pDevice->WakeUpDisableAutoNeg = pDevice->DisableAutoNeg; - pDevice->WakeUpRequestedMediaType = pDevice->RequestedMediaType; - } - - /* Force auto-negotiation to 10 line speed. */ - pDevice->DisableAutoNeg = FALSE; - pDevice->RequestedMediaType = LM_REQUESTED_MEDIA_TYPE_UTP_10MBPS; - LM_SetupPhy(pDevice); - - /* Put the driver in the initial state, and go through the power down */ - /* sequence. */ - LM_Halt(pDevice); - - MM_ReadConfig32(pDevice, T3_PCI_PM_CAP_REG, &PmeSupport); - - if (pDevice->WakeUpModeCap != LM_WAKE_UP_MODE_NONE) - { - - /* Enable WOL. */ - LM_WritePhy(pDevice, BCM5401_AUX_CTRL, 0x5a); - MM_Wait(40); - - /* Set LED mode. */ - if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700 || - T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5701) - { - Value32 = LED_CTRL_PHY_MODE_1; - } - else - { - if(pDevice->LedMode == LED_MODE_OUTPUT) - { - Value32 = LED_CTRL_PHY_MODE_2; - } - else - { - Value32 = LED_CTRL_PHY_MODE_1; - } - } - - Value32 = MAC_MODE_PORT_MODE_MII; - if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700) - { - if(pDevice->LedMode == LED_MODE_LINK10 || - pDevice->WolSpeed == WOL_SPEED_10MB) - { - Value32 |= MAC_MODE_LINK_POLARITY; - } - } - else - { - Value32 |= MAC_MODE_LINK_POLARITY; - } - REG_WR(pDevice, MacCtrl.Mode, Value32); - MM_Wait(40); MM_Wait(40); MM_Wait(40); - - /* Always enable magic packet wake-up if we have vaux. */ - if((PmeSupport & T3_PCI_PM_CAP_PME_D3COLD) && - (pDevice->WakeUpModeCap & LM_WAKE_UP_MODE_MAGIC_PACKET)) - { - Value32 |= MAC_MODE_DETECT_MAGIC_PACKET_ENABLE; - } - - REG_WR(pDevice, MacCtrl.Mode, Value32); - - /* Enable the receiver. */ - REG_WR(pDevice, MacCtrl.RxMode, RX_MODE_ENABLE); - } - - /* Disable tx/rx clocks, and seletect an alternate clock. */ - if(pDevice->WolSpeed == WOL_SPEED_100MB) - { - if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700 || - T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5701) - { - Value32 = T3_PCI_DISABLE_RX_CLOCK | T3_PCI_DISABLE_TX_CLOCK | - T3_PCI_SELECT_ALTERNATE_CLOCK; - } - else - { - Value32 = T3_PCI_SELECT_ALTERNATE_CLOCK; - } - REG_WR(pDevice, PciCfg.ClockCtrl, Value32); - - MM_Wait(40); - - if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700 || - T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5701) - { - Value32 = T3_PCI_DISABLE_RX_CLOCK | T3_PCI_DISABLE_TX_CLOCK | - T3_PCI_SELECT_ALTERNATE_CLOCK | T3_PCI_44MHZ_CORE_CLOCK; - } - else - { - Value32 = T3_PCI_SELECT_ALTERNATE_CLOCK | - T3_PCI_44MHZ_CORE_CLOCK; - } - - REG_WR(pDevice, PciCfg.ClockCtrl, Value32); - - MM_Wait(40); - - if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700 || - T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5701) - { - Value32 = T3_PCI_DISABLE_RX_CLOCK | T3_PCI_DISABLE_TX_CLOCK | - T3_PCI_44MHZ_CORE_CLOCK; - } - else - { - Value32 = T3_PCI_44MHZ_CORE_CLOCK; - } - - REG_WR(pDevice, PciCfg.ClockCtrl, Value32); - } - else - { - if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700 || - T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5701) - { - Value32 = T3_PCI_DISABLE_RX_CLOCK | T3_PCI_DISABLE_TX_CLOCK | - T3_PCI_SELECT_ALTERNATE_CLOCK | - T3_PCI_POWER_DOWN_PCI_PLL133; - } - else - { - Value32 = T3_PCI_SELECT_ALTERNATE_CLOCK | - T3_PCI_POWER_DOWN_PCI_PLL133; - } - - REG_WR(pDevice, PciCfg.ClockCtrl, Value32); - } - - MM_Wait(40); - - if(!pDevice->EepromWp && (pDevice->WakeUpModeCap != LM_WAKE_UP_MODE_NONE)) - { - /* Switch adapter to auxilliary power. */ - if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700 || - T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5701) - { - /* GPIO0 = 1, GPIO1 = 1, GPIO2 = 0. */ - REG_WR(pDevice, Grc.LocalCtrl, pDevice->GrcLocalCtrl | - GRC_MISC_LOCAL_CTRL_GPIO_OE0 | - GRC_MISC_LOCAL_CTRL_GPIO_OE1 | - GRC_MISC_LOCAL_CTRL_GPIO_OE2 | - GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT0 | - GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT1); - MM_Wait(40); - } - else - { - /* GPIO0 = 0, GPIO1 = 1, GPIO2 = 1. */ - REG_WR(pDevice, Grc.LocalCtrl, pDevice->GrcLocalCtrl | - GRC_MISC_LOCAL_CTRL_GPIO_OE0 | - GRC_MISC_LOCAL_CTRL_GPIO_OE1 | - GRC_MISC_LOCAL_CTRL_GPIO_OE2 | - GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT1 | - GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT2); - MM_Wait(40); - - /* GPIO0 = 1, GPIO1 = 1, GPIO2 = 1. */ - REG_WR(pDevice, Grc.LocalCtrl, pDevice->GrcLocalCtrl | - GRC_MISC_LOCAL_CTRL_GPIO_OE0 | - GRC_MISC_LOCAL_CTRL_GPIO_OE1 | - GRC_MISC_LOCAL_CTRL_GPIO_OE2 | - GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT0 | - GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT1 | - GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT2); - MM_Wait(40); - - /* GPIO0 = 1, GPIO1 = 1, GPIO2 = 0. */ - REG_WR(pDevice, Grc.LocalCtrl, pDevice->GrcLocalCtrl | - GRC_MISC_LOCAL_CTRL_GPIO_OE0 | - GRC_MISC_LOCAL_CTRL_GPIO_OE1 | - GRC_MISC_LOCAL_CTRL_GPIO_OE2 | - GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT0 | - GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT1); - MM_Wait(40); - } - } - - /* Set the phy to low power mode. */ - /* Put the the hardware in low power mode. */ - MM_WriteConfig32(pDevice, T3_PCI_PM_STATUS_CTRL_REG, PmCtrl); - - return LM_STATUS_SUCCESS; -} /* LM_SetPowerState */ - +} /* LM_SetupCopperPhy */ /******************************************************************************/ /* Description: */ /* */ /* Return: */ /******************************************************************************/ -static LM_UINT32 -GetPhyAdFlowCntrlSettings( - PLM_DEVICE_BLOCK pDevice) +LM_STATUS LM_SetupPhy (PLM_DEVICE_BLOCK pDevice) { - LM_UINT32 Value32; + LM_STATUS LmStatus; + LM_UINT32 Value32; - Value32 = 0; +#if INCLUDE_TBI_SUPPORT + if (pDevice->EnableTbi) { + LmStatus = LM_SetupFiberPhy (pDevice); + } else +#endif /* INCLUDE_TBI_SUPPORT */ + { + LmStatus = LM_SetupCopperPhy (pDevice); + } + if (pDevice->ChipRevId == T3_CHIP_ID_5704_A0) { + if (!(pDevice->PciState & T3_PCI_STATE_CONVENTIONAL_PCI_MODE)) { + Value32 = REG_RD (pDevice, PciCfg.PciState); + REG_WR (pDevice, PciCfg.PciState, + Value32 | T3_PCI_STATE_RETRY_SAME_DMA); + } + } + if ((pDevice->LineSpeed == LM_LINE_SPEED_1000MBPS) && + (pDevice->DuplexMode == LM_DUPLEX_MODE_HALF)) { + REG_WR (pDevice, MacCtrl.TxLengths, 0x26ff); + } else { + REG_WR (pDevice, MacCtrl.TxLengths, 0x2620); + } - /* Auto negotiation flow control only when autonegotiation is enabled. */ - if(pDevice->DisableAutoNeg == FALSE || - pDevice->RequestedMediaType == LM_REQUESTED_MEDIA_TYPE_AUTO || - pDevice->RequestedMediaType == LM_REQUESTED_MEDIA_TYPE_UTP_AUTO) - { - /* Please refer to Table 28B-3 of the 802.3ab-1999 spec. */ - if((pDevice->FlowControlCap == LM_FLOW_CONTROL_AUTO_PAUSE) || - ((pDevice->FlowControlCap & LM_FLOW_CONTROL_RECEIVE_PAUSE) && - (pDevice->FlowControlCap & LM_FLOW_CONTROL_TRANSMIT_PAUSE))) - { - Value32 |= PHY_AN_AD_PAUSE_CAPABLE; - } - else if(pDevice->FlowControlCap & LM_FLOW_CONTROL_TRANSMIT_PAUSE) - { - Value32 |= PHY_AN_AD_ASYM_PAUSE; - } - else if(pDevice->FlowControlCap & LM_FLOW_CONTROL_RECEIVE_PAUSE) - { - Value32 |= PHY_AN_AD_PAUSE_CAPABLE | PHY_AN_AD_ASYM_PAUSE; - } - } - - return Value32; + return LmStatus; } +/******************************************************************************/ +/* Description: */ +/* */ +/* Return: */ +/******************************************************************************/ +LM_VOID +LM_ReadPhy (PLM_DEVICE_BLOCK pDevice, LM_UINT32 PhyReg, PLM_UINT32 pData32) +{ + LM_UINT32 Value32; + LM_UINT32 j; + + if (pDevice->PhyIntMode == T3_PHY_INT_MODE_AUTO_POLLING) { + REG_WR (pDevice, MacCtrl.MiMode, pDevice->MiMode & + ~MI_MODE_AUTO_POLLING_ENABLE); + MM_Wait (40); + } + + Value32 = (pDevice->PhyAddr << MI_COM_FIRST_PHY_ADDR_BIT) | + ((PhyReg & MI_COM_PHY_REG_ADDR_MASK) << + MI_COM_FIRST_PHY_REG_ADDR_BIT) | MI_COM_CMD_READ | MI_COM_START; + + REG_WR (pDevice, MacCtrl.MiCom, Value32); + + for (j = 0; j < 20; j++) { + MM_Wait (25); + + Value32 = REG_RD (pDevice, MacCtrl.MiCom); + + if (!(Value32 & MI_COM_BUSY)) { + MM_Wait (5); + Value32 = REG_RD (pDevice, MacCtrl.MiCom); + Value32 &= MI_COM_PHY_DATA_MASK; + break; + } + } + + if (Value32 & MI_COM_BUSY) { + Value32 = 0; + } + + *pData32 = Value32; + + if (pDevice->PhyIntMode == T3_PHY_INT_MODE_AUTO_POLLING) { + REG_WR (pDevice, MacCtrl.MiMode, pDevice->MiMode); + MM_Wait (40); + } +} /* LM_ReadPhy */ + +/******************************************************************************/ +/* Description: */ +/* */ +/* Return: */ +/******************************************************************************/ +LM_VOID +LM_WritePhy (PLM_DEVICE_BLOCK pDevice, LM_UINT32 PhyReg, LM_UINT32 Data32) +{ + LM_UINT32 Value32; + LM_UINT32 j; + + if (pDevice->PhyIntMode == T3_PHY_INT_MODE_AUTO_POLLING) { + REG_WR (pDevice, MacCtrl.MiMode, pDevice->MiMode & + ~MI_MODE_AUTO_POLLING_ENABLE); + MM_Wait (40); + } + + Value32 = (pDevice->PhyAddr << MI_COM_FIRST_PHY_ADDR_BIT) | + ((PhyReg & MI_COM_PHY_REG_ADDR_MASK) << + MI_COM_FIRST_PHY_REG_ADDR_BIT) | (Data32 & MI_COM_PHY_DATA_MASK) | + MI_COM_CMD_WRITE | MI_COM_START; + + REG_WR (pDevice, MacCtrl.MiCom, Value32); + + for (j = 0; j < 20; j++) { + MM_Wait (25); + + Value32 = REG_RD (pDevice, MacCtrl.MiCom); + + if (!(Value32 & MI_COM_BUSY)) { + MM_Wait (5); + break; + } + } + + if (pDevice->PhyIntMode == T3_PHY_INT_MODE_AUTO_POLLING) { + REG_WR (pDevice, MacCtrl.MiMode, pDevice->MiMode); + MM_Wait (40); + } +} /* LM_WritePhy */ + +/******************************************************************************/ +/* Description: */ +/* */ +/* Return: */ +/******************************************************************************/ +LM_STATUS LM_SetPowerState (PLM_DEVICE_BLOCK pDevice, LM_POWER_STATE PowerLevel) +{ + LM_UINT32 PmeSupport; + LM_UINT32 Value32; + LM_UINT32 PmCtrl; + + /* make sureindirect accesses are enabled */ + MM_WriteConfig32 (pDevice, T3_PCI_MISC_HOST_CTRL_REG, + pDevice->MiscHostCtrl); + + /* Clear the PME_ASSERT bit and the power state bits. Also enable */ + /* the PME bit. */ + MM_ReadConfig32 (pDevice, T3_PCI_PM_STATUS_CTRL_REG, &PmCtrl); + + PmCtrl |= T3_PM_PME_ASSERTED; + PmCtrl &= ~T3_PM_POWER_STATE_MASK; + + /* Set the appropriate power state. */ + if (PowerLevel == LM_POWER_STATE_D0) { + + /* Bring the card out of low power mode. */ + PmCtrl |= T3_PM_POWER_STATE_D0; + MM_WriteConfig32 (pDevice, T3_PCI_PM_STATUS_CTRL_REG, PmCtrl); + + REG_WR (pDevice, Grc.LocalCtrl, pDevice->GrcLocalCtrl); + MM_Wait (40); +#if 0 /* Bugfix by jmb...can't call WritePhy here because pDevice not fully initialized */ + LM_WritePhy (pDevice, BCM5401_AUX_CTRL, 0x02); +#endif + + return LM_STATUS_SUCCESS; + } else if (PowerLevel == LM_POWER_STATE_D1) { + PmCtrl |= T3_PM_POWER_STATE_D1; + } else if (PowerLevel == LM_POWER_STATE_D2) { + PmCtrl |= T3_PM_POWER_STATE_D2; + } else if (PowerLevel == LM_POWER_STATE_D3) { + PmCtrl |= T3_PM_POWER_STATE_D3; + } else { + return LM_STATUS_FAILURE; + } + PmCtrl |= T3_PM_PME_ENABLE; + + /* Mask out all interrupts so LM_SetupPhy won't be called while we are */ + /* setting new line speed. */ + Value32 = REG_RD (pDevice, PciCfg.MiscHostCtrl); + REG_WR (pDevice, PciCfg.MiscHostCtrl, + Value32 | MISC_HOST_CTRL_MASK_PCI_INT); + + if (!pDevice->RestoreOnWakeUp) { + pDevice->RestoreOnWakeUp = TRUE; + pDevice->WakeUpDisableAutoNeg = pDevice->DisableAutoNeg; + pDevice->WakeUpRequestedMediaType = pDevice->RequestedMediaType; + } + + /* Force auto-negotiation to 10 line speed. */ + pDevice->DisableAutoNeg = FALSE; + pDevice->RequestedMediaType = LM_REQUESTED_MEDIA_TYPE_UTP_10MBPS; + LM_SetupPhy (pDevice); + + /* Put the driver in the initial state, and go through the power down */ + /* sequence. */ + LM_Halt (pDevice); + + MM_ReadConfig32 (pDevice, T3_PCI_PM_CAP_REG, &PmeSupport); + + if (pDevice->WakeUpModeCap != LM_WAKE_UP_MODE_NONE) { + + /* Enable WOL. */ + LM_WritePhy (pDevice, BCM5401_AUX_CTRL, 0x5a); + MM_Wait (40); + + /* Set LED mode. */ + if (T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5700 || + T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5701) { + Value32 = LED_CTRL_PHY_MODE_1; + } else { + if (pDevice->LedMode == LED_MODE_OUTPUT) { + Value32 = LED_CTRL_PHY_MODE_2; + } else { + Value32 = LED_CTRL_PHY_MODE_1; + } + } + + Value32 = MAC_MODE_PORT_MODE_MII; + if (T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5700) { + if (pDevice->LedMode == LED_MODE_LINK10 || + pDevice->WolSpeed == WOL_SPEED_10MB) { + Value32 |= MAC_MODE_LINK_POLARITY; + } + } else { + Value32 |= MAC_MODE_LINK_POLARITY; + } + REG_WR (pDevice, MacCtrl.Mode, Value32); + MM_Wait (40); + MM_Wait (40); + MM_Wait (40); + + /* Always enable magic packet wake-up if we have vaux. */ + if ((PmeSupport & T3_PCI_PM_CAP_PME_D3COLD) && + (pDevice->WakeUpModeCap & LM_WAKE_UP_MODE_MAGIC_PACKET)) { + Value32 |= MAC_MODE_DETECT_MAGIC_PACKET_ENABLE; + } + + REG_WR (pDevice, MacCtrl.Mode, Value32); + + /* Enable the receiver. */ + REG_WR (pDevice, MacCtrl.RxMode, RX_MODE_ENABLE); + } + + /* Disable tx/rx clocks, and seletect an alternate clock. */ + if (pDevice->WolSpeed == WOL_SPEED_100MB) { + if (T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5700 || + T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5701) { + Value32 = + T3_PCI_DISABLE_RX_CLOCK | T3_PCI_DISABLE_TX_CLOCK | + T3_PCI_SELECT_ALTERNATE_CLOCK; + } else { + Value32 = T3_PCI_SELECT_ALTERNATE_CLOCK; + } + REG_WR (pDevice, PciCfg.ClockCtrl, Value32); + + MM_Wait (40); + + if (T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5700 || + T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5701) { + Value32 = + T3_PCI_DISABLE_RX_CLOCK | T3_PCI_DISABLE_TX_CLOCK | + T3_PCI_SELECT_ALTERNATE_CLOCK | + T3_PCI_44MHZ_CORE_CLOCK; + } else { + Value32 = T3_PCI_SELECT_ALTERNATE_CLOCK | + T3_PCI_44MHZ_CORE_CLOCK; + } + + REG_WR (pDevice, PciCfg.ClockCtrl, Value32); + + MM_Wait (40); + + if (T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5700 || + T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5701) { + Value32 = + T3_PCI_DISABLE_RX_CLOCK | T3_PCI_DISABLE_TX_CLOCK | + T3_PCI_44MHZ_CORE_CLOCK; + } else { + Value32 = T3_PCI_44MHZ_CORE_CLOCK; + } + + REG_WR (pDevice, PciCfg.ClockCtrl, Value32); + } else { + if (T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5700 || + T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5701) { + Value32 = + T3_PCI_DISABLE_RX_CLOCK | T3_PCI_DISABLE_TX_CLOCK | + T3_PCI_SELECT_ALTERNATE_CLOCK | + T3_PCI_POWER_DOWN_PCI_PLL133; + } else { + Value32 = T3_PCI_SELECT_ALTERNATE_CLOCK | + T3_PCI_POWER_DOWN_PCI_PLL133; + } + + REG_WR (pDevice, PciCfg.ClockCtrl, Value32); + } + + MM_Wait (40); + + if (!pDevice->EepromWp + && (pDevice->WakeUpModeCap != LM_WAKE_UP_MODE_NONE)) { + /* Switch adapter to auxilliary power. */ + if (T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5700 || + T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5701) { + /* GPIO0 = 1, GPIO1 = 1, GPIO2 = 0. */ + REG_WR (pDevice, Grc.LocalCtrl, pDevice->GrcLocalCtrl | + GRC_MISC_LOCAL_CTRL_GPIO_OE0 | + GRC_MISC_LOCAL_CTRL_GPIO_OE1 | + GRC_MISC_LOCAL_CTRL_GPIO_OE2 | + GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT0 | + GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT1); + MM_Wait (40); + } else { + /* GPIO0 = 0, GPIO1 = 1, GPIO2 = 1. */ + REG_WR (pDevice, Grc.LocalCtrl, pDevice->GrcLocalCtrl | + GRC_MISC_LOCAL_CTRL_GPIO_OE0 | + GRC_MISC_LOCAL_CTRL_GPIO_OE1 | + GRC_MISC_LOCAL_CTRL_GPIO_OE2 | + GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT1 | + GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT2); + MM_Wait (40); + + /* GPIO0 = 1, GPIO1 = 1, GPIO2 = 1. */ + REG_WR (pDevice, Grc.LocalCtrl, pDevice->GrcLocalCtrl | + GRC_MISC_LOCAL_CTRL_GPIO_OE0 | + GRC_MISC_LOCAL_CTRL_GPIO_OE1 | + GRC_MISC_LOCAL_CTRL_GPIO_OE2 | + GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT0 | + GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT1 | + GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT2); + MM_Wait (40); + + /* GPIO0 = 1, GPIO1 = 1, GPIO2 = 0. */ + REG_WR (pDevice, Grc.LocalCtrl, pDevice->GrcLocalCtrl | + GRC_MISC_LOCAL_CTRL_GPIO_OE0 | + GRC_MISC_LOCAL_CTRL_GPIO_OE1 | + GRC_MISC_LOCAL_CTRL_GPIO_OE2 | + GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT0 | + GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT1); + MM_Wait (40); + } + } + + /* Set the phy to low power mode. */ + /* Put the the hardware in low power mode. */ + MM_WriteConfig32 (pDevice, T3_PCI_PM_STATUS_CTRL_REG, PmCtrl); + + return LM_STATUS_SUCCESS; +} /* LM_SetPowerState */ + +/******************************************************************************/ +/* Description: */ +/* */ +/* Return: */ +/******************************************************************************/ +static LM_UINT32 GetPhyAdFlowCntrlSettings (PLM_DEVICE_BLOCK pDevice) +{ + LM_UINT32 Value32; + + Value32 = 0; + + /* Auto negotiation flow control only when autonegotiation is enabled. */ + if (pDevice->DisableAutoNeg == FALSE || + pDevice->RequestedMediaType == LM_REQUESTED_MEDIA_TYPE_AUTO || + pDevice->RequestedMediaType == LM_REQUESTED_MEDIA_TYPE_UTP_AUTO) { + /* Please refer to Table 28B-3 of the 802.3ab-1999 spec. */ + if ((pDevice->FlowControlCap == LM_FLOW_CONTROL_AUTO_PAUSE) || + ((pDevice->FlowControlCap & LM_FLOW_CONTROL_RECEIVE_PAUSE) + && (pDevice-> + FlowControlCap & LM_FLOW_CONTROL_TRANSMIT_PAUSE))) { + Value32 |= PHY_AN_AD_PAUSE_CAPABLE; + } else if (pDevice-> + FlowControlCap & LM_FLOW_CONTROL_TRANSMIT_PAUSE) { + Value32 |= PHY_AN_AD_ASYM_PAUSE; + } else if (pDevice-> + FlowControlCap & LM_FLOW_CONTROL_RECEIVE_PAUSE) { + Value32 |= + PHY_AN_AD_PAUSE_CAPABLE | PHY_AN_AD_ASYM_PAUSE; + } + } + + return Value32; +} /******************************************************************************/ /* Description: */ @@ -5632,195 +5177,169 @@ GetPhyAdFlowCntrlSettings( /* */ /******************************************************************************/ static LM_STATUS -LM_ForceAutoNegBcm540xPhy( -PLM_DEVICE_BLOCK pDevice, -LM_REQUESTED_MEDIA_TYPE RequestedMediaType) +LM_ForceAutoNegBcm540xPhy (PLM_DEVICE_BLOCK pDevice, + LM_REQUESTED_MEDIA_TYPE RequestedMediaType) { - LM_MEDIA_TYPE MediaType; - LM_LINE_SPEED LineSpeed; - LM_DUPLEX_MODE DuplexMode; - LM_UINT32 NewPhyCtrl; - LM_UINT32 Value32; - LM_UINT32 Cnt; + LM_MEDIA_TYPE MediaType; + LM_LINE_SPEED LineSpeed; + LM_DUPLEX_MODE DuplexMode; + LM_UINT32 NewPhyCtrl; + LM_UINT32 Value32; + LM_UINT32 Cnt; - /* Get the interface type, line speed, and duplex mode. */ - LM_TranslateRequestedMediaType(RequestedMediaType, &MediaType, &LineSpeed, - &DuplexMode); + /* Get the interface type, line speed, and duplex mode. */ + LM_TranslateRequestedMediaType (RequestedMediaType, &MediaType, + &LineSpeed, &DuplexMode); - if (pDevice->RestoreOnWakeUp) - { - LM_WritePhy(pDevice, BCM540X_1000BASET_CTRL_REG, 0); - pDevice->advertising1000 = 0; - Value32 = PHY_AN_AD_10BASET_FULL | PHY_AN_AD_10BASET_HALF; - if (pDevice->WolSpeed == WOL_SPEED_100MB) - { - Value32 |= PHY_AN_AD_100BASETX_FULL | PHY_AN_AD_100BASETX_HALF; + if (pDevice->RestoreOnWakeUp) { + LM_WritePhy (pDevice, BCM540X_1000BASET_CTRL_REG, 0); + pDevice->advertising1000 = 0; + Value32 = PHY_AN_AD_10BASET_FULL | PHY_AN_AD_10BASET_HALF; + if (pDevice->WolSpeed == WOL_SPEED_100MB) { + Value32 |= + PHY_AN_AD_100BASETX_FULL | PHY_AN_AD_100BASETX_HALF; + } + Value32 |= PHY_AN_AD_PROTOCOL_802_3_CSMA_CD; + Value32 |= GetPhyAdFlowCntrlSettings (pDevice); + LM_WritePhy (pDevice, PHY_AN_AD_REG, Value32); + pDevice->advertising = Value32; } - Value32 |= PHY_AN_AD_PROTOCOL_802_3_CSMA_CD; - Value32 |= GetPhyAdFlowCntrlSettings(pDevice); - LM_WritePhy(pDevice, PHY_AN_AD_REG, Value32); - pDevice->advertising = Value32; - } - /* Setup the auto-negotiation advertisement register. */ - else if(LineSpeed == LM_LINE_SPEED_UNKNOWN) - { - /* Setup the 10/100 Mbps auto-negotiation advertisement register. */ - Value32 = PHY_AN_AD_PROTOCOL_802_3_CSMA_CD | - PHY_AN_AD_10BASET_HALF | PHY_AN_AD_10BASET_FULL | - PHY_AN_AD_100BASETX_FULL | PHY_AN_AD_100BASETX_HALF; - Value32 |= GetPhyAdFlowCntrlSettings(pDevice); + /* Setup the auto-negotiation advertisement register. */ + else if (LineSpeed == LM_LINE_SPEED_UNKNOWN) { + /* Setup the 10/100 Mbps auto-negotiation advertisement register. */ + Value32 = PHY_AN_AD_PROTOCOL_802_3_CSMA_CD | + PHY_AN_AD_10BASET_HALF | PHY_AN_AD_10BASET_FULL | + PHY_AN_AD_100BASETX_FULL | PHY_AN_AD_100BASETX_HALF; + Value32 |= GetPhyAdFlowCntrlSettings (pDevice); - LM_WritePhy(pDevice, PHY_AN_AD_REG, Value32); - pDevice->advertising = Value32; + LM_WritePhy (pDevice, PHY_AN_AD_REG, Value32); + pDevice->advertising = Value32; - /* Advertise 1000Mbps */ - Value32 = BCM540X_AN_AD_1000BASET_HALF | BCM540X_AN_AD_1000BASET_FULL; + /* Advertise 1000Mbps */ + Value32 = + BCM540X_AN_AD_1000BASET_HALF | BCM540X_AN_AD_1000BASET_FULL; #if INCLUDE_5701_AX_FIX - /* Bug: workaround for CRC error in gigabit mode when we are in */ - /* slave mode. This will force the PHY to operate in */ - /* master mode. */ - if(pDevice->ChipRevId == T3_CHIP_ID_5701_A0 || - pDevice->ChipRevId == T3_CHIP_ID_5701_B0) - { - Value32 |= BCM540X_CONFIG_AS_MASTER | - BCM540X_ENABLE_CONFIG_AS_MASTER; - } + /* Bug: workaround for CRC error in gigabit mode when we are in */ + /* slave mode. This will force the PHY to operate in */ + /* master mode. */ + if (pDevice->ChipRevId == T3_CHIP_ID_5701_A0 || + pDevice->ChipRevId == T3_CHIP_ID_5701_B0) { + Value32 |= BCM540X_CONFIG_AS_MASTER | + BCM540X_ENABLE_CONFIG_AS_MASTER; + } #endif - LM_WritePhy(pDevice, BCM540X_1000BASET_CTRL_REG, Value32); - pDevice->advertising1000 = Value32; - } - else - { - if(LineSpeed == LM_LINE_SPEED_1000MBPS) - { - Value32 = PHY_AN_AD_PROTOCOL_802_3_CSMA_CD; - Value32 |= GetPhyAdFlowCntrlSettings(pDevice); + LM_WritePhy (pDevice, BCM540X_1000BASET_CTRL_REG, Value32); + pDevice->advertising1000 = Value32; + } else { + if (LineSpeed == LM_LINE_SPEED_1000MBPS) { + Value32 = PHY_AN_AD_PROTOCOL_802_3_CSMA_CD; + Value32 |= GetPhyAdFlowCntrlSettings (pDevice); - LM_WritePhy(pDevice, PHY_AN_AD_REG, Value32); - pDevice->advertising = Value32; + LM_WritePhy (pDevice, PHY_AN_AD_REG, Value32); + pDevice->advertising = Value32; - if(DuplexMode != LM_DUPLEX_MODE_FULL) - { - Value32 = BCM540X_AN_AD_1000BASET_HALF; - } - else - { - Value32 = BCM540X_AN_AD_1000BASET_FULL; - } + if (DuplexMode != LM_DUPLEX_MODE_FULL) { + Value32 = BCM540X_AN_AD_1000BASET_HALF; + } else { + Value32 = BCM540X_AN_AD_1000BASET_FULL; + } - LM_WritePhy(pDevice, BCM540X_1000BASET_CTRL_REG, Value32); - pDevice->advertising1000 = Value32; - } - else if(LineSpeed == LM_LINE_SPEED_100MBPS) - { - LM_WritePhy(pDevice, BCM540X_1000BASET_CTRL_REG, 0); - pDevice->advertising1000 = 0; + LM_WritePhy (pDevice, BCM540X_1000BASET_CTRL_REG, + Value32); + pDevice->advertising1000 = Value32; + } else if (LineSpeed == LM_LINE_SPEED_100MBPS) { + LM_WritePhy (pDevice, BCM540X_1000BASET_CTRL_REG, 0); + pDevice->advertising1000 = 0; - if(DuplexMode != LM_DUPLEX_MODE_FULL) - { - Value32 = PHY_AN_AD_100BASETX_HALF; - } - else - { - Value32 = PHY_AN_AD_100BASETX_FULL; - } + if (DuplexMode != LM_DUPLEX_MODE_FULL) { + Value32 = PHY_AN_AD_100BASETX_HALF; + } else { + Value32 = PHY_AN_AD_100BASETX_FULL; + } - Value32 |= PHY_AN_AD_PROTOCOL_802_3_CSMA_CD; - Value32 |= GetPhyAdFlowCntrlSettings(pDevice); + Value32 |= PHY_AN_AD_PROTOCOL_802_3_CSMA_CD; + Value32 |= GetPhyAdFlowCntrlSettings (pDevice); - LM_WritePhy(pDevice, PHY_AN_AD_REG, Value32); - pDevice->advertising = Value32; - } - else if(LineSpeed == LM_LINE_SPEED_10MBPS) - { - LM_WritePhy(pDevice, BCM540X_1000BASET_CTRL_REG, 0); - pDevice->advertising1000 = 0; + LM_WritePhy (pDevice, PHY_AN_AD_REG, Value32); + pDevice->advertising = Value32; + } else if (LineSpeed == LM_LINE_SPEED_10MBPS) { + LM_WritePhy (pDevice, BCM540X_1000BASET_CTRL_REG, 0); + pDevice->advertising1000 = 0; - if(DuplexMode != LM_DUPLEX_MODE_FULL) - { - Value32 = PHY_AN_AD_10BASET_HALF; - } - else - { - Value32 = PHY_AN_AD_10BASET_FULL; - } + if (DuplexMode != LM_DUPLEX_MODE_FULL) { + Value32 = PHY_AN_AD_10BASET_HALF; + } else { + Value32 = PHY_AN_AD_10BASET_FULL; + } - Value32 |= PHY_AN_AD_PROTOCOL_802_3_CSMA_CD; - Value32 |= GetPhyAdFlowCntrlSettings(pDevice); + Value32 |= PHY_AN_AD_PROTOCOL_802_3_CSMA_CD; + Value32 |= GetPhyAdFlowCntrlSettings (pDevice); - LM_WritePhy(pDevice, PHY_AN_AD_REG, Value32); - pDevice->advertising = Value32; - } - } - - /* Force line speed if auto-negotiation is disabled. */ - if(pDevice->DisableAutoNeg && LineSpeed != LM_LINE_SPEED_UNKNOWN) - { - /* This code path is executed only when there is link. */ - pDevice->MediaType = MediaType; - pDevice->LineSpeed = LineSpeed; - pDevice->DuplexMode = DuplexMode; - - /* Force line seepd. */ - NewPhyCtrl = 0; - switch(LineSpeed) - { - case LM_LINE_SPEED_10MBPS: - NewPhyCtrl |= PHY_CTRL_SPEED_SELECT_10MBPS; - break; - case LM_LINE_SPEED_100MBPS: - NewPhyCtrl |= PHY_CTRL_SPEED_SELECT_100MBPS; - break; - case LM_LINE_SPEED_1000MBPS: - NewPhyCtrl |= PHY_CTRL_SPEED_SELECT_1000MBPS; - break; - default: - NewPhyCtrl |= PHY_CTRL_SPEED_SELECT_1000MBPS; - break; - } - - if(DuplexMode == LM_DUPLEX_MODE_FULL) - { - NewPhyCtrl |= PHY_CTRL_FULL_DUPLEX_MODE; - } - - /* Don't do anything if the PHY_CTRL is already what we wanted. */ - LM_ReadPhy(pDevice, PHY_CTRL_REG, &Value32); - if(Value32 != NewPhyCtrl) - { - /* Temporary bring the link down before forcing line speed. */ - LM_WritePhy(pDevice, PHY_CTRL_REG, PHY_CTRL_LOOPBACK_MODE); - - /* Wait for link to go down. */ - for(Cnt = 0; Cnt < 15000; Cnt++) - { - MM_Wait(10); - - LM_ReadPhy(pDevice, PHY_STATUS_REG, &Value32); - LM_ReadPhy(pDevice, PHY_STATUS_REG, &Value32); - - if(!(Value32 & PHY_STATUS_LINK_PASS)) - { - MM_Wait(40); - break; + LM_WritePhy (pDevice, PHY_AN_AD_REG, Value32); + pDevice->advertising = Value32; } - } - - LM_WritePhy(pDevice, PHY_CTRL_REG, NewPhyCtrl); - MM_Wait(40); } - } - else - { - LM_WritePhy(pDevice, PHY_CTRL_REG, PHY_CTRL_AUTO_NEG_ENABLE | - PHY_CTRL_RESTART_AUTO_NEG); - } - return LM_STATUS_SUCCESS; -} /* LM_ForceAutoNegBcm540xPhy */ + /* Force line speed if auto-negotiation is disabled. */ + if (pDevice->DisableAutoNeg && LineSpeed != LM_LINE_SPEED_UNKNOWN) { + /* This code path is executed only when there is link. */ + pDevice->MediaType = MediaType; + pDevice->LineSpeed = LineSpeed; + pDevice->DuplexMode = DuplexMode; + /* Force line seepd. */ + NewPhyCtrl = 0; + switch (LineSpeed) { + case LM_LINE_SPEED_10MBPS: + NewPhyCtrl |= PHY_CTRL_SPEED_SELECT_10MBPS; + break; + case LM_LINE_SPEED_100MBPS: + NewPhyCtrl |= PHY_CTRL_SPEED_SELECT_100MBPS; + break; + case LM_LINE_SPEED_1000MBPS: + NewPhyCtrl |= PHY_CTRL_SPEED_SELECT_1000MBPS; + break; + default: + NewPhyCtrl |= PHY_CTRL_SPEED_SELECT_1000MBPS; + break; + } + + if (DuplexMode == LM_DUPLEX_MODE_FULL) { + NewPhyCtrl |= PHY_CTRL_FULL_DUPLEX_MODE; + } + + /* Don't do anything if the PHY_CTRL is already what we wanted. */ + LM_ReadPhy (pDevice, PHY_CTRL_REG, &Value32); + if (Value32 != NewPhyCtrl) { + /* Temporary bring the link down before forcing line speed. */ + LM_WritePhy (pDevice, PHY_CTRL_REG, + PHY_CTRL_LOOPBACK_MODE); + + /* Wait for link to go down. */ + for (Cnt = 0; Cnt < 15000; Cnt++) { + MM_Wait (10); + + LM_ReadPhy (pDevice, PHY_STATUS_REG, &Value32); + LM_ReadPhy (pDevice, PHY_STATUS_REG, &Value32); + + if (!(Value32 & PHY_STATUS_LINK_PASS)) { + MM_Wait (40); + break; + } + } + + LM_WritePhy (pDevice, PHY_CTRL_REG, NewPhyCtrl); + MM_Wait (40); + } + } else { + LM_WritePhy (pDevice, PHY_CTRL_REG, PHY_CTRL_AUTO_NEG_ENABLE | + PHY_CTRL_RESTART_AUTO_NEG); + } + + return LM_STATUS_SUCCESS; +} /* LM_ForceAutoNegBcm540xPhy */ /******************************************************************************/ /* Description: */ @@ -5828,218 +5347,199 @@ LM_REQUESTED_MEDIA_TYPE RequestedMediaType) /* Return: */ /******************************************************************************/ static LM_STATUS -LM_ForceAutoNeg( -PLM_DEVICE_BLOCK pDevice, -LM_REQUESTED_MEDIA_TYPE RequestedMediaType) +LM_ForceAutoNeg (PLM_DEVICE_BLOCK pDevice, + LM_REQUESTED_MEDIA_TYPE RequestedMediaType) { - LM_STATUS LmStatus; + LM_STATUS LmStatus; - /* Initialize the phy chip. */ - switch(pDevice->PhyId & PHY_ID_MASK) - { + /* Initialize the phy chip. */ + switch (pDevice->PhyId & PHY_ID_MASK) { case PHY_BCM5400_PHY_ID: case PHY_BCM5401_PHY_ID: case PHY_BCM5411_PHY_ID: case PHY_BCM5701_PHY_ID: case PHY_BCM5703_PHY_ID: case PHY_BCM5704_PHY_ID: - LmStatus = LM_ForceAutoNegBcm540xPhy(pDevice, RequestedMediaType); - break; + LmStatus = + LM_ForceAutoNegBcm540xPhy (pDevice, RequestedMediaType); + break; default: - LmStatus = LM_STATUS_FAILURE; - break; - } + LmStatus = LM_STATUS_FAILURE; + break; + } - return LmStatus; -} /* LM_ForceAutoNeg */ + return LmStatus; +} /* LM_ForceAutoNeg */ /******************************************************************************/ /* Description: */ /* */ /* Return: */ /******************************************************************************/ -LM_STATUS LM_LoadFirmware(PLM_DEVICE_BLOCK pDevice, - PT3_FWIMG_INFO pFwImg, - LM_UINT32 LoadCpu, - LM_UINT32 StartCpu) +LM_STATUS LM_LoadFirmware (PLM_DEVICE_BLOCK pDevice, + PT3_FWIMG_INFO pFwImg, + LM_UINT32 LoadCpu, LM_UINT32 StartCpu) { - LM_UINT32 i; - LM_UINT32 address; + LM_UINT32 i; + LM_UINT32 address; - if (LoadCpu & T3_RX_CPU_ID) - { - if (LM_HaltCpu(pDevice,T3_RX_CPU_ID) != LM_STATUS_SUCCESS) - { - return LM_STATUS_FAILURE; + if (LoadCpu & T3_RX_CPU_ID) { + if (LM_HaltCpu (pDevice, T3_RX_CPU_ID) != LM_STATUS_SUCCESS) { + return LM_STATUS_FAILURE; + } + + /* First of all clear scrach pad memory */ + for (i = 0; i < T3_RX_CPU_SPAD_SIZE; i += 4) { + LM_RegWrInd (pDevice, T3_RX_CPU_SPAD_ADDR + i, 0); + } + + /* Copy code first */ + address = T3_RX_CPU_SPAD_ADDR + (pFwImg->Text.Offset & 0xffff); + for (i = 0; i <= pFwImg->Text.Length; i += 4) { + LM_RegWrInd (pDevice, address + i, + ((LM_UINT32 *) pFwImg->Text.Buffer)[i / + 4]); + } + + address = + T3_RX_CPU_SPAD_ADDR + (pFwImg->ROnlyData.Offset & 0xffff); + for (i = 0; i <= pFwImg->ROnlyData.Length; i += 4) { + LM_RegWrInd (pDevice, address + i, + ((LM_UINT32 *) pFwImg->ROnlyData. + Buffer)[i / 4]); + } + + address = T3_RX_CPU_SPAD_ADDR + (pFwImg->Data.Offset & 0xffff); + for (i = 0; i <= pFwImg->Data.Length; i += 4) { + LM_RegWrInd (pDevice, address + i, + ((LM_UINT32 *) pFwImg->Data.Buffer)[i / + 4]); + } } - /* First of all clear scrach pad memory */ - for (i = 0; i < T3_RX_CPU_SPAD_SIZE; i+=4) - { - LM_RegWrInd(pDevice,T3_RX_CPU_SPAD_ADDR+i,0); + if (LoadCpu & T3_TX_CPU_ID) { + if (LM_HaltCpu (pDevice, T3_TX_CPU_ID) != LM_STATUS_SUCCESS) { + return LM_STATUS_FAILURE; + } + + /* First of all clear scrach pad memory */ + for (i = 0; i < T3_TX_CPU_SPAD_SIZE; i += 4) { + LM_RegWrInd (pDevice, T3_TX_CPU_SPAD_ADDR + i, 0); + } + + /* Copy code first */ + address = T3_TX_CPU_SPAD_ADDR + (pFwImg->Text.Offset & 0xffff); + for (i = 0; i <= pFwImg->Text.Length; i += 4) { + LM_RegWrInd (pDevice, address + i, + ((LM_UINT32 *) pFwImg->Text.Buffer)[i / + 4]); + } + + address = + T3_TX_CPU_SPAD_ADDR + (pFwImg->ROnlyData.Offset & 0xffff); + for (i = 0; i <= pFwImg->ROnlyData.Length; i += 4) { + LM_RegWrInd (pDevice, address + i, + ((LM_UINT32 *) pFwImg->ROnlyData. + Buffer)[i / 4]); + } + + address = T3_TX_CPU_SPAD_ADDR + (pFwImg->Data.Offset & 0xffff); + for (i = 0; i <= pFwImg->Data.Length; i += 4) { + LM_RegWrInd (pDevice, address + i, + ((LM_UINT32 *) pFwImg->Data.Buffer)[i / + 4]); + } } - /* Copy code first */ - address = T3_RX_CPU_SPAD_ADDR + (pFwImg->Text.Offset & 0xffff); - for (i = 0; i <= pFwImg->Text.Length; i+=4) - { - LM_RegWrInd(pDevice,address+i, - ((LM_UINT32 *)pFwImg->Text.Buffer)[i/4]); + if (StartCpu & T3_RX_CPU_ID) { + /* Start Rx CPU */ + REG_WR (pDevice, rxCpu.reg.state, 0xffffffff); + REG_WR (pDevice, rxCpu.reg.PC, pFwImg->StartAddress); + for (i = 0; i < 5; i++) { + if (pFwImg->StartAddress == + REG_RD (pDevice, rxCpu.reg.PC)) + break; + + REG_WR (pDevice, rxCpu.reg.state, 0xffffffff); + REG_WR (pDevice, rxCpu.reg.mode, CPU_MODE_HALT); + REG_WR (pDevice, rxCpu.reg.PC, pFwImg->StartAddress); + MM_Wait (1000); + } + + REG_WR (pDevice, rxCpu.reg.state, 0xffffffff); + REG_WR (pDevice, rxCpu.reg.mode, 0); } - address = T3_RX_CPU_SPAD_ADDR + (pFwImg->ROnlyData.Offset & 0xffff); - for (i = 0; i <= pFwImg->ROnlyData.Length; i+=4) - { - LM_RegWrInd(pDevice,address+i, - ((LM_UINT32 *)pFwImg->ROnlyData.Buffer)[i/4]); + if (StartCpu & T3_TX_CPU_ID) { + /* Start Tx CPU */ + REG_WR (pDevice, txCpu.reg.state, 0xffffffff); + REG_WR (pDevice, txCpu.reg.PC, pFwImg->StartAddress); + for (i = 0; i < 5; i++) { + if (pFwImg->StartAddress == + REG_RD (pDevice, txCpu.reg.PC)) + break; + + REG_WR (pDevice, txCpu.reg.state, 0xffffffff); + REG_WR (pDevice, txCpu.reg.mode, CPU_MODE_HALT); + REG_WR (pDevice, txCpu.reg.PC, pFwImg->StartAddress); + MM_Wait (1000); + } + + REG_WR (pDevice, txCpu.reg.state, 0xffffffff); + REG_WR (pDevice, txCpu.reg.mode, 0); } - address = T3_RX_CPU_SPAD_ADDR + (pFwImg->Data.Offset & 0xffff); - for (i= 0; i <= pFwImg->Data.Length; i+=4) - { - LM_RegWrInd(pDevice,address+i, - ((LM_UINT32 *)pFwImg->Data.Buffer)[i/4]); - } - } - - if (LoadCpu & T3_TX_CPU_ID) - { - if (LM_HaltCpu(pDevice,T3_TX_CPU_ID) != LM_STATUS_SUCCESS) - { - return LM_STATUS_FAILURE; - } - - /* First of all clear scrach pad memory */ - for (i = 0; i < T3_TX_CPU_SPAD_SIZE; i+=4) - { - LM_RegWrInd(pDevice,T3_TX_CPU_SPAD_ADDR+i,0); - } - - /* Copy code first */ - address = T3_TX_CPU_SPAD_ADDR + (pFwImg->Text.Offset & 0xffff); - for (i= 0; i <= pFwImg->Text.Length; i+=4) - { - LM_RegWrInd(pDevice,address+i, - ((LM_UINT32 *)pFwImg->Text.Buffer)[i/4]); - } - - address = T3_TX_CPU_SPAD_ADDR + (pFwImg->ROnlyData.Offset & 0xffff); - for (i= 0; i <= pFwImg->ROnlyData.Length; i+=4) - { - LM_RegWrInd(pDevice,address+i, - ((LM_UINT32 *)pFwImg->ROnlyData.Buffer)[i/4]); - } - - address = T3_TX_CPU_SPAD_ADDR + (pFwImg->Data.Offset & 0xffff); - for (i= 0; i <= pFwImg->Data.Length; i+=4) - { - LM_RegWrInd(pDevice,address+i, - ((LM_UINT32 *)pFwImg->Data.Buffer)[i/4]); - } - } - - if (StartCpu & T3_RX_CPU_ID) - { - /* Start Rx CPU */ - REG_WR(pDevice,rxCpu.reg.state, 0xffffffff); - REG_WR(pDevice,rxCpu.reg.PC,pFwImg->StartAddress); - for (i = 0 ; i < 5; i++) - { - if (pFwImg->StartAddress == REG_RD(pDevice,rxCpu.reg.PC)) - break; - - REG_WR(pDevice,rxCpu.reg.state, 0xffffffff); - REG_WR(pDevice,rxCpu.reg.mode,CPU_MODE_HALT); - REG_WR(pDevice,rxCpu.reg.PC,pFwImg->StartAddress); - MM_Wait(1000); - } - - REG_WR(pDevice,rxCpu.reg.state, 0xffffffff); - REG_WR(pDevice,rxCpu.reg.mode, 0); - } - - if (StartCpu & T3_TX_CPU_ID) - { - /* Start Tx CPU */ - REG_WR(pDevice,txCpu.reg.state, 0xffffffff); - REG_WR(pDevice,txCpu.reg.PC,pFwImg->StartAddress); - for (i = 0 ; i < 5; i++) - { - if (pFwImg->StartAddress == REG_RD(pDevice,txCpu.reg.PC)) - break; - - REG_WR(pDevice,txCpu.reg.state, 0xffffffff); - REG_WR(pDevice,txCpu.reg.mode,CPU_MODE_HALT); - REG_WR(pDevice,txCpu.reg.PC,pFwImg->StartAddress); - MM_Wait(1000); - } - - REG_WR(pDevice,txCpu.reg.state, 0xffffffff); - REG_WR(pDevice,txCpu.reg.mode, 0); - } - - return LM_STATUS_SUCCESS; + return LM_STATUS_SUCCESS; } -STATIC LM_STATUS LM_HaltCpu(PLM_DEVICE_BLOCK pDevice,LM_UINT32 cpu_number) +STATIC LM_STATUS LM_HaltCpu (PLM_DEVICE_BLOCK pDevice, LM_UINT32 cpu_number) { - LM_UINT32 i; + LM_UINT32 i; - if (cpu_number == T3_RX_CPU_ID) - { - for (i = 0 ; i < 10000; i++) - { - REG_WR(pDevice,rxCpu.reg.state, 0xffffffff); - REG_WR(pDevice,rxCpu.reg.mode,CPU_MODE_HALT); + if (cpu_number == T3_RX_CPU_ID) { + for (i = 0; i < 10000; i++) { + REG_WR (pDevice, rxCpu.reg.state, 0xffffffff); + REG_WR (pDevice, rxCpu.reg.mode, CPU_MODE_HALT); - if (REG_RD(pDevice,rxCpu.reg.mode) & CPU_MODE_HALT) - break; + if (REG_RD (pDevice, rxCpu.reg.mode) & CPU_MODE_HALT) + break; + } + + REG_WR (pDevice, rxCpu.reg.state, 0xffffffff); + REG_WR (pDevice, rxCpu.reg.mode, CPU_MODE_HALT); + MM_Wait (10); + } else { + for (i = 0; i < 10000; i++) { + REG_WR (pDevice, txCpu.reg.state, 0xffffffff); + REG_WR (pDevice, txCpu.reg.mode, CPU_MODE_HALT); + + if (REG_RD (pDevice, txCpu.reg.mode) & CPU_MODE_HALT) + break; + } } - REG_WR(pDevice,rxCpu.reg.state, 0xffffffff); - REG_WR(pDevice,rxCpu.reg.mode,CPU_MODE_HALT); - MM_Wait(10); - } - else - { - for (i = 0 ; i < 10000; i++) - { - REG_WR(pDevice,txCpu.reg.state, 0xffffffff); - REG_WR(pDevice,txCpu.reg.mode,CPU_MODE_HALT); - - if (REG_RD(pDevice,txCpu.reg.mode) & CPU_MODE_HALT) - break; - } - } - - return (( i == 10000) ? LM_STATUS_FAILURE : LM_STATUS_SUCCESS); + return ((i == 10000) ? LM_STATUS_FAILURE : LM_STATUS_SUCCESS); } - -int -LM_BlinkLED(PLM_DEVICE_BLOCK pDevice, LM_UINT32 BlinkDurationSec) +int LM_BlinkLED (PLM_DEVICE_BLOCK pDevice, LM_UINT32 BlinkDurationSec) { LM_UINT32 Oldcfg; int j; int ret = 0; - if(BlinkDurationSec == 0) - { + if (BlinkDurationSec == 0) { return 0; } - if(BlinkDurationSec > 120) - { + if (BlinkDurationSec > 120) { BlinkDurationSec = 120; } - Oldcfg = REG_RD(pDevice, MacCtrl.LedCtrl); - for(j = 0; j < BlinkDurationSec * 2; j++) - { - if(j % 2) - { + Oldcfg = REG_RD (pDevice, MacCtrl.LedCtrl); + for (j = 0; j < BlinkDurationSec * 2; j++) { + if (j % 2) { /* Turn on the LEDs. */ - REG_WR(pDevice, MacCtrl.LedCtrl, + REG_WR (pDevice, MacCtrl.LedCtrl, LED_CTRL_OVERRIDE_LINK_LED | LED_CTRL_1000MBPS_LED_ON | LED_CTRL_100MBPS_LED_ON | @@ -6047,154 +5547,152 @@ LM_BlinkLED(PLM_DEVICE_BLOCK pDevice, LM_UINT32 BlinkDurationSec) LED_CTRL_OVERRIDE_TRAFFIC_LED | LED_CTRL_BLINK_TRAFFIC_LED | LED_CTRL_TRAFFIC_LED); - } - else - { + } else { /* Turn off the LEDs. */ - REG_WR(pDevice, MacCtrl.LedCtrl, + REG_WR (pDevice, MacCtrl.LedCtrl, LED_CTRL_OVERRIDE_LINK_LED | LED_CTRL_OVERRIDE_TRAFFIC_LED); } #ifndef EMBEDDED current->state = TASK_INTERRUPTIBLE; - if (schedule_timeout(HZ/2) != 0) { + if (schedule_timeout (HZ / 2) != 0) { ret = -EINTR; break; } #else - udelay(100000); /* 1s sleep */ + udelay (100000); /* 1s sleep */ #endif } - REG_WR(pDevice, MacCtrl.LedCtrl, Oldcfg); + REG_WR (pDevice, MacCtrl.LedCtrl, Oldcfg); return ret; } -int t3_do_dma(PLM_DEVICE_BLOCK pDevice, - LM_PHYSICAL_ADDRESS host_addr_phy, int length, - int dma_read) +int t3_do_dma (PLM_DEVICE_BLOCK pDevice, + LM_PHYSICAL_ADDRESS host_addr_phy, int length, int dma_read) { - T3_DMA_DESC dma_desc; - int i; - LM_UINT32 dma_desc_addr; - LM_UINT32 value32; + T3_DMA_DESC dma_desc; + int i; + LM_UINT32 dma_desc_addr; + LM_UINT32 value32; - REG_WR(pDevice, BufMgr.Mode, 0); - REG_WR(pDevice, Ftq.Reset, 0); + REG_WR (pDevice, BufMgr.Mode, 0); + REG_WR (pDevice, Ftq.Reset, 0); - dma_desc.host_addr.High = host_addr_phy.High; - dma_desc.host_addr.Low = host_addr_phy.Low; - dma_desc.nic_mbuf = 0x2100; - dma_desc.len = length; - dma_desc.flags = 0x00000004; /* Generate Rx-CPU event */ + dma_desc.host_addr.High = host_addr_phy.High; + dma_desc.host_addr.Low = host_addr_phy.Low; + dma_desc.nic_mbuf = 0x2100; + dma_desc.len = length; + dma_desc.flags = 0x00000004; /* Generate Rx-CPU event */ - if (dma_read) - { - dma_desc.cqid_sqid = (T3_QID_RX_BD_COMP << 8) | - T3_QID_DMA_HIGH_PRI_READ; - REG_WR(pDevice, DmaRead.Mode, DMA_READ_MODE_ENABLE); - } - else - { - dma_desc.cqid_sqid = (T3_QID_RX_DATA_COMP << 8) | - T3_QID_DMA_HIGH_PRI_WRITE; - REG_WR(pDevice, DmaWrite.Mode, DMA_WRITE_MODE_ENABLE); - } + if (dma_read) { + dma_desc.cqid_sqid = (T3_QID_RX_BD_COMP << 8) | + T3_QID_DMA_HIGH_PRI_READ; + REG_WR (pDevice, DmaRead.Mode, DMA_READ_MODE_ENABLE); + } else { + dma_desc.cqid_sqid = (T3_QID_RX_DATA_COMP << 8) | + T3_QID_DMA_HIGH_PRI_WRITE; + REG_WR (pDevice, DmaWrite.Mode, DMA_WRITE_MODE_ENABLE); + } - dma_desc_addr = T3_NIC_DMA_DESC_POOL_ADDR; + dma_desc_addr = T3_NIC_DMA_DESC_POOL_ADDR; - /* Writing this DMA descriptor to DMA memory */ - for (i = 0; i < sizeof(T3_DMA_DESC); i += 4) - { - value32 = *((PLM_UINT32) (((PLM_UINT8) &dma_desc) + i)); - MM_WriteConfig32(pDevice, T3_PCI_MEM_WIN_ADDR_REG, dma_desc_addr+i); - MM_WriteConfig32(pDevice, T3_PCI_MEM_WIN_DATA_REG, cpu_to_le32(value32)); - } - MM_WriteConfig32(pDevice, T3_PCI_MEM_WIN_ADDR_REG, 0); + /* Writing this DMA descriptor to DMA memory */ + for (i = 0; i < sizeof (T3_DMA_DESC); i += 4) { + value32 = *((PLM_UINT32) (((PLM_UINT8) & dma_desc) + i)); + MM_WriteConfig32 (pDevice, T3_PCI_MEM_WIN_ADDR_REG, + dma_desc_addr + i); + MM_WriteConfig32 (pDevice, T3_PCI_MEM_WIN_DATA_REG, + cpu_to_le32 (value32)); + } + MM_WriteConfig32 (pDevice, T3_PCI_MEM_WIN_ADDR_REG, 0); - if (dma_read) - REG_WR(pDevice, Ftq.DmaHighReadFtqFifoEnqueueDequeue, dma_desc_addr); - else - REG_WR(pDevice, Ftq.DmaHighWriteFtqFifoEnqueueDequeue, dma_desc_addr); - - for (i = 0; i < 40; i++) - { if (dma_read) - value32 = REG_RD(pDevice, Ftq.RcvBdCompFtqFifoEnqueueDequeue); + REG_WR (pDevice, Ftq.DmaHighReadFtqFifoEnqueueDequeue, + dma_desc_addr); else - value32 = REG_RD(pDevice, Ftq.RcvDataCompFtqFifoEnqueueDequeue); + REG_WR (pDevice, Ftq.DmaHighWriteFtqFifoEnqueueDequeue, + dma_desc_addr); - if ((value32 & 0xffff) == dma_desc_addr) - break; + for (i = 0; i < 40; i++) { + if (dma_read) + value32 = + REG_RD (pDevice, + Ftq.RcvBdCompFtqFifoEnqueueDequeue); + else + value32 = + REG_RD (pDevice, + Ftq.RcvDataCompFtqFifoEnqueueDequeue); - MM_Wait(10); - } + if ((value32 & 0xffff) == dma_desc_addr) + break; - return LM_STATUS_SUCCESS; + MM_Wait (10); + } + + return LM_STATUS_SUCCESS; } STATIC LM_STATUS -LM_DmaTest(PLM_DEVICE_BLOCK pDevice, PLM_UINT8 pBufferVirt, - LM_PHYSICAL_ADDRESS BufferPhy, LM_UINT32 BufferSize) +LM_DmaTest (PLM_DEVICE_BLOCK pDevice, PLM_UINT8 pBufferVirt, + LM_PHYSICAL_ADDRESS BufferPhy, LM_UINT32 BufferSize) { - int j; - LM_UINT32 *ptr; - int dma_success = 0; + int j; + LM_UINT32 *ptr; + int dma_success = 0; - if(T3_ASIC_REV(pDevice->ChipRevId) != T3_ASIC_REV_5700 && - T3_ASIC_REV(pDevice->ChipRevId) != T3_ASIC_REV_5701) - { + if (T3_ASIC_REV (pDevice->ChipRevId) != T3_ASIC_REV_5700 && + T3_ASIC_REV (pDevice->ChipRevId) != T3_ASIC_REV_5701) { + return LM_STATUS_SUCCESS; + } + while (!dma_success) { + /* Fill data with incremental patterns */ + ptr = (LM_UINT32 *) pBufferVirt; + for (j = 0; j < BufferSize / 4; j++) + *ptr++ = j; + + if (t3_do_dma (pDevice, BufferPhy, BufferSize, 1) == + LM_STATUS_FAILURE) { + return LM_STATUS_FAILURE; + } + + MM_Wait (40); + ptr = (LM_UINT32 *) pBufferVirt; + /* Fill data with zero */ + for (j = 0; j < BufferSize / 4; j++) + *ptr++ = 0; + + if (t3_do_dma (pDevice, BufferPhy, BufferSize, 0) == + LM_STATUS_FAILURE) { + return LM_STATUS_FAILURE; + } + + MM_Wait (40); + /* Check for data */ + ptr = (LM_UINT32 *) pBufferVirt; + for (j = 0; j < BufferSize / 4; j++) { + if (*ptr++ != j) { + if ((pDevice-> + DmaReadWriteCtrl & + DMA_CTRL_WRITE_BOUNDARY_MASK) + == DMA_CTRL_WRITE_BOUNDARY_DISABLE) { + pDevice->DmaReadWriteCtrl = + (pDevice-> + DmaReadWriteCtrl & + ~DMA_CTRL_WRITE_BOUNDARY_MASK) | + DMA_CTRL_WRITE_BOUNDARY_16; + REG_WR (pDevice, + PciCfg.DmaReadWriteCtrl, + pDevice->DmaReadWriteCtrl); + break; + } else { + return LM_STATUS_FAILURE; + } + } + } + if (j == (BufferSize / 4)) + dma_success = 1; + } return LM_STATUS_SUCCESS; - } - while (!dma_success) - { - /* Fill data with incremental patterns */ - ptr = (LM_UINT32 *)pBufferVirt; - for (j = 0; j < BufferSize/4; j++) - *ptr++ = j; - - if (t3_do_dma(pDevice,BufferPhy,BufferSize, 1) == LM_STATUS_FAILURE) - { - return LM_STATUS_FAILURE; - } - - MM_Wait(40); - ptr = (LM_UINT32 *)pBufferVirt; - /* Fill data with zero */ - for (j = 0; j < BufferSize/4; j++) - *ptr++ = 0; - - if (t3_do_dma(pDevice,BufferPhy,BufferSize, 0) == LM_STATUS_FAILURE) - { - return LM_STATUS_FAILURE; - } - - MM_Wait(40); - /* Check for data */ - ptr = (LM_UINT32 *)pBufferVirt; - for (j = 0; j < BufferSize/4; j++) - { - if (*ptr++ != j) - { - if ((pDevice->DmaReadWriteCtrl & DMA_CTRL_WRITE_BOUNDARY_MASK) - == DMA_CTRL_WRITE_BOUNDARY_DISABLE) - { - pDevice->DmaReadWriteCtrl = (pDevice->DmaReadWriteCtrl & - ~DMA_CTRL_WRITE_BOUNDARY_MASK) | - DMA_CTRL_WRITE_BOUNDARY_16; - REG_WR(pDevice, PciCfg.DmaReadWriteCtrl, - pDevice->DmaReadWriteCtrl); - break; - } - else - { - return LM_STATUS_FAILURE; - } - } - } - if (j == (BufferSize/4)) - dma_success = 1; - } - return LM_STATUS_SUCCESS; } -#endif /* CFG_CMD_NET, !CONFIG_NET_MULTI, CONFIG_TIGON3 */ +#endif /* CFG_CMD_NET, !CONFIG_NET_MULTI, CONFIG_TIGON3 */ diff --git a/drivers/tigon3.h b/drivers/tigon3.h index ea4367d61..c03347fdc 100644 --- a/drivers/tigon3.h +++ b/drivers/tigon3.h @@ -21,7 +21,6 @@ #include "bcm570x_autoneg.h" #endif - /* io defines */ #if !defined(BIG_ENDIAN_HOST) #define readl(addr) \ @@ -29,7 +28,7 @@ #define writel(b,addr) \ ((*(volatile unsigned int *)(addr)) = (LONGSWAP(b))) #else -#if 0 /* !defined(PPC603) */ +#if 0 /* !defined(PPC603) */ #define readl(addr) (*(volatile unsigned int*)(0xa0000000 + (unsigned long)(addr))) #define writel(b,addr) ((*(volatile unsigned int *) ((unsigned long)(addr) + 0xa0000000)) = (b)) #else @@ -37,25 +36,28 @@ #define readl(addr) (*(volatile unsigned int*)(addr)) #define writel(b,addr) ((*(volatile unsigned int *) (addr)) = (b)) #else -extern int sprintf(char* buf, const char* f, ...); -static __inline unsigned int readl(void* addr){ - char buf[128]; - unsigned int tmp = (*(volatile unsigned int*)(addr)); - sprintf(buf,"%s:%s: read 0x%x from 0x%x\n",__FILE__,__LINE__,tmp,addr,0,0); - sysSerialPrintString(buf); - return tmp; +extern int sprintf (char *buf, const char *f, ...); +static __inline unsigned int readl (void *addr) +{ + char buf[128]; + unsigned int tmp = (*(volatile unsigned int *)(addr)); + sprintf (buf, "%s:%s: read 0x%x from 0x%x\n", __FILE__, __LINE__, tmp, + addr, 0, 0); + sysSerialPrintString (buf); + return tmp; } -static __inline void writel(unsigned int b, unsigned int addr){ - char buf[128]; - ((*(volatile unsigned int *) (addr)) = (b)); - sprintf(buf,"%s:%s: write 0x%x to 0x%x\n",__FILE__,__LINE__,b,addr,0,0); - sysSerialPrintString(buf); +static __inline void writel (unsigned int b, unsigned int addr) +{ + char buf[128]; + ((*(volatile unsigned int *)(addr)) = (b)); + sprintf (buf, "%s:%s: write 0x%x to 0x%x\n", __FILE__, __LINE__, b, + addr, 0, 0); + sysSerialPrintString (buf); } #endif -#endif /* PPC603 */ +#endif /* PPC603 */ #endif - /******************************************************************************/ /* Constants. */ /******************************************************************************/ @@ -90,7 +92,7 @@ static __inline void writel(unsigned int b, unsigned int addr){ /* B0 bug. */ #define BCM5700_BX_MIN_FRAG_SIZE 10 -#define BCM5700_BX_MIN_FRAG_BUF_SIZE 16 /* nice aligned size. */ +#define BCM5700_BX_MIN_FRAG_BUF_SIZE 16 /* nice aligned size. */ #define BCM5700_BX_MIN_FRAG_BUF_SIZE_MASK (BCM5700_BX_MIN_FRAG_BUF_SIZE-1) #define BCM5700_BX_TX_COPY_BUF_SIZE (BCM5700_BX_MIN_FRAG_BUF_SIZE * \ MAX_FRAGMENT_COUNT) @@ -161,32 +163,32 @@ static __inline void writel(unsigned int b, unsigned int addr){ /* Number of entries in the Standard Receive RCB. Must be 512 entries. */ #define T3_STD_RCV_RCB_ENTRY_COUNT 512 #define T3_STD_RCV_RCB_ENTRY_COUNT_MASK (T3_STD_RCV_RCB_ENTRY_COUNT-1) -#define DEFAULT_STD_RCV_DESC_COUNT 200 /* Must be < 512. */ +#define DEFAULT_STD_RCV_DESC_COUNT 200 /* Must be < 512. */ #define MAX_STD_RCV_BUFFER_SIZE 0x600 /* Number of entries in the Mini Receive RCB. This value can either be */ /* 0, 1024. Currently Mini Receive RCB is disabled. */ #ifndef T3_MINI_RCV_RCB_ENTRY_COUNT #define T3_MINI_RCV_RCB_ENTRY_COUNT 0 -#endif /* T3_MINI_RCV_RCB_ENTRY_COUNT */ +#endif /* T3_MINI_RCV_RCB_ENTRY_COUNT */ #define T3_MINI_RCV_RCB_ENTRY_COUNT_MASK (T3_MINI_RCV_RCB_ENTRY_COUNT-1) #define MAX_MINI_RCV_BUFFER_SIZE 512 #define DEFAULT_MINI_RCV_BUFFER_SIZE 64 -#define DEFAULT_MINI_RCV_DESC_COUNT 100 /* Must be < 1024. */ +#define DEFAULT_MINI_RCV_DESC_COUNT 100 /* Must be < 1024. */ /* Number of entries in the Jumbo Receive RCB. This value must 256 or 0. */ /* Currently, Jumbo Receive RCB is disabled. */ #ifndef T3_JUMBO_RCV_RCB_ENTRY_COUNT #define T3_JUMBO_RCV_RCB_ENTRY_COUNT 0 -#endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */ +#endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */ #define T3_JUMBO_RCV_RCB_ENTRY_COUNT_MASK (T3_JUMBO_RCV_RCB_ENTRY_COUNT-1) -#define MAX_JUMBO_RCV_BUFFER_SIZE (10 * 1024) /* > 1514 */ -#define DEFAULT_JUMBO_RCV_BUFFER_SIZE (4 * 1024) /* > 1514 */ -#define DEFAULT_JUMBO_RCV_DESC_COUNT 128 /* Must be < 256. */ +#define MAX_JUMBO_RCV_BUFFER_SIZE (10 * 1024) /* > 1514 */ +#define DEFAULT_JUMBO_RCV_BUFFER_SIZE (4 * 1024) /* > 1514 */ +#define DEFAULT_JUMBO_RCV_DESC_COUNT 128 /* Must be < 256. */ -#define MAX_JUMBO_TX_BUFFER_SIZE (8 * 1024) /* > 1514 */ -#define DEFAULT_JUMBO_TX_BUFFER_SIZE (4 * 1024) /* > 1514 */ +#define MAX_JUMBO_TX_BUFFER_SIZE (8 * 1024) /* > 1514 */ +#define DEFAULT_JUMBO_TX_BUFFER_SIZE (4 * 1024) /* > 1514 */ /* Number of receive return RCBs. Maybe 1-16 but for now, only support one. */ #define T3_MAX_RCV_RETURN_RCB_COUNT 16 @@ -195,10 +197,9 @@ static __inline void writel(unsigned int b, unsigned int addr){ /* or 2048. */ #ifndef T3_RCV_RETURN_RCB_ENTRY_COUNT #define T3_RCV_RETURN_RCB_ENTRY_COUNT 1024 -#endif /* T3_RCV_RETURN_RCB_ENTRY_COUNT */ +#endif /* T3_RCV_RETURN_RCB_ENTRY_COUNT */ #define T3_RCV_RETURN_RCB_ENTRY_COUNT_MASK (T3_RCV_RETURN_RCB_ENTRY_COUNT-1) - /* Default coalescing parameters. */ #define DEFAULT_RX_COALESCING_TICKS 100 #define MAX_RX_COALESCING_TICKS 500 @@ -227,7 +228,6 @@ static __inline void writel(unsigned int b, unsigned int addr){ #define DEFAULT_STATS_COALESCING_TICKS 1000000 #define MAX_STATS_COALESCING_TICKS 3600000000U - /* Receive BD Replenish thresholds. */ #define DEFAULT_RCV_STD_BD_REPLENISH_THRESHOLD 4 #define DEFAULT_RCV_JUMBO_BD_REPLENISH_THRESHOLD 4 @@ -240,12 +240,10 @@ static __inline void writel(unsigned int b, unsigned int addr){ /* Maximum physical fragment size. */ #define MAX_FRAGMENT_SIZE (64 * 1024) - /* Standard view. */ #define T3_STD_VIEW_SIZE (64 * 1024) #define T3_FLAT_VIEW_SIZE (32 * 1024 * 1024) - /* Buffer descriptor base address on the NIC's memory. */ #define T3_NIC_SND_BUFFER_DESC_ADDR 0x4000 @@ -265,19 +263,17 @@ static __inline void writel(unsigned int b, unsigned int addr){ #define T3_NIC_JUMBO_RCV_BUFFER_DESC_SIZE (T3_JUMBO_RCV_RCB_ENTRY_COUNT * \ sizeof(T3_EXT_RCV_BD) / 4) - /* MBUF pool. */ #define T3_NIC_MBUF_POOL_ADDR 0x8000 /* #define T3_NIC_MBUF_POOL_SIZE 0x18000 */ #define T3_NIC_MBUF_POOL_SIZE96 0x18000 #define T3_NIC_MBUF_POOL_SIZE64 0x10000 - #define T3_NIC_MBUF_POOL_ADDR_EXT_MEM 0x20000 /* DMA descriptor pool */ #define T3_NIC_DMA_DESC_POOL_ADDR 0x2000 -#define T3_NIC_DMA_DESC_POOL_SIZE 0x2000 /* 8KB. */ +#define T3_NIC_DMA_DESC_POOL_SIZE 0x2000 /* 8KB. */ #define T3_DEF_DMA_MBUF_LOW_WMARK 0x40 #define T3_DEF_RX_MAC_MBUF_LOW_WMARK 0x20 @@ -301,24 +297,21 @@ static __inline void writel(unsigned int b, unsigned int addr){ #define T3_TX_CPU_SPAD_ADDR 0x34000 #define T3_TX_CPU_SPAD_SIZE 0x4000 -typedef struct T3_DIR_ENTRY -{ - PLM_UINT8 Buffer; - LM_UINT32 Offset; - LM_UINT32 Length; -} T3_DIR_ENTRY,*PT3_DIR_ENTRY; +typedef struct T3_DIR_ENTRY { + PLM_UINT8 Buffer; + LM_UINT32 Offset; + LM_UINT32 Length; +} T3_DIR_ENTRY, *PT3_DIR_ENTRY; -typedef struct T3_FWIMG_INFO -{ - LM_UINT32 StartAddress; - T3_DIR_ENTRY Text; - T3_DIR_ENTRY ROnlyData; - T3_DIR_ENTRY Data; - T3_DIR_ENTRY Sbss; - T3_DIR_ENTRY Bss; +typedef struct T3_FWIMG_INFO { + LM_UINT32 StartAddress; + T3_DIR_ENTRY Text; + T3_DIR_ENTRY ROnlyData; + T3_DIR_ENTRY Data; + T3_DIR_ENTRY Sbss; + T3_DIR_ENTRY Bss; } T3_FWIMG_INFO, *PT3_FWIMG_INFO; - /******************************************************************************/ /* Tigon3 PCI Registers. */ /******************************************************************************/ @@ -362,7 +355,6 @@ typedef struct T3_FWIMG_INFO #define T3_ASIC_REV_5703 0x01 #define T3_ASIC_REV_5704 0x02 - /* Chip id and revision. */ #define T3_CHIP_REV(_ChipRevId) ((_ChipRevId) >> 8) #define T3_CHIP_REV_5700_AX 0x70 @@ -386,7 +378,6 @@ typedef struct T3_FWIMG_INFO #define T3_PCI_POWER_DOWN_PCI_PLL133 BIT_15 #define T3_PCI_44MHZ_CORE_CLOCK BIT_18 - #define T3_PCI_REG_ADDR_REG 0x78 #define T3_PCI_REG_DATA_REG 0x80 @@ -409,7 +400,6 @@ typedef struct T3_FWIMG_INFO #define T3_PM_PME_ENABLE BIT_8 #define T3_PM_PME_ASSERTED BIT_15 - /* PCI state register. */ #define T3_PCI_STATE_REG 0x70 @@ -419,17 +409,16 @@ typedef struct T3_FWIMG_INFO #define T3_PCI_STATE_BUS_SPEED_HIGH BIT_3 #define T3_PCI_STATE_32BIT_PCI_BUS BIT_4 - /* Broadcom subsystem/subvendor IDs. */ #define T3_SVID_BROADCOM 0x14e4 #define T3_SSID_BROADCOM_BCM95700A6 0x1644 #define T3_SSID_BROADCOM_BCM95701A5 0x0001 -#define T3_SSID_BROADCOM_BCM95700T6 0x0002 /* BCM8002 */ -#define T3_SSID_BROADCOM_BCM95700A9 0x0003 /* Agilent */ +#define T3_SSID_BROADCOM_BCM95700T6 0x0002 /* BCM8002 */ +#define T3_SSID_BROADCOM_BCM95700A9 0x0003 /* Agilent */ #define T3_SSID_BROADCOM_BCM95701T1 0x0005 #define T3_SSID_BROADCOM_BCM95701T8 0x0006 -#define T3_SSID_BROADCOM_BCM95701A7 0x0007 /* Agilent */ +#define T3_SSID_BROADCOM_BCM95701A7 0x0007 /* Agilent */ #define T3_SSID_BROADCOM_BCM95701A10 0x0008 #define T3_SSID_BROADCOM_BCM95701A12 0x8008 #define T3_SSID_BROADCOM_BCM95703Ax1 0x0009 @@ -449,7 +438,6 @@ typedef struct T3_FWIMG_INFO #define T3_SSID_3COM_3C996SX 0x1004 #define T3_SSID_3COM_3C997SX 0x1005 - /* Dell subsystem/subvendor IDs. */ #define T3_SVID_DELL 0x1028 @@ -469,7 +457,6 @@ typedef struct T3_FWIMG_INFO #define T3_SSID_COMPAQ_NC7780 0x0085 #define T3_SSID_COMPAQ_NC7780_2 0x0099 - /******************************************************************************/ /* MII registers. */ /******************************************************************************/ @@ -490,14 +477,12 @@ typedef struct T3_FWIMG_INFO #define PHY_CTRL_LOOPBACK_MODE BIT_14 #define PHY_CTRL_PHY_RESET BIT_15 - /* Status register. */ #define PHY_STATUS_REG 0x01 #define PHY_STATUS_LINK_PASS BIT_2 #define PHY_STATUS_AUTO_NEG_COMPLETE BIT_5 - /* Phy Id registers. */ #define PHY_ID1_REG 0x02 #define PHY_ID1_OUI_MASK 0xffff @@ -507,7 +492,6 @@ typedef struct T3_FWIMG_INFO #define PHY_ID2_MODEL_MASK 0x03f0 #define PHY_ID2_OUI_MASK 0xfc00 - /* Auto-negotiation advertisement register. */ #define PHY_AN_AD_REG 0x04 @@ -519,18 +503,15 @@ typedef struct T3_FWIMG_INFO #define PHY_AN_AD_100BASETX_FULL BIT_8 #define PHY_AN_AD_PROTOCOL_802_3_CSMA_CD 0x01 - /* Auto-negotiation Link Partner Ability register. */ #define PHY_LINK_PARTNER_ABILITY_REG 0x05 #define PHY_LINK_PARTNER_ASYM_PAUSE BIT_11 #define PHY_LINK_PARTNER_PAUSE_CAPABLE BIT_10 - /* Auto-negotiation expansion register. */ #define PHY_AN_EXPANSION_REG 0x06 - /******************************************************************************/ /* BCM5400 and BCM5401 phy info. */ /******************************************************************************/ @@ -557,7 +538,6 @@ typedef struct T3_FWIMG_INFO #define PHY_ID_MASK (PHY_ID_OUI_MASK | \ PHY_ID_MODEL_MASK) - #define UNKNOWN_PHY_ID(x) ((((x) & PHY_ID_MASK) != PHY_BCM5400_PHY_ID) && \ (((x) & PHY_ID_MASK) != PHY_BCM5401_PHY_ID) && \ (((x) & PHY_ID_MASK) != PHY_BCM5411_PHY_ID) && \ @@ -566,7 +546,6 @@ typedef struct T3_FWIMG_INFO (((x) & PHY_ID_MASK) != PHY_BCM5704_PHY_ID) && \ (((x) & PHY_ID_MASK) != PHY_BCM8002_PHY_ID)) - /* 1000Base-T control register. */ #define BCM540X_1000BASET_CTRL_REG 0x09 @@ -575,7 +554,6 @@ typedef struct T3_FWIMG_INFO #define BCM540X_CONFIG_AS_MASTER BIT_11 #define BCM540X_ENABLE_CONFIG_AS_MASTER BIT_12 - /* Extended control register. */ #define BCM540X_EXT_CTRL_REG 0x10 @@ -587,11 +565,9 @@ typedef struct T3_FWIMG_INFO #define BCM540X_EXT_STATUS_LINK_PASS BIT_8 - /* DSP Coefficient Read/Write Port. */ #define BCM540X_DSP_RW_PORT 0x15 - /* DSP Coeficient Address Register. */ #define BCM540X_DSP_ADDRESS_REG 0x17 @@ -631,7 +607,6 @@ typedef struct T3_FWIMG_INFO #define BCM540X_CONTROL_ALL_CHANNELS BIT_15 - /* Auxilliary Control Register (Shadow Register) */ #define BCM5401_AUX_CTRL 0x18 @@ -644,7 +619,6 @@ typedef struct T3_FWIMG_INFO #define BCM5401_SHADOW_SEL_MISC_TEST2 0x05 #define BCM5401_SHADOW_SEL_IP_PHONE_SEED 0x06 - /* Shadow register selector == '000' */ #define BCM5401_SHDW_NORMAL_DIAG_MODE BIT_3 #define BCM5401_SHDW_NORMAL_DISABLE_MBP BIT_4 @@ -664,7 +638,6 @@ typedef struct T3_FWIMG_INFO #define BCM5401_SHDW_NORMAL_EXT_PACKET_LENGTH BIT_14 #define BCM5401_SHDW_NORMAL_EXTERNAL_LOOPBACK BIT_15 - /* Auxilliary status summary. */ #define BCM540X_AUX_STATUS_REG 0x19 @@ -678,7 +651,6 @@ typedef struct T3_FWIMG_INFO #define BCM540X_AUX_100BASET_HD (BIT_9 | BIT_10) #define BCM540X_AUX_100BASET_FD (BIT_8 | BIT_9 | BIT_10) - /* Interrupt status. */ #define BCM540X_INT_STATUS_REG 0x1a @@ -687,11 +659,9 @@ typedef struct T3_FWIMG_INFO #define BCM540X_INT_DUPLEX_CHANGE BIT_3 #define BCM540X_INT_AUTO_NEG_PAGE_RX BIT_10 - /* Interrupt mask register. */ #define BCM540X_INT_MASK_REG 0x1b - /******************************************************************************/ /* Register definitions. */ /******************************************************************************/ @@ -701,9 +671,9 @@ typedef volatile LM_UINT16 T3_16BIT_REGISTER, *PT3_16BIT_REGISTER; typedef volatile LM_UINT32 T3_32BIT_REGISTER, *PT3_32BIT_REGISTER; typedef struct { - /* Big endian format. */ - T3_32BIT_REGISTER High; - T3_32BIT_REGISTER Low; + /* Big endian format. */ + T3_32BIT_REGISTER High; + T3_32BIT_REGISTER Low; } T3_64BIT_REGISTER, *PT3_64BIT_REGISTER; typedef T3_64BIT_REGISTER T3_64BIT_HOST_ADDR, *PT3_64BIT_HOST_ADDR; @@ -711,47 +681,44 @@ typedef T3_64BIT_REGISTER T3_64BIT_HOST_ADDR, *PT3_64BIT_HOST_ADDR; #define T3_NUM_OF_DMA_DESC 256 #define T3_NUM_OF_MBUF 768 -typedef struct -{ - T3_64BIT_REGISTER host_addr; - T3_32BIT_REGISTER nic_mbuf; - T3_16BIT_REGISTER len; - T3_16BIT_REGISTER cqid_sqid; - T3_32BIT_REGISTER flags; - T3_32BIT_REGISTER opaque1; - T3_32BIT_REGISTER opaque2; - T3_32BIT_REGISTER opaque3; -}T3_DMA_DESC, *PT3_DMA_DESC; - +typedef struct { + T3_64BIT_REGISTER host_addr; + T3_32BIT_REGISTER nic_mbuf; + T3_16BIT_REGISTER len; + T3_16BIT_REGISTER cqid_sqid; + T3_32BIT_REGISTER flags; + T3_32BIT_REGISTER opaque1; + T3_32BIT_REGISTER opaque2; + T3_32BIT_REGISTER opaque3; +} T3_DMA_DESC, *PT3_DMA_DESC; /******************************************************************************/ /* Ring control block. */ /******************************************************************************/ typedef struct { - T3_64BIT_REGISTER HostRingAddr; + T3_64BIT_REGISTER HostRingAddr; - union { - struct { + union { + struct { #ifdef BIG_ENDIAN_HOST - T3_16BIT_REGISTER MaxLen; - T3_16BIT_REGISTER Flags; -#else /* BIG_ENDIAN_HOST */ - T3_16BIT_REGISTER Flags; - T3_16BIT_REGISTER MaxLen; + T3_16BIT_REGISTER MaxLen; + T3_16BIT_REGISTER Flags; +#else /* BIG_ENDIAN_HOST */ + T3_16BIT_REGISTER Flags; + T3_16BIT_REGISTER MaxLen; #endif - } s; + } s; - T3_32BIT_REGISTER MaxLen_Flags; - } u; + T3_32BIT_REGISTER MaxLen_Flags; + } u; - T3_32BIT_REGISTER NicRingAddr; + T3_32BIT_REGISTER NicRingAddr; } T3_RCB, *PT3_RCB; #define T3_RCB_FLAG_USE_EXT_RECV_BD BIT_0 #define T3_RCB_FLAG_RING_DISABLED BIT_1 - /******************************************************************************/ /* Status block. */ /******************************************************************************/ @@ -763,98 +730,95 @@ typedef struct { #define T3_STATUS_BLOCK_SIZE 0x80 typedef struct { - volatile LM_UINT32 Status; - #define STATUS_BLOCK_UPDATED BIT_0 - #define STATUS_BLOCK_LINK_CHANGED_STATUS BIT_1 - #define STATUS_BLOCK_ERROR BIT_2 + volatile LM_UINT32 Status; +#define STATUS_BLOCK_UPDATED BIT_0 +#define STATUS_BLOCK_LINK_CHANGED_STATUS BIT_1 +#define STATUS_BLOCK_ERROR BIT_2 - volatile LM_UINT32 StatusTag; + volatile LM_UINT32 StatusTag; #ifdef BIG_ENDIAN_HOST - volatile LM_UINT16 RcvStdConIdx; - volatile LM_UINT16 RcvJumboConIdx; + volatile LM_UINT16 RcvStdConIdx; + volatile LM_UINT16 RcvJumboConIdx; - volatile LM_UINT16 Reserved2; - volatile LM_UINT16 RcvMiniConIdx; + volatile LM_UINT16 Reserved2; + volatile LM_UINT16 RcvMiniConIdx; - struct { - volatile LM_UINT16 SendConIdx; /* Send consumer index. */ - volatile LM_UINT16 RcvProdIdx; /* Receive producer index. */ - } Idx[16]; -#else /* BIG_ENDIAN_HOST */ - volatile LM_UINT16 RcvJumboConIdx; - volatile LM_UINT16 RcvStdConIdx; + struct { + volatile LM_UINT16 SendConIdx; /* Send consumer index. */ + volatile LM_UINT16 RcvProdIdx; /* Receive producer index. */ + } Idx[16]; +#else /* BIG_ENDIAN_HOST */ + volatile LM_UINT16 RcvJumboConIdx; + volatile LM_UINT16 RcvStdConIdx; - volatile LM_UINT16 RcvMiniConIdx; - volatile LM_UINT16 Reserved2; + volatile LM_UINT16 RcvMiniConIdx; + volatile LM_UINT16 Reserved2; - struct { - volatile LM_UINT16 RcvProdIdx; /* Receive producer index. */ - volatile LM_UINT16 SendConIdx; /* Send consumer index. */ - } Idx[16]; + struct { + volatile LM_UINT16 RcvProdIdx; /* Receive producer index. */ + volatile LM_UINT16 SendConIdx; /* Send consumer index. */ + } Idx[16]; #endif } T3_STATUS_BLOCK, *PT3_STATUS_BLOCK; - /******************************************************************************/ /* Receive buffer descriptors. */ /******************************************************************************/ typedef struct { - T3_64BIT_HOST_ADDR HostAddr; + T3_64BIT_HOST_ADDR HostAddr; #ifdef BIG_ENDIAN_HOST - volatile LM_UINT16 Index; - volatile LM_UINT16 Len; + volatile LM_UINT16 Index; + volatile LM_UINT16 Len; - volatile LM_UINT16 Type; - volatile LM_UINT16 Flags; + volatile LM_UINT16 Type; + volatile LM_UINT16 Flags; - volatile LM_UINT16 IpCksum; - volatile LM_UINT16 TcpUdpCksum; + volatile LM_UINT16 IpCksum; + volatile LM_UINT16 TcpUdpCksum; - volatile LM_UINT16 ErrorFlag; - volatile LM_UINT16 VlanTag; -#else /* BIG_ENDIAN_HOST */ - volatile LM_UINT16 Len; - volatile LM_UINT16 Index; + volatile LM_UINT16 ErrorFlag; + volatile LM_UINT16 VlanTag; +#else /* BIG_ENDIAN_HOST */ + volatile LM_UINT16 Len; + volatile LM_UINT16 Index; - volatile LM_UINT16 Flags; - volatile LM_UINT16 Type; + volatile LM_UINT16 Flags; + volatile LM_UINT16 Type; - volatile LM_UINT16 TcpUdpCksum; - volatile LM_UINT16 IpCksum; + volatile LM_UINT16 TcpUdpCksum; + volatile LM_UINT16 IpCksum; - volatile LM_UINT16 VlanTag; - volatile LM_UINT16 ErrorFlag; + volatile LM_UINT16 VlanTag; + volatile LM_UINT16 ErrorFlag; #endif - volatile LM_UINT32 Reserved; - volatile LM_UINT32 Opaque; + volatile LM_UINT32 Reserved; + volatile LM_UINT32 Opaque; } T3_RCV_BD, *PT3_RCV_BD; - typedef struct { - T3_64BIT_HOST_ADDR HostAddr[3]; + T3_64BIT_HOST_ADDR HostAddr[3]; #ifdef BIG_ENDIAN_HOST - LM_UINT16 Len1; - LM_UINT16 Len2; + LM_UINT16 Len1; + LM_UINT16 Len2; - LM_UINT16 Len3; - LM_UINT16 Reserved1; -#else /* BIG_ENDIAN_HOST */ - LM_UINT16 Len2; - LM_UINT16 Len1; + LM_UINT16 Len3; + LM_UINT16 Reserved1; +#else /* BIG_ENDIAN_HOST */ + LM_UINT16 Len2; + LM_UINT16 Len1; - LM_UINT16 Reserved1; - LM_UINT16 Len3; + LM_UINT16 Reserved1; + LM_UINT16 Len3; #endif - T3_RCV_BD StdRcvBd; + T3_RCV_BD StdRcvBd; } T3_EXT_RCV_BD, *PT3_EXT_RCV_BD; - /* Error flags. */ #define RCV_BD_ERR_BAD_CRC 0x0001 #define RCV_BD_ERR_COLL_DETECT 0x0002 @@ -866,7 +830,6 @@ typedef struct { #define RCV_BD_ERR_TRUNC_NO_RESOURCES 0x0080 #define RCV_BD_ERR_GIANT_FRAME_RCVD 0x0100 - /* Buffer descriptor flags. */ #define RCV_BD_FLAG_END 0x0004 #define RCV_BD_FLAG_JUMBO_RING 0x0020 @@ -877,44 +840,42 @@ typedef struct { #define RCV_BD_FLAG_TCP_UDP_CHKSUM_FIELD 0x2000 #define RCV_BD_FLAG_TCP_PACKET 0x4000 - /******************************************************************************/ /* Send buffer descriptor. */ /******************************************************************************/ typedef struct { - T3_64BIT_HOST_ADDR HostAddr; + T3_64BIT_HOST_ADDR HostAddr; - union { - struct { + union { + struct { #ifdef BIG_ENDIAN_HOST - LM_UINT16 Len; - LM_UINT16 Flags; -#else /* BIG_ENDIAN_HOST */ - LM_UINT16 Flags; - LM_UINT16 Len; + LM_UINT16 Len; + LM_UINT16 Flags; +#else /* BIG_ENDIAN_HOST */ + LM_UINT16 Flags; + LM_UINT16 Len; #endif - } s1; + } s1; - LM_UINT32 Len_Flags; - } u1; + LM_UINT32 Len_Flags; + } u1; - union { - struct { + union { + struct { #ifdef BIG_ENDIAN_HOST - LM_UINT16 Reserved; - LM_UINT16 VlanTag; -#else /* BIG_ENDIAN_HOST */ - LM_UINT16 VlanTag; - LM_UINT16 Reserved; + LM_UINT16 Reserved; + LM_UINT16 VlanTag; +#else /* BIG_ENDIAN_HOST */ + LM_UINT16 VlanTag; + LM_UINT16 Reserved; #endif - } s2; + } s2; - LM_UINT32 VlanTag; - } u2; + LM_UINT32 VlanTag; + } u2; } T3_SND_BD, *PT3_SND_BD; - /* Send buffer descriptor flags. */ #define SND_BD_FLAG_TCP_UDP_CKSUM 0x0001 #define SND_BD_FLAG_IP_CKSUM 0x0002 @@ -932,435 +893,426 @@ typedef struct { /* MBUFs */ typedef struct T3_MBUF_FRAME_DESC { #ifdef BIG_ENDIAN_HOST - LM_UINT32 status_control; - union { - struct { - LM_UINT8 cqid; - LM_UINT8 reserved1; - LM_UINT16 length; - }s1; - LM_UINT32 word; - }u1; - union { - struct - { - LM_UINT16 ip_hdr_start; - LM_UINT16 tcp_udp_hdr_start; - }s2; + LM_UINT32 status_control; + union { + struct { + LM_UINT8 cqid; + LM_UINT8 reserved1; + LM_UINT16 length; + } s1; + LM_UINT32 word; + } u1; + union { + struct { + LM_UINT16 ip_hdr_start; + LM_UINT16 tcp_udp_hdr_start; + } s2; - LM_UINT32 word; - }u2; + LM_UINT32 word; + } u2; - union { - struct { - LM_UINT16 data_start; - LM_UINT16 vlan_id; - }s3; + union { + struct { + LM_UINT16 data_start; + LM_UINT16 vlan_id; + } s3; - LM_UINT32 word; - }u3; + LM_UINT32 word; + } u3; - union { - struct { - LM_UINT16 ip_checksum; - LM_UINT16 tcp_udp_checksum; - }s4; + union { + struct { + LM_UINT16 ip_checksum; + LM_UINT16 tcp_udp_checksum; + } s4; - LM_UINT32 word; - }u4; + LM_UINT32 word; + } u4; - union { - struct { - LM_UINT16 pseudo_checksum; - LM_UINT16 checksum_status; - }s5; + union { + struct { + LM_UINT16 pseudo_checksum; + LM_UINT16 checksum_status; + } s5; - LM_UINT32 word; - }u5; + LM_UINT32 word; + } u5; - union { - struct { - LM_UINT16 rule_match; - LM_UINT8 class; - LM_UINT8 rupt; - }s6; + union { + struct { + LM_UINT16 rule_match; + LM_UINT8 class; + LM_UINT8 rupt; + } s6; - LM_UINT32 word; - }u6; + LM_UINT32 word; + } u6; - union { - struct { - LM_UINT16 reserved2; - LM_UINT16 mbuf_num; - }s7; + union { + struct { + LM_UINT16 reserved2; + LM_UINT16 mbuf_num; + } s7; - LM_UINT32 word; - }u7; + LM_UINT32 word; + } u7; - LM_UINT32 reserved3; - LM_UINT32 reserved4; + LM_UINT32 reserved3; + LM_UINT32 reserved4; #else - LM_UINT32 status_control; - union { - struct { - LM_UINT16 length; - LM_UINT8 reserved1; - LM_UINT8 cqid; - }s1; - LM_UINT32 word; - }u1; - union { - struct - { - LM_UINT16 tcp_udp_hdr_start; - LM_UINT16 ip_hdr_start; - }s2; + LM_UINT32 status_control; + union { + struct { + LM_UINT16 length; + LM_UINT8 reserved1; + LM_UINT8 cqid; + } s1; + LM_UINT32 word; + } u1; + union { + struct { + LM_UINT16 tcp_udp_hdr_start; + LM_UINT16 ip_hdr_start; + } s2; - LM_UINT32 word; - }u2; + LM_UINT32 word; + } u2; - union { - struct { - LM_UINT16 vlan_id; - LM_UINT16 data_start; - }s3; + union { + struct { + LM_UINT16 vlan_id; + LM_UINT16 data_start; + } s3; - LM_UINT32 word; - }u3; + LM_UINT32 word; + } u3; - union { - struct { - LM_UINT16 tcp_udp_checksum; - LM_UINT16 ip_checksum; - }s4; + union { + struct { + LM_UINT16 tcp_udp_checksum; + LM_UINT16 ip_checksum; + } s4; - LM_UINT32 word; - }u4; + LM_UINT32 word; + } u4; - union { - struct { - LM_UINT16 checksum_status; - LM_UINT16 pseudo_checksum; - }s5; + union { + struct { + LM_UINT16 checksum_status; + LM_UINT16 pseudo_checksum; + } s5; - LM_UINT32 word; - }u5; + LM_UINT32 word; + } u5; - union { - struct { - LM_UINT8 rupt; - LM_UINT8 class; - LM_UINT16 rule_match; - }s6; + union { + struct { + LM_UINT8 rupt; + LM_UINT8 class; + LM_UINT16 rule_match; + } s6; - LM_UINT32 word; - }u6; + LM_UINT32 word; + } u6; - union { - struct { - LM_UINT16 mbuf_num; - LM_UINT16 reserved2; - }s7; + union { + struct { + LM_UINT16 mbuf_num; + LM_UINT16 reserved2; + } s7; - LM_UINT32 word; - }u7; + LM_UINT32 word; + } u7; - LM_UINT32 reserved3; - LM_UINT32 reserved4; + LM_UINT32 reserved3; + LM_UINT32 reserved4; #endif -}T3_MBUF_FRAME_DESC,*PT3_MBUF_FRAME_DESC; +} T3_MBUF_FRAME_DESC, *PT3_MBUF_FRAME_DESC; typedef struct T3_MBUF_HDR { - union { - struct { - unsigned int C:1; - unsigned int F:1; - unsigned int reserved1:7; - unsigned int next_mbuf:16; - unsigned int length:7; - }s1; + union { + struct { + unsigned int C:1; + unsigned int F:1; + unsigned int reserved1:7; + unsigned int next_mbuf:16; + unsigned int length:7; + } s1; - LM_UINT32 word; - }u1; + LM_UINT32 word; + } u1; - LM_UINT32 next_frame_ptr; -}T3_MBUF_HDR, *PT3_MBUF_HDR; + LM_UINT32 next_frame_ptr; +} T3_MBUF_HDR, *PT3_MBUF_HDR; -typedef struct T3_MBUF -{ - T3_MBUF_HDR hdr; - union - { - struct { - T3_MBUF_FRAME_DESC frame_hdr; - LM_UINT32 data[20]; - }s1; +typedef struct T3_MBUF { + T3_MBUF_HDR hdr; + union { + struct { + T3_MBUF_FRAME_DESC frame_hdr; + LM_UINT32 data[20]; + } s1; - struct { - LM_UINT32 data[30]; - }s2; - }body; -}T3_MBUF, *PT3_MBUF; + struct { + LM_UINT32 data[30]; + } s2; + } body; +} T3_MBUF, *PT3_MBUF; #define T3_MBUF_BASE (T3_NIC_MBUF_POOL_ADDR >> 7) #define T3_MBUF_END ((T3_NIC_MBUF_POOL_ADDR + T3_NIC_MBUF_POOL_SIZE) >> 7) - /******************************************************************************/ /* Statistics block. */ /******************************************************************************/ typedef struct { - LM_UINT8 Reserved0[0x400-0x300]; + LM_UINT8 Reserved0[0x400 - 0x300]; - /* Statistics maintained by Receive MAC. */ - T3_64BIT_REGISTER ifHCInOctets; - T3_64BIT_REGISTER Reserved1; - T3_64BIT_REGISTER etherStatsFragments; - T3_64BIT_REGISTER ifHCInUcastPkts; - T3_64BIT_REGISTER ifHCInMulticastPkts; - T3_64BIT_REGISTER ifHCInBroadcastPkts; - T3_64BIT_REGISTER dot3StatsFCSErrors; - T3_64BIT_REGISTER dot3StatsAlignmentErrors; - T3_64BIT_REGISTER xonPauseFramesReceived; - T3_64BIT_REGISTER xoffPauseFramesReceived; - T3_64BIT_REGISTER macControlFramesReceived; - T3_64BIT_REGISTER xoffStateEntered; - T3_64BIT_REGISTER dot3StatsFramesTooLong; - T3_64BIT_REGISTER etherStatsJabbers; - T3_64BIT_REGISTER etherStatsUndersizePkts; - T3_64BIT_REGISTER inRangeLengthError; - T3_64BIT_REGISTER outRangeLengthError; - T3_64BIT_REGISTER etherStatsPkts64Octets; - T3_64BIT_REGISTER etherStatsPkts65Octetsto127Octets; - T3_64BIT_REGISTER etherStatsPkts128Octetsto255Octets; - T3_64BIT_REGISTER etherStatsPkts256Octetsto511Octets; - T3_64BIT_REGISTER etherStatsPkts512Octetsto1023Octets; - T3_64BIT_REGISTER etherStatsPkts1024Octetsto1522Octets; - T3_64BIT_REGISTER etherStatsPkts1523Octetsto2047Octets; - T3_64BIT_REGISTER etherStatsPkts2048Octetsto4095Octets; - T3_64BIT_REGISTER etherStatsPkts4096Octetsto8191Octets; - T3_64BIT_REGISTER etherStatsPkts8192Octetsto9022Octets; + /* Statistics maintained by Receive MAC. */ + T3_64BIT_REGISTER ifHCInOctets; + T3_64BIT_REGISTER Reserved1; + T3_64BIT_REGISTER etherStatsFragments; + T3_64BIT_REGISTER ifHCInUcastPkts; + T3_64BIT_REGISTER ifHCInMulticastPkts; + T3_64BIT_REGISTER ifHCInBroadcastPkts; + T3_64BIT_REGISTER dot3StatsFCSErrors; + T3_64BIT_REGISTER dot3StatsAlignmentErrors; + T3_64BIT_REGISTER xonPauseFramesReceived; + T3_64BIT_REGISTER xoffPauseFramesReceived; + T3_64BIT_REGISTER macControlFramesReceived; + T3_64BIT_REGISTER xoffStateEntered; + T3_64BIT_REGISTER dot3StatsFramesTooLong; + T3_64BIT_REGISTER etherStatsJabbers; + T3_64BIT_REGISTER etherStatsUndersizePkts; + T3_64BIT_REGISTER inRangeLengthError; + T3_64BIT_REGISTER outRangeLengthError; + T3_64BIT_REGISTER etherStatsPkts64Octets; + T3_64BIT_REGISTER etherStatsPkts65Octetsto127Octets; + T3_64BIT_REGISTER etherStatsPkts128Octetsto255Octets; + T3_64BIT_REGISTER etherStatsPkts256Octetsto511Octets; + T3_64BIT_REGISTER etherStatsPkts512Octetsto1023Octets; + T3_64BIT_REGISTER etherStatsPkts1024Octetsto1522Octets; + T3_64BIT_REGISTER etherStatsPkts1523Octetsto2047Octets; + T3_64BIT_REGISTER etherStatsPkts2048Octetsto4095Octets; + T3_64BIT_REGISTER etherStatsPkts4096Octetsto8191Octets; + T3_64BIT_REGISTER etherStatsPkts8192Octetsto9022Octets; - T3_64BIT_REGISTER Unused1[37]; + T3_64BIT_REGISTER Unused1[37]; - /* Statistics maintained by Transmit MAC. */ - T3_64BIT_REGISTER ifHCOutOctets; - T3_64BIT_REGISTER Reserved2; - T3_64BIT_REGISTER etherStatsCollisions; - T3_64BIT_REGISTER outXonSent; - T3_64BIT_REGISTER outXoffSent; - T3_64BIT_REGISTER flowControlDone; - T3_64BIT_REGISTER dot3StatsInternalMacTransmitErrors; - T3_64BIT_REGISTER dot3StatsSingleCollisionFrames; - T3_64BIT_REGISTER dot3StatsMultipleCollisionFrames; - T3_64BIT_REGISTER dot3StatsDeferredTransmissions; - T3_64BIT_REGISTER Reserved3; - T3_64BIT_REGISTER dot3StatsExcessiveCollisions; - T3_64BIT_REGISTER dot3StatsLateCollisions; - T3_64BIT_REGISTER dot3Collided2Times; - T3_64BIT_REGISTER dot3Collided3Times; - T3_64BIT_REGISTER dot3Collided4Times; - T3_64BIT_REGISTER dot3Collided5Times; - T3_64BIT_REGISTER dot3Collided6Times; - T3_64BIT_REGISTER dot3Collided7Times; - T3_64BIT_REGISTER dot3Collided8Times; - T3_64BIT_REGISTER dot3Collided9Times; - T3_64BIT_REGISTER dot3Collided10Times; - T3_64BIT_REGISTER dot3Collided11Times; - T3_64BIT_REGISTER dot3Collided12Times; - T3_64BIT_REGISTER dot3Collided13Times; - T3_64BIT_REGISTER dot3Collided14Times; - T3_64BIT_REGISTER dot3Collided15Times; - T3_64BIT_REGISTER ifHCOutUcastPkts; - T3_64BIT_REGISTER ifHCOutMulticastPkts; - T3_64BIT_REGISTER ifHCOutBroadcastPkts; - T3_64BIT_REGISTER dot3StatsCarrierSenseErrors; - T3_64BIT_REGISTER ifOutDiscards; - T3_64BIT_REGISTER ifOutErrors; + /* Statistics maintained by Transmit MAC. */ + T3_64BIT_REGISTER ifHCOutOctets; + T3_64BIT_REGISTER Reserved2; + T3_64BIT_REGISTER etherStatsCollisions; + T3_64BIT_REGISTER outXonSent; + T3_64BIT_REGISTER outXoffSent; + T3_64BIT_REGISTER flowControlDone; + T3_64BIT_REGISTER dot3StatsInternalMacTransmitErrors; + T3_64BIT_REGISTER dot3StatsSingleCollisionFrames; + T3_64BIT_REGISTER dot3StatsMultipleCollisionFrames; + T3_64BIT_REGISTER dot3StatsDeferredTransmissions; + T3_64BIT_REGISTER Reserved3; + T3_64BIT_REGISTER dot3StatsExcessiveCollisions; + T3_64BIT_REGISTER dot3StatsLateCollisions; + T3_64BIT_REGISTER dot3Collided2Times; + T3_64BIT_REGISTER dot3Collided3Times; + T3_64BIT_REGISTER dot3Collided4Times; + T3_64BIT_REGISTER dot3Collided5Times; + T3_64BIT_REGISTER dot3Collided6Times; + T3_64BIT_REGISTER dot3Collided7Times; + T3_64BIT_REGISTER dot3Collided8Times; + T3_64BIT_REGISTER dot3Collided9Times; + T3_64BIT_REGISTER dot3Collided10Times; + T3_64BIT_REGISTER dot3Collided11Times; + T3_64BIT_REGISTER dot3Collided12Times; + T3_64BIT_REGISTER dot3Collided13Times; + T3_64BIT_REGISTER dot3Collided14Times; + T3_64BIT_REGISTER dot3Collided15Times; + T3_64BIT_REGISTER ifHCOutUcastPkts; + T3_64BIT_REGISTER ifHCOutMulticastPkts; + T3_64BIT_REGISTER ifHCOutBroadcastPkts; + T3_64BIT_REGISTER dot3StatsCarrierSenseErrors; + T3_64BIT_REGISTER ifOutDiscards; + T3_64BIT_REGISTER ifOutErrors; - T3_64BIT_REGISTER Unused2[31]; + T3_64BIT_REGISTER Unused2[31]; - /* Statistics maintained by Receive List Placement. */ - T3_64BIT_REGISTER COSIfHCInPkts[16]; - T3_64BIT_REGISTER COSFramesDroppedDueToFilters; - T3_64BIT_REGISTER nicDmaWriteQueueFull; - T3_64BIT_REGISTER nicDmaWriteHighPriQueueFull; - T3_64BIT_REGISTER nicNoMoreRxBDs; - T3_64BIT_REGISTER ifInDiscards; - T3_64BIT_REGISTER ifInErrors; - T3_64BIT_REGISTER nicRecvThresholdHit; + /* Statistics maintained by Receive List Placement. */ + T3_64BIT_REGISTER COSIfHCInPkts[16]; + T3_64BIT_REGISTER COSFramesDroppedDueToFilters; + T3_64BIT_REGISTER nicDmaWriteQueueFull; + T3_64BIT_REGISTER nicDmaWriteHighPriQueueFull; + T3_64BIT_REGISTER nicNoMoreRxBDs; + T3_64BIT_REGISTER ifInDiscards; + T3_64BIT_REGISTER ifInErrors; + T3_64BIT_REGISTER nicRecvThresholdHit; - T3_64BIT_REGISTER Unused3[9]; + T3_64BIT_REGISTER Unused3[9]; - /* Statistics maintained by Send Data Initiator. */ - T3_64BIT_REGISTER COSIfHCOutPkts[16]; - T3_64BIT_REGISTER nicDmaReadQueueFull; - T3_64BIT_REGISTER nicDmaReadHighPriQueueFull; - T3_64BIT_REGISTER nicSendDataCompQueueFull; + /* Statistics maintained by Send Data Initiator. */ + T3_64BIT_REGISTER COSIfHCOutPkts[16]; + T3_64BIT_REGISTER nicDmaReadQueueFull; + T3_64BIT_REGISTER nicDmaReadHighPriQueueFull; + T3_64BIT_REGISTER nicSendDataCompQueueFull; - /* Statistics maintained by Host Coalescing. */ - T3_64BIT_REGISTER nicRingSetSendProdIndex; - T3_64BIT_REGISTER nicRingStatusUpdate; - T3_64BIT_REGISTER nicInterrupts; - T3_64BIT_REGISTER nicAvoidedInterrupts; - T3_64BIT_REGISTER nicSendThresholdHit; + /* Statistics maintained by Host Coalescing. */ + T3_64BIT_REGISTER nicRingSetSendProdIndex; + T3_64BIT_REGISTER nicRingStatusUpdate; + T3_64BIT_REGISTER nicInterrupts; + T3_64BIT_REGISTER nicAvoidedInterrupts; + T3_64BIT_REGISTER nicSendThresholdHit; - LM_UINT8 Reserved4[0xb00-0x9c0]; + LM_UINT8 Reserved4[0xb00 - 0x9c0]; } T3_STATS_BLOCK, *PT3_STATS_BLOCK; - /******************************************************************************/ /* PCI configuration registers. */ /******************************************************************************/ typedef struct { - T3_16BIT_REGISTER VendorId; - T3_16BIT_REGISTER DeviceId; + T3_16BIT_REGISTER VendorId; + T3_16BIT_REGISTER DeviceId; - T3_16BIT_REGISTER Command; - T3_16BIT_REGISTER Status; + T3_16BIT_REGISTER Command; + T3_16BIT_REGISTER Status; - T3_32BIT_REGISTER ClassCodeRevId; + T3_32BIT_REGISTER ClassCodeRevId; - T3_8BIT_REGISTER CacheLineSize; - T3_8BIT_REGISTER LatencyTimer; - T3_8BIT_REGISTER HeaderType; - T3_8BIT_REGISTER Bist; + T3_8BIT_REGISTER CacheLineSize; + T3_8BIT_REGISTER LatencyTimer; + T3_8BIT_REGISTER HeaderType; + T3_8BIT_REGISTER Bist; - T3_32BIT_REGISTER MemBaseAddrLow; - T3_32BIT_REGISTER MemBaseAddrHigh; + T3_32BIT_REGISTER MemBaseAddrLow; + T3_32BIT_REGISTER MemBaseAddrHigh; - LM_UINT8 Unused1[20]; + LM_UINT8 Unused1[20]; - T3_16BIT_REGISTER SubsystemVendorId; - T3_16BIT_REGISTER SubsystemId; + T3_16BIT_REGISTER SubsystemVendorId; + T3_16BIT_REGISTER SubsystemId; - T3_32BIT_REGISTER RomBaseAddr; + T3_32BIT_REGISTER RomBaseAddr; - T3_8BIT_REGISTER PciXCapiblityPtr; - LM_UINT8 Unused2[7]; + T3_8BIT_REGISTER PciXCapiblityPtr; + LM_UINT8 Unused2[7]; - T3_8BIT_REGISTER IntLine; - T3_8BIT_REGISTER IntPin; - T3_8BIT_REGISTER MinGnt; - T3_8BIT_REGISTER MaxLat; + T3_8BIT_REGISTER IntLine; + T3_8BIT_REGISTER IntPin; + T3_8BIT_REGISTER MinGnt; + T3_8BIT_REGISTER MaxLat; - T3_8BIT_REGISTER PciXCapabilities; - T3_8BIT_REGISTER PmCapabilityPtr; - T3_16BIT_REGISTER PciXCommand; + T3_8BIT_REGISTER PciXCapabilities; + T3_8BIT_REGISTER PmCapabilityPtr; + T3_16BIT_REGISTER PciXCommand; - T3_32BIT_REGISTER PciXStatus; + T3_32BIT_REGISTER PciXStatus; - T3_8BIT_REGISTER PmCapabilityId; - T3_8BIT_REGISTER VpdCapabilityPtr; - T3_16BIT_REGISTER PmCapabilities; + T3_8BIT_REGISTER PmCapabilityId; + T3_8BIT_REGISTER VpdCapabilityPtr; + T3_16BIT_REGISTER PmCapabilities; - T3_16BIT_REGISTER PmCtrlStatus; - #define PM_CTRL_PME_STATUS BIT_15 - #define PM_CTRL_PME_ENABLE BIT_8 - #define PM_CTRL_PME_POWER_STATE_D0 0 - #define PM_CTRL_PME_POWER_STATE_D1 1 - #define PM_CTRL_PME_POWER_STATE_D2 2 - #define PM_CTRL_PME_POWER_STATE_D3H 3 + T3_16BIT_REGISTER PmCtrlStatus; +#define PM_CTRL_PME_STATUS BIT_15 +#define PM_CTRL_PME_ENABLE BIT_8 +#define PM_CTRL_PME_POWER_STATE_D0 0 +#define PM_CTRL_PME_POWER_STATE_D1 1 +#define PM_CTRL_PME_POWER_STATE_D2 2 +#define PM_CTRL_PME_POWER_STATE_D3H 3 - T3_8BIT_REGISTER BridgeSupportExt; - T3_8BIT_REGISTER PmData; + T3_8BIT_REGISTER BridgeSupportExt; + T3_8BIT_REGISTER PmData; - T3_8BIT_REGISTER VpdCapabilityId; - T3_8BIT_REGISTER MsiCapabilityPtr; - T3_16BIT_REGISTER VpdAddrFlag; - #define VPD_FLAG_WRITE (1 << 15) - #define VPD_FLAG_RW_MASK (1 << 15) - #define VPD_FLAG_READ 0 + T3_8BIT_REGISTER VpdCapabilityId; + T3_8BIT_REGISTER MsiCapabilityPtr; + T3_16BIT_REGISTER VpdAddrFlag; +#define VPD_FLAG_WRITE (1 << 15) +#define VPD_FLAG_RW_MASK (1 << 15) +#define VPD_FLAG_READ 0 + T3_32BIT_REGISTER VpdData; - T3_32BIT_REGISTER VpdData; + T3_8BIT_REGISTER MsiCapabilityId; + T3_8BIT_REGISTER NextCapabilityPtr; + T3_16BIT_REGISTER MsiCtrl; +#define MSI_CTRL_64BIT_CAP (1 << 7) +#define MSI_CTRL_MSG_ENABLE(x) (x << 4) +#define MSI_CTRL_MSG_CAP(x) (x << 1) +#define MSI_CTRL_ENABLE (1 << 0) - T3_8BIT_REGISTER MsiCapabilityId; - T3_8BIT_REGISTER NextCapabilityPtr; - T3_16BIT_REGISTER MsiCtrl; - #define MSI_CTRL_64BIT_CAP (1 << 7) - #define MSI_CTRL_MSG_ENABLE(x) (x << 4) - #define MSI_CTRL_MSG_CAP(x) (x << 1) - #define MSI_CTRL_ENABLE (1 << 0) + T3_32BIT_REGISTER MsiAddrLow; + T3_32BIT_REGISTER MsiAddrHigh; + T3_16BIT_REGISTER MsiData; + T3_16BIT_REGISTER Unused3; - T3_32BIT_REGISTER MsiAddrLow; - T3_32BIT_REGISTER MsiAddrHigh; + T3_32BIT_REGISTER MiscHostCtrl; +#define MISC_HOST_CTRL_CLEAR_INT BIT_0 +#define MISC_HOST_CTRL_MASK_PCI_INT BIT_1 +#define MISC_HOST_CTRL_ENABLE_ENDIAN_BYTE_SWAP BIT_2 +#define MISC_HOST_CTRL_ENABLE_ENDIAN_WORD_SWAP BIT_3 +#define MISC_HOST_CTRL_ENABLE_PCI_STATE_REG_RW BIT_4 +#define MISC_HOST_CTRL_ENABLE_CLK_REG_RW BIT_5 +#define MISC_HOST_CTRL_ENABLE_REG_WORD_SWAP BIT_6 +#define MISC_HOST_CTRL_ENABLE_INDIRECT_ACCESS BIT_7 +#define MISC_HOST_CTRL_ENABLE_INT_MASK_MODE BIT_8 +#define MISC_HOST_CTRL_ENABLE_TAGGED_STATUS_MODE BIT_9 - T3_16BIT_REGISTER MsiData; - T3_16BIT_REGISTER Unused3; + T3_32BIT_REGISTER DmaReadWriteCtrl; +#define DMA_CTRL_WRITE_BOUNDARY_MASK (BIT_11 | BIT_12 | BIT_13) +#define DMA_CTRL_WRITE_BOUNDARY_DISABLE 0 +#define DMA_CTRL_WRITE_BOUNDARY_16 BIT_11 +#define DMA_CTRL_WRITE_BOUNDARY_32 BIT_12 +#define DMA_CTRL_WRITE_BOUNDARY_64 (BIT_12 | BIT_11) +#define DMA_CTRL_WRITE_BOUNDARY_128 BIT_13 +#define DMA_CTRL_WRITE_BOUNDARY_256 (BIT_13 | BIT_11) +#define DMA_CTRL_WRITE_BOUNDARY_512 (BIT_13 | BIT_12) +#define DMA_CTRL_WRITE_BOUNDARY_1024 (BIT_13 | BIT_12 | BIT_11) +#define DMA_CTRL_WRITE_ONE_DMA_AT_ONCE BIT_14 - T3_32BIT_REGISTER MiscHostCtrl; - #define MISC_HOST_CTRL_CLEAR_INT BIT_0 - #define MISC_HOST_CTRL_MASK_PCI_INT BIT_1 - #define MISC_HOST_CTRL_ENABLE_ENDIAN_BYTE_SWAP BIT_2 - #define MISC_HOST_CTRL_ENABLE_ENDIAN_WORD_SWAP BIT_3 - #define MISC_HOST_CTRL_ENABLE_PCI_STATE_REG_RW BIT_4 - #define MISC_HOST_CTRL_ENABLE_CLK_REG_RW BIT_5 - #define MISC_HOST_CTRL_ENABLE_REG_WORD_SWAP BIT_6 - #define MISC_HOST_CTRL_ENABLE_INDIRECT_ACCESS BIT_7 - #define MISC_HOST_CTRL_ENABLE_INT_MASK_MODE BIT_8 - #define MISC_HOST_CTRL_ENABLE_TAGGED_STATUS_MODE BIT_9 + T3_32BIT_REGISTER PciState; +#define T3_PCI_STATE_FORCE_PCI_RESET BIT_0 +#define T3_PCI_STATE_INTERRUPT_NOT_ACTIVE BIT_1 +#define T3_PCI_STATE_NOT_PCI_X_BUS BIT_2 +#define T3_PCI_STATE_HIGH_BUS_SPEED BIT_3 +#define T3_PCI_STATE_32BIT_PCI_BUS BIT_4 +#define T3_PCI_STATE_PCI_ROM_ENABLE BIT_5 +#define T3_PCI_STATE_PCI_ROM_RETRY_ENABLE BIT_6 +#define T3_PCI_STATE_FLAT_VIEW BIT_8 +#define T3_PCI_STATE_RETRY_SAME_DMA BIT_13 - T3_32BIT_REGISTER DmaReadWriteCtrl; - #define DMA_CTRL_WRITE_BOUNDARY_MASK (BIT_11 | BIT_12 | BIT_13) - #define DMA_CTRL_WRITE_BOUNDARY_DISABLE 0 - #define DMA_CTRL_WRITE_BOUNDARY_16 BIT_11 - #define DMA_CTRL_WRITE_BOUNDARY_32 BIT_12 - #define DMA_CTRL_WRITE_BOUNDARY_64 (BIT_12 | BIT_11) - #define DMA_CTRL_WRITE_BOUNDARY_128 BIT_13 - #define DMA_CTRL_WRITE_BOUNDARY_256 (BIT_13 | BIT_11) - #define DMA_CTRL_WRITE_BOUNDARY_512 (BIT_13 | BIT_12) - #define DMA_CTRL_WRITE_BOUNDARY_1024 (BIT_13 | BIT_12 | BIT_11) - #define DMA_CTRL_WRITE_ONE_DMA_AT_ONCE BIT_14 + T3_32BIT_REGISTER ClockCtrl; +#define T3_PCI_CLKCTRL_TXCPU_CLK_DISABLE BIT_11 +#define T3_PCI_CLKCTRL_RXCPU_CLK_DISABLE BIT_10 +#define T3_PCI_CLKCTRL_CORE_CLK_DISABLE BIT_9 + T3_32BIT_REGISTER RegBaseAddr; - T3_32BIT_REGISTER PciState; - #define T3_PCI_STATE_FORCE_PCI_RESET BIT_0 - #define T3_PCI_STATE_INTERRUPT_NOT_ACTIVE BIT_1 - #define T3_PCI_STATE_NOT_PCI_X_BUS BIT_2 - #define T3_PCI_STATE_HIGH_BUS_SPEED BIT_3 - #define T3_PCI_STATE_32BIT_PCI_BUS BIT_4 - #define T3_PCI_STATE_PCI_ROM_ENABLE BIT_5 - #define T3_PCI_STATE_PCI_ROM_RETRY_ENABLE BIT_6 - #define T3_PCI_STATE_FLAT_VIEW BIT_8 - #define T3_PCI_STATE_RETRY_SAME_DMA BIT_13 - - T3_32BIT_REGISTER ClockCtrl; - #define T3_PCI_CLKCTRL_TXCPU_CLK_DISABLE BIT_11 - #define T3_PCI_CLKCTRL_RXCPU_CLK_DISABLE BIT_10 - #define T3_PCI_CLKCTRL_CORE_CLK_DISABLE BIT_9 - - T3_32BIT_REGISTER RegBaseAddr; - - T3_32BIT_REGISTER MemWindowBaseAddr; + T3_32BIT_REGISTER MemWindowBaseAddr; #ifdef NIC_CPU_VIEW - /* These registers are ONLY visible to NIC CPU */ - T3_32BIT_REGISTER PowerConsumed; - T3_32BIT_REGISTER PowerDissipated; -#else /* NIC_CPU_VIEW */ - T3_32BIT_REGISTER RegData; - T3_32BIT_REGISTER MemWindowData; -#endif /* !NIC_CPU_VIEW */ + /* These registers are ONLY visible to NIC CPU */ + T3_32BIT_REGISTER PowerConsumed; + T3_32BIT_REGISTER PowerDissipated; +#else /* NIC_CPU_VIEW */ + T3_32BIT_REGISTER RegData; + T3_32BIT_REGISTER MemWindowData; +#endif /* !NIC_CPU_VIEW */ - T3_32BIT_REGISTER ModeCtrl; + T3_32BIT_REGISTER ModeCtrl; - T3_32BIT_REGISTER MiscCfg; + T3_32BIT_REGISTER MiscCfg; - T3_32BIT_REGISTER MiscLocalCtrl; + T3_32BIT_REGISTER MiscLocalCtrl; - T3_32BIT_REGISTER Unused4; + T3_32BIT_REGISTER Unused4; - /* NOTE: Big/Little-endian clarification needed. Are these register */ - /* in big or little endian formate. */ - T3_64BIT_REGISTER StdRingProdIdx; - T3_64BIT_REGISTER RcvRetRingConIdx; - T3_64BIT_REGISTER SndProdIdx; + /* NOTE: Big/Little-endian clarification needed. Are these register */ + /* in big or little endian formate. */ + T3_64BIT_REGISTER StdRingProdIdx; + T3_64BIT_REGISTER RcvRetRingConIdx; + T3_64BIT_REGISTER SndProdIdx; - LM_UINT8 Unused5[80]; + LM_UINT8 Unused5[80]; } T3_PCI_CONFIGURATION, *PT3_PCI_CONFIGURATION; #define PCIX_CMD_MAX_SPLIT_MASK 0x0070 @@ -1374,1382 +1326,1347 @@ typedef struct { /******************************************************************************/ typedef struct { - /* MAC mode control. */ - T3_32BIT_REGISTER Mode; - #define MAC_MODE_GLOBAL_RESET BIT_0 - #define MAC_MODE_HALF_DUPLEX BIT_1 - #define MAC_MODE_PORT_MODE_MASK (BIT_2 | BIT_3) - #define MAC_MODE_PORT_MODE_TBI (BIT_2 | BIT_3) - #define MAC_MODE_PORT_MODE_GMII BIT_3 - #define MAC_MODE_PORT_MODE_MII BIT_2 - #define MAC_MODE_PORT_MODE_NONE BIT_NONE - #define MAC_MODE_PORT_INTERNAL_LOOPBACK BIT_4 - #define MAC_MODE_TAGGED_MAC_CONTROL BIT_7 - #define MAC_MODE_TX_BURSTING BIT_8 - #define MAC_MODE_MAX_DEFER BIT_9 - #define MAC_MODE_LINK_POLARITY BIT_10 - #define MAC_MODE_ENABLE_RX_STATISTICS BIT_11 - #define MAC_MODE_CLEAR_RX_STATISTICS BIT_12 - #define MAC_MODE_FLUSH_RX_STATISTICS BIT_13 - #define MAC_MODE_ENABLE_TX_STATISTICS BIT_14 - #define MAC_MODE_CLEAR_TX_STATISTICS BIT_15 - #define MAC_MODE_FLUSH_TX_STATISTICS BIT_16 - #define MAC_MODE_SEND_CONFIGS BIT_17 - #define MAC_MODE_DETECT_MAGIC_PACKET_ENABLE BIT_18 - #define MAC_MODE_ACPI_POWER_ON_ENABLE BIT_19 - #define MAC_MODE_ENABLE_MIP BIT_20 - #define MAC_MODE_ENABLE_TDE BIT_21 - #define MAC_MODE_ENABLE_RDE BIT_22 - #define MAC_MODE_ENABLE_FHDE BIT_23 + /* MAC mode control. */ + T3_32BIT_REGISTER Mode; +#define MAC_MODE_GLOBAL_RESET BIT_0 +#define MAC_MODE_HALF_DUPLEX BIT_1 +#define MAC_MODE_PORT_MODE_MASK (BIT_2 | BIT_3) +#define MAC_MODE_PORT_MODE_TBI (BIT_2 | BIT_3) +#define MAC_MODE_PORT_MODE_GMII BIT_3 +#define MAC_MODE_PORT_MODE_MII BIT_2 +#define MAC_MODE_PORT_MODE_NONE BIT_NONE +#define MAC_MODE_PORT_INTERNAL_LOOPBACK BIT_4 +#define MAC_MODE_TAGGED_MAC_CONTROL BIT_7 +#define MAC_MODE_TX_BURSTING BIT_8 +#define MAC_MODE_MAX_DEFER BIT_9 +#define MAC_MODE_LINK_POLARITY BIT_10 +#define MAC_MODE_ENABLE_RX_STATISTICS BIT_11 +#define MAC_MODE_CLEAR_RX_STATISTICS BIT_12 +#define MAC_MODE_FLUSH_RX_STATISTICS BIT_13 +#define MAC_MODE_ENABLE_TX_STATISTICS BIT_14 +#define MAC_MODE_CLEAR_TX_STATISTICS BIT_15 +#define MAC_MODE_FLUSH_TX_STATISTICS BIT_16 +#define MAC_MODE_SEND_CONFIGS BIT_17 +#define MAC_MODE_DETECT_MAGIC_PACKET_ENABLE BIT_18 +#define MAC_MODE_ACPI_POWER_ON_ENABLE BIT_19 +#define MAC_MODE_ENABLE_MIP BIT_20 +#define MAC_MODE_ENABLE_TDE BIT_21 +#define MAC_MODE_ENABLE_RDE BIT_22 +#define MAC_MODE_ENABLE_FHDE BIT_23 - /* MAC status */ - T3_32BIT_REGISTER Status; - #define MAC_STATUS_PCS_SYNCED BIT_0 - #define MAC_STATUS_SIGNAL_DETECTED BIT_1 - #define MAC_STATUS_RECEIVING_CFG BIT_2 - #define MAC_STATUS_CFG_CHANGED BIT_3 - #define MAC_STATUS_SYNC_CHANGED BIT_4 - #define MAC_STATUS_PORT_DECODE_ERROR BIT_10 - #define MAC_STATUS_LINK_STATE_CHANGED BIT_12 - #define MAC_STATUS_MI_COMPLETION BIT_22 - #define MAC_STATUS_MI_INTERRUPT BIT_23 - #define MAC_STATUS_AP_ERROR BIT_24 - #define MAC_STATUS_ODI_ERROR BIT_25 - #define MAC_STATUS_RX_STATS_OVERRUN BIT_26 - #define MAC_STATUS_TX_STATS_OVERRUN BIT_27 + /* MAC status */ + T3_32BIT_REGISTER Status; +#define MAC_STATUS_PCS_SYNCED BIT_0 +#define MAC_STATUS_SIGNAL_DETECTED BIT_1 +#define MAC_STATUS_RECEIVING_CFG BIT_2 +#define MAC_STATUS_CFG_CHANGED BIT_3 +#define MAC_STATUS_SYNC_CHANGED BIT_4 +#define MAC_STATUS_PORT_DECODE_ERROR BIT_10 +#define MAC_STATUS_LINK_STATE_CHANGED BIT_12 +#define MAC_STATUS_MI_COMPLETION BIT_22 +#define MAC_STATUS_MI_INTERRUPT BIT_23 +#define MAC_STATUS_AP_ERROR BIT_24 +#define MAC_STATUS_ODI_ERROR BIT_25 +#define MAC_STATUS_RX_STATS_OVERRUN BIT_26 +#define MAC_STATUS_TX_STATS_OVERRUN BIT_27 - /* Event Enable */ - T3_32BIT_REGISTER MacEvent; - #define MAC_EVENT_ENABLE_PORT_DECODE_ERR BIT_10 - #define MAC_EVENT_ENABLE_LINK_STATE_CHANGED_ATTN BIT_12 - #define MAC_EVENT_ENABLE_MI_COMPLETION BIT_22 - #define MAC_EVENT_ENABLE_MI_INTERRUPT BIT_23 - #define MAC_EVENT_ENABLE_AP_ERROR BIT_24 - #define MAC_EVENT_ENABLE_ODI_ERROR BIT_25 - #define MAC_EVENT_ENABLE_RX_STATS_OVERRUN BIT_26 - #define MAC_EVENT_ENABLE_TX_STATS_OVERRUN BIT_27 + /* Event Enable */ + T3_32BIT_REGISTER MacEvent; +#define MAC_EVENT_ENABLE_PORT_DECODE_ERR BIT_10 +#define MAC_EVENT_ENABLE_LINK_STATE_CHANGED_ATTN BIT_12 +#define MAC_EVENT_ENABLE_MI_COMPLETION BIT_22 +#define MAC_EVENT_ENABLE_MI_INTERRUPT BIT_23 +#define MAC_EVENT_ENABLE_AP_ERROR BIT_24 +#define MAC_EVENT_ENABLE_ODI_ERROR BIT_25 +#define MAC_EVENT_ENABLE_RX_STATS_OVERRUN BIT_26 +#define MAC_EVENT_ENABLE_TX_STATS_OVERRUN BIT_27 - /* Led control. */ - T3_32BIT_REGISTER LedCtrl; - #define LED_CTRL_OVERRIDE_LINK_LED BIT_0 - #define LED_CTRL_1000MBPS_LED_ON BIT_1 - #define LED_CTRL_100MBPS_LED_ON BIT_2 - #define LED_CTRL_10MBPS_LED_ON BIT_3 - #define LED_CTRL_OVERRIDE_TRAFFIC_LED BIT_4 - #define LED_CTRL_BLINK_TRAFFIC_LED BIT_5 - #define LED_CTRL_TRAFFIC_LED BIT_6 - #define LED_CTRL_1000MBPS_LED_STATUS BIT_7 - #define LED_CTRL_100MBPS_LED_STATUS BIT_8 - #define LED_CTRL_10MBPS_LED_STATUS BIT_9 - #define LED_CTRL_TRAFFIC_LED_STATUS BIT_10 - #define LED_CTRL_MAC_MODE BIT_NONE - #define LED_CTRL_PHY_MODE_1 BIT_11 - #define LED_CTRL_PHY_MODE_2 BIT_12 - #define LED_CTRL_BLINK_RATE_MASK 0x7ff80000 - #define LED_CTRL_OVERRIDE_BLINK_PERIOD BIT_19 - #define LED_CTRL_OVERRIDE_BLINK_RATE BIT_31 + /* Led control. */ + T3_32BIT_REGISTER LedCtrl; +#define LED_CTRL_OVERRIDE_LINK_LED BIT_0 +#define LED_CTRL_1000MBPS_LED_ON BIT_1 +#define LED_CTRL_100MBPS_LED_ON BIT_2 +#define LED_CTRL_10MBPS_LED_ON BIT_3 +#define LED_CTRL_OVERRIDE_TRAFFIC_LED BIT_4 +#define LED_CTRL_BLINK_TRAFFIC_LED BIT_5 +#define LED_CTRL_TRAFFIC_LED BIT_6 +#define LED_CTRL_1000MBPS_LED_STATUS BIT_7 +#define LED_CTRL_100MBPS_LED_STATUS BIT_8 +#define LED_CTRL_10MBPS_LED_STATUS BIT_9 +#define LED_CTRL_TRAFFIC_LED_STATUS BIT_10 +#define LED_CTRL_MAC_MODE BIT_NONE +#define LED_CTRL_PHY_MODE_1 BIT_11 +#define LED_CTRL_PHY_MODE_2 BIT_12 +#define LED_CTRL_BLINK_RATE_MASK 0x7ff80000 +#define LED_CTRL_OVERRIDE_BLINK_PERIOD BIT_19 +#define LED_CTRL_OVERRIDE_BLINK_RATE BIT_31 - /* MAC addresses. */ - struct { - T3_32BIT_REGISTER High; /* Upper 2 bytes. */ - T3_32BIT_REGISTER Low; /* Lower 4 bytes. */ - } MacAddr[4]; + /* MAC addresses. */ + struct { + T3_32BIT_REGISTER High; /* Upper 2 bytes. */ + T3_32BIT_REGISTER Low; /* Lower 4 bytes. */ + } MacAddr[4]; - /* ACPI Mbuf pointer. */ - T3_32BIT_REGISTER AcpiMbufPtr; + /* ACPI Mbuf pointer. */ + T3_32BIT_REGISTER AcpiMbufPtr; - /* ACPI Length and Offset. */ - T3_32BIT_REGISTER AcpiLengthOffset; - #define ACPI_LENGTH_MASK 0xffff - #define ACPI_OFFSET_MASK 0x0fff0000 - #define ACPI_LENGTH(x) x - #define ACPI_OFFSET(x) ((x) << 16) + /* ACPI Length and Offset. */ + T3_32BIT_REGISTER AcpiLengthOffset; +#define ACPI_LENGTH_MASK 0xffff +#define ACPI_OFFSET_MASK 0x0fff0000 +#define ACPI_LENGTH(x) x +#define ACPI_OFFSET(x) ((x) << 16) - /* Transmit random backoff. */ - T3_32BIT_REGISTER TxBackoffSeed; - #define MAC_TX_BACKOFF_SEED_MASK 0x3ff + /* Transmit random backoff. */ + T3_32BIT_REGISTER TxBackoffSeed; +#define MAC_TX_BACKOFF_SEED_MASK 0x3ff - /* Receive MTU */ - T3_32BIT_REGISTER MtuSize; - #define MAC_RX_MTU_MASK 0xffff + /* Receive MTU */ + T3_32BIT_REGISTER MtuSize; +#define MAC_RX_MTU_MASK 0xffff - /* Gigabit PCS Test. */ - T3_32BIT_REGISTER PcsTest; - #define MAC_PCS_TEST_DATA_PATTERN_MASK 0x0fffff - #define MAC_PCS_TEST_ENABLE BIT_20 + /* Gigabit PCS Test. */ + T3_32BIT_REGISTER PcsTest; +#define MAC_PCS_TEST_DATA_PATTERN_MASK 0x0fffff +#define MAC_PCS_TEST_ENABLE BIT_20 - /* Transmit Gigabit Auto-Negotiation. */ - T3_32BIT_REGISTER TxAutoNeg; - #define MAC_AN_TX_AN_DATA_MASK 0xffff + /* Transmit Gigabit Auto-Negotiation. */ + T3_32BIT_REGISTER TxAutoNeg; +#define MAC_AN_TX_AN_DATA_MASK 0xffff - /* Receive Gigabit Auto-Negotiation. */ - T3_32BIT_REGISTER RxAutoNeg; - #define MAC_AN_RX_AN_DATA_MASK 0xffff + /* Receive Gigabit Auto-Negotiation. */ + T3_32BIT_REGISTER RxAutoNeg; +#define MAC_AN_RX_AN_DATA_MASK 0xffff - /* MI Communication. */ - T3_32BIT_REGISTER MiCom; - #define MI_COM_CMD_MASK (BIT_26 | BIT_27) - #define MI_COM_CMD_WRITE BIT_26 - #define MI_COM_CMD_READ BIT_27 - #define MI_COM_READ_FAILED BIT_28 - #define MI_COM_START BIT_29 - #define MI_COM_BUSY BIT_29 + /* MI Communication. */ + T3_32BIT_REGISTER MiCom; +#define MI_COM_CMD_MASK (BIT_26 | BIT_27) +#define MI_COM_CMD_WRITE BIT_26 +#define MI_COM_CMD_READ BIT_27 +#define MI_COM_READ_FAILED BIT_28 +#define MI_COM_START BIT_29 +#define MI_COM_BUSY BIT_29 - #define MI_COM_PHY_ADDR_MASK 0x1f - #define MI_COM_FIRST_PHY_ADDR_BIT 21 +#define MI_COM_PHY_ADDR_MASK 0x1f +#define MI_COM_FIRST_PHY_ADDR_BIT 21 - #define MI_COM_PHY_REG_ADDR_MASK 0x1f - #define MI_COM_FIRST_PHY_REG_ADDR_BIT 16 +#define MI_COM_PHY_REG_ADDR_MASK 0x1f +#define MI_COM_FIRST_PHY_REG_ADDR_BIT 16 - #define MI_COM_PHY_DATA_MASK 0xffff +#define MI_COM_PHY_DATA_MASK 0xffff - /* MI Status. */ - T3_32BIT_REGISTER MiStatus; - #define MI_STATUS_ENABLE_LINK_STATUS_ATTN BIT_0 + /* MI Status. */ + T3_32BIT_REGISTER MiStatus; +#define MI_STATUS_ENABLE_LINK_STATUS_ATTN BIT_0 - /* MI Mode. */ - T3_32BIT_REGISTER MiMode; - #define MI_MODE_CLOCK_SPEED_10MHZ BIT_0 - #define MI_MODE_USE_SHORT_PREAMBLE BIT_1 - #define MI_MODE_AUTO_POLLING_ENABLE BIT_4 - #define MI_MODE_CORE_CLOCK_SPEED_62MHZ BIT_15 + /* MI Mode. */ + T3_32BIT_REGISTER MiMode; +#define MI_MODE_CLOCK_SPEED_10MHZ BIT_0 +#define MI_MODE_USE_SHORT_PREAMBLE BIT_1 +#define MI_MODE_AUTO_POLLING_ENABLE BIT_4 +#define MI_MODE_CORE_CLOCK_SPEED_62MHZ BIT_15 - /* Auto-polling status. */ - T3_32BIT_REGISTER AutoPollStatus; - #define AUTO_POLL_ERROR BIT_0 + /* Auto-polling status. */ + T3_32BIT_REGISTER AutoPollStatus; +#define AUTO_POLL_ERROR BIT_0 - /* Transmit MAC mode. */ - T3_32BIT_REGISTER TxMode; - #define TX_MODE_RESET BIT_0 - #define TX_MODE_ENABLE BIT_1 - #define TX_MODE_ENABLE_FLOW_CONTROL BIT_4 - #define TX_MODE_ENABLE_BIG_BACKOFF BIT_5 - #define TX_MODE_ENABLE_LONG_PAUSE BIT_6 + /* Transmit MAC mode. */ + T3_32BIT_REGISTER TxMode; +#define TX_MODE_RESET BIT_0 +#define TX_MODE_ENABLE BIT_1 +#define TX_MODE_ENABLE_FLOW_CONTROL BIT_4 +#define TX_MODE_ENABLE_BIG_BACKOFF BIT_5 +#define TX_MODE_ENABLE_LONG_PAUSE BIT_6 - /* Transmit MAC status. */ - T3_32BIT_REGISTER TxStatus; - #define TX_STATUS_RX_CURRENTLY_XOFFED BIT_0 - #define TX_STATUS_SENT_XOFF BIT_1 - #define TX_STATUS_SENT_XON BIT_2 - #define TX_STATUS_LINK_UP BIT_3 - #define TX_STATUS_ODI_UNDERRUN BIT_4 - #define TX_STATUS_ODI_OVERRUN BIT_5 + /* Transmit MAC status. */ + T3_32BIT_REGISTER TxStatus; +#define TX_STATUS_RX_CURRENTLY_XOFFED BIT_0 +#define TX_STATUS_SENT_XOFF BIT_1 +#define TX_STATUS_SENT_XON BIT_2 +#define TX_STATUS_LINK_UP BIT_3 +#define TX_STATUS_ODI_UNDERRUN BIT_4 +#define TX_STATUS_ODI_OVERRUN BIT_5 - /* Transmit MAC length. */ - T3_32BIT_REGISTER TxLengths; - #define TX_LEN_SLOT_TIME_MASK 0xff - #define TX_LEN_IPG_MASK 0x0f00 - #define TX_LEN_IPG_CRS_MASK (BIT_12 | BIT_13) + /* Transmit MAC length. */ + T3_32BIT_REGISTER TxLengths; +#define TX_LEN_SLOT_TIME_MASK 0xff +#define TX_LEN_IPG_MASK 0x0f00 +#define TX_LEN_IPG_CRS_MASK (BIT_12 | BIT_13) - /* Receive MAC mode. */ - T3_32BIT_REGISTER RxMode; - #define RX_MODE_RESET BIT_0 - #define RX_MODE_ENABLE BIT_1 - #define RX_MODE_ENABLE_FLOW_CONTROL BIT_2 - #define RX_MODE_KEEP_MAC_CONTROL BIT_3 - #define RX_MODE_KEEP_PAUSE BIT_4 - #define RX_MODE_ACCEPT_OVERSIZED BIT_5 - #define RX_MODE_ACCEPT_RUNTS BIT_6 - #define RX_MODE_LENGTH_CHECK BIT_7 - #define RX_MODE_PROMISCUOUS_MODE BIT_8 - #define RX_MODE_NO_CRC_CHECK BIT_9 - #define RX_MODE_KEEP_VLAN_TAG BIT_10 + /* Receive MAC mode. */ + T3_32BIT_REGISTER RxMode; +#define RX_MODE_RESET BIT_0 +#define RX_MODE_ENABLE BIT_1 +#define RX_MODE_ENABLE_FLOW_CONTROL BIT_2 +#define RX_MODE_KEEP_MAC_CONTROL BIT_3 +#define RX_MODE_KEEP_PAUSE BIT_4 +#define RX_MODE_ACCEPT_OVERSIZED BIT_5 +#define RX_MODE_ACCEPT_RUNTS BIT_6 +#define RX_MODE_LENGTH_CHECK BIT_7 +#define RX_MODE_PROMISCUOUS_MODE BIT_8 +#define RX_MODE_NO_CRC_CHECK BIT_9 +#define RX_MODE_KEEP_VLAN_TAG BIT_10 - /* Receive MAC status. */ - T3_32BIT_REGISTER RxStatus; - #define RX_STATUS_REMOTE_TRANSMITTER_XOFFED BIT_0 - #define RX_STATUS_XOFF_RECEIVED BIT_1 - #define RX_STATUS_XON_RECEIVED BIT_2 + /* Receive MAC status. */ + T3_32BIT_REGISTER RxStatus; +#define RX_STATUS_REMOTE_TRANSMITTER_XOFFED BIT_0 +#define RX_STATUS_XOFF_RECEIVED BIT_1 +#define RX_STATUS_XON_RECEIVED BIT_2 - /* Hash registers. */ - T3_32BIT_REGISTER HashReg[4]; + /* Hash registers. */ + T3_32BIT_REGISTER HashReg[4]; - /* Receive placement rules registers. */ - struct { - T3_32BIT_REGISTER Rule; - T3_32BIT_REGISTER Value; - } RcvRules[16]; + /* Receive placement rules registers. */ + struct { + T3_32BIT_REGISTER Rule; + T3_32BIT_REGISTER Value; + } RcvRules[16]; - #define RCV_DISABLE_RULE_MASK 0x7fffffff +#define RCV_DISABLE_RULE_MASK 0x7fffffff - #define RCV_RULE1_REJECT_BROADCAST_IDX 0x00 - #define REJECT_BROADCAST_RULE1_RULE 0xc2000000 - #define REJECT_BROADCAST_RULE1_VALUE 0xffffffff +#define RCV_RULE1_REJECT_BROADCAST_IDX 0x00 +#define REJECT_BROADCAST_RULE1_RULE 0xc2000000 +#define REJECT_BROADCAST_RULE1_VALUE 0xffffffff - #define RCV_RULE2_REJECT_BROADCAST_IDX 0x01 - #define REJECT_BROADCAST_RULE2_RULE 0x86000004 - #define REJECT_BROADCAST_RULE2_VALUE 0xffffffff +#define RCV_RULE2_REJECT_BROADCAST_IDX 0x01 +#define REJECT_BROADCAST_RULE2_RULE 0x86000004 +#define REJECT_BROADCAST_RULE2_VALUE 0xffffffff #if INCLUDE_5701_AX_FIX - #define RCV_LAST_RULE_IDX 0x04 +#define RCV_LAST_RULE_IDX 0x04 #else - #define RCV_LAST_RULE_IDX 0x02 +#define RCV_LAST_RULE_IDX 0x02 #endif - T3_32BIT_REGISTER RcvRuleCfg; - #define RX_RULE_DEFAULT_CLASS (1 << 3) + T3_32BIT_REGISTER RcvRuleCfg; +#define RX_RULE_DEFAULT_CLASS (1 << 3) - LM_UINT8 Reserved1[140]; + LM_UINT8 Reserved1[140]; - T3_32BIT_REGISTER SerdesCfg; - T3_32BIT_REGISTER SerdesStatus; + T3_32BIT_REGISTER SerdesCfg; + T3_32BIT_REGISTER SerdesStatus; - LM_UINT8 Reserved2[104]; + LM_UINT8 Reserved2[104]; - volatile LM_UINT8 TxMacState[16]; - volatile LM_UINT8 RxMacState[20]; + volatile LM_UINT8 TxMacState[16]; + volatile LM_UINT8 RxMacState[20]; - LM_UINT8 Reserved3[476]; + LM_UINT8 Reserved3[476]; - T3_32BIT_REGISTER RxStats[26]; + T3_32BIT_REGISTER RxStats[26]; - LM_UINT8 Reserved4[24]; + LM_UINT8 Reserved4[24]; - T3_32BIT_REGISTER TxStats[28]; + T3_32BIT_REGISTER TxStats[28]; - LM_UINT8 Reserved5[784]; + LM_UINT8 Reserved5[784]; } T3_MAC_CONTROL, *PT3_MAC_CONTROL; - /******************************************************************************/ /* Send data initiator control registers. */ /******************************************************************************/ typedef struct { - T3_32BIT_REGISTER Mode; - #define T3_SND_DATA_IN_MODE_RESET BIT_0 - #define T3_SND_DATA_IN_MODE_ENABLE BIT_1 - #define T3_SND_DATA_IN_MODE_STATS_OFLW_ATTN_ENABLE BIT_2 + T3_32BIT_REGISTER Mode; +#define T3_SND_DATA_IN_MODE_RESET BIT_0 +#define T3_SND_DATA_IN_MODE_ENABLE BIT_1 +#define T3_SND_DATA_IN_MODE_STATS_OFLW_ATTN_ENABLE BIT_2 - T3_32BIT_REGISTER Status; - #define T3_SND_DATA_IN_STATUS_STATS_OFLW_ATTN BIT_2 + T3_32BIT_REGISTER Status; +#define T3_SND_DATA_IN_STATUS_STATS_OFLW_ATTN BIT_2 - T3_32BIT_REGISTER StatsCtrl; - #define T3_SND_DATA_IN_STATS_CTRL_ENABLE BIT_0 - #define T3_SND_DATA_IN_STATS_CTRL_FASTER_UPDATE BIT_1 - #define T3_SND_DATA_IN_STATS_CTRL_CLEAR BIT_2 - #define T3_SND_DATA_IN_STATS_CTRL_FLUSH BIT_3 - #define T3_SND_DATA_IN_STATS_CTRL_FORCE_ZERO BIT_4 + T3_32BIT_REGISTER StatsCtrl; +#define T3_SND_DATA_IN_STATS_CTRL_ENABLE BIT_0 +#define T3_SND_DATA_IN_STATS_CTRL_FASTER_UPDATE BIT_1 +#define T3_SND_DATA_IN_STATS_CTRL_CLEAR BIT_2 +#define T3_SND_DATA_IN_STATS_CTRL_FLUSH BIT_3 +#define T3_SND_DATA_IN_STATS_CTRL_FORCE_ZERO BIT_4 - T3_32BIT_REGISTER StatsEnableMask; - T3_32BIT_REGISTER StatsIncMask; + T3_32BIT_REGISTER StatsEnableMask; + T3_32BIT_REGISTER StatsIncMask; - LM_UINT8 Reserved[108]; + LM_UINT8 Reserved[108]; - T3_32BIT_REGISTER ClassOfServCnt[16]; - T3_32BIT_REGISTER DmaReadQFullCnt; - T3_32BIT_REGISTER DmaPriorityReadQFullCnt; - T3_32BIT_REGISTER SdcQFullCnt; + T3_32BIT_REGISTER ClassOfServCnt[16]; + T3_32BIT_REGISTER DmaReadQFullCnt; + T3_32BIT_REGISTER DmaPriorityReadQFullCnt; + T3_32BIT_REGISTER SdcQFullCnt; - T3_32BIT_REGISTER NicRingSetSendProdIdxCnt; - T3_32BIT_REGISTER StatusUpdatedCnt; - T3_32BIT_REGISTER InterruptsCnt; - T3_32BIT_REGISTER AvoidInterruptsCnt; - T3_32BIT_REGISTER SendThresholdHitCnt; + T3_32BIT_REGISTER NicRingSetSendProdIdxCnt; + T3_32BIT_REGISTER StatusUpdatedCnt; + T3_32BIT_REGISTER InterruptsCnt; + T3_32BIT_REGISTER AvoidInterruptsCnt; + T3_32BIT_REGISTER SendThresholdHitCnt; - /* Unused space. */ - LM_UINT8 Unused[800]; + /* Unused space. */ + LM_UINT8 Unused[800]; } T3_SEND_DATA_INITIATOR, *PT3_SEND_DATA_INITIATOR; - /******************************************************************************/ /* Send data completion control registers. */ /******************************************************************************/ typedef struct { - T3_32BIT_REGISTER Mode; - #define SND_DATA_COMP_MODE_RESET BIT_0 - #define SND_DATA_COMP_MODE_ENABLE BIT_1 + T3_32BIT_REGISTER Mode; +#define SND_DATA_COMP_MODE_RESET BIT_0 +#define SND_DATA_COMP_MODE_ENABLE BIT_1 - /* Unused space. */ - LM_UINT8 Unused[1020]; + /* Unused space. */ + LM_UINT8 Unused[1020]; } T3_SEND_DATA_COMPLETION, *PT3_SEND_DATA_COMPLETION; - /******************************************************************************/ /* Send BD Ring Selector Control Registers. */ /******************************************************************************/ typedef struct { - T3_32BIT_REGISTER Mode; - #define SND_BD_SEL_MODE_RESET BIT_0 - #define SND_BD_SEL_MODE_ENABLE BIT_1 - #define SND_BD_SEL_MODE_ATTN_ENABLE BIT_2 + T3_32BIT_REGISTER Mode; +#define SND_BD_SEL_MODE_RESET BIT_0 +#define SND_BD_SEL_MODE_ENABLE BIT_1 +#define SND_BD_SEL_MODE_ATTN_ENABLE BIT_2 - T3_32BIT_REGISTER Status; - #define SND_BD_SEL_STATUS_ERROR_ATTN BIT_2 + T3_32BIT_REGISTER Status; +#define SND_BD_SEL_STATUS_ERROR_ATTN BIT_2 - T3_32BIT_REGISTER HwDiag; + T3_32BIT_REGISTER HwDiag; - /* Unused space. */ - LM_UINT8 Unused1[52]; + /* Unused space. */ + LM_UINT8 Unused1[52]; - /* Send BD Ring Selector Local NIC Send BD Consumer Index. */ - T3_32BIT_REGISTER NicSendBdSelConIdx[16]; + /* Send BD Ring Selector Local NIC Send BD Consumer Index. */ + T3_32BIT_REGISTER NicSendBdSelConIdx[16]; - /* Unused space. */ - LM_UINT8 Unused2[896]; + /* Unused space. */ + LM_UINT8 Unused2[896]; } T3_SEND_BD_SELECTOR, *PT3_SEND_BD_SELECTOR; - /******************************************************************************/ /* Send BD initiator control registers. */ /******************************************************************************/ typedef struct { - T3_32BIT_REGISTER Mode; - #define SND_BD_IN_MODE_RESET BIT_0 - #define SND_BD_IN_MODE_ENABLE BIT_1 - #define SND_BD_IN_MODE_ATTN_ENABLE BIT_2 + T3_32BIT_REGISTER Mode; +#define SND_BD_IN_MODE_RESET BIT_0 +#define SND_BD_IN_MODE_ENABLE BIT_1 +#define SND_BD_IN_MODE_ATTN_ENABLE BIT_2 - T3_32BIT_REGISTER Status; - #define SND_BD_IN_STATUS_ERROR_ATTN BIT_2 + T3_32BIT_REGISTER Status; +#define SND_BD_IN_STATUS_ERROR_ATTN BIT_2 - /* Send BD initiator local NIC send BD producer index. */ - T3_32BIT_REGISTER NicSendBdInProdIdx[16]; + /* Send BD initiator local NIC send BD producer index. */ + T3_32BIT_REGISTER NicSendBdInProdIdx[16]; - /* Unused space. */ - LM_UINT8 Unused2[952]; + /* Unused space. */ + LM_UINT8 Unused2[952]; } T3_SEND_BD_INITIATOR, *PT3_SEND_BD_INITIATOR; - /******************************************************************************/ /* Send BD Completion Control. */ /******************************************************************************/ typedef struct { - T3_32BIT_REGISTER Mode; - #define SND_BD_COMP_MODE_RESET BIT_0 - #define SND_BD_COMP_MODE_ENABLE BIT_1 - #define SND_BD_COMP_MODE_ATTN_ENABLE BIT_2 + T3_32BIT_REGISTER Mode; +#define SND_BD_COMP_MODE_RESET BIT_0 +#define SND_BD_COMP_MODE_ENABLE BIT_1 +#define SND_BD_COMP_MODE_ATTN_ENABLE BIT_2 - /* Unused space. */ - LM_UINT8 Unused2[1020]; + /* Unused space. */ + LM_UINT8 Unused2[1020]; } T3_SEND_BD_COMPLETION, *PT3_SEND_BD_COMPLETION; - /******************************************************************************/ /* Receive list placement control registers. */ /******************************************************************************/ typedef struct { - /* Mode. */ - T3_32BIT_REGISTER Mode; - #define RCV_LIST_PLMT_MODE_RESET BIT_0 - #define RCV_LIST_PLMT_MODE_ENABLE BIT_1 - #define RCV_LIST_PLMT_MODE_CLASS0_ATTN_ENABLE BIT_2 - #define RCV_LIST_PLMT_MODE_MAPPING_OOR_ATTN_ENABLE BIT_3 - #define RCV_LIST_PLMT_MODE_STATS_OFLOW_ATTN_ENABLE BIT_4 + /* Mode. */ + T3_32BIT_REGISTER Mode; +#define RCV_LIST_PLMT_MODE_RESET BIT_0 +#define RCV_LIST_PLMT_MODE_ENABLE BIT_1 +#define RCV_LIST_PLMT_MODE_CLASS0_ATTN_ENABLE BIT_2 +#define RCV_LIST_PLMT_MODE_MAPPING_OOR_ATTN_ENABLE BIT_3 +#define RCV_LIST_PLMT_MODE_STATS_OFLOW_ATTN_ENABLE BIT_4 - /* Status. */ - T3_32BIT_REGISTER Status; - #define RCV_LIST_PLMT_STATUS_CLASS0_ATTN BIT_2 - #define RCV_LIST_PLMT_STATUS_MAPPING_ATTN BIT_3 - #define RCV_LIST_PLMT_STATUS_STATS_OFLOW_ATTN BIT_4 + /* Status. */ + T3_32BIT_REGISTER Status; +#define RCV_LIST_PLMT_STATUS_CLASS0_ATTN BIT_2 +#define RCV_LIST_PLMT_STATUS_MAPPING_ATTN BIT_3 +#define RCV_LIST_PLMT_STATUS_STATS_OFLOW_ATTN BIT_4 - /* Receive selector list lock register. */ - T3_32BIT_REGISTER Lock; - #define RCV_LIST_SEL_LOCK_REQUEST_MASK 0xffff - #define RCV_LIST_SEL_LOCK_GRANT_MASK 0xffff0000 + /* Receive selector list lock register. */ + T3_32BIT_REGISTER Lock; +#define RCV_LIST_SEL_LOCK_REQUEST_MASK 0xffff +#define RCV_LIST_SEL_LOCK_GRANT_MASK 0xffff0000 - /* Selector non-empty bits. */ - T3_32BIT_REGISTER NonEmptyBits; - #define RCV_LIST_SEL_NON_EMPTY_MASK 0xffff + /* Selector non-empty bits. */ + T3_32BIT_REGISTER NonEmptyBits; +#define RCV_LIST_SEL_NON_EMPTY_MASK 0xffff - /* Receive list placement configuration register. */ - T3_32BIT_REGISTER Config; + /* Receive list placement configuration register. */ + T3_32BIT_REGISTER Config; - /* Receive List Placement statistics Control. */ - T3_32BIT_REGISTER StatsCtrl; + /* Receive List Placement statistics Control. */ + T3_32BIT_REGISTER StatsCtrl; #define RCV_LIST_STATS_ENABLE BIT_0 #define RCV_LIST_STATS_FAST_UPDATE BIT_1 - /* Receive List Placement statistics Enable Mask. */ - T3_32BIT_REGISTER StatsEnableMask; + /* Receive List Placement statistics Enable Mask. */ + T3_32BIT_REGISTER StatsEnableMask; - /* Receive List Placement statistics Increment Mask. */ - T3_32BIT_REGISTER StatsIncMask; - - /* Unused space. */ - LM_UINT8 Unused1[224]; - - struct { - T3_32BIT_REGISTER Head; - T3_32BIT_REGISTER Tail; - T3_32BIT_REGISTER Count; + /* Receive List Placement statistics Increment Mask. */ + T3_32BIT_REGISTER StatsIncMask; /* Unused space. */ - LM_UINT8 Unused[4]; - } RcvSelectorList[16]; + LM_UINT8 Unused1[224]; - /* Local statistics counter. */ - T3_32BIT_REGISTER ClassOfServCnt[16]; + struct { + T3_32BIT_REGISTER Head; + T3_32BIT_REGISTER Tail; + T3_32BIT_REGISTER Count; - T3_32BIT_REGISTER DropDueToFilterCnt; - T3_32BIT_REGISTER DmaWriteQFullCnt; - T3_32BIT_REGISTER DmaHighPriorityWriteQFullCnt; - T3_32BIT_REGISTER NoMoreReceiveBdCnt; - T3_32BIT_REGISTER IfInDiscardsCnt; - T3_32BIT_REGISTER IfInErrorsCnt; - T3_32BIT_REGISTER RcvThresholdHitCnt; + /* Unused space. */ + LM_UINT8 Unused[4]; + } RcvSelectorList[16]; - /* Another unused space. */ - LM_UINT8 Unused2[420]; + /* Local statistics counter. */ + T3_32BIT_REGISTER ClassOfServCnt[16]; + + T3_32BIT_REGISTER DropDueToFilterCnt; + T3_32BIT_REGISTER DmaWriteQFullCnt; + T3_32BIT_REGISTER DmaHighPriorityWriteQFullCnt; + T3_32BIT_REGISTER NoMoreReceiveBdCnt; + T3_32BIT_REGISTER IfInDiscardsCnt; + T3_32BIT_REGISTER IfInErrorsCnt; + T3_32BIT_REGISTER RcvThresholdHitCnt; + + /* Another unused space. */ + LM_UINT8 Unused2[420]; } T3_RCV_LIST_PLACEMENT, *PT3_RCV_LIST_PLACEMENT; - /******************************************************************************/ /* Receive Data and Receive BD Initiator Control. */ /******************************************************************************/ typedef struct { - /* Mode. */ - T3_32BIT_REGISTER Mode; - #define RCV_DATA_BD_IN_MODE_RESET BIT_0 - #define RCV_DATA_BD_IN_MODE_ENABLE BIT_1 - #define RCV_DATA_BD_IN_MODE_JUMBO_BD_NEEDED BIT_2 - #define RCV_DATA_BD_IN_MODE_FRAME_TOO_BIG BIT_3 - #define RCV_DATA_BD_IN_MODE_INVALID_RING_SIZE BIT_4 + /* Mode. */ + T3_32BIT_REGISTER Mode; +#define RCV_DATA_BD_IN_MODE_RESET BIT_0 +#define RCV_DATA_BD_IN_MODE_ENABLE BIT_1 +#define RCV_DATA_BD_IN_MODE_JUMBO_BD_NEEDED BIT_2 +#define RCV_DATA_BD_IN_MODE_FRAME_TOO_BIG BIT_3 +#define RCV_DATA_BD_IN_MODE_INVALID_RING_SIZE BIT_4 - /* Status. */ - T3_32BIT_REGISTER Status; - #define RCV_DATA_BD_IN_STATUS_JUMBO_BD_NEEDED BIT_2 - #define RCV_DATA_BD_IN_STATUS_FRAME_TOO_BIG BIT_3 - #define RCV_DATA_BD_IN_STATUS_INVALID_RING_SIZE BIT_4 + /* Status. */ + T3_32BIT_REGISTER Status; +#define RCV_DATA_BD_IN_STATUS_JUMBO_BD_NEEDED BIT_2 +#define RCV_DATA_BD_IN_STATUS_FRAME_TOO_BIG BIT_3 +#define RCV_DATA_BD_IN_STATUS_INVALID_RING_SIZE BIT_4 - /* Split frame minium size. */ - T3_32BIT_REGISTER SplitFrameMinSize; + /* Split frame minium size. */ + T3_32BIT_REGISTER SplitFrameMinSize; - /* Unused space. */ - LM_UINT8 Unused1[0x2440-0x240c]; + /* Unused space. */ + LM_UINT8 Unused1[0x2440 - 0x240c]; - /* Receive RCBs. */ - T3_RCB JumboRcvRcb; - T3_RCB StdRcvRcb; - T3_RCB MiniRcvRcb; + /* Receive RCBs. */ + T3_RCB JumboRcvRcb; + T3_RCB StdRcvRcb; + T3_RCB MiniRcvRcb; - /* Receive Data and Receive BD Ring Initiator Local NIC Receive */ - /* BD Consumber Index. */ - T3_32BIT_REGISTER NicJumboConIdx; - T3_32BIT_REGISTER NicStdConIdx; - T3_32BIT_REGISTER NicMiniConIdx; + /* Receive Data and Receive BD Ring Initiator Local NIC Receive */ + /* BD Consumber Index. */ + T3_32BIT_REGISTER NicJumboConIdx; + T3_32BIT_REGISTER NicStdConIdx; + T3_32BIT_REGISTER NicMiniConIdx; - /* Unused space. */ - LM_UINT8 Unused2[4]; + /* Unused space. */ + LM_UINT8 Unused2[4]; - /* Receive Data and Receive BD Initiator Local Receive Return ProdIdx. */ - T3_32BIT_REGISTER RcvDataBdProdIdx[16]; + /* Receive Data and Receive BD Initiator Local Receive Return ProdIdx. */ + T3_32BIT_REGISTER RcvDataBdProdIdx[16]; - /* Receive Data and Receive BD Initiator Hardware Diagnostic. */ - T3_32BIT_REGISTER HwDiag; + /* Receive Data and Receive BD Initiator Hardware Diagnostic. */ + T3_32BIT_REGISTER HwDiag; - /* Unused space. */ - LM_UINT8 Unused3[828]; + /* Unused space. */ + LM_UINT8 Unused3[828]; } T3_RCV_DATA_BD_INITIATOR, *PT3_RCV_DATA_BD_INITIATOR; - /******************************************************************************/ /* Receive Data Completion Control Registes. */ /******************************************************************************/ typedef struct { - T3_32BIT_REGISTER Mode; - #define RCV_DATA_COMP_MODE_RESET BIT_0 - #define RCV_DATA_COMP_MODE_ENABLE BIT_1 - #define RCV_DATA_COMP_MODE_ATTN_ENABLE BIT_2 + T3_32BIT_REGISTER Mode; +#define RCV_DATA_COMP_MODE_RESET BIT_0 +#define RCV_DATA_COMP_MODE_ENABLE BIT_1 +#define RCV_DATA_COMP_MODE_ATTN_ENABLE BIT_2 - /* Unused spaced. */ - LM_UINT8 Unused[1020]; + /* Unused spaced. */ + LM_UINT8 Unused[1020]; } T3_RCV_DATA_COMPLETION, *PT3_RCV_DATA_COMPLETION; - /******************************************************************************/ /* Receive BD Initiator Control. */ /******************************************************************************/ typedef struct { - T3_32BIT_REGISTER Mode; - #define RCV_BD_IN_MODE_RESET BIT_0 - #define RCV_BD_IN_MODE_ENABLE BIT_1 - #define RCV_BD_IN_MODE_BD_IN_DIABLED_RCB_ATTN_ENABLE BIT_2 + T3_32BIT_REGISTER Mode; +#define RCV_BD_IN_MODE_RESET BIT_0 +#define RCV_BD_IN_MODE_ENABLE BIT_1 +#define RCV_BD_IN_MODE_BD_IN_DIABLED_RCB_ATTN_ENABLE BIT_2 - T3_32BIT_REGISTER Status; - #define RCV_BD_IN_STATUS_BD_IN_DIABLED_RCB_ATTN BIT_2 + T3_32BIT_REGISTER Status; +#define RCV_BD_IN_STATUS_BD_IN_DIABLED_RCB_ATTN BIT_2 - T3_32BIT_REGISTER NicJumboRcvProdIdx; - T3_32BIT_REGISTER NicStdRcvProdIdx; - T3_32BIT_REGISTER NicMiniRcvProdIdx; + T3_32BIT_REGISTER NicJumboRcvProdIdx; + T3_32BIT_REGISTER NicStdRcvProdIdx; + T3_32BIT_REGISTER NicMiniRcvProdIdx; - T3_32BIT_REGISTER MiniRcvThreshold; - T3_32BIT_REGISTER StdRcvThreshold; - T3_32BIT_REGISTER JumboRcvThreshold; + T3_32BIT_REGISTER MiniRcvThreshold; + T3_32BIT_REGISTER StdRcvThreshold; + T3_32BIT_REGISTER JumboRcvThreshold; - /* Unused space. */ - LM_UINT8 Unused[992]; + /* Unused space. */ + LM_UINT8 Unused[992]; } T3_RCV_BD_INITIATOR, *PT3_RCV_BD_INITIATOR; - /******************************************************************************/ /* Receive BD Completion Control Registers. */ /******************************************************************************/ typedef struct { - T3_32BIT_REGISTER Mode; - #define RCV_BD_COMP_MODE_RESET BIT_0 - #define RCV_BD_COMP_MODE_ENABLE BIT_1 - #define RCV_BD_COMP_MODE_ATTN_ENABLE BIT_2 + T3_32BIT_REGISTER Mode; +#define RCV_BD_COMP_MODE_RESET BIT_0 +#define RCV_BD_COMP_MODE_ENABLE BIT_1 +#define RCV_BD_COMP_MODE_ATTN_ENABLE BIT_2 - T3_32BIT_REGISTER Status; - #define RCV_BD_COMP_STATUS_ERROR_ATTN BIT_2 + T3_32BIT_REGISTER Status; +#define RCV_BD_COMP_STATUS_ERROR_ATTN BIT_2 - T3_32BIT_REGISTER NicJumboRcvBdProdIdx; - T3_32BIT_REGISTER NicStdRcvBdProdIdx; - T3_32BIT_REGISTER NicMiniRcvBdProdIdx; + T3_32BIT_REGISTER NicJumboRcvBdProdIdx; + T3_32BIT_REGISTER NicStdRcvBdProdIdx; + T3_32BIT_REGISTER NicMiniRcvBdProdIdx; - /* Unused space. */ - LM_UINT8 Unused[1004]; + /* Unused space. */ + LM_UINT8 Unused[1004]; } T3_RCV_BD_COMPLETION, *PT3_RCV_BD_COMPLETION; - /******************************************************************************/ /* Receive list selector control register. */ /******************************************************************************/ typedef struct { - T3_32BIT_REGISTER Mode; - #define RCV_LIST_SEL_MODE_RESET BIT_0 - #define RCV_LIST_SEL_MODE_ENABLE BIT_1 - #define RCV_LIST_SEL_MODE_ATTN_ENABLE BIT_2 + T3_32BIT_REGISTER Mode; +#define RCV_LIST_SEL_MODE_RESET BIT_0 +#define RCV_LIST_SEL_MODE_ENABLE BIT_1 +#define RCV_LIST_SEL_MODE_ATTN_ENABLE BIT_2 - T3_32BIT_REGISTER Status; - #define RCV_LIST_SEL_STATUS_ERROR_ATTN BIT_2 + T3_32BIT_REGISTER Status; +#define RCV_LIST_SEL_STATUS_ERROR_ATTN BIT_2 - /* Unused space. */ - LM_UINT8 Unused[1016]; + /* Unused space. */ + LM_UINT8 Unused[1016]; } T3_RCV_LIST_SELECTOR, *PT3_RCV_LIST_SELECTOR; - /******************************************************************************/ /* Mbuf cluster free registers. */ /******************************************************************************/ typedef struct { - T3_32BIT_REGISTER Mode; + T3_32BIT_REGISTER Mode; #define MBUF_CLUSTER_FREE_MODE_RESET BIT_0 #define MBUF_CLUSTER_FREE_MODE_ENABLE BIT_1 - T3_32BIT_REGISTER Status; + T3_32BIT_REGISTER Status; - /* Unused space. */ - LM_UINT8 Unused[1016]; + /* Unused space. */ + LM_UINT8 Unused[1016]; } T3_MBUF_CLUSTER_FREE, *PT3_MBUF_CLUSTER_FREE; - /******************************************************************************/ /* Host coalescing control registers. */ /******************************************************************************/ typedef struct { - /* Mode. */ - T3_32BIT_REGISTER Mode; - #define HOST_COALESCE_RESET BIT_0 - #define HOST_COALESCE_ENABLE BIT_1 - #define HOST_COALESCE_ATTN BIT_2 - #define HOST_COALESCE_NOW BIT_3 - #define HOST_COALESCE_FULL_STATUS_MODE BIT_NONE - #define HOST_COALESCE_64_BYTE_STATUS_MODE BIT_7 - #define HOST_COALESCE_32_BYTE_STATUS_MODE BIT_8 - #define HOST_COALESCE_CLEAR_TICKS_ON_RX_BD_EVENT BIT_9 - #define HOST_COALESCE_CLEAR_TICKS_ON_TX_BD_EVENT BIT_10 - #define HOST_COALESCE_NO_INT_ON_COALESCE_NOW_MODE BIT_11 - #define HOST_COALESCE_NO_INT_ON_FORCE_DMAD_MODE BIT_12 + /* Mode. */ + T3_32BIT_REGISTER Mode; +#define HOST_COALESCE_RESET BIT_0 +#define HOST_COALESCE_ENABLE BIT_1 +#define HOST_COALESCE_ATTN BIT_2 +#define HOST_COALESCE_NOW BIT_3 +#define HOST_COALESCE_FULL_STATUS_MODE BIT_NONE +#define HOST_COALESCE_64_BYTE_STATUS_MODE BIT_7 +#define HOST_COALESCE_32_BYTE_STATUS_MODE BIT_8 +#define HOST_COALESCE_CLEAR_TICKS_ON_RX_BD_EVENT BIT_9 +#define HOST_COALESCE_CLEAR_TICKS_ON_TX_BD_EVENT BIT_10 +#define HOST_COALESCE_NO_INT_ON_COALESCE_NOW_MODE BIT_11 +#define HOST_COALESCE_NO_INT_ON_FORCE_DMAD_MODE BIT_12 - /* Status. */ - T3_32BIT_REGISTER Status; - #define HOST_COALESCE_ERROR_ATTN BIT_2 + /* Status. */ + T3_32BIT_REGISTER Status; +#define HOST_COALESCE_ERROR_ATTN BIT_2 - /* Receive coalescing ticks. */ - T3_32BIT_REGISTER RxCoalescingTicks; + /* Receive coalescing ticks. */ + T3_32BIT_REGISTER RxCoalescingTicks; - /* Send coalescing ticks. */ - T3_32BIT_REGISTER TxCoalescingTicks; + /* Send coalescing ticks. */ + T3_32BIT_REGISTER TxCoalescingTicks; - /* Receive max coalesced frames. */ - T3_32BIT_REGISTER RxMaxCoalescedFrames; + /* Receive max coalesced frames. */ + T3_32BIT_REGISTER RxMaxCoalescedFrames; - /* Send max coalesced frames. */ - T3_32BIT_REGISTER TxMaxCoalescedFrames; + /* Send max coalesced frames. */ + T3_32BIT_REGISTER TxMaxCoalescedFrames; - /* Receive coalescing ticks during interrupt. */ - T3_32BIT_REGISTER RxCoalescedTickDuringInt; + /* Receive coalescing ticks during interrupt. */ + T3_32BIT_REGISTER RxCoalescedTickDuringInt; - /* Send coalescing ticks during interrupt. */ - T3_32BIT_REGISTER TxCoalescedTickDuringInt; + /* Send coalescing ticks during interrupt. */ + T3_32BIT_REGISTER TxCoalescedTickDuringInt; - /* Receive max coalesced frames during interrupt. */ - T3_32BIT_REGISTER RxMaxCoalescedFramesDuringInt; + /* Receive max coalesced frames during interrupt. */ + T3_32BIT_REGISTER RxMaxCoalescedFramesDuringInt; - /* Send max coalesced frames during interrupt. */ - T3_32BIT_REGISTER TxMaxCoalescedFramesDuringInt; + /* Send max coalesced frames during interrupt. */ + T3_32BIT_REGISTER TxMaxCoalescedFramesDuringInt; - /* Statistics tick. */ - T3_32BIT_REGISTER StatsCoalescingTicks; + /* Statistics tick. */ + T3_32BIT_REGISTER StatsCoalescingTicks; - /* Unused space. */ - LM_UINT8 Unused2[4]; + /* Unused space. */ + LM_UINT8 Unused2[4]; - /* Statistics host address. */ - T3_64BIT_REGISTER StatsBlkHostAddr; + /* Statistics host address. */ + T3_64BIT_REGISTER StatsBlkHostAddr; - /* Status block host address.*/ - T3_64BIT_REGISTER StatusBlkHostAddr; + /* Status block host address. */ + T3_64BIT_REGISTER StatusBlkHostAddr; - /* Statistics NIC address. */ - T3_32BIT_REGISTER StatsBlkNicAddr; + /* Statistics NIC address. */ + T3_32BIT_REGISTER StatsBlkNicAddr; - /* Statust block NIC address. */ - T3_32BIT_REGISTER StatusBlkNicAddr; + /* Statust block NIC address. */ + T3_32BIT_REGISTER StatusBlkNicAddr; - /* Flow attention registers. */ - T3_32BIT_REGISTER FlowAttn; + /* Flow attention registers. */ + T3_32BIT_REGISTER FlowAttn; - /* Unused space. */ - LM_UINT8 Unused3[4]; + /* Unused space. */ + LM_UINT8 Unused3[4]; - T3_32BIT_REGISTER NicJumboRcvBdConIdx; - T3_32BIT_REGISTER NicStdRcvBdConIdx; - T3_32BIT_REGISTER NicMiniRcvBdConIdx; + T3_32BIT_REGISTER NicJumboRcvBdConIdx; + T3_32BIT_REGISTER NicStdRcvBdConIdx; + T3_32BIT_REGISTER NicMiniRcvBdConIdx; - /* Unused space. */ - LM_UINT8 Unused4[36]; + /* Unused space. */ + LM_UINT8 Unused4[36]; - T3_32BIT_REGISTER NicRetProdIdx[16]; - T3_32BIT_REGISTER NicSndBdConIdx[16]; + T3_32BIT_REGISTER NicRetProdIdx[16]; + T3_32BIT_REGISTER NicSndBdConIdx[16]; - /* Unused space. */ - LM_UINT8 Unused5[768]; + /* Unused space. */ + LM_UINT8 Unused5[768]; } T3_HOST_COALESCING, *PT3_HOST_COALESCING; - /******************************************************************************/ /* Memory arbiter registers. */ /******************************************************************************/ typedef struct { - T3_32BIT_REGISTER Mode; + T3_32BIT_REGISTER Mode; #define T3_MEM_ARBITER_MODE_RESET BIT_0 #define T3_MEM_ARBITER_MODE_ENABLE BIT_1 - T3_32BIT_REGISTER Status; + T3_32BIT_REGISTER Status; - T3_32BIT_REGISTER ArbTrapAddrLow; - T3_32BIT_REGISTER ArbTrapAddrHigh; + T3_32BIT_REGISTER ArbTrapAddrLow; + T3_32BIT_REGISTER ArbTrapAddrHigh; - /* Unused space. */ - LM_UINT8 Unused[1008]; + /* Unused space. */ + LM_UINT8 Unused[1008]; } T3_MEM_ARBITER, *PT3_MEM_ARBITER; - /******************************************************************************/ /* Buffer manager control register. */ /******************************************************************************/ typedef struct { - T3_32BIT_REGISTER Mode; - #define BUFMGR_MODE_RESET BIT_0 - #define BUFMGR_MODE_ENABLE BIT_1 - #define BUFMGR_MODE_ATTN_ENABLE BIT_2 - #define BUFMGR_MODE_BM_TEST BIT_3 - #define BUFMGR_MODE_MBUF_LOW_ATTN_ENABLE BIT_4 + T3_32BIT_REGISTER Mode; +#define BUFMGR_MODE_RESET BIT_0 +#define BUFMGR_MODE_ENABLE BIT_1 +#define BUFMGR_MODE_ATTN_ENABLE BIT_2 +#define BUFMGR_MODE_BM_TEST BIT_3 +#define BUFMGR_MODE_MBUF_LOW_ATTN_ENABLE BIT_4 - T3_32BIT_REGISTER Status; - #define BUFMGR_STATUS_ERROR BIT_2 - #define BUFMGR_STATUS_MBUF_LOW BIT_4 + T3_32BIT_REGISTER Status; +#define BUFMGR_STATUS_ERROR BIT_2 +#define BUFMGR_STATUS_MBUF_LOW BIT_4 - T3_32BIT_REGISTER MbufPoolAddr; - T3_32BIT_REGISTER MbufPoolSize; - T3_32BIT_REGISTER MbufReadDmaLowWaterMark; - T3_32BIT_REGISTER MbufMacRxLowWaterMark; - T3_32BIT_REGISTER MbufHighWaterMark; + T3_32BIT_REGISTER MbufPoolAddr; + T3_32BIT_REGISTER MbufPoolSize; + T3_32BIT_REGISTER MbufReadDmaLowWaterMark; + T3_32BIT_REGISTER MbufMacRxLowWaterMark; + T3_32BIT_REGISTER MbufHighWaterMark; - T3_32BIT_REGISTER RxCpuMbufAllocReq; - #define BUFMGR_MBUF_ALLOC_BIT BIT_31 - T3_32BIT_REGISTER RxCpuMbufAllocResp; - T3_32BIT_REGISTER TxCpuMbufAllocReq; - T3_32BIT_REGISTER TxCpuMbufAllocResp; + T3_32BIT_REGISTER RxCpuMbufAllocReq; +#define BUFMGR_MBUF_ALLOC_BIT BIT_31 + T3_32BIT_REGISTER RxCpuMbufAllocResp; + T3_32BIT_REGISTER TxCpuMbufAllocReq; + T3_32BIT_REGISTER TxCpuMbufAllocResp; - T3_32BIT_REGISTER DmaDescPoolAddr; - T3_32BIT_REGISTER DmaDescPoolSize; - T3_32BIT_REGISTER DmaLowWaterMark; - T3_32BIT_REGISTER DmaHighWaterMark; + T3_32BIT_REGISTER DmaDescPoolAddr; + T3_32BIT_REGISTER DmaDescPoolSize; + T3_32BIT_REGISTER DmaLowWaterMark; + T3_32BIT_REGISTER DmaHighWaterMark; - T3_32BIT_REGISTER RxCpuDmaAllocReq; - T3_32BIT_REGISTER RxCpuDmaAllocResp; - T3_32BIT_REGISTER TxCpuDmaAllocReq; - T3_32BIT_REGISTER TxCpuDmaAllocResp; + T3_32BIT_REGISTER RxCpuDmaAllocReq; + T3_32BIT_REGISTER RxCpuDmaAllocResp; + T3_32BIT_REGISTER TxCpuDmaAllocReq; + T3_32BIT_REGISTER TxCpuDmaAllocResp; - T3_32BIT_REGISTER Hwdiag[3]; + T3_32BIT_REGISTER Hwdiag[3]; - /* Unused space. */ - LM_UINT8 Unused[936]; + /* Unused space. */ + LM_UINT8 Unused[936]; } T3_BUFFER_MANAGER, *PT3_BUFFER_MANAGER; - /******************************************************************************/ /* Read DMA control registers. */ /******************************************************************************/ typedef struct { - T3_32BIT_REGISTER Mode; - #define DMA_READ_MODE_RESET BIT_0 - #define DMA_READ_MODE_ENABLE BIT_1 - #define DMA_READ_MODE_TARGET_ABORT_ATTN_ENABLE BIT_2 - #define DMA_READ_MODE_MASTER_ABORT_ATTN_ENABLE BIT_3 - #define DMA_READ_MODE_PARITY_ERROR_ATTN_ENABLE BIT_4 - #define DMA_READ_MODE_ADDR_OVERFLOW_ATTN_ENABLE BIT_5 - #define DMA_READ_MODE_FIFO_OVERRUN_ATTN_ENABLE BIT_6 - #define DMA_READ_MODE_FIFO_UNDERRUN_ATTN_ENABLE BIT_7 - #define DMA_READ_MODE_FIFO_OVERREAD_ATTN_ENABLE BIT_8 - #define DMA_READ_MODE_LONG_READ_ATTN_ENABLE BIT_9 - #define DMA_READ_MODE_SPLIT_ENABLE BIT_11 - #define DMA_READ_MODE_SPLIT_RESET BIT_12 + T3_32BIT_REGISTER Mode; +#define DMA_READ_MODE_RESET BIT_0 +#define DMA_READ_MODE_ENABLE BIT_1 +#define DMA_READ_MODE_TARGET_ABORT_ATTN_ENABLE BIT_2 +#define DMA_READ_MODE_MASTER_ABORT_ATTN_ENABLE BIT_3 +#define DMA_READ_MODE_PARITY_ERROR_ATTN_ENABLE BIT_4 +#define DMA_READ_MODE_ADDR_OVERFLOW_ATTN_ENABLE BIT_5 +#define DMA_READ_MODE_FIFO_OVERRUN_ATTN_ENABLE BIT_6 +#define DMA_READ_MODE_FIFO_UNDERRUN_ATTN_ENABLE BIT_7 +#define DMA_READ_MODE_FIFO_OVERREAD_ATTN_ENABLE BIT_8 +#define DMA_READ_MODE_LONG_READ_ATTN_ENABLE BIT_9 +#define DMA_READ_MODE_SPLIT_ENABLE BIT_11 +#define DMA_READ_MODE_SPLIT_RESET BIT_12 - T3_32BIT_REGISTER Status; - #define DMA_READ_STATUS_TARGET_ABORT_ATTN BIT_2 - #define DMA_READ_STATUS_MASTER_ABORT_ATTN BIT_3 - #define DMA_READ_STATUS_PARITY_ERROR_ATTN BIT_4 - #define DMA_READ_STATUS_ADDR_OVERFLOW_ATTN BIT_5 - #define DMA_READ_STATUS_FIFO_OVERRUN_ATTN BIT_6 - #define DMA_READ_STATUS_FIFO_UNDERRUN_ATTN BIT_7 - #define DMA_READ_STATUS_FIFO_OVERREAD_ATTN BIT_8 - #define DMA_READ_STATUS_LONG_READ_ATTN BIT_9 + T3_32BIT_REGISTER Status; +#define DMA_READ_STATUS_TARGET_ABORT_ATTN BIT_2 +#define DMA_READ_STATUS_MASTER_ABORT_ATTN BIT_3 +#define DMA_READ_STATUS_PARITY_ERROR_ATTN BIT_4 +#define DMA_READ_STATUS_ADDR_OVERFLOW_ATTN BIT_5 +#define DMA_READ_STATUS_FIFO_OVERRUN_ATTN BIT_6 +#define DMA_READ_STATUS_FIFO_UNDERRUN_ATTN BIT_7 +#define DMA_READ_STATUS_FIFO_OVERREAD_ATTN BIT_8 +#define DMA_READ_STATUS_LONG_READ_ATTN BIT_9 - /* Unused space. */ - LM_UINT8 Unused[1016]; + /* Unused space. */ + LM_UINT8 Unused[1016]; } T3_DMA_READ, *PT3_DMA_READ; -typedef union T3_CPU -{ - struct - { - T3_32BIT_REGISTER mode; - #define CPU_MODE_HALT BIT_10 - #define CPU_MODE_RESET BIT_0 - T3_32BIT_REGISTER state; - T3_32BIT_REGISTER EventMask; - T3_32BIT_REGISTER reserved1[4]; - T3_32BIT_REGISTER PC; - T3_32BIT_REGISTER Instruction; - T3_32BIT_REGISTER SpadUnderflow; - T3_32BIT_REGISTER WatchdogClear; - T3_32BIT_REGISTER WatchdogVector; - T3_32BIT_REGISTER WatchdogSavedPC; - T3_32BIT_REGISTER HardwareBp; - T3_32BIT_REGISTER reserved2[3]; - T3_32BIT_REGISTER WatchdogSavedState; - T3_32BIT_REGISTER LastBrchAddr; - T3_32BIT_REGISTER SpadUnderflowSet; - T3_32BIT_REGISTER reserved3[(0x200-0x50)/4]; - T3_32BIT_REGISTER Regs[32]; - T3_32BIT_REGISTER reserved4[(0x400-0x280)/4]; - }reg; -}T3_CPU, *PT3_CPU; +typedef union T3_CPU { + struct { + T3_32BIT_REGISTER mode; +#define CPU_MODE_HALT BIT_10 +#define CPU_MODE_RESET BIT_0 + T3_32BIT_REGISTER state; + T3_32BIT_REGISTER EventMask; + T3_32BIT_REGISTER reserved1[4]; + T3_32BIT_REGISTER PC; + T3_32BIT_REGISTER Instruction; + T3_32BIT_REGISTER SpadUnderflow; + T3_32BIT_REGISTER WatchdogClear; + T3_32BIT_REGISTER WatchdogVector; + T3_32BIT_REGISTER WatchdogSavedPC; + T3_32BIT_REGISTER HardwareBp; + T3_32BIT_REGISTER reserved2[3]; + T3_32BIT_REGISTER WatchdogSavedState; + T3_32BIT_REGISTER LastBrchAddr; + T3_32BIT_REGISTER SpadUnderflowSet; + T3_32BIT_REGISTER reserved3[(0x200 - 0x50) / 4]; + T3_32BIT_REGISTER Regs[32]; + T3_32BIT_REGISTER reserved4[(0x400 - 0x280) / 4]; + } reg; +} T3_CPU, *PT3_CPU; /******************************************************************************/ /* Write DMA control registers. */ /******************************************************************************/ typedef struct { - T3_32BIT_REGISTER Mode; - #define DMA_WRITE_MODE_RESET BIT_0 - #define DMA_WRITE_MODE_ENABLE BIT_1 - #define DMA_WRITE_MODE_TARGET_ABORT_ATTN_ENABLE BIT_2 - #define DMA_WRITE_MODE_MASTER_ABORT_ATTN_ENABLE BIT_3 - #define DMA_WRITE_MODE_PARITY_ERROR_ATTN_ENABLE BIT_4 - #define DMA_WRITE_MODE_ADDR_OVERFLOW_ATTN_ENABLE BIT_5 - #define DMA_WRITE_MODE_FIFO_OVERRUN_ATTN_ENABLE BIT_6 - #define DMA_WRITE_MODE_FIFO_UNDERRUN_ATTN_ENABLE BIT_7 - #define DMA_WRITE_MODE_FIFO_OVERREAD_ATTN_ENABLE BIT_8 - #define DMA_WRITE_MODE_LONG_READ_ATTN_ENABLE BIT_9 + T3_32BIT_REGISTER Mode; +#define DMA_WRITE_MODE_RESET BIT_0 +#define DMA_WRITE_MODE_ENABLE BIT_1 +#define DMA_WRITE_MODE_TARGET_ABORT_ATTN_ENABLE BIT_2 +#define DMA_WRITE_MODE_MASTER_ABORT_ATTN_ENABLE BIT_3 +#define DMA_WRITE_MODE_PARITY_ERROR_ATTN_ENABLE BIT_4 +#define DMA_WRITE_MODE_ADDR_OVERFLOW_ATTN_ENABLE BIT_5 +#define DMA_WRITE_MODE_FIFO_OVERRUN_ATTN_ENABLE BIT_6 +#define DMA_WRITE_MODE_FIFO_UNDERRUN_ATTN_ENABLE BIT_7 +#define DMA_WRITE_MODE_FIFO_OVERREAD_ATTN_ENABLE BIT_8 +#define DMA_WRITE_MODE_LONG_READ_ATTN_ENABLE BIT_9 - T3_32BIT_REGISTER Status; - #define DMA_WRITE_STATUS_TARGET_ABORT_ATTN BIT_2 - #define DMA_WRITE_STATUS_MASTER_ABORT_ATTN BIT_3 - #define DMA_WRITE_STATUS_PARITY_ERROR_ATTN BIT_4 - #define DMA_WRITE_STATUS_ADDR_OVERFLOW_ATTN BIT_5 - #define DMA_WRITE_STATUS_FIFO_OVERRUN_ATTN BIT_6 - #define DMA_WRITE_STATUS_FIFO_UNDERRUN_ATTN BIT_7 - #define DMA_WRITE_STATUS_FIFO_OVERREAD_ATTN BIT_8 - #define DMA_WRITE_STATUS_LONG_READ_ATTN BIT_9 + T3_32BIT_REGISTER Status; +#define DMA_WRITE_STATUS_TARGET_ABORT_ATTN BIT_2 +#define DMA_WRITE_STATUS_MASTER_ABORT_ATTN BIT_3 +#define DMA_WRITE_STATUS_PARITY_ERROR_ATTN BIT_4 +#define DMA_WRITE_STATUS_ADDR_OVERFLOW_ATTN BIT_5 +#define DMA_WRITE_STATUS_FIFO_OVERRUN_ATTN BIT_6 +#define DMA_WRITE_STATUS_FIFO_UNDERRUN_ATTN BIT_7 +#define DMA_WRITE_STATUS_FIFO_OVERREAD_ATTN BIT_8 +#define DMA_WRITE_STATUS_LONG_READ_ATTN BIT_9 - /* Unused space. */ - LM_UINT8 Unused[1016]; + /* Unused space. */ + LM_UINT8 Unused[1016]; } T3_DMA_WRITE, *PT3_DMA_WRITE; - /******************************************************************************/ /* Mailbox registers. */ /******************************************************************************/ typedef struct { - /* Interrupt mailbox registers. */ - T3_64BIT_REGISTER Interrupt[4]; + /* Interrupt mailbox registers. */ + T3_64BIT_REGISTER Interrupt[4]; - /* General mailbox registers. */ - T3_64BIT_REGISTER General[8]; + /* General mailbox registers. */ + T3_64BIT_REGISTER General[8]; - /* Reload statistics mailbox. */ - T3_64BIT_REGISTER ReloadStat; + /* Reload statistics mailbox. */ + T3_64BIT_REGISTER ReloadStat; - /* Receive BD ring producer index registers. */ - T3_64BIT_REGISTER RcvStdProdIdx; - T3_64BIT_REGISTER RcvJumboProdIdx; - T3_64BIT_REGISTER RcvMiniProdIdx; + /* Receive BD ring producer index registers. */ + T3_64BIT_REGISTER RcvStdProdIdx; + T3_64BIT_REGISTER RcvJumboProdIdx; + T3_64BIT_REGISTER RcvMiniProdIdx; - /* Receive return ring consumer index registers. */ - T3_64BIT_REGISTER RcvRetConIdx[16]; + /* Receive return ring consumer index registers. */ + T3_64BIT_REGISTER RcvRetConIdx[16]; - /* Send BD ring host producer index registers. */ - T3_64BIT_REGISTER SendHostProdIdx[16]; + /* Send BD ring host producer index registers. */ + T3_64BIT_REGISTER SendHostProdIdx[16]; - /* Send BD ring nic producer index registers. */ - T3_64BIT_REGISTER SendNicProdIdx[16]; -}T3_MAILBOX, *PT3_MAILBOX; + /* Send BD ring nic producer index registers. */ + T3_64BIT_REGISTER SendNicProdIdx[16]; +} T3_MAILBOX, *PT3_MAILBOX; typedef struct { - T3_MAILBOX Mailbox; + T3_MAILBOX Mailbox; - /* Priority mailbox registers. */ - T3_32BIT_REGISTER HighPriorityEventVector; - T3_32BIT_REGISTER HighPriorityEventMask; - T3_32BIT_REGISTER LowPriorityEventVector; - T3_32BIT_REGISTER LowPriorityEventMask; + /* Priority mailbox registers. */ + T3_32BIT_REGISTER HighPriorityEventVector; + T3_32BIT_REGISTER HighPriorityEventMask; + T3_32BIT_REGISTER LowPriorityEventVector; + T3_32BIT_REGISTER LowPriorityEventMask; - /* Unused space. */ - LM_UINT8 Unused[496]; + /* Unused space. */ + LM_UINT8 Unused[496]; } T3_GRC_MAILBOX, *PT3_GRC_MAILBOX; - /******************************************************************************/ /* Flow through queues. */ /******************************************************************************/ typedef struct { - T3_32BIT_REGISTER Reset; + T3_32BIT_REGISTER Reset; - LM_UINT8 Unused[12]; + LM_UINT8 Unused[12]; - T3_32BIT_REGISTER DmaNormalReadFtqCtrl; - T3_32BIT_REGISTER DmaNormalReadFtqFullCnt; - T3_32BIT_REGISTER DmaNormalReadFtqFifoEnqueueDequeue; - T3_32BIT_REGISTER DmaNormalReadFtqFifoWritePeek; + T3_32BIT_REGISTER DmaNormalReadFtqCtrl; + T3_32BIT_REGISTER DmaNormalReadFtqFullCnt; + T3_32BIT_REGISTER DmaNormalReadFtqFifoEnqueueDequeue; + T3_32BIT_REGISTER DmaNormalReadFtqFifoWritePeek; - T3_32BIT_REGISTER DmaHighReadFtqCtrl; - T3_32BIT_REGISTER DmaHighReadFtqFullCnt; - T3_32BIT_REGISTER DmaHighReadFtqFifoEnqueueDequeue; - T3_32BIT_REGISTER DmaHighReadFtqFifoWritePeek; + T3_32BIT_REGISTER DmaHighReadFtqCtrl; + T3_32BIT_REGISTER DmaHighReadFtqFullCnt; + T3_32BIT_REGISTER DmaHighReadFtqFifoEnqueueDequeue; + T3_32BIT_REGISTER DmaHighReadFtqFifoWritePeek; - T3_32BIT_REGISTER DmaCompDiscardFtqCtrl; - T3_32BIT_REGISTER DmaCompDiscardFtqFullCnt; - T3_32BIT_REGISTER DmaCompDiscardFtqFifoEnqueueDequeue; - T3_32BIT_REGISTER DmaCompDiscardFtqFifoWritePeek; + T3_32BIT_REGISTER DmaCompDiscardFtqCtrl; + T3_32BIT_REGISTER DmaCompDiscardFtqFullCnt; + T3_32BIT_REGISTER DmaCompDiscardFtqFifoEnqueueDequeue; + T3_32BIT_REGISTER DmaCompDiscardFtqFifoWritePeek; - T3_32BIT_REGISTER SendBdCompFtqCtrl; - T3_32BIT_REGISTER SendBdCompFtqFullCnt; - T3_32BIT_REGISTER SendBdCompFtqFifoEnqueueDequeue; - T3_32BIT_REGISTER SendBdCompFtqFifoWritePeek; + T3_32BIT_REGISTER SendBdCompFtqCtrl; + T3_32BIT_REGISTER SendBdCompFtqFullCnt; + T3_32BIT_REGISTER SendBdCompFtqFifoEnqueueDequeue; + T3_32BIT_REGISTER SendBdCompFtqFifoWritePeek; - T3_32BIT_REGISTER SendDataInitiatorFtqCtrl; - T3_32BIT_REGISTER SendDataInitiatorFtqFullCnt; - T3_32BIT_REGISTER SendDataInitiatorFtqFifoEnqueueDequeue; - T3_32BIT_REGISTER SendDataInitiatorFtqFifoWritePeek; + T3_32BIT_REGISTER SendDataInitiatorFtqCtrl; + T3_32BIT_REGISTER SendDataInitiatorFtqFullCnt; + T3_32BIT_REGISTER SendDataInitiatorFtqFifoEnqueueDequeue; + T3_32BIT_REGISTER SendDataInitiatorFtqFifoWritePeek; - T3_32BIT_REGISTER DmaNormalWriteFtqCtrl; - T3_32BIT_REGISTER DmaNormalWriteFtqFullCnt; - T3_32BIT_REGISTER DmaNormalWriteFtqFifoEnqueueDequeue; - T3_32BIT_REGISTER DmaNormalWriteFtqFifoWritePeek; + T3_32BIT_REGISTER DmaNormalWriteFtqCtrl; + T3_32BIT_REGISTER DmaNormalWriteFtqFullCnt; + T3_32BIT_REGISTER DmaNormalWriteFtqFifoEnqueueDequeue; + T3_32BIT_REGISTER DmaNormalWriteFtqFifoWritePeek; - T3_32BIT_REGISTER DmaHighWriteFtqCtrl; - T3_32BIT_REGISTER DmaHighWriteFtqFullCnt; - T3_32BIT_REGISTER DmaHighWriteFtqFifoEnqueueDequeue; - T3_32BIT_REGISTER DmaHighWriteFtqFifoWritePeek; + T3_32BIT_REGISTER DmaHighWriteFtqCtrl; + T3_32BIT_REGISTER DmaHighWriteFtqFullCnt; + T3_32BIT_REGISTER DmaHighWriteFtqFifoEnqueueDequeue; + T3_32BIT_REGISTER DmaHighWriteFtqFifoWritePeek; - T3_32BIT_REGISTER SwType1FtqCtrl; - T3_32BIT_REGISTER SwType1FtqFullCnt; - T3_32BIT_REGISTER SwType1FtqFifoEnqueueDequeue; - T3_32BIT_REGISTER SwType1FtqFifoWritePeek; + T3_32BIT_REGISTER SwType1FtqCtrl; + T3_32BIT_REGISTER SwType1FtqFullCnt; + T3_32BIT_REGISTER SwType1FtqFifoEnqueueDequeue; + T3_32BIT_REGISTER SwType1FtqFifoWritePeek; - T3_32BIT_REGISTER SendDataCompFtqCtrl; - T3_32BIT_REGISTER SendDataCompFtqFullCnt; - T3_32BIT_REGISTER SendDataCompFtqFifoEnqueueDequeue; - T3_32BIT_REGISTER SendDataCompFtqFifoWritePeek; + T3_32BIT_REGISTER SendDataCompFtqCtrl; + T3_32BIT_REGISTER SendDataCompFtqFullCnt; + T3_32BIT_REGISTER SendDataCompFtqFifoEnqueueDequeue; + T3_32BIT_REGISTER SendDataCompFtqFifoWritePeek; - T3_32BIT_REGISTER HostCoalesceFtqCtrl; - T3_32BIT_REGISTER HostCoalesceFtqFullCnt; - T3_32BIT_REGISTER HostCoalesceFtqFifoEnqueueDequeue; - T3_32BIT_REGISTER HostCoalesceFtqFifoWritePeek; + T3_32BIT_REGISTER HostCoalesceFtqCtrl; + T3_32BIT_REGISTER HostCoalesceFtqFullCnt; + T3_32BIT_REGISTER HostCoalesceFtqFifoEnqueueDequeue; + T3_32BIT_REGISTER HostCoalesceFtqFifoWritePeek; - T3_32BIT_REGISTER MacTxFtqCtrl; - T3_32BIT_REGISTER MacTxFtqFullCnt; - T3_32BIT_REGISTER MacTxFtqFifoEnqueueDequeue; - T3_32BIT_REGISTER MacTxFtqFifoWritePeek; + T3_32BIT_REGISTER MacTxFtqCtrl; + T3_32BIT_REGISTER MacTxFtqFullCnt; + T3_32BIT_REGISTER MacTxFtqFifoEnqueueDequeue; + T3_32BIT_REGISTER MacTxFtqFifoWritePeek; - T3_32BIT_REGISTER MbufClustFreeFtqCtrl; - T3_32BIT_REGISTER MbufClustFreeFtqFullCnt; - T3_32BIT_REGISTER MbufClustFreeFtqFifoEnqueueDequeue; - T3_32BIT_REGISTER MbufClustFreeFtqFifoWritePeek; + T3_32BIT_REGISTER MbufClustFreeFtqCtrl; + T3_32BIT_REGISTER MbufClustFreeFtqFullCnt; + T3_32BIT_REGISTER MbufClustFreeFtqFifoEnqueueDequeue; + T3_32BIT_REGISTER MbufClustFreeFtqFifoWritePeek; - T3_32BIT_REGISTER RcvBdCompFtqCtrl; - T3_32BIT_REGISTER RcvBdCompFtqFullCnt; - T3_32BIT_REGISTER RcvBdCompFtqFifoEnqueueDequeue; - T3_32BIT_REGISTER RcvBdCompFtqFifoWritePeek; + T3_32BIT_REGISTER RcvBdCompFtqCtrl; + T3_32BIT_REGISTER RcvBdCompFtqFullCnt; + T3_32BIT_REGISTER RcvBdCompFtqFifoEnqueueDequeue; + T3_32BIT_REGISTER RcvBdCompFtqFifoWritePeek; - T3_32BIT_REGISTER RcvListPlmtFtqCtrl; - T3_32BIT_REGISTER RcvListPlmtFtqFullCnt; - T3_32BIT_REGISTER RcvListPlmtFtqFifoEnqueueDequeue; - T3_32BIT_REGISTER RcvListPlmtFtqFifoWritePeek; + T3_32BIT_REGISTER RcvListPlmtFtqCtrl; + T3_32BIT_REGISTER RcvListPlmtFtqFullCnt; + T3_32BIT_REGISTER RcvListPlmtFtqFifoEnqueueDequeue; + T3_32BIT_REGISTER RcvListPlmtFtqFifoWritePeek; - T3_32BIT_REGISTER RcvDataBdInitiatorFtqCtrl; - T3_32BIT_REGISTER RcvDataBdInitiatorFtqFullCnt; - T3_32BIT_REGISTER RcvDataBdInitiatorFtqFifoEnqueueDequeue; - T3_32BIT_REGISTER RcvDataBdInitiatorFtqFifoWritePeek; + T3_32BIT_REGISTER RcvDataBdInitiatorFtqCtrl; + T3_32BIT_REGISTER RcvDataBdInitiatorFtqFullCnt; + T3_32BIT_REGISTER RcvDataBdInitiatorFtqFifoEnqueueDequeue; + T3_32BIT_REGISTER RcvDataBdInitiatorFtqFifoWritePeek; - T3_32BIT_REGISTER RcvDataCompFtqCtrl; - T3_32BIT_REGISTER RcvDataCompFtqFullCnt; - T3_32BIT_REGISTER RcvDataCompFtqFifoEnqueueDequeue; - T3_32BIT_REGISTER RcvDataCompFtqFifoWritePeek; + T3_32BIT_REGISTER RcvDataCompFtqCtrl; + T3_32BIT_REGISTER RcvDataCompFtqFullCnt; + T3_32BIT_REGISTER RcvDataCompFtqFifoEnqueueDequeue; + T3_32BIT_REGISTER RcvDataCompFtqFifoWritePeek; - T3_32BIT_REGISTER SwType2FtqCtrl; - T3_32BIT_REGISTER SwType2FtqFullCnt; - T3_32BIT_REGISTER SwType2FtqFifoEnqueueDequeue; - T3_32BIT_REGISTER SwType2FtqFifoWritePeek; + T3_32BIT_REGISTER SwType2FtqCtrl; + T3_32BIT_REGISTER SwType2FtqFullCnt; + T3_32BIT_REGISTER SwType2FtqFifoEnqueueDequeue; + T3_32BIT_REGISTER SwType2FtqFifoWritePeek; - /* Unused space. */ - LM_UINT8 Unused2[736]; + /* Unused space. */ + LM_UINT8 Unused2[736]; } T3_FTQ, *PT3_FTQ; - /******************************************************************************/ /* Message signaled interrupt registers. */ /******************************************************************************/ typedef struct { - T3_32BIT_REGISTER Mode; + T3_32BIT_REGISTER Mode; #define MSI_MODE_RESET BIT_0 #define MSI_MODE_ENABLE BIT_1 - T3_32BIT_REGISTER Status; + T3_32BIT_REGISTER Status; - T3_32BIT_REGISTER MsiFifoAccess; + T3_32BIT_REGISTER MsiFifoAccess; - /* Unused space. */ - LM_UINT8 Unused[1012]; + /* Unused space. */ + LM_UINT8 Unused[1012]; } T3_MSG_SIGNALED_INT, *PT3_MSG_SIGNALED_INT; - /******************************************************************************/ /* DMA Completion registes. */ /******************************************************************************/ typedef struct { - T3_32BIT_REGISTER Mode; - #define DMA_COMP_MODE_RESET BIT_0 - #define DMA_COMP_MODE_ENABLE BIT_1 + T3_32BIT_REGISTER Mode; +#define DMA_COMP_MODE_RESET BIT_0 +#define DMA_COMP_MODE_ENABLE BIT_1 - /* Unused space. */ - LM_UINT8 Unused[1020]; + /* Unused space. */ + LM_UINT8 Unused[1020]; } T3_DMA_COMPLETION, *PT3_DMA_COMPLETION; - /******************************************************************************/ /* GRC registers. */ /******************************************************************************/ typedef struct { - /* Mode control register. */ - T3_32BIT_REGISTER Mode; - #define GRC_MODE_UPDATE_ON_COALESCING BIT_0 - #define GRC_MODE_BYTE_SWAP_NON_FRAME_DATA BIT_1 - #define GRC_MODE_WORD_SWAP_NON_FRAME_DATA BIT_2 - #define GRC_MODE_BYTE_SWAP_DATA BIT_4 - #define GRC_MODE_WORD_SWAP_DATA BIT_5 - #define GRC_MODE_SPLIT_HEADER_MODE BIT_8 - #define GRC_MODE_NO_FRAME_CRACKING BIT_9 - #define GRC_MODE_INCLUDE_CRC BIT_10 - #define GRC_MODE_ALLOW_BAD_FRAMES BIT_11 - #define GRC_MODE_NO_INTERRUPT_ON_SENDS BIT_13 - #define GRC_MODE_NO_INTERRUPT_ON_RECEIVE BIT_14 - #define GRC_MODE_FORCE_32BIT_PCI_BUS_MODE BIT_15 - #define GRC_MODE_HOST_STACK_UP BIT_16 - #define GRC_MODE_HOST_SEND_BDS BIT_17 - #define GRC_MODE_TX_NO_PSEUDO_HEADER_CHKSUM BIT_20 - #define GRC_MODE_RX_NO_PSEUDO_HEADER_CHKSUM BIT_23 - #define GRC_MODE_INT_ON_TX_CPU_ATTN BIT_24 - #define GRC_MODE_INT_ON_RX_CPU_ATTN BIT_25 - #define GRC_MODE_INT_ON_MAC_ATTN BIT_26 - #define GRC_MODE_INT_ON_DMA_ATTN BIT_27 - #define GRC_MODE_INT_ON_FLOW_ATTN BIT_28 - #define GRC_MODE_4X_NIC_BASED_SEND_RINGS BIT_29 - #define GRC_MODE_MULTICAST_FRAME_ENABLE BIT_30 + /* Mode control register. */ + T3_32BIT_REGISTER Mode; +#define GRC_MODE_UPDATE_ON_COALESCING BIT_0 +#define GRC_MODE_BYTE_SWAP_NON_FRAME_DATA BIT_1 +#define GRC_MODE_WORD_SWAP_NON_FRAME_DATA BIT_2 +#define GRC_MODE_BYTE_SWAP_DATA BIT_4 +#define GRC_MODE_WORD_SWAP_DATA BIT_5 +#define GRC_MODE_SPLIT_HEADER_MODE BIT_8 +#define GRC_MODE_NO_FRAME_CRACKING BIT_9 +#define GRC_MODE_INCLUDE_CRC BIT_10 +#define GRC_MODE_ALLOW_BAD_FRAMES BIT_11 +#define GRC_MODE_NO_INTERRUPT_ON_SENDS BIT_13 +#define GRC_MODE_NO_INTERRUPT_ON_RECEIVE BIT_14 +#define GRC_MODE_FORCE_32BIT_PCI_BUS_MODE BIT_15 +#define GRC_MODE_HOST_STACK_UP BIT_16 +#define GRC_MODE_HOST_SEND_BDS BIT_17 +#define GRC_MODE_TX_NO_PSEUDO_HEADER_CHKSUM BIT_20 +#define GRC_MODE_RX_NO_PSEUDO_HEADER_CHKSUM BIT_23 +#define GRC_MODE_INT_ON_TX_CPU_ATTN BIT_24 +#define GRC_MODE_INT_ON_RX_CPU_ATTN BIT_25 +#define GRC_MODE_INT_ON_MAC_ATTN BIT_26 +#define GRC_MODE_INT_ON_DMA_ATTN BIT_27 +#define GRC_MODE_INT_ON_FLOW_ATTN BIT_28 +#define GRC_MODE_4X_NIC_BASED_SEND_RINGS BIT_29 +#define GRC_MODE_MULTICAST_FRAME_ENABLE BIT_30 - /* Misc configuration register. */ - T3_32BIT_REGISTER MiscCfg; - #define GRC_MISC_CFG_CORE_CLOCK_RESET BIT_0 - #define GRC_MISC_PRESCALAR_TIMER_MASK 0xfe - #define GRC_MISC_BD_ID_MASK 0x0001e000 - #define GRC_MISC_BD_ID_5700 0x0001e000 - #define GRC_MISC_BD_ID_5701 0x00000000 - #define GRC_MISC_BD_ID_5703 0x00000000 - #define GRC_MISC_BD_ID_5703S 0x00002000 - #define GRC_MISC_BD_ID_5702FE 0x00004000 - #define GRC_MISC_BD_ID_5704 0x00000000 - #define GRC_MISC_BD_ID_5704CIOBE 0x00004000 + /* Misc configuration register. */ + T3_32BIT_REGISTER MiscCfg; +#define GRC_MISC_CFG_CORE_CLOCK_RESET BIT_0 +#define GRC_MISC_PRESCALAR_TIMER_MASK 0xfe +#define GRC_MISC_BD_ID_MASK 0x0001e000 +#define GRC_MISC_BD_ID_5700 0x0001e000 +#define GRC_MISC_BD_ID_5701 0x00000000 +#define GRC_MISC_BD_ID_5703 0x00000000 +#define GRC_MISC_BD_ID_5703S 0x00002000 +#define GRC_MISC_BD_ID_5702FE 0x00004000 +#define GRC_MISC_BD_ID_5704 0x00000000 +#define GRC_MISC_BD_ID_5704CIOBE 0x00004000 - /* Miscellaneous local control register. */ - T3_32BIT_REGISTER LocalCtrl; - #define GRC_MISC_LOCAL_CTRL_INT_ACTIVE BIT_0 - #define GRC_MISC_LOCAL_CTRL_CLEAR_INT BIT_1 - #define GRC_MISC_LOCAL_CTRL_SET_INT BIT_2 - #define GRC_MISC_LOCAL_CTRL_INT_ON_ATTN BIT_3 - #define GRC_MISC_LOCAL_CTRL_GPIO_INPUT0 BIT_8 - #define GRC_MISC_LOCAL_CTRL_GPIO_INPUT1 BIT_9 - #define GRC_MISC_LOCAL_CTRL_GPIO_INPUT2 BIT_10 - #define GRC_MISC_LOCAL_CTRL_GPIO_OE0 BIT_11 - #define GRC_MISC_LOCAL_CTRL_GPIO_OE1 BIT_12 - #define GRC_MISC_LOCAL_CTRL_GPIO_OE2 BIT_13 - #define GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT0 BIT_14 - #define GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT1 BIT_15 - #define GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT2 BIT_16 - #define GRC_MISC_LOCAL_CTRL_ENABLE_EXT_MEMORY BIT_17 - #define GRC_MISC_LOCAL_CTRL_BANK_SELECT BIT_21 - #define GRC_MISC_LOCAL_CTRL_SSRAM_TYPE BIT_22 + /* Miscellaneous local control register. */ + T3_32BIT_REGISTER LocalCtrl; +#define GRC_MISC_LOCAL_CTRL_INT_ACTIVE BIT_0 +#define GRC_MISC_LOCAL_CTRL_CLEAR_INT BIT_1 +#define GRC_MISC_LOCAL_CTRL_SET_INT BIT_2 +#define GRC_MISC_LOCAL_CTRL_INT_ON_ATTN BIT_3 +#define GRC_MISC_LOCAL_CTRL_GPIO_INPUT0 BIT_8 +#define GRC_MISC_LOCAL_CTRL_GPIO_INPUT1 BIT_9 +#define GRC_MISC_LOCAL_CTRL_GPIO_INPUT2 BIT_10 +#define GRC_MISC_LOCAL_CTRL_GPIO_OE0 BIT_11 +#define GRC_MISC_LOCAL_CTRL_GPIO_OE1 BIT_12 +#define GRC_MISC_LOCAL_CTRL_GPIO_OE2 BIT_13 +#define GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT0 BIT_14 +#define GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT1 BIT_15 +#define GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT2 BIT_16 +#define GRC_MISC_LOCAL_CTRL_ENABLE_EXT_MEMORY BIT_17 +#define GRC_MISC_LOCAL_CTRL_BANK_SELECT BIT_21 +#define GRC_MISC_LOCAL_CTRL_SSRAM_TYPE BIT_22 - #define GRC_MISC_MEMSIZE_256K 0 - #define GRC_MISC_MEMSIZE_512K (1 << 18) - #define GRC_MISC_MEMSIZE_1024K (2 << 18) - #define GRC_MISC_MEMSIZE_2048K (3 << 18) - #define GRC_MISC_MEMSIZE_4096K (4 << 18) - #define GRC_MISC_MEMSIZE_8192K (5 << 18) - #define GRC_MISC_MEMSIZE_16M (6 << 18) - #define GRC_MISC_LOCAL_CTRL_AUTO_SEEPROM BIT_24 +#define GRC_MISC_MEMSIZE_256K 0 +#define GRC_MISC_MEMSIZE_512K (1 << 18) +#define GRC_MISC_MEMSIZE_1024K (2 << 18) +#define GRC_MISC_MEMSIZE_2048K (3 << 18) +#define GRC_MISC_MEMSIZE_4096K (4 << 18) +#define GRC_MISC_MEMSIZE_8192K (5 << 18) +#define GRC_MISC_MEMSIZE_16M (6 << 18) +#define GRC_MISC_LOCAL_CTRL_AUTO_SEEPROM BIT_24 + T3_32BIT_REGISTER Timer; - T3_32BIT_REGISTER Timer; + T3_32BIT_REGISTER RxCpuEvent; + T3_32BIT_REGISTER RxTimerRef; + T3_32BIT_REGISTER RxCpuSemaphore; + T3_32BIT_REGISTER RemoteRxCpuAttn; - T3_32BIT_REGISTER RxCpuEvent; - T3_32BIT_REGISTER RxTimerRef; - T3_32BIT_REGISTER RxCpuSemaphore; - T3_32BIT_REGISTER RemoteRxCpuAttn; + T3_32BIT_REGISTER TxCpuEvent; + T3_32BIT_REGISTER TxTimerRef; + T3_32BIT_REGISTER TxCpuSemaphore; + T3_32BIT_REGISTER RemoteTxCpuAttn; - T3_32BIT_REGISTER TxCpuEvent; - T3_32BIT_REGISTER TxTimerRef; - T3_32BIT_REGISTER TxCpuSemaphore; - T3_32BIT_REGISTER RemoteTxCpuAttn; + T3_64BIT_REGISTER MemoryPowerUp; - T3_64BIT_REGISTER MemoryPowerUp; + T3_32BIT_REGISTER EepromAddr; +#define SEEPROM_ADDR_WRITE 0 +#define SEEPROM_ADDR_READ (1 << 31) +#define SEEPROM_ADDR_RW_MASK 0x80000000 +#define SEEPROM_ADDR_COMPLETE (1 << 30) +#define SEEPROM_ADDR_FSM_RESET (1 << 29) +#define SEEPROM_ADDR_DEV_ID(x) (x << 26) +#define SEEPROM_ADDR_DEV_ID_MASK 0x1c000000 +#define SEEPROM_ADDR_START (1 << 25) +#define SEEPROM_ADDR_CLK_PERD(x) (x << 16) +#define SEEPROM_ADDR_ADDRESS(x) (x & 0xfffc) +#define SEEPROM_ADDR_ADDRESS_MASK 0x0000ffff - T3_32BIT_REGISTER EepromAddr; - #define SEEPROM_ADDR_WRITE 0 - #define SEEPROM_ADDR_READ (1 << 31) - #define SEEPROM_ADDR_RW_MASK 0x80000000 - #define SEEPROM_ADDR_COMPLETE (1 << 30) - #define SEEPROM_ADDR_FSM_RESET (1 << 29) - #define SEEPROM_ADDR_DEV_ID(x) (x << 26) - #define SEEPROM_ADDR_DEV_ID_MASK 0x1c000000 - #define SEEPROM_ADDR_START (1 << 25) - #define SEEPROM_ADDR_CLK_PERD(x) (x << 16) - #define SEEPROM_ADDR_ADDRESS(x) (x & 0xfffc) - #define SEEPROM_ADDR_ADDRESS_MASK 0x0000ffff +#define SEEPROM_CLOCK_PERIOD 60 +#define SEEPROM_CHIP_SIZE (64 * 1024) - #define SEEPROM_CLOCK_PERIOD 60 - #define SEEPROM_CHIP_SIZE (64 * 1024) + T3_32BIT_REGISTER EepromData; + T3_32BIT_REGISTER EepromCtrl; - T3_32BIT_REGISTER EepromData; - T3_32BIT_REGISTER EepromCtrl; + T3_32BIT_REGISTER MdiCtrl; + T3_32BIT_REGISTER SepromDelay; - T3_32BIT_REGISTER MdiCtrl; - T3_32BIT_REGISTER SepromDelay; - - /* Unused space. */ - LM_UINT8 Unused[948]; + /* Unused space. */ + LM_UINT8 Unused[948]; } T3_GRC, *PT3_GRC; - /******************************************************************************/ /* NVRAM control registers. */ /******************************************************************************/ -typedef struct -{ - T3_32BIT_REGISTER Cmd; - #define NVRAM_CMD_RESET BIT_0 - #define NVRAM_CMD_DONE BIT_3 - #define NVRAM_CMD_DO_IT BIT_4 - #define NVRAM_CMD_WR BIT_5 - #define NVRAM_CMD_RD BIT_NONE - #define NVRAM_CMD_ERASE BIT_6 - #define NVRAM_CMD_FIRST BIT_7 - #define NVRAM_CMD_LAST BIT_8 +typedef struct { + T3_32BIT_REGISTER Cmd; +#define NVRAM_CMD_RESET BIT_0 +#define NVRAM_CMD_DONE BIT_3 +#define NVRAM_CMD_DO_IT BIT_4 +#define NVRAM_CMD_WR BIT_5 +#define NVRAM_CMD_RD BIT_NONE +#define NVRAM_CMD_ERASE BIT_6 +#define NVRAM_CMD_FIRST BIT_7 +#define NVRAM_CMD_LAST BIT_8 - T3_32BIT_REGISTER Status; - T3_32BIT_REGISTER WriteData; + T3_32BIT_REGISTER Status; + T3_32BIT_REGISTER WriteData; - T3_32BIT_REGISTER Addr; - #define NVRAM_ADDRESS_MASK 0xffffff + T3_32BIT_REGISTER Addr; +#define NVRAM_ADDRESS_MASK 0xffffff - T3_32BIT_REGISTER ReadData; + T3_32BIT_REGISTER ReadData; - /* Flash config 1 register. */ - T3_32BIT_REGISTER Config1; - #define FLASH_INTERFACE_ENABLE BIT_0 - #define FLASH_SSRAM_BUFFERRED_MODE BIT_1 - #define FLASH_PASS_THRU_MODE BIT_2 - #define FLASH_BIT_BANG_MODE BIT_3 - #define FLASH_COMPAT_BYPASS BIT_31 + /* Flash config 1 register. */ + T3_32BIT_REGISTER Config1; +#define FLASH_INTERFACE_ENABLE BIT_0 +#define FLASH_SSRAM_BUFFERRED_MODE BIT_1 +#define FLASH_PASS_THRU_MODE BIT_2 +#define FLASH_BIT_BANG_MODE BIT_3 +#define FLASH_COMPAT_BYPASS BIT_31 - /* Buffered flash (Atmel: AT45DB011B) specific information */ - #define BUFFERED_FLASH_PAGE_POS 9 - #define BUFFERED_FLASH_BYTE_ADDR_MASK ((1<pMemView + Offset)) - /* There could be problem access the memory window directly. For now, */ /* we have to go through the PCI configuration register. */ #define MEM_RD(pDevice, AddrName) \ @@ -3368,9 +3277,9 @@ LM_VOID LM_MemWrInd(PLM_DEVICE_BLOCK pDevice, LM_UINT32 MemAddr, #define MEM_WR_OFFSET(pDevice, Offset, Value32) \ LM_MemWrInd(pDevice, Offset, Value32) -#endif /* PCIX_TARGET_WORKAROUND */ +#endif /* PCIX_TARGET_WORKAROUND */ -#endif /* Jimmy, merging */ +#endif /* Jimmy, merging */ /* Jimmy...rest of file is new stuff! */ /******************************************************************************/ @@ -3378,14 +3287,14 @@ LM_VOID LM_MemWrInd(PLM_DEVICE_BLOCK pDevice, LM_UINT32 MemAddr, /******************************************************************************/ /* MAC register access. */ -LM_UINT32 LM_RegRdInd(PLM_DEVICE_BLOCK pDevice, LM_UINT32 Register); -LM_VOID LM_RegWrInd(PLM_DEVICE_BLOCK pDevice, LM_UINT32 Register, - LM_UINT32 Value32); +LM_UINT32 LM_RegRdInd (PLM_DEVICE_BLOCK pDevice, LM_UINT32 Register); +LM_VOID LM_RegWrInd (PLM_DEVICE_BLOCK pDevice, LM_UINT32 Register, + LM_UINT32 Value32); /* MAC memory access. */ -LM_UINT32 LM_MemRdInd(PLM_DEVICE_BLOCK pDevice, LM_UINT32 MemAddr); -LM_VOID LM_MemWrInd(PLM_DEVICE_BLOCK pDevice, LM_UINT32 MemAddr, - LM_UINT32 Value32); +LM_UINT32 LM_MemRdInd (PLM_DEVICE_BLOCK pDevice, LM_UINT32 MemAddr); +LM_VOID LM_MemWrInd (PLM_DEVICE_BLOCK pDevice, LM_UINT32 MemAddr, + LM_UINT32 Value32); #define MB_REG_WR(pDevice, OffsetName, Value32) \ ((pDevice)->UndiFix) ? \ @@ -3427,4 +3336,4 @@ LM_VOID LM_MemWrInd(PLM_DEVICE_BLOCK pDevice, LM_UINT32 MemAddr, #define MEM_WR_OFFSET(pDevice, Offset, Value32) \ LM_MemWrInd(pDevice, Offset, Value32) -#endif /* TIGON3_H */ +#endif /* TIGON3_H */ From 8e585f02f82c17cc66cd229dbf0fd3066bbbf658 Mon Sep 17 00:00:00 2001 From: TsiChung Liew Date: Mon, 18 Jun 2007 13:50:13 -0500 Subject: [PATCH 003/259] Added M5329AFEE and M5329BFEE Platforms Added board/freescale/m5329evb, cpu/mcf532x, drivers/net, drivers/serial, immap_5329.h, m5329.h, mcfrtc.h, include/configs/M5329EVB.h, lib_m68k/interrupts.c, and rtc/mcfrtc.c Modified CREDITS, MAKEFILE, Makefile, README, common/cmd_bdinfo.c, common/cmd_mii.c, include/asm-m68k/byteorder.h, include/asm-m68k/fec.h, include/asm-m68k/io.h, include/asm-m68k/mcftimer.h, include/asm-m68k/mcfuart.h, include/asm-m68k/ptrace.h, include/asm-m68k/u-boot.h, lib_m68k/Makefile, lib_m68k/board.c, lib_m68k/time.c, net/eth.c and rtc/Makefile Signed-off-by: TsiChung Liew --- CREDITS | 6 + MAKEALL | 2 +- Makefile | 14 + README | 5 + board/freescale/m5329evb/Makefile | 44 + board/freescale/m5329evb/config.mk | 25 + board/freescale/m5329evb/flash.c | 643 +++++++++ board/freescale/m5329evb/m5329evb.c | 376 +++++ board/freescale/m5329evb/u-boot.lds | 144 ++ common/cmd_bdinfo.c | 53 + common/cmd_mii.c | 2 +- cpu/mcf532x/Makefile | 48 + cpu/mcf532x/config.mk | 27 + cpu/mcf532x/cpu.c | 134 ++ cpu/mcf532x/cpu_init.c | 126 ++ cpu/mcf532x/speed.c | 222 +++ cpu/mcf532x/start.S | 338 +++++ drivers/net/Makefile | 45 + drivers/net/mcffec.c | 594 ++++++++ drivers/serial/Makefile | 45 + drivers/serial/mcfserial.c | 126 ++ include/asm-m68k/byteorder.h | 102 +- include/asm-m68k/fec.h | 241 +++- include/asm-m68k/immap_5329.h | 793 +++++++++++ include/asm-m68k/io.h | 214 ++- include/asm-m68k/m5329.h | 2023 +++++++++++++++++++++++++++ include/asm-m68k/mcfrtc.h | 108 ++ include/asm-m68k/mcftimer.h | 144 +- include/asm-m68k/mcfuart.h | 324 +++-- include/asm-m68k/ptrace.h | 44 +- include/asm-m68k/u-boot.h | 48 +- include/configs/M5329EVB.h | 275 ++++ lib_m68k/Makefile | 2 +- lib_m68k/board.c | 67 +- lib_m68k/interrupts.c | 118 ++ lib_m68k/time.c | 167 ++- net/eth.c | 1 + rtc/Makefile | 3 +- rtc/mcfrtc.c | 120 ++ 39 files changed, 7627 insertions(+), 186 deletions(-) mode change 100755 => 100644 MAKEALL mode change 100644 => 100755 Makefile create mode 100644 board/freescale/m5329evb/Makefile create mode 100644 board/freescale/m5329evb/config.mk create mode 100644 board/freescale/m5329evb/flash.c create mode 100644 board/freescale/m5329evb/m5329evb.c create mode 100644 board/freescale/m5329evb/u-boot.lds create mode 100644 cpu/mcf532x/Makefile create mode 100644 cpu/mcf532x/config.mk create mode 100644 cpu/mcf532x/cpu.c create mode 100644 cpu/mcf532x/cpu_init.c create mode 100644 cpu/mcf532x/speed.c create mode 100644 cpu/mcf532x/start.S create mode 100644 drivers/net/Makefile create mode 100644 drivers/net/mcffec.c create mode 100644 drivers/serial/Makefile create mode 100644 drivers/serial/mcfserial.c create mode 100644 include/asm-m68k/immap_5329.h create mode 100644 include/asm-m68k/m5329.h create mode 100644 include/asm-m68k/mcfrtc.h create mode 100644 include/configs/M5329EVB.h create mode 100644 lib_m68k/interrupts.c create mode 100644 rtc/mcfrtc.c diff --git a/CREDITS b/CREDITS index 7af1b806a..8558a4012 100644 --- a/CREDITS +++ b/CREDITS @@ -479,3 +479,9 @@ N: Michal Simek E: monstr@monstr.eu D: Support for Microblaze, ML401, XUPV2P board W: www.monstr.eu + +N: TsiChung Liew +E: Tsi-Chung.Liew@freescale.com +D: Support for ColdFire MCF532x +W: www.freescale.com + diff --git a/MAKEALL b/MAKEALL old mode 100755 new mode 100644 index 0e4e74409..22c6c6da2 --- a/MAKEALL +++ b/MAKEALL @@ -306,7 +306,7 @@ LIST_microblaze=" \ LIST_coldfire=" \ cobra5272 EB+MCF-EV123 EB+MCF-EV123_internal \ idmr M5271EVB M5272C3 M5282EVB \ - TASREG r5200 M5271EVB \ + TASREG r5200 M5271EVB M5329EVB \ " ######################################################################### diff --git a/Makefile b/Makefile old mode 100644 new mode 100755 index d5e220aad..8a728a432 --- a/Makefile +++ b/Makefile @@ -207,9 +207,11 @@ LIBS += dtt/libdtt.a LIBS += drivers/libdrivers.a LIBS += drivers/nand/libnand.a LIBS += drivers/nand_legacy/libnand_legacy.a +LIBS += drivers/net/libnet.a ifeq ($(CPU),mpc83xx) LIBS += drivers/qe/qe.a endif +LIBS += drivers/serial/libserial.a LIBS += drivers/sk98lin/libsk98lin.a LIBS += post/libpost.a post/drivers/libpostdrivers.a LIBS += $(shell if [ -d post/lib_$(ARCH) ]; then echo \ @@ -1637,6 +1639,18 @@ TASREG_config : unconfig r5200_config : unconfig @$(MKCONFIG) $(@:_config=) m68k mcf52x2 r5200 +M5329AFEE_config \ +M5329BFEE_config : unconfig + @case "$@" in \ + M5329AFEE_config) NAND=0;; \ + M5329BFEE_config) NAND=16;; \ + esac; \ + >include/config.h ; \ + if [ "$${NAND}" != "0" ] ; then \ + echo "#define NANDFLASH_SIZE $${NAND}" >> include/config.h ; \ + fi + @$(MKCONFIG) -a M5329EVB m68k mcf532x m5329evb freescale + ######################################################################### ## MPC83xx Systems ######################################################################### diff --git a/README b/README index bb5b46e33..dd12cd7ee 100644 --- a/README +++ b/README @@ -136,6 +136,7 @@ Directory Hierarchy: - i386 Files specific to i386 CPUs - ixp Files specific to Intel XScale IXP CPUs - mcf52x2 Files specific to Freescale ColdFire MCF52x2 CPUs + - mcf532x Files specific to Freescale ColdFire MCF5329 CPUs - mips Files specific to MIPS CPUs - mpc5xx Files specific to Freescale MPC5xx CPUs - mpc5xxx Files specific to Freescale MPC5xxx CPUs @@ -251,6 +252,10 @@ The following options need to be configured: CONFIG_PXA250 CONFIG_CPU_MONAHANS + ColdFire based CPUs: + -------------------- + CONFIG_M5329 + MicroBlaze based CPUs: ---------------------- CONFIG_MICROBLAZE diff --git a/board/freescale/m5329evb/Makefile b/board/freescale/m5329evb/Makefile new file mode 100644 index 000000000..f94ee9d13 --- /dev/null +++ b/board/freescale/m5329evb/Makefile @@ -0,0 +1,44 @@ +# +# (C) Copyright 2000-2003 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS = $(BOARD).o flash.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/freescale/m5329evb/config.mk b/board/freescale/m5329evb/config.mk new file mode 100644 index 000000000..ce014edca --- /dev/null +++ b/board/freescale/m5329evb/config.mk @@ -0,0 +1,25 @@ +# +# (C) Copyright 2000-2003 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# Coldfire contribution by Bernhard Kuhn +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +TEXT_BASE = 0 diff --git a/board/freescale/m5329evb/flash.c b/board/freescale/m5329evb/flash.c new file mode 100644 index 000000000..7d3b0e84d --- /dev/null +++ b/board/freescale/m5329evb/flash.c @@ -0,0 +1,643 @@ +/* + * (C) Copyright 2000-2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +#ifndef CFG_FLASH_CFI + +typedef unsigned short FLASH_PORT_WIDTH; +typedef volatile unsigned short FLASH_PORT_WIDTHV; + +#define PHYS_FLASH_1 CFG_FLASH_BASE +#define FLASH_BANK_SIZE 0x200000 + +#define FPW FLASH_PORT_WIDTH +#define FPWV FLASH_PORT_WIDTHV + +/* Intel-compatible flash commands */ +#define INTEL_PROGRAM 0x00100010 +#define INTEL_ERASE 0x00200020 +#define INTEL_WRSETUP 0x00400040 +#define INTEL_CLEAR 0x00500050 +#define INTEL_LOCKBIT 0x00600060 +#define INTEL_PROTECT 0x00010001 +#define INTEL_STATUS 0x00700070 +#define INTEL_READID 0x00900090 +#define INTEL_CFIQRY 0x00980098 +#define INTEL_SUSERASE 0x00B000B0 +#define INTEL_PROTPROG 0x00C000C0 +#define INTEL_CONFIRM 0x00D000D0 +#define INTEL_RESET 0x00FF00FF + +/* Intel-compatible flash status bits */ +#define INTEL_FINISHED 0x00800080 +#define INTEL_OK 0x00800080 +#define INTEL_ERASESUS 0x00600060 +#define INTEL_WSM_SUS (INTEL_FINISHED | INTEL_ERASESUS) + +/* 28F160C3B CFI Data offset - This could vary */ +#define INTEL_CFI_MFG 0x00 /* Manufacturer ID */ +#define INTEL_CFI_PART 0x01 /* Product ID */ +#define INTEL_CFI_LOCK 0x02 /* */ +#define INTEL_CFI_TWPRG 0x1F /* Typical Single Word Program Timeout 2^n us */ +#define INTEL_CFI_MBUFW 0x20 /* Typical Max Buffer Write Timeout 2^n us */ +#define INTEL_CFI_TERB 0x21 /* Typical Block Erase Timeout 2^n ms */ +#define INTEL_CFI_MWPRG 0x23 /* Maximum Word program timeout 2^n us */ +#define INTEL_CFI_MERB 0x25 /* Maximum Block Erase Timeout 2^n s */ +#define INTEL_CFI_SIZE 0x27 /* Device size 2^n bytes */ +#define INTEL_CFI_BANK 0x2C /* Number of Bank */ +#define INTEL_CFI_SZ1A 0x2F /* Block Region Size */ +#define INTEL_CFI_SZ1B 0x30 +#define INTEL_CFI_SZ2A 0x33 +#define INTEL_CFI_SZ2B 0x34 +#define INTEL_CFI_BLK1 0x2D /* Number of Blocks */ +#define INTEL_CFI_BLK2 0x31 + +#define WR_BLOCK 0x20 + +#define SYNC __asm__("nop") + +/*----------------------------------------------------------------------- + * Functions + */ + +ulong flash_get_size(FPWV * addr, flash_info_t * info); +int flash_get_offsets(ulong base, flash_info_t * info); +int flash_cmd_rd(FPWV * addr, int index); +int write_data(flash_info_t * info, ulong dest, FPW data); +void flash_sync_real_protect(flash_info_t * info); +uchar intel_sector_protected(flash_info_t * info, ushort sector); + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; + +ulong flash_init(void) +{ + FPWV *flash_addr[CFG_MAX_FLASH_BANKS]; + ulong size; + int i; + + flash_addr[0] = (FPW *) CFG_FLASH0_BASE; +#ifdef CFG_FLASH1_BASE + flash_addr[1] = (FPW *) CFG_FLASH1_BASE; +#endif + + for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) { + memset(&flash_info[i], 0, sizeof(flash_info_t)); + + size = flash_get_size(flash_addr[i], &flash_info[i]); + flash_protect(FLAG_PROTECT_CLEAR, + flash_info[i].start[0], + flash_info[i].start[0] + size - 1, + &flash_info[0]); + /* get the h/w and s/w protection status in sync */ + flash_sync_real_protect(&flash_info[i]); + } + + /* Protect monitor and environment sectors */ + flash_protect(FLAG_PROTECT_SET, + CFG_MONITOR_BASE, + CFG_MONITOR_BASE + monitor_flash_len - 1, &flash_info[0]); + + return size; +} + +void flash_print_info(flash_info_t * info) +{ + int i; + + switch (info->flash_id & FLASH_VENDMASK) { + case FLASH_MAN_INTEL: + printf("INTEL "); + break; + default: + printf("Unknown Vendor "); + break; + } + + switch (info->flash_id & FLASH_TYPEMASK) { + case FLASH_28F160C3B: + printf("28F160C3B\n"); + break; + case FLASH_28F160C3T: + printf("28F160C3T\n"); + break; + case FLASH_28F320C3B: + printf("28F320C3B\n"); + break; + case FLASH_28F320C3T: + printf("28F320C3T\n"); + break; + case FLASH_28F640C3B: + printf("28F640C3B\n"); + break; + case FLASH_28F640C3T: + printf("28F640C3T\n"); + break; + default: + printf("Unknown Chip Type\n"); + return; + } + + if (info->size > 0x100000) { + int remainder; + + printf(" Size: %ld", info->size >> 20); + + remainder = (info->size % 0x100000); + if (remainder) { + remainder >>= 10; + remainder = (int)((float) + (((float)remainder / (float)1024) * + 10000)); + printf(".%d ", remainder); + } + + printf("MB in %d Sectors\n", info->sector_count); + } else + printf(" Size: %ld KB in %d Sectors\n", + info->size >> 10, info->sector_count); + + printf(" Sector Start Addresses:"); + for (i = 0; i < info->sector_count; ++i) { + if ((i % 5) == 0) + printf("\n "); + printf(" %08lX%s", + info->start[i], info->protect[i] ? " (RO)" : " "); + } + printf("\n"); +} + +/* + * The following code cannot be run from FLASH! + */ +ulong flash_get_size(FPWV * addr, flash_info_t * info) +{ + int intel = 0; + u16 value; + static int bank = 0; + + /* Write auto select command: read Manufacturer ID */ + /* Write auto select command sequence and test FLASH answer */ + *addr = (FPW) INTEL_RESET; /* restore read mode */ + *addr = (FPW) INTEL_READID; + + switch (addr[INTEL_CFI_MFG] & 0xff) { + case (ushort) INTEL_MANUFACT: + info->flash_id = FLASH_MAN_INTEL; + value = addr[INTEL_CFI_PART]; + intel = 1; + break; + default: + printf("Unknown Flash\n"); + info->flash_id = FLASH_UNKNOWN; + info->sector_count = 0; + info->size = 0; + *addr = (FPW) INTEL_RESET; /* restore read mode */ + return (0); /* no or unknown flash */ + } + + switch (value) { + case (u16) INTEL_ID_28F160C3B: + info->flash_id += FLASH_28F160C3B; + break; + case (u16) INTEL_ID_28F160C3T: + info->flash_id += FLASH_28F160C3T; + break; + case (u16) INTEL_ID_28F320C3B: + info->flash_id += FLASH_28F320C3B; + break; + case (u16) INTEL_ID_28F320C3T: + info->flash_id += FLASH_28F320C3T; + break; + case (u16) INTEL_ID_28F640C3B: + info->flash_id += FLASH_28F640C3B; + break; + case (u16) INTEL_ID_28F640C3T: + info->flash_id += FLASH_28F640C3T; + break; + default: + info->flash_id = FLASH_UNKNOWN; + break; + } + + if (intel) { + /* Intel spec. under CFI section */ + u32 sz, size, offset; + int sec, sectors, bs; + int part, i, j, cnt; + + part = flash_cmd_rd(addr, INTEL_CFI_BANK); + + /* Geometry y1 = y1 + 1, y2 = y2 + 1, CFI spec. + * To be exact, Z = [0x2f 0x30] (LE) * 256 bytes * [0x2D 0x2E] block count + * Z = [0x33 0x34] (LE) * 256 bytes * [0x31 0x32] block count + */ + offset = (u32) addr; + sectors = sec = 0; + size = sz = cnt = 0; + for (i = 0; i < part; i++) { + bs = (((addr[INTEL_CFI_SZ1B + i * 4] << 8) | + addr[INTEL_CFI_SZ1A + i * 4]) * 0x100); + sec = addr[INTEL_CFI_BLK1 + i * 4] + 1; + sz = bs * sec; + + for (j = 0; j < sec; j++) { + info->start[cnt++] = offset; + offset += bs; + } + + sectors += sec; + size += sz; + } + info->sector_count = sectors; + info->size = size; + } + + if (info->sector_count > CFG_MAX_FLASH_SECT) { + printf("** ERROR: sector count %d > max (%d) **\n", + info->sector_count, CFG_MAX_FLASH_SECT); + info->sector_count = CFG_MAX_FLASH_SECT; + } + + *addr = (FPW) INTEL_RESET; /* restore read mode */ + + return (info->size); +} + +int flash_cmd_rd(FPWV * addr, int index) +{ + return (int)addr[index]; +} + +/* + * This function gets the u-boot flash sector protection status + * (flash_info_t.protect[]) in sync with the sector protection + * status stored in hardware. + */ +void flash_sync_real_protect(flash_info_t * info) +{ + int i; + + switch (info->flash_id & FLASH_TYPEMASK) { + case FLASH_28F160C3B: + case FLASH_28F160C3T: + case FLASH_28F320C3B: + case FLASH_28F320C3T: + case FLASH_28F640C3B: + case FLASH_28F640C3T: + for (i = 0; i < info->sector_count; ++i) { + info->protect[i] = intel_sector_protected(info, i); + } + break; + default: + /* no h/w protect support */ + break; + } +} + +/* + * checks if "sector" in bank "info" is protected. Should work on intel + * strata flash chips 28FxxxJ3x in 8-bit mode. + * Returns 1 if sector is protected (or timed-out while trying to read + * protection status), 0 if it is not. + */ +uchar intel_sector_protected(flash_info_t * info, ushort sector) +{ + FPWV *addr; + FPWV *lock_conf_addr; + ulong start; + unsigned char ret; + + /* + * first, wait for the WSM to be finished. The rationale for + * waiting for the WSM to become idle for at most + * CFG_FLASH_ERASE_TOUT is as follows. The WSM can be busy + * because of: (1) erase, (2) program or (3) lock bit + * configuration. So we just wait for the longest timeout of + * the (1)-(3), i.e. the erase timeout. + */ + + /* wait at least 35ns (W12) before issuing Read Status Register */ + /*udelay(1); */ + addr = (FPWV *) info->start[sector]; + *addr = (FPW) INTEL_STATUS; + + start = get_timer(0); + while ((*addr & (FPW) INTEL_FINISHED) != (FPW) INTEL_FINISHED) { + if (get_timer(start) > CFG_FLASH_UNLOCK_TOUT) { + *addr = (FPW) INTEL_RESET; /* restore read mode */ + printf("WSM busy too long, can't get prot status\n"); + return 1; + } + } + + /* issue the Read Identifier Codes command */ + *addr = (FPW) INTEL_READID; + + /* Intel example code uses offset of 4 for 8-bit flash */ + lock_conf_addr = (FPWV *) info->start[sector]; + ret = (lock_conf_addr[INTEL_CFI_LOCK] & (FPW) INTEL_PROTECT) ? 1 : 0; + + /* put flash back in read mode */ + *addr = (FPW) INTEL_RESET; + + return ret; +} + +int flash_erase(flash_info_t * info, int s_first, int s_last) +{ + int flag, prot, sect; + ulong type, start, last; + int rcode = 0; + + if ((s_first < 0) || (s_first > s_last)) { + if (info->flash_id == FLASH_UNKNOWN) + printf("- missing\n"); + else + printf("- no sectors to erase\n"); + return 1; + } + + type = (info->flash_id & FLASH_VENDMASK); + if ((type != FLASH_MAN_INTEL)) { + type = (info->flash_id & FLASH_VENDMASK); + printf("Can't erase unknown flash type %08lx - aborted\n", + info->flash_id); + return 1; + } + + prot = 0; + for (sect = s_first; sect <= s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + + if (prot) + printf("- Warning: %d protected sectors will not be erased!\n", + prot); + else + printf("\n"); + + start = get_timer(0); + last = start; + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + /* Start erase on unprotected sectors */ + for (sect = s_first; sect <= s_last; sect++) { + if (info->protect[sect] == 0) { /* not protected */ + + FPWV *addr = (FPWV *) (info->start[sect]); + int min = 0; + + printf("Erasing sector %2d ... ", sect); + + /* arm simple, non interrupt dependent timer */ + start = get_timer(0); + + *addr = (FPW) INTEL_READID; + min = addr[INTEL_CFI_TERB]; + min = 1 << min; /* ms */ + min = (min / info->sector_count) * 1000; + + /* start erase block */ + *addr = (FPW) INTEL_CLEAR; /* clear status register */ + *addr = (FPW) INTEL_ERASE; /* erase setup */ + *addr = (FPW) INTEL_CONFIRM; /* erase confirm */ + + while ((*addr & (FPW) INTEL_FINISHED) != + (FPW) INTEL_FINISHED) { + + if (get_timer(start) > CFG_FLASH_ERASE_TOUT) { + printf("Timeout\n"); + *addr = (FPW) INTEL_SUSERASE; /* suspend erase */ + *addr = (FPW) INTEL_RESET; /* reset to read mode */ + + rcode = 1; + break; + } + } + + *addr = (FPW) INTEL_RESET; /* resest to read mode */ + + printf(" done\n"); + } + } + + return rcode; +} + +int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt) +{ + if (info->flash_id == FLASH_UNKNOWN) + return 4; + + switch (info->flash_id & FLASH_VENDMASK) { + case FLASH_MAN_INTEL: + { + ulong cp, wp; + FPW data; + int i, l, rc, port_width; + + /* get lower word aligned address */ + wp = addr; + port_width = 1; + + /* + * handle unaligned start bytes + */ + if ((l = addr - wp) != 0) { + data = 0; + for (i = 0, cp = wp; i < l; ++i, ++cp) { + data = (data << 8) | (*(uchar *) cp); + } + + for (; i < port_width && cnt > 0; ++i) { + data = (data << 8) | *src++; + --cnt; + ++cp; + } + + for (; cnt == 0 && i < port_width; ++i, ++cp) + data = (data << 8) | (*(uchar *) cp); + + if ((rc = write_data(info, wp, data)) != 0) + return (rc); + + wp += port_width; + } + + /* handle word aligned part */ + while (cnt >= 2) { + data = *((FPW *) src); + + if ((rc = + write_data(info, (ulong) ((FPWV *) wp), + (FPW) data)) != 0) { + return (rc); + } + + src += sizeof(FPW); + wp += sizeof(FPW); + cnt -= sizeof(FPW); + } + + if (cnt == 0) + return ERR_OK; + + /* + * handle unaligned tail bytes + */ + data = 0; + for (i = 0, cp = wp; i < 2 && cnt > 0; ++i, ++cp) { + data = (data >> 8) | (*src++ << 8); + --cnt; + } + for (; i < 2; ++i, ++cp) { + data |= (*(uchar *) cp); + } + + return write_data(info, (ulong) ((FPWV *) wp), + (FPW) data); + + } /* case FLASH_MAN_INTEL */ + + } /* switch */ + + return ERR_OK; +} + +/*----------------------------------------------------------------------- + * Write a word or halfword to Flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +int write_data(flash_info_t * info, ulong dest, FPW data) +{ + FPWV *addr = (FPWV *) dest; + ulong start; + int flag; + + /* Check if Flash is (sufficiently) erased */ + if ((*addr & data) != data) { + printf("not erased at %08lx (%lx)\n", (ulong) addr, + (ulong) * addr); + return (2); + } + + /* Disable interrupts which might cause a timeout here */ + flag = (int)disable_interrupts(); + + *addr = (FPW) INTEL_CLEAR; + *addr = (FPW) INTEL_RESET; + + *addr = (FPW) INTEL_WRSETUP; /* write setup */ + *addr = data; + + /* arm simple, non interrupt dependent timer */ + start = get_timer(0); + + /* wait while polling the status register */ + while ((*addr & (FPW) INTEL_OK) != (FPW) INTEL_OK) { + if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + *addr = (FPW) INTEL_SUSERASE; /* suspend mode */ + *addr = (FPW) INTEL_CLEAR; /* clear status */ + *addr = (FPW) INTEL_RESET; /* reset */ + return (1); + } + } + + *addr = (FPW) INTEL_CLEAR; /* clear status */ + *addr = (FPW) INTEL_RESET; /* restore read mode */ + + return (0); +} + +#ifdef CFG_FLASH_PROTECTION +/*----------------------------------------------------------------------- + */ +int flash_real_protect(flash_info_t * info, long sector, int prot) +{ + int rcode = 0; /* assume success */ + FPWV *addr; /* address of sector */ + FPW value; + + addr = (FPWV *) (info->start[sector]); + + switch (info->flash_id & FLASH_TYPEMASK) { + case FLASH_28F160C3B: + case FLASH_28F160C3T: + case FLASH_28F320C3B: + case FLASH_28F320C3T: + case FLASH_28F640C3B: + case FLASH_28F640C3T: + *addr = (FPW) INTEL_RESET; /* make sure in read mode */ + *addr = (FPW) INTEL_LOCKBIT; /* lock command setup */ + + if (prot) + *addr = (FPW) INTEL_PROTECT; /* lock sector */ + else + *addr = (FPW) INTEL_CONFIRM; /* unlock sector */ + + /* now see if it really is locked/unlocked as requested */ + *addr = (FPW) INTEL_READID; + + /* read sector protection at sector address, (A7 .. A0) = 0x02. + * D0 = 1 for each device if protected. + * If at least one device is protected the sector is marked + * protected, but return failure. Mixed protected and + * unprotected devices within a sector should never happen. + */ + value = addr[2] & (FPW) INTEL_PROTECT; + if (value == 0) + info->protect[sector] = 0; + else if (value == (FPW) INTEL_PROTECT) + info->protect[sector] = 1; + else { + /* error, mixed protected and unprotected */ + rcode = 1; + info->protect[sector] = 1; + } + if (info->protect[sector] != prot) + rcode = 1; /* failed to protect/unprotect as requested */ + + /* reload all protection bits from hardware for now */ + flash_sync_real_protect(info); + break; + + default: + /* no hardware protect that we support */ + info->protect[sector] = prot; + break; + } + + return rcode; +} +#endif /* CFG_FLASH_PROTECTION */ +#endif /* CFG_FLASH_CFI */ diff --git a/board/freescale/m5329evb/m5329evb.c b/board/freescale/m5329evb/m5329evb.c new file mode 100644 index 000000000..4ccea30d6 --- /dev/null +++ b/board/freescale/m5329evb/m5329evb.c @@ -0,0 +1,376 @@ +/* + * (C) Copyright 2000-2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include + +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +int checkboard(void) +{ + puts("Board: "); + puts("Freescale FireEngine 5329 EVB\n"); + return 0; +}; + +long int initdram(int board_type) +{ + volatile sdram_t *sdram = (volatile sdram_t *)(MMAP_SDRAM); + u32 dramsize, i; + + dramsize = CFG_SDRAM_SIZE * 0x100000; + + for (i = 0x13; i < 0x20; i++) { + if (dramsize == (1 << i)) + break; + } + i--; + + sdram->cs0 = (CFG_SDRAM_BASE | i); + sdram->cfg1 = CFG_SDRAM_CFG1; + sdram->cfg2 = CFG_SDRAM_CFG2; + + /* Issue PALL */ + sdram->ctrl = CFG_SDRAM_CTRL | 2; + + /* Issue LEMR */ + sdram->mode = CFG_SDRAM_EMOD; + sdram->mode = (CFG_SDRAM_MODE | 0x04000000); + + udelay(500); + + /* Issue PALL */ + sdram->ctrl = (CFG_SDRAM_CTRL | 2); + + /* Perform two refresh cycles */ + sdram->ctrl = CFG_SDRAM_CTRL | 4; + sdram->ctrl = CFG_SDRAM_CTRL | 4; + + sdram->mode = CFG_SDRAM_MODE; + + sdram->ctrl = (CFG_SDRAM_CTRL & ~0x80000000) | 0x10000c00; + + udelay(100); + + return dramsize; +}; + +int testdram(void) +{ + /* TODO: XXX XXX XXX */ + printf("DRAM test not implemented!\n"); + + return (0); +} + +#ifdef CFG_FLASH_CFI +void sync(void) +{ + /* This sync function is PowerPC intruction, + coldfire does not have this instruction. Dummy function */ +} +#endif + +#if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(CONFIG_NET_MULTI) +#undef MII_DEBUG +#undef ET_DEBUG + +int fecpin_setclear(struct eth_device *dev, int setclear) +{ + volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; + + if (setclear) { + gpio->par_fec |= GPIO_PAR_FEC_7W_FEC | GPIO_PAR_FEC_MII_FEC; + gpio->par_feci2c |= + GPIO_PAR_FECI2C_MDC_EMDC | GPIO_PAR_FECI2C_MDIO_EMDIO; + } else { + gpio->par_fec &= ~(GPIO_PAR_FEC_7W_FEC | GPIO_PAR_FEC_MII_FEC); + gpio->par_feci2c &= + ~(GPIO_PAR_FECI2C_MDC_EMDC | GPIO_PAR_FECI2C_MDIO_EMDIO); + } + return 0; +} + +#if defined(CFG_DISCOVER_PHY) || (CONFIG_COMMANDS & CFG_CMD_MII) +#include + +/* Make MII read/write commands for the FEC. */ +#define mk_mii_read(ADDR, REG) (0x60020000 | ((ADDR << 23) | \ + (REG & 0x1f) << 18)) + +#define mk_mii_write(ADDR, REG, VAL) (0x50020000 | ((ADDR << 23) | \ + (REG & 0x1f) << 18) | \ + (VAL & 0xffff)) + +/* PHY identification */ +#define PHY_ID_LXT970 0x78100000 /* LXT970 */ +#define PHY_ID_LXT971 0x001378e0 /* LXT971 and 972 */ +#define PHY_ID_82555 0x02a80150 /* Intel 82555 */ +#define PHY_ID_QS6612 0x01814400 /* QS6612 */ +#define PHY_ID_AMD79C784 0x00225610 /* AMD 79C784 */ +#define PHY_ID_LSI80225 0x0016f870 /* LSI 80225 */ +#define PHY_ID_LSI80225B 0x0016f880 /* LSI 80225/B */ +#define PHY_ID_DP83848VV 0x20005C90 /* National 83848 */ +#define PHY_ID_DP83849 0x20005CA2 /* National 82849 */ + +#define STR_ID_LXT970 "LXT970" +#define STR_ID_LXT971 "LXT971" +#define STR_ID_82555 "Intel82555" +#define STR_ID_QS6612 "QS6612" +#define STR_ID_AMD79C784 "AMD79C784" +#define STR_ID_LSI80225 "LSI80225" +#define STR_ID_LSI80225B "LSI80225/B" +#define STR_ID_DP83848VV "N83848" +#define STR_ID_DP83849 "N83849" + +/**************************************************************************** + * mii_init -- Initialize the MII for MII command without ethernet + * This function is a subset of eth_init + **************************************************************************** + */ +void mii_reset(struct fec_info_s *info) +{ + volatile fec_t *fecp = (fec_t *) (info->miibase); + int i; + + fecp->ecr = FEC_ECR_RESET; + for (i = 0; (fecp->ecr & FEC_ECR_RESET) && (i < FEC_RESET_DELAY); ++i) { + udelay(1); + } + if (i == FEC_RESET_DELAY) { + printf("FEC_RESET_DELAY timeout\n"); + } +} + +/* send command to phy using mii, wait for result */ +uint mii_send(uint mii_cmd) +{ + struct fec_info_s *info; + struct eth_device *dev; + volatile fec_t *ep; + uint mii_reply; + int j = 0; + + /* retrieve from register structure */ + dev = eth_get_dev(); + info = dev->priv; + + ep = (fec_t *) info->miibase; + + ep->mmfr = mii_cmd; /* command to phy */ + + /* wait for mii complete */ + while (!(ep->eir & FEC_EIR_MII) && (j < MCFFEC_TOUT_LOOP)) { + udelay(1); + j++; + } + if (j >= MCFFEC_TOUT_LOOP) { + printf("MII not complete\n"); + return -1; + } + + mii_reply = ep->mmfr; /* result from phy */ + ep->eir = FEC_EIR_MII; /* clear MII complete */ +#ifdef ET_DEBUG + printf("%s[%d] %s: sent=0x%8.8x, reply=0x%8.8x\n", + __FILE__, __LINE__, __FUNCTION__, mii_cmd, mii_reply); +#endif + + return (mii_reply & 0xffff); /* data read from phy */ +} +#endif /* CFG_DISCOVER_PHY || (CONFIG_COMMANDS & CFG_CMD_MII) */ + +#if defined(CFG_DISCOVER_PHY) +int mii_discover_phy(struct eth_device *dev) +{ +#define MAX_PHY_PASSES 11 + struct fec_info_s *info = dev->priv; + int phyaddr, pass; + uint phyno, phytype; + + if (info->phyname_init) + return info->phy_addr; + + phyaddr = -1; /* didn't find a PHY yet */ + for (pass = 1; pass <= MAX_PHY_PASSES && phyaddr < 0; ++pass) { + if (pass > 1) { + /* PHY may need more time to recover from reset. + * The LXT970 needs 50ms typical, no maximum is + * specified, so wait 10ms before try again. + * With 11 passes this gives it 100ms to wake up. + */ + udelay(10000); /* wait 10ms */ + } + + for (phyno = 0; phyno < 32 && phyaddr < 0; ++phyno) { + + phytype = mii_send(mk_mii_read(phyno, PHY_PHYIDR1)); +#ifdef ET_DEBUG + printf("PHY type 0x%x pass %d type\n", phytype, pass); +#endif + if (phytype != 0xffff) { + phyaddr = phyno; + phytype <<= 16; + phytype |= + mii_send(mk_mii_read(phyno, PHY_PHYIDR2)); + + switch (phytype & 0xffffffff) { + case PHY_ID_DP83848VV: + strcpy(info->phy_name, + STR_ID_DP83848VV); + info->phyname_init = 1; + break; + default: + strcpy(info->phy_name, "unknown"); + info->phyname_init = 1; + break; + } + +#ifdef ET_DEBUG + printf("PHY @ 0x%x pass %d type ", phyno, pass); + switch (phytype & 0xffffffff) { + case PHY_ID_DP83848VV: + printf(STR_ID_DP83848VV); + break; + default: + printf("0x%08x\n", phytype); + break; + } +#endif + } + } + } + if (phyaddr < 0) + printf("No PHY device found.\n"); + + return phyaddr; +} +#endif /* CFG_DISCOVER_PHY */ + +void mii_init(void) +{ + volatile fec_t *fecp; + struct fec_info_s *info; + struct eth_device *dev; + int miispd = 0, i = 0; + u16 autoneg = 0; + + /* retrieve from register structure */ + dev = eth_get_dev(); + info = dev->priv; + + fecp = (fec_t *) info->miibase; + + fecpin_setclear(dev, 1); + + mii_reset(info); + + /* We use strictly polling mode only */ + fecp->eimr = 0; + + /* Clear any pending interrupt */ + fecp->eir = 0xffffffff; + + /* Set MII speed */ + miispd = (gd->bus_clk / 1000000) / 5; + fecp->mscr = miispd << 1; + + info->phy_addr = mii_discover_phy(dev); + +#define AUTONEGLINK (PHY_BMSR_AUTN_COMP | PHY_BMSR_LS) + while (i < MCFFEC_TOUT_LOOP) { + autoneg = 0; + miiphy_read(dev->name, info->phy_addr, PHY_BMSR, &autoneg); + i++; + + if ((autoneg & AUTONEGLINK) == AUTONEGLINK) + break; + + udelay(500); + } + if (i >= MCFFEC_TOUT_LOOP) { + printf("Auto Negotiation not complete\n"); + } + + /* adapt to the half/full speed settings */ + info->dup_spd = miiphy_duplex(dev->name, info->phy_addr) << 16; + info->dup_spd |= miiphy_speed(dev->name, info->phy_addr); +} + +/***************************************************************************** + * Read and write a MII PHY register, routines used by MII Utilities + * + * FIXME: These routines are expected to return 0 on success, but mii_send + * does _not_ return an error code. Maybe 0xFFFF means error, i.e. + * no PHY connected... + * For now always return 0. + * FIXME: These routines only work after calling eth_init() at least once! + * Otherwise they hang in mii_send() !!! Sorry! + *****************************************************************************/ + +int mcffec_miiphy_read(char *devname, unsigned char addr, + unsigned char reg, unsigned short *value) +{ + short rdreg; /* register working value */ + +#ifdef MII_DEBUG + printf("miiphy_read(0x%x) @ 0x%x = ", reg, addr); +#endif + rdreg = mii_send(mk_mii_read(addr, reg)); + + *value = rdreg; + +#ifdef MII_DEBUG + printf("0x%04x\n", *value); +#endif + + return 0; +} + +int mcffec_miiphy_write(char *devname, unsigned char addr, + unsigned char reg, unsigned short value) +{ + short rdreg; /* register working value */ + +#ifdef MII_DEBUG + printf("miiphy_write(0x%x) @ 0x%x = ", reg, addr); +#endif + + rdreg = mii_send(mk_mii_write(addr, reg, value)); + +#ifdef MII_DEBUG + printf("0x%04x\n", value); +#endif + + return 0; +} + +#endif /* CFG_CMD_NET, FEC_ENET & NET_MULTI */ diff --git a/board/freescale/m5329evb/u-boot.lds b/board/freescale/m5329evb/u-boot.lds new file mode 100644 index 000000000..9b994a09d --- /dev/null +++ b/board/freescale/m5329evb/u-boot.lds @@ -0,0 +1,144 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(m68k) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/mcf532x/start.o (.text) + lib_m68k/traps.o (.text) + lib_m68k/interrupts.o (.text) + common/dlmalloc.o (.text) + lib_generic/zlib.o (.text) + + . = DEFINED(env_offset) ? env_offset : .; + common/environment.o (.text) + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + + .reloc : + { + __got_start = .; + *(.got) + __got_end = .; + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + _sbss = .; + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + . = ALIGN(4); + _ebss = .; + } + _end = . ; + PROVIDE (end = .); +} diff --git a/common/cmd_bdinfo.c b/common/cmd_bdinfo.c index d97c09e88..9651b3097 100644 --- a/common/cmd_bdinfo.c +++ b/common/cmd_bdinfo.c @@ -207,6 +207,59 @@ int do_bdinfo ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) return 0; } +#elif defined(CONFIG_M68K) /* M68K */ + +int do_bdinfo ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + int i; + bd_t *bd = gd->bd; + print_num ("memstart", (ulong)bd->bi_memstart); + print_num ("memsize", (ulong)bd->bi_memsize); + print_num ("flashstart", (ulong)bd->bi_flashstart); + print_num ("flashsize", (ulong)bd->bi_flashsize); + print_num ("flashoffset", (ulong)bd->bi_flashoffset); +#if defined(CFG_INIT_RAM_ADDR) + print_num ("sramstart", (ulong)bd->bi_sramstart); + print_num ("sramsize", (ulong)bd->bi_sramsize); +#endif +#if defined(CFG_MBAR) + print_num ("mbar", bd->bi_mbar_base ); +#endif +#if defined(CFG_CMD_NET) + puts ("ethaddr ="); + for (i=0; i<6; ++i) { + printf ("%c%02X", i ? ':' : ' ', bd->bi_enetaddr[i]); + } + +#if defined(CONFIG_HAS_ETH1) + puts ("\neth1addr ="); + for (i=0; i<6; ++i) { + printf ("%c%02X", i ? ':' : ' ', bd->bi_enet1addr[i]); + } +#endif + +#if defined(CONFIG_HAS_ETH2) + puts ("\neth2addr ="); + for (i=0; i<6; ++i) { + printf ("%c%02X", i ? ':' : ' ', bd->bi_enet2addr[i]); + } +#endif + +#if defined(CONFIG_HAS_ETH3) + puts ("\neth3addr ="); + for (i=0; i<6; ++i) { + printf ("%c%02X", i ? ':' : ' ', bd->bi_enet3addr[i]); + } +#endif + + puts ("\nip_addr = "); + print_IPaddr (bd->bi_ip_addr); +#endif /* CFG_CMD_NET */ + printf ("\nbaudrate = %d bps\n", bd->bi_baudrate); + + return 0; +} + #else /* ! PPC, which leaves MIPS */ int do_bdinfo ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) diff --git a/common/cmd_mii.c b/common/cmd_mii.c index e6595360c..c3f43d7f4 100644 --- a/common/cmd_mii.c +++ b/common/cmd_mii.c @@ -438,7 +438,7 @@ int do_mii (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) int rcode = 0; char *devname; -#ifdef CONFIG_8xx +#if defined(CONFIG_8xx) || defined(CONFIG_MCF532x) mii_init (); #endif diff --git a/cpu/mcf532x/Makefile b/cpu/mcf532x/Makefile new file mode 100644 index 000000000..452848d32 --- /dev/null +++ b/cpu/mcf532x/Makefile @@ -0,0 +1,48 @@ +# +# (C) Copyright 2000-2004 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +# CFLAGS += -DET_DEBUG + +LIB = lib$(CPU).a + +START = +COBJS = cpu.o speed.o cpu_init.o + +SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) +START := $(addprefix $(obj),$(START)) + +all: $(obj).depend $(START) $(LIB) + +$(LIB): $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +######################################################################### + +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/cpu/mcf532x/config.mk b/cpu/mcf532x/config.mk new file mode 100644 index 000000000..ba324a894 --- /dev/null +++ b/cpu/mcf532x/config.mk @@ -0,0 +1,27 @@ +# +# (C) Copyright 2003 Josef Baumgartner +# +# (C) Copyright 2000-2004 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +PLATFORM_RELFLAGS += -ffixed-d7 -msep-data +PLATFORM_CPPFLAGS += -m5307 -fPIC diff --git a/cpu/mcf532x/cpu.c b/cpu/mcf532x/cpu.c new file mode 100644 index 000000000..071c50304 --- /dev/null +++ b/cpu/mcf532x/cpu.c @@ -0,0 +1,134 @@ +/* + * + * (C) Copyright 2000-2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +#include +#include + +int do_reset(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char *argv[]) +{ + volatile wdog_t *wdp = (wdog_t *) (MMAP_WDOG); + + wdp->cr = 0; + udelay(1000); + + /* enable watchdog, set timeout to 0 and wait */ + wdp->cr = WTM_WCR_EN; + while (1) ; + + /* we don't return! */ + return 0; +}; + +int checkcpu(void) +{ + DECLARE_GLOBAL_DATA_PTR; + + volatile ccm_t *ccm = (ccm_t *) MMAP_CCM; + u16 msk; + u16 id = 0; + u8 ver; + + puts("CPU: "); + msk = (ccm->cir >> 6); + ver = (ccm->cir & 0x003f); + switch (msk) { + case 0x54: + id = 5329; + break; + case 0x59: + id = 5328; + break; + case 0x61: + id = 5327; + break; + } + + if (id) { + printf("Freescale MCF%d (Mask:%01x Version:%x)\n", id, msk, + ver); + printf(" CPU CLK %d Mhz BUS CLK %d Mhz\n", + (int)(gd->cpu_clk / 1000000), + (int)(gd->bus_clk / 1000000)); + } + + return 0; +}; + +#if defined(CONFIG_WATCHDOG) +/* Called by macro WATCHDOG_RESET */ +void watchdog_reset(void) +{ + volatile wdog_t *wdp = (wdog_t *) (MMAP_WDOG); + + wdp->sr = 0x5555; /* Count register */ +} + +int watchdog_disable(void) +{ + volatile wdog_t *wdp = (wdog_t *) (MMAP_WDOG); + + /* UserManual, once the wdog is disabled, wdog cannot be re-enabled */ + wdp->cr |= WTM_WCR_HALTED; /* halted watchdog timer */ + + puts("WATCHDOG:disabled\n"); + return (0); +} + +int watchdog_init(void) +{ + volatile wdog_t *wdp = (wdog_t *) (MMAP_WDOG); + u32 wdog_module = 0; + + /* set timeout and enable watchdog */ + wdog_module = ((CFG_CLK / 1000) * CONFIG_WATCHDOG_TIMEOUT); + wdog_module |= (wdog_module / 8192); + wdp->mr = wdog_module; + + wdp->cr = WTM_WCR_EN; + puts("WATCHDOG:enabled\n"); + + return (0); +} +#endif /* #ifdef CONFIG_WATCHDOG */ + +#ifdef CONFIG_MCFINTC +int interrupt_init(void) +{ + volatile int0_t *intp = (int0_t *) (CFG_INTR_BASE); + + /* Make sure all interrupts are disabled */ + intp->imrh0 |= 0xFFFFFFFF; + intp->imrl0 |= 0xFFFFFFFF; + + enable_interrupts(); + return 0; +} +#endif /* CONFIG_MCFINTC */ diff --git a/cpu/mcf532x/cpu_init.c b/cpu/mcf532x/cpu_init.c new file mode 100644 index 000000000..6319658c0 --- /dev/null +++ b/cpu/mcf532x/cpu_init.c @@ -0,0 +1,126 @@ +/* + * + * (C) Copyright 2000-2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * (C) Copyright 2007 + * TsiChung Liew (Tsi-Chung.Liew@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +#include +#include + +/* + * Breath some life into the CPU... + * + * Set up the memory map, + * initialize a bunch of registers, + * initialize the UPM's + */ +void cpu_init_f(void) +{ + volatile scm1_t *scm1 = (scm1_t *) MMAP_SCM1; + volatile scm2_t *scm2 = (scm2_t *) MMAP_SCM2; + volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; + volatile fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS; + volatile wdog_t *wdog = (wdog_t *) MMAP_WDOG; + + /* watchdog is enabled by default - disable the watchdog */ +#ifndef CONFIG_WATCHDOG + wdog->cr = 0; +#endif + + scm1->mpr0 = 0x77777777; + scm2->pacra = 0; + scm2->pacrb = 0; + scm2->pacrc = 0; + scm2->pacrd = 0; + scm2->pacre = 0; + scm2->pacrf = 0; + scm2->pacrg = 0; + scm1->pacrh = 0; + + /* Setup Ports: */ + switch (CFG_UART_PORT) { + case 0: + gpio->par_uart = (GPIO_PAR_UART_TXD0 | GPIO_PAR_UART_RXD0); + break; + case 1: + gpio->par_uart = + (GPIO_PAR_UART_TXD1(3) | GPIO_PAR_UART_RXD1(3)); + break; + case 2: + gpio->par_uart = (GPIO_PAR_TIN3_URXD2 | GPIO_PAR_TIN2_UTXD2); + break; + } + + /* Port configuration */ + gpio->par_cs = 0x3E; + +#if (defined(CFG_CS0_BASE) && defined(CFG_CS0_MASK) && defined(CFG_CS0_CTRL)) + fbcs->csar0 = CFG_CS0_BASE; + fbcs->cscr0 = CFG_CS0_CTRL; + fbcs->csmr0 = CFG_CS0_MASK; +#endif + +#if (defined(CFG_CS1_BASE) && defined(CFG_CS1_MASK) && defined(CFG_CS1_CTRL)) + /* Latch chipselect */ + fbcs->csar1 = CFG_CS1_BASE; + fbcs->cscr1 = CFG_CS1_CTRL; + fbcs->csmr1 = CFG_CS1_MASK; +#endif + +#if (defined(CFG_CS2_BASE) && defined(CFG_CS2_MASK) && defined(CFG_CS2_CTRL)) + fbcs->csar2 = CFG_CS2_BASE; + fbcs->cscr2 = CFG_CS2_CTRL; + fbcs->csmr2 = CFG_CS2_MASK; +#endif + +#if (defined(CFG_CS3_BASE) && defined(CFG_CS3_MASK) && defined(CFG_CS3_CTRL)) + fbcs->csar3 = CFG_CS3_BASE; + fbcs->cscr3 = CFG_CS3_CTRL; + fbcs->csmr3 = CFG_CS3_MASK; +#endif + +#if (defined(CFG_CS4_BASE) && defined(CFG_CS4_MASK) && defined(CFG_CS4_CTRL)) + fbcs->csar4 = CFG_CS4_BASE; + fbcs->cscr4 = CFG_CS4_CTRL; + fbcs->csmr4 = CFG_CS4_MASK; +#endif + +#if (defined(CFG_CS5_BASE) && defined(CFG_CS5_MASK) && defined(CFG_CS5_CTRL)) + fbcs->csar5 = CFG_CS5_BASE; + fbcs->cscr5 = CFG_CS5_CTRL; + fbcs->csmr5 = CFG_CS5_MASK; +#endif +} + +/* + * initialize higher level parts of CPU like timers + */ +int cpu_init_r(void) +{ + /*icache_enable(); */ + return (0); +} diff --git a/cpu/mcf532x/speed.c b/cpu/mcf532x/speed.c new file mode 100644 index 000000000..c4ba7ec66 --- /dev/null +++ b/cpu/mcf532x/speed.c @@ -0,0 +1,222 @@ +/* + * + * (C) Copyright 2000-2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +#include +#include + +/* PLL min/max specifications */ +#define MAX_FVCO 500000 /* KHz */ +#define MAX_FSYS 80000 /* KHz */ +#define MIN_FSYS 58333 /* KHz */ +#define FREF 16000 /* KHz */ +#define MAX_MFD 135 /* Multiplier */ +#define MIN_MFD 88 /* Multiplier */ +#define BUSDIV 6 /* Divider */ +/* + * Low Power Divider specifications + */ +#define MIN_LPD (1 << 0) /* Divider (not encoded) */ +#define MAX_LPD (1 << 15) /* Divider (not encoded) */ +#define DEFAULT_LPD (1 << 1) /* Divider (not encoded) */ + +/* + * Get the value of the current system clock + * + * Parameters: + * none + * + * Return Value: + * The current output system frequency + */ +int get_sys_clock(void) +{ + volatile ccm_t *ccm = (volatile ccm_t *)(MMAP_CCM); + volatile pll_t *pll = (volatile pll_t *)(MMAP_PLL); + int divider; + + /* Test to see if device is in LIMP mode */ + if (ccm->misccr & CCM_MISCCR_LIMP) { + divider = ccm->cdr & CCM_CDR_LPDIV(0xF); + return (FREF / (2 << divider)); + } else { + return ((FREF * pll->pfdr) / (BUSDIV * 4)); + } +} + +/* + * Initialize the Low Power Divider circuit + * + * Parameters: + * div Desired system frequency divider + * + * Return Value: + * The resulting output system frequency + */ +int clock_limp(int div) +{ + volatile ccm_t *ccm = (volatile ccm_t *)(MMAP_CCM); + u32 temp; + + /* Check bounds of divider */ + if (div < MIN_LPD) + div = MIN_LPD; + if (div > MAX_LPD) + div = MAX_LPD; + + /* Save of the current value of the SSIDIV so we don't overwrite the value */ + temp = (ccm->cdr & CCM_CDR_SSIDIV(0xF)); + + /* Apply the divider to the system clock */ + ccm->cdr = (CCM_CDR_LPDIV(div) | CCM_CDR_SSIDIV(temp)); + + ccm->misccr |= CCM_MISCCR_LIMP; + + return (FREF / (3 * (1 << div))); +} + +/* + * Exit low power LIMP mode + * + * Parameters: + * div Desired system frequency divider + * + * Return Value: + * The resulting output system frequency + */ +int clock_exit_limp(void) +{ + volatile ccm_t *ccm = (volatile ccm_t *)(MMAP_CCM); + int fout; + + /* Exit LIMP mode */ + ccm->misccr &= (~CCM_MISCCR_LIMP); + + /* Wait for PLL to lock */ + while (!(ccm->misccr & CCM_MISCCR_PLL_LOCK)) ; + + fout = get_sys_clock(); + + return fout; +} + +/* Initialize the PLL + * + * Parameters: + * fref PLL reference clock frequency in KHz + * fsys Desired PLL output frequency in KHz + * flags Operating parameters + * + * Return Value: + * The resulting output system frequency + */ +int clock_pll(int fsys, int flags) +{ + volatile u32 *sdram_workaround = (volatile u32 *)(MMAP_SDRAM + 0x80); + volatile pll_t *pll = (volatile pll_t *)(MMAP_PLL); + int fref, temp, fout, mfd; + u32 i; + + fref = FREF; + + if (fsys == 0) { + /* Return current PLL output */ + mfd = pll->pfdr; + + return (fref * mfd / (BUSDIV * 4)); + } + + /* Check bounds of requested system clock */ + if (fsys > MAX_FSYS) + fsys = MAX_FSYS; + + if (fsys < MIN_FSYS) + fsys = MIN_FSYS; + + /* Multiplying by 100 when calculating the temp value, + and then dividing by 100 to calculate the mfd allows + for exact values without needing to include floating + point libraries. */ + temp = (100 * fsys) / fref; + mfd = (4 * BUSDIV * temp) / 100; + + /* Determine the output frequency for selected values */ + fout = ((fref * mfd) / (BUSDIV * 4)); + + /* + * Check to see if the SDRAM has already been initialized. + * If it has then the SDRAM needs to be put into self refresh + * mode before reprogramming the PLL. + */ + /* Put SDRAM into self refresh mode */ +/* if (MCF_SDRAMC_SDCR & MCF_SDRAMC_SDCR_REF) + MCF_SDRAMC_SDCR &= ~MCF_SDRAMC_SDCR_CKE;*/ + + /* + * Initialize the PLL to generate the new system clock frequency. + * The device must be put into LIMP mode to reprogram the PLL. + */ + + /* Enter LIMP mode */ + clock_limp(DEFAULT_LPD); + + /* Reprogram PLL for desired fsys */ + pll->podr = (PLL_PODR_CPUDIV(BUSDIV / 3) | PLL_PODR_BUSDIV(BUSDIV)); + + pll->pfdr = mfd; + + /* Exit LIMP mode */ + clock_exit_limp(); + + /* + * Return the SDRAM to normal operation if it is in use. + */ + /* Exit self refresh mode */ +/* if (MCF_SDRAMC_SDCR & MCF_SDRAMC_SDCR_REF) + MCF_SDRAMC_SDCR |= MCF_SDRAMC_SDCR_CKE;*/ + + /* software workaround for SDRAM opeartion after exiting LIMP mode errata */ + *sdram_workaround = CFG_SDRAM_BASE; + /* wait for DQS logic to relock */ + for (i = 0; i < 0x200; i++) ; + + return fout; +} + +/* + * get_clocks() fills in gd->cpu_clock and gd->bus_clk + */ +int get_clocks(void) +{ + DECLARE_GLOBAL_DATA_PTR; + + gd->bus_clk = clock_pll(CFG_CLK / 1000, 0) * 1000; + gd->cpu_clk = (gd->bus_clk * 3); + return (0); +} diff --git a/cpu/mcf532x/start.S b/cpu/mcf532x/start.S new file mode 100644 index 000000000..d36d076cf --- /dev/null +++ b/cpu/mcf532x/start.S @@ -0,0 +1,338 @@ +/* + * Copyright (C) 2003 Josef Baumgartner + * Based on code from Bernhard Kuhn + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include "version.h" + +#ifndef CONFIG_IDENT_STRING +#define CONFIG_IDENT_STRING "" +#endif + +#define _START _start +#define _FAULT _fault + + +#define SAVE_ALL \ + move.w #0x2700,%sr; /* disable intrs */ \ + subl #60,%sp; /* space for 15 regs */ \ + moveml %d0-%d7/%a0-%a6,%sp@; + +#define RESTORE_ALL \ + moveml %sp@,%d0-%d7/%a0-%a6; \ + addl #60,%sp; /* space for 15 regs */ \ + rte; + + +.text +/* + * Vector table. This is used for initial platform startup. + * These vectors are to catch any un-intended traps. + */ +_vectors: + +INITSP: .long 0x00000000 /* Initial SP */ +INITPC: .long _START /* Initial PC */ +vector02: .long _FAULT /* Access Error */ +vector03: .long _FAULT /* Address Error */ +vector04: .long _FAULT /* Illegal Instruction */ +vector05: .long _FAULT /* Reserved */ +vector06: .long _FAULT /* Reserved */ +vector07: .long _FAULT /* Reserved */ +vector08: .long _FAULT /* Privilege Violation */ +vector09: .long _FAULT /* Trace */ +vector0A: .long _FAULT /* Unimplemented A-Line */ +vector0B: .long _FAULT /* Unimplemented F-Line */ +vector0C: .long _FAULT /* Debug Interrupt */ +vector0D: .long _FAULT /* Reserved */ +vector0E: .long _FAULT /* Format Error */ +vector0F: .long _FAULT /* Unitialized Int. */ + +/* Reserved */ +vector10_17: +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT + +vector18: .long _FAULT /* Spurious Interrupt */ +vector19: .long _FAULT /* Autovector Level 1 */ +vector1A: .long _FAULT /* Autovector Level 2 */ +vector1B: .long _FAULT /* Autovector Level 3 */ +vector1C: .long _FAULT /* Autovector Level 4 */ +vector1D: .long _FAULT /* Autovector Level 5 */ +vector1E: .long _FAULT /* Autovector Level 6 */ +vector1F: .long _FAULT /* Autovector Level 7 */ + +/* TRAP #0 - #15 */ +vector20_2F: +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT + +/* Reserved */ +vector30_3F: +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT + +vector64_127: +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT + +vector128_191: +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT + +vector192_255: +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT + + .text + + .globl _start +_start: + nop + nop + move.w #0x2700,%sr /* Mask off Interrupt */ + + /* Set vector base register at the beginning of the Flash */ + move.l #CFG_FLASH_BASE, %d0 + movec %d0, %VBR + + move.l #(CFG_INIT_RAM_ADDR + CFG_INIT_RAM_CTRL), %d0 + movec %d0, %RAMBAR0 + + /* invalidate and disable cache */ + move.l #0x01000000, %d0 /* Invalidate cache cmd */ + movec %d0, %CACR /* Invalidate cache */ + move.l #0, %d0 + movec %d0, %ACR0 + movec %d0, %ACR1 + + /* initialize general use internal ram */ + move.l #0, %d0 + move.l #(CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END-8), %a1 + move.l #(CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END-4), %a2 + move.l %d0, (%a1) + move.l %d0, (%a2) + + /* set stackpointer to end of internal ram to get some stackspace for the first c-code */ + move.l #(CFG_INIT_RAM_ADDR + CFG_INIT_SP_OFFSET), %sp + clr.l %sp@- + + move.l #__got_start, %a5 /* put relocation table address to a5 */ + + bsr cpu_init_f /* run low-level CPU init code (from flash) */ + bsr board_init_f /* run low-level board init code (from flash) */ + + /* board_init_f() does not return */ + +/*------------------------------------------------------------------------------*/ + +/* + * void relocate_code (addr_sp, gd, addr_moni) + * + * This "function" does not return, instead it continues in RAM + * after relocating the monitor code. + * + * r3 = dest + * r4 = src + * r5 = length in bytes + * r6 = cachelinesize + */ + .globl relocate_code +relocate_code: + link.w %a6,#0 + move.l 8(%a6), %sp /* set new stack pointer */ + + move.l 12(%a6), %d0 /* Save copy of Global Data pointer */ + move.l 16(%a6), %a0 /* Save copy of Destination Address */ + + move.l #CFG_MONITOR_BASE, %a1 + move.l #__init_end, %a2 + move.l %a0, %a3 + + /* copy the code to RAM */ +1: + move.l (%a1)+, (%a3)+ + cmp.l %a1,%a2 + bgt.s 1b + +/* + * We are done. Do not return, instead branch to second part of board + * initialization, now running from RAM. + */ + move.l %a0, %a1 + add.l #(in_ram - CFG_MONITOR_BASE), %a1 + jmp (%a1) + +in_ram: + +clear_bss: + /* + * Now clear BSS segment + */ + move.l %a0, %a1 + add.l #(_sbss - CFG_MONITOR_BASE),%a1 + move.l %a0, %d1 + add.l #(_ebss - CFG_MONITOR_BASE),%d1 +6: + clr.l (%a1)+ + cmp.l %a1,%d1 + bgt.s 6b + + /* + * fix got table in RAM + */ + move.l %a0, %a1 + add.l #(__got_start - CFG_MONITOR_BASE),%a1 + move.l %a1,%a5 /* * fix got pointer register a5 */ + + move.l %a0, %a2 + add.l #(__got_end - CFG_MONITOR_BASE),%a2 + +7: + move.l (%a1),%d1 + sub.l #_start,%d1 + add.l %a0,%d1 + move.l %d1,(%a1)+ + cmp.l %a2, %a1 + bne 7b + + /* calculate relative jump to board_init_r in ram */ + move.l %a0, %a1 + add.l #(board_init_r - CFG_MONITOR_BASE), %a1 + + /* set parameters for board_init_r */ + move.l %a0,-(%sp) /* dest_addr */ + move.l %d0,-(%sp) /* gd */ + jsr (%a1) + +/*------------------------------------------------------------------------------*/ +/* exception code */ + .globl _fault +_fault: + jmp _fault + .globl _exc_handler + +_exc_handler: + SAVE_ALL + movel %sp,%sp@- + bsr exc_handler + addql #4,%sp + RESTORE_ALL + + .globl _int_handler +_int_handler: + SAVE_ALL + movel %sp,%sp@- + bsr int_handler + addql #4,%sp + RESTORE_ALL + +/*------------------------------------------------------------------------------*/ +/* cache functions */ + .globl icache_enable +icache_enable: + move.l #0x01000000, %d0 /* Invalidate cache cmd */ + movec %d0, %CACR /* Invalidate cache */ + move.l #(CFG_SDRAM_BASE + 0xc000), %d0 /* Setup cache mask */ + movec %d0, %ACR0 /* Enable cache */ + move.l #(CFG_CS0_BASE + 0xc000), %d0 /* Setup cache mask */ + movec %d0, %ACR1 /* Enable cache */ + + /*move.l #0x81000100, %d0*/ /* Setup cache mask */ + move.l #0x81000100, %d0 /* Setup cache mask */ + movec %d0, %CACR /* Enable cache */ + + move.l #(CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END-8), %a1 + moveq #1, %d0 + move.l %d0, (%a1) + rts + + .globl icache_disable +icache_disable: + move.l #0x00000100, %d0 /* Setup cache mask */ + movec %d0, %CACR /* Enable cache */ + clr.l %d0 /* Setup cache mask */ + movec %d0, %ACR0 /* Enable cache */ + movec %d0, %ACR1 /* Enable cache */ + + move.l #(CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END-8), %a1 + moveq #0, %d0 + move.l %d0, (%a1) + rts + + .globl icache_status +icache_status: + move.l #(CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END-8), %a1 + move.l (%a1), %d0 + rts + + .globl icache_invalid +icache_invalid: + move.l #0x00000100, %d0 /* Setup cache mask */ + movec %d0, %CACR /* Enable cache */ + rts + + .globl dcache_enable +dcache_enable: + move.l #(CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END-4), %a1 + moveq #1, %d0 + move.l %d0, (%a1) + rts + + /* No dcache, just a dummy function */ + .globl dcache_disable +dcache_disable: + move.l #(CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END-4), %a1 + moveq #0, %d0 + move.l %d0, (%a1) + rts + + .globl dcache_status +dcache_status: + move.l #(CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END-4), %a1 + move.l (%a1), %d0 + rts + +/*------------------------------------------------------------------------------*/ + + .globl version_string +version_string: + .ascii U_BOOT_VERSION + .ascii " (", __DATE__, " - ", __TIME__, ")" + .ascii CONFIG_IDENT_STRING, "\0" diff --git a/drivers/net/Makefile b/drivers/net/Makefile new file mode 100644 index 000000000..37d69b994 --- /dev/null +++ b/drivers/net/Makefile @@ -0,0 +1,45 @@ +# +# (C) Copyright 2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB := $(obj)libnet.a + +COBJS := mcffec.o + +SRCS := $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) + +all: $(LIB) + +$(LIB): $(obj).depend $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/drivers/net/mcffec.c b/drivers/net/mcffec.c new file mode 100644 index 000000000..d1c84caee --- /dev/null +++ b/drivers/net/mcffec.c @@ -0,0 +1,594 @@ +/* + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * (C) Copyright 2007 + * TsiChung Liew (Tsi-Chung.Liew@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +#include +#include +#include + +#include +#include +#include +#include + +#ifdef CONFIG_MCFFEC +#undef ET_DEBUG +#undef MII_DEBUG + +/* Ethernet Transmit and Receive Buffers */ +#define DBUF_LENGTH 1520 + +#define TX_BUF_CNT 2 + +/* + NOTE: PKT_MAXBUF_SIZE must be larger or equal to PKT_MAXBLR_SIZE, + see M54455 User Manual for MAX_FL of Receive Control Register for more + description. If PKT_MAXBUF_SIZE set to 1518, the FEC bandwidth will + reduce to about 20~40% of normal bandwidth. Changing PKT_MAXBLR_SIZE + will not make any improvement on speed +*/ +#define PKT_MAXBUF_SIZE 1518 +#define PKT_MINBUF_SIZE 64 +#define PKT_MAXBLR_SIZE 1520 +#define LAST_PKTBUFSRX PKTBUFSRX - 1 +#define BD_ENET_RX_W_E (BD_ENET_RX_WRAP | BD_ENET_RX_EMPTY) +#define BD_ENET_TX_RDY_LST (BD_ENET_TX_READY | BD_ENET_TX_LAST) + +DECLARE_GLOBAL_DATA_PTR; + +#if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(CONFIG_NET_MULTI) + +struct fec_info_s fec_info[] = { +#ifdef CFG_FEC0_IOBASE + { + 0, /* index */ + CFG_FEC0_IOBASE, /* io base */ + CFG_FEC0_PINMUX, /* gpio pin muxing */ + CFG_FEC0_MIIBASE, /* mii base */ + -1, /* phy_addr */ + 0, /* duplex and speed */ + 0, /* phy name */ + 0, /* phyname init */ + 0, /* RX BD */ + 0, /* TX BD */ + 0, /* rx Index */ + 0, /* tx Index */ + 0, /* tx buffer */ + 0, /* initialized flag */ + }, +#endif +#ifdef CFG_FEC1_IOBASE + { + 1, /* index */ + CFG_FEC1_IOBASE, /* io base */ + CFG_FEC1_PINMUX, /* gpio pin muxing */ + CFG_FEC1_MIIBASE, /* mii base */ + -1, /* phy_addr */ + 0, /* duplex and speed */ + 0, /* phy name */ + 0, /* phy name init */ + 0, /* RX BD */ + 0, /* TX BD */ + 0, /* rx Index */ + 0, /* tx Index */ + 0, /* tx buffer */ + 0, /* initialized flag */ + } +#endif +}; + +/* + * FEC Ethernet Tx and Rx buffer descriptors allocated at the + * immr->udata_bd address on Dual-Port RAM + * Provide for Double Buffering + */ + +int fec_send(struct eth_device *dev, volatile void *packet, int length); +int fec_recv(struct eth_device *dev); +int fec_init(struct eth_device *dev, bd_t * bd); +void fec_halt(struct eth_device *dev); +void fec_reset(struct eth_device *dev); + +extern int fecpin_setclear(struct eth_device *dev, int setclear); + +#ifdef CFG_DISCOVER_PHY +extern void mii_init(void); +extern uint mii_send(uint mii_cmd); +extern int mii_discover_phy(struct eth_device *dev); +extern int mcffec_miiphy_read(char *devname, unsigned char addr, + unsigned char reg, unsigned short *value); +extern int mcffec_miiphy_write(char *devname, unsigned char addr, + unsigned char reg, unsigned short value); +#endif + +void setFecDuplexSpeed(volatile fec_t * fecp, bd_t * bd, int dup_spd) +{ + if ((dup_spd >> 16) == FULL) { + /* Set maximum frame length */ + fecp->rcr = FEC_RCR_MAX_FL(PKT_MAXBUF_SIZE) | FEC_RCR_MII_MODE | + FEC_RCR_PROM | 0x100; + fecp->tcr = FEC_TCR_FDEN; + } else { + /* Half duplex mode */ + fecp->rcr = FEC_RCR_MAX_FL(PKT_MAXBUF_SIZE) | + FEC_RCR_MII_MODE | FEC_RCR_DRT; + fecp->tcr &= ~FEC_TCR_FDEN; + } + + if ((dup_spd & 0xFFFF) == _100BASET) { +#ifdef MII_DEBUG + printf("100Mbps\n"); +#endif + bd->bi_ethspeed = 100; + } else { +#ifdef MII_DEBUG + printf("10Mbps\n"); +#endif + bd->bi_ethspeed = 10; + } +} + +int fec_send(struct eth_device *dev, volatile void *packet, int length) +{ + struct fec_info_s *info = dev->priv; + volatile fec_t *fecp = (fec_t *) (info->iobase); + int j, rc; + u16 phyStatus; + + miiphy_read(dev->name, info->phy_addr, PHY_BMSR, &phyStatus); + + /* section 16.9.23.3 + * Wait for ready + */ + j = 0; + while ((info->txbd[info->txIdx].cbd_sc & BD_ENET_TX_READY) && + (j < MCFFEC_TOUT_LOOP)) { + udelay(1); + j++; + } + if (j >= MCFFEC_TOUT_LOOP) { + printf("TX not ready\n"); + } + + info->txbd[info->txIdx].cbd_bufaddr = (uint) packet; + info->txbd[info->txIdx].cbd_datlen = length; + info->txbd[info->txIdx].cbd_sc |= BD_ENET_TX_RDY_LST; + + /* Activate transmit Buffer Descriptor polling */ + fecp->tdar = 0x01000000; /* Descriptor polling active */ + + j = 0; + while ((info->txbd[info->txIdx].cbd_sc & BD_ENET_TX_READY) && + (j < MCFFEC_TOUT_LOOP)) { + udelay(1); + j++; + } + if (j >= MCFFEC_TOUT_LOOP) { + printf("TX timeout\n"); + } +#ifdef ET_DEBUG + printf("%s[%d] %s: cycles: %d status: %x retry cnt: %d\n", + __FILE__, __LINE__, __FUNCTION__, j, + info->txbd[info->txIdx].cbd_sc, + (info->txbd[info->txIdx].cbd_sc & 0x003C) >> 2); +#endif + + /* return only status bits */ ; + rc = (info->txbd[info->txIdx].cbd_sc & BD_ENET_TX_STATS); + info->txIdx = (info->txIdx + 1) % TX_BUF_CNT; + + return rc; +} + +int fec_recv(struct eth_device *dev) +{ + struct fec_info_s *info = dev->priv; + volatile fec_t *fecp = (fec_t *) (info->iobase); + int length; + + for (;;) { + /* section 16.9.23.2 */ + if (info->rxbd[info->rxIdx].cbd_sc & BD_ENET_RX_EMPTY) { + length = -1; + break; /* nothing received - leave for() loop */ + } + + length = info->rxbd[info->rxIdx].cbd_datlen; + + if (info->rxbd[info->rxIdx].cbd_sc & 0x003f) { + printf("%s[%d] err: %x\n", + __FUNCTION__, __LINE__, + info->rxbd[info->rxIdx].cbd_sc); +#ifdef ET_DEBUG + printf("%s[%d] err: %x\n", + __FUNCTION__, __LINE__, + info->rxbd[info->rxIdx].cbd_sc); +#endif + } else { + + length -= 4; + /* Pass the packet up to the protocol layers. */ + NetReceive(NetRxPackets[info->rxIdx], length); + + fecp->eir |= FEC_EIR_RXF; + } + + /* Give the buffer back to the FEC. */ + info->rxbd[info->rxIdx].cbd_datlen = 0; + + /* wrap around buffer index when necessary */ + if (info->rxIdx == LAST_PKTBUFSRX) { + info->rxbd[PKTBUFSRX - 1].cbd_sc = BD_ENET_RX_W_E; + info->rxIdx = 0; + } else { + info->rxbd[info->rxIdx].cbd_sc = BD_ENET_RX_EMPTY; + info->rxIdx++; + } + + /* Try to fill Buffer Descriptors */ + fecp->rdar = 0x01000000; /* Descriptor polling active */ + } + + return length; +} + +/************************************************************** + * + * FEC Ethernet Initialization Routine + * + *************************************************************/ + +#ifdef ET_DEBUG +void dbgFecRegs(struct eth_device *dev) +{ + struct fec_info_s *info = dev->priv; + volatile fec_t *fecp = (fec_t *) (info->iobase); + + printf("=====\n"); + printf("ievent %x - %x\n", (int)&fecp->eir, fecp->eir); + printf("imask %x - %x\n", (int)&fecp->eimr, fecp->eimr); + printf("r_des_active %x - %x\n", (int)&fecp->rdar, fecp->rdar); + printf("x_des_active %x - %x\n", (int)&fecp->tdar, fecp->tdar); + printf("ecntrl %x - %x\n", (int)&fecp->ecr, fecp->ecr); + printf("mii_mframe %x - %x\n", (int)&fecp->mmfr, fecp->mmfr); + printf("mii_speed %x - %x\n", (int)&fecp->mscr, fecp->mscr); + printf("mii_ctrlstat %x - %x\n", (int)&fecp->mibc, fecp->mibc); + printf("r_cntrl %x - %x\n", (int)&fecp->rcr, fecp->rcr); + printf("x_cntrl %x - %x\n", (int)&fecp->tcr, fecp->tcr); + printf("padr_l %x - %x\n", (int)&fecp->palr, fecp->palr); + printf("padr_u %x - %x\n", (int)&fecp->paur, fecp->paur); + printf("op_pause %x - %x\n", (int)&fecp->opd, fecp->opd); + printf("iadr_u %x - %x\n", (int)&fecp->iaur, fecp->iaur); + printf("iadr_l %x - %x\n", (int)&fecp->ialr, fecp->ialr); + printf("gadr_u %x - %x\n", (int)&fecp->gaur, fecp->gaur); + printf("gadr_l %x - %x\n", (int)&fecp->galr, fecp->galr); + printf("x_wmrk %x - %x\n", (int)&fecp->tfwr, fecp->tfwr); + printf("r_bound %x - %x\n", (int)&fecp->frbr, fecp->frbr); + printf("r_fstart %x - %x\n", (int)&fecp->frsr, fecp->frsr); + printf("r_drng %x - %x\n", (int)&fecp->erdsr, fecp->erdsr); + printf("x_drng %x - %x\n", (int)&fecp->etdsr, fecp->etdsr); + printf("r_bufsz %x - %x\n", (int)&fecp->emrbr, fecp->emrbr); + + printf("\n"); + printf("rmon_t_drop %x - %x\n", (int)&fecp->rmon_t_drop, + fecp->rmon_t_drop); + printf("rmon_t_packets %x - %x\n", (int)&fecp->rmon_t_packets, + fecp->rmon_t_packets); + printf("rmon_t_bc_pkt %x - %x\n", (int)&fecp->rmon_t_bc_pkt, + fecp->rmon_t_bc_pkt); + printf("rmon_t_mc_pkt %x - %x\n", (int)&fecp->rmon_t_mc_pkt, + fecp->rmon_t_mc_pkt); + printf("rmon_t_crc_align %x - %x\n", (int)&fecp->rmon_t_crc_align, + fecp->rmon_t_crc_align); + printf("rmon_t_undersize %x - %x\n", (int)&fecp->rmon_t_undersize, + fecp->rmon_t_undersize); + printf("rmon_t_oversize %x - %x\n", (int)&fecp->rmon_t_oversize, + fecp->rmon_t_oversize); + printf("rmon_t_frag %x - %x\n", (int)&fecp->rmon_t_frag, + fecp->rmon_t_frag); + printf("rmon_t_jab %x - %x\n", (int)&fecp->rmon_t_jab, + fecp->rmon_t_jab); + printf("rmon_t_col %x - %x\n", (int)&fecp->rmon_t_col, + fecp->rmon_t_col); + printf("rmon_t_p64 %x - %x\n", (int)&fecp->rmon_t_p64, + fecp->rmon_t_p64); + printf("rmon_t_p65to127 %x - %x\n", (int)&fecp->rmon_t_p65to127, + fecp->rmon_t_p65to127); + printf("rmon_t_p128to255 %x - %x\n", (int)&fecp->rmon_t_p128to255, + fecp->rmon_t_p128to255); + printf("rmon_t_p256to511 %x - %x\n", (int)&fecp->rmon_t_p256to511, + fecp->rmon_t_p256to511); + printf("rmon_t_p512to1023 %x - %x\n", (int)&fecp->rmon_t_p512to1023, + fecp->rmon_t_p512to1023); + printf("rmon_t_p1024to2047 %x - %x\n", (int)&fecp->rmon_t_p1024to2047, + fecp->rmon_t_p1024to2047); + printf("rmon_t_p_gte2048 %x - %x\n", (int)&fecp->rmon_t_p_gte2048, + fecp->rmon_t_p_gte2048); + printf("rmon_t_octets %x - %x\n", (int)&fecp->rmon_t_octets, + fecp->rmon_t_octets); + + printf("\n"); + printf("ieee_t_drop %x - %x\n", (int)&fecp->ieee_t_drop, + fecp->ieee_t_drop); + printf("ieee_t_frame_ok %x - %x\n", (int)&fecp->ieee_t_frame_ok, + fecp->ieee_t_frame_ok); + printf("ieee_t_1col %x - %x\n", (int)&fecp->ieee_t_1col, + fecp->ieee_t_1col); + printf("ieee_t_mcol %x - %x\n", (int)&fecp->ieee_t_mcol, + fecp->ieee_t_mcol); + printf("ieee_t_def %x - %x\n", (int)&fecp->ieee_t_def, + fecp->ieee_t_def); + printf("ieee_t_lcol %x - %x\n", (int)&fecp->ieee_t_lcol, + fecp->ieee_t_lcol); + printf("ieee_t_excol %x - %x\n", (int)&fecp->ieee_t_excol, + fecp->ieee_t_excol); + printf("ieee_t_macerr %x - %x\n", (int)&fecp->ieee_t_macerr, + fecp->ieee_t_macerr); + printf("ieee_t_cserr %x - %x\n", (int)&fecp->ieee_t_cserr, + fecp->ieee_t_cserr); + printf("ieee_t_sqe %x - %x\n", (int)&fecp->ieee_t_sqe, + fecp->ieee_t_sqe); + printf("ieee_t_fdxfc %x - %x\n", (int)&fecp->ieee_t_fdxfc, + fecp->ieee_t_fdxfc); + printf("ieee_t_octets_ok %x - %x\n", (int)&fecp->ieee_t_octets_ok, + fecp->ieee_t_octets_ok); + + printf("\n"); + printf("rmon_r_drop %x - %x\n", (int)&fecp->rmon_r_drop, + fecp->rmon_r_drop); + printf("rmon_r_packets %x - %x\n", (int)&fecp->rmon_r_packets, + fecp->rmon_r_packets); + printf("rmon_r_bc_pkt %x - %x\n", (int)&fecp->rmon_r_bc_pkt, + fecp->rmon_r_bc_pkt); + printf("rmon_r_mc_pkt %x - %x\n", (int)&fecp->rmon_r_mc_pkt, + fecp->rmon_r_mc_pkt); + printf("rmon_r_crc_align %x - %x\n", (int)&fecp->rmon_r_crc_align, + fecp->rmon_r_crc_align); + printf("rmon_r_undersize %x - %x\n", (int)&fecp->rmon_r_undersize, + fecp->rmon_r_undersize); + printf("rmon_r_oversize %x - %x\n", (int)&fecp->rmon_r_oversize, + fecp->rmon_r_oversize); + printf("rmon_r_frag %x - %x\n", (int)&fecp->rmon_r_frag, + fecp->rmon_r_frag); + printf("rmon_r_jab %x - %x\n", (int)&fecp->rmon_r_jab, + fecp->rmon_r_jab); + printf("rmon_r_p64 %x - %x\n", (int)&fecp->rmon_r_p64, + fecp->rmon_r_p64); + printf("rmon_r_p65to127 %x - %x\n", (int)&fecp->rmon_r_p65to127, + fecp->rmon_r_p65to127); + printf("rmon_r_p128to255 %x - %x\n", (int)&fecp->rmon_r_p128to255, + fecp->rmon_r_p128to255); + printf("rmon_r_p256to511 %x - %x\n", (int)&fecp->rmon_r_p256to511, + fecp->rmon_r_p256to511); + printf("rmon_r_p512to1023 %x - %x\n", (int)&fecp->rmon_r_p512to1023, + fecp->rmon_r_p512to1023); + printf("rmon_r_p1024to2047 %x - %x\n", (int)&fecp->rmon_r_p1024to2047, + fecp->rmon_r_p1024to2047); + printf("rmon_r_p_gte2048 %x - %x\n", (int)&fecp->rmon_r_p_gte2048, + fecp->rmon_r_p_gte2048); + printf("rmon_r_octets %x - %x\n", (int)&fecp->rmon_r_octets, + fecp->rmon_r_octets); + + printf("\n"); + printf("ieee_r_drop %x - %x\n", (int)&fecp->ieee_r_drop, + fecp->ieee_r_drop); + printf("ieee_r_frame_ok %x - %x\n", (int)&fecp->ieee_r_frame_ok, + fecp->ieee_r_frame_ok); + printf("ieee_r_crc %x - %x\n", (int)&fecp->ieee_r_crc, + fecp->ieee_r_crc); + printf("ieee_r_align %x - %x\n", (int)&fecp->ieee_r_align, + fecp->ieee_r_align); + printf("ieee_r_macerr %x - %x\n", (int)&fecp->ieee_r_macerr, + fecp->ieee_r_macerr); + printf("ieee_r_fdxfc %x - %x\n", (int)&fecp->ieee_r_fdxfc, + fecp->ieee_r_fdxfc); + printf("ieee_r_octets_ok %x - %x\n", (int)&fecp->ieee_r_octets_ok, + fecp->ieee_r_octets_ok); + + printf("\n\n\n"); +} +#endif + +int fec_init(struct eth_device *dev, bd_t * bd) +{ + struct fec_info_s *info = dev->priv; + volatile fec_t *fecp = (fec_t *) (info->iobase); + int i; + u8 *ea; + + fecpin_setclear(dev, 1); + + fec_reset(dev); + +#if (CONFIG_COMMANDS & CFG_CMD_MII) || defined (CONFIG_MII) || \ + defined (CFG_DISCOVER_PHY) + + mii_init(); + + setFecDuplexSpeed(fecp, bd, info->dup_spd); +#else +#ifndef CFG_DISCOVER_PHY + setFecDuplexSpeed(fecp, bd, (FECDUPLEX << 16) | FECSPEED); +#endif /* ifndef CFG_DISCOVER_PHY */ +#endif /* CFG_CMD_MII || CONFIG_MII */ + + /* We use strictly polling mode only */ + fecp->eimr = 0; + + /* Clear any pending interrupt */ + fecp->eir = 0xffffffff; + + /* Set station address */ + if ((u32) fecp == CFG_FEC0_IOBASE) { + ea = &bd->bi_enetaddr[0]; + } else { +#ifdef CFG_FEC1_IOBASE + ea = &bd->bi_enet1addr[0]; +#endif + } + + fecp->palr = (ea[0] << 24) | (ea[1] << 16) | (ea[2] << 8) | (ea[3]); + fecp->paur = (ea[4] << 24) | (ea[5] << 16); +#ifdef ET_DEBUG + printf("Eth Addrs: %02x:%02x:%02x:%02x:%02x:%02x\n", + ea[0], ea[1], ea[2], ea[3], ea[4], ea[5]); +#endif + + /* Clear unicast address hash table */ + fecp->iaur = 0; + fecp->ialr = 0; + + /* Clear multicast address hash table */ + fecp->gaur = 0; + fecp->galr = 0; + + /* Set maximum receive buffer size. */ + fecp->emrbr = PKT_MAXBLR_SIZE; + + /* + * Setup Buffers and Buffer Desriptors + */ + info->rxIdx = 0; + info->txIdx = 0; + + /* + * Setup Receiver Buffer Descriptors (13.14.24.18) + * Settings: + * Empty, Wrap + */ + for (i = 0; i < PKTBUFSRX; i++) { + info->rxbd[i].cbd_sc = BD_ENET_RX_EMPTY; + info->rxbd[i].cbd_datlen = 0; /* Reset */ + info->rxbd[i].cbd_bufaddr = (uint) NetRxPackets[i]; + } + info->rxbd[PKTBUFSRX - 1].cbd_sc |= BD_ENET_RX_WRAP; + + /* + * Setup Ethernet Transmitter Buffer Descriptors (13.14.24.19) + * Settings: + * Last, Tx CRC + */ + for (i = 0; i < TX_BUF_CNT; i++) { + info->txbd[i].cbd_sc = BD_ENET_TX_LAST | BD_ENET_TX_TC; + info->txbd[i].cbd_datlen = 0; /* Reset */ + info->txbd[i].cbd_bufaddr = (uint) (&info->txbuf[0]); + } + info->txbd[TX_BUF_CNT - 1].cbd_sc |= BD_ENET_TX_WRAP; + + /* Set receive and transmit descriptor base */ + fecp->erdsr = (unsigned int)(&info->rxbd[0]); + fecp->etdsr = (unsigned int)(&info->txbd[0]); + + /* Now enable the transmit and receive processing */ + fecp->ecr |= FEC_ECR_ETHER_EN; + + /* And last, try to fill Rx Buffer Descriptors */ + fecp->rdar = 0x01000000; /* Descriptor polling active */ + + return 1; +} + +void fec_reset(struct eth_device *dev) +{ + struct fec_info_s *info = dev->priv; + volatile fec_t *fecp = (fec_t *) (info->iobase); + int i; + + fecp->ecr = FEC_ECR_RESET; + for (i = 0; (fecp->ecr & FEC_ECR_RESET) && (i < FEC_RESET_DELAY); ++i) { + udelay(1); + } + if (i == FEC_RESET_DELAY) { + printf("FEC_RESET_DELAY timeout\n"); + } +} + +void fec_halt(struct eth_device *dev) +{ + struct fec_info_s *info = dev->priv; + + fec_reset(dev); + + fecpin_setclear(dev, 0); + + info->rxIdx = info->txIdx = 0; + memset(info->rxbd, 0, PKTBUFSRX * sizeof(cbd_t)); + memset(info->txbd, 0, TX_BUF_CNT * sizeof(cbd_t)); + memset(info->txbuf, 0, DBUF_LENGTH); +} + +int mcffec_initialize(bd_t * bis) +{ + struct eth_device *dev; + int i; + + for (i = 0; i < sizeof(fec_info) / sizeof(fec_info[0]); i++) { + + dev = (struct eth_device *)malloc(sizeof *dev); + if (dev == NULL) + hang(); + + memset(dev, 0, sizeof(*dev)); + + sprintf(dev->name, "FEC%d", fec_info[i].index); + + dev->priv = &fec_info[i]; + dev->init = fec_init; + dev->halt = fec_halt; + dev->send = fec_send; + dev->recv = fec_recv; + + /* setup Receive and Transmit buffer descriptor */ + fec_info[i].rxbd = + (cbd_t *) memalign(32, (PKTBUFSRX * sizeof(cbd_t) + 31)); + fec_info[i].txbd = + (cbd_t *) memalign(32, (TX_BUF_CNT * sizeof(cbd_t) + 31)); + fec_info[i].txbuf = (char *)memalign(32, DBUF_LENGTH + 31); +#ifdef ET_DEBUG + printf("rxbd %x txbd %x\n", + (int)fec_info[i].rxbd, (int)fec_info[i].txbd); +#endif + + fec_info[i].phy_name = (char *)malloc(32); + + eth_register(dev); + +#if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII) + miiphy_register(dev->name, + mcffec_miiphy_read, mcffec_miiphy_write); +#endif + } + + /* default speed */ + bis->bi_ethspeed = 10; + + return 1; +} + +#endif /* CFG_CMD_NET, FEC_ENET & NET_MULTI */ +#endif /* CONFIG_MCFFEC */ diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile new file mode 100644 index 000000000..2208a08a7 --- /dev/null +++ b/drivers/serial/Makefile @@ -0,0 +1,45 @@ +# +# (C) Copyright 2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB := $(obj)libserial.a + +COBJS := mcfserial.o + +SRCS := $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) + +all: $(LIB) + +$(LIB): $(obj).depend $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/drivers/serial/mcfserial.c b/drivers/serial/mcfserial.c new file mode 100644 index 000000000..a8ca78ad8 --- /dev/null +++ b/drivers/serial/mcfserial.c @@ -0,0 +1,126 @@ +/* + * (C) Copyright 2004, Freescale, Inc + * TsiChung Liew, Tsi-Chung.Liew@freescale.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +/* + * Minimal serial functions needed to use one of the uart ports + * as serial console interface. + */ + +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#ifdef CONFIG_MCFSERIAL +int serial_init(void) +{ + volatile uart_t *uart; + u32 counter; + + uart = (volatile uart_t *)(CFG_UART_BASE); + + /* write to SICR: SIM2 = uart mode,dcd does not affect rx */ + uart->ucr = UART_UCR_RESET_RX; + uart->ucr = UART_UCR_RESET_TX; + uart->ucr = UART_UCR_RESET_ERROR; + uart->ucr = UART_UCR_RESET_MR; + __asm__("nop"); + + uart->uimr = 0; + + /* write to CSR: RX/TX baud rate from timers */ + uart->ucsr = (UART_UCSR_RCS_SYS_CLK | UART_UCSR_TCS_SYS_CLK); + + uart->umr = (UART_UMR_BC_8 | UART_UMR_PM_NONE); + uart->umr = UART_UMR_SB_STOP_BITS_1; + + /* Setting up BaudRate */ + counter = (u32) (gd->bus_clk / (gd->baudrate)); + counter >>= 5; + + /* write to CTUR: divide counter upper byte */ + uart->ubg1 = (u8) ((counter & 0xff00) >> 8); + /* write to CTLR: divide counter lower byte */ + uart->ubg2 = (u8) (counter & 0x00ff); + + uart->ucr = (UART_UCR_RX_ENABLED | UART_UCR_TX_ENABLED); + + return (0); +} + +void serial_putc(const char c) +{ + volatile uart_t *uart = (volatile uart_t *)(CFG_UART_BASE); + + if (c == '\n') + serial_putc('\r'); + + /* Wait for last character to go. */ + while (!(uart->usr & UART_USR_TXRDY)) ; + + uart->utb = c; +} + +void serial_puts(const char *s) +{ + while (*s) { + serial_putc(*s++); + } +} + +int serial_getc(void) +{ + volatile uart_t *uart = (volatile uart_t *)(CFG_UART_BASE); + + /* Wait for a character to arrive. */ + while (!(uart->usr & UART_USR_RXRDY)) ; + return uart->urb; +} + +int serial_tstc(void) +{ + volatile uart_t *uart = (volatile uart_t *)(CFG_UART_BASE); + + return (uart->usr & UART_USR_RXRDY); +} + +void serial_setbrg(void) +{ + volatile uart_t *uart = (volatile uart_t *)(CFG_UART_BASE); + u32 counter; + + counter = ((gd->bus_clk / gd->baudrate)) >> 5; + counter++; + + /* write to CTUR: divide counter upper byte */ + uart->ubg1 = ((counter & 0xff00) >> 8); + /* write to CTLR: divide counter lower byte */ + uart->ubg2 = (counter & 0x00ff); + + uart->ucr = UART_UCR_RESET_RX; + uart->ucr = UART_UCR_RESET_TX; + + uart->ucr = UART_UCR_RX_ENABLED | UART_UCR_TX_ENABLED; +} +#endif /* CONFIG_MCFSERIAL */ diff --git a/include/asm-m68k/byteorder.h b/include/asm-m68k/byteorder.h index ce613ac38..0e2a0ed8c 100644 --- a/include/asm-m68k/byteorder.h +++ b/include/asm-m68k/byteorder.h @@ -1,7 +1,107 @@ +/* + * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + #ifndef _M68K_BYTEORDER_H #define _M68K_BYTEORDER_H #include + +#ifdef __GNUC__ +#define __sw16(x) \ + ((__u16)( \ + (((__u16)(x) & (__u16)0x00ffU) << 8) | \ + (((__u16)(x) & (__u16)0xff00U) >> 8) )) +#define __sw32(x) \ + ((__u32)( \ + (((__u32)(x)) << 24) | \ + (((__u32)(x) & (__u32)0x0000ff00UL) << 8) | \ + (((__u32)(x) & (__u32)0x00ff0000UL) >> 8) | \ + (((__u32)(x)) >> 24) )) + +extern __inline__ unsigned ld_le16(const volatile unsigned short *addr) +{ + unsigned result = *addr; + return __sw16(result); +} + +extern __inline__ void st_le16(volatile unsigned short *addr, + const unsigned val) +{ + *addr = __sw16(val); +} + +extern __inline__ unsigned ld_le32(const volatile unsigned *addr) +{ + unsigned result = *addr; + return __sw32(result); +} + +extern __inline__ void st_le32(volatile unsigned *addr, const unsigned val) +{ + *addr = __sw32(val); +} + +#if 0 +/* alas, egcs sounds like it has a bug in this code that doesn't use the + inline asm correctly, and can cause file corruption. Until I hear that + it's fixed, I can live without the extra speed. I hope. */ +#if !(__GNUC__ >= 2 && __GNUC_MINOR__ >= 90) +#if 0 +# define __arch_swab16(x) ld_le16(&x) +# define __arch_swab32(x) ld_le32(&x) +#else +static __inline__ __attribute__ ((const)) +__u16 ___arch__swab16(__u16 value) +{ + return __sw16(value); +} + +static __inline__ __attribute__ ((const)) +__u32 ___arch__swab32(__u32 value) +{ + return __sw32(value); +} + +#define __arch__swab32(x) ___arch__swab32(x) +#define __arch__swab16(x) ___arch__swab16(x) +#endif /* 0 */ + +#endif + +/* The same, but returns converted value from the location pointer by addr. */ +#define __arch__swab16p(addr) ld_le16(addr) +#define __arch__swab32p(addr) ld_le32(addr) + +/* The same, but do the conversion in situ, ie. put the value back to addr. */ +#define __arch__swab16s(addr) st_le16(addr,*addr) +#define __arch__swab32s(addr) st_le32(addr,*addr) +#endif + +#endif /* __GNUC__ */ + +#if defined(__GNUC__) && !defined(__STRICT_ANSI__) +#define __BYTEORDER_HAS_U64__ +#endif #include -#endif /* _M68K_BYTEORDER_H */ +#endif /* _M68K_BYTEORDER_H */ diff --git a/include/asm-m68k/fec.h b/include/asm-m68k/fec.h index 5bbbfb245..9a5e7d5ab 100644 --- a/include/asm-m68k/fec.h +++ b/include/asm-m68k/fec.h @@ -5,6 +5,10 @@ * MPC8xx Communication Processor Module. * Copyright (c) 1997 Dan Malek (dmalek@jlc.net) * + * Add FEC Structure and definitions + * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew@freescale.com) + * * See file CREDITS for list of people who contributed to this * project. * @@ -30,9 +34,9 @@ /* Buffer descriptors used FEC. */ typedef struct cpm_buf_desc { - ushort cbd_sc; /* Status and Control */ - ushort cbd_datlen; /* Data length in buffer */ - uint cbd_bufaddr; /* Buffer address in host memory */ + ushort cbd_sc; /* Status and Control */ + ushort cbd_datlen; /* Data length in buffer */ + uint cbd_bufaddr; /* Buffer address in host memory */ } cbd_t; #define BD_SC_EMPTY ((ushort)0x8000) /* Recieve is empty */ @@ -53,28 +57,36 @@ typedef struct cpm_buf_desc { /* Buffer descriptor control/status used by Ethernet receive. */ #define BD_ENET_RX_EMPTY ((ushort)0x8000) +#define BD_ENET_RX_RO1 ((ushort)0x4000) #define BD_ENET_RX_WRAP ((ushort)0x2000) #define BD_ENET_RX_INTR ((ushort)0x1000) +#define BD_ENET_RX_RO2 BD_ENET_RX_INTR #define BD_ENET_RX_LAST ((ushort)0x0800) #define BD_ENET_RX_FIRST ((ushort)0x0400) #define BD_ENET_RX_MISS ((ushort)0x0100) +#define BD_ENET_RX_BC ((ushort)0x0080) +#define BD_ENET_RX_MC ((ushort)0x0040) #define BD_ENET_RX_LG ((ushort)0x0020) #define BD_ENET_RX_NO ((ushort)0x0010) #define BD_ENET_RX_SH ((ushort)0x0008) #define BD_ENET_RX_CR ((ushort)0x0004) #define BD_ENET_RX_OV ((ushort)0x0002) #define BD_ENET_RX_CL ((ushort)0x0001) +#define BD_ENET_RX_TR BD_ENET_RX_CL #define BD_ENET_RX_STATS ((ushort)0x013f) /* All status bits */ /* Buffer descriptor control/status used by Ethernet transmit. */ #define BD_ENET_TX_READY ((ushort)0x8000) #define BD_ENET_TX_PAD ((ushort)0x4000) +#define BD_ENET_TX_TO1 BD_ENET_TX_PAD #define BD_ENET_TX_WRAP ((ushort)0x2000) #define BD_ENET_TX_INTR ((ushort)0x1000) +#define BD_ENET_TX_TO2 BD_ENET_TX_INTR_ #define BD_ENET_TX_LAST ((ushort)0x0800) #define BD_ENET_TX_TC ((ushort)0x0400) #define BD_ENET_TX_DEF ((ushort)0x0200) +#define BD_ENET_TX_ABC BD_ENET_TX_DEF #define BD_ENET_TX_HB ((ushort)0x0100) #define BD_ENET_TX_LC ((ushort)0x0080) #define BD_ENET_TX_RL ((ushort)0x0040) @@ -83,4 +95,225 @@ typedef struct cpm_buf_desc { #define BD_ENET_TX_CSL ((ushort)0x0001) #define BD_ENET_TX_STATS ((ushort)0x03ff) /* All status bits */ -#endif /* fec_h */ +#ifdef CONFIG_MCFFEC +/********************************************************************* +* +* Fast Ethernet Controller (FEC) +* +*********************************************************************/ +/* FEC private information */ +struct fec_info_s { + int index; + u32 iobase; + u32 pinmux; + u32 miibase; + int phy_addr; + int dup_spd; + char *phy_name; + int phyname_init; + cbd_t *rxbd; /* Rx BD */ + cbd_t *txbd; /* Tx BD */ + uint rxIdx; + uint txIdx; + char *txbuf; + int initialized; +}; + +/* Register read/write struct */ +typedef struct fec { + u8 resv0[0x4]; + u32 eir; + u32 eimr; + u8 resv1[0x4]; + u32 rdar; + u32 tdar; + u8 resv2[0xC]; + u32 ecr; + u8 resv3[0x18]; + u32 mmfr; + u32 mscr; + u8 resv4[0x1C]; + u32 mibc; + u8 resv5[0x1C]; + u32 rcr; + u8 resv6[0x3C]; + u32 tcr; + u8 resv7[0x1C]; + u32 palr; + u32 paur; + u32 opd; + u8 resv8[0x28]; + u32 iaur; + u32 ialr; + u32 gaur; + u32 galr; + u8 resv9[0x1C]; + u32 tfwr; + u8 resv10[0x4]; + u32 frbr; + u32 frsr; + u8 resv11[0x2C]; + u32 erdsr; + u32 etdsr; + u32 emrbr; + u8 resv12[0x74]; + + u32 rmon_t_drop; + u32 rmon_t_packets; + u32 rmon_t_bc_pkt; + u32 rmon_t_mc_pkt; + u32 rmon_t_crc_align; + u32 rmon_t_undersize; + u32 rmon_t_oversize; + u32 rmon_t_frag; + u32 rmon_t_jab; + u32 rmon_t_col; + u32 rmon_t_p64; + u32 rmon_t_p65to127; + u32 rmon_t_p128to255; + u32 rmon_t_p256to511; + u32 rmon_t_p512to1023; + u32 rmon_t_p1024to2047; + u32 rmon_t_p_gte2048; + u32 rmon_t_octets; + + u32 ieee_t_drop; + u32 ieee_t_frame_ok; + u32 ieee_t_1col; + u32 ieee_t_mcol; + u32 ieee_t_def; + u32 ieee_t_lcol; + u32 ieee_t_excol; + u32 ieee_t_macerr; + u32 ieee_t_cserr; + u32 ieee_t_sqe; + u32 ieee_t_fdxfc; + u32 ieee_t_octets_ok; + u8 resv13[0x8]; + + u32 rmon_r_drop; + u32 rmon_r_packets; + u32 rmon_r_bc_pkt; + u32 rmon_r_mc_pkt; + u32 rmon_r_crc_align; + u32 rmon_r_undersize; + u32 rmon_r_oversize; + u32 rmon_r_frag; + u32 rmon_r_jab; + u32 rmon_r_resvd_0; + u32 rmon_r_p64; + u32 rmon_r_p65to127; + u32 rmon_r_p128to255; + u32 rmon_r_p256to511; + u32 rmon_r_p512to1023; + u32 rmon_r_p1024to2047; + u32 rmon_r_p_gte2048; + u32 rmon_r_octets; + + u32 ieee_r_drop; + u32 ieee_r_frame_ok; + u32 ieee_r_crc; + u32 ieee_r_align; + u32 ieee_r_macerr; + u32 ieee_r_fdxfc; + u32 ieee_r_octets_ok; +} fec_t; + +/********************************************************************* +* Fast Ethernet Controller (FEC) +*********************************************************************/ +/* Bit definitions and macros for FEC_EIR */ +#define FEC_EIR_CLEAR_ALL (0xFFF80000) +#define FEC_EIR_HBERR (0x80000000) +#define FEC_EIR_BABR (0x40000000) +#define FEC_EIR_BABT (0x20000000) +#define FEC_EIR_GRA (0x10000000) +#define FEC_EIR_TXF (0x08000000) +#define FEC_EIR_TXB (0x04000000) +#define FEC_EIR_RXF (0x02000000) +#define FEC_EIR_RXB (0x01000000) +#define FEC_EIR_MII (0x00800000) +#define FEC_EIR_EBERR (0x00400000) +#define FEC_EIR_LC (0x00200000) +#define FEC_EIR_RL (0x00100000) +#define FEC_EIR_UN (0x00080000) + +/* Bit definitions and macros for FEC_RDAR */ +#define FEC_RDAR_R_DES_ACTIVE (0x01000000) + +/* Bit definitions and macros for FEC_TDAR */ +#define FEC_TDAR_X_DES_ACTIVE (0x01000000) + +/* Bit definitions and macros for FEC_ECR */ +#define FEC_ECR_ETHER_EN (0x00000002) +#define FEC_ECR_RESET (0x00000001) + +/* Bit definitions and macros for FEC_MMFR */ +#define FEC_MMFR_DATA(x) (((x)&0xFFFF)) +#define FEC_MMFR_ST(x) (((x)&0x03)<<30) +#define FEC_MMFR_ST_01 (0x40000000) +#define FEC_MMFR_OP_RD (0x20000000) +#define FEC_MMFR_OP_WR (0x10000000) +#define FEC_MMFR_PA(x) (((x)&0x1F)<<23) +#define FEC_MMFR_RA(x) (((x)&0x1F)<<18) +#define FEC_MMFR_TA(x) (((x)&0x03)<<16) +#define FEC_MMFR_TA_10 (0x00020000) + +/* Bit definitions and macros for FEC_MSCR */ +#define FEC_MSCR_DIS_PREAMBLE (0x00000080) +#define FEC_MSCR_MII_SPEED(x) (((x)&0x3F)<<1) + +/* Bit definitions and macros for FEC_MIBC */ +#define FEC_MIBC_MIB_DISABLE (0x80000000) +#define FEC_MIBC_MIB_IDLE (0x40000000) + +/* Bit definitions and macros for FEC_RCR */ +#define FEC_RCR_MAX_FL(x) (((x)&0x7FF)<<16) +#define FEC_RCR_FCE (0x00000020) +#define FEC_RCR_BC_REJ (0x00000010) +#define FEC_RCR_PROM (0x00000008) +#define FEC_RCR_MII_MODE (0x00000004) +#define FEC_RCR_DRT (0x00000002) +#define FEC_RCR_LOOP (0x00000001) + +/* Bit definitions and macros for FEC_TCR */ +#define FEC_TCR_RFC_PAUSE (0x00000010) +#define FEC_TCR_TFC_PAUSE (0x00000008) +#define FEC_TCR_FDEN (0x00000004) +#define FEC_TCR_HBC (0x00000002) +#define FEC_TCR_GTS (0x00000001) + +/* Bit definitions and macros for FEC_PAUR */ +#define FEC_PAUR_PADDR2(x) (((x)&0xFFFF)<<16) +#define FEC_PAUR_TYPE(x) ((x)&0xFFFF) + +/* Bit definitions and macros for FEC_OPD */ +#define FEC_OPD_PAUSE_DUR(x) (((x)&0x0000FFFF)<<0) +#define FEC_OPD_OPCODE(x) (((x)&0x0000FFFF)<<16) + +/* Bit definitions and macros for FEC_TFWR */ +#define FEC_TFWR_X_WMRK(x) ((x)&0x03) +#define FEC_TFWR_X_WMRK_64 (0x01) +#define FEC_TFWR_X_WMRK_128 (0x02) +#define FEC_TFWR_X_WMRK_192 (0x03) + +/* Bit definitions and macros for FEC_FRBR */ +#define FEC_FRBR_R_BOUND(x) (((x)&0xFF)<<2) + +/* Bit definitions and macros for FEC_FRSR */ +#define FEC_FRSR_R_FSTART(x) (((x)&0xFF)<<2) + +/* Bit definitions and macros for FEC_ERDSR */ +#define FEC_ERDSR_R_DES_START(x)(((x)&0x3FFFFFFF)<<2) + +/* Bit definitions and macros for FEC_ETDSR */ +#define FEC_ETDSR_X_DES_START(x)(((x)&0x3FFFFFFF)<<2) + +/* Bit definitions and macros for FEC_EMRBR */ +#define FEC_EMRBR_R_BUF_SIZE(x) (((x)&0x7F)<<4) + +#define FEC_RESET_DELAY 100 +#define FEC_RX_TOUT 100 + +#endif /* CONFIG_MCFFEC */ +#endif /* fec_h */ diff --git a/include/asm-m68k/immap_5329.h b/include/asm-m68k/immap_5329.h new file mode 100644 index 000000000..5ef1265f8 --- /dev/null +++ b/include/asm-m68k/immap_5329.h @@ -0,0 +1,793 @@ +/* + * MCF5329 Internal Memory Map + * + * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __IMMAP_5329__ +#define __IMMAP_5329__ + +#define MMAP_SCM1 0xEC000000 +#define MMAP_MDHA 0xEC080000 +#define MMAP_SKHA 0xEC084000 +#define MMAP_RNG 0xEC088000 +#define MMAP_SCM2 0xFC000000 +#define MMAP_XBS 0xFC004000 +#define MMAP_FBCS 0xFC008000 +#define MMAP_CAN 0xFC020000 +#define MMAP_FEC 0xFC030000 +#define MMAP_SCM3 0xFC040000 +#define MMAP_EDMA 0xFC044000 +#define MMAP_TCD 0xFC045000 +#define MMAP_INTC0 0xFC048000 +#define MMAP_INTC1 0xFC04C000 +#define MMAP_INTCACK 0xFC054000 +#define MMAP_I2C 0xFC058000 +#define MMAP_QSPI 0xFC05C000 +#define MMAP_UART0 0xFC060000 +#define MMAP_UART1 0xFC064000 +#define MMAP_UART2 0xFC068000 +#define MMAP_DTMR0 0xFC070000 +#define MMAP_DTMR1 0xFC074000 +#define MMAP_DTMR2 0xFC078000 +#define MMAP_DTMR3 0xFC07C000 +#define MMAP_PIT0 0xFC080000 +#define MMAP_PIT1 0xFC084000 +#define MMAP_PIT2 0xFC088000 +#define MMAP_PIT3 0xFC08C000 +#define MMAP_PWM 0xFC090000 +#define MMAP_EPORT 0xFC094000 +#define MMAP_WDOG 0xFC098000 +#define MMAP_CCM 0xFC0A0000 +#define MMAP_GPIO 0xFC0A4000 +#define MMAP_RTC 0xFC0A8000 +#define MMAP_LCDC 0xFC0AC000 +#define MMAP_USBOTG 0xFC0B0000 +#define MMAP_USBH 0xFC0B4000 +#define MMAP_SDRAM 0xFC0B8000 +#define MMAP_SSI 0xFC0BC000 +#define MMAP_PLL 0xFC0C0000 + +/* System control module registers */ +typedef struct scm1_ctrl { + u32 mpr0; /* 0x00 Master Privilege Register 0 */ + u32 res1[15]; /* 0x04 - 0x3F */ + u32 pacrh; /* 0x40 Peripheral Access Control Register H */ + u32 res2[3]; /* 0x44 - 0x53 */ + u32 bmt0; /*0x54 Bus Monitor Timeout 0 */ +} scm1_t; + +/* Message Digest Hardware Accelerator */ +typedef struct mdha_ctrl { + u32 mdmr; /* 0x00 MDHA Mode Register */ + u32 mdcr; /* 0x04 Control register */ + u32 mdcmr; /* 0x08 Command Register */ + u32 mdsr; /* 0x0C Status Register */ + u32 mdisr; /* 0x10 Interrupt Status Register */ + u32 mdimr; /* 0x14 Interrupt Mask Register */ + u32 mddsr; /* 0x1C Data Size Register */ + u32 mdin; /* 0x20 Input FIFO */ + u32 res1[3]; /* 0x24 - 0x2F */ + u32 mdao; /* 0x30 Message Digest AO Register */ + u32 mdbo; /* 0x34 Message Digest BO Register */ + u32 mdco; /* 0x38 Message Digest CO Register */ + u32 mddo; /* 0x3C Message Digest DO Register */ + u32 mdeo; /* 0x40 Message Digest EO Register */ + u32 mdmds; /* 0x44 Message Data Size Register */ + u32 res[10]; /* 0x48 - 0x6F */ + u32 mda1; /* 0x70 Message Digest A1 Register */ + u32 mdb1; /* 0x74 Message Digest B1 Register */ + u32 mdc1; /* 0x78 Message Digest C1 Register */ + u32 mdd1; /* 0x7C Message Digest D1 Register */ + u32 mde1; /* 0x80 Message Digest E1 Register */ +} mdha_t; + +/* Symmetric Key Hardware Accelerator */ +typedef struct skha_ctrl { + u32 mr; /* 0x00 Mode Register */ + u32 cr; /* 0x04 Control Register */ + u32 cmr; /* 0x08 Command Register */ + u32 sr; /* 0x0C Status Register */ + u32 esr; /* 0x10 Error Status Register */ + u32 emr; /* 0x14 Error Status Mask Register) */ + u32 ksr; /* 0x18 Key Size Register */ + u32 dsr; /* 0x1C Data Size Register */ + u32 in; /* 0x20 Input FIFO */ + u32 out; /* 0x24 Output FIFO */ + u32 res1[2]; /* 0x28 - 0x2F */ + u32 kdr1; /* 0x30 Key Data Register 1 */ + u32 kdr2; /* 0x34 Key Data Register 2 */ + u32 kdr3; /* 0x38 Key Data Register 3 */ + u32 kdr4; /* 0x3C Key Data Register 4 */ + u32 kdr5; /* 0x40 Key Data Register 5 */ + u32 kdr6; /* 0x44 Key Data Register 6 */ + u32 res2[10]; /* 0x48 - 0x6F */ + u32 c1; /* 0x70 Context 1 */ + u32 c2; /* 0x74 Context 2 */ + u32 c3; /* 0x78 Context 3 */ + u32 c4; /* 0x7C Context 4 */ + u32 c5; /* 0x80 Context 5 */ + u32 c6; /* 0x84 Context 6 */ + u32 c7; /* 0x88 Context 7 */ + u32 c8; /* 0x8C Context 8 */ + u32 c9; /* 0x90 Context 9 */ + u32 c10; /* 0x94 Context 10 */ + u32 c11; /* 0x98 Context 11 */ +} skha_t; + +/* Random Number Generator */ +typedef struct rng_ctrl { + u32 rngcr; /* 0x00 RNG Control Register */ + u32 rngsr; /* 0x04 RNG Status Register */ + u32 rnger; /* 0x08 RNG Entropy Register */ + u32 rngout; /* 0x0C RNG Output FIFO */ +} rng_t; + +/* System control module registers 2 */ +typedef struct scm2_ctrl { + u32 mpr1; /* 0x00 Master Privilege Register */ + u32 res1[7]; /* 0x04 - 0x1F */ + u32 pacra; /* 0x20 Peripheral Access Control Register A */ + u32 pacrb; /* 0x24 Peripheral Access Control Register B */ + u32 pacrc; /* 0x28 Peripheral Access Control Register C */ + u32 pacrd; /* 0x2C Peripheral Access Control Register D */ + u32 res2[4]; /* 0x30 - 0x3F */ + u32 pacre; /* 0x40 Peripheral Access Control Register E */ + u32 pacrf; /* 0x44 Peripheral Access Control Register F */ + u32 pacrg; /* 0x48 Peripheral Access Control Register G */ + u32 res3[2]; /* 0x4C - 0x53 */ + u32 bmt1; /* 0x54 Bus Monitor Timeout 1 */ +} scm2_t; + +/* Cross-Bar Switch Module */ +typedef struct xbs_ctrl { + u32 prs1; /* 0x100 Priority Register Slave 1 */ + u32 res1[3]; /* 0x104 - 0F */ + u32 crs1; /* 0x110 Control Register Slave 1 */ + u32 res2[187]; /* 0x114 - 0x3FF */ + + u32 prs4; /* 0x400 Priority Register Slave 4 */ + u32 res3[3]; /* 0x404 - 0F */ + u32 crs4; /* 0x410 Control Register Slave 4 */ + u32 res4[123]; /* 0x414 - 0x5FF */ + + u32 prs6; /* 0x600 Priority Register Slave 6 */ + u32 res5[3]; /* 0x604 - 0F */ + u32 crs6; /* 0x610 Control Register Slave 6 */ + u32 res6[59]; /* 0x614 - 0x6FF */ + + u32 prs7; /* 0x700 Priority Register Slave 7 */ + u32 res7[3]; /* 0x704 - 0F */ + u32 crs7; /* 0x710 Control Register Slave 7 */ +} xbs_t; + +/* Flexbus module Chip select registers */ +typedef struct fbcs_ctrl { + u16 csar0; /* 0x00 Chip-Select Address Register 0 */ + u16 res0; + u32 csmr0; /* 0x04 Chip-Select Mask Register 0 */ + u32 cscr0; /* 0x08 Chip-Select Control Register 0 */ + + u16 csar1; /* 0x0C Chip-Select Address Register 1 */ + u16 res1; + u32 csmr1; /* 0x10 Chip-Select Mask Register 1 */ + u32 cscr1; /* 0x14 Chip-Select Control Register 1 */ + + u16 csar2; /* 0x18 Chip-Select Address Register 2 */ + u16 res2; + u32 csmr2; /* 0x1C Chip-Select Mask Register 2 */ + u32 cscr2; /* 0x20 Chip-Select Control Register 2 */ + + u16 csar3; /* 0x24 Chip-Select Address Register 3 */ + u16 res3; + u32 csmr3; /* 0x28 Chip-Select Mask Register 3 */ + u32 cscr3; /* 0x2C Chip-Select Control Register 3 */ + + u16 csar4; /* 0x30 Chip-Select Address Register 4 */ + u16 res4; + u32 csmr4; /* 0x34 Chip-Select Mask Register 4 */ + u32 cscr4; /* 0x38 Chip-Select Control Register 4 */ + + u16 csar5; /* 0x3C Chip-Select Address Register 5 */ + u16 res5; + u32 csmr5; /* 0x40 Chip-Select Mask Register 5 */ + u32 cscr5; /* 0x44 Chip-Select Control Register 5 */ +} fbcs_t; + +/* FlexCan module registers */ +typedef struct can_ctrl { + u32 mcr; /* 0x00 Module Configuration register */ + u32 ctrl; /* 0x04 Control register */ + u32 timer; /* 0x08 Free Running Timer */ + u32 res1; /* 0x0C */ + u32 rxgmask; /* 0x10 Rx Global Mask */ + u32 rx14mask; /* 0x14 RxBuffer 14 Mask */ + u32 rx15mask; /* 0x18 RxBuffer 15 Mask */ + u32 errcnt; /* 0x1C Error Counter Register */ + u32 errstat; /* 0x20 Error and status Register */ + u32 res2; /* 0x24 */ + u32 imask; /* 0x28 Interrupt Mask Register */ + u32 res3; /* 0x2C */ + u32 iflag; /* 0x30 Interrupt Flag Register */ + u32 res4[19]; /* 0x34 - 0x7F */ + u32 MB0_15[2048]; /* 0x80 Message Buffer 0-15 */ +} can_t; + +/* System Control Module register 3 */ +typedef struct scm3_ctrl { + u8 res1[19]; /* 0x00 - 0x12 */ + u8 wcr; /* 0x13 wakeup control register */ + u16 res2; /* 0x14 - 0x15 */ + u16 cwcr; /* 0x16 Core Watchdog Control Register */ + u8 res3[3]; /* 0x18 - 0x1A */ + u8 cwsr; /* 0x1B Core Watchdog Service Register */ + u8 res4[2]; /* 0x1C - 0x1D */ + u8 scmisr; /* 0x1F Interrupt Status Register */ + u32 res5; /* 0x20 */ + u32 bcr; /* 0x24 Burst Configuration Register */ + u32 res6[18]; /* 0x28 - 0x6F */ + u32 cfadr; /* 0x70 Core Fault Address Register */ + u8 res7[4]; /* 0x71 - 0x74 */ + u8 cfier; /* 0x75 Core Fault Interrupt Enable Register */ + u8 cfloc; /* 0x76 Core Fault Location Register */ + u8 cfatr; /* 0x77 Core Fault Attributes Register */ + u32 res8; /* 0x78 */ + u32 cfdtr; /* 0x7C Core Fault Data Register */ +} scm3_t; + +/* eDMA module registers */ +typedef struct edma_ctrl { + u32 cr; /* 0x00 Control Register */ + u32 es; /* 0x04 Error Status Register */ + u16 res1[3]; /* 0x08 - 0x0D */ + u16 erq; /* 0x0E Enable Request Register */ + u16 res2[3]; /* 0x10 - 0x15 */ + u16 eei; /* 0x16 Enable Error Interrupt Request */ + u8 serq; /* 0x18 Set Enable Request */ + u8 cerq; /* 0x19 Clear Enable Request */ + u8 seei; /* 0x1A Set Enable Error Interrupt Request */ + u8 ceei; /* 0x1B Clear Enable Error Interrupt Request */ + u8 cint; /* 0x1C Clear Interrupt Enable Register */ + u8 cerr; /* 0x1D Clear Error Register */ + u8 ssrt; /* 0x1E Set START Bit Register */ + u8 cdne; /* 0x1F Clear DONE Status Bit Register */ + u16 res3[3]; /* 0x20 - 0x25 */ + u16 intr; /* 0x26 Interrupt Request Register */ + u16 res4[3]; /* 0x28 - 0x2D */ + u16 err; /* 0x2E Error Register */ + u32 res5[52]; /* 0x30 - 0xFF */ + u8 dchpri0; /* 0x100 Channel 0 Priority Register */ + u8 dchpri1; /* 0x101 Channel 1 Priority Register */ + u8 dchpri2; /* 0x102 Channel 2 Priority Register */ + u8 dchpri3; /* 0x103 Channel 3 Priority Register */ + u8 dchpri4; /* 0x104 Channel 4 Priority Register */ + u8 dchpri5; /* 0x105 Channel 5 Priority Register */ + u8 dchpri6; /* 0x106 Channel 6 Priority Register */ + u8 dchpri7; /* 0x107 Channel 7 Priority Register */ + u8 dchpri8; /* 0x108 Channel 8 Priority Register */ + u8 dchpri9; /* 0x109 Channel 9 Priority Register */ + u8 dchpri10; /* 0x110 Channel 10 Priority Register */ + u8 dchpri11; /* 0x111 Channel 11 Priority Register */ + u8 dchpri12; /* 0x112 Channel 12 Priority Register */ + u8 dchpri13; /* 0x113 Channel 13 Priority Register */ + u8 dchpri14; /* 0x114 Channel 14 Priority Register */ + u8 dchpri15; /* 0x115 Channel 15 Priority Register */ +} edma_t; + +/* TCD - eDMA*/ +typedef struct tcd_ctrl { + u32 saddr; /* 0x00 Source Address */ + u16 attr; /* 0x04 Transfer Attributes */ + u16 soff; /* 0x06 Signed Source Address Offset */ + u32 nbytes; /* 0x08 Minor Byte Count */ + u32 slast; /* 0x0C Last Source Address Adjustment */ + u32 daddr; /* 0x10 Destination address */ + u16 citer; /* 0x14 Current Minor Loop Link, Major Loop Count */ + u16 doff; /* 0x16 Signed Destination Address Offset */ + u32 dlast_sga; /* 0x18 Last Destination Address Adjustment/Scatter Gather Address */ + u16 biter; /* 0x1C Beginning Minor Loop Link, Major Loop Count */ + u16 csr; /* 0x1E Control and Status */ +} tcd_st; + +typedef struct tcd_multiple { + tcd_st tcd[16]; +} tcd_t; + +/* Interrupt module registers */ +typedef struct int0_ctrl { + /* Interrupt Controller 0 */ + u32 iprh0; /* 0x00 Pending Register High */ + u32 iprl0; /* 0x04 Pending Register Low */ + u32 imrh0; /* 0x08 Mask Register High */ + u32 imrl0; /* 0x0C Mask Register Low */ + u32 frch0; /* 0x10 Force Register High */ + u32 frcl0; /* 0x14 Force Register Low */ + u16 res1; /* 0x18 - 0x19 */ + u16 icfg0; /* 0x1A Configuration Register */ + u8 simr0; /* 0x1C Set Interrupt Mask */ + u8 cimr0; /* 0x1D Clear Interrupt Mask */ + u8 clmask0; /* 0x1E Current Level Mask */ + u8 slmask; /* 0x1F Saved Level Mask */ + u32 res2[8]; /* 0x20 - 0x3F */ + u8 icr0[64]; /* 0x40 - 0x7F Control registers */ + u32 res3[24]; /* 0x80 - 0xDF */ + u8 swiack0; /* 0xE0 Software Interrupt Acknowledge */ + u8 res4[3]; /* 0xE1 - 0xE3 */ + u8 Lniack0_1; /* 0xE4 Level n interrupt acknowledge resister */ + u8 res5[3]; /* 0xE5 - 0xE7 */ + u8 Lniack0_2; /* 0xE8 Level n interrupt acknowledge resister */ + u8 res6[3]; /* 0xE9 - 0xEB */ + u8 Lniack0_3; /* 0xEC Level n interrupt acknowledge resister */ + u8 res7[3]; /* 0xED - 0xEF */ + u8 Lniack0_4; /* 0xF0 Level n interrupt acknowledge resister */ + u8 res8[3]; /* 0xF1 - 0xF3 */ + u8 Lniack0_5; /* 0xF4 Level n interrupt acknowledge resister */ + u8 res9[3]; /* 0xF5 - 0xF7 */ + u8 Lniack0_6; /* 0xF8 Level n interrupt acknowledge resister */ + u8 resa[3]; /* 0xF9 - 0xFB */ + u8 Lniack0_7; /* 0xFC Level n interrupt acknowledge resister */ + u8 resb[3]; /* 0xFD - 0xFF */ +} int0_t; + +typedef struct int1_ctrl { + /* Interrupt Controller 1 */ + u32 iprh1; /* 0x00 Pending Register High */ + u32 iprl1; /* 0x04 Pending Register Low */ + u32 imrh1; /* 0x08 Mask Register High */ + u32 imrl1; /* 0x0C Mask Register Low */ + u32 frch1; /* 0x10 Force Register High */ + u32 frcl1; /* 0x14 Force Register Low */ + u16 res1; /* 0x18 */ + u16 icfg1; /* 0x1A Configuration Register */ + u8 simr1; /* 0x1C Set Interrupt Mask */ + u8 cimr1; /* 0x1D Clear Interrupt Mask */ + u16 res2; /* 0x1E - 0x1F */ + u32 res3[8]; /* 0x20 - 0x3F */ + u8 icr1[64]; /* 0x40 - 0x7F */ + u32 res4[24]; /* 0x80 - 0xDF */ + u8 swiack1; /* 0xE0 Software Interrupt Acknowledge */ + u8 res5[3]; /* 0xE1 - 0xE3 */ + u8 Lniack1_1; /* 0xE4 Level n interrupt acknowledge resister */ + u8 res6[3]; /* 0xE5 - 0xE7 */ + u8 Lniack1_2; /* 0xE8 Level n interrupt acknowledge resister */ + u8 res7[3]; /* 0xE9 - 0xEB */ + u8 Lniack1_3; /* 0xEC Level n interrupt acknowledge resister */ + u8 res8[3]; /* 0xED - 0xEF */ + u8 Lniack1_4; /* 0xF0 Level n interrupt acknowledge resister */ + u8 res9[3]; /* 0xF1 - 0xF3 */ + u8 Lniack1_5; /* 0xF4 Level n interrupt acknowledge resister */ + u8 resa[3]; /* 0xF5 - 0xF7 */ + u8 Lniack1_6; /* 0xF8 Level n interrupt acknowledge resister */ + u8 resb[3]; /* 0xF9 - 0xFB */ + u8 Lniack1_7; /* 0xFC Level n interrupt acknowledge resister */ + u8 resc[3]; /* 0xFD - 0xFF */ +} int1_t; + +typedef struct intgack_ctrl1 { + /* Global IACK Registers */ + u8 swiack; /* 0xE0 Global Software Interrupt Acknowledge */ + u8 Lniack[7]; /* 0xE1 - 0xE7 Global Level 0 Interrupt Acknowledge */ +} intgack_t; + +/*I2C module registers */ +typedef struct i2c_ctrl { + u8 adr; /* 0x00 address register */ + u8 res1[3]; /* 0x01 - 0x03 */ + u8 fdr; /* 0x04 frequency divider register */ + u8 res2[3]; /* 0x05 - 0x07 */ + u8 cr; /* 0x08 control register */ + u8 res3[3]; /* 0x09 - 0x0B */ + u8 sr; /* 0x0C status register */ + u8 res4[3]; /* 0x0D - 0x0F */ + u8 dr; /* 0x10 data register */ + u8 res5[3]; /* 0x11 - 0x13 */ +} i2c_t; + +/* QSPI module registers */ +typedef struct qspi_ctrl { + u16 qmr; /* Mode register */ + u16 res1; + u16 qdlyr; /* Delay register */ + u16 res2; + u16 qwr; /* Wrap register */ + u16 res3; + u16 qir; /* Interrupt register */ + u16 res4; + u16 qar; /* Address register */ + u16 res5; + u16 qdr; /* Data register */ + u16 res6; +} qspi_t; + +/* PWM module registers */ +typedef struct pwm_ctrl { + u8 en; /* 0x00 PWM Enable Register */ + u8 pol; /* 0x01 Polarity Register */ + u8 clk; /* 0x02 Clock Select Register */ + u8 prclk; /* 0x03 Prescale Clock Select Register */ + u8 cae; /* 0x04 Center Align Enable Register */ + u8 ctl; /* 0x05 Control Register */ + u8 res1[2]; /* 0x06 - 0x07 */ + u8 scla; /* 0x08 Scale A register */ + u8 sclb; /* 0x09 Scale B register */ + u8 res2[2]; /* 0x0A - 0x0B */ + u8 cnt0; /* 0x0C Channel 0 Counter register */ + u8 cnt1; /* 0x0D Channel 1 Counter register */ + u8 cnt2; /* 0x0E Channel 2 Counter register */ + u8 cnt3; /* 0x0F Channel 3 Counter register */ + u8 cnt4; /* 0x10 Channel 4 Counter register */ + u8 cnt5; /* 0x11 Channel 5 Counter register */ + u8 cnt6; /* 0x12 Channel 6 Counter register */ + u8 cnt7; /* 0x13 Channel 7 Counter register */ + u8 per0; /* 0x14 Channel 0 Period register */ + u8 per1; /* 0x15 Channel 1 Period register */ + u8 per2; /* 0x16 Channel 2 Period register */ + u8 per3; /* 0x17 Channel 3 Period register */ + u8 per4; /* 0x18 Channel 4 Period register */ + u8 per5; /* 0x19 Channel 5 Period register */ + u8 per6; /* 0x1A Channel 6 Period register */ + u8 per7; /* 0x1B Channel 7 Period register */ + u8 dty0; /* 0x1C Channel 0 Duty register */ + u8 dty1; /* 0x1D Channel 1 Duty register */ + u8 dty2; /* 0x1E Channel 2 Duty register */ + u8 dty3; /* 0x1F Channel 3 Duty register */ + u8 dty4; /* 0x20 Channel 4 Duty register */ + u8 dty5; /* 0x21 Channel 5 Duty register */ + u8 dty6; /* 0x22 Channel 6 Duty register */ + u8 dty7; /* 0x23 Channel 7 Duty register */ + u8 sdn; /* 0x24 Shutdown register */ + u8 res3[3]; /* 0x25 - 0x27 */ +} pwm_t; + +/* Edge Port module registers */ +typedef struct eport_ctrl { + u16 par; /* 0x00 Pin Assignment Register */ + u8 ddar; /* 0x02 Data Direction Register */ + u8 ier; /* 0x03 Interrupt Enable Register */ + u8 dr; /* 0x04 Data Register */ + u8 pdr; /* 0x05 Pin Data Register */ + u8 fr; /* 0x06 Flag_Register */ + u8 res1; +} eport_t; + +/* Watchdog registers */ +typedef struct wdog_ctrl { + u16 cr; /* 0x00 Control register */ + u16 mr; /* 0x02 Modulus register */ + u16 cntr; /* 0x04 Count register */ + u16 sr; /* 0x06 Service register */ +} wdog_t; + +/*Chip configuration module registers */ +typedef struct ccm_ctrl { + u8 rstctrl; /* 0x00 Reset Controller register */ + u8 rststat; /* 0x01 Reset Status register */ + u16 res1; /* 0x02 - 0x03 */ + u16 ccr; /* 0x04 Chip configuration register */ + u16 res2; /* 0x06 */ + u16 rcon; /* 0x08 Rreset configuration register */ + u16 cir; /* 0x0A Chip identification register */ + u32 res3; /* 0x0C */ + u16 misccr; /* 0x10 Miscellaneous control register */ + u16 cdr; /* 0x12 Clock divider register */ + u16 uhcsr; /* 0x14 USB Host controller status register */ + u16 uocsr; /* 0x16 USB On-the-Go Controller Status Register */ +} ccm_t; + +/* GPIO port registers */ +typedef struct gpio_ctrl { + /* Port Output Data Registers */ + u8 podr_fech; /* 0x00 */ + u8 podr_fecl; /* 0x01 */ + u8 podr_ssi; /* 0x02 */ + u8 podr_busctl; /* 0x03 */ + u8 podr_be; /* 0x04 */ + u8 podr_cs; /* 0x05 */ + u8 podr_pwm; /* 0x06 */ + u8 podr_feci2c; /* 0x07 */ + u8 res1; /* 0x08 */ + u8 podr_uart; /* 0x09 */ + u8 podr_qspi; /* 0x0A */ + u8 podr_timer; /* 0x0B */ + u8 res2; /* 0x0C */ + u8 podr_lcddatah; /* 0x0D */ + u8 podr_lcddatam; /* 0x0E */ + u8 podr_lcddatal; /* 0x0F */ + u8 podr_lcdctlh; /* 0x10 */ + u8 podr_lcdctll; /* 0x11 */ + + /* Port Data Direction Registers */ + u16 res3; /* 0x12 - 0x13 */ + u8 pddr_fech; /* 0x14 */ + u8 pddr_fecl; /* 0x15 */ + u8 pddr_ssi; /* 0x16 */ + u8 pddr_busctl; /* 0x17 */ + u8 pddr_be; /* 0x18 */ + u8 pddr_cs; /* 0x19 */ + u8 pddr_pwm; /* 0x1A */ + u8 pddr_feci2c; /* 0x1B */ + u8 res4; /* 0x1C */ + u8 pddr_uart; /* 0x1D */ + u8 pddr_qspi; /* 0x1E */ + u8 pddr_timer; /* 0x1F */ + u8 res5; /* 0x20 */ + u8 pddr_lcddatah; /* 0x21 */ + u8 pddr_lcddatam; /* 0x22 */ + u8 pddr_lcddatal; /* 0x23 */ + u8 pddr_lcdctlh; /* 0x24 */ + u8 pddr_lcdctll; /* 0x25 */ + u16 res6; /* 0x26 - 0x27 */ + + /* Port Data Direction Registers */ + u8 ppd_fech; /* 0x28 */ + u8 ppd_fecl; /* 0x29 */ + u8 ppd_ssi; /* 0x2A */ + u8 ppd_busctl; /* 0x2B */ + u8 ppd_be; /* 0x2C */ + u8 ppd_cs; /* 0x2D */ + u8 ppd_pwm; /* 0x2E */ + u8 ppd_feci2c; /* 0x2F */ + u8 res7; /* 0x30 */ + u8 ppd_uart; /* 0x31 */ + u8 ppd_qspi; /* 0x32 */ + u8 ppd_timer; /* 0x33 */ + u8 res8; /* 0x34 */ + u8 ppd_lcddatah; /* 0x35 */ + u8 ppd_lcddatam; /* 0x36 */ + u8 ppd_lcddatal; /* 0x37 */ + u8 ppd_lcdctlh; /* 0x38 */ + u8 ppd_lcdctll; /* 0x39 */ + u16 res9; /* 0x3A - 0x3B */ + + /* Port Clear Output Data Registers */ + u8 pclrr_fech; /* 0x3C */ + u8 pclrr_fecl; /* 0x3D */ + u8 pclrr_ssi; /* 0x3E */ + u8 pclrr_busctl; /* 0x3F */ + u8 pclrr_be; /* 0x40 */ + u8 pclrr_cs; /* 0x41 */ + u8 pclrr_pwm; /* 0x42 */ + u8 pclrr_feci2c; /* 0x43 */ + u8 res10; /* 0x44 */ + u8 pclrr_uart; /* 0x45 */ + u8 pclrr_qspi; /* 0x46 */ + u8 pclrr_timer; /* 0x47 */ + u8 res11; /* 0x48 */ + u8 pclrr_lcddatah; /* 0x49 */ + u8 pclrr_lcddatam; /* 0x4A */ + u8 pclrr_lcddatal; /* 0x4B */ + u8 pclrr_lcdctlh; /* 0x4C */ + u8 pclrr_lcdctll; /* 0x4D */ + u16 res12; /* 0x4E - 0x4F */ + + /* Pin Assignment Registers */ + u8 par_fec; /* 0x50 */ + u8 par_pwm; /* 0x51 */ + u8 par_busctl; /* 0x52 */ + u8 par_feci2c; /* 0x53 */ + u8 par_be; /* 0x54 */ + u8 par_cs; /* 0x55 */ + u16 par_ssi; /* 0x56 */ + u16 par_uart; /* 0x58 */ + u16 par_qspi; /* 0x5A */ + u8 par_timer; /* 0x5C */ + u8 par_lcddata; /* 0x5D */ + u16 par_lcdctl; /* 0x5E */ + u16 par_irq; /* 0x60 */ + u16 res16; /* 0x62 - 0x63 */ + + /* Mode Select Control Registers */ + u8 mscr_flexbus; /* 0x64 */ + u8 mscr_sdram; /* 0x65 */ + u16 res17; /* 0x66 - 0x67 */ + + /* Drive Strength Control Registers */ + u8 dscr_i2c; /* 0x68 */ + u8 dscr_pwm; /* 0x69 */ + u8 dscr_fec; /* 0x6A */ + u8 dscr_uart; /* 0x6B */ + u8 dscr_qspi; /* 0x6C */ + u8 dscr_timer; /* 0x6D */ + u8 dscr_ssi; /* 0x6E */ + u8 dscr_lcd; /* 0x6F */ + u8 dscr_debug; /* 0x70 */ + u8 dscr_clkrst; /* 0x71 */ + u8 dscr_irq; /* 0x72 */ +} gpio_t; + +/* LCD module registers */ +typedef struct lcd_ctrl { + u32 ssar; /* 0x00 Screen Start Address Register */ + u32 sr; /* 0x04 LCD Size Register */ + u32 vpw; /* 0x08 Virtual Page Width Register */ + u32 cpr; /* 0x0C Cursor Position Register */ + u32 cwhb; /* 0x10 Cursor Width Height and Blink Register */ + u32 ccmr; /* 0x14 Color Cursor Mapping Register */ + u32 pcr; /* 0x18 Panel Configuration Register */ + u32 hcr; /* 0x1C Horizontal Configuration Register */ + u32 vcr; /* 0x20 Vertical Configuration Register */ + u32 por; /* 0x24 Panning Offset Register */ + u32 scr; /* 0x28 Sharp Configuration Register */ + u32 pccr; /* 0x2C PWM Contrast Control Register */ + u32 dcr; /* 0x30 DMA Control Register */ + u32 rmcr; /* 0x34 Refresh Mode Control Register */ + u32 icr; /* 0x38 Refresh Mode Control Register */ + u32 ier; /* 0x3C Interrupt Enable Register */ + u32 isr; /* 0x40 Interrupt Status Register */ + u32 res[4]; + u32 gwsar; /* 0x50 Graphic Window Start Address Register */ + u32 gwsr; /* 0x54 Graphic Window Size Register */ + u32 gwvpw; /* 0x58 Graphic Window Virtual Page Width Register */ + u32 gwpor; /* 0x5C Graphic Window Panning Offset Register */ + u32 gwpr; /* 0x60 Graphic Window Position Register */ + u32 gwcr; /* 0x64 Graphic Window Control Register */ + u32 gwdcr; /* 0x68 Graphic Window DMA Control Register */ +} lcd_t; + +typedef struct lcdbg_ctrl { + u32 bglut[255]; +} lcdbg_t; + +typedef struct lcdgw_ctrl { + u32 gwlut[255]; +} lcdgw_t; + +/* USB OTG module registers */ +typedef struct usb_otg { + u32 id; /* 0x000 Identification Register */ + u32 hwgeneral; /* 0x004 General HW Parameters */ + u32 hwhost; /* 0x008 Host HW Parameters */ + u32 hwdev; /* 0x00C Device HW parameters */ + u32 hwtxbuf; /* 0x010 TX Buffer HW Parameters */ + u32 hwrxbuf; /* 0x014 RX Buffer HW Parameters */ + u32 res1[58]; /* 0x18 - 0xFF */ + u8 caplength; /* 0x100 Capability Register Length */ + u8 res2; /* 0x101 */ + u16 hciver; /* 0x102 Host Interface Version Number */ + u32 hcsparams; /* 0x104 Host Structural Parameters */ + u32 hccparams; /* 0x108 Host Capability Parameters */ + u32 res3[5]; /* 0x10C - 0x11F */ + u16 dciver; /* 0x120 Device Interface Version Number */ + u16 res4; /* 0x122 */ + u32 dccparams; /* 0x124 Device Capability Parameters */ + u32 res5[6]; /* 0x128 - 0x13F */ + u32 cmd; /* 0x140 USB Command */ + u32 sts; /* 0x144 USB Status */ + u32 intr; /* 0x148 USB Interrupt Enable */ + u32 frindex; /* 0x14C USB Frame Index */ + u32 res6; /* 0x150 */ + u32 prd_dev; /* 0x154 Periodic Frame List Base or Device Address */ + u32 aync_ep; /* 0x158 Current Asynchronous List or Address at Endpoint List Address */ + u32 ttctrl; /* 0x15C Host TT Asynchronous Buffer Control */ + u32 burstsize; /* 0x160 Master Interface Data Burst Size */ + u32 txfill; /* 0x164 Host Transmit FIFO Tuning Control */ + u32 res7[6]; /* 0x168 - 0x17F */ + u32 cfgflag; /* 0x180 Configure Flag Register */ + u32 portsc1; /* 0x184 Port Status/Control */ + u32 res8[7]; /* 0x188 - 0x1A3 */ + u32 otgsc; /* 0x1A4 On The Go Status and Control */ + u32 mode; /* 0x1A8 USB mode register */ + u32 eptsetstat; /* 0x1AC Endpoint Setup status */ + u32 eptprime; /* 0x1B0 Endpoint initialization */ + u32 eptflush; /* 0x1B4 Endpoint de-initialize */ + u32 eptstat; /* 0x1B8 Endpoint status */ + u32 eptcomplete; /* 0x1BC Endpoint Complete */ + u32 eptctrl0; /* 0x1C0 Endpoint control 0 */ + u32 eptctrl1; /* 0x1C4 Endpoint control 1 */ + u32 eptctrl2; /* 0x1C8 Endpoint control 2 */ + u32 eptctrl3; /* 0x1CC Endpoint control 3 */ +} usbotg_t; + +/* USB Host module registers */ +typedef struct usb_host { + u32 id; /* 0x000 Identification Register */ + u32 hwgeneral; /* 0x004 General HW Parameters */ + u32 hwhost; /* 0x008 Host HW Parameters */ + u32 res1; /* 0x0C */ + u32 hwtxbuf; /* 0x010 TX Buffer HW Parameters */ + u32 hwrxbuf; /* 0x014 RX Buffer HW Parameters */ + u32 res2[58]; /* 0x18 - 0xFF */ + + /* Host Controller Capability Register */ + u8 caplength; /* 0x100 Capability Register Length */ + u8 res3; /* 0x101 */ + u16 hciver; /* 0x102 Host Interface Version Number */ + u32 hcsparams; /* 0x104 Host Structural Parameters */ + u32 hccparams; /* 0x108 Host Capability Parameters */ + u32 res4[13]; /* 0x10C - 0x13F */ + + /* Host Controller Operational Register */ + u32 cmd; /* 0x140 USB Command */ + u32 sts; /* 0x144 USB Status */ + u32 intr; /* 0x148 USB Interrupt Enable */ + u32 frindex; /* 0x14C USB Frame Index */ + u32 res5; /* 0x150 (ctrl segment register in EHCI spec) */ + u32 prdlst; /* 0x154 Periodic Frame List Base Address */ + u32 aynclst; /* 0x158 Current Asynchronous List Address */ + u32 ttctrl; /* 0x15C Host TT Asynchronous Buffer Control (non-ehci) */ + u32 burstsize; /* 0x160 Master Interface Data Burst Size (non-ehci) */ + u32 txfill; /* 0x164 Host Transmit FIFO Tuning Control (non-ehci) */ + u32 res6[6]; /* 0x168 - 0x17F */ + u32 cfgflag; /* 0x180 Configure Flag Register */ + u32 portsc1; /* 0x184 Port Status/Control */ + u32 res7[8]; /* 0x188 - 0x1A7 */ + + /* non-ehci registers */ + u32 mode; /* 0x1A8 USB mode register */ + u32 eptsetstat; /* 0x1AC Endpoint Setup status */ + u32 eptprime; /* 0x1B0 Endpoint initialization */ + u32 eptflush; /* 0x1B4 Endpoint de-initialize */ + u32 eptstat; /* 0x1B8 Endpoint status */ + u32 eptcomplete; /* 0x1BC Endpoint Complete */ + u32 eptctrl0; /* 0x1C0 Endpoint control 0 */ + u32 eptctrl1; /* 0x1C4 Endpoint control 1 */ + u32 eptctrl2; /* 0x1C8 Endpoint control 2 */ + u32 eptctrl3; /* 0x1CC Endpoint control 3 */ +} usbhost_t; + +/* SDRAM controller registers */ +typedef struct sdram_ctrl { + u32 mode; /* 0x00 Mode/Extended Mode register */ + u32 ctrl; /* 0x04 Control register */ + u32 cfg1; /* 0x08 Configuration register 1 */ + u32 cfg2; /* 0x0C Configuration register 2 */ + u32 res1[64]; /* 0x10 - 0x10F */ + u32 cs0; /* 0x110 Chip Select 0 Configuration */ + u32 cs1; /* 0x114 Chip Select 1 Configuration */ +} sdram_t; + +/* Synchronous serial interface */ +typedef struct ssi_ctrl { + u32 tx0; /* 0x00 Transmit Data Register 0 */ + u32 tx1; /* 0x04 Transmit Data Register 1 */ + u32 rx0; /* 0x08 Receive Data Register 0 */ + u32 rx1; /* 0x0C Receive Data Register 1 */ + u32 cr; /* 0x10 Control Register */ + u32 isr; /* 0x14 Interrupt Status Register */ + u32 ier; /* 0x18 Interrupt Enable Register */ + u32 tcr; /* 0x1C Transmit Configuration Register */ + u32 rcr; /* 0x20 Receive Configuration Register */ + u32 ccr; /* 0x24 Clock Control Register */ + u32 res1; /* 0x28 */ + u32 fcsr; /* 0x2C FIFO Control/Status Register */ + u32 res2[2]; /* 0x30 - 0x37 */ + u32 acr; /* 0x38 AC97 Control Register */ + u32 acadd; /* 0x3C AC97 Command Address Register */ + u32 acdat; /* 0x40 AC97 Command Data Register */ + u32 atag; /* 0x44 AC97 Tag Register */ + u32 tmask; /* 0x48 Transmit Time Slot Mask Register */ + u32 rmask; /* 0x4C Receive Time Slot Mask Register */ +} ssi_t; + +/* Clock Module registers */ +typedef struct pll_ctrl { + u8 podr; /* 0x00 Output Divider Register */ + u8 res1[3]; + u8 pcr; /* 0x04 Control Register */ + u8 res2[3]; + u8 pmdr; /* 0x08 Modulation Divider Register */ + u8 res3[3]; + u8 pfdr; /* 0x0C Feedback Divider Register */ + u8 res4[3]; +} pll_t; + +#endif /* __IMMAP_5329__ */ diff --git a/include/asm-m68k/io.h b/include/asm-m68k/io.h index 7bbdefba7..cec25d0bf 100644 --- a/include/asm-m68k/io.h +++ b/include/asm-m68k/io.h @@ -1,8 +1,214 @@ -#ifndef __ASM_M68K_IO_H_ -#define __ASM_M68K_IO_H_ +/* + * IO header file + * + * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ -static inline void sync(void) + #ifndef __ASM_M68K_IO_H__ +#define __ASM_M68K_IO_H__ + +#include + +#define readb(addr) in_8((volatile u8 *)(addr)) +#define writeb(b,addr) out_8((volatile u8 *)(addr), (b)) +#if !defined(__BIG_ENDIAN) +#define readw(addr) (*(volatile u16 *) (addr)) +#define readl(addr) (*(volatile u32 *) (addr)) +#define writew(b,addr) ((*(volatile u16 *) (addr)) = (b)) +#define writel(b,addr) ((*(volatile u32 *) (addr)) = (b)) +#else +#define readw(addr) in_le16((volatile u16 *)(addr)) +#define readl(addr) in_le32((volatile u32 *)(addr)) +#define writew(b,addr) out_le16((volatile u16 *)(addr),(b)) +#define writel(b,addr) out_le32((volatile u32 *)(addr),(b)) +#endif + +/* + * The insw/outsw/insl/outsl macros don't do byte-swapping. + * They are only used in practice for transferring buffers which + * are arrays of bytes, and byte-swapping is not appropriate in + * that case. - paulus + */ +#define insb(port, buf, ns) _insb((u8 *)((port)+_IO_BASE), (buf), (ns)) +#define outsb(port, buf, ns) _outsb((u8 *)((port)+_IO_BASE), (buf), (ns)) +#define insw(port, buf, ns) _insw_ns((u16 *)((port)+_IO_BASE), (buf), (ns)) +#define outsw(port, buf, ns) _outsw_ns((u16 *)((port)+_IO_BASE), (buf), (ns)) +#define insl(port, buf, nl) _insl_ns((u32 *)((port)+_IO_BASE), (buf), (nl)) +#define outsl(port, buf, nl) _outsl_ns((u32 *)((port)+_IO_BASE), (buf), (nl)) + +#define inb(port) in_8((u8 *)((port)+_IO_BASE)) +#define outb(val, port) out_8((u8 *)((port)+_IO_BASE), (val)) +#if !defined(__BIG_ENDIAN) +#define inw(port) in_be16((u16 *)((port)+_IO_BASE)) +#define outw(val, port) out_be16((u16 *)((port)+_IO_BASE), (val)) +#define inl(port) in_be32((u32 *)((port)+_IO_BASE)) +#define outl(val, port) out_be32((u32 *)((port)+_IO_BASE), (val)) +#else +#define inw(port) in_le16((u16 *)((port)+_IO_BASE)) +#define outw(val, port) out_le16((u16 *)((port)+_IO_BASE), (val)) +#define inl(port) in_le32((u32 *)((port)+_IO_BASE)) +#define outl(val, port) out_le32((u32 *)((port)+_IO_BASE), (val)) +#endif + +extern inline void _insb(volatile u8 * port, void *buf, int ns) { + u8 *data = (u8 *) buf; + while (ns--) + *data++ = *port; } -#endif /* __ASM_M68K_IO_H_ */ +extern inline void _outsb(volatile u8 * port, const void *buf, int ns) +{ + u8 *data = (u8 *) buf; + while (ns--) + *port = *data++; +} + +extern inline void _insw(volatile u16 * port, void *buf, int ns) +{ + u16 *data = (u16 *) buf; + while (ns--) + *data++ = __sw16(*port); +} + +extern inline void _outsw(volatile u16 * port, const void *buf, int ns) +{ + u16 *data = (u16 *) buf; + while (ns--) { + *port = __sw16(*data); + data++; + } +} + +extern inline void _insl(volatile u32 * port, void *buf, int nl) +{ + u32 *data = (u32 *) buf; + while (nl--) + *data++ = __sw32(*port); +} + +extern inline void _outsl(volatile u32 * port, const void *buf, int nl) +{ + u32 *data = (u32 *) buf; + while (nl--) { + *port = __sw32(*data); + data++; + } +} + +extern inline void _insw_ns(volatile u16 * port, void *buf, int ns) +{ + u16 *data = (u16 *) buf; + while (ns--) + *data++ = *port; +} + +extern inline void _outsw_ns(volatile u16 * port, const void *buf, int ns) +{ + u16 *data = (u16 *) buf; + while (ns--) { + *port = *data++; + } +} + +extern inline void _insl_ns(volatile u32 * port, void *buf, int nl) +{ + u32 *data = (u32 *) buf; + while (nl--) + *data++ = *port; +} + +extern inline void _outsl_ns(volatile u32 * port, const void *buf, int nl) +{ + u32 *data = (u32 *) buf; + while (nl--) { + *port = *data; + data++; + } +} + +/* + * The *_ns versions below don't do byte-swapping. + * Neither do the standard versions now, these are just here + * for older code. + */ +#define insw_ns(port, buf, ns) _insw_ns((u16 *)((port)+_IO_BASE), (buf), (ns)) +#define outsw_ns(port, buf, ns) _outsw_ns((u16 *)((port)+_IO_BASE), (buf), (ns)) +#define insl_ns(port, buf, nl) _insl_ns((u32 *)((port)+_IO_BASE), (buf), (nl)) +#define outsl_ns(port, buf, nl) _outsl_ns((u32 *)((port)+_IO_BASE), (buf), (nl)) + +#define IO_SPACE_LIMIT ~0 + +/* + * 8, 16 and 32 bit, big and little endian I/O operations, with barrier. + */ +extern inline int in_8(volatile u8 * addr) +{ + return (int)*addr; +} + +extern inline void out_8(volatile u8 * addr, int val) +{ + *addr = (u8) val; +} + +extern inline int in_le16(volatile u16 * addr) +{ + return __sw16(*addr); +} + +extern inline int in_be16(volatile u16 * addr) +{ + return (*addr & 0xFFFF); +} + +extern inline void out_le16(volatile u16 * addr, int val) +{ + *addr = __sw16(val); +} + +extern inline void out_be16(volatile u16 * addr, int val) +{ + *addr = (u16) val; +} + +extern inline unsigned in_le32(volatile u32 * addr) +{ + return __sw32(*addr); +} + +extern inline unsigned in_be32(volatile u32 * addr) +{ + return (*addr); +} + +extern inline void out_le32(volatile unsigned *addr, int val) +{ + *addr = __sw32(val); +} + +extern inline void out_be32(volatile unsigned *addr, int val) +{ + *addr = val; +} + +#endif /* __ASM_M68K_IO_H__ */ diff --git a/include/asm-m68k/m5329.h b/include/asm-m68k/m5329.h new file mode 100644 index 000000000..15bb121ed --- /dev/null +++ b/include/asm-m68k/m5329.h @@ -0,0 +1,2023 @@ +/* + * mcf5329.h -- Definitions for Freescale Coldfire 5329 + * + * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef mcf5329_h +#define mcf5329_h +/****************************************************************************/ + +/********************************************************************* +* System Control Module (SCM) +*********************************************************************/ +/* Bit definitions and macros for SCM_MPR */ +#define SCM_MPR_MPROT0(x) (((x)&0x0F)<<28) +#define SCM_MPR_MPROT1(x) (((x)&0x0F)<<24) +#define SCM_MPR_MPROT2(x) (((x)&0x0F)<<20) +#define SCM_MPR_MPROT4(x) (((x)&0x0F)<<12) +#define SCM_MPR_MPROT5(x) (((x)&0x0F)<<8) +#define SCM_MPR_MPROT6(x) (((x)&0x0F)<<4) +#define MPROT_MTR 4 +#define MPROT_MTW 2 +#define MPROT_MPL 1 + +/* Bit definitions and macros for SCM_BMT */ +#define BMT_BME (0x08) +#define BMT_8 (0x07) +#define BMT_16 (0x06) +#define BMT_32 (0x05) +#define BMT_64 (0x04) +#define BMT_128 (0x03) +#define BMT_256 (0x02) +#define BMT_512 (0x01) +#define BMT_1024 (0x00) + +/* Bit definitions and macros for SCM_PACRA */ +#define SCM_PACRA_PACR0(x) (((x)&0x0F)<<28) +#define SCM_PACRA_PACR1(x) (((x)&0x0F)<<24) +#define SCM_PACRA_PACR2(x) (((x)&0x0F)<<20) +#define PACR_SP 4 +#define PACR_WP 2 +#define PACR_TP 1 + +/* Bit definitions and macros for SCM_PACRB */ +#define SCM_PACRB_PACR8(x) (((x)&0x0F)<<28) +#define SCM_PACRB_PACR12(x) (((x)&0x0F)<<12) + +/* Bit definitions and macros for SCM_PACRC */ +#define SCM_PACRC_PACR16(x) (((x)&0x0F)<<28) +#define SCM_PACRC_PACR17(x) (((x)&0x0F)<<24) +#define SCM_PACRC_PACR18(x) (((x)&0x0F)<<20) +#define SCM_PACRC_PACR19(x) (((x)&0x0F)<<16) +#define SCM_PACRC_PACR21(x) (((x)&0x0F)<<8) +#define SCM_PACRC_PACR22(x) (((x)&0x0F)<<4) +#define SCM_PACRC_PACR23(x) (((x)&0x0F)<<0) + +/* Bit definitions and macros for SCM_PACRD */ +#define SCM_PACRD_PACR24(x) (((x)&0x0F)<<28) +#define SCM_PACRD_PACR25(x) (((x)&0x0F)<<24) +#define SCM_PACRD_PACR26(x) (((x)&0x0F)<<20) +#define SCM_PACRD_PACR28(x) (((x)&0x0F)<<12) +#define SCM_PACRD_PACR29(x) (((x)&0x0F)<<8) +#define SCM_PACRD_PACR30(x) (((x)&0x0F)<<4) +#define SCM_PACRD_PACR31(x) (((x)&0x0F)<<0) + +/* Bit definitions and macros for SCM_PACRE */ +#define SCM_PACRE_PACR32(x) (((x)&0x0F)<<28) +#define SCM_PACRE_PACR33(x) (((x)&0x0F)<<24) +#define SCM_PACRE_PACR34(x) (((x)&0x0F)<<20) +#define SCM_PACRE_PACR35(x) (((x)&0x0F)<<16) +#define SCM_PACRE_PACR36(x) (((x)&0x0F)<<12) +#define SCM_PACRE_PACR37(x) (((x)&0x0F)<<8) +#define SCM_PACRE_PACR38(x) (((x)&0x0F)<<4) + +/* Bit definitions and macros for SCM_PACRF */ +#define SCM_PACRF_PACR40(x) (((x)&0x0F)<<28) +#define SCM_PACRF_PACR41(x) (((x)&0x0F)<<24) +#define SCM_PACRF_PACR42(x) (((x)&0x0F)<<20) +#define SCM_PACRF_PACR43(x) (((x)&0x0F)<<16) +#define SCM_PACRF_PACR44(x) (((x)&0x0F)<<12) +#define SCM_PACRF_PACR45(x) (((x)&0x0F)<<8) +#define SCM_PACRF_PACR46(x) (((x)&0x0F)<<4) +#define SCM_PACRF_PACR47(x) (((x)&0x0F)<<0) + +/* Bit definitions and macros for SCM_PACRG */ +#define SCM_PACRG_PACR48(x) (((x)&0x0F)<<28) + +/* Bit definitions and macros for SCM_PACRH */ +#define SCM_PACRH_PACR56(x) (((x)&0x0F)<<28) +#define SCM_PACRH_PACR57(x) (((x)&0x0F)<<24) +#define SCM_PACRH_PACR58(x) (((x)&0x0F)<<20) + +/* PACRn Assignments */ +#define PACR0(x) SCM_PACRA_PACR0(x) +#define PACR1(x) SCM_PACRA_PACR1(x) +#define PACR2(x) SCM_PACRA_PACR2(x) +#define PACR8(x) SCM_PACRB_PACR8(x) +#define PACR12(x) SCM_PACRB_PACR12(x) +#define PACR16(x) SCM_PACRC_PACR16(x) +#define PACR17(x) SCM_PACRC_PACR17(x) +#define PACR18(x) SCM_PACRC_PACR18(x) +#define PACR19(x) SCM_PACRC_PACR19(x) +#define PACR21(x) SCM_PACRC_PACR21(x) +#define PACR22(x) SCM_PACRC_PACR22(x) +#define PACR23(x) SCM_PACRC_PACR23(x) +#define PACR24(x) SCM_PACRD_PACR24(x) +#define PACR25(x) SCM_PACRD_PACR25(x) +#define PACR26(x) SCM_PACRD_PACR26(x) +#define PACR28(x) SCM_PACRD_PACR28(x) +#define PACR29(x) SCM_PACRD_PACR29(x) +#define PACR30(x) SCM_PACRD_PACR30(x) +#define PACR31(x) SCM_PACRD_PACR31(x) +#define PACR32(x) SCM_PACRE_PACR32(x) +#define PACR33(x) SCM_PACRE_PACR33(x) +#define PACR34(x) SCM_PACRE_PACR34(x) +#define PACR35(x) SCM_PACRE_PACR35(x) +#define PACR36(x) SCM_PACRE_PACR36(x) +#define PACR37(x) SCM_PACRE_PACR37(x) +#define PACR38(x) SCM_PACRE_PACR38(x) +#define PACR40(x) SCM_PACRF_PACR40(x) +#define PACR41(x) SCM_PACRF_PACR41(x) +#define PACR42(x) SCM_PACRF_PACR42(x) +#define PACR43(x) SCM_PACRF_PACR43(x) +#define PACR44(x) SCM_PACRF_PACR44(x) +#define PACR45(x) SCM_PACRF_PACR45(x) +#define PACR46(x) SCM_PACRF_PACR46(x) +#define PACR47(x) SCM_PACRF_PACR47(x) +#define PACR48(x) SCM_PACRG_PACR48(x) +#define PACR56(x) SCM_PACRH_PACR56(x) +#define PACR57(x) SCM_PACRH_PACR57(x) +#define PACR58(x) SCM_PACRH_PACR58(x) + +/* Bit definitions and macros for SCM_CWCR */ +#define CWCR_RO (0x8000) +#define CWCR_CWR_WH (0x0100) +#define CWCR_CWE (0x0080) +#define CWRI_WINDOW (0x0060) +#define CWRI_RESET (0x0040) +#define CWRI_INT_RESET (0x0020) +#define CWRI_INT (0x0000) +#define CWCR_CWT(x) (((x)&0x001F)) + +/* Bit definitions and macros for SCM_ISR */ +#define SCMISR_CFEI (0x02) +#define SCMISR_CWIC (0x01) + +/* Bit definitions and macros for SCM_BCR */ +#define BCR_GBR (0x00000200) +#define BCR_GBW (0x00000100) +#define BCR_S7 (0x00000080) +#define BCR_S6 (0x00000040) +#define BCR_S4 (0x00000010) +#define BCR_S1 (0x00000002) + +/* Bit definitions and macros for SCM_CFIER */ +#define CFIER_ECFEI (0x01) + +/* Bit definitions and macros for SCM_CFLOC */ +#define CFLOC_LOC (0x80) + +/* Bit definitions and macros for SCM_CFATR */ +#define CFATR_WRITE (0x80) +#define CFATR_SZ32 (0x20) +#define CFATR_SZ16 (0x10) +#define CFATR_SZ08 (0x00) +#define CFATR_CACHE (0x08) +#define CFATR_MODE (0x02) +#define CFATR_TYPE (0x01) + +/********************************************************************* +* +* Random Number Generator (RNG) +* +*********************************************************************/ +/* Bit definitions and macros for RNG_RNGCR */ +#define RNGCR_CI (0x00000008) +#define RNGCR_IM (0x00000004) +#define RNGCR_HA (0x00000002) +#define RNGCR_GO (0x00000001) + +/* Bit definitions and macros for RNG_RNGSR */ +#define RNGSR_OFS(x) (((x)&0xFF)<<16) +#define RNGSR_OFL(x) (((x)&0xFF)<<8) +#define RNGSR_EI (0x00000008) +#define RNGSR_FUF (0x00000004) +#define RNGSR_LRS (0x00000002) +#define RNGSR_SV (0x00000001) + +/********************************************************************* +* FlexBus Chip Selects (FBCS) +*********************************************************************/ +/* Bit definitions and macros for FBCS_CSAR */ +#define CSAR_BA(x) (((x)&0xFFFF)<<16) + +/* Bit definitions and macros for FBCS_CSMR */ +#define CSMR_BAM(x) (((x)&0xFFFF)<<16) +#define CSMR_BAM_4G (0xFFFF0000) +#define CSMR_BAM_2G (0x7FFF0000) +#define CSMR_BAM_1G (0x3FFF0000) +#define CSMR_BAM_1024M (0x3FFF0000) +#define CSMR_BAM_512M (0x1FFF0000) +#define CSMR_BAM_256M (0x0FFF0000) +#define CSMR_BAM_128M (0x07FF0000) +#define CSMR_BAM_64M (0x03FF0000) +#define CSMR_BAM_32M (0x01FF0000) +#define CSMR_BAM_16M (0x00FF0000) +#define CSMR_BAM_8M (0x007F0000) +#define CSMR_BAM_4M (0x003F0000) +#define CSMR_BAM_2M (0x001F0000) +#define CSMR_BAM_1M (0x000F0000) +#define CSMR_BAM_1024K (0x000F0000) +#define CSMR_BAM_512K (0x00070000) +#define CSMR_BAM_256K (0x00030000) +#define CSMR_BAM_128K (0x00010000) +#define CSMR_BAM_64K (0x00000000) +#define CSMR_WP (0x00000100) +#define CSMR_V (0x00000001) + +/* Bit definitions and macros for FBCS_CSCR */ +#define CSCR_SWS(x) (((x)&0x3F)<<26) +#define CSCR_ASET(x) (((x)&0x03)<<20) +#define CSCR_SWSEN (0x00800000) +#define CSCR_ASET_4CLK (0x00300000) +#define CSCR_ASET_3CLK (0x00200000) +#define CSCR_ASET_2CLK (0x00100000) +#define CSCR_ASET_1CLK (0x00000000) +#define CSCR_RDAH(x) (((x)&0x03)<<18) +#define CSCR_RDAH_4CYC (0x000C0000) +#define CSCR_RDAH_3CYC (0x00080000) +#define CSCR_RDAH_2CYC (0x00040000) +#define CSCR_RDAH_1CYC (0x00000000) +#define CSCR_WRAH(x) (((x)&0x03)<<16) +#define CSCR_WDAH_4CYC (0x00003000) +#define CSCR_WDAH_3CYC (0x00002000) +#define CSCR_WDAH_2CYC (0x00001000) +#define CSCR_WDAH_1CYC (0x00000000) +#define CSCR_WS(x) (((x)&0x3F)<<10) +#define CSCR_SBM (0x00000200) +#define CSCR_AA (0x00000100) +#define CSCR_PS_MASK (0x000000C0) +#define CSCR_PS_32 (0x00000000) +#define CSCR_PS_16 (0x00000080) +#define CSCR_PS_8 (0x00000040) +#define CSCR_BEM (0x00000020) +#define CSCR_BSTR (0x00000010) +#define CSCR_BSTW (0x00000008) + +/********************************************************************* +* FlexCAN Module (CAN) +*********************************************************************/ +/* Bit definitions and macros for CAN_CANMCR */ +#define CANMCR_MDIS (0x80000000) +#define CANMCR_FRZ (0x40000000) +#define CANMCR_HALT (0x10000000) +#define CANMCR_NORDY (0x08000000) +#define CANMCR_SOFTRST (0x02000000) +#define CANMCR_FRZACK (0x01000000) +#define CANMCR_SUPV (0x00800000) +#define CANMCR_LPMACK (0x00100000) +#define CANMCR_MAXMB(x) (((x)&0x0F)) + +/* Bit definitions and macros for CAN_CANCTRL */ +#define CANCTRL_PRESDIV(x) (((x)&0xFF)<<24) +#define CANCTRL_RJW(x) (((x)&0x03)<<22) +#define CANCTRL_PSEG1(x) (((x)&0x07)<<19) +#define CANCTRL_PSEG2(x) (((x)&0x07)<<16) +#define CANCTRL_BOFFMSK (0x00008000) +#define CANCTRL_ERRMSK (0x00004000) +#define CANCTRL_CLKSRC (0x00002000) +#define CANCTRL_LPB (0x00001000) +#define CANCTRL_SMP (0x00000080) +#define CANCTRL_BOFFREC (0x00000040) +#define CANCTRL_TSYNC (0x00000020) +#define CANCTRL_LBUF (0x00000010) +#define CANCTRL_LOM (0x00000008) +#define CANCTRL_PROPSEG(x) (((x)&0x07)) + +/* Bit definitions and macros for CAN_TIMER */ +#define TIMER_TIMER(x) ((x)&0xFFFF) + +/* Bit definitions and macros for CAN_RXGMASK */ +#define RXGMASK_MI(x) ((x)&0x1FFFFFFF) + +/* Bit definitions and macros for CAN_ERRCNT */ +#define ERRCNT_TXECTR(x) (((x)&0xFF)) +#define ERRCNT_RXECTR(x) (((x)&0xFF)<<8) + +/* Bit definitions and macros for CAN_ERRSTAT */ +#define ERRSTAT_BITERR1 (0x00008000) +#define ERRSTAT_BITERR0 (0x00004000) +#define ERRSTAT_ACKERR (0x00002000) +#define ERRSTAT_CRCERR (0x00001000) +#define ERRSTAT_FRMERR (0x00000800) +#define ERRSTAT_STFERR (0x00000400) +#define ERRSTAT_TXWRN (0x00000200) +#define ERRSTAT_RXWRN (0x00000100) +#define ERRSTAT_IDLE (0x00000080) +#define ERRSTAT_TXRX (0x00000040) +#define ERRSTAT_FLT_BUSOFF (0x00000020) +#define ERRSTAT_FLT_PASSIVE (0x00000010) +#define ERRSTAT_FLT_ACTIVE (0x00000000) +#define ERRSTAT_BOFFINT (0x00000004) +#define ERRSTAT_ERRINT (0x00000002) +#define ERRSTAT_WAKINT (0x00000001) + +/* Bit definitions and macros for CAN_IMASK */ +#define IMASK_BUF15M (0x00008000) +#define IMASK_BUF14M (0x00004000) +#define IMASK_BUF13M (0x00002000) +#define IMASK_BUF12M (0x00001000) +#define IMASK_BUF11M (0x00000800) +#define IMASK_BUF10M (0x00000400) +#define IMASK_BUF9M (0x00000200) +#define IMASK_BUF8M (0x00000100) +#define IMASK_BUF7M (0x00000080) +#define IMASK_BUF6M (0x00000040) +#define IMASK_BUF5M (0x00000020) +#define IMASK_BUF4M (0x00000010) +#define IMASK_BUF3M (0x00000008) +#define IMASK_BUF2M (0x00000004) +#define IMASK_BUF1M (0x00000002) +#define IMASK_BUF0M (0x00000001) + +/* Bit definitions and macros for CAN_IFLAG */ +#define IFLAG_BUF15I (0x00008000) +#define IFLAG_BUF14I (0x00004000) +#define IFLAG_BUF13I (0x00002000) +#define IFLAG_BUF12I (0x00001000) +#define IFLAG_BUF11I (0x00000800) +#define IFLAG_BUF10I (0x00000400) +#define IFLAG_BUF9I (0x00000200) +#define IFLAG_BUF8I (0x00000100) +#define IFLAG_BUF7I (0x00000080) +#define IFLAG_BUF6I (0x00000040) +#define IFLAG_BUF5I (0x00000020) +#define IFLAG_BUF4I (0x00000010) +#define IFLAG_BUF3I (0x00000008) +#define IFLAG_BUF2I (0x00000004) +#define IFLAG_BUF1I (0x00000002) +#define IFLAG_BUF0I (0x00000001) + +/********************************************************************* +* Interrupt Controller (INTC) +*********************************************************************/ +#define INTC0_EPORT INTC_IPRL_INT1 + +#define INT0_LO_RSVD0 (0) +#define INT0_LO_EPORT1 (1) +#define INT0_LO_EPORT2 (2) +#define INT0_LO_EPORT3 (3) +#define INT0_LO_EPORT4 (4) +#define INT0_LO_EPORT5 (5) +#define INT0_LO_EPORT6 (6) +#define INT0_LO_EPORT7 (7) +#define INT0_LO_EDMA_00 (8) +#define INT0_LO_EDMA_01 (9) +#define INT0_LO_EDMA_02 (10) +#define INT0_LO_EDMA_03 (11) +#define INT0_LO_EDMA_04 (12) +#define INT0_LO_EDMA_05 (13) +#define INT0_LO_EDMA_06 (14) +#define INT0_LO_EDMA_07 (15) +#define INT0_LO_EDMA_08 (16) +#define INT0_LO_EDMA_09 (17) +#define INT0_LO_EDMA_10 (18) +#define INT0_LO_EDMA_11 (19) +#define INT0_LO_EDMA_12 (20) +#define INT0_LO_EDMA_13 (21) +#define INT0_LO_EDMA_14 (22) +#define INT0_LO_EDMA_15 (23) +#define INT0_LO_EDMA_ERR (24) +#define INT0_LO_SCM (25) +#define INT0_LO_UART0 (26) +#define INT0_LO_UART1 (27) +#define INT0_LO_UART2 (28) +#define INT0_LO_RSVD1 (29) +#define INT0_LO_I2C (30) +#define INT0_LO_QSPI (31) +#define INT0_HI_DTMR0 (32) +#define INT0_HI_DTMR1 (33) +#define INT0_HI_DTMR2 (34) +#define INT0_HI_DTMR3 (35) +#define INT0_HI_FEC_TXF (36) +#define INT0_HI_FEC_TXB (37) +#define INT0_HI_FEC_UN (38) +#define INT0_HI_FEC_RL (39) +#define INT0_HI_FEC_RXF (40) +#define INT0_HI_FEC_RXB (41) +#define INT0_HI_FEC_MII (42) +#define INT0_HI_FEC_LC (43) +#define INT0_HI_FEC_HBERR (44) +#define INT0_HI_FEC_GRA (45) +#define INT0_HI_FEC_EBERR (46) +#define INT0_HI_FEC_BABT (47) +#define INT0_HI_FEC_BABR (48) +/* 49 - 61 Reserved */ +#define INT0_HI_SCM (62) + +/*#define INT1_HI_ */ + +/* Bit definitions and macros for INTC_IPRH */ +#define INTC_IPRH_INT63 (0x80000000) +#define INTC_IPRH_INT62 (0x40000000) +#define INTC_IPRH_INT61 (0x20000000) +#define INTC_IPRH_INT60 (0x10000000) +#define INTC_IPRH_INT59 (0x08000000) +#define INTC_IPRH_INT58 (0x04000000) +#define INTC_IPRH_INT57 (0x02000000) +#define INTC_IPRH_INT56 (0x01000000) +#define INTC_IPRH_INT55 (0x00800000) +#define INTC_IPRH_INT54 (0x00400000) +#define INTC_IPRH_INT53 (0x00200000) +#define INTC_IPRH_INT52 (0x00100000) +#define INTC_IPRH_INT51 (0x00080000) +#define INTC_IPRH_INT50 (0x00040000) +#define INTC_IPRH_INT49 (0x00020000) +#define INTC_IPRH_INT48 (0x00010000) +#define INTC_IPRH_INT47 (0x00008000) +#define INTC_IPRH_INT46 (0x00004000) +#define INTC_IPRH_INT45 (0x00002000) +#define INTC_IPRH_INT44 (0x00001000) +#define INTC_IPRH_INT43 (0x00000800) +#define INTC_IPRH_INT42 (0x00000400) +#define INTC_IPRH_INT41 (0x00000200) +#define INTC_IPRH_INT40 (0x00000100) +#define INTC_IPRH_INT39 (0x00000080) +#define INTC_IPRH_INT38 (0x00000040) +#define INTC_IPRH_INT37 (0x00000020) +#define INTC_IPRH_INT36 (0x00000010) +#define INTC_IPRH_INT35 (0x00000008) +#define INTC_IPRH_INT34 (0x00000004) +#define INTC_IPRH_INT33 (0x00000002) +#define INTC_IPRH_INT32 (0x00000001) + +/* Bit definitions and macros for INTC_IPRL */ +#define INTC_IPRL_INT31 (0x80000000) +#define INTC_IPRL_INT30 (0x40000000) +#define INTC_IPRL_INT29 (0x20000000) +#define INTC_IPRL_INT28 (0x10000000) +#define INTC_IPRL_INT27 (0x08000000) +#define INTC_IPRL_INT26 (0x04000000) +#define INTC_IPRL_INT25 (0x02000000) +#define INTC_IPRL_INT24 (0x01000000) +#define INTC_IPRL_INT23 (0x00800000) +#define INTC_IPRL_INT22 (0x00400000) +#define INTC_IPRL_INT21 (0x00200000) +#define INTC_IPRL_INT20 (0x00100000) +#define INTC_IPRL_INT19 (0x00080000) +#define INTC_IPRL_INT18 (0x00040000) +#define INTC_IPRL_INT17 (0x00020000) +#define INTC_IPRL_INT16 (0x00010000) +#define INTC_IPRL_INT15 (0x00008000) +#define INTC_IPRL_INT14 (0x00004000) +#define INTC_IPRL_INT13 (0x00002000) +#define INTC_IPRL_INT12 (0x00001000) +#define INTC_IPRL_INT11 (0x00000800) +#define INTC_IPRL_INT10 (0x00000400) +#define INTC_IPRL_INT9 (0x00000200) +#define INTC_IPRL_INT8 (0x00000100) +#define INTC_IPRL_INT7 (0x00000080) +#define INTC_IPRL_INT6 (0x00000040) +#define INTC_IPRL_INT5 (0x00000020) +#define INTC_IPRL_INT4 (0x00000010) +#define INTC_IPRL_INT3 (0x00000008) +#define INTC_IPRL_INT2 (0x00000004) +#define INTC_IPRL_INT1 (0x00000002) +#define INTC_IPRL_INT0 (0x00000001) + +/* Bit definitions and macros for INTC_ICONFIG */ +#define INTC_ICFG_ELVLPRI7 (0x8000) +#define INTC_ICFG_ELVLPRI6 (0x4000) +#define INTC_ICFG_ELVLPRI5 (0x2000) +#define INTC_ICFG_ELVLPRI4 (0x1000) +#define INTC_ICFG_ELVLPRI3 (0x0800) +#define INTC_ICFG_ELVLPRI2 (0x0400) +#define INTC_ICFG_ELVLPRI1 (0x0200) +#define INTC_ICFG_EMASK (0x0020) + +/* Bit definitions and macros for INTC_SIMR */ +#define INTC_SIMR_SALL (0x40) +#define INTC_SIMR_SIMR(x) ((x)&0x3F) + +/* Bit definitions and macros for INTC_CIMR */ +#define INTC_CIMR_CALL (0x40) +#define INTC_CIMR_CIMR(x) ((x)&0x3F) + +/* Bit definitions and macros for INTC_CLMASK */ +#define INTC_CLMASK_CLMASK(x) ((x)&0x0F) + +/* Bit definitions and macros for INTC_SLMASK */ +#define INTC_SLMASK_SLMASK(x) ((x)&0x0F) + +/* Bit definitions and macros for INTC_ICR */ +#define INTC_ICR_IL(x) ((x)&0x07) + +/********************************************************************* +* I2C Module (I2C) +*********************************************************************/ +/* Bit definitions and macros for I2C_AR */ +#define I2C_AR_ADR(x) (((x)&0x7F)<<1) + +/* Bit definitions and macros for I2C_FDR */ +#define I2C_FDR_IC(x) ((x)&0x3F) + +/* Bit definitions and macros for I2C_CR */ +#define I2C_CR_IEN (0x80) +#define I2C_CR_IIEN (0x40) +#define I2C_CR_MSTA (0x20) +#define I2C_CR_MTX (0x10) +#define I2C_CR_TXAK (0x08) +#define I2C_CR_RSTA (0x04) + +/* Bit definitions and macros for I2C_SR */ +#define I2C_SR_ICF (0x80) +#define I2C_SR_IAAS (0x40) +#define I2C_SR_IBB (0x20) +#define I2C_SR_IAL (0x10) +#define I2C_SR_SRW (0x04) +#define I2C_SR_IIF (0x02) +#define I2C_SR_RXAK (0x01) + +/* Bit definitions and macros for I2C_ICR */ +#define I2C_ICR_BNBE (0x08) +#define I2C_ICR_TE (0x04) +#define I2C_ICR_RE (0x02) +#define I2C_ICR_IE (0x01) + +/********************************************************************* +* Queued Serial Peripheral Interface (QSPI) +*********************************************************************/ +/* Bit definitions and macros for QSPI_QMR */ +#define QSPI_QMR_MSTR (0x8000) +#define QSPI_QMR_DOHIE (0x4000) +#define QSPI_QMR_BITS(x) (((x)&0x000F)<<10) +#define QSPI_QMR_CPOL (0x0200) +#define QSPI_QMR_CPHA (0x0100) +#define QSPI_QMR_BAUD(x) ((x)&0x00FF) + +/* Bit definitions and macros for QSPI_QDLYR */ +#define QSPI_QDLYR_SPE (0x8000) +#define QSPI_QDLYR_QCD(x) (((x)&0x007F)<<8) +#define QSPI_QDLYR_DTL(x) ((x)&0x00FF) + +/* Bit definitions and macros for QSPI_QWR */ +#define QSPI_QWR_NEWQP(x) ((x)&0x000F) +#define QSPI_QWR_ENDQP(x) (((x)&0x000F)<<8) +#define QSPI_QWR_CSIV (0x1000) +#define QSPI_QWR_WRTO (0x2000) +#define QSPI_QWR_WREN (0x4000) +#define QSPI_QWR_HALT (0x8000) + +/* Bit definitions and macros for QSPI_QIR */ +#define QSPI_QIR_WCEFB (0x8000) +#define QSPI_QIR_ABRTB (0x4000) +#define QSPI_QIR_ABRTL (0x1000) +#define QSPI_QIR_WCEFE (0x0800) +#define QSPI_QIR_ABRTE (0x0400) +#define QSPI_QIR_SPIFE (0x0100) +#define QSPI_QIR_WCEF (0x0008) +#define QSPI_QIR_ABRT (0x0004) +#define QSPI_QIR_SPIF (0x0001) + +/* Bit definitions and macros for QSPI_QAR */ +#define QSPI_QAR_ADDR(x) ((x)&0x003F) +#define QSPI_QAR_TRANS (0x0000) +#define QSPI_QAR_RECV (0x0010) +#define QSPI_QAR_CMD (0x0020) + +/* Bit definitions and macros for QSPI_QDR */ +#define QSPI_QDR_CONT (0x8000) +#define QSPI_QDR_BITSE (0x4000) +#define QSPI_QDR_DT (0x2000) +#define QSPI_QDR_DSCK (0x1000) +#define QSPI_QDR_QSPI_CS3 (0x0800) +#define QSPI_QDR_QSPI_CS2 (0x0400) +#define QSPI_QDR_QSPI_CS1 (0x0200) +#define QSPI_QDR_QSPI_CS0 (0x0100) + +/********************************************************************* +* Pulse Width Modulation (PWM) +*********************************************************************/ +/* Bit definitions and macros for PWM_E */ +#define PWM_EN_PWME7 (0x80) +#define PWM_EN_PWME5 (0x20) +#define PWM_EN_PWME3 (0x08) +#define PWM_EN_PWME1 (0x02) + +/* Bit definitions and macros for PWM_POL */ +#define PWM_POL_PPOL7 (0x80) +#define PWM_POL_PPOL5 (0x20) +#define PWM_POL_PPOL3 (0x08) +#define PWM_POL_PPOL1 (0x02) + +/* Bit definitions and macros for PWM_CLK */ +#define PWM_CLK_PCLK7 (0x80) +#define PWM_CLK_PCLK5 (0x20) +#define PWM_CLK_PCLK3 (0x08) +#define PWM_CLK_PCLK1 (0x02) + +/* Bit definitions and macros for PWM_PRCLK */ +#define PWM_PRCLK_PCKB(x) (((x)&0x07)<<4) +#define PWM_PRCLK_PCKA(x) ((x)&0x07) + +/* Bit definitions and macros for PWM_CAE */ +#define PWM_CAE_CAE7 (0x80) +#define PWM_CAE_CAE5 (0x20) +#define PWM_CAE_CAE3 (0x08) +#define PWM_CAE_CAE1 (0x02) + +/* Bit definitions and macros for PWM_CTL */ +#define PWM_CTL_CON67 (0x80) +#define PWM_CTL_CON45 (0x40) +#define PWM_CTL_CON23 (0x20) +#define PWM_CTL_CON01 (0x10) +#define PWM_CTL_PSWAR (0x08) +#define PWM_CTL_PFRZ (0x04) + +/* Bit definitions and macros for PWM_SDN */ +#define PWM_SDN_IF (0x80) +#define PWM_SDN_IE (0x40) +#define PWM_SDN_RESTART (0x20) +#define PWM_SDN_LVL (0x10) +#define PWM_SDN_PWM7IN (0x04) +#define PWM_SDN_PWM7IL (0x02) +#define PWM_SDN_SDNEN (0x01) + +/********************************************************************* +* Watchdog Timer Modules (WTM) +*********************************************************************/ +/* Bit definitions and macros for WTM_WCR */ +#define WTM_WCR_WAIT (0x0008) +#define WTM_WCR_DOZE (0x0004) +#define WTM_WCR_HALTED (0x0002) +#define WTM_WCR_EN (0x0001) + +/********************************************************************* +* Chip Configuration Module (CCM) +*********************************************************************/ +/* Bit definitions and macros for CCM_CCR */ +#define CCM_CCR_CSC(x) (((x)&0x0003)<<8|0x0001) +#define CCM_CCR_LIMP (0x0041) +#define CCM_CCR_LOAD (0x0021) +#define CCM_CCR_BOOTPS(x) (((x)&0x0003)<<3|0x0001) +#define CCM_CCR_OSC_MODE (0x0005) +#define CCM_CCR_PLL_MODE (0x0003) +#define CCM_CCR_RESERVED (0x0001) + +/* Bit definitions and macros for CCM_RCON */ +#define CCM_RCON_CSC(x) (((x)&0x0003)<<8|0x0001) +#define CCM_RCON_LIMP (0x0041) +#define CCM_RCON_LOAD (0x0021) +#define CCM_RCON_BOOTPS(x) (((x)&0x0003)<<3|0x0001) +#define CCM_RCON_OSC_MODE (0x0005) +#define CCM_RCON_PLL_MODE (0x0003) +#define CCM_RCON_RESERVED (0x0001) + +/* Bit definitions and macros for CCM_CIR */ +#define CCM_CIR_PIN(x) (((x)&0x03FF)<<6) +#define CCM_CIR_PRN(x) ((x)&0x003F) + +/* Bit definitions and macros for CCM_MISCCR */ +#define CCM_MISCCR_PLL_LOCK (0x2000) +#define CCM_MISCCR_LIMP (0x1000) +#define CCM_MISCCR_LCD_CHEN (0x0100) +#define CCM_MISCCR_SSI_PUE (0x0080) +#define CCM_MISCCR_SSI_PUS (0x0040) +#define CCM_MISCCR_TIM_DMA (0x0020) +#define CCM_MISCCR_SSI_SRC (0x0010) +#define CCM_MISCCR_USBDIV (0x0002) +#define CCM_MISCCR_USBSRC (0x0001) + +/* Bit definitions and macros for CCM_CDR */ +#define CCM_CDR_LPDIV(x) (((x)&0x000F)<<8) +#define CCM_CDR_SSIDIV(x) ((x)&0x000F) + +/* Bit definitions and macros for CCM_UHCSR */ +#define CCM_UHCSR_PORTIND(x) (((x)&0x0003)<<14) +#define CCM_UHCSR_WKUP (0x0004) +#define CCM_UHCSR_UHMIE (0x0002) +#define CCM_UHCSR_XPDE (0x0001) + +/* Bit definitions and macros for CCM_UOCSR */ +#define CCM_UOCSR_PORTIND(x) (((x)&0x0003)<<14) +#define CCM_UOCSR_DPPD (0x2000) +#define CCM_UOCSR_DMPD (0x1000) +#define CCM_UOCSR_DRV_VBUS (0x0800) +#define CCM_UOCSR_CRG_VBUS (0x0400) +#define CCM_UOCSR_DCR_VBUS (0x0200) +#define CCM_UOCSR_DPPU (0x0100) +#define CCM_UOCSR_AVLD (0x0080) +#define CCM_UOCSR_BVLD (0x0040) +#define CCM_UOCSR_VVLD (0x0020) +#define CCM_UOCSR_SEND (0x0010) +#define CCM_UOCSR_PWRFLT (0x0008) +#define CCM_UOCSR_WKUP (0x0004) +#define CCM_UOCSR_UOMIE (0x0002) +#define CCM_UOCSR_XPDE (0x0001) + +/* not done yet */ +/********************************************************************* +* General Purpose I/O (GPIO) +*********************************************************************/ +/* Bit definitions and macros for GPIO_PODR_FECH_L */ +#define GPIO_PODR_FECH_L7 (0x80) +#define GPIO_PODR_FECH_L6 (0x40) +#define GPIO_PODR_FECH_L5 (0x20) +#define GPIO_PODR_FECH_L4 (0x10) +#define GPIO_PODR_FECH_L3 (0x08) +#define GPIO_PODR_FECH_L2 (0x04) +#define GPIO_PODR_FECH_L1 (0x02) +#define GPIO_PODR_FECH_L0 (0x01) + +/* Bit definitions and macros for GPIO_PODR_SSI */ +#define GPIO_PODR_SSI_4 (0x10) +#define GPIO_PODR_SSI_3 (0x08) +#define GPIO_PODR_SSI_2 (0x04) +#define GPIO_PODR_SSI_1 (0x02) +#define GPIO_PODR_SSI_0 (0x01) + +/* Bit definitions and macros for GPIO_PODR_BUSCTL */ +#define GPIO_PODR_BUSCTL_3 (0x08) +#define GPIO_PODR_BUSCTL_2 (0x04) +#define GPIO_PODR_BUSCTL_1 (0x02) +#define GPIO_PODR_BUSCTL_0 (0x01) + +/* Bit definitions and macros for GPIO_PODR_BE */ +#define GPIO_PODR_BE_3 (0x08) +#define GPIO_PODR_BE_2 (0x04) +#define GPIO_PODR_BE_1 (0x02) +#define GPIO_PODR_BE_0 (0x01) + +/* Bit definitions and macros for GPIO_PODR_CS */ +#define GPIO_PODR_CS_5 (0x20) +#define GPIO_PODR_CS_4 (0x10) +#define GPIO_PODR_CS_3 (0x08) +#define GPIO_PODR_CS_2 (0x04) +#define GPIO_PODR_CS_1 (0x02) + +/* Bit definitions and macros for GPIO_PODR_PWM */ +#define GPIO_PODR_PWM_5 (0x20) +#define GPIO_PODR_PWM_4 (0x10) +#define GPIO_PODR_PWM_3 (0x08) +#define GPIO_PODR_PWM_2 (0x04) + +/* Bit definitions and macros for GPIO_PODR_FECI2C */ +#define GPIO_PODR_FECI2C_3 (0x08) +#define GPIO_PODR_FECI2C_2 (0x04) +#define GPIO_PODR_FECI2C_1 (0x02) +#define GPIO_PODR_FECI2C_0 (0x01) + +/* Bit definitions and macros for GPIO_PODR_UART */ +#define GPIO_PODR_UART_7 (0x80) +#define GPIO_PODR_UART_6 (0x40) +#define GPIO_PODR_UART_5 (0x20) +#define GPIO_PODR_UART_4 (0x10) +#define GPIO_PODR_UART_3 (0x08) +#define GPIO_PODR_UART_2 (0x04) +#define GPIO_PODR_UART_1 (0x02) +#define GPIO_PODR_UART_0 (0x01) + +/* Bit definitions and macros for GPIO_PODR_QSPI */ +#define GPIO_PODR_QSPI_5 (0x20) +#define GPIO_PODR_QSPI_4 (0x10) +#define GPIO_PODR_QSPI_3 (0x08) +#define GPIO_PODR_QSPI_2 (0x04) +#define GPIO_PODR_QSPI_1 (0x02) +#define GPIO_PODR_QSPI_0 (0x01) + +/* Bit definitions and macros for GPIO_PODR_TIMER */ +#define GPIO_PODR_TIMER_3 (0x08) +#define GPIO_PODR_TIMER_2 (0x04) +#define GPIO_PODR_TIMER_1 (0x02) +#define GPIO_PODR_TIMER_0 (0x01) + +/* Bit definitions and macros for GPIO_PODR_LCDDATAH */ +#define GPIO_PODR_LCDDATAH_1 (0x02) +#define GPIO_PODR_LCDDATAH_0 (0x01) + +/* Bit definitions and macros for GPIO_PODR_LCDDATAM */ +#define GPIO_PODR_LCDDATAM_7 (0x80) +#define GPIO_PODR_LCDDATAM_6 (0x40) +#define GPIO_PODR_LCDDATAM_5 (0x20) +#define GPIO_PODR_LCDDATAM_4 (0x10) +#define GPIO_PODR_LCDDATAM_3 (0x08) +#define GPIO_PODR_LCDDATAM_2 (0x04) +#define GPIO_PODR_LCDDATAM_1 (0x02) +#define GPIO_PODR_LCDDATAM_0 (0x01) + +/* Bit definitions and macros for GPIO_PODR_LCDDATAL */ +#define GPIO_PODR_LCDDATAL_7 (0x80) +#define GPIO_PODR_LCDDATAL_6 (0x40) +#define GPIO_PODR_LCDDATAL_5 (0x20) +#define GPIO_PODR_LCDDATAL_4 (0x10) +#define GPIO_PODR_LCDDATAL_3 (0x08) +#define GPIO_PODR_LCDDATAL_2 (0x04) +#define GPIO_PODR_LCDDATAL_1 (0x02) +#define GPIO_PODR_LCDDATAL_0 (0x01) + +/* Bit definitions and macros for GPIO_PODR_LCDCTLH */ +#define GPIO_PODR_LCDCTLH_0 (0x01) + +/* Bit definitions and macros for GPIO_PODR_LCDCTLL */ +#define GPIO_PODR_LCDCTLL_7 (0x80) +#define GPIO_PODR_LCDCTLL_6 (0x40) +#define GPIO_PODR_LCDCTLL_5 (0x20) +#define GPIO_PODR_LCDCTLL_4 (0x10) +#define GPIO_PODR_LCDCTLL_3 (0x08) +#define GPIO_PODR_LCDCTLL_2 (0x04) +#define GPIO_PODR_LCDCTLL_1 (0x02) +#define GPIO_PODR_LCDCTLL_0 (0x01) + +/* Bit definitions and macros for GPIO_PDDR_FECH */ +#define GPIO_PDDR_FECH_L7 (0x80) +#define GPIO_PDDR_FECH_L6 (0x40) +#define GPIO_PDDR_FECH_L5 (0x20) +#define GPIO_PDDR_FECH_L4 (0x10) +#define GPIO_PDDR_FECH_L3 (0x08) +#define GPIO_PDDR_FECH_L2 (0x04) +#define GPIO_PDDR_FECH_L1 (0x02) +#define GPIO_PDDR_FECH_L0 (0x01) + +/* Bit definitions and macros for GPIO_PDDR_SSI */ +#define GPIO_PDDR_SSI_4 (0x10) +#define GPIO_PDDR_SSI_3 (0x08) +#define GPIO_PDDR_SSI_2 (0x04) +#define GPIO_PDDR_SSI_1 (0x02) +#define GPIO_PDDR_SSI_0 (0x01) + +/* Bit definitions and macros for GPIO_PDDR_BUSCTL */ +#define GPIO_PDDR_BUSCTL_3 (0x08) +#define GPIO_PDDR_BUSCTL_2 (0x04) +#define GPIO_PDDR_BUSCTL_1 (0x02) +#define GPIO_PDDR_BUSCTL_0 (0x01) + +/* Bit definitions and macros for GPIO_PDDR_BE */ +#define GPIO_PDDR_BE_3 (0x08) +#define GPIO_PDDR_BE_2 (0x04) +#define GPIO_PDDR_BE_1 (0x02) +#define GPIO_PDDR_BE_0 (0x01) + +/* Bit definitions and macros for GPIO_PDDR_CS */ +#define GPIO_PDDR_CS_1 (0x02) +#define GPIO_PDDR_CS_2 (0x04) +#define GPIO_PDDR_CS_3 (0x08) +#define GPIO_PDDR_CS_4 (0x10) +#define GPIO_PDDR_CS_5 (0x20) + +/* Bit definitions and macros for GPIO_PDDR_PWM */ +#define GPIO_PDDR_PWM_2 (0x04) +#define GPIO_PDDR_PWM_3 (0x08) +#define GPIO_PDDR_PWM_4 (0x10) +#define GPIO_PDDR_PWM_5 (0x20) + +/* Bit definitions and macros for GPIO_PDDR_FECI2C */ +#define GPIO_PDDR_FECI2C_0 (0x01) +#define GPIO_PDDR_FECI2C_1 (0x02) +#define GPIO_PDDR_FECI2C_2 (0x04) +#define GPIO_PDDR_FECI2C_3 (0x08) + +/* Bit definitions and macros for GPIO_PDDR_UART */ +#define GPIO_PDDR_UART_0 (0x01) +#define GPIO_PDDR_UART_1 (0x02) +#define GPIO_PDDR_UART_2 (0x04) +#define GPIO_PDDR_UART_3 (0x08) +#define GPIO_PDDR_UART_4 (0x10) +#define GPIO_PDDR_UART_5 (0x20) +#define GPIO_PDDR_UART_6 (0x40) +#define GPIO_PDDR_UART_7 (0x80) + +/* Bit definitions and macros for GPIO_PDDR_QSPI */ +#define GPIO_PDDR_QSPI_0 (0x01) +#define GPIO_PDDR_QSPI_1 (0x02) +#define GPIO_PDDR_QSPI_2 (0x04) +#define GPIO_PDDR_QSPI_3 (0x08) +#define GPIO_PDDR_QSPI_4 (0x10) +#define GPIO_PDDR_QSPI_5 (0x20) + +/* Bit definitions and macros for GPIO_PDDR_TIMER */ +#define GPIO_PDDR_TIMER_0 (0x01) +#define GPIO_PDDR_TIMER_1 (0x02) +#define GPIO_PDDR_TIMER_2 (0x04) +#define GPIO_PDDR_TIMER_3 (0x08) + +/* Bit definitions and macros for GPIO_PDDR_LCDDATAH */ +#define GPIO_PDDR_LCDDATAH_0 (0x01) +#define GPIO_PDDR_LCDDATAH_1 (0x02) + +/* Bit definitions and macros for GPIO_PDDR_LCDDATAM */ +#define GPIO_PDDR_LCDDATAM_0 (0x01) +#define GPIO_PDDR_LCDDATAM_1 (0x02) +#define GPIO_PDDR_LCDDATAM_2 (0x04) +#define GPIO_PDDR_LCDDATAM_3 (0x08) +#define GPIO_PDDR_LCDDATAM_4 (0x10) +#define GPIO_PDDR_LCDDATAM_5 (0x20) +#define GPIO_PDDR_LCDDATAM_6 (0x40) +#define GPIO_PDDR_LCDDATAM_7 (0x80) + +/* Bit definitions and macros for GPIO_PDDR_LCDDATAL */ +#define GPIO_PDDR_LCDDATAL_0 (0x01) +#define GPIO_PDDR_LCDDATAL_1 (0x02) +#define GPIO_PDDR_LCDDATAL_2 (0x04) +#define GPIO_PDDR_LCDDATAL_3 (0x08) +#define GPIO_PDDR_LCDDATAL_4 (0x10) +#define GPIO_PDDR_LCDDATAL_5 (0x20) +#define GPIO_PDDR_LCDDATAL_6 (0x40) +#define GPIO_PDDR_LCDDATAL_7 (0x80) + +/* Bit definitions and macros for GPIO_PDDR_LCDCTLH */ +#define GPIO_PDDR_LCDCTLH_0 (0x01) + +/* Bit definitions and macros for GPIO_PDDR_LCDCTLL */ +#define GPIO_PDDR_LCDCTLL_0 (0x01) +#define GPIO_PDDR_LCDCTLL_1 (0x02) +#define GPIO_PDDR_LCDCTLL_2 (0x04) +#define GPIO_PDDR_LCDCTLL_3 (0x08) +#define GPIO_PDDR_LCDCTLL_4 (0x10) +#define GPIO_PDDR_LCDCTLL_5 (0x20) +#define GPIO_PDDR_LCDCTLL_6 (0x40) +#define GPIO_PDDR_LCDCTLL_7 (0x80) + +/* Bit definitions and macros for GPIO_PPDSDR_FECH */ +#define GPIO_PPDSDR_FECH_L0 (0x01) +#define GPIO_PPDSDR_FECH_L1 (0x02) +#define GPIO_PPDSDR_FECH_L2 (0x04) +#define GPIO_PPDSDR_FECH_L3 (0x08) +#define GPIO_PPDSDR_FECH_L4 (0x10) +#define GPIO_PPDSDR_FECH_L5 (0x20) +#define GPIO_PPDSDR_FECH_L6 (0x40) +#define GPIO_PPDSDR_FECH_L7 (0x80) + +/* Bit definitions and macros for GPIO_PPDSDR_SSI */ +#define GPIO_PPDSDR_SSI_0 (0x01) +#define GPIO_PPDSDR_SSI_1 (0x02) +#define GPIO_PPDSDR_SSI_2 (0x04) +#define GPIO_PPDSDR_SSI_3 (0x08) +#define GPIO_PPDSDR_SSI_4 (0x10) + +/* Bit definitions and macros for GPIO_PPDSDR_BUSCTL */ +#define GPIO_PPDSDR_BUSCTL_0 (0x01) +#define GPIO_PPDSDR_BUSCTL_1 (0x02) +#define GPIO_PPDSDR_BUSCTL_2 (0x04) +#define GPIO_PPDSDR_BUSCTL_3 (0x08) + +/* Bit definitions and macros for GPIO_PPDSDR_BE */ +#define GPIO_PPDSDR_BE_0 (0x01) +#define GPIO_PPDSDR_BE_1 (0x02) +#define GPIO_PPDSDR_BE_2 (0x04) +#define GPIO_PPDSDR_BE_3 (0x08) + +/* Bit definitions and macros for GPIO_PPDSDR_CS */ +#define GPIO_PPDSDR_CS_1 (0x02) +#define GPIO_PPDSDR_CS_2 (0x04) +#define GPIO_PPDSDR_CS_3 (0x08) +#define GPIO_PPDSDR_CS_4 (0x10) +#define GPIO_PPDSDR_CS_5 (0x20) + +/* Bit definitions and macros for GPIO_PPDSDR_PWM */ +#define GPIO_PPDSDR_PWM_2 (0x04) +#define GPIO_PPDSDR_PWM_3 (0x08) +#define GPIO_PPDSDR_PWM_4 (0x10) +#define GPIO_PPDSDR_PWM_5 (0x20) + +/* Bit definitions and macros for GPIO_PPDSDR_FECI2C */ +#define GPIO_PPDSDR_FECI2C_0 (0x01) +#define GPIO_PPDSDR_FECI2C_1 (0x02) +#define GPIO_PPDSDR_FECI2C_2 (0x04) +#define GPIO_PPDSDR_FECI2C_3 (0x08) + +/* Bit definitions and macros for GPIO_PPDSDR_UART */ +#define GPIO_PPDSDR_UART_0 (0x01) +#define GPIO_PPDSDR_UART_1 (0x02) +#define GPIO_PPDSDR_UART_2 (0x04) +#define GPIO_PPDSDR_UART_3 (0x08) +#define GPIO_PPDSDR_UART_4 (0x10) +#define GPIO_PPDSDR_UART_5 (0x20) +#define GPIO_PPDSDR_UART_6 (0x40) +#define GPIO_PPDSDR_UART_7 (0x80) + +/* Bit definitions and macros for GPIO_PPDSDR_QSPI */ +#define GPIO_PPDSDR_QSPI_0 (0x01) +#define GPIO_PPDSDR_QSPI_1 (0x02) +#define GPIO_PPDSDR_QSPI_2 (0x04) +#define GPIO_PPDSDR_QSPI_3 (0x08) +#define GPIO_PPDSDR_QSPI_4 (0x10) +#define GPIO_PPDSDR_QSPI_5 (0x20) + +/* Bit definitions and macros for GPIO_PPDSDR_TIMER */ +#define GPIO_PPDSDR_TIMER_0 (0x01) +#define GPIO_PPDSDR_TIMER_1 (0x02) +#define GPIO_PPDSDR_TIMER_2 (0x04) +#define GPIO_PPDSDR_TIMER_3 (0x08) + +/* Bit definitions and macros for GPIO_PPDSDR_LCDDATAH */ +#define GPIO_PPDSDR_LCDDATAH_0 (0x01) +#define GPIO_PPDSDR_LCDDATAH_1 (0x02) + +/* Bit definitions and macros for GPIO_PPDSDR_LCDDATAM */ +#define GPIO_PPDSDR_LCDDATAM_0 (0x01) +#define GPIO_PPDSDR_LCDDATAM_1 (0x02) +#define GPIO_PPDSDR_LCDDATAM_2 (0x04) +#define GPIO_PPDSDR_LCDDATAM_3 (0x08) +#define GPIO_PPDSDR_LCDDATAM_4 (0x10) +#define GPIO_PPDSDR_LCDDATAM_5 (0x20) +#define GPIO_PPDSDR_LCDDATAM_6 (0x40) +#define GPIO_PPDSDR_LCDDATAM_7 (0x80) + +/* Bit definitions and macros for GPIO_PPDSDR_LCDDATAL */ +#define GPIO_PPDSDR_LCDDATAL_0 (0x01) +#define GPIO_PPDSDR_LCDDATAL_1 (0x02) +#define GPIO_PPDSDR_LCDDATAL_2 (0x04) +#define GPIO_PPDSDR_LCDDATAL_3 (0x08) +#define GPIO_PPDSDR_LCDDATAL_4 (0x10) +#define GPIO_PPDSDR_LCDDATAL_5 (0x20) +#define GPIO_PPDSDR_LCDDATAL_6 (0x40) +#define GPIO_PPDSDR_LCDDATAL_7 (0x80) + +/* Bit definitions and macros for GPIO_PPDSDR_LCDCTLH */ +#define GPIO_PPDSDR_LCDCTLH_0 (0x01) + +/* Bit definitions and macros for GPIO_PPDSDR_LCDCTLL */ +#define GPIO_PPDSDR_LCDCTLL_0 (0x01) +#define GPIO_PPDSDR_LCDCTLL_1 (0x02) +#define GPIO_PPDSDR_LCDCTLL_2 (0x04) +#define GPIO_PPDSDR_LCDCTLL_3 (0x08) +#define GPIO_PPDSDR_LCDCTLL_4 (0x10) +#define GPIO_PPDSDR_LCDCTLL_5 (0x20) +#define GPIO_PPDSDR_LCDCTLL_6 (0x40) +#define GPIO_PPDSDR_LCDCTLL_7 (0x80) + +/* Bit definitions and macros for GPIO_PCLRR_FECH */ +#define GPIO_PCLRR_FECH_L0 (0x01) +#define GPIO_PCLRR_FECH_L1 (0x02) +#define GPIO_PCLRR_FECH_L2 (0x04) +#define GPIO_PCLRR_FECH_L3 (0x08) +#define GPIO_PCLRR_FECH_L4 (0x10) +#define GPIO_PCLRR_FECH_L5 (0x20) +#define GPIO_PCLRR_FECH_L6 (0x40) +#define GPIO_PCLRR_FECH_L7 (0x80) + +/* Bit definitions and macros for GPIO_PCLRR_SSI */ +#define GPIO_PCLRR_SSI_0 (0x01) +#define GPIO_PCLRR_SSI_1 (0x02) +#define GPIO_PCLRR_SSI_2 (0x04) +#define GPIO_PCLRR_SSI_3 (0x08) +#define GPIO_PCLRR_SSI_4 (0x10) + +/* Bit definitions and macros for GPIO_PCLRR_BUSCTL */ +#define GPIO_PCLRR_BUSCTL_L0 (0x01) +#define GPIO_PCLRR_BUSCTL_L1 (0x02) +#define GPIO_PCLRR_BUSCTL_L2 (0x04) +#define GPIO_PCLRR_BUSCTL_L3 (0x08) + +/* Bit definitions and macros for GPIO_PCLRR_BE */ +#define GPIO_PCLRR_BE_0 (0x01) +#define GPIO_PCLRR_BE_1 (0x02) +#define GPIO_PCLRR_BE_2 (0x04) +#define GPIO_PCLRR_BE_3 (0x08) + +/* Bit definitions and macros for GPIO_PCLRR_CS */ +#define GPIO_PCLRR_CS_1 (0x02) +#define GPIO_PCLRR_CS_2 (0x04) +#define GPIO_PCLRR_CS_3 (0x08) +#define GPIO_PCLRR_CS_4 (0x10) +#define GPIO_PCLRR_CS_5 (0x20) + +/* Bit definitions and macros for GPIO_PCLRR_PWM */ +#define GPIO_PCLRR_PWM_2 (0x04) +#define GPIO_PCLRR_PWM_3 (0x08) +#define GPIO_PCLRR_PWM_4 (0x10) +#define GPIO_PCLRR_PWM_5 (0x20) + +/* Bit definitions and macros for GPIO_PCLRR_FECI2C */ +#define GPIO_PCLRR_FECI2C_0 (0x01) +#define GPIO_PCLRR_FECI2C_1 (0x02) +#define GPIO_PCLRR_FECI2C_2 (0x04) +#define GPIO_PCLRR_FECI2C_3 (0x08) + +/* Bit definitions and macros for GPIO_PCLRR_UART */ +#define GPIO_PCLRR_UART0 (0x01) +#define GPIO_PCLRR_UART1 (0x02) +#define GPIO_PCLRR_UART2 (0x04) +#define GPIO_PCLRR_UART3 (0x08) +#define GPIO_PCLRR_UART4 (0x10) +#define GPIO_PCLRR_UART5 (0x20) +#define GPIO_PCLRR_UART6 (0x40) +#define GPIO_PCLRR_UART7 (0x80) + +/* Bit definitions and macros for GPIO_PCLRR_QSPI */ +#define GPIO_PCLRR_QSPI0 (0x01) +#define GPIO_PCLRR_QSPI1 (0x02) +#define GPIO_PCLRR_QSPI2 (0x04) +#define GPIO_PCLRR_QSPI3 (0x08) +#define GPIO_PCLRR_QSPI4 (0x10) +#define GPIO_PCLRR_QSPI5 (0x20) + +/* Bit definitions and macros for GPIO_PCLRR_TIMER */ +#define GPIO_PCLRR_TIMER0 (0x01) +#define GPIO_PCLRR_TIMER1 (0x02) +#define GPIO_PCLRR_TIMER2 (0x04) +#define GPIO_PCLRR_TIMER3 (0x08) + +/* Bit definitions and macros for GPIO_PCLRR_LCDDATAH */ +#define GPIO_PCLRR_LCDDATAH0 (0x01) +#define GPIO_PCLRR_LCDDATAH1 (0x02) + +/* Bit definitions and macros for GPIO_PCLRR_LCDDATAM */ +#define GPIO_PCLRR_LCDDATAM0 (0x01) +#define GPIO_PCLRR_LCDDATAM1 (0x02) +#define GPIO_PCLRR_LCDDATAM2 (0x04) +#define GPIO_PCLRR_LCDDATAM3 (0x08) +#define GPIO_PCLRR_LCDDATAM4 (0x10) +#define GPIO_PCLRR_LCDDATAM5 (0x20) +#define GPIO_PCLRR_LCDDATAM6 (0x40) +#define GPIO_PCLRR_LCDDATAM7 (0x80) + +/* Bit definitions and macros for GPIO_PCLRR_LCDDATAL */ +#define GPIO_PCLRR_LCDDATAL0 (0x01) +#define GPIO_PCLRR_LCDDATAL1 (0x02) +#define GPIO_PCLRR_LCDDATAL2 (0x04) +#define GPIO_PCLRR_LCDDATAL3 (0x08) +#define GPIO_PCLRR_LCDDATAL4 (0x10) +#define GPIO_PCLRR_LCDDATAL5 (0x20) +#define GPIO_PCLRR_LCDDATAL6 (0x40) +#define GPIO_PCLRR_LCDDATAL7 (0x80) + +/* Bit definitions and macros for GPIO_PCLRR_LCDCTLH */ +#define GPIO_PCLRR_LCDCTLH_PCLRR_LCDCTLH0 (0x01) + +/* Bit definitions and macros for GPIO_PCLRR_LCDCTLL */ +#define GPIO_PCLRR_LCDCTLL0 (0x01) +#define GPIO_PCLRR_LCDCTLL1 (0x02) +#define GPIO_PCLRR_LCDCTLL2 (0x04) +#define GPIO_PCLRR_LCDCTLL3 (0x08) +#define GPIO_PCLRR_LCDCTLL4 (0x10) +#define GPIO_PCLRR_LCDCTLL5 (0x20) +#define GPIO_PCLRR_LCDCTLL6 (0x40) +#define GPIO_PCLRR_LCDCTLL7 (0x80) + +/* Bit definitions and macros for GPIO_PAR_FEC */ +#define GPIO_PAR_FEC_MII(x) (((x)&0x03)<<0) +#define GPIO_PAR_FEC_7W(x) (((x)&0x03)<<2) +#define GPIO_PAR_FEC_7W_GPIO (0x00) +#define GPIO_PAR_FEC_7W_URTS1 (0x04) +#define GPIO_PAR_FEC_7W_FEC (0x0C) +#define GPIO_PAR_FEC_MII_GPIO (0x00) +#define GPIO_PAR_FEC_MII_UART (0x01) +#define GPIO_PAR_FEC_MII_FEC (0x03) + +/* Bit definitions and macros for GPIO_PAR_PWM */ +#define GPIO_PAR_PWM1(x) (((x)&0x03)<<0) +#define GPIO_PAR_PWM3(x) (((x)&0x03)<<2) +#define GPIO_PAR_PWM5 (0x10) +#define GPIO_PAR_PWM7 (0x20) + +/* Bit definitions and macros for GPIO_PAR_BUSCTL */ +#define GPIO_PAR_BUSCTL_TS(x) (((x)&0x03)<<3) +#define GPIO_PAR_BUSCTL_RWB (0x20) +#define GPIO_PAR_BUSCTL_TA (0x40) +#define GPIO_PAR_BUSCTL_OE (0x80) +#define GPIO_PAR_BUSCTL_OE_GPIO (0x00) +#define GPIO_PAR_BUSCTL_OE_OE (0x80) +#define GPIO_PAR_BUSCTL_TA_GPIO (0x00) +#define GPIO_PAR_BUSCTL_TA_TA (0x40) +#define GPIO_PAR_BUSCTL_RWB_GPIO (0x00) +#define GPIO_PAR_BUSCTL_RWB_RWB (0x20) +#define GPIO_PAR_BUSCTL_TS_GPIO (0x00) +#define GPIO_PAR_BUSCTL_TS_DACK0 (0x10) +#define GPIO_PAR_BUSCTL_TS_TS (0x18) + +/* Bit definitions and macros for GPIO_PAR_FECI2C */ +#define GPIO_PAR_FECI2C_SDA(x) (((x)&0x03)<<0) +#define GPIO_PAR_FECI2C_SCL(x) (((x)&0x03)<<2) +#define GPIO_PAR_FECI2C_MDIO(x) (((x)&0x03)<<4) +#define GPIO_PAR_FECI2C_MDC(x) (((x)&0x03)<<6) +#define GPIO_PAR_FECI2C_MDC_GPIO (0x00) +#define GPIO_PAR_FECI2C_MDC_UTXD2 (0x40) +#define GPIO_PAR_FECI2C_MDC_SCL (0x80) +#define GPIO_PAR_FECI2C_MDC_EMDC (0xC0) +#define GPIO_PAR_FECI2C_MDIO_GPIO (0x00) +#define GPIO_PAR_FECI2C_MDIO_URXD2 (0x10) +#define GPIO_PAR_FECI2C_MDIO_SDA (0x20) +#define GPIO_PAR_FECI2C_MDIO_EMDIO (0x30) +#define GPIO_PAR_FECI2C_SCL_GPIO (0x00) +#define GPIO_PAR_FECI2C_SCL_UTXD2 (0x04) +#define GPIO_PAR_FECI2C_SCL_SCL (0x0C) +#define GPIO_PAR_FECI2C_SDA_GPIO (0x00) +#define GPIO_PAR_FECI2C_SDA_URXD2 (0x02) +#define GPIO_PAR_FECI2C_SDA_SDA (0x03) + +/* Bit definitions and macros for GPIO_PAR_BE */ +#define GPIO_PAR_BE0 (0x01) +#define GPIO_PAR_BE1 (0x02) +#define GPIO_PAR_BE2 (0x04) +#define GPIO_PAR_BE3 (0x08) + +/* Bit definitions and macros for GPIO_PAR_CS */ +#define GPIO_PAR_CS1 (0x02) +#define GPIO_PAR_CS2 (0x04) +#define GPIO_PAR_CS3 (0x08) +#define GPIO_PAR_CS4 (0x10) +#define GPIO_PAR_CS5 (0x20) +#define GPIO_PAR_CS1_GPIO (0x00) +#define GPIO_PAR_CS1_SDCS1 (0x01) +#define GPIO_PAR_CS1_CS1 (0x03) + +/* Bit definitions and macros for GPIO_PAR_SSI */ +#define GPIO_PAR_SSI_MCLK (0x0080) +#define GPIO_PAR_SSI_TXD(x) (((x)&0x0003)<<8) +#define GPIO_PAR_SSI_RXD(x) (((x)&0x0003)<<10) +#define GPIO_PAR_SSI_FS(x) (((x)&0x0003)<<12) +#define GPIO_PAR_SSI_BCLK(x) (((x)&0x0003)<<14) + +/* Bit definitions and macros for GPIO_PAR_UART */ +#define GPIO_PAR_UART_TXD0 (0x0001) +#define GPIO_PAR_UART_RXD0 (0x0002) +#define GPIO_PAR_UART_RTS0 (0x0004) +#define GPIO_PAR_UART_CTS0 (0x0008) +#define GPIO_PAR_UART_TXD1(x) (((x)&0x0003)<<4) +#define GPIO_PAR_UART_RXD1(x) (((x)&0x0003)<<6) +#define GPIO_PAR_UART_RTS1(x) (((x)&0x0003)<<8) +#define GPIO_PAR_UART_CTS1(x) (((x)&0x0003)<<10) +#define GPIO_PAR_UART_CTS1_GPIO (0x0000) +#define GPIO_PAR_UART_CTS1_SSI_BCLK (0x0800) +#define GPIO_PAR_UART_CTS1_ULPI_D7 (0x0400) +#define GPIO_PAR_UART_CTS1_UCTS1 (0x0C00) +#define GPIO_PAR_UART_RTS1_GPIO (0x0000) +#define GPIO_PAR_UART_RTS1_SSI_FS (0x0200) +#define GPIO_PAR_UART_RTS1_ULPI_D6 (0x0100) +#define GPIO_PAR_UART_RTS1_URTS1 (0x0300) +#define GPIO_PAR_UART_RXD1_GPIO (0x0000) +#define GPIO_PAR_UART_RXD1_SSI_RXD (0x0080) +#define GPIO_PAR_UART_RXD1_ULPI_D5 (0x0040) +#define GPIO_PAR_UART_RXD1_URXD1 (0x00C0) +#define GPIO_PAR_UART_TXD1_GPIO (0x0000) +#define GPIO_PAR_UART_TXD1_SSI_TXD (0x0020) +#define GPIO_PAR_UART_TXD1_ULPI_D4 (0x0010) +#define GPIO_PAR_UART_TXD1_UTXD1 (0x0030) + +/* Bit definitions and macros for GPIO_PAR_QSPI */ +#define GPIO_PAR_QSPI_SCK(x) (((x)&0x0003)<<4) +#define GPIO_PAR_QSPI_DOUT(x) (((x)&0x0003)<<6) +#define GPIO_PAR_QSPI_DIN(x) (((x)&0x0003)<<8) +#define GPIO_PAR_QSPI_PCS0(x) (((x)&0x0003)<<10) +#define GPIO_PAR_QSPI_PCS1(x) (((x)&0x0003)<<12) +#define GPIO_PAR_QSPI_PCS2(x) (((x)&0x0003)<<14) + +/* Bit definitions and macros for GPIO_PAR_TIMER */ +#define GPIO_PAR_TIN0(x) (((x)&0x03)<<0) +#define GPIO_PAR_TIN1(x) (((x)&0x03)<<2) +#define GPIO_PAR_TIN2(x) (((x)&0x03)<<4) +#define GPIO_PAR_TIN3(x) (((x)&0x03)<<6) +#define GPIO_PAR_TIN3_GPIO (0x00) +#define GPIO_PAR_TIN3_TOUT3 (0x80) +#define GPIO_PAR_TIN3_URXD2 (0x40) +#define GPIO_PAR_TIN3_TIN3 (0xC0) +#define GPIO_PAR_TIN2_GPIO (0x00) +#define GPIO_PAR_TIN2_TOUT2 (0x20) +#define GPIO_PAR_TIN2_UTXD2 (0x10) +#define GPIO_PAR_TIN2_TIN2 (0x30) +#define GPIO_PAR_TIN1_GPIO (0x00) +#define GPIO_PAR_TIN1_TOUT1 (0x08) +#define GPIO_PAR_TIN1_DACK1 (0x04) +#define GPIO_PAR_TIN1_TIN1 (0x0C) +#define GPIO_PAR_TIN0_GPIO (0x00) +#define GPIO_PAR_TIN0_TOUT0 (0x02) +#define GPIO_PAR_TIN0_DREQ0 (0x01) +#define GPIO_PAR_TIN0_TIN0 (0x03) + +/* Bit definitions and macros for GPIO_PAR_LCDDATA */ +#define GPIO_PAR_LCDDATA_LD7_0(x) ((x)&0x03) +#define GPIO_PAR_LCDDATA_LD15_8(x) (((x)&0x03)<<2) +#define GPIO_PAR_LCDDATA_LD16(x) (((x)&0x03)<<4) +#define GPIO_PAR_LCDDATA_LD17(x) (((x)&0x03)<<6) + +/* Bit definitions and macros for GPIO_PAR_LCDCTL */ +#define GPIO_PAR_LCDCTL_CLS (0x0001) +#define GPIO_PAR_LCDCTL_PS (0x0002) +#define GPIO_PAR_LCDCTL_REV (0x0004) +#define GPIO_PAR_LCDCTL_SPL_SPR (0x0008) +#define GPIO_PAR_LCDCTL_CONTRAST (0x0010) +#define GPIO_PAR_LCDCTL_LSCLK (0x0020) +#define GPIO_PAR_LCDCTL_LP_HSYNC (0x0040) +#define GPIO_PAR_LCDCTL_FLM_VSYNC (0x0080) +#define GPIO_PAR_LCDCTL_ACD_OE (0x0100) + +/* Bit definitions and macros for GPIO_PAR_IRQ */ +#define GPIO_PAR_IRQ1(x) (((x)&0x0003)<<4) +#define GPIO_PAR_IRQ2(x) (((x)&0x0003)<<6) +#define GPIO_PAR_IRQ4(x) (((x)&0x0003)<<8) +#define GPIO_PAR_IRQ5(x) (((x)&0x0003)<<10) +#define GPIO_PAR_IRQ6(x) (((x)&0x0003)<<12) + +/* Bit definitions and macros for GPIO_MSCR_FLEXBUS */ +#define GPIO_MSCR_FLEXBUS_ADDRCTL(x) ((x)&0x03) +#define GPIO_MSCR_FLEXBUS_DLOWER(x) (((x)&0x03)<<2) +#define GPIO_MSCR_FLEXBUS_DUPPER(x) (((x)&0x03)<<4) + +/* Bit definitions and macros for GPIO_MSCR_SDRAM */ +#define GPIO_MSCR_SDRAM_SDRAM(x) ((x)&0x03) +#define GPIO_MSCR_SDRAM_SDCLK(x) (((x)&0x03)<<2) +#define GPIO_MSCR_SDRAM_SDCLKB(x) (((x)&0x03)<<4) + +/* Bit definitions and macros for GPIO_DSCR_I2C */ +#define GPIO_DSCR_I2C_DSE(x) ((x)&0x03) + +/* Bit definitions and macros for GPIO_DSCR_PWM */ +#define GPIO_DSCR_PWM_DSE(x) ((x)&0x03) + +/* Bit definitions and macros for GPIO_DSCR_FEC */ +#define GPIO_DSCR_FEC_DSE(x) ((x)&0x03) + +/* Bit definitions and macros for GPIO_DSCR_UART */ +#define GPIO_DSCR_UART0_DSE(x) ((x)&0x03) +#define GPIO_DSCR_UART1_DSE(x) (((x)&0x03)<<2) + +/* Bit definitions and macros for GPIO_DSCR_QSPI */ +#define GPIO_DSCR_QSPI_DSE(x) ((x)&0x03) + +/* Bit definitions and macros for GPIO_DSCR_TIMER */ +#define GPIO_DSCR_TIMER_DSE(x) ((x)&0x03) + +/* Bit definitions and macros for GPIO_DSCR_SSI */ +#define GPIO_DSCR_SSI_DSE(x) ((x)&0x03) + +/* Bit definitions and macros for GPIO_DSCR_LCD */ +#define GPIO_DSCR_LCD_DSE(x) ((x)&0x03) + +/* Bit definitions and macros for GPIO_DSCR_DEBUG */ +#define GPIO_DSCR_DEBUG_DSE(x) ((x)&0x03) + +/* Bit definitions and macros for GPIO_DSCR_CLKRST */ +#define GPIO_DSCR_CLKRST_DSE(x) ((x)&0x03) + +/* Bit definitions and macros for GPIO_DSCR_IRQ */ +#define GPIO_DSCR_IRQ_DSE(x) ((x)&0x03) + +/* not done yet */ +/********************************************************************* +* LCD Controller (LCDC) +*********************************************************************/ +/* Bit definitions and macros for LCDC_LSSAR */ +#define LCDC_LSSAR_SSA(x) (((x)&0x3FFFFFFF)<<2) + +/* Bit definitions and macros for LCDC_LSR */ +#define LCDC_LSR_YMAX(x) (((x)&0x000003FF)<<0) +#define LCDC_LSR_XMAX(x) (((x)&0x0000003F)<<20) + +/* Bit definitions and macros for LCDC_LVPWR */ +#define LCDC_LVPWR_VPW(x) (((x)&0x000003FF)<<0) + +/* Bit definitions and macros for LCDC_LCPR */ +#define LCDC_LCPR_CYP(x) (((x)&0x000003FF)<<0) +#define LCDC_LCPR_CXP(x) (((x)&0x000003FF)<<16) +#define LCDC_LCPR_OP (0x10000000) +#define LCDC_LCPR_CC(x) (((x)&0x00000003)<<30) +#define LCDC_LCPR_CC_TRANSPARENT (0x00000000) +#define LCDC_LCPR_CC_OR (0x40000000) +#define LCDC_LCPR_CC_XOR (0x80000000) +#define LCDC_LCPR_CC_AND (0xC0000000) +#define LCDC_LCPR_OP_ON (0x10000000) +#define LCDC_LCPR_OP_OFF (0x00000000) + +/* Bit definitions and macros for LCDC_LCWHBR */ +#define LCDC_LCWHBR_BD(x) (((x)&0x000000FF)<<0) +#define LCDC_LCWHBR_CH(x) (((x)&0x0000001F)<<16) +#define LCDC_LCWHBR_CW(x) (((x)&0x0000001F)<<24) +#define LCDC_LCWHBR_BK_EN (0x80000000) +#define LCDC_LCWHBR_BK_EN_ON (0x80000000) +#define LCDC_LCWHBR_BK_EN_OFF (0x00000000) + +/* Bit definitions and macros for LCDC_LCCMR */ +#define LCDC_LCCMR_CUR_COL_B(x) (((x)&0x0000003F)<<0) +#define LCDC_LCCMR_CUR_COL_G(x) (((x)&0x0000003F)<<6) +#define LCDC_LCCMR_CUR_COL_R(x) (((x)&0x0000003F)<<12) + +/* Bit definitions and macros for LCDC_LPCR */ +#define LCDC_LPCR_PCD(x) (((x)&0x0000003F)<<0) +#define LCDC_LPCR_SHARP (0x00000040) +#define LCDC_LPCR_SCLKSEL (0x00000080) +#define LCDC_LPCR_ACD(x) (((x)&0x0000007F)<<8) +#define LCDC_LPCR_ACDSEL (0x00008000) +#define LCDC_LPCR_REV_VS (0x00010000) +#define LCDC_LPCR_SWAP_SEL (0x00020000) +#define LCDC_LPCR_ENDSEL (0x00040000) +#define LCDC_LPCR_SCLKIDLE (0x00080000) +#define LCDC_LPCR_OEPOL (0x00100000) +#define LCDC_LPCR_CLKPOL (0x00200000) +#define LCDC_LPCR_LPPOL (0x00400000) +#define LCDC_LPCR_FLM (0x00800000) +#define LCDC_LPCR_PIXPOL (0x01000000) +#define LCDC_LPCR_BPIX(x) (((x)&0x00000007)<<25) +#define LCDC_LPCR_PBSIZ(x) (((x)&0x00000003)<<28) +#define LCDC_LPCR_COLOR (0x40000000) +#define LCDC_LPCR_TFT (0x80000000) +#define LCDC_LPCR_MODE_MONOCHROME (0x00000000) +#define LCDC_LPCR_MODE_CSTN (0x40000000) +#define LCDC_LPCR_MODE_TFT (0xC0000000) +#define LCDC_LPCR_PBSIZ_1 (0x00000000) +#define LCDC_LPCR_PBSIZ_2 (0x10000000) +#define LCDC_LPCR_PBSIZ_4 (0x20000000) +#define LCDC_LPCR_PBSIZ_8 (0x30000000) +#define LCDC_LPCR_BPIX_1bpp (0x00000000) +#define LCDC_LPCR_BPIX_2bpp (0x02000000) +#define LCDC_LPCR_BPIX_4bpp (0x04000000) +#define LCDC_LPCR_BPIX_8bpp (0x06000000) +#define LCDC_LPCR_BPIX_12bpp (0x08000000) +#define LCDC_LPCR_BPIX_16bpp (0x0A000000) +#define LCDC_LPCR_BPIX_18bpp (0x0C000000) + +#define LCDC_LPCR_PANEL_TYPE(x) (((x)&0x00000003)<<30) + +/* Bit definitions and macros for LCDC_LHCR */ +#define LCDC_LHCR_H_WAIT_2(x) (((x)&0x000000FF)<<0) +#define LCDC_LHCR_H_WAIT_1(x) (((x)&0x000000FF)<<8) +#define LCDC_LHCR_H_WIDTH(x) (((x)&0x0000003F)<<26) + +/* Bit definitions and macros for LCDC_LVCR */ +#define LCDC_LVCR_V_WAIT_2(x) (((x)&0x000000FF)<<0) +#define LCDC_LVCR_V_WAIT_1(x) (((x)&0x000000FF)<<8) +#define LCDC_LVCR_V_WIDTH(x) (((x)&0x0000003F)<<26) + +/* Bit definitions and macros for LCDC_LPOR */ +#define LCDC_LPOR_POS(x) (((x)&0x0000001F)<<0) + +/* Bit definitions and macros for LCDC_LPCCR */ +#define LCDC_LPCCR_PW(x) (((x)&0x000000FF)<<0) +#define LCDC_LPCCR_CC_EN (0x00000100) +#define LCDC_LPCCR_SCR(x) (((x)&0x00000003)<<9) +#define LCDC_LPCCR_LDMSK (0x00008000) +#define LCDC_LPCCR_CLS_HI_WIDTH(x) (((x)&0x000001FF)<<16) +#define LCDC_LPCCR_SCR_LINEPULSE (0x00000000) +#define LCDC_LPCCR_SCR_PIXELCLK (0x00002000) +#define LCDC_LPCCR_SCR_LCDCLOCK (0x00004000) + +/* Bit definitions and macros for LCDC_LDCR */ +#define LCDC_LDCR_TM(x) (((x)&0x0000001F)<<0) +#define LCDC_LDCR_HM(x) (((x)&0x0000001F)<<16) +#define LCDC_LDCR_BURST (0x80000000) + +/* Bit definitions and macros for LCDC_LRMCR */ +#define LCDC_LRMCR_SEL_REF (0x00000001) + +/* Bit definitions and macros for LCDC_LICR */ +#define LCDC_LICR_INTCON (0x00000001) +#define LCDC_LICR_INTSYN (0x00000004) +#define LCDC_LICR_GW_INT_CON (0x00000010) + +/* Bit definitions and macros for LCDC_LIER */ +#define LCDC_LIER_BOF_EN (0x00000001) +#define LCDC_LIER_EOF_EN (0x00000002) +#define LCDC_LIER_ERR_RES_EN (0x00000004) +#define LCDC_LIER_UDR_ERR_EN (0x00000008) +#define LCDC_LIER_GW_BOF_EN (0x00000010) +#define LCDC_LIER_GW_EOF_EN (0x00000020) +#define LCDC_LIER_GW_ERR_RES_EN (0x00000040) +#define LCDC_LIER_GW_UDR_ERR_EN (0x00000080) + +/* Bit definitions and macros for LCDC_LISR */ +#define LCDC_LISR_BOF (0x00000001) +#define LCDC_LISR_EOF (0x00000002) +#define LCDC_LISR_ERR_RES (0x00000004) +#define LCDC_LISR_UDR_ERR (0x00000008) +#define LCDC_LISR_GW_BOF (0x00000010) +#define LCDC_LISR_GW_EOF (0x00000020) +#define LCDC_LISR_GW_ERR_RES (0x00000040) +#define LCDC_LISR_GW_UDR_ERR (0x00000080) + +/* Bit definitions and macros for LCDC_LGWSAR */ +#define LCDC_LGWSAR_GWSA(x) (((x)&0x3FFFFFFF)<<2) + +/* Bit definitions and macros for LCDC_LGWSR */ +#define LCDC_LGWSR_GWH(x) (((x)&0x000003FF)<<0) +#define LCDC_LGWSR_GWW(x) (((x)&0x0000003F)<<20) + +/* Bit definitions and macros for LCDC_LGWVPWR */ +#define LCDC_LGWVPWR_GWVPW(x) (((x)&0x000003FF)<<0) + +/* Bit definitions and macros for LCDC_LGWPOR */ +#define LCDC_LGWPOR_GWPO(x) (((x)&0x0000001F)<<0) + +/* Bit definitions and macros for LCDC_LGWPR */ +#define LCDC_LGWPR_GWYP(x) (((x)&0x000003FF)<<0) +#define LCDC_LGWPR_GWXP(x) (((x)&0x000003FF)<<16) + +/* Bit definitions and macros for LCDC_LGWCR */ +#define LCDC_LGWCR_GWCKB(x) (((x)&0x0000003F)<<0) +#define LCDC_LGWCR_GWCKG(x) (((x)&0x0000003F)<<6) +#define LCDC_LGWCR_GWCKR(x) (((x)&0x0000003F)<<12) +#define LCDC_LGWCR_GW_RVS (0x00200000) +#define LCDC_LGWCR_GWE (0x00400000) +#define LCDC_LGWCR_GWCKE (0x00800000) +#define LCDC_LGWCR_GWAV(x) (((x)&0x000000FF)<<24) + +/* Bit definitions and macros for LCDC_LGWDCR */ +#define LCDC_LGWDCR_GWTM(x) (((x)&0x0000001F)<<0) +#define LCDC_LGWDCR_GWHM(x) (((x)&0x0000001F)<<16) +#define LCDC_LGWDCR_GWBT (0x80000000) + +/* Bit definitions and macros for LCDC_BPLUT_BASE */ +#define LCDC_BPLUT_BASE_BASE(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for LCDC_GWLUT_BASE */ +#define LCDC_GWLUT_BASE_BASE(x) (((x)&0xFFFFFFFF)<<0) + +/* not done yet */ +/********************************************************************* +* USB Controller (USB) +*********************************************************************/ +/* Bit definitions and macros for USB_HCSPARAMS */ +#define USB_HCSPARAMS_N_PORTS(x) ((x)&0x0000000F) +#define USB_HCSPARAMS_PPC (0x00000010) +#define USB_HCSPARAMS_N_PCC(x) (((x)&0x0000000F)<<8) +#define USB_HCSPARAMS_N_CC(x) (((x)&0x0000000F)<<12) +#define USB_HCSPARAMS_PI (0x00010000) +#define USB_HCSPARAMS_N_PTT(x) (((x)&0x0000000F)<<20) +#define USB_HCSPARAMS_N_TT(x) (((x)&0x0000000F)<<24) + +/* Bit definitions and macros for USB_HCCPARAMS */ +#define USB_HCCPARAMS_ADC (0x00000001) +#define USB_HCCPARAMS_PFL (0x00000002) +#define USB_HCCPARAMS_ASP (0x00000004) +#define USB_HCCPARAMS_IST(x) (((x)&0x0000000F)<<4) +#define USB_HCCPARAMS_EECP(x) (((x)&0x000000FF)<<8) + +/* Bit definitions and macros for USB_DCIVERSION */ +#define USB_DCIVERSION_DCIVERSION(x) (((x)&0xFFFF)<<0) + +/* Bit definitions and macros for USB_DCCPARAMS */ +#define USB_DCCPARAMS_DEN(x) (((x)&0x0000001F)<<0) +#define USB_DCCPARAMS_DC (0x00000080) +#define USB_DCCPARAMS_HC (0x00000100) + +/* Bit definitions and macros for USB_USBCMD */ +#define USB_USBCMD_RS (0x00000001) +#define USB_USBCMD_RST (0x00000002) +#define USB_USBCMD_FS0 (0x00000004) +#define USB_USBCMD_FS1 (0x00000008) +#define USB_USBCMD_PSE (0x00000010) +#define USB_USBCMD_ASE (0x00000020) +#define USB_USBCMD_IAA (0x00000040) +#define USB_USBCMD_LR (0x00000080) +#define USB_USBCMD_ASP(x) (((x)&0x00000003)<<8) +#define USB_USBCMD_ASPE (0x00000800) +#define USB_USBCMD_SUTW (0x00002000) +#define USB_USBCMD_ATDTW (0x00004000) +#define USB_USBCMD_FS2 (0x00008000) +#define USB_USBCMD_ITC(x) (((x)&0x000000FF)<<16) +#define USB_USBCMD_ITC_IMM (0x00000000) +#define USB_USBCMD_ITC_1 (0x00010000) +#define USB_USBCMD_ITC_2 (0x00020000) +#define USB_USBCMD_ITC_4 (0x00040000) +#define USB_USBCMD_ITC_8 (0x00080000) +#define USB_USBCMD_ITC_16 (0x00100000) +#define USB_USBCMD_ITC_32 (0x00200000) +#define USB_USBCMD_ITC_40 (0x00400000) +#define USB_USBCMD_FS_1024 (0x00000000) +#define USB_USBCMD_FS_512 (0x00000004) +#define USB_USBCMD_FS_256 (0x00000008) +#define USB_USBCMD_FS_128 (0x0000000C) +#define USB_USBCMD_FS_64 (0x00008000) +#define USB_USBCMD_FS_32 (0x00008004) +#define USB_USBCMD_FS_16 (0x00008008) +#define USB_USBCMD_FS_8 (0x0000800C) + +/* Bit definitions and macros for USB_USBSTS */ +#define USB_USBSTS_UI (0x00000001) +#define USB_USBSTS_UEI (0x00000002) +#define USB_USBSTS_PCI (0x00000004) +#define USB_USBSTS_FRI (0x00000008) +#define USB_USBSTS_SEI (0x00000010) +#define USB_USBSTS_AAI (0x00000020) +#define USB_USBSTS_URI (0x00000040) +#define USB_USBSTS_SRI (0x00000080) +#define USB_USBSTS_SLI (0x00000100) +#define USB_USBSTS_HCH (0x00001000) +#define USB_USBSTS_RCL (0x00002000) +#define USB_USBSTS_PS (0x00004000) +#define USB_USBSTS_AS (0x00008000) + +/* Bit definitions and macros for USB_USBINTR */ +#define USB_USBINTR_UE (0x00000001) +#define USB_USBINTR_UEE (0x00000002) +#define USB_USBINTR_PCE (0x00000004) +#define USB_USBINTR_FRE (0x00000008) +#define USB_USBINTR_SEE (0x00000010) +#define USB_USBINTR_AAE (0x00000020) +#define USB_USBINTR_URE (0x00000040) +#define USB_USBINTR_SRE (0x00000080) +#define USB_USBINTR_SLE (0x00000100) + +/* Bit definitions and macros for USB_FRINDEX */ +#define USB_FRINDEX_FRINDEX(x) (((x)&0x00003FFF)<<0) + +/* Bit definitions and macros for USB_PERIODICLISTBASE */ +#define USB_PERIODICLISTBASE_PERBASE(x) (((x)&0x000FFFFF)<<12) + +/* Bit definitions and macros for USB_DEVICEADDR */ +#define USB_DEVICEADDR_USBADR(x) (((x)&0x0000007F)<<25) + +/* Bit definitions and macros for USB_ASYNCLISTADDR */ +#define USB_ASYNCLISTADDR_ASYBASE(x) (((x)&0x07FFFFFF)<<5) + +/* Bit definitions and macros for USB_EPLISTADDR */ +#define USB_EPLISTADDR_EPBASE(x) (((x)&0x001FFFFF)<<11) + +/* Bit definitions and macros for USB_ASNCTTSTS */ +#define USB_ASNCTTSTS_TTAS (0x00000001) +#define USB_ASNCTTSTS_TTAC (0x00000002) + +/* Bit definitions and macros for USB_BURSTSIZE */ +#define USB_BURSTSIZE_RXPBURST(x) (((x)&0x000000FF)<<0) +#define USB_BURSTSIZE_TXPBURST(x) (((x)&0x000000FF)<<8) + +/* Bit definitions and macros for USB_TXFILLTUNING */ +#define USB_TXFILLTUNING_TXSCHOH(x) (((x)&0x000000FF)<<0) +#define USB_TXFILLTUNING_TXSCHHEALTH(x) (((x)&0x0000001F)<<8) +#define USB_TXFILLTUNING_TXFIFOTHRES(x) (((x)&0x0000003F)<<16) + +/* Bit definitions and macros for USB_TXTTFILLTUNING */ +#define USB_TXTTFILLTUNING_TXTTSCHOH(x) (((x)&0x0000001F)<<0) +#define USB_TXTTFILLTUNING_TXTTSCHHEALTH(x) (((x)&0x0000001F)<<8) + +/* Bit definitions and macros for USB_ULPI_VIEWPORT */ +#define USB_ULPI_VIEWPORT_ULPI_DATWR(x) (((x)&0x000000FF)<<0) +#define USB_ULPI_VIEWPORT_ULPI_DATRD(x) (((x)&0x000000FF)<<8) +#define USB_ULPI_VIEWPORT_ULPI_ADDR(x) (((x)&0x000000FF)<<16) +#define USB_ULPI_VIEWPORT_ULPI_PORT(x) (((x)&0x00000007)<<24) +#define USB_ULPI_VIEWPORT_ULPI_SS (0x08000000) +#define USB_ULPI_VIEWPORT_ULPI_RW (0x20000000) +#define USB_ULPI_VIEWPORT_ULPI_RUN (0x40000000) +#define USB_ULPI_VIEWPORT_ULPI_WU (0x80000000) + +/* Bit definitions and macros for USB_CONFIGFLAG */ +#define USB_CONFIGFLAG_CONFIGFLAG(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for USB_PORTSC */ +#define USB_PORTSC_CCS (0x00000001) +#define USB_PORTSC_CSC (0x00000002) +#define USB_PORTSC_PE (0x00000004) +#define USB_PORTSC_PEC (0x00000008) +#define USB_PORTSC_OCA (0x00000010) +#define USB_PORTSC_OCC (0x00000020) +#define USB_PORTSC_FPR (0x00000040) +#define USB_PORTSC_SUSP (0x00000080) +#define USB_PORTSC_PR (0x00000100) +#define USB_PORTSC_LS(x) (((x)&0x00000003)<<10) +#define USB_PORTSC_PP (0x00001000) +#define USB_PORTSC_PO (0x00002000) +#define USB_PORTSC_PIC(x) (((x)&0x00000003)<<14) +#define USB_PORTSC_PTC(x) (((x)&0x0000000F)<<16) +#define USB_PORTSC_WLCN (0x00100000) +#define USB_PORTSC_WKDS (0x00200000) +#define USB_PORTSC_WKOC (0x00400000) +#define USB_PORTSC_PHCD (0x00800000) +#define USB_PORTSC_PFSC (0x01000000) +#define USB_PORTSC_PSPD(x) (((x)&0x00000003)<<26) +#define USB_PORTSC_PTS(x) (((x)&0x00000003)<<30) +#define USB_PORTSC_PTS_ULPI (0x80000000) +#define USB_PORTSC_PTS_FS_LS (0xC0000000) +#define USB_PORTSC_PSPD_FULL (0x00000000) +#define USB_PORTSC_PSPD_LOW (0x04000000) +#define USB_PORTSC_PSPD_HIGH (0x08000000) +#define USB_PORTSC_PTC_DISBALE (0x00000000) +#define USB_PORTSC_PTC_JSTATE (0x00010000) +#define USB_PORTSC_PTC_KSTATE (0x00020000) +#define USB_PORTSC_PTC_SEQ_NAK (0x00030000) +#define USB_PORTSC_PTC_PACKET (0x00040000) +#define USB_PORTSC_PTC_FORCE_ENABLE (0x00050000) +#define USB_PORTSC_PIC_OFF (0x00000000) +#define USB_PORTSC_PIC_AMBER (0x00004000) +#define USB_PORTSC_PIC_GREEN (0x00008000) +#define USB_PORTSC_LS_SE0 (0x00000000) +#define USB_PORTSC_LS_JSTATE (0x00000400) +#define USB_PORTSC_LS_KSTATE (0x00000800) + +/* Bit definitions and macros for USB_OTGSC */ +#define USB_OTGSC_VD (0x00000001) +#define USB_OTGSC_VC (0x00000002) +#define USB_OTGSC_OT (0x00000008) +#define USB_OTGSC_DP (0x00000010) +#define USB_OTGSC_ID (0x00000100) +#define USB_OTGSC_AVV (0x00000200) +#define USB_OTGSC_ASV (0x00000400) +#define USB_OTGSC_BSV (0x00000800) +#define USB_OTGSC_BSE (0x00001000) +#define USB_OTGSC_1MST (0x00002000) +#define USB_OTGSC_DPS (0x00004000) +#define USB_OTGSC_IDIS (0x00010000) +#define USB_OTGSC_AVVIS (0x00020000) +#define USB_OTGSC_ASVIS (0x00040000) +#define USB_OTGSC_BSVIS (0x00080000) +#define USB_OTGSC_BSEIS (0x00100000) +#define USB_OTGSC_1MSS (0x00200000) +#define USB_OTGSC_DPIS (0x00400000) +#define USB_OTGSC_IDIE (0x01000000) +#define USB_OTGSC_AVVIE (0x02000000) +#define USB_OTGSC_ASVIE (0x04000000) +#define USB_OTGSC_BSVIE (0x08000000) +#define USB_OTGSC_BSEIE (0x10000000) +#define USB_OTGSC_1MSE (0x20000000) +#define USB_OTGSC_DPIE (0x40000000) +#define USB_OTGSC_CLEAR (0x007F0000) +#define USB_OTGSC_ENABLE_ALL (0x7F000000) + +/* Bit definitions and macros for USB_USBMODE */ +#define USB_USBMODE_CM(x) (((x)&0x00000003)<<0) +#define USB_USBMODE_SLOM (0x00000008) +#define USB_USBMODE_SDIS (0x00000010) +#define USB_USBMODE_CM_IDLE (0x00000000) +#define USB_USBMODE_CM_DEVICE (0x00000002) +#define USB_USBMODE_CM_HOST (0x00000003) +#define USB_USBMODE_ES (0x00000004) + +/* Bit definitions and macros for USB_EPSETUPSR */ +#define USB_EPSETUPSR_EPSETUPSTAT(x) (((x)&0x0000003F)<<0) + +/* Bit definitions and macros for USB_EPPRIME */ +#define USB_EPPRIME_PERB(x) (((x)&0x0000003F)<<0) +#define USB_EPPRIME_PETB(x) (((x)&0x0000003F)<<16) +#define USB_EPPRIME_PETB0 (0x00010000) +#define USB_EPPRIME_PETB1 (0x00020000) +#define USB_EPPRIME_PETB2 (0x00040000) +#define USB_EPPRIME_PETB3 (0x00080000) +#define USB_EPPRIME_PETB4 (0x00100000) +#define USB_EPPRIME_PETB5 (0x00200000) +#define USB_EPPRIME_PERB0 (0x00000001) +#define USB_EPPRIME_PERB1 (0x00000002) +#define USB_EPPRIME_PERB2 (0x00000004) +#define USB_EPPRIME_PERB3 (0x00000008) +#define USB_EPPRIME_PERB4 (0x00000010) +#define USB_EPPRIME_PERB5 (0x00000020) + +/* Bit definitions and macros for USB_EPFLUSH */ +#define USB_EPFLUSH_FERB(x) (((x)&0x0000003F)<<0) +#define USB_EPFLUSH_FETB(x) (((x)&0x0000003F)<<16) +#define USB_EPFLUSH_FETB0 (0x00010000) +#define USB_EPFLUSH_FETB1 (0x00020000) +#define USB_EPFLUSH_FETB2 (0x00040000) +#define USB_EPFLUSH_FETB3 (0x00080000) +#define USB_EPFLUSH_FETB4 (0x00100000) +#define USB_EPFLUSH_FETB5 (0x00200000) +#define USB_EPFLUSH_FERB0 (0x00000001) +#define USB_EPFLUSH_FERB1 (0x00000002) +#define USB_EPFLUSH_FERB2 (0x00000004) +#define USB_EPFLUSH_FERB3 (0x00000008) +#define USB_EPFLUSH_FERB4 (0x00000010) +#define USB_EPFLUSH_FERB5 (0x00000020) + +/* Bit definitions and macros for USB_EPSR */ +#define USB_EPSR_ERBR(x) (((x)&0x0000003F)<<0) +#define USB_EPSR_ETBR(x) (((x)&0x0000003F)<<16) +#define USB_EPSR_ETBR0 (0x00010000) +#define USB_EPSR_ETBR1 (0x00020000) +#define USB_EPSR_ETBR2 (0x00040000) +#define USB_EPSR_ETBR3 (0x00080000) +#define USB_EPSR_ETBR4 (0x00100000) +#define USB_EPSR_ETBR5 (0x00200000) +#define USB_EPSR_ERBR0 (0x00000001) +#define USB_EPSR_ERBR1 (0x00000002) +#define USB_EPSR_ERBR2 (0x00000004) +#define USB_EPSR_ERBR3 (0x00000008) +#define USB_EPSR_ERBR4 (0x00000010) +#define USB_EPSR_ERBR5 (0x00000020) + +/* Bit definitions and macros for USB_EPCOMPLETE */ +#define USB_EPCOMPLETE_ERCE(x) (((x)&0x0000003F)<<0) +#define USB_EPCOMPLETE_ETCE(x) (((x)&0x0000003F)<<16) +#define USB_EPCOMPLETE_ETCE0 (0x00010000) +#define USB_EPCOMPLETE_ETCE1 (0x00020000) +#define USB_EPCOMPLETE_ETCE2 (0x00040000) +#define USB_EPCOMPLETE_ETCE3 (0x00080000) +#define USB_EPCOMPLETE_ETCE4 (0x00100000) +#define USB_EPCOMPLETE_ETCE5 (0x00200000) +#define USB_EPCOMPLETE_ERCE0 (0x00000001) +#define USB_EPCOMPLETE_ERCE1 (0x00000002) +#define USB_EPCOMPLETE_ERCE2 (0x00000004) +#define USB_EPCOMPLETE_ERCE3 (0x00000008) +#define USB_EPCOMPLETE_ERCE4 (0x00000010) +#define USB_EPCOMPLETE_ERCE5 (0x00000020) + +/* Bit definitions and macros for USB_EPCR0 */ +#define USB_EPCR0_RXS (0x00000001) +#define USB_EPCR0_RXT(x) (((x)&0x00000003)<<2) +#define USB_EPCR0_RXE (0x00000080) +#define USB_EPCR0_TXS (0x00010000) +#define USB_EPCR0_TXT(x) (((x)&0x00000003)<<18) +#define USB_EPCR0_TXE (0x00800000) + +/* Bit definitions and macros for USB_EPCR */ +#define USB_EPCR_RXS (0x00000001) +#define USB_EPCR_RXD (0x00000002) +#define USB_EPCR_RXT(x) (((x)&0x00000003)<<2) +#define USB_EPCR_RXI (0x00000020) +#define USB_EPCR_RXR (0x00000040) +#define USB_EPCR_RXE (0x00000080) +#define USB_EPCR_TXS (0x00010000) +#define USB_EPCR_TXD (0x00020000) +#define USB_EPCR_TXT(x) (((x)&0x00000003)<<18) +#define USB_EPCR_TXI (0x00200000) +#define USB_EPCR_TXR (0x00400000) +#define USB_EPCR_TXE (0x00800000) +#define USB_EPCR_TXT_CONTROL (0x00000000) +#define USB_EPCR_TXT_ISO (0x00040000) +#define USB_EPCR_TXT_BULK (0x00080000) +#define USB_EPCR_TXT_INT (0x000C0000) +#define USB_EPCR_RXT_CONTROL (0x00000000) +#define USB_EPCR_RXT_ISO (0x00000004) +#define USB_EPCR_RXT_BULK (0x00000008) +#define USB_EPCR_RXT_INT (0x0000000C) + +/********************************************************************* +* SDRAM Controller (SDRAMC) +*********************************************************************/ +/* Bit definitions and macros for SDRAMC_SDMR */ +#define SDRAMC_SDMR_BNKAD_LEMR (0x40000000) +#define SDRAMC_SDMR_BNKAD_LMR (0x00000000) +#define SDRAMC_SDMR_AD(x) (((x)&0x00000FFF)<<18) +#define SDRAMC_SDMR_CMD (0x00010000) + +/* Bit definitions and macros for SDRAMC_SDCR */ +#define SDRAMC_SDCR_MODE_EN (0x80000000) +#define SDRAMC_SDCR_CKE (0x40000000) +#define SDRAMC_SDCR_DDR (0x20000000) +#define SDRAMC_SDCR_REF (0x10000000) +#define SDRAMC_SDCR_MUX(x) (((x)&0x00000003)<<24) +#define SDRAMC_SDCR_OE_RULE (0x00400000) +#define SDRAMC_SDCR_RCNT(x) (((x)&0x0000003F)<<16) +#define SDRAMC_SDCR_PS_32 (0x00000000) +#define SDRAMC_SDCR_PS_16 (0x00002000) +#define SDRAMC_SDCR_DQS_OE(x) (((x)&0x0000000F)<<8) +#define SDRAMC_SDCR_IREF (0x00000004) +#define SDRAMC_SDCR_IPALL (0x00000002) + +/* Bit definitions and macros for SDRAMC_SDCFG1 */ +#define SDRAMC_SDCFG1_SRD2RW(x) (((x)&0x0000000F)<<28) +#define SDRAMC_SDCFG1_SWT2RD(x) (((x)&0x00000007)<<24) +#define SDRAMC_SDCFG1_RDLAT(x) (((x)&0x0000000F)<<20) +#define SDRAMC_SDCFG1_ACT2RW(x) (((x)&0x00000007)<<16) +#define SDRAMC_SDCFG1_PRE2ACT(x) (((x)&0x00000007)<<12) +#define SDRAMC_SDCFG1_REF2ACT(x) (((x)&0x0000000F)<<8) +#define SDRAMC_SDCFG1_WTLAT(x) (((x)&0x00000007)<<4) + +/* Bit definitions and macros for SDRAMC_SDCFG2 */ +#define SDRAMC_SDCFG2_BRD2PRE(x) (((x)&0x0000000F)<<28) +#define SDRAMC_SDCFG2_BWT2RW(x) (((x)&0x0000000F)<<24) +#define SDRAMC_SDCFG2_BRD2WT(x) (((x)&0x0000000F)<<20) +#define SDRAMC_SDCFG2_BL(x) (((x)&0x0000000F)<<16) + +/* Bit definitions and macros for SDRAMC_SDDS */ +#define SDRAMC_SDDS_SB_E(x) (((x)&0x00000003)<<8) +#define SDRAMC_SDDS_SB_C(x) (((x)&0x00000003)<<6) +#define SDRAMC_SDDS_SB_A(x) (((x)&0x00000003)<<4) +#define SDRAMC_SDDS_SB_S(x) (((x)&0x00000003)<<2) +#define SDRAMC_SDDS_SB_D(x) ((x)&0x00000003) + +/* Bit definitions and macros for SDRAMC_SDCS */ +#define SDRAMC_SDCS_BASE(x) (((x)&0x00000FFF)<<20) +#define SDRAMC_SDCS_CSSZ(x) ((x)&0x0000001F) +#define SDRAMC_SDCS_CSSZ_4GBYTE (0x0000001F) +#define SDRAMC_SDCS_CSSZ_2GBYTE (0x0000001E) +#define SDRAMC_SDCS_CSSZ_1GBYTE (0x0000001D) +#define SDRAMC_SDCS_CSSZ_512MBYTE (0x0000001C) +#define SDRAMC_SDCS_CSSZ_256MBYTE (0x0000001B) +#define SDRAMC_SDCS_CSSZ_128MBYTE (0x0000001A) +#define SDRAMC_SDCS_CSSZ_64MBYTE (0x00000019) +#define SDRAMC_SDCS_CSSZ_32MBYTE (0x00000018) +#define SDRAMC_SDCS_CSSZ_16MBYTE (0x00000017) +#define SDRAMC_SDCS_CSSZ_8MBYTE (0x00000016) +#define SDRAMC_SDCS_CSSZ_4MBYTE (0x00000015) +#define SDRAMC_SDCS_CSSZ_2MBYTE (0x00000014) +#define SDRAMC_SDCS_CSSZ_1MBYTE (0x00000013) +#define SDRAMC_SDCS_CSSZ_DIABLE (0x00000000) + +/********************************************************************* +* Synchronous Serial Interface (SSI) +*********************************************************************/ +/* Bit definitions and macros for SSI_CR */ +#define SSI_CR_CIS (0x00000200) +#define SSI_CR_TCH (0x00000100) +#define SSI_CR_MCE (0x00000080) +#define SSI_CR_I2S_SLAVE (0x00000040) +#define SSI_CR_I2S_MASTER (0x00000020) +#define SSI_CR_I2S_NORMAL (0x00000000) +#define SSI_CR_SYN (0x00000010) +#define SSI_CR_NET (0x00000008) +#define SSI_CR_RE (0x00000004) +#define SSI_CR_TE (0x00000002) +#define SSI_CR_SSI_EN (0x00000001) + +/* Bit definitions and macros for SSI_ISR */ +#define SSI_ISR_CMDAU (0x00040000) +#define SSI_ISR_CMDDU (0x00020000) +#define SSI_ISR_RXT (0x00010000) +#define SSI_ISR_RDR1 (0x00008000) +#define SSI_ISR_RDR0 (0x00004000) +#define SSI_ISR_TDE1 (0x00002000) +#define SSI_ISR_TDE0 (0x00001000) +#define SSI_ISR_ROE1 (0x00000800) +#define SSI_ISR_ROE0 (0x00000400) +#define SSI_ISR_TUE1 (0x00000200) +#define SSI_ISR_TUE0 (0x00000100) +#define SSI_ISR_TFS (0x00000080) +#define SSI_ISR_RFS (0x00000040) +#define SSI_ISR_TLS (0x00000020) +#define SSI_ISR_RLS (0x00000010) +#define SSI_ISR_RFF1 (0x00000008) +#define SSI_ISR_RFF0 (0x00000004) +#define SSI_ISR_TFE1 (0x00000002) +#define SSI_ISR_TFE0 (0x00000001) + +/* Bit definitions and macros for SSI_IER */ +#define SSI_IER_RDMAE (0x00400000) +#define SSI_IER_RIE (0x00200000) +#define SSI_IER_TDMAE (0x00100000) +#define SSI_IER_TIE (0x00080000) +#define SSI_IER_CMDAU (0x00040000) +#define SSI_IER_CMDU (0x00020000) +#define SSI_IER_RXT (0x00010000) +#define SSI_IER_RDR1 (0x00008000) +#define SSI_IER_RDR0 (0x00004000) +#define SSI_IER_TDE1 (0x00002000) +#define SSI_IER_TDE0 (0x00001000) +#define SSI_IER_ROE1 (0x00000800) +#define SSI_IER_ROE0 (0x00000400) +#define SSI_IER_TUE1 (0x00000200) +#define SSI_IER_TUE0 (0x00000100) +#define SSI_IER_TFS (0x00000080) +#define SSI_IER_RFS (0x00000040) +#define SSI_IER_TLS (0x00000020) +#define SSI_IER_RLS (0x00000010) +#define SSI_IER_RFF1 (0x00000008) +#define SSI_IER_RFF0 (0x00000004) +#define SSI_IER_TFE1 (0x00000002) +#define SSI_IER_TFE0 (0x00000001) + +/* Bit definitions and macros for SSI_TCR */ +#define SSI_TCR_TXBIT0 (0x00000200) +#define SSI_TCR_TFEN1 (0x00000100) +#define SSI_TCR_TFEN0 (0x00000080) +#define SSI_TCR_TFDIR (0x00000040) +#define SSI_TCR_TXDIR (0x00000020) +#define SSI_TCR_TSHFD (0x00000010) +#define SSI_TCR_TSCKP (0x00000008) +#define SSI_TCR_TFSI (0x00000004) +#define SSI_TCR_TFSL (0x00000002) +#define SSI_TCR_TEFS (0x00000001) + +/* Bit definitions and macros for SSI_RCR */ +#define SSI_RCR_RXEXT (0x00000400) +#define SSI_RCR_RXBIT0 (0x00000200) +#define SSI_RCR_RFEN1 (0x00000100) +#define SSI_RCR_RFEN0 (0x00000080) +#define SSI_RCR_RSHFD (0x00000010) +#define SSI_RCR_RSCKP (0x00000008) +#define SSI_RCR_RFSI (0x00000004) +#define SSI_RCR_RFSL (0x00000002) +#define SSI_RCR_REFS (0x00000001) + +/* Bit definitions and macros for SSI_CCR */ +#define SSI_CCR_DIV2 (0x00040000) +#define SSI_CCR_PSR (0x00020000) +#define SSI_CCR_WL(x) (((x)&0x0000000F)<<13) +#define SSI_CCR_DC(x) (((x)&0x0000001F)<<8) +#define SSI_CCR_PM(x) ((x)&0x000000FF) + +/* Bit definitions and macros for SSI_FCSR */ +#define SSI_FCSR_RFCNT1(x) (((x)&0x0000000F)<<28) +#define SSI_FCSR_TFCNT1(x) (((x)&0x0000000F)<<24) +#define SSI_FCSR_RFWM1(x) (((x)&0x0000000F)<<20) +#define SSI_FCSR_TFWM1(x) (((x)&0x0000000F)<<16) +#define SSI_FCSR_RFCNT0(x) (((x)&0x0000000F)<<12) +#define SSI_FCSR_TFCNT0(x) (((x)&0x0000000F)<<8) +#define SSI_FCSR_RFWM0(x) (((x)&0x0000000F)<<4) +#define SSI_FCSR_TFWM0(x) ((x)&0x0000000F) + +/* Bit definitions and macros for SSI_ACR */ +#define SSI_ACR_FRDIV(x) (((x)&0x0000003F)<<5) +#define SSI_ACR_WR (0x00000010) +#define SSI_ACR_RD (0x00000008) +#define SSI_ACR_TIF (0x00000004) +#define SSI_ACR_FV (0x00000002) +#define SSI_ACR_AC97EN (0x00000001) + +/* Bit definitions and macros for SSI_ACADD */ +#define SSI_ACADD_SSI_ACADD(x) ((x)&0x0007FFFF) + +/* Bit definitions and macros for SSI_ACDAT */ +#define SSI_ACDAT_SSI_ACDAT(x) ((x)&0x0007FFFF) + +/* Bit definitions and macros for SSI_ATAG */ +#define SSI_ATAG_DDI_ATAG(x) ((x)&0x0000FFFF) + +/********************************************************************* +* Phase Locked Loop (PLL) +*********************************************************************/ +/* Bit definitions and macros for PLL_PODR */ +#define PLL_PODR_CPUDIV(x) (((x)&0x0F)<<4) +#define PLL_PODR_BUSDIV(x) ((x)&0x0F) + +/* Bit definitions and macros for PLL_PLLCR */ +#define PLL_PLLCR_DITHEN (0x80) +#define PLL_PLLCR_DITHDEV(x) ((x)&0x07) + +#endif /* mcf5329_h */ diff --git a/include/asm-m68k/mcfrtc.h b/include/asm-m68k/mcfrtc.h new file mode 100644 index 000000000..70785354f --- /dev/null +++ b/include/asm-m68k/mcfrtc.h @@ -0,0 +1,108 @@ +/* + * RealTime Clock + * + * (C) Copyright 2007 + * TsiChung Liew (Tsi-Chung.Liew@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __MCFRTC_H__ +#define __MCFRTC_H__ + +/* Real time Clock */ +typedef struct rtc_ctrl { + u32 hourmin; /* 0x00 Hours and Minutes Counter Register */ + u32 seconds; /* 0x04 Seconds Counter Register */ + u32 alrm_hm; /* 0x08 Hours and Minutes Alarm Register */ + u32 alrm_sec; /* 0x0C Seconds Alarm Register */ + u32 cr; /* 0x10 Control Register */ + u32 isr; /* 0x14 Interrupt Status Register */ + u32 ier; /* 0x18 Interrupt Enable Register */ + u32 stpwach; /* 0x1C Stopwatch Minutes Register */ + u32 days; /* 0x20 Days Counter Register */ + u32 alrm_day; /* 0x24 Days Alarm Register */ +} rtc_t; + +/* Bit definitions and macros for HOURMIN */ +#define RTC_HOURMIN_MINUTES(x) (((x)&0x0000003F)) +#define RTC_HOURMIN_HOURS(x) (((x)&0x0000001F)<<8) + +/* Bit definitions and macros for SECONDS */ +#define RTC_SECONDS_SECONDS(x) (((x)&0x0000003F)) + +/* Bit definitions and macros for ALRM_HM */ +#define RTC_ALRM_HM_MINUTES(x) (((x)&0x0000003F)) +#define RTC_ALRM_HM_HOURS(x) (((x)&0x0000001F)<<8) + +/* Bit definitions and macros for ALRM_SEC */ +#define RTC_ALRM_SEC_SECONDS(x) (((x)&0x0000003F)) + +/* Bit definitions and macros for CR */ +#define RTC_CR_SWR (0x00000001) +#define RTC_CR_XTL(x) (((x)&0x00000003)<<5) +#define RTC_CR_EN (0x00000080) +#define RTC_CR_32768 (0x0) +#define RTC_CR_32000 (0x1) +#define RTC_CR_38400 (0x2) + +/* Bit definitions and macros for ISR */ +#define RTC_ISR_SW (0x00000001) +#define RTC_ISR_MIN (0x00000002) +#define RTC_ISR_ALM (0x00000004) +#define RTC_ISR_DAY (0x00000008) +#define RTC_ISR_1HZ (0x00000010) +#define RTC_ISR_HR (0x00000020) +#define RTC_ISR_2HZ (0x00000080) +#define RTC_ISR_SAM0 (0x00000100) +#define RTC_ISR_SAM1 (0x00000200) +#define RTC_ISR_SAM2 (0x00000400) +#define RTC_ISR_SAM3 (0x00000800) +#define RTC_ISR_SAM4 (0x00001000) +#define RTC_ISR_SAM5 (0x00002000) +#define RTC_ISR_SAM6 (0x00004000) +#define RTC_ISR_SAM7 (0x00008000) + +/* Bit definitions and macros for IER */ +#define RTC_IER_SW (0x00000001) +#define RTC_IER_MIN (0x00000002) +#define RTC_IER_ALM (0x00000004) +#define RTC_IER_DAY (0x00000008) +#define RTC_IER_1HZ (0x00000010) +#define RTC_IER_HR (0x00000020) +#define RTC_IER_2HZ (0x00000080) +#define RTC_IER_SAM0 (0x00000100) +#define RTC_IER_SAM1 (0x00000200) +#define RTC_IER_SAM2 (0x00000400) +#define RTC_IER_SAM3 (0x00000800) +#define RTC_IER_SAM4 (0x00001000) +#define RTC_IER_SAM5 (0x00002000) +#define RTC_IER_SAM6 (0x00004000) +#define RTC_IER_SAM7 (0x00008000) + +/* Bit definitions and macros for STPWCH */ +#define RTC_STPWCH_CNT(x) (((x)&0x0000003F)) + +/* Bit definitions and macros for DAYS */ +#define RTC_DAYS_DAYS(x) (((x)&0x0000FFFF)) + +/* Bit definitions and macros for ALRM_DAY */ +#define RTC_ALRM_DAY_DAYS(x) (((x)&0x0000FFFF)) + +#endif /* __MCFRTC_H__ */ diff --git a/include/asm-m68k/mcftimer.h b/include/asm-m68k/mcftimer.h index a73b80eaf..988860d07 100644 --- a/include/asm-m68k/mcftimer.h +++ b/include/asm-m68k/mcftimer.h @@ -35,32 +35,31 @@ * Get address specific defines for this ColdFire member. */ #if defined(CONFIG_M5204) || defined(CONFIG_M5206) || defined(CONFIG_M5206e) -#define MCFTIMER_BASE1 0x100 /* Base address of TIMER1 */ -#define MCFTIMER_BASE2 0x120 /* Base address of TIMER2 */ +#define MCFTIMER_BASE1 0x100 /* Base address of TIMER1 */ +#define MCFTIMER_BASE2 0x120 /* Base address of TIMER2 */ #elif defined(CONFIG_M5272) -#define MCFTIMER_BASE1 0x200 /* Base address of TIMER1 */ -#define MCFTIMER_BASE2 0x220 /* Base address of TIMER2 */ -#define MCFTIMER_BASE3 0x240 /* Base address of TIMER4 */ -#define MCFTIMER_BASE4 0x260 /* Base address of TIMER3 */ +#define MCFTIMER_BASE1 0x200 /* Base address of TIMER1 */ +#define MCFTIMER_BASE2 0x220 /* Base address of TIMER2 */ +#define MCFTIMER_BASE3 0x240 /* Base address of TIMER4 */ +#define MCFTIMER_BASE4 0x260 /* Base address of TIMER3 */ #elif defined(CONFIG_M5249) || defined(CONFIG_M5307) || defined(CONFIG_M5407) -#define MCFTIMER_BASE1 0x140 /* Base address of TIMER1 */ -#define MCFTIMER_BASE2 0x180 /* Base address of TIMER2 */ +#define MCFTIMER_BASE1 0x140 /* Base address of TIMER1 */ +#define MCFTIMER_BASE2 0x180 /* Base address of TIMER2 */ #elif defined(CONFIG_M5282) | defined(CONFIG_M5271) -#define MCFTIMER_BASE1 0x150000 /* Base address of TIMER1 */ -#define MCFTIMER_BASE2 0x160000 /* Base address of TIMER2 */ -#define MCFTIMER_BASE3 0x170000 /* Base address of TIMER4 */ +#define MCFTIMER_BASE1 0x150000 /* Base address of TIMER1 */ +#define MCFTIMER_BASE2 0x160000 /* Base address of TIMER2 */ +#define MCFTIMER_BASE3 0x170000 /* Base address of TIMER4 */ #define MCFTIMER_BASE4 0x180000 /* Base address of TIMER3 */ #endif /* * Define the TIMER register set addresses. */ -#define MCFTIMER_TMR 0x00 /* Timer Mode reg (r/w) */ -#define MCFTIMER_TRR 0x02 /* Timer Reference (r/w) */ -#define MCFTIMER_TCR 0x04 /* Timer Capture reg (r/w) */ -#define MCFTIMER_TCN 0x06 /* Timer Counter reg (r/w) */ -#define MCFTIMER_TER 0x11 /* Timer Event reg (r/w) */ - +#define MCFTIMER_TMR 0x00 /* Timer Mode reg (r/w) */ +#define MCFTIMER_TRR 0x02 /* Timer Reference (r/w) */ +#define MCFTIMER_TCR 0x04 /* Timer Capture reg (r/w) */ +#define MCFTIMER_TCN 0x06 /* Timer Counter reg (r/w) */ +#define MCFTIMER_TER 0x11 /* Timer Event reg (r/w) */ /* * Define the TIMER register set addresses for 5282. @@ -73,29 +72,29 @@ * Bit definitions for the Timer Mode Register (TMR). * Register bit flags are common accross ColdFires. */ -#define MCFTIMER_TMR_PREMASK 0xff00 /* Prescalar mask */ -#define MCFTIMER_TMR_DISCE 0x0000 /* Disable capture */ -#define MCFTIMER_TMR_ANYCE 0x00c0 /* Capture any edge */ -#define MCFTIMER_TMR_FALLCE 0x0080 /* Capture fallingedge */ -#define MCFTIMER_TMR_RISECE 0x0040 /* Capture rising edge */ -#define MCFTIMER_TMR_ENOM 0x0020 /* Enable output toggle */ -#define MCFTIMER_TMR_DISOM 0x0000 /* Do single output pulse */ -#define MCFTIMER_TMR_ENORI 0x0010 /* Enable ref interrupt */ -#define MCFTIMER_TMR_DISORI 0x0000 /* Disable ref interrupt */ -#define MCFTIMER_TMR_RESTART 0x0008 /* Restart counter */ -#define MCFTIMER_TMR_FREERUN 0x0000 /* Free running counter */ -#define MCFTIMER_TMR_CLKTIN 0x0006 /* Input clock is TIN */ -#define MCFTIMER_TMR_CLK16 0x0004 /* Input clock is /16 */ -#define MCFTIMER_TMR_CLK1 0x0002 /* Input clock is /1 */ -#define MCFTIMER_TMR_CLKSTOP 0x0000 /* Stop counter */ -#define MCFTIMER_TMR_ENABLE 0x0001 /* Enable timer */ -#define MCFTIMER_TMR_DISABLE 0x0000 /* Disable timer */ +#define MCFTIMER_TMR_PREMASK 0xff00 /* Prescalar mask */ +#define MCFTIMER_TMR_DISCE 0x0000 /* Disable capture */ +#define MCFTIMER_TMR_ANYCE 0x00c0 /* Capture any edge */ +#define MCFTIMER_TMR_FALLCE 0x0080 /* Capture fallingedge */ +#define MCFTIMER_TMR_RISECE 0x0040 /* Capture rising edge */ +#define MCFTIMER_TMR_ENOM 0x0020 /* Enable output toggle */ +#define MCFTIMER_TMR_DISOM 0x0000 /* Do single output pulse */ +#define MCFTIMER_TMR_ENORI 0x0010 /* Enable ref interrupt */ +#define MCFTIMER_TMR_DISORI 0x0000 /* Disable ref interrupt */ +#define MCFTIMER_TMR_RESTART 0x0008 /* Restart counter */ +#define MCFTIMER_TMR_FREERUN 0x0000 /* Free running counter */ +#define MCFTIMER_TMR_CLKTIN 0x0006 /* Input clock is TIN */ +#define MCFTIMER_TMR_CLK16 0x0004 /* Input clock is /16 */ +#define MCFTIMER_TMR_CLK1 0x0002 /* Input clock is /1 */ +#define MCFTIMER_TMR_CLKSTOP 0x0000 /* Stop counter */ +#define MCFTIMER_TMR_ENABLE 0x0001 /* Enable timer */ +#define MCFTIMER_TMR_DISABLE 0x0000 /* Disable timer */ /* * Bit definitions for the Timer Event Registers (TER). */ -#define MCFTIMER_TER_CAP 0x01 /* Capture event */ -#define MCFTIMER_TER_REF 0x02 /* Refernece event */ +#define MCFTIMER_TER_CAP 0x01 /* Capture event */ +#define MCFTIMER_TER_REF 0x02 /* Refernece event */ /* * Bit definitions for the 5282 PIT Control and Status Register (PCSR). @@ -108,6 +107,77 @@ #define MCFTIMER_PCSR_HALTED 0x0020 #define MCFTIMER_PCSR_DOZE 0x0040 +/****************************************************************************/ +/* New Timer structure */ +/****************************************************************************/ +/* DMA Timer module registers */ +typedef struct dtimer_ctrl { + u16 tmr; /* 0x00 Mode register */ + u8 txmr; /* 0x02 Extended Mode register */ + u8 ter; /* 0x03 Event register */ + u32 trr; /* 0x04 Reference register */ + u32 tcr; /* 0x08 Capture register */ + u32 tcn; /* 0x0C Counter register */ +} dtmr_t; + +/*Programmable Interrupt Timer */ +typedef struct pit_ctrl { + u16 pcsr; /* 0x00 Control and Status Register */ + u16 pmr; /* 0x02 Modulus Register */ + u16 pcntr; /* 0x04 Count Register */ +} pit_t; + +/********************************************************************* +* DMA Timers (DTIM) +*********************************************************************/ +/* Bit definitions and macros for DTMR */ +#define DTIM_DTMR_RST (0x0001) /* Reset */ +#define DTIM_DTMR_CLK(x) (((x)&0x0003)<<1) /* Input clock source */ +#define DTIM_DTMR_FRR (0x0008) /* Free run/restart */ +#define DTIM_DTMR_ORRI (0x0010) /* Output reference request/interrupt enable */ +#define DTIM_DTMR_OM (0x0020) /* Output Mode */ +#define DTIM_DTMR_CE(x) (((x)&0x0003)<<6) /* Capture Edge */ +#define DTIM_DTMR_PS(x) (((x)&0x00FF)<<8) /* Prescaler value */ +#define DTIM_DTMR_RST_EN (0x0001) +#define DTIM_DTMR_RST_RST (0x0000) +#define DTIM_DTMR_CE_ANY (0x00C0) +#define DTIM_DTMR_CE_FALL (0x0080) +#define DTIM_DTMR_CE_RISE (0x0040) +#define DTIM_DTMR_CE_NONE (0x0000) +#define DTIM_DTMR_CLK_DTIN (0x0006) +#define DTIM_DTMR_CLK_DIV16 (0x0004) +#define DTIM_DTMR_CLK_DIV1 (0x0002) +#define DTIM_DTMR_CLK_STOP (0x0000) + +/* Bit definitions and macros for DTXMR */ +#define DTIM_DTXMR_MODE16 (0x01) /* Increment Mode */ +#define DTIM_DTXMR_DMAEN (0x80) /* DMA request */ + +/* Bit definitions and macros for DTER */ +#define DTIM_DTER_CAP (0x01) /* Capture event */ +#define DTIM_DTER_REF (0x02) /* Output reference event */ + +/********************************************************************* +* +* Programmable Interrupt Timer Modules (PIT) +* +*********************************************************************/ + +/* Bit definitions and macros for PCSR */ +#define PIT_PCSR_EN (0x0001) +#define PIT_PCSR_RLD (0x0002) +#define PIT_PCSR_PIF (0x0004) +#define PIT_PCSR_PIE (0x0008) +#define PIT_PCSR_OVW (0x0010) +#define PIT_PCSR_HALTED (0x0020) +#define PIT_PCSR_DOZE (0x0040) +#define PIT_PCSR_PRE(x) (((x)&0x000F)<<8) + +/* Bit definitions and macros for PMR */ +#define PIT_PMR_PM(x) (x) + +/* Bit definitions and macros for PCNTR */ +#define PIT_PCNTR_PC(x) (x) /****************************************************************************/ -#endif /* mcftimer_h */ +#endif /* mcftimer_h */ diff --git a/include/asm-m68k/mcfuart.h b/include/asm-m68k/mcfuart.h index 7c0999d61..43b49a87c 100644 --- a/include/asm-m68k/mcfuart.h +++ b/include/asm-m68k/mcfuart.h @@ -36,106 +36,105 @@ * space. */ #if defined(CONFIG_M5272) -#define MCFUART_BASE1 0x100 /* Base address of UART1 */ -#define MCFUART_BASE2 0x140 /* Base address of UART2 */ +#define MCFUART_BASE1 0x100 /* Base address of UART1 */ +#define MCFUART_BASE2 0x140 /* Base address of UART2 */ #elif defined(CONFIG_M5204) || defined(CONFIG_M5206) || defined(CONFIG_M5206e) #if defined(CONFIG_NETtel) -#define MCFUART_BASE1 0x180 /* Base address of UART1 */ -#define MCFUART_BASE2 0x140 /* Base address of UART2 */ +#define MCFUART_BASE1 0x180 /* Base address of UART1 */ +#define MCFUART_BASE2 0x140 /* Base address of UART2 */ #else -#define MCFUART_BASE1 0x140 /* Base address of UART1 */ -#define MCFUART_BASE2 0x180 /* Base address of UART2 */ +#define MCFUART_BASE1 0x140 /* Base address of UART1 */ +#define MCFUART_BASE2 0x180 /* Base address of UART2 */ #endif #elif defined(CONFIG_M5282) || defined(CONFIG_M5271) -#define MCFUART_BASE1 0x200 /* Base address of UART1 */ -#define MCFUART_BASE2 0x240 /* Base address of UART2 */ -#define MCFUART_BASE3 0x280 /* Base address of UART3 */ +#define MCFUART_BASE1 0x200 /* Base address of UART1 */ +#define MCFUART_BASE2 0x240 /* Base address of UART2 */ +#define MCFUART_BASE3 0x280 /* Base address of UART3 */ #elif defined(CONFIG_M5249) || defined(CONFIG_M5307) || defined(CONFIG_M5407) #if defined(CONFIG_NETtel) || defined(CONFIG_DISKtel) || defined(CONFIG_SECUREEDGEMP3) -#define MCFUART_BASE1 0x200 /* Base address of UART1 */ -#define MCFUART_BASE2 0x1c0 /* Base address of UART2 */ +#define MCFUART_BASE1 0x200 /* Base address of UART1 */ +#define MCFUART_BASE2 0x1c0 /* Base address of UART2 */ #else -#define MCFUART_BASE1 0x1c0 /* Base address of UART1 */ -#define MCFUART_BASE2 0x200 /* Base address of UART2 */ +#define MCFUART_BASE1 0x1c0 /* Base address of UART1 */ +#define MCFUART_BASE2 0x200 /* Base address of UART2 */ #endif #endif - /* * Define the ColdFire UART register set addresses. */ -#define MCFUART_UMR 0x00 /* Mode register (r/w) */ -#define MCFUART_USR 0x04 /* Status register (r) */ -#define MCFUART_UCSR 0x04 /* Clock Select (w) */ -#define MCFUART_UCR 0x08 /* Command register (w) */ -#define MCFUART_URB 0x0c /* Receiver Buffer (r) */ -#define MCFUART_UTB 0x0c /* Transmit Buffer (w) */ -#define MCFUART_UIPCR 0x10 /* Input Port Change (r) */ -#define MCFUART_UACR 0x10 /* Auxiliary Control (w) */ -#define MCFUART_UISR 0x14 /* Interrup Status (r) */ -#define MCFUART_UIMR 0x14 /* Interrupt Mask (w) */ -#define MCFUART_UBG1 0x18 /* Baud Rate MSB (r/w) */ -#define MCFUART_UBG2 0x1c /* Baud Rate LSB (r/w) */ +#define MCFUART_UMR 0x00 /* Mode register (r/w) */ +#define MCFUART_USR 0x04 /* Status register (r) */ +#define MCFUART_UCSR 0x04 /* Clock Select (w) */ +#define MCFUART_UCR 0x08 /* Command register (w) */ +#define MCFUART_URB 0x0c /* Receiver Buffer (r) */ +#define MCFUART_UTB 0x0c /* Transmit Buffer (w) */ +#define MCFUART_UIPCR 0x10 /* Input Port Change (r) */ +#define MCFUART_UACR 0x10 /* Auxiliary Control (w) */ +#define MCFUART_UISR 0x14 /* Interrup Status (r) */ +#define MCFUART_UIMR 0x14 /* Interrupt Mask (w) */ +#define MCFUART_UBG1 0x18 /* Baud Rate MSB (r/w) */ +#define MCFUART_UBG2 0x1c /* Baud Rate LSB (r/w) */ #ifdef CONFIG_M5272 -#define MCFUART_UTF 0x28 /* Transmitter FIFO (r/w) */ -#define MCFUART_URF 0x2c /* Receiver FIFO (r/w) */ -#define MCFUART_UFPD 0x30 /* Frac Prec. Divider (r/w) */ +#define MCFUART_UTF 0x28 /* Transmitter FIFO (r/w) */ +#define MCFUART_URF 0x2c /* Receiver FIFO (r/w) */ +#define MCFUART_UFPD 0x30 /* Frac Prec. Divider (r/w) */ #else -#define MCFUART_UIVR 0x30 /* Interrupt Vector (r/w) */ +#define MCFUART_UIVR 0x30 /* Interrupt Vector (r/w) */ #endif -#define MCFUART_UIPR 0x34 /* Input Port (r) */ -#define MCFUART_UOP1 0x38 /* Output Port Bit Set (w) */ -#define MCFUART_UOP0 0x3c /* Output Port Bit Reset (w) */ +#define MCFUART_UIPR 0x34 /* Input Port (r) */ +#define MCFUART_UOP1 0x38 /* Output Port Bit Set (w) */ +#define MCFUART_UOP0 0x3c /* Output Port Bit Reset (w) */ #ifdef CONFIG_M5249 /* Note: This isn't in the 5249 docs */ -#define MCFUART_UFPD 0x30 /* Frac Prec. Divider (r/w) */ +#define MCFUART_UFPD 0x30 /* Frac Prec. Divider (r/w) */ #endif /* * Define bit flags in Mode Register 1 (MR1). */ -#define MCFUART_MR1_RXRTS 0x80 /* Auto RTS flow control */ -#define MCFUART_MR1_RXIRQFULL 0x40 /* RX IRQ type FULL */ -#define MCFUART_MR1_RXIRQRDY 0x00 /* RX IRQ type RDY */ -#define MCFUART_MR1_RXERRBLOCK 0x20 /* RX block error mode */ -#define MCFUART_MR1_RXERRCHAR 0x00 /* RX char error mode */ +#define MCFUART_MR1_RXRTS 0x80 /* Auto RTS flow control */ +#define MCFUART_MR1_RXIRQFULL 0x40 /* RX IRQ type FULL */ +#define MCFUART_MR1_RXIRQRDY 0x00 /* RX IRQ type RDY */ +#define MCFUART_MR1_RXERRBLOCK 0x20 /* RX block error mode */ +#define MCFUART_MR1_RXERRCHAR 0x00 /* RX char error mode */ -#define MCFUART_MR1_PARITYNONE 0x10 /* No parity */ -#define MCFUART_MR1_PARITYEVEN 0x00 /* Even parity */ -#define MCFUART_MR1_PARITYODD 0x04 /* Odd parity */ -#define MCFUART_MR1_PARITYSPACE 0x08 /* Space parity */ -#define MCFUART_MR1_PARITYMARK 0x0c /* Mark parity */ +#define MCFUART_MR1_PARITYNONE 0x10 /* No parity */ +#define MCFUART_MR1_PARITYEVEN 0x00 /* Even parity */ +#define MCFUART_MR1_PARITYODD 0x04 /* Odd parity */ +#define MCFUART_MR1_PARITYSPACE 0x08 /* Space parity */ +#define MCFUART_MR1_PARITYMARK 0x0c /* Mark parity */ -#define MCFUART_MR1_CS5 0x00 /* 5 bits per char */ -#define MCFUART_MR1_CS6 0x01 /* 6 bits per char */ -#define MCFUART_MR1_CS7 0x02 /* 7 bits per char */ -#define MCFUART_MR1_CS8 0x03 /* 8 bits per char */ +#define MCFUART_MR1_CS5 0x00 /* 5 bits per char */ +#define MCFUART_MR1_CS6 0x01 /* 6 bits per char */ +#define MCFUART_MR1_CS7 0x02 /* 7 bits per char */ +#define MCFUART_MR1_CS8 0x03 /* 8 bits per char */ /* * Define bit flags in Mode Register 2 (MR2). */ -#define MCFUART_MR2_LOOPBACK 0x80 /* Loopback mode */ -#define MCFUART_MR2_REMOTELOOP 0xc0 /* Remote loopback mode */ -#define MCFUART_MR2_AUTOECHO 0x40 /* Automatic echo */ -#define MCFUART_MR2_TXRTS 0x20 /* Assert RTS on TX */ -#define MCFUART_MR2_TXCTS 0x10 /* Auto CTS flow control */ +#define MCFUART_MR2_LOOPBACK 0x80 /* Loopback mode */ +#define MCFUART_MR2_REMOTELOOP 0xc0 /* Remote loopback mode */ +#define MCFUART_MR2_AUTOECHO 0x40 /* Automatic echo */ +#define MCFUART_MR2_TXRTS 0x20 /* Assert RTS on TX */ +#define MCFUART_MR2_TXCTS 0x10 /* Auto CTS flow control */ -#define MCFUART_MR2_STOP1 0x07 /* 1 stop bit */ -#define MCFUART_MR2_STOP15 0x08 /* 1.5 stop bits */ -#define MCFUART_MR2_STOP2 0x0f /* 2 stop bits */ +#define MCFUART_MR2_STOP1 0x07 /* 1 stop bit */ +#define MCFUART_MR2_STOP15 0x08 /* 1.5 stop bits */ +#define MCFUART_MR2_STOP2 0x0f /* 2 stop bits */ /* * Define bit flags in Status Register (USR). */ -#define MCFUART_USR_RXBREAK 0x80 /* Received BREAK */ -#define MCFUART_USR_RXFRAMING 0x40 /* Received framing error */ -#define MCFUART_USR_RXPARITY 0x20 /* Received parity error */ -#define MCFUART_USR_RXOVERRUN 0x10 /* Received overrun error */ -#define MCFUART_USR_TXEMPTY 0x08 /* Transmitter empty */ -#define MCFUART_USR_TXREADY 0x04 /* Transmitter ready */ -#define MCFUART_USR_RXFULL 0x02 /* Receiver full */ -#define MCFUART_USR_RXREADY 0x01 /* Receiver ready */ +#define MCFUART_USR_RXBREAK 0x80 /* Received BREAK */ +#define MCFUART_USR_RXFRAMING 0x40 /* Received framing error */ +#define MCFUART_USR_RXPARITY 0x20 /* Received parity error */ +#define MCFUART_USR_RXOVERRUN 0x10 /* Received overrun error */ +#define MCFUART_USR_TXEMPTY 0x08 /* Transmitter empty */ +#define MCFUART_USR_TXREADY 0x04 /* Transmitter ready */ +#define MCFUART_USR_RXFULL 0x02 /* Receiver full */ +#define MCFUART_USR_RXREADY 0x01 /* Receiver ready */ #define MCFUART_USR_RXERR (MCFUART_USR_RXBREAK | MCFUART_USR_RXFRAMING | \ MCFUART_USR_RXPARITY | MCFUART_USR_RXOVERRUN) @@ -143,13 +142,13 @@ /* * Define bit flags in Clock Select Register (UCSR). */ -#define MCFUART_UCSR_RXCLKTIMER 0xd0 /* RX clock is timer */ -#define MCFUART_UCSR_RXCLKEXT16 0xe0 /* RX clock is external x16 */ -#define MCFUART_UCSR_RXCLKEXT1 0xf0 /* RX clock is external x1 */ +#define MCFUART_UCSR_RXCLKTIMER 0xd0 /* RX clock is timer */ +#define MCFUART_UCSR_RXCLKEXT16 0xe0 /* RX clock is external x16 */ +#define MCFUART_UCSR_RXCLKEXT1 0xf0 /* RX clock is external x1 */ -#define MCFUART_UCSR_TXCLKTIMER 0x0d /* TX clock is timer */ -#define MCFUART_UCSR_TXCLKEXT16 0x0e /* TX clock is external x16 */ -#define MCFUART_UCSR_TXCLKEXT1 0x0f /* TX clock is external x1 */ +#define MCFUART_UCSR_TXCLKTIMER 0x0d /* TX clock is timer */ +#define MCFUART_UCSR_TXCLKEXT16 0x0e /* TX clock is external x16 */ +#define MCFUART_UCSR_TXCLKEXT1 0x0f /* TX clock is external x1 */ /* * Define bit flags in Command Register (UCR). @@ -163,59 +162,200 @@ #define MCFUART_UCR_CMDBREAKSTART 0x60 /* Start BREAK */ #define MCFUART_UCR_CMDBREAKSTOP 0x70 /* Stop BREAK */ -#define MCFUART_UCR_TXNULL 0x00 /* No TX command */ -#define MCFUART_UCR_TXENABLE 0x04 /* Enable TX */ -#define MCFUART_UCR_TXDISABLE 0x08 /* Disable TX */ -#define MCFUART_UCR_RXNULL 0x00 /* No RX command */ -#define MCFUART_UCR_RXENABLE 0x01 /* Enable RX */ -#define MCFUART_UCR_RXDISABLE 0x02 /* Disable RX */ +#define MCFUART_UCR_TXNULL 0x00 /* No TX command */ +#define MCFUART_UCR_TXENABLE 0x04 /* Enable TX */ +#define MCFUART_UCR_TXDISABLE 0x08 /* Disable TX */ +#define MCFUART_UCR_RXNULL 0x00 /* No RX command */ +#define MCFUART_UCR_RXENABLE 0x01 /* Enable RX */ +#define MCFUART_UCR_RXDISABLE 0x02 /* Disable RX */ /* * Define bit flags in Input Port Change Register (UIPCR). */ -#define MCFUART_UIPCR_CTSCOS 0x10 /* CTS change of state */ -#define MCFUART_UIPCR_CTS 0x01 /* CTS value */ +#define MCFUART_UIPCR_CTSCOS 0x10 /* CTS change of state */ +#define MCFUART_UIPCR_CTS 0x01 /* CTS value */ /* * Define bit flags in Input Port Register (UIP). */ -#define MCFUART_UIPR_CTS 0x01 /* CTS value */ +#define MCFUART_UIPR_CTS 0x01 /* CTS value */ /* * Define bit flags in Output Port Registers (UOP). * Clear bit by writing to UOP0, set by writing to UOP1. */ -#define MCFUART_UOP_RTS 0x01 /* RTS set or clear */ +#define MCFUART_UOP_RTS 0x01 /* RTS set or clear */ /* * Define bit flags in the Auxiliary Control Register (UACR). */ -#define MCFUART_UACR_IEC 0x01 /* Input enable control */ +#define MCFUART_UACR_IEC 0x01 /* Input enable control */ /* * Define bit flags in Interrupt Status Register (UISR). * These same bits are used for the Interrupt Mask Register (UIMR). */ -#define MCFUART_UIR_COS 0x80 /* Change of state (CTS) */ -#define MCFUART_UIR_DELTABREAK 0x04 /* Break start or stop */ -#define MCFUART_UIR_RXREADY 0x02 /* Receiver ready */ -#define MCFUART_UIR_TXREADY 0x01 /* Transmitter ready */ +#define MCFUART_UIR_COS 0x80 /* Change of state (CTS) */ +#define MCFUART_UIR_DELTABREAK 0x04 /* Break start or stop */ +#define MCFUART_UIR_RXREADY 0x02 /* Receiver ready */ +#define MCFUART_UIR_TXREADY 0x01 /* Transmitter ready */ #ifdef CONFIG_M5272 /* * Define bit flags in the Transmitter FIFO Register (UTF). */ -#define MCFUART_UTF_TXB 0x1f /* transmitter data level */ -#define MCFUART_UTF_FULL 0x20 /* transmitter fifo full */ -#define MCFUART_UTF_TXS 0xc0 /* transmitter status */ +#define MCFUART_UTF_TXB 0x1f /* transmitter data level */ +#define MCFUART_UTF_FULL 0x20 /* transmitter fifo full */ +#define MCFUART_UTF_TXS 0xc0 /* transmitter status */ /* * Define bit flags in the Receiver FIFO Register (URF). */ -#define MCFUART_URF_RXB 0x1f /* receiver data level */ -#define MCFUART_URF_FULL 0x20 /* receiver fifo full */ -#define MCFUART_URF_RXS 0xc0 /* receiver status */ +#define MCFUART_URF_RXB 0x1f /* receiver data level */ +#define MCFUART_URF_FULL 0x20 /* receiver fifo full */ +#define MCFUART_URF_RXS 0xc0 /* receiver status */ #endif +#ifdef CONFIG_MCFUART +/* UART module registers */ +/* Register read/write struct */ +typedef struct uart { + u8 umr; /* 0x00 Mode Register */ + u8 resv0[0x3]; + union { + u8 usr; /* 0x04 Status Register */ + u8 ucsr; /* 0x04 Clock Select Register */ + }; + u8 resv1[0x3]; + u8 ucr; /* 0x08 Command Register */ + u8 resv2[0x3]; + union { + u8 utb; /* 0x0c Transmit Buffer */ + u8 urb; /* 0x0c Receive Buffer */ + }; + u8 resv3[0x3]; + union { + u8 uipcr; /* 0x10 Input Port Change Register */ + u8 uacr; /* 0x10 Auxiliary Control reg */ + }; + u8 resv4[0x3]; + union { + u8 uimr; /* 0x14 Interrupt Mask reg */ + u8 uisr; /* 0x14 Interrupt Status reg */ + }; + u8 resv5[0x3]; + u8 ubg1; /* 0x18 Counter Timer Upper Register */ + u8 resv6[0x3]; + u8 ubg2; /* 0x1c Counter Timer Lower Register */ + u8 resv7[0x17]; + u8 uip; /* 0x34 Input Port Register */ + u8 resv8[0x3]; + u8 uop1; /* 0x38 Output Port Set Register */ + u8 resv9[0x3]; + u8 uop0; /* 0x3c Output Port Reset Register */ +} uart_t; + +/********************************************************************* +* Universal Asynchronous Receiver Transmitter (UART) +*********************************************************************/ +/* Bit definitions and macros for UMR */ +#define UART_UMR_BC(x) (((x)&0x03)) +#define UART_UMR_PT (0x04) +#define UART_UMR_PM(x) (((x)&0x03)<<3) +#define UART_UMR_ERR (0x20) +#define UART_UMR_RXIRQ (0x40) +#define UART_UMR_RXRTS (0x80) +#define UART_UMR_SB(x) (((x)&0x0F)) +#define UART_UMR_TXCTS (0x10) /* Trsnsmit CTS */ +#define UART_UMR_TXRTS (0x20) /* Transmit RTS */ +#define UART_UMR_CM(x) (((x)&0x03)<<6) /* CM bits */ +#define UART_UMR_PM_MULTI_ADDR (0x1C) +#define UART_UMR_PM_MULTI_DATA (0x18) +#define UART_UMR_PM_NONE (0x10) +#define UART_UMR_PM_FORCE_HI (0x0C) +#define UART_UMR_PM_FORCE_LO (0x08) +#define UART_UMR_PM_ODD (0x04) +#define UART_UMR_PM_EVEN (0x00) +#define UART_UMR_BC_5 (0x00) +#define UART_UMR_BC_6 (0x01) +#define UART_UMR_BC_7 (0x02) +#define UART_UMR_BC_8 (0x03) +#define UART_UMR_CM_NORMAL (0x00) +#define UART_UMR_CM_ECH (0x40) +#define UART_UMR_CM_LOCAL_LOOP (0x80) +#define UART_UMR_CM_REMOTE_LOOP (0xC0) +#define UART_UMR_SB_STOP_BITS_1 (0x07) +#define UART_UMR_SB_STOP_BITS_15 (0x08) +#define UART_UMR_SB_STOP_BITS_2 (0x0F) + +/* Bit definitions and macros for USR */ +#define UART_USR_RXRDY (0x01) +#define UART_USR_FFULL (0x02) +#define UART_USR_TXRDY (0x04) +#define UART_USR_TXEMP (0x08) +#define UART_USR_OE (0x10) +#define UART_USR_PE (0x20) +#define UART_USR_FE (0x40) +#define UART_USR_RB (0x80) + +/* Bit definitions and macros for UCSR */ +#define UART_UCSR_TCS(x) (((x)&0x0F)) +#define UART_UCSR_RCS(x) (((x)&0x0F)<<4) +#define UART_UCSR_RCS_SYS_CLK (0xD0) +#define UART_UCSR_RCS_CTM16 (0xE0) +#define UART_UCSR_RCS_CTM (0xF0) +#define UART_UCSR_TCS_SYS_CLK (0x0D) +#define UART_UCSR_TCS_CTM16 (0x0E) +#define UART_UCSR_TCS_CTM (0x0F) + +/* Bit definitions and macros for UCR */ +#define UART_UCR_RXC(x) (((x)&0x03)) +#define UART_UCR_TXC(x) (((x)&0x03)<<2) +#define UART_UCR_MISC(x) (((x)&0x07)<<4) +#define UART_UCR_NONE (0x00) +#define UART_UCR_STOP_BREAK (0x70) +#define UART_UCR_START_BREAK (0x60) +#define UART_UCR_BKCHGINT (0x50) +#define UART_UCR_RESET_ERROR (0x40) +#define UART_UCR_RESET_TX (0x30) +#define UART_UCR_RESET_RX (0x20) +#define UART_UCR_RESET_MR (0x10) +#define UART_UCR_TX_DISABLED (0x08) +#define UART_UCR_TX_ENABLED (0x04) +#define UART_UCR_RX_DISABLED (0x02) +#define UART_UCR_RX_ENABLED (0x01) + +/* Bit definitions and macros for UIPCR */ +#define UART_UIPCR_CTS (0x01) +#define UART_UIPCR_COS (0x10) + +/* Bit definitions and macros for UACR */ +#define UART_UACR_IEC (0x01) + +/* Bit definitions and macros for UIMR */ +#define UART_UIMR_TXRDY (0x01) +#define UART_UIMR_RXRDY_FU (0x02) +#define UART_UIMR_DB (0x04) +#define UART_UIMR_COS (0x80) + +/* Bit definitions and macros for UISR */ +#define UART_UISR_TXRDY (0x01) +#define UART_UISR_RXRDY_FU (0x02) +#define UART_UISR_DB (0x04) +#define UART_UISR_RXFTO (0x08) +#define UART_UISR_TXFIFO (0x10) +#define UART_UISR_RXFIFO (0x20) +#define UART_UISR_COS (0x80) + +/* Bit definitions and macros for UIP */ +#define UART_UIP_CTS (0x01) + +/* Bit definitions and macros for UOP1 */ +#define UART_UOP1_RTS (0x01) + +/* Bit definitions and macros for UOP0 */ +#define UART_UOP0_RTS (0x01) +#endif /* CONFIG_MCFUART */ + /****************************************************************************/ -#endif /* mcfuart_h */ +#endif /* mcfuart_h */ diff --git a/include/asm-m68k/ptrace.h b/include/asm-m68k/ptrace.h index 75b241883..01535beb1 100644 --- a/include/asm-m68k/ptrace.h +++ b/include/asm-m68k/ptrace.h @@ -28,32 +28,32 @@ #ifndef __ASSEMBLY__ struct pt_regs { - ulong d0; - ulong d1; - ulong d2; - ulong d3; - ulong d4; - ulong d5; - ulong d6; - ulong d7; - ulong a0; - ulong a1; - ulong a2; - ulong a3; - ulong a4; - ulong a5; - ulong a6; -#if defined(CONFIG_M5272) || defined(CONFIG_M5282) || defined(CONFIG_M5249) || defined(CONFIG_M5271) - unsigned format : 4; /* frame format specifier */ - unsigned vector : 12; /* vector offset */ + ulong d0; + ulong d1; + ulong d2; + ulong d3; + ulong d4; + ulong d5; + ulong d6; + ulong d7; + ulong a0; + ulong a1; + ulong a2; + ulong a3; + ulong a4; + ulong a5; + ulong a6; +#if defined(__M68K__) + unsigned format:4; /* frame format specifier */ + unsigned vector:12; /* vector offset */ unsigned short sr; - unsigned long pc; + unsigned long pc; #else unsigned short sr; - unsigned long pc; + unsigned long pc; #endif }; -#endif /* #ifndef __ASSEMBLY__ */ +#endif /* #ifndef __ASSEMBLY__ */ -#endif /* #ifndef _M68K_PTRACE_H */ +#endif /* #ifndef _M68K_PTRACE_H */ diff --git a/include/asm-m68k/u-boot.h b/include/asm-m68k/u-boot.h index 7a6a8c1ff..70dbda464 100644 --- a/include/asm-m68k/u-boot.h +++ b/include/asm-m68k/u-boot.h @@ -37,24 +37,36 @@ #ifndef __ASSEMBLY__ typedef struct bd_info { - unsigned long bi_memstart; /* start of DRAM memory */ - unsigned long bi_memsize; /* size of DRAM memory in bytes */ - unsigned long bi_flashstart; /* start of FLASH memory */ - unsigned long bi_flashsize; /* size of FLASH memory */ - unsigned long bi_flashoffset; /* reserved area for startup monitor */ - unsigned long bi_sramstart; /* start of SRAM memory */ - unsigned long bi_sramsize; /* size of SRAM memory */ - unsigned long bi_mbar_base; /* base of internal registers */ - unsigned long bi_bootflags; /* boot / reboot flag (for LynxOS) */ - unsigned long bi_boot_params; /* where this board expects params */ - unsigned long bi_ip_addr; /* IP Address */ - unsigned char bi_enetaddr[6]; /* Ethernet adress */ - unsigned short bi_ethspeed; /* Ethernet speed in Mbps */ - unsigned long bi_intfreq; /* Internal Freq, in MHz */ - unsigned long bi_busfreq; /* Bus Freq, in MHz */ - unsigned long bi_baudrate; /* Console Baudrate */ + unsigned long bi_memstart; /* start of DRAM memory */ + unsigned long bi_memsize; /* size of DRAM memory in bytes */ + unsigned long bi_flashstart; /* start of FLASH memory */ + unsigned long bi_flashsize; /* size of FLASH memory */ + unsigned long bi_flashoffset; /* reserved area for startup monitor */ + unsigned long bi_sramstart; /* start of SRAM memory */ + unsigned long bi_sramsize; /* size of SRAM memory */ + unsigned long bi_mbar_base; /* base of internal registers */ + unsigned long bi_bootflags; /* boot / reboot flag (for LynxOS) */ + unsigned long bi_boot_params; /* where this board expects params */ + unsigned long bi_ip_addr; /* IP Address */ + unsigned char bi_enetaddr[6]; /* Ethernet adress */ + unsigned short bi_ethspeed; /* Ethernet speed in Mbps */ + unsigned long bi_intfreq; /* Internal Freq, in MHz */ + unsigned long bi_busfreq; /* Bus Freq, in MHz */ + unsigned long bi_baudrate; /* Console Baudrate */ + +#ifdef CONFIG_HAS_ETH1 + /* second onboard ethernet port */ + unsigned char bi_enet1addr[6]; +#endif +#ifdef CONFIG_HAS_ETH2 + /* third onboard ethernet port */ + unsigned char bi_enet2addr[6]; +#endif +#ifdef CONFIG_HAS_ETH3 + unsigned char bi_enet3addr[6]; +#endif } bd_t; -#endif /* __ASSEMBLY__ */ +#endif /* __ASSEMBLY__ */ -#endif /* __U_BOOT_H__ */ +#endif /* __U_BOOT_H__ */ diff --git a/include/configs/M5329EVB.h b/include/configs/M5329EVB.h new file mode 100644 index 000000000..ac529dfbc --- /dev/null +++ b/include/configs/M5329EVB.h @@ -0,0 +1,275 @@ +/* + * Configuation settings for the Freescale MCF5329 FireEngine board. + * + * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef _M5329EVB_H +#define _M5329EVB_H + +/* + * High Level Configuration Options + * (easy to change) + */ +#define CONFIG_MCF532x /* define processor family */ +#define CONFIG_M5329 /* define processor type */ + +#undef DEBUG + +#define CONFIG_MCFSERIAL +#define CONFIG_BAUDRATE 115200 +#define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 } + +#undef CONFIG_WATCHDOG +#define CONFIG_WATCHDOG_TIMEOUT 5000 /* timeout in milliseconds, max timeout is 6.71sec */ + +#define CFG_NUM_IRQS 128 + +#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ + CFG_CMD_CACHE | \ + CFG_CMD_DATE | \ + CFG_CMD_ELF | \ + CFG_CMD_FLASH | \ + (CFG_CMD_LOADB | CFG_CMD_LOADS) | \ + CFG_CMD_MEMORY | \ + CFG_CMD_MISC | \ + CFG_CMD_MII | \ + CFG_CMD_NET | \ + CFG_CMD_PING | \ + CFG_CMD_REGINFO \ + ) + +#define CONFIG_MCFFEC +#ifdef CONFIG_MCFFEC +# define CONFIG_NET_MULTI 1 +# define CONFIG_MII 1 +# define CFG_DISCOVER_PHY +# define CFG_RX_ETH_BUFFER 8 +# define CFG_FAULT_ECHO_LINK_DOWN + +# define CFG_FEC0_IOBASE 0xFC030000 +# define CFG_FEC0_PINMUX 0 +# define CFG_FEC0_MIIBASE CFG_FEC0_IOBASE +# define MCFFEC_TOUT_LOOP 50000 +/* If CFG_DISCOVER_PHY is not defined - hardcoded */ +# ifndef CFG_DISCOVER_PHY +# define FECDUPLEX FULL +# define FECSPEED _100BASET +# else +# ifndef CFG_FAULT_ECHO_LINK_DOWN +# define CFG_FAULT_ECHO_LINK_DOWN +# endif +# endif /* CFG_DISCOVER_PHY */ +#endif + +#define CONFIG_MCFUART +#ifdef CONFIG_MCFUART +# define CFG_UART_PORT (0) +# define CFG_UART_BASE (0xFC060000) +#endif + +#define CONFIG_MCFRTC +#ifdef CONFIG_MCFRTC +# define CFG_MCFRTC_BASE (0xFC0A8000) +# undef RTC_DEBUG +#endif + +/* Timer */ +#define CONFIG_MCFTMR +#ifdef CONFIG_MCFTMR +# define CFG_UDELAY_BASE (0xFC070000) +# define CFG_TMR_BASE (0xFC074000) +# define CFG_TMRINTR_NO (33) +# define CFG_TMRINTR_MASK (2) +# define CFG_TMRINTR_PRI (6) +# define CFG_TIMER_PRESCALER (((CFG_CLK / 1000000) - 1) << 8) +#endif + +#undef CONFIG_MCFPIT +#ifdef CONFIG_MCFPIT +# define CFG_UDELAY_BASE (0xFC080000) +# define CFG_PIT_BASE (0xFC084000) +# define CFG_PIT_PRESCALE (6) +#endif + +#define CONFIG_MCFINTC +#ifdef CONFIG_MCFINTC +# define CFG_INTR_BASE (0xFC048000) +# define CFG_NUM_IRQ0 64 +# define CFG_NUM_IRQ1 64 +#endif + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include +#define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */ +#ifdef CONFIG_MCFFEC +# define CONFIG_ETHADDR 00:e0:0c:bc:e5:60 +# define CONFIG_IPADDR 192.162.1.2 +# define CONFIG_NETMASK 255.255.255.0 +# define CONFIG_SERVERIP 192.162.1.1 +# define CONFIG_GATEWAYIP 192.162.1.1 +# define CONFIG_OVERWRITE_ETHADDR_ONCE +#endif /* FEC_ENET */ + +#define CONFIG_HOSTNAME M5329EVB +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "loadaddr=40010000\0" \ + "u-boot=u-boot.bin\0" \ + "load=tftp ${loadaddr) ${u-boot}\0" \ + "upd=run load; run prog\0" \ + "prog=prot off 0 2ffff;" \ + "era 0 2ffff;" \ + "cp.b ${loadaddr} 0 ${filesize};" \ + "save\0" \ + "" + +#define CONFIG_PRAM 512 /* 512 KB */ +#define CFG_PROMPT "-> " +#define CFG_LONGHELP /* undef to save memory */ + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +# define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +# define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif + +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ +#define CFG_LOAD_ADDR 0x40010000 + +#define CFG_HZ 1000 +#define CFG_CLK 80000000 +#define CFG_CPU_CLK CFG_CLK * 3 + +#define CFG_MBAR 0xFC000000 + +/* + * Low Level Configuration Settings + * (address mappings, register initial values, etc.) + * You should know what you are doing if you make changes here. + */ +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area (in DPRAM) + */ +#define CFG_INIT_RAM_ADDR 0x80000000 +#define CFG_INIT_RAM_END 0x8000 /* End of used area in internal SRAM */ +#define CFG_INIT_RAM_CTRL 0x221 +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + */ +#define CFG_SDRAM_BASE 0x40000000 +#define CFG_SDRAM_SIZE 16 /* SDRAM size in MB */ +#define CFG_SDRAM_CFG1 0x53722730 +#define CFG_SDRAM_CFG2 0x56670000 +#define CFG_SDRAM_CTRL 0xE1092000 +#define CFG_SDRAM_EMOD 0x40010000 +#define CFG_SDRAM_MODE 0x018D0000 + +#define CFG_MEMTEST_START CFG_SDRAM_BASE + 0x400 +#define CFG_MEMTEST_END ((CFG_SDRAM_SIZE - 3) << 20) + +#define CFG_MONITOR_BASE (CFG_FLASH_BASE + 0x400) +#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ + +#define CFG_BOOTPARAMS_LEN 64*1024 +#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization ?? + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/*----------------------------------------------------------------------- + * FLASH organization + */ +#undef CFG_FLASH_CFI +#ifdef CFG_FLASH_CFI +# define CFG_FLASH_CFI_DRIVER 1 +# define CFG_FLASH_SIZE 0x800000 /* Max size that the board might have */ +# define CFG_FLASH_CFI_WIDTH FLASH_CFI_16BIT +#else +# define CFG_FLASH_UNLOCK_TOUT 1000 +# define CFG_FLASH_WRITE_TOUT 1000 +#endif + +#define CFG_FLASH_BASE 0 +#define CFG_FLASH0_BASE (CFG_CS0_BASE << 16) +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ +#define CFG_FLASH_ERASE_TOUT 1000 +#define CFG_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ + +/* Configuration for environment + * Environment is embedded in u-boot in the second sector of the flash + */ +#define CFG_ENV_OFFSET 0x4000 +#define CFG_ENV_SECT_SIZE 0x2000 +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_IS_EMBEDDED 1 + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_CACHELINE_SIZE 16 + +/*----------------------------------------------------------------------- + * Chipselect bank definitions + */ +/* + * CS0 - NOR Flash 1, 2, 4, or 8MB + * CS1 - CompactFlash and registers + * CS2 - NAND Flash 16, 32, or 64MB + * CS3 - Available + * CS4 - Available + * CS5 - Available + */ +#define CFG_CS0_BASE 0 +#define CFG_CS0_MASK 0x007f0001 +#define CFG_CS0_CTRL 0x00001fa0 + +#define CFG_CS1_BASE 0x1000 +#define CFG_CS1_MASK 0x001f0001 +#define CFG_CS1_CTRL 0x002A3780 + +#ifdef NANDFLASH_SIZE +#define CFG_CS2_BASE 0x00800000 +#define CFG_CS2_MASK 0x00ff0001 +#define CFG_CS2_CTRL 0x00001f60 +#endif + +#define CONFIG_UDP_CHECKSUM + +#endif /* _M5329EVB_H */ diff --git a/lib_m68k/Makefile b/lib_m68k/Makefile index 82165f098..03784fd84 100644 --- a/lib_m68k/Makefile +++ b/lib_m68k/Makefile @@ -27,7 +27,7 @@ LIB = $(obj)lib$(ARCH).a SOBJS = -COBJS = cache.o traps.o time.o board.o m68k_linux.o +COBJS = cache.o traps.o time.o interrupts.o board.o m68k_linux.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) diff --git a/lib_m68k/board.c b/lib_m68k/board.c index 6aaf60991..1b515a4c5 100644 --- a/lib_m68k/board.c +++ b/lib_m68k/board.c @@ -221,6 +221,7 @@ static int init_func_i2c (void) */ init_fnc_t *init_sequence[] = { + get_clocks, env_init, init_baudrate, serial_init, @@ -371,6 +372,10 @@ board_init_f (ulong bootflag) */ bd->bi_memstart = CFG_SDRAM_BASE; /* start of DRAM memory */ bd->bi_memsize = gd->ram_size; /* size of DRAM memory in bytes */ +#ifdef CFG_INIT_RAM_ADDR + bd->bi_sramstart = CFG_INIT_RAM_ADDR; /* start of SRAM memory */ + bd->bi_sramsize = CFG_INIT_RAM_END; /* size of SRAM memory */ +#endif bd->bi_mbar_base = CFG_MBAR; /* base of internal registers */ bd->bi_bootflags = bootflag; /* boot / reboot flag (for LynxOS) */ @@ -430,6 +435,10 @@ void board_init_r (gd_t *id, ulong dest_addr) gd->flags |= GD_FLG_RELOC; /* tell others: relocation done */ +#ifdef CONFIG_SERIAL_MULTI + serial_initialize(); +#endif + debug ("Now running in RAM - U-Boot at: %08lx\n", dest_addr); WATCHDOG_RESET (); @@ -489,7 +498,7 @@ void board_init_r (gd_t *id, ulong dest_addr) /* * Setup trap handlers */ - trap_init (0); + trap_init (CFG_SDRAM_BASE); #if !defined(CFG_NO_FLASH) puts ("FLASH: "); @@ -562,12 +571,48 @@ void board_init_r (gd_t *id, ulong dest_addr) if (s) s = (*e) ? e + 1 : e; } +#ifdef CONFIG_HAS_ETH1 + /* handle the 2nd ethernet address */ + + s = getenv ("eth1addr"); + for (i = 0; i < 6; ++i) { + bd->bi_enet1addr[i] = s ? simple_strtoul (s, &e, 16) : 0; + if (s) + s = (*e) ? e + 1 : e; + } +#endif +#ifdef CONFIG_HAS_ETH2 + /* handle the 3rd ethernet address */ + + s = getenv ("eth2addr"); + for (i = 0; i < 6; ++i) { + bd->bi_enet2addr[i] = s ? simple_strtoul (s, &e, 16) : 0; + if (s) + s = (*e) ? e + 1 : e; + } +#endif + +#ifdef CONFIG_HAS_ETH3 + /* handle 4th ethernet address */ + s = getenv("eth3addr"); + for (i = 0; i < 6; ++i) { + bd->bi_enet3addr[i] = s ? simple_strtoul (s, &e, 16) : 0; + if (s) + s = (*e) ? e + 1 : e; + } +#endif /* IP Address */ bd->bi_ip_addr = getenv_IPaddr ("ipaddr"); WATCHDOG_RESET (); +#if defined(CONFIG_PCI) + /* + * Do pci configuration + */ + pci_init (); +#endif /** leave this here (after malloc(), environment and PCI are working) **/ /* Initialize devices */ @@ -640,15 +685,33 @@ void board_init_r (gd_t *id, ulong dest_addr) nand_init(); /* go init the NAND */ #endif -#if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(FEC_ENET) +#if (CONFIG_COMMANDS & CFG_CMD_NET) WATCHDOG_RESET(); +#if defined(FEC_ENET) eth_init(bd); #endif +#if defined(CONFIG_NET_MULTI) + puts ("Net: "); + eth_initialize (bd); +#endif +#endif #ifdef CONFIG_POST post_run (NULL, POST_RAM | post_bootmode_get(0)); #endif +#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA) && !(CONFIG_COMMANDS & CFG_CMD_IDE) + WATCHDOG_RESET (); + puts ("PCMCIA:"); + pcmcia_init (); +#endif + +#if (CONFIG_COMMANDS & CFG_CMD_IDE) + WATCHDOG_RESET (); + puts ("IDE: "); + ide_init (); +#endif /* CFG_CMD_IDE */ + #ifdef CONFIG_LAST_STAGE_INIT WATCHDOG_RESET (); /* diff --git a/lib_m68k/interrupts.c b/lib_m68k/interrupts.c new file mode 100644 index 000000000..6b3ce8975 --- /dev/null +++ b/lib_m68k/interrupts.c @@ -0,0 +1,118 @@ +/* + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * (C) Copyright 2007 + * TsiChung Liew (Tsi-Chung.Liew@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +#ifdef CONFIG_MCFINTC +#define NR_IRQS (CFG_NUM_IRQS) + +/* + * Interrupt vector functions. + */ +struct interrupt_action { + interrupt_handler_t *handler; + void *arg; +}; + +static struct interrupt_action irq_vecs[NR_IRQS]; + +static __inline__ unsigned short get_sr (void) +{ + unsigned short sr; + + asm volatile ("move.w %%sr,%0":"=r" (sr):); + + return sr; +} + +static __inline__ void set_sr (unsigned short sr) +{ + asm volatile ("move.w %0,%%sr"::"r" (sr)); +} + +/************************************************************************/ +/* + * Install and free an interrupt handler + */ +void irq_install_handler (int vec, interrupt_handler_t * handler, void *arg) +{ + if ((vec < 0) || (vec > NR_IRQS)) { + printf ("irq_install_handler: wrong interrupt vector %d\n", + vec); + return; + } + + irq_vecs[vec].handler = handler; + irq_vecs[vec].arg = arg; +} + +void irq_free_handler (int vec) +{ + if ((vec < 0) || (vec > NR_IRQS)) { + return; + } + + irq_vecs[vec].handler = NULL; + irq_vecs[vec].arg = NULL; +} + +void enable_interrupts (void) +{ + unsigned short sr; + + sr = get_sr (); + set_sr (sr & ~0x0700); +} + +int disable_interrupts (void) +{ + unsigned short sr; + + sr = get_sr (); + set_sr (sr | 0x0700); + + return ((sr & 0x0700) == 0); /* return TRUE, if interrupts were enabled before */ +} + +void int_handler (struct pt_regs *fp) +{ + int vec; + + vec = (fp->vector >> 2) & 0xff; + if (vec > 0x40) + vec -= 0x40; + else + return; + + if (irq_vecs[vec].handler != NULL) { + irq_vecs[vec].handler (irq_vecs[vec].arg); + } else { + printf ("\nBogus External Interrupt Vector %d\n", vec); + } +} +#endif /* CONFIG_MCFINTC */ \ No newline at end of file diff --git a/lib_m68k/time.c b/lib_m68k/time.c index 12e38f057..0e4efa473 100644 --- a/lib_m68k/time.c +++ b/lib_m68k/time.c @@ -46,13 +46,11 @@ #include #endif - static ulong timestamp; #if defined(CONFIG_M5282) || defined(CONFIG_M5271) static unsigned short lastinc; #endif - #if defined(CONFIG_M5272) /* * We use timer 3 which is running with a period of 1 us @@ -293,6 +291,171 @@ void set_timer (ulong t) } #endif +#if defined(CONFIG_MCFTMR) +#ifndef CFG_UDELAY_BASE +# error "uDelay base not defined!" +#endif + +#if !defined(CFG_TMR_BASE) || !defined(CFG_INTR_BASE) || !defined(CFG_TMRINTR_NO) || !defined(CFG_TMRINTR_MASK) +# error "TMR_BASE, INTR_BASE, TMRINTR_NO or TMRINTR_MASk not defined!" +#endif + +#include + +extern void dtimer_interrupt(void *not_used); +extern void dtimer_interrupt_setup(void); +extern void dtimer_interrupt_enable(void); + +void udelay(unsigned long usec) +{ + volatile dtmr_t *timerp = (dtmr_t *) (CFG_UDELAY_BASE); + uint start, now, tmp; + + while (usec > 0) { + if (usec > 65000) + tmp = 65000; + else + tmp = usec; + usec = usec - tmp; + + /* Set up TIMER 3 as timebase clock */ + timerp->tmr = DTIM_DTMR_RST_RST; + timerp->tcn = 0; + /* set period to 1 us */ + timerp->tmr = + (((CFG_CLK / 1000000) - + 1) << 8) | DTIM_DTMR_CLK_DIV1 | DTIM_DTMR_FRR | DTIM_DTMR_RST_EN; + + start = now = timerp->tcn; + while (now < start + tmp) + now = timerp->tcn; + } +} + +void dtimer_interrupt(void *not_used) +{ + volatile dtmr_t *timerp = (dtmr_t *) (CFG_TMR_BASE); + volatile int0_t *intp = (int0_t *) (CFG_INTR_BASE); + + /* check for timer interrupt asserted */ + if ((intp->iprh0 & CFG_TMRINTR_MASK) == CFG_TMRINTR_MASK) { + timerp->ter = (DTIM_DTER_CAP | DTIM_DTER_REF); + timestamp++; + return; + } +} + +void timer_init(void) +{ + volatile dtmr_t *timerp = (dtmr_t *) (CFG_TMR_BASE); + volatile int0_t *intp = (int0_t *) (CFG_INTR_BASE); + + timestamp = 0; + + timerp->tcn = 0; + timerp->trr = 0; + + /* Set up TIMER 4 as clock */ + timerp->tmr = DTIM_DTMR_RST_RST; + + /* initialize and enable timer 4 interrupt */ + irq_install_handler(CFG_TMRINTR_NO, dtimer_interrupt, 0); + intp->icr0[CFG_TMRINTR_NO] = CFG_TMRINTR_PRI; + + timerp->tcn = 0; + timerp->trr = 1000; /* Interrupt every ms */ + + intp->imrh0 &= ~CFG_TMRINTR_MASK; + + /* set a period of 1us, set timer mode to restart and enable timer and interrupt */ + timerp->tmr = CFG_TIMER_PRESCALER | DTIM_DTMR_CLK_DIV1 | + DTIM_DTMR_FRR | DTIM_DTMR_ORRI | DTIM_DTMR_RST_EN; +} + +void reset_timer(void) +{ + timestamp = 0; +} + +ulong get_timer(ulong base) +{ + return (timestamp - base); +} + +void set_timer(ulong t) +{ + timestamp = t; +} +#endif /* CONFIG_MCFTMR */ + +#if defined(CONFIG_MCFPIT) +#if !defined(CFG_PIT_BASE) +# error "CFG_PIT_BASE not defined!" +#endif + +static unsigned short lastinc; + +void udelay(unsigned long usec) +{ + volatile pit_t *timerp = (pit_t *) (CFG_UDELAY_BASE); + uint tmp; + + while (usec > 0) { + if (usec > 65000) + tmp = 65000; + else + tmp = usec; + usec = usec - tmp; + + /* Set up TIMER 3 as timebase clock */ + timerp->pcsr = PIT_PCSR_OVW; + timerp->pmr = 0; + /* set period to 1 us */ + timerp->pcsr |= PIT_PCSR_PRE(CFG_PIT_PRESCALE) | PIT_PCSR_EN; + + timerp->pmr = tmp; + while (timerp->pcntr > 0) ; + } +} + +void timer_init(void) +{ + volatile pit_t *timerp = (pit_t *) (CFG_PIT_BASE); + timestamp = 0; + + /* Set up TIMER 4 as poll clock */ + timerp->pcsr = PIT_PCSR_OVW; + timerp->pmr = lastinc = 0; + timerp->pcsr |= PIT_PCSR_PRE(CFG_PIT_PRESCALE) | PIT_PCSR_EN; +} + +void set_timer(ulong t) +{ + volatile pit_t *timerp = (pit_t *) (CFG_PIT_BASE); + + timestamp = 0; + timerp->pmr = lastinc = 0; +} + +ulong get_timer(ulong base) +{ + unsigned short now, diff; + volatile pit_t *timerp = (pit_t *) (CFG_PIT_BASE); + + now = timerp->pcntr; + diff = -(now - lastinc); + + timestamp += diff; + lastinc = now; + return timestamp - base; +} + +void wait_ticks(unsigned long ticks) +{ + set_timer(0); + while (get_timer(0) < ticks) ; +} +#endif /* CONFIG_MCFPIT */ /* * This function is derived from PowerPC code (read timebase as long long). diff --git a/net/eth.c b/net/eth.c index 0fc22115d..cefd30ff2 100644 --- a/net/eth.c +++ b/net/eth.c @@ -58,6 +58,7 @@ extern int npe_initialize(bd_t *); extern int uec_initialize(int); extern int bfin_EMAC_initialize(bd_t *); extern int atstk1000_eth_initialize(bd_t *); +extern int mcffec_initialize(bd_t*); static struct eth_device *eth_devices, *eth_current; diff --git a/rtc/Makefile b/rtc/Makefile index 96c68c0ce..2e6f3bddd 100644 --- a/rtc/Makefile +++ b/rtc/Makefile @@ -31,7 +31,8 @@ COBJS = date.o \ bf5xx_rtc.o ds12887.o ds1302.o ds1306.o ds1307.o \ ds1337.o ds1374.o ds1556.o ds164x.o ds174x.o ds3231.o \ m41t11.o max6900.o m48t35ax.o mc146818.o mk48t59.o \ - mpc5xxx.o mpc8xx.o pcf8563.o s3c24x0_rtc.o rs5c372.o + mpc5xxx.o mpc8xx.o pcf8563.o s3c24x0_rtc.o rs5c372.o \ + mcfrtc.o SRCS := $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/rtc/mcfrtc.c b/rtc/mcfrtc.c new file mode 100644 index 000000000..c7eb53fb4 --- /dev/null +++ b/rtc/mcfrtc.c @@ -0,0 +1,120 @@ +/* + * (C) Copyright 2007 + * Freescale Semiconductor Tsi-Chung.Liew@freescale.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +#include + +#if defined(CONFIG_MCFRTC) && (CONFIG_COMMANDS & CFG_CMD_DATE) + +#undef RTC_DEBUG + +#ifndef CFG_MCFRTC_BASE +#error RTC_BASE is not defined! +#endif + +#define isleap(y) ((((y) % 4) == 0 && ((y) % 100) != 0) || ((y) % 400) == 0) +#define STARTOFTIME 1970 + +void rtc_get(struct rtc_time *tmp) +{ + volatile rtc_t *rtc = (rtc_t *) (CFG_MCFRTC_BASE); + + int rtc_days, rtc_hrs, rtc_mins; + int tim; + + rtc_days = rtc->days; + rtc_hrs = rtc->hourmin >> 8; + rtc_mins = RTC_HOURMIN_MINUTES(rtc->hourmin); + + tim = (rtc_days * 24) + rtc_hrs; + tim = (tim * 60) + rtc_mins; + tim = (tim * 60) + rtc->seconds; + + to_tm(tim, tmp); + + tmp->tm_yday = 0; + tmp->tm_isdst = 0; + +#ifdef RTC_DEBUG + printf("Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", + tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, + tmp->tm_hour, tmp->tm_min, tmp->tm_sec); +#endif +} + +void rtc_set(struct rtc_time *tmp) +{ + volatile rtc_t *rtc = (rtc_t *) (CFG_MCFRTC_BASE); + + static int month_days[12] = { + 31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31 + }; + int days, i, months; + + if (tmp->tm_year > 2037) { + printf("Unable to handle. Exceeding integer limitation!\n"); + tmp->tm_year = 2027; + } +#ifdef RTC_DEBUG + printf("Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", + tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, + tmp->tm_hour, tmp->tm_min, tmp->tm_sec); +#endif + + /* calculate days by years */ + for (i = STARTOFTIME, days = 0; i < tmp->tm_year; i++) { + days += 365 + isleap(i); + } + + /* calculate days by months */ + months = tmp->tm_mon - 1; + for (i = 0; i < months; i++) { + days += month_days[i]; + + if (i == 1) + days += isleap(i); + } + + days += tmp->tm_mday - 1; + + rtc->days = days; + rtc->hourmin = (tmp->tm_hour << 8) | tmp->tm_min; + rtc->seconds = tmp->tm_sec; +} + +void rtc_reset(void) +{ + volatile rtc_t *rtc = (rtc_t *) (CFG_MCFRTC_BASE); + + if ((rtc->cr & RTC_CR_EN) == 0) { + printf("real-time-clock was stopped. Now starting...\n"); + rtc->cr |= RTC_CR_EN; + } + + rtc->cr |= RTC_CR_SWR; +} + +#endif /* CONFIG_MCFRTC && CFG_CMD_DATE */ From d677b32855f577ae2690dcd64a172cdd706e0ffc Mon Sep 17 00:00:00 2001 From: Mike Frysinger Date: Fri, 22 Jun 2007 10:34:12 +0200 Subject: [PATCH 004/259] [patch] add nand_init() prototype to nand.h since nand_init() is expected to be called by other parts of u-boot, there should be a prototype for it in nand.h Signed-off-by: Mike Frysinger Signed-off-by: Stefan Roese --- include/nand.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/nand.h b/include/nand.h index 23493f7e9..3c0752ea1 100644 --- a/include/nand.h +++ b/include/nand.h @@ -32,6 +32,7 @@ typedef struct mtd_info nand_info_t; extern int nand_curr_device; extern nand_info_t nand_info[]; +extern void nand_init(void); static inline int nand_read(nand_info_t *info, ulong ofs, ulong *len, u_char *buf) { From 5d187430a055d62f17ca84d75e7245439d1f7e75 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Fri, 6 Jul 2007 11:48:24 +0200 Subject: [PATCH 005/259] ppc4xx: Update lwmon5 board Add unlock=yes environment variable to default variables to unlock the CFI flash by default. Signed-off-by: Stefan Roese --- include/configs/lwmon5.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/configs/lwmon5.h b/include/configs/lwmon5.h index 1d87c73c7..01adef1d6 100644 --- a/include/configs/lwmon5.h +++ b/include/configs/lwmon5.h @@ -162,6 +162,7 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ "hostname=lwmon5\0" \ "netdev=eth0\0" \ + "unlock=yes\0" \ "nfsargs=setenv bootargs root=/dev/nfs rw " \ "nfsroot=${serverip}:${rootpath}\0" \ "ramargs=setenv bootargs root=/dev/ram rw\0" \ From 334043f601a90ac53e5ecc846fbb73a1ef38cb1f Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Fri, 6 Jul 2007 12:26:51 +0200 Subject: [PATCH 006/259] ppc4xx: Update lwmon5 default environment Signed-off-by: Stefan Roese --- include/configs/lwmon5.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/configs/lwmon5.h b/include/configs/lwmon5.h index 01adef1d6..c4b7c4ee5 100644 --- a/include/configs/lwmon5.h +++ b/include/configs/lwmon5.h @@ -184,6 +184,8 @@ "update=protect off FFF80000 FFFFFFFF;era FFF80000 FFFFFFFF;" \ "cp.b 200000 FFF80000 80000\0" \ "upd=run load;run update\0" \ + "lwe_env=tftp 200000 /tftpboot.dev/lwmon5/env_uboot.bin;" \ + "autoscr 200000\0" \ "" #define CONFIG_BOOTCOMMAND "run flash_self" From 10e038932f22ee80ebd53de312531e70e6590a2f Mon Sep 17 00:00:00 2001 From: Thomas Knobloch Date: Fri, 6 Jul 2007 14:58:39 +0200 Subject: [PATCH 007/259] [NAND] Bad block skipping for command nboot The old implementation of command nboot does not support reading the image from NAND flash with skipping of bad blocks. The patch implements a new version of the nboot command: by calling nboot.jffs2 from the u-boot command line the command will load the image from NAND flash with respect to bad blocks (by using nand_read_opts()). This is similar to e.g. the NAND read command: "nand read.jffs2 ...". Signed-off-by: Thomas Knobloch Signed-off-by: Stefan Roese --- common/cmd_nand.c | 37 ++++++++++++++++++++++++++++++++----- 1 file changed, 32 insertions(+), 5 deletions(-) diff --git a/common/cmd_nand.c b/common/cmd_nand.c index b011b5e3d..9ef31d456 100644 --- a/common/cmd_nand.c +++ b/common/cmd_nand.c @@ -476,14 +476,31 @@ static int nand_load_image(cmd_tbl_t *cmdtp, nand_info_t *nand, ulong offset, ulong addr, char *cmd) { int r; - char *ep; + char *ep, *s; ulong cnt; image_header_t *hdr; + int jffs2 = 0; + + s = strchr(cmd, '.'); + if (s != NULL && + (!strcmp(s, ".jffs2") || !strcmp(s, ".e") || !strcmp(s, ".i"))) + jffs2 = 1; printf("\nLoading from %s, offset 0x%lx\n", nand->name, offset); cnt = nand->oobblock; - r = nand_read(nand, offset, &cnt, (u_char *) addr); + if (jffs2) { + nand_read_options_t opts; + memset(&opts, 0, sizeof(opts)); + opts.buffer = (u_char*) addr; + opts.length = cnt; + opts.offset = offset; + opts.quiet = 1; + r = nand_read_opts(nand, &opts); + } else { + r = nand_read(nand, offset, &cnt, (u_char *) addr); + } + if (r) { puts("** Read error\n"); SHOW_BOOT_PROGRESS(-1); @@ -501,8 +518,18 @@ static int nand_load_image(cmd_tbl_t *cmdtp, nand_info_t *nand, print_image_hdr(hdr); cnt = (ntohl(hdr->ih_size) + sizeof (image_header_t)); + if (jffs2) { + nand_read_options_t opts; + memset(&opts, 0, sizeof(opts)); + opts.buffer = (u_char*) addr; + opts.length = cnt; + opts.offset = offset; + opts.quiet = 1; + r = nand_read_opts(nand, &opts); + } else { + r = nand_read(nand, offset, &cnt, (u_char *) addr); + } - r = nand_read(nand, offset, &cnt, (u_char *) addr); if (r) { puts("** Read error\n"); SHOW_BOOT_PROGRESS(-1); @@ -550,7 +577,7 @@ int do_nandboot(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) if (argc > 3) goto usage; if (argc == 3) - addr = simple_strtoul(argv[2], NULL, 16); + addr = simple_strtoul(argv[1], NULL, 16); else addr = CFG_LOAD_ADDR; return nand_load_image(cmdtp, &nand_info[dev->id->num], @@ -605,7 +632,7 @@ usage: U_BOOT_CMD(nboot, 4, 1, do_nandboot, "nboot - boot from NAND device\n", - "[partition] | [[[loadAddr] dev] offset]\n"); + "[.jffs2] [partition] | [[[loadAddr] dev] offset]\n"); #endif /* (CONFIG_COMMANDS & CFG_CMD_NAND) */ From e09f7ab5749c345f924da272bea0521a73af5b11 Mon Sep 17 00:00:00 2001 From: Matthias Fuchs Date: Mon, 9 Jul 2007 10:10:04 +0200 Subject: [PATCH 008/259] Migrate esd 405EP boards to new NAND subsystem This patch prepares the migration from the legacy NAND driver to U-Boot's new NAND subsystem for esd boards. Signed-off-by: Matthias Fuchs --- board/esd/common/auto_update.c | 4 ++ board/esd/common/esd405ep_nand.c | 87 ++++++++++++++++++++++++++++++++ 2 files changed, 91 insertions(+) create mode 100644 board/esd/common/esd405ep_nand.c diff --git a/board/esd/common/auto_update.c b/board/esd/common/auto_update.c index 001fd68da..b5f772202 100644 --- a/board/esd/common/auto_update.c +++ b/board/esd/common/auto_update.c @@ -31,7 +31,9 @@ #include #include #include +#if defined(CFG_NAND_LEGACY) #include +#endif #include #include @@ -294,6 +296,8 @@ int au_do_update(int i, long sz) rc = nand_legacy_rw(nand_dev_desc, NANDRW_WRITE | NANDRW_JFFS2, start, nbytes, (size_t *)&total, (uchar *)addr); debug ("nand_legacy_rw: ret=%x total=%d nbytes=%d\n", rc, total, nbytes); +#else + rc = -1; #endif } if (rc != 0) { diff --git a/board/esd/common/esd405ep_nand.c b/board/esd/common/esd405ep_nand.c new file mode 100644 index 000000000..7ac4b835a --- /dev/null +++ b/board/esd/common/esd405ep_nand.c @@ -0,0 +1,87 @@ +/* + * (C) Copyright 2007 + * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +#if (CONFIG_COMMANDS & CFG_CMD_NAND) +#include +#include + +/* + * hardware specific access to control-lines + */ +static void esd405ep_nand_hwcontrol(struct mtd_info *mtdinfo, int cmd) +{ + switch(cmd) { + case NAND_CTL_SETCLE: + out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CFG_NAND_CLE); + break; + case NAND_CTL_CLRCLE: + out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CFG_NAND_CLE); + break; + case NAND_CTL_SETALE: + out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CFG_NAND_ALE); + break; + case NAND_CTL_CLRALE: + out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CFG_NAND_ALE); + break; + case NAND_CTL_SETNCE: + out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CFG_NAND_CE); + break; + case NAND_CTL_CLRNCE: + out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CFG_NAND_CE); + break; + } +} + + +/* + * read device ready pin + */ +static int esd405ep_nand_device_ready(struct mtd_info *mtdinfo) +{ + if (in_be32((void *)GPIO0_IR) & CFG_NAND_RDY) + return 1; + return 0; +} + + +int board_nand_init(struct nand_chip *nand) +{ + /* + * Set NAND-FLASH GPIO signals to defaults + */ + out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~(CFG_NAND_CLE | CFG_NAND_ALE)); + out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CFG_NAND_CE); + + /* + * Initialize nand_chip structure + */ + nand->hwcontrol = esd405ep_nand_hwcontrol; + nand->dev_ready = esd405ep_nand_device_ready; + nand->eccmode = NAND_ECC_SOFT; + nand->chip_delay = NAND_BIG_DELAY_US; + nand->options = NAND_SAMSUNG_LP_OPTIONS; + return 0; +} +#endif /* (CONFIG_COMMANDS & CFG_CMD_NAND) */ From bd84ee4c2020c3a6861f4bb2e7ea0fb49f82e803 Mon Sep 17 00:00:00 2001 From: Matthias Fuchs Date: Mon, 9 Jul 2007 10:10:06 +0200 Subject: [PATCH 009/259] Migrate esd 405EP boards to new NAND subsystem Migrate esd 405EP boards to new NAND subsystem -cleanup -use correct io accessors (in/out_be32()) Signed-off-by: Matthias Fuchs --- board/esd/ash405/Makefile | 4 ++- board/esd/ash405/ash405.c | 43 ++++++++--------------------- board/esd/cms700/Makefile | 5 +++- board/esd/cms700/cms700.c | 39 ++++++--------------------- board/esd/hh405/Makefile | 5 +++- board/esd/hh405/hh405.c | 22 +-------------- board/esd/hub405/Makefile | 4 ++- board/esd/hub405/hub405.c | 34 ----------------------- board/esd/plu405/Makefile | 5 +++- board/esd/plu405/plu405.c | 56 +++++++------------------------------- board/esd/voh405/Makefile | 4 ++- board/esd/voh405/voh405.c | 20 -------------- board/esd/wuh405/Makefile | 4 ++- board/esd/wuh405/wuh405.c | 33 ----------------------- include/configs/ASH405.h | 43 +++++++++-------------------- include/configs/CMS700.h | 37 ++++++------------------- include/configs/HH405.h | 37 ++++++------------------- include/configs/HUB405.h | 37 ++++++------------------- include/configs/PLU405.h | 57 +++++++-------------------------------- include/configs/VOH405.h | 37 ++++++------------------- include/configs/WUH405.h | 38 ++++++-------------------- 21 files changed, 114 insertions(+), 450 deletions(-) diff --git a/board/esd/ash405/Makefile b/board/esd/ash405/Makefile index 4d75868ea..308f752d0 100644 --- a/board/esd/ash405/Makefile +++ b/board/esd/ash405/Makefile @@ -28,7 +28,9 @@ endif LIB = $(obj)lib$(BOARD).a -COBJS = $(BOARD).o flash.o ../common/misc.o +COBJS = $(BOARD).o flash.o \ + ../common/misc.o \ + ../common/esd405ep_nand.o \ SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/board/esd/ash405/ash405.c b/board/esd/ash405/ash405.c index 84fc3a01d..0151d740c 100644 --- a/board/esd/ash405/ash405.c +++ b/board/esd/ash405/ash405.c @@ -23,6 +23,7 @@ #include #include +#include #include #include @@ -33,6 +34,7 @@ #endif extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); +extern void lxt971_no_sleep(void); /* fpga configuration data - gzip compressed and generated by bin2c */ const unsigned char fpgadata[] = @@ -164,17 +166,11 @@ int misc_init_r (void) /* * Reset external DUARTs */ - out32(GPIO0_OR, in32(GPIO0_OR) | CFG_DUART_RST); /* set reset to high */ + out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CFG_DUART_RST); udelay(10); /* wait 10us */ - out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_DUART_RST); /* set reset to low */ + out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CFG_DUART_RST); udelay(1000); /* wait 1ms */ - /* - * Set NAND-FLASH GPIO signals to default - */ - out32(GPIO0_OR, in32(GPIO0_OR) & ~(CFG_NAND_CLE | CFG_NAND_ALE)); - out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE); - /* * Enable interrupts in exar duart mcr[3] */ @@ -218,35 +214,18 @@ long int initdram (int board_type) mtdcr(memcfga, mem_mb0cf); val = mfdcr(memcfgd); -#if 0 - printf("\nmb0cf=%x\n", val); /* test-only */ - printf("strap=%x\n", mfdcr(strap)); /* test-only */ -#endif - return (4*1024*1024 << ((val & 0x000e0000) >> 17)); } /* ------------------------------------------------------------------------- */ -int testdram (void) +void reset_phy(void) { - /* TODO: XXX XXX XXX */ - printf ("test: 16 MB - ok\n"); +#ifdef CONFIG_LXT971_NO_SLEEP - return (0); -} - -/* ------------------------------------------------------------------------- */ - -#if (CONFIG_COMMANDS & CFG_CMD_NAND) -#include -extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE]; - -void nand_init(void) -{ - nand_probe(CFG_NAND_BASE); - if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) { - print_size(nand_dev_desc[0].totlen, "\n"); - } -} + /* + * Disable sleep mode in LXT971 + */ + lxt971_no_sleep(); #endif +} diff --git a/board/esd/cms700/Makefile b/board/esd/cms700/Makefile index df487662f..0d4ab2d13 100644 --- a/board/esd/cms700/Makefile +++ b/board/esd/cms700/Makefile @@ -33,7 +33,10 @@ CPLD = ../common/xilinx_jtag/lenval.o \ ../common/xilinx_jtag/micro.o \ ../common/xilinx_jtag/ports.o -COBJS = $(BOARD).o flash.o ../common/misc.o $(CPLD) +COBJS = $(BOARD).o flash.o \ + ../common/misc.o \ + $(CPLD) \ + ../common/esd405ep_nand.o \ SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/board/esd/cms700/cms700.c b/board/esd/cms700/cms700.c index cb0471073..2cdd7be36 100644 --- a/board/esd/cms700/cms700.c +++ b/board/esd/cms700/cms700.c @@ -1,5 +1,5 @@ /* - * (C) Copyright 2005 + * (C) Copyright 2005-2007 * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com * * See file CREDITS for list of people who contributed to this @@ -23,6 +23,7 @@ #include #include +#include #include #include @@ -68,9 +69,9 @@ int board_early_init_f (void) /* * Reset CPLD via GPIO12 (CS3) pin */ - out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_PLD_RESET); + out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CFG_PLD_RESET); udelay(1000); /* wait 1ms */ - out32(GPIO0_OR, in32(GPIO0_OR) | CFG_PLD_RESET); + out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CFG_PLD_RESET); udelay(1000); /* wait 1ms */ return 0; @@ -94,13 +95,7 @@ int misc_init_r (void) /* * Setup and enable EEPROM write protection */ - out32(GPIO0_OR, in32(GPIO0_OR) | CFG_EEPROM_WP); - - /* - * Set NAND-FLASH GPIO signals to default - */ - out32(GPIO0_OR, in32(GPIO0_OR) & ~(CFG_NAND_CLE | CFG_NAND_ALE)); - out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE); + out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CFG_EEPROM_WP); return (0); } @@ -153,11 +148,6 @@ long int initdram (int board_type) mtdcr(memcfga, mem_mb0cf); val = mfdcr(memcfgd); -#if 0 - printf("\nmb0cf=%x\n", val); /* test-only */ - printf("strap=%x\n", mfdcr(strap)); /* test-only */ -#endif - return (4*1024*1024 << ((val & 0x000e0000) >> 17)); } @@ -180,17 +170,17 @@ int eeprom_write_enable (unsigned dev_addr, int state) switch (state) { case 1: /* Enable write access, clear bit GPIO_SINT2. */ - out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_EEPROM_WP); + out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CFG_EEPROM_WP); state = 0; break; case 0: /* Disable write access, set bit GPIO_SINT2. */ - out32(GPIO0_OR, in32(GPIO0_OR) | CFG_EEPROM_WP); + out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CFG_EEPROM_WP); state = 0; break; default: /* Read current status back. */ - state = (0 == (in32(GPIO0_OR) & CFG_EEPROM_WP)); + state = (0 == (in_be32((void *)GPIO0_OR) & CFG_EEPROM_WP)); break; } } @@ -235,19 +225,6 @@ U_BOOT_CMD(eepwren, 2, 0, do_eep_wren, /* ------------------------------------------------------------------------- */ -#if (CONFIG_COMMANDS & CFG_CMD_NAND) -#include -extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE]; - -void nand_init(void) -{ - nand_probe(CFG_NAND_BASE); - if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) { - print_size(nand_dev_desc[0].totlen, "\n"); - } -} -#endif - void reset_phy(void) { #ifdef CONFIG_LXT971_NO_SLEEP diff --git a/board/esd/hh405/Makefile b/board/esd/hh405/Makefile index ce7876c41..0e5e57a5a 100644 --- a/board/esd/hh405/Makefile +++ b/board/esd/hh405/Makefile @@ -28,7 +28,10 @@ endif LIB = $(obj)lib$(BOARD).a -COBJS = $(BOARD).o flash.o ../common/misc.o ../common/auto_update.o +COBJS = $(BOARD).o flash.o \ + ../common/misc.o \ + ../common/esd405ep_nand.o \ + ../common/auto_update.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/board/esd/hh405/hh405.c b/board/esd/hh405/hh405.c index ea344c0f2..67b5d5406 100644 --- a/board/esd/hh405/hh405.c +++ b/board/esd/hh405/hh405.c @@ -5,7 +5,7 @@ * (C) Copyright 2005 * Stefan Roese, DENX Software Engineering, sr@denx.de. * - * (C) Copyright 2006 + * (C) Copyright 2006-2007 * Matthias Fuchs, esd GmbH, matthias.fuchs@esd-electronics.com * * See file CREDITS for list of people who contributed to this @@ -476,12 +476,6 @@ int misc_init_r (void) */ out32(GPIO0_OR, in32(GPIO0_OR) | CFG_EEPROM_WP); - /* - * Set NAND-FLASH GPIO signals to default - */ - out32(GPIO0_OR, in32(GPIO0_OR) & ~(CFG_NAND_CLE | CFG_NAND_ALE)); - out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE); - /* * Reset touch-screen controller */ @@ -690,20 +684,6 @@ void ide_set_reset(int on) #endif /* CONFIG_IDE_RESET */ -#if (CONFIG_COMMANDS & CFG_CMD_NAND) -#include -extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE]; - -void nand_init(void) -{ - nand_probe(CFG_NAND_BASE); - if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) { - print_size(nand_dev_desc[0].totlen, "\n"); - } -} -#endif - - #if defined(CFG_EEPROM_WREN) /* Input: I2C address of EEPROM device to enable. * -1: deliver current state diff --git a/board/esd/hub405/Makefile b/board/esd/hub405/Makefile index 4d75868ea..308f752d0 100644 --- a/board/esd/hub405/Makefile +++ b/board/esd/hub405/Makefile @@ -28,7 +28,9 @@ endif LIB = $(obj)lib$(BOARD).a -COBJS = $(BOARD).o flash.o ../common/misc.o +COBJS = $(BOARD).o flash.o \ + ../common/misc.o \ + ../common/esd405ep_nand.o \ SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/board/esd/hub405/hub405.c b/board/esd/hub405/hub405.c index 1e0accbe0..25c8068fd 100644 --- a/board/esd/hub405/hub405.c +++ b/board/esd/hub405/hub405.c @@ -152,12 +152,6 @@ int misc_init_r (void) out32(GPIO0_OR, val); - /* - * Set NAND-FLASH GPIO signals to default - */ - out32(GPIO0_OR, in32(GPIO0_OR) & ~(CFG_NAND_CLE | CFG_NAND_ALE)); - out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE); - /* * check board type and setup AP power */ @@ -242,33 +236,5 @@ long int initdram (int board_type) mtdcr(memcfga, mem_mb0cf); val = mfdcr(memcfgd); -#if 0 - printf("\nmb0cf=%x\n", val); /* test-only */ - printf("strap=%x\n", mfdcr(strap)); /* test-only */ -#endif - return (4*1024*1024 << ((val & 0x000e0000) >> 17)); } - - -int testdram (void) -{ - /* TODO: XXX XXX XXX */ - printf ("test: 16 MB - ok\n"); - - return (0); -} - - -#if (CONFIG_COMMANDS & CFG_CMD_NAND) -#include -extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE]; - -void nand_init(void) -{ - nand_probe(CFG_NAND_BASE); - if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) { - print_size(nand_dev_desc[0].totlen, "\n"); - } -} -#endif diff --git a/board/esd/plu405/Makefile b/board/esd/plu405/Makefile index ce7876c41..0e5e57a5a 100644 --- a/board/esd/plu405/Makefile +++ b/board/esd/plu405/Makefile @@ -28,7 +28,10 @@ endif LIB = $(obj)lib$(BOARD).a -COBJS = $(BOARD).o flash.o ../common/misc.o ../common/auto_update.o +COBJS = $(BOARD).o flash.o \ + ../common/misc.o \ + ../common/esd405ep_nand.o \ + ../common/auto_update.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/board/esd/plu405/plu405.c b/board/esd/plu405/plu405.c index 59171f8f4..f026a7ac3 100644 --- a/board/esd/plu405/plu405.c +++ b/board/esd/plu405/plu405.c @@ -23,6 +23,7 @@ #include #include +#include #include #include @@ -31,6 +32,8 @@ #define FPGA_DEBUG #endif +DECLARE_GLOBAL_DATA_PTR; + extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); extern void lxt971_no_sleep(void); @@ -114,6 +117,10 @@ int misc_init_r (void) int index; int i; + /* adjust flash start and offset */ + gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize; + gd->bd->bi_flashoffset = 0; + dst = malloc(CFG_FPGA_MAX_SIZE); if (gunzip (dst, CFG_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) { printf ("GUNZIP ERROR - must RESET board to recover\n"); @@ -177,17 +184,11 @@ int misc_init_r (void) /* * Reset external DUARTs */ - out32(GPIO0_OR, in32(GPIO0_OR) | CFG_DUART_RST); /* set reset to high */ + out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CFG_DUART_RST); udelay(10); /* wait 10us */ - out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_DUART_RST); /* set reset to low */ + out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CFG_DUART_RST); udelay(1000); /* wait 1ms */ - /* - * Set NAND-FLASH GPIO signals to default - */ - out32(GPIO0_OR, in32(GPIO0_OR) & ~(CFG_NAND_CLE | CFG_NAND_ALE)); - out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE); - /* * Enable interrupts in exar duart mcr[3] */ @@ -226,24 +227,10 @@ long int initdram (int board_type) mtdcr(memcfga, mem_mb0cf); val = mfdcr(memcfgd); -#if 0 - printf("\nmb0cf=%x\n", val); /* test-only */ - printf("strap=%x\n", mfdcr(strap)); /* test-only */ -#endif - return (4*1024*1024 << ((val & 0x000e0000) >> 17)); } -int testdram (void) -{ - /* TODO: XXX XXX XXX */ - printf ("test: 16 MB - ok\n"); - - return (0); -} - - #ifdef CONFIG_IDE_RESET void ide_set_reset(int on) { @@ -262,31 +249,6 @@ void ide_set_reset(int on) #endif /* CONFIG_IDE_RESET */ -#if (CONFIG_COMMANDS & CFG_CMD_NAND) -#include -extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE]; - -void nand_init(void) -{ - nand_probe(CFG_NAND_BASE); - if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) { - print_size(nand_dev_desc[0].totlen, "\n"); - } -} -#endif - - -#ifdef CONFIG_AUTO_UPDATE_SHOW -void board_auto_update_show(int au_active) -{ - if (au_active) { - printf("\n Dies ist die board-funktion: Updating!!!\n"); - } else { - printf("\n Dies ist die board-funktion: Updating done!!!\n"); - } -} -#endif - void reset_phy(void) { #ifdef CONFIG_LXT971_NO_SLEEP diff --git a/board/esd/voh405/Makefile b/board/esd/voh405/Makefile index 4d75868ea..308f752d0 100644 --- a/board/esd/voh405/Makefile +++ b/board/esd/voh405/Makefile @@ -28,7 +28,9 @@ endif LIB = $(obj)lib$(BOARD).a -COBJS = $(BOARD).o flash.o ../common/misc.o +COBJS = $(BOARD).o flash.o \ + ../common/misc.o \ + ../common/esd405ep_nand.o \ SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/board/esd/voh405/voh405.c b/board/esd/voh405/voh405.c index 22995b502..2857a0bef 100644 --- a/board/esd/voh405/voh405.c +++ b/board/esd/voh405/voh405.c @@ -194,12 +194,6 @@ int misc_init_r (void) out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_DUART_RST); /* set reset to low */ udelay(1000); /* wait 1ms */ - /* - * Set NAND-FLASH GPIO signals to default - */ - out32(GPIO0_OR, in32(GPIO0_OR) & ~(CFG_NAND_CLE | CFG_NAND_ALE)); - out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE); - /* * Enable interrupts in exar duart mcr[3] */ @@ -340,17 +334,3 @@ void ide_set_reset(int on) } } #endif /* CONFIG_IDE_RESET */ - - -#if (CONFIG_COMMANDS & CFG_CMD_NAND) -#include -extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE]; - -void nand_init(void) -{ - nand_probe(CFG_NAND_BASE); - if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) { - print_size(nand_dev_desc[0].totlen, "\n"); - } -} -#endif diff --git a/board/esd/wuh405/Makefile b/board/esd/wuh405/Makefile index 4d75868ea..308f752d0 100644 --- a/board/esd/wuh405/Makefile +++ b/board/esd/wuh405/Makefile @@ -28,7 +28,9 @@ endif LIB = $(obj)lib$(BOARD).a -COBJS = $(BOARD).o flash.o ../common/misc.o +COBJS = $(BOARD).o flash.o \ + ../common/misc.o \ + ../common/esd405ep_nand.o \ SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/board/esd/wuh405/wuh405.c b/board/esd/wuh405/wuh405.c index 5a1a3f3e8..0b5306235 100644 --- a/board/esd/wuh405/wuh405.c +++ b/board/esd/wuh405/wuh405.c @@ -169,12 +169,6 @@ int misc_init_r (void) out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_DUART_RST); /* set reset to low */ udelay(1000); /* wait 1ms */ - /* - * Set NAND-FLASH GPIO signals to default - */ - out32(GPIO0_OR, in32(GPIO0_OR) & ~(CFG_NAND_CLE | CFG_NAND_ALE)); - out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE); - /* * Enable interrupts in exar duart mcr[3] */ @@ -218,35 +212,8 @@ long int initdram (int board_type) mtdcr(memcfga, mem_mb0cf); val = mfdcr(memcfgd); -#if 0 - printf("\nmb0cf=%x\n", val); /* test-only */ - printf("strap=%x\n", mfdcr(strap)); /* test-only */ -#endif - return (4*1024*1024 << ((val & 0x000e0000) >> 17)); } /* ------------------------------------------------------------------------- */ -int testdram (void) -{ - /* TODO: XXX XXX XXX */ - printf ("test: 16 MB - ok\n"); - - return (0); -} - -/* ------------------------------------------------------------------------- */ - -#if (CONFIG_COMMANDS & CFG_CMD_NAND) -#include -extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE]; - -void nand_init(void) -{ - nand_probe(CFG_NAND_BASE); - if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) { - print_size(nand_dev_desc[0].totlen, "\n"); - } -} -#endif diff --git a/include/configs/ASH405.h b/include/configs/ASH405.h index d03c05bf3..584f49068 100644 --- a/include/configs/ASH405.h +++ b/include/configs/ASH405.h @@ -53,9 +53,13 @@ #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ +#define CONFIG_NET_MULTI 1 +#undef CONFIG_HAS_ETH1 + #define CONFIG_MII 1 /* MII PHY management */ #define CONFIG_PHY_ADDR 0 /* PHY address */ #define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */ +#define CONFIG_RESET_PHY_R 1 /* use reset_phy() to disable phy sleep mode */ #define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/ @@ -132,39 +136,16 @@ * NAND-FLASH stuff *----------------------------------------------------------------------- */ +#define CFG_NAND_BASE_LIST { CFG_NAND_BASE } +#define NAND_MAX_CHIPS 1 +#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ +#define NAND_BIG_DELAY_US 25 -#define CFG_NAND_LEGACY +#define CFG_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */ +#define CFG_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */ +#define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */ +#define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */ -#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ -#define SECTORSIZE 512 - -#define ADDR_COLUMN 1 -#define ADDR_PAGE 2 -#define ADDR_COLUMN_PAGE 3 - -#define NAND_ChipID_UNKNOWN 0x00 -#define NAND_MAX_FLOORS 1 -#define NAND_MAX_CHIPS 1 - -#define CFG_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */ -#define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */ -#define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */ -#define CFG_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */ - -#define NAND_DISABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);} while(0) -#define NAND_ENABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CE);} while(0) -#define NAND_CTL_CLRALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_ALE);} while(0) -#define NAND_CTL_SETALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_ALE);} while(0) -#define NAND_CTL_CLRCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CLE);} while(0) -#define NAND_CTL_SETCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CLE);} while(0) -#define NAND_WAIT_READY(nand) while (!(in32(GPIO0_IR) & CFG_NAND_RDY)) - -#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0) -#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0) -#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0) -#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr)) - -#define CONFIG_MTD_NAND_VERIFY_WRITE 1 /* verify all writes!!! */ #define CFG_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */ /*----------------------------------------------------------------------- diff --git a/include/configs/CMS700.h b/include/configs/CMS700.h index 1cca2859f..96952118c 100644 --- a/include/configs/CMS700.h +++ b/include/configs/CMS700.h @@ -81,8 +81,6 @@ /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ #include -#define CFG_NAND_LEGACY - #undef CONFIG_WATCHDOG /* watchdog disabled */ #define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ @@ -148,34 +146,15 @@ * NAND-FLASH stuff *----------------------------------------------------------------------- */ -#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ -#define SECTORSIZE 512 +#define CFG_NAND_BASE_LIST { CFG_NAND_BASE } +#define NAND_MAX_CHIPS 1 +#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ +#define NAND_BIG_DELAY_US 25 -#define ADDR_COLUMN 1 -#define ADDR_PAGE 2 -#define ADDR_COLUMN_PAGE 3 - -#define NAND_ChipID_UNKNOWN 0x00 -#define NAND_MAX_FLOORS 1 -#define NAND_MAX_CHIPS 1 - -#define CFG_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */ -#define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */ -#define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */ -#define CFG_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */ - -#define NAND_DISABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);} while(0) -#define NAND_ENABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CE);} while(0) -#define NAND_CTL_CLRALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_ALE);} while(0) -#define NAND_CTL_SETALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_ALE);} while(0) -#define NAND_CTL_CLRCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CLE);} while(0) -#define NAND_CTL_SETCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CLE);} while(0) -#define NAND_WAIT_READY(nand) while (!(in32(GPIO0_IR) & CFG_NAND_RDY)) - -#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0) -#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0) -#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0) -#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr)) +#define CFG_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */ +#define CFG_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */ +#define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */ +#define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */ #define CFG_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */ diff --git a/include/configs/HH405.h b/include/configs/HH405.h index dc40ebc86..f36777a12 100644 --- a/include/configs/HH405.h +++ b/include/configs/HH405.h @@ -130,8 +130,6 @@ /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ #include -#define CFG_NAND_LEGACY - #undef CONFIG_BZIP2 /* include support for bzip2 compressed images */ #undef CONFIG_WATCHDOG /* watchdog disabled */ @@ -198,34 +196,15 @@ * NAND-FLASH stuff *----------------------------------------------------------------------- */ -#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ -#define SECTORSIZE 512 +#define CFG_NAND_BASE_LIST { CFG_NAND_BASE } +#define NAND_MAX_CHIPS 1 +#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ +#define NAND_BIG_DELAY_US 25 -#define ADDR_COLUMN 1 -#define ADDR_PAGE 2 -#define ADDR_COLUMN_PAGE 3 - -#define NAND_ChipID_UNKNOWN 0x00 -#define NAND_MAX_FLOORS 1 -#define NAND_MAX_CHIPS 1 - -#define CFG_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */ -#define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */ -#define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */ -#define CFG_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */ - -#define NAND_DISABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);} while(0) -#define NAND_ENABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CE);} while(0) -#define NAND_CTL_CLRALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_ALE);} while(0) -#define NAND_CTL_SETALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_ALE);} while(0) -#define NAND_CTL_CLRCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CLE);} while(0) -#define NAND_CTL_SETCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CLE);} while(0) -#define NAND_WAIT_READY(nand) while (!(in32(GPIO0_IR) & CFG_NAND_RDY)) - -#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0) -#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0) -#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0) -#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr)) +#define CFG_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */ +#define CFG_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */ +#define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */ +#define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */ #define CFG_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */ diff --git a/include/configs/HUB405.h b/include/configs/HUB405.h index f84e35621..88cc6a482 100644 --- a/include/configs/HUB405.h +++ b/include/configs/HUB405.h @@ -135,36 +135,15 @@ * NAND-FLASH stuff *----------------------------------------------------------------------- */ -#define CFG_NAND_LEGACY +#define CFG_NAND_BASE_LIST { CFG_NAND_BASE } +#define NAND_MAX_CHIPS 1 +#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ +#define NAND_BIG_DELAY_US 25 -#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ -#define SECTORSIZE 512 - -#define ADDR_COLUMN 1 -#define ADDR_PAGE 2 -#define ADDR_COLUMN_PAGE 3 - -#define NAND_ChipID_UNKNOWN 0x00 -#define NAND_MAX_FLOORS 1 -#define NAND_MAX_CHIPS 1 - -#define CFG_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */ -#define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */ -#define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */ -#define CFG_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */ - -#define NAND_DISABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);} while(0) -#define NAND_ENABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CE);} while(0) -#define NAND_CTL_CLRALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_ALE);} while(0) -#define NAND_CTL_SETALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_ALE);} while(0) -#define NAND_CTL_CLRCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CLE);} while(0) -#define NAND_CTL_SETCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CLE);} while(0) -#define NAND_WAIT_READY(nand) while (!(in32(GPIO0_IR) & CFG_NAND_RDY)) - -#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0) -#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0) -#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0) -#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr)) +#define CFG_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */ +#define CFG_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */ +#define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */ +#define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */ #define CFG_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */ diff --git a/include/configs/PLU405.h b/include/configs/PLU405.h index d02c39b28..ef5ecba22 100644 --- a/include/configs/PLU405.h +++ b/include/configs/PLU405.h @@ -81,7 +81,6 @@ #define CONFIG_SUPPORT_VFAT #define CONFIG_AUTO_UPDATE 1 /* autoupdate via compactflash */ -#define CONFIG_AUTO_UPDATE_SHOW 1 /* use board show routine */ /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ #include @@ -156,36 +155,15 @@ * NAND-FLASH stuff *----------------------------------------------------------------------- */ -#define CFG_NAND_LEGACY +#define CFG_NAND_BASE_LIST { CFG_NAND_BASE } +#define NAND_MAX_CHIPS 1 +#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ +#define NAND_BIG_DELAY_US 25 -#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ -#define SECTORSIZE 512 - -#define ADDR_COLUMN 1 -#define ADDR_PAGE 2 -#define ADDR_COLUMN_PAGE 3 - -#define NAND_ChipID_UNKNOWN 0x00 -#define NAND_MAX_FLOORS 1 -#define NAND_MAX_CHIPS 1 - -#define CFG_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */ -#define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */ -#define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */ -#define CFG_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */ - -#define NAND_DISABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);} while(0) -#define NAND_ENABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CE);} while(0) -#define NAND_CTL_CLRALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_ALE);} while(0) -#define NAND_CTL_SETALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_ALE);} while(0) -#define NAND_CTL_CLRCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CLE);} while(0) -#define NAND_CTL_SETCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CLE);} while(0) -#define NAND_WAIT_READY(nand) while (!(in32(GPIO0_IR) & CFG_NAND_RDY)) - -#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0) -#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0) -#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0) -#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr)) +#define CFG_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */ +#define CFG_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */ +#define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */ +#define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */ #define CFG_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */ @@ -264,11 +242,6 @@ #define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ -#if 0 /* test-only */ -#define CFG_JFFS2_FIRST_BANK 0 /* use for JFFS2 */ -#define CFG_JFFS2_NUM_BANKS 1 /* ! second bank contains U-Boot */ -#endif - /*----------------------------------------------------------------------- * Start addresses for the final memory configuration * (Set up by the startup code) @@ -294,9 +267,6 @@ #define CFG_ENV_SIZE 0x700 /* 2048 bytes may be used for env vars*/ /* total size of a CAT24WC16 is 2048 bytes */ -#define CFG_NVRAM_BASE_ADDR 0xF0000500 /* NVRAM base address */ -#define CFG_NVRAM_SIZE 242 /* NVRAM size */ - /*----------------------------------------------------------------------- * I2C EEPROM (CAT24WC16) for environment */ @@ -305,7 +275,7 @@ #define CFG_I2C_SLAVE 0x7F #define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT24WC08 */ -#if 1 /* test-only */ + /* CAT24WC08/16... */ #define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ /* mask of address bits that overflow into the "EEPROM chip address" */ @@ -313,15 +283,6 @@ #define CFG_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */ /* 16 byte page write mode using*/ /* last 4 bits of the address */ -#else -/* CAT24WC32/64... */ -#define CFG_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */ -/* mask of address bits that overflow into the "EEPROM chip address" */ -#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x01 -#define CFG_EEPROM_PAGE_WRITE_BITS 5 /* The Catalyst CAT24WC32 has */ - /* 32 byte page write mode using*/ - /* last 5 bits of the address */ -#endif #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ #define CFG_EEPROM_PAGE_WRITE_ENABLE diff --git a/include/configs/VOH405.h b/include/configs/VOH405.h index 96f3d26cc..abd1ef43c 100644 --- a/include/configs/VOH405.h +++ b/include/configs/VOH405.h @@ -141,36 +141,15 @@ * NAND-FLASH stuff *----------------------------------------------------------------------- */ -#define CFG_NAND_LEGACY +#define CFG_NAND_BASE_LIST { CFG_NAND_BASE } +#define NAND_MAX_CHIPS 1 +#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ +#define NAND_BIG_DELAY_US 25 -#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ -#define SECTORSIZE 512 - -#define ADDR_COLUMN 1 -#define ADDR_PAGE 2 -#define ADDR_COLUMN_PAGE 3 - -#define NAND_ChipID_UNKNOWN 0x00 -#define NAND_MAX_FLOORS 1 -#define NAND_MAX_CHIPS 1 - -#define CFG_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */ -#define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */ -#define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */ -#define CFG_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */ - -#define NAND_DISABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);} while(0) -#define NAND_ENABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CE);} while(0) -#define NAND_CTL_CLRALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_ALE);} while(0) -#define NAND_CTL_SETALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_ALE);} while(0) -#define NAND_CTL_CLRCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CLE);} while(0) -#define NAND_CTL_SETCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CLE);} while(0) -#define NAND_WAIT_READY(nand) while (!(in32(GPIO0_IR) & CFG_NAND_RDY)) - -#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0) -#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0) -#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0) -#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr)) +#define CFG_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */ +#define CFG_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */ +#define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */ +#define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */ #define CFG_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */ diff --git a/include/configs/WUH405.h b/include/configs/WUH405.h index faf855d24..52bff401a 100644 --- a/include/configs/WUH405.h +++ b/include/configs/WUH405.h @@ -133,38 +133,16 @@ * NAND-FLASH stuff *----------------------------------------------------------------------- */ -#define CFG_NAND_LEGACY +#define CFG_NAND_BASE_LIST { CFG_NAND_BASE } +#define NAND_MAX_CHIPS 1 +#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ +#define NAND_BIG_DELAY_US 25 -#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ -#define SECTORSIZE 512 +#define CFG_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */ +#define CFG_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */ +#define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */ +#define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */ -#define ADDR_COLUMN 1 -#define ADDR_PAGE 2 -#define ADDR_COLUMN_PAGE 3 - -#define NAND_ChipID_UNKNOWN 0x00 -#define NAND_MAX_FLOORS 1 -#define NAND_MAX_CHIPS 1 - -#define CFG_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */ -#define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */ -#define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */ -#define CFG_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */ - -#define NAND_DISABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);} while(0) -#define NAND_ENABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CE);} while(0) -#define NAND_CTL_CLRALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_ALE);} while(0) -#define NAND_CTL_SETALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_ALE);} while(0) -#define NAND_CTL_CLRCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CLE);} while(0) -#define NAND_CTL_SETCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CLE);} while(0) -#define NAND_WAIT_READY(nand) while (!(in32(GPIO0_IR) & CFG_NAND_RDY)) - -#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0) -#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0) -#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0) -#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr)) - -#define CONFIG_MTD_NAND_VERIFY_WRITE 1 /* verify all writes!!! */ #define CFG_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */ /*----------------------------------------------------------------------- From 0f92c7e7c9a62755b1457d3c46f93c8c1f6c19fc Mon Sep 17 00:00:00 2001 From: Matthias Fuchs Date: Mon, 9 Jul 2007 10:10:08 +0200 Subject: [PATCH 010/259] Migrate esd 405EP boards to new NAND subsystem Remove unused CFG_NAND_LEGACY define These boards to not have NAND. Signed-off-by: Matthias Fuchs --- include/configs/CPCI405.h | 2 -- include/configs/CPCI4052.h | 2 -- include/configs/CPCI405AB.h | 3 --- include/configs/CPCI405DT.h | 2 -- 4 files changed, 9 deletions(-) diff --git a/include/configs/CPCI405.h b/include/configs/CPCI405.h index 9acde1e6f..9c0412932 100644 --- a/include/configs/CPCI405.h +++ b/include/configs/CPCI405.h @@ -83,8 +83,6 @@ /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ #include -#define CFG_NAND_LEGACY - #undef CONFIG_WATCHDOG /* watchdog disabled */ #define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ diff --git a/include/configs/CPCI4052.h b/include/configs/CPCI4052.h index 3fc99c502..2a328a63a 100644 --- a/include/configs/CPCI4052.h +++ b/include/configs/CPCI4052.h @@ -105,8 +105,6 @@ /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ #include -#define CFG_NAND_LEGACY - #undef CONFIG_WATCHDOG /* watchdog disabled */ #define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ diff --git a/include/configs/CPCI405AB.h b/include/configs/CPCI405AB.h index 4e2e1a834..69466862b 100644 --- a/include/configs/CPCI405AB.h +++ b/include/configs/CPCI405AB.h @@ -91,9 +91,6 @@ /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ #include -#define CFG_NAND_LEGACY - - #undef CONFIG_WATCHDOG /* watchdog disabled */ #define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ diff --git a/include/configs/CPCI405DT.h b/include/configs/CPCI405DT.h index ab302df74..4ae240e91 100644 --- a/include/configs/CPCI405DT.h +++ b/include/configs/CPCI405DT.h @@ -102,8 +102,6 @@ /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ #include -#define CFG_NAND_LEGACY - #undef CONFIG_WATCHDOG /* watchdog disabled */ #define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ From c8603cfbd4573379a6076c9c208545ba2bbf019a Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Mon, 9 Jul 2007 11:00:24 +0200 Subject: [PATCH 011/259] Small coding style cleanup Signed-off-by: Stefan Roese --- board/esd/cpci405/cpci405.c | 1 - board/esd/wuh405/wuh405.c | 1 - 2 files changed, 2 deletions(-) diff --git a/board/esd/cpci405/cpci405.c b/board/esd/cpci405/cpci405.c index 2ed0fc272..23585777d 100644 --- a/board/esd/cpci405/cpci405.c +++ b/board/esd/cpci405/cpci405.c @@ -585,7 +585,6 @@ int pci_pre_init(struct pci_controller *hose) #endif /* defined(CONFIG_PCI) */ - #ifdef CONFIG_CPCI405AB #define ONE_WIRE_CLEAR (*(volatile unsigned short *)(CFG_FPGA_BASE_ADDR + CFG_FPGA_MODE) \ diff --git a/board/esd/wuh405/wuh405.c b/board/esd/wuh405/wuh405.c index 0b5306235..5fde8d650 100644 --- a/board/esd/wuh405/wuh405.c +++ b/board/esd/wuh405/wuh405.c @@ -216,4 +216,3 @@ long int initdram (int board_type) } /* ------------------------------------------------------------------------- */ - From be296e31c4411f96d9cb3d2afc8fcb006867abfa Mon Sep 17 00:00:00 2001 From: TsiChungLiew Date: Thu, 5 Jul 2007 22:24:58 -0500 Subject: [PATCH 012/259] Revert file mode Changed MAKEALL file mode to executable, removed executable file mode from Makefile Signed-off-by: TsiChungLiew --- MAKEALL | 0 Makefile | 0 2 files changed, 0 insertions(+), 0 deletions(-) mode change 100644 => 100755 MAKEALL mode change 100755 => 100644 Makefile diff --git a/MAKEALL b/MAKEALL old mode 100644 new mode 100755 diff --git a/Makefile b/Makefile old mode 100755 new mode 100644 From 48dbfeabc7afffe30609a4489f10c22cb67ef7dd Mon Sep 17 00:00:00 2001 From: TsiChungLiew Date: Thu, 5 Jul 2007 22:39:07 -0500 Subject: [PATCH 013/259] Create new header file and move peripherals base address from configs file to new header file. Create new header file to include immap_5xxx.h and m5xxx.h and to share among drivers without update in driver file each processor is added. Moved peripherals base address and defines from configs file to immap.h. Signed-off-by: TsiChungLiew --- include/asm-m68k/immap.h | 57 ++++++++++++++++++++++++++++++++++++++ include/configs/M5329EVB.h | 46 ++++-------------------------- 2 files changed, 63 insertions(+), 40 deletions(-) create mode 100644 include/asm-m68k/immap.h diff --git a/include/asm-m68k/immap.h b/include/asm-m68k/immap.h new file mode 100644 index 000000000..495459e83 --- /dev/null +++ b/include/asm-m68k/immap.h @@ -0,0 +1,57 @@ +/* + * ColdFire Internal Memory Map and Defines + * + * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __IMMAP_H +#define __IMMAP_H + +#ifdef CONFIG_M5329 +#include +#include + +#define CFG_FEC0_IOBASE (MMAP_FEC) +#define CFG_UART_BASE (MMAP_UART0 + (CFG_UART_PORT * 0x4000)) +#define CFG_MCFRTC_BASE (MMAP_RTC) + +/* Timer */ +#ifdef CONFIG_MCFTMR +#define CFG_UDELAY_BASE (MMAP_DTMR0) +#define CFG_TMR_BASE (MMAP_DTMR1) +#define CFG_TMRINTR_NO (INT0_HI_DTMR1) +#define CFG_TMRINTR_MASK (INTC_IPRH_INT33) +#define CFG_TMRINTR_PRI (6) +#define CFG_TIMER_PRESCALER (((CFG_CLK / 1000000) - 1) << 8) +#endif + +#ifdef CONFIG_MCFPIT +#define CFG_UDELAY_BASE (MMAP_PIT0) +#define CFG_PIT_BASE (MMAP_PIT1) +#define CFG_PIT_PRESCALE (6) +#endif + +#define CFG_INTR_BASE (MMAP_INTC0) +#define CFG_NUM_IRQS (128) +#endif /* CONFIG_M5329 */ + +#endif /* __IMMAP_H */ diff --git a/include/configs/M5329EVB.h b/include/configs/M5329EVB.h index ac529dfbc..c90773c50 100644 --- a/include/configs/M5329EVB.h +++ b/include/configs/M5329EVB.h @@ -46,8 +46,6 @@ #undef CONFIG_WATCHDOG #define CONFIG_WATCHDOG_TIMEOUT 5000 /* timeout in milliseconds, max timeout is 6.71sec */ -#define CFG_NUM_IRQS 128 - #define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ CFG_CMD_CACHE | \ CFG_CMD_DATE | \ @@ -70,7 +68,6 @@ # define CFG_RX_ETH_BUFFER 8 # define CFG_FAULT_ECHO_LINK_DOWN -# define CFG_FEC0_IOBASE 0xFC030000 # define CFG_FEC0_PINMUX 0 # define CFG_FEC0_MIIBASE CFG_FEC0_IOBASE # define MCFFEC_TOUT_LOOP 50000 @@ -86,41 +83,14 @@ #endif #define CONFIG_MCFUART -#ifdef CONFIG_MCFUART -# define CFG_UART_PORT (0) -# define CFG_UART_BASE (0xFC060000) -#endif +#define CFG_UART_PORT (0) #define CONFIG_MCFRTC -#ifdef CONFIG_MCFRTC -# define CFG_MCFRTC_BASE (0xFC0A8000) -# undef RTC_DEBUG -#endif +#undef RTC_DEBUG /* Timer */ #define CONFIG_MCFTMR -#ifdef CONFIG_MCFTMR -# define CFG_UDELAY_BASE (0xFC070000) -# define CFG_TMR_BASE (0xFC074000) -# define CFG_TMRINTR_NO (33) -# define CFG_TMRINTR_MASK (2) -# define CFG_TMRINTR_PRI (6) -# define CFG_TIMER_PRESCALER (((CFG_CLK / 1000000) - 1) << 8) -#endif - #undef CONFIG_MCFPIT -#ifdef CONFIG_MCFPIT -# define CFG_UDELAY_BASE (0xFC080000) -# define CFG_PIT_BASE (0xFC084000) -# define CFG_PIT_PRESCALE (6) -#endif - -#define CONFIG_MCFINTC -#ifdef CONFIG_MCFINTC -# define CFG_INTR_BASE (0xFC048000) -# define CFG_NUM_IRQ0 64 -# define CFG_NUM_IRQ1 64 -#endif /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ #include @@ -215,22 +185,18 @@ /*----------------------------------------------------------------------- * FLASH organization */ -#undef CFG_FLASH_CFI +#define CFG_FLASH_CFI #ifdef CFG_FLASH_CFI # define CFG_FLASH_CFI_DRIVER 1 # define CFG_FLASH_SIZE 0x800000 /* Max size that the board might have */ # define CFG_FLASH_CFI_WIDTH FLASH_CFI_16BIT -#else -# define CFG_FLASH_UNLOCK_TOUT 1000 -# define CFG_FLASH_WRITE_TOUT 1000 +# define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +# define CFG_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ +# define CFG_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ #endif #define CFG_FLASH_BASE 0 #define CFG_FLASH0_BASE (CFG_CS0_BASE << 16) -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ -#define CFG_FLASH_ERASE_TOUT 1000 -#define CFG_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ /* Configuration for environment * Environment is embedded in u-boot in the second sector of the flash From 514871f565dd8bd1121e4a3ac1665a790e20b8f2 Mon Sep 17 00:00:00 2001 From: TsiChungLiew Date: Thu, 5 Jul 2007 22:41:24 -0500 Subject: [PATCH 014/259] Clean up Replaced whitespace with tabs Signed-off-by: TsiChungLiew --- include/asm-m68k/immap_5329.h | 80 +++++++++++++++++------------------ 1 file changed, 40 insertions(+), 40 deletions(-) diff --git a/include/asm-m68k/immap_5329.h b/include/asm-m68k/immap_5329.h index 5ef1265f8..2a3980c13 100644 --- a/include/asm-m68k/immap_5329.h +++ b/include/asm-m68k/immap_5329.h @@ -26,46 +26,46 @@ #ifndef __IMMAP_5329__ #define __IMMAP_5329__ -#define MMAP_SCM1 0xEC000000 -#define MMAP_MDHA 0xEC080000 -#define MMAP_SKHA 0xEC084000 -#define MMAP_RNG 0xEC088000 -#define MMAP_SCM2 0xFC000000 -#define MMAP_XBS 0xFC004000 -#define MMAP_FBCS 0xFC008000 -#define MMAP_CAN 0xFC020000 -#define MMAP_FEC 0xFC030000 -#define MMAP_SCM3 0xFC040000 -#define MMAP_EDMA 0xFC044000 -#define MMAP_TCD 0xFC045000 -#define MMAP_INTC0 0xFC048000 -#define MMAP_INTC1 0xFC04C000 -#define MMAP_INTCACK 0xFC054000 -#define MMAP_I2C 0xFC058000 -#define MMAP_QSPI 0xFC05C000 -#define MMAP_UART0 0xFC060000 -#define MMAP_UART1 0xFC064000 -#define MMAP_UART2 0xFC068000 -#define MMAP_DTMR0 0xFC070000 -#define MMAP_DTMR1 0xFC074000 -#define MMAP_DTMR2 0xFC078000 -#define MMAP_DTMR3 0xFC07C000 -#define MMAP_PIT0 0xFC080000 -#define MMAP_PIT1 0xFC084000 -#define MMAP_PIT2 0xFC088000 -#define MMAP_PIT3 0xFC08C000 -#define MMAP_PWM 0xFC090000 -#define MMAP_EPORT 0xFC094000 -#define MMAP_WDOG 0xFC098000 -#define MMAP_CCM 0xFC0A0000 -#define MMAP_GPIO 0xFC0A4000 -#define MMAP_RTC 0xFC0A8000 -#define MMAP_LCDC 0xFC0AC000 -#define MMAP_USBOTG 0xFC0B0000 -#define MMAP_USBH 0xFC0B4000 -#define MMAP_SDRAM 0xFC0B8000 -#define MMAP_SSI 0xFC0BC000 -#define MMAP_PLL 0xFC0C0000 +#define MMAP_SCM1 0xEC000000 +#define MMAP_MDHA 0xEC080000 +#define MMAP_SKHA 0xEC084000 +#define MMAP_RNG 0xEC088000 +#define MMAP_SCM2 0xFC000000 +#define MMAP_XBS 0xFC004000 +#define MMAP_FBCS 0xFC008000 +#define MMAP_CAN 0xFC020000 +#define MMAP_FEC 0xFC030000 +#define MMAP_SCM3 0xFC040000 +#define MMAP_EDMA 0xFC044000 +#define MMAP_TCD 0xFC045000 +#define MMAP_INTC0 0xFC048000 +#define MMAP_INTC1 0xFC04C000 +#define MMAP_INTCACK 0xFC054000 +#define MMAP_I2C 0xFC058000 +#define MMAP_QSPI 0xFC05C000 +#define MMAP_UART0 0xFC060000 +#define MMAP_UART1 0xFC064000 +#define MMAP_UART2 0xFC068000 +#define MMAP_DTMR0 0xFC070000 +#define MMAP_DTMR1 0xFC074000 +#define MMAP_DTMR2 0xFC078000 +#define MMAP_DTMR3 0xFC07C000 +#define MMAP_PIT0 0xFC080000 +#define MMAP_PIT1 0xFC084000 +#define MMAP_PIT2 0xFC088000 +#define MMAP_PIT3 0xFC08C000 +#define MMAP_PWM 0xFC090000 +#define MMAP_EPORT 0xFC094000 +#define MMAP_WDOG 0xFC098000 +#define MMAP_CCM 0xFC0A0000 +#define MMAP_GPIO 0xFC0A4000 +#define MMAP_RTC 0xFC0A8000 +#define MMAP_LCDC 0xFC0AC000 +#define MMAP_USBOTG 0xFC0B0000 +#define MMAP_USBH 0xFC0B4000 +#define MMAP_SDRAM 0xFC0B8000 +#define MMAP_SSI 0xFC0BC000 +#define MMAP_PLL 0xFC0C0000 /* System control module registers */ typedef struct scm1_ctrl { From 8cd5cd6de4ff92e03978338ed7aeb3ce7b7b9784 Mon Sep 17 00:00:00 2001 From: TsiChungLiew Date: Thu, 5 Jul 2007 22:42:23 -0500 Subject: [PATCH 015/259] Clean up Removed whitespace Signed-off-by: TsiChungLiew --- include/asm-m68k/io.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/asm-m68k/io.h b/include/asm-m68k/io.h index cec25d0bf..8dea02aba 100644 --- a/include/asm-m68k/io.h +++ b/include/asm-m68k/io.h @@ -23,7 +23,7 @@ * MA 02111-1307 USA */ - #ifndef __ASM_M68K_IO_H__ +#ifndef __ASM_M68K_IO_H__ #define __ASM_M68K_IO_H__ #include From 2bd58608dbcff8890ca9a0c59e861ac24f8bb230 Mon Sep 17 00:00:00 2001 From: TsiChungLiew Date: Thu, 5 Jul 2007 22:45:01 -0500 Subject: [PATCH 016/259] Seperate old structure defines and new structure defines New timer structure and defines will move to new timer.h Signed-off-by: TsiChungLiew --- include/asm-m68k/mcftimer.h | 72 ------------------------------------- 1 file changed, 72 deletions(-) diff --git a/include/asm-m68k/mcftimer.h b/include/asm-m68k/mcftimer.h index 988860d07..381f4eb8e 100644 --- a/include/asm-m68k/mcftimer.h +++ b/include/asm-m68k/mcftimer.h @@ -107,77 +107,5 @@ #define MCFTIMER_PCSR_HALTED 0x0020 #define MCFTIMER_PCSR_DOZE 0x0040 -/****************************************************************************/ -/* New Timer structure */ -/****************************************************************************/ -/* DMA Timer module registers */ -typedef struct dtimer_ctrl { - u16 tmr; /* 0x00 Mode register */ - u8 txmr; /* 0x02 Extended Mode register */ - u8 ter; /* 0x03 Event register */ - u32 trr; /* 0x04 Reference register */ - u32 tcr; /* 0x08 Capture register */ - u32 tcn; /* 0x0C Counter register */ -} dtmr_t; - -/*Programmable Interrupt Timer */ -typedef struct pit_ctrl { - u16 pcsr; /* 0x00 Control and Status Register */ - u16 pmr; /* 0x02 Modulus Register */ - u16 pcntr; /* 0x04 Count Register */ -} pit_t; - -/********************************************************************* -* DMA Timers (DTIM) -*********************************************************************/ -/* Bit definitions and macros for DTMR */ -#define DTIM_DTMR_RST (0x0001) /* Reset */ -#define DTIM_DTMR_CLK(x) (((x)&0x0003)<<1) /* Input clock source */ -#define DTIM_DTMR_FRR (0x0008) /* Free run/restart */ -#define DTIM_DTMR_ORRI (0x0010) /* Output reference request/interrupt enable */ -#define DTIM_DTMR_OM (0x0020) /* Output Mode */ -#define DTIM_DTMR_CE(x) (((x)&0x0003)<<6) /* Capture Edge */ -#define DTIM_DTMR_PS(x) (((x)&0x00FF)<<8) /* Prescaler value */ -#define DTIM_DTMR_RST_EN (0x0001) -#define DTIM_DTMR_RST_RST (0x0000) -#define DTIM_DTMR_CE_ANY (0x00C0) -#define DTIM_DTMR_CE_FALL (0x0080) -#define DTIM_DTMR_CE_RISE (0x0040) -#define DTIM_DTMR_CE_NONE (0x0000) -#define DTIM_DTMR_CLK_DTIN (0x0006) -#define DTIM_DTMR_CLK_DIV16 (0x0004) -#define DTIM_DTMR_CLK_DIV1 (0x0002) -#define DTIM_DTMR_CLK_STOP (0x0000) - -/* Bit definitions and macros for DTXMR */ -#define DTIM_DTXMR_MODE16 (0x01) /* Increment Mode */ -#define DTIM_DTXMR_DMAEN (0x80) /* DMA request */ - -/* Bit definitions and macros for DTER */ -#define DTIM_DTER_CAP (0x01) /* Capture event */ -#define DTIM_DTER_REF (0x02) /* Output reference event */ - -/********************************************************************* -* -* Programmable Interrupt Timer Modules (PIT) -* -*********************************************************************/ - -/* Bit definitions and macros for PCSR */ -#define PIT_PCSR_EN (0x0001) -#define PIT_PCSR_RLD (0x0002) -#define PIT_PCSR_PIF (0x0004) -#define PIT_PCSR_PIE (0x0008) -#define PIT_PCSR_OVW (0x0010) -#define PIT_PCSR_HALTED (0x0020) -#define PIT_PCSR_DOZE (0x0040) -#define PIT_PCSR_PRE(x) (((x)&0x000F)<<8) - -/* Bit definitions and macros for PMR */ -#define PIT_PMR_PM(x) (x) - -/* Bit definitions and macros for PCNTR */ -#define PIT_PCNTR_PC(x) (x) - /****************************************************************************/ #endif /* mcftimer_h */ From 2744354a8437b8f78db178e30660215688bff570 Mon Sep 17 00:00:00 2001 From: TsiChungLiew Date: Thu, 5 Jul 2007 22:46:38 -0500 Subject: [PATCH 017/259] Seperate old structure defines and new structure defines Removed new uart structure and defines to uart.h Signed-off-by: TsiChungLiew --- include/asm-m68k/mcfuart.h | 144 ------------------------------------- 1 file changed, 144 deletions(-) diff --git a/include/asm-m68k/mcfuart.h b/include/asm-m68k/mcfuart.h index 43b49a87c..1ccc43f0f 100644 --- a/include/asm-m68k/mcfuart.h +++ b/include/asm-m68k/mcfuart.h @@ -215,147 +215,3 @@ #define MCFUART_URF_FULL 0x20 /* receiver fifo full */ #define MCFUART_URF_RXS 0xc0 /* receiver status */ #endif - -#ifdef CONFIG_MCFUART -/* UART module registers */ -/* Register read/write struct */ -typedef struct uart { - u8 umr; /* 0x00 Mode Register */ - u8 resv0[0x3]; - union { - u8 usr; /* 0x04 Status Register */ - u8 ucsr; /* 0x04 Clock Select Register */ - }; - u8 resv1[0x3]; - u8 ucr; /* 0x08 Command Register */ - u8 resv2[0x3]; - union { - u8 utb; /* 0x0c Transmit Buffer */ - u8 urb; /* 0x0c Receive Buffer */ - }; - u8 resv3[0x3]; - union { - u8 uipcr; /* 0x10 Input Port Change Register */ - u8 uacr; /* 0x10 Auxiliary Control reg */ - }; - u8 resv4[0x3]; - union { - u8 uimr; /* 0x14 Interrupt Mask reg */ - u8 uisr; /* 0x14 Interrupt Status reg */ - }; - u8 resv5[0x3]; - u8 ubg1; /* 0x18 Counter Timer Upper Register */ - u8 resv6[0x3]; - u8 ubg2; /* 0x1c Counter Timer Lower Register */ - u8 resv7[0x17]; - u8 uip; /* 0x34 Input Port Register */ - u8 resv8[0x3]; - u8 uop1; /* 0x38 Output Port Set Register */ - u8 resv9[0x3]; - u8 uop0; /* 0x3c Output Port Reset Register */ -} uart_t; - -/********************************************************************* -* Universal Asynchronous Receiver Transmitter (UART) -*********************************************************************/ -/* Bit definitions and macros for UMR */ -#define UART_UMR_BC(x) (((x)&0x03)) -#define UART_UMR_PT (0x04) -#define UART_UMR_PM(x) (((x)&0x03)<<3) -#define UART_UMR_ERR (0x20) -#define UART_UMR_RXIRQ (0x40) -#define UART_UMR_RXRTS (0x80) -#define UART_UMR_SB(x) (((x)&0x0F)) -#define UART_UMR_TXCTS (0x10) /* Trsnsmit CTS */ -#define UART_UMR_TXRTS (0x20) /* Transmit RTS */ -#define UART_UMR_CM(x) (((x)&0x03)<<6) /* CM bits */ -#define UART_UMR_PM_MULTI_ADDR (0x1C) -#define UART_UMR_PM_MULTI_DATA (0x18) -#define UART_UMR_PM_NONE (0x10) -#define UART_UMR_PM_FORCE_HI (0x0C) -#define UART_UMR_PM_FORCE_LO (0x08) -#define UART_UMR_PM_ODD (0x04) -#define UART_UMR_PM_EVEN (0x00) -#define UART_UMR_BC_5 (0x00) -#define UART_UMR_BC_6 (0x01) -#define UART_UMR_BC_7 (0x02) -#define UART_UMR_BC_8 (0x03) -#define UART_UMR_CM_NORMAL (0x00) -#define UART_UMR_CM_ECH (0x40) -#define UART_UMR_CM_LOCAL_LOOP (0x80) -#define UART_UMR_CM_REMOTE_LOOP (0xC0) -#define UART_UMR_SB_STOP_BITS_1 (0x07) -#define UART_UMR_SB_STOP_BITS_15 (0x08) -#define UART_UMR_SB_STOP_BITS_2 (0x0F) - -/* Bit definitions and macros for USR */ -#define UART_USR_RXRDY (0x01) -#define UART_USR_FFULL (0x02) -#define UART_USR_TXRDY (0x04) -#define UART_USR_TXEMP (0x08) -#define UART_USR_OE (0x10) -#define UART_USR_PE (0x20) -#define UART_USR_FE (0x40) -#define UART_USR_RB (0x80) - -/* Bit definitions and macros for UCSR */ -#define UART_UCSR_TCS(x) (((x)&0x0F)) -#define UART_UCSR_RCS(x) (((x)&0x0F)<<4) -#define UART_UCSR_RCS_SYS_CLK (0xD0) -#define UART_UCSR_RCS_CTM16 (0xE0) -#define UART_UCSR_RCS_CTM (0xF0) -#define UART_UCSR_TCS_SYS_CLK (0x0D) -#define UART_UCSR_TCS_CTM16 (0x0E) -#define UART_UCSR_TCS_CTM (0x0F) - -/* Bit definitions and macros for UCR */ -#define UART_UCR_RXC(x) (((x)&0x03)) -#define UART_UCR_TXC(x) (((x)&0x03)<<2) -#define UART_UCR_MISC(x) (((x)&0x07)<<4) -#define UART_UCR_NONE (0x00) -#define UART_UCR_STOP_BREAK (0x70) -#define UART_UCR_START_BREAK (0x60) -#define UART_UCR_BKCHGINT (0x50) -#define UART_UCR_RESET_ERROR (0x40) -#define UART_UCR_RESET_TX (0x30) -#define UART_UCR_RESET_RX (0x20) -#define UART_UCR_RESET_MR (0x10) -#define UART_UCR_TX_DISABLED (0x08) -#define UART_UCR_TX_ENABLED (0x04) -#define UART_UCR_RX_DISABLED (0x02) -#define UART_UCR_RX_ENABLED (0x01) - -/* Bit definitions and macros for UIPCR */ -#define UART_UIPCR_CTS (0x01) -#define UART_UIPCR_COS (0x10) - -/* Bit definitions and macros for UACR */ -#define UART_UACR_IEC (0x01) - -/* Bit definitions and macros for UIMR */ -#define UART_UIMR_TXRDY (0x01) -#define UART_UIMR_RXRDY_FU (0x02) -#define UART_UIMR_DB (0x04) -#define UART_UIMR_COS (0x80) - -/* Bit definitions and macros for UISR */ -#define UART_UISR_TXRDY (0x01) -#define UART_UISR_RXRDY_FU (0x02) -#define UART_UISR_DB (0x04) -#define UART_UISR_RXFTO (0x08) -#define UART_UISR_TXFIFO (0x10) -#define UART_UISR_RXFIFO (0x20) -#define UART_UISR_COS (0x80) - -/* Bit definitions and macros for UIP */ -#define UART_UIP_CTS (0x01) - -/* Bit definitions and macros for UOP1 */ -#define UART_UOP1_RTS (0x01) - -/* Bit definitions and macros for UOP0 */ -#define UART_UOP0_RTS (0x01) -#endif /* CONFIG_MCFUART */ - -/****************************************************************************/ -#endif /* mcfuart_h */ From 01a793fda09c63df5a496f09dc1c7cb26e6751a2 Mon Sep 17 00:00:00 2001 From: TsiChungLiew Date: Thu, 5 Jul 2007 22:51:05 -0500 Subject: [PATCH 018/259] Duplicate code There is a Common Flash Interface Driver existed. To use the CFI driver, define CFG_FLASH_CFI in configuration file. Signed-off-by: TsiChungLiew --- board/freescale/m5329evb/flash.c | 643 ------------------------------- 1 file changed, 643 deletions(-) delete mode 100644 board/freescale/m5329evb/flash.c diff --git a/board/freescale/m5329evb/flash.c b/board/freescale/m5329evb/flash.c deleted file mode 100644 index 7d3b0e84d..000000000 --- a/board/freescale/m5329evb/flash.c +++ /dev/null @@ -1,643 +0,0 @@ -/* - * (C) Copyright 2000-2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. - * TsiChung Liew (Tsi-Chung.Liew@freescale.com) - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include - -#ifndef CFG_FLASH_CFI - -typedef unsigned short FLASH_PORT_WIDTH; -typedef volatile unsigned short FLASH_PORT_WIDTHV; - -#define PHYS_FLASH_1 CFG_FLASH_BASE -#define FLASH_BANK_SIZE 0x200000 - -#define FPW FLASH_PORT_WIDTH -#define FPWV FLASH_PORT_WIDTHV - -/* Intel-compatible flash commands */ -#define INTEL_PROGRAM 0x00100010 -#define INTEL_ERASE 0x00200020 -#define INTEL_WRSETUP 0x00400040 -#define INTEL_CLEAR 0x00500050 -#define INTEL_LOCKBIT 0x00600060 -#define INTEL_PROTECT 0x00010001 -#define INTEL_STATUS 0x00700070 -#define INTEL_READID 0x00900090 -#define INTEL_CFIQRY 0x00980098 -#define INTEL_SUSERASE 0x00B000B0 -#define INTEL_PROTPROG 0x00C000C0 -#define INTEL_CONFIRM 0x00D000D0 -#define INTEL_RESET 0x00FF00FF - -/* Intel-compatible flash status bits */ -#define INTEL_FINISHED 0x00800080 -#define INTEL_OK 0x00800080 -#define INTEL_ERASESUS 0x00600060 -#define INTEL_WSM_SUS (INTEL_FINISHED | INTEL_ERASESUS) - -/* 28F160C3B CFI Data offset - This could vary */ -#define INTEL_CFI_MFG 0x00 /* Manufacturer ID */ -#define INTEL_CFI_PART 0x01 /* Product ID */ -#define INTEL_CFI_LOCK 0x02 /* */ -#define INTEL_CFI_TWPRG 0x1F /* Typical Single Word Program Timeout 2^n us */ -#define INTEL_CFI_MBUFW 0x20 /* Typical Max Buffer Write Timeout 2^n us */ -#define INTEL_CFI_TERB 0x21 /* Typical Block Erase Timeout 2^n ms */ -#define INTEL_CFI_MWPRG 0x23 /* Maximum Word program timeout 2^n us */ -#define INTEL_CFI_MERB 0x25 /* Maximum Block Erase Timeout 2^n s */ -#define INTEL_CFI_SIZE 0x27 /* Device size 2^n bytes */ -#define INTEL_CFI_BANK 0x2C /* Number of Bank */ -#define INTEL_CFI_SZ1A 0x2F /* Block Region Size */ -#define INTEL_CFI_SZ1B 0x30 -#define INTEL_CFI_SZ2A 0x33 -#define INTEL_CFI_SZ2B 0x34 -#define INTEL_CFI_BLK1 0x2D /* Number of Blocks */ -#define INTEL_CFI_BLK2 0x31 - -#define WR_BLOCK 0x20 - -#define SYNC __asm__("nop") - -/*----------------------------------------------------------------------- - * Functions - */ - -ulong flash_get_size(FPWV * addr, flash_info_t * info); -int flash_get_offsets(ulong base, flash_info_t * info); -int flash_cmd_rd(FPWV * addr, int index); -int write_data(flash_info_t * info, ulong dest, FPW data); -void flash_sync_real_protect(flash_info_t * info); -uchar intel_sector_protected(flash_info_t * info, ushort sector); - -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; - -ulong flash_init(void) -{ - FPWV *flash_addr[CFG_MAX_FLASH_BANKS]; - ulong size; - int i; - - flash_addr[0] = (FPW *) CFG_FLASH0_BASE; -#ifdef CFG_FLASH1_BASE - flash_addr[1] = (FPW *) CFG_FLASH1_BASE; -#endif - - for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) { - memset(&flash_info[i], 0, sizeof(flash_info_t)); - - size = flash_get_size(flash_addr[i], &flash_info[i]); - flash_protect(FLAG_PROTECT_CLEAR, - flash_info[i].start[0], - flash_info[i].start[0] + size - 1, - &flash_info[0]); - /* get the h/w and s/w protection status in sync */ - flash_sync_real_protect(&flash_info[i]); - } - - /* Protect monitor and environment sectors */ - flash_protect(FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE + monitor_flash_len - 1, &flash_info[0]); - - return size; -} - -void flash_print_info(flash_info_t * info) -{ - int i; - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_INTEL: - printf("INTEL "); - break; - default: - printf("Unknown Vendor "); - break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_28F160C3B: - printf("28F160C3B\n"); - break; - case FLASH_28F160C3T: - printf("28F160C3T\n"); - break; - case FLASH_28F320C3B: - printf("28F320C3B\n"); - break; - case FLASH_28F320C3T: - printf("28F320C3T\n"); - break; - case FLASH_28F640C3B: - printf("28F640C3B\n"); - break; - case FLASH_28F640C3T: - printf("28F640C3T\n"); - break; - default: - printf("Unknown Chip Type\n"); - return; - } - - if (info->size > 0x100000) { - int remainder; - - printf(" Size: %ld", info->size >> 20); - - remainder = (info->size % 0x100000); - if (remainder) { - remainder >>= 10; - remainder = (int)((float) - (((float)remainder / (float)1024) * - 10000)); - printf(".%d ", remainder); - } - - printf("MB in %d Sectors\n", info->sector_count); - } else - printf(" Size: %ld KB in %d Sectors\n", - info->size >> 10, info->sector_count); - - printf(" Sector Start Addresses:"); - for (i = 0; i < info->sector_count; ++i) { - if ((i % 5) == 0) - printf("\n "); - printf(" %08lX%s", - info->start[i], info->protect[i] ? " (RO)" : " "); - } - printf("\n"); -} - -/* - * The following code cannot be run from FLASH! - */ -ulong flash_get_size(FPWV * addr, flash_info_t * info) -{ - int intel = 0; - u16 value; - static int bank = 0; - - /* Write auto select command: read Manufacturer ID */ - /* Write auto select command sequence and test FLASH answer */ - *addr = (FPW) INTEL_RESET; /* restore read mode */ - *addr = (FPW) INTEL_READID; - - switch (addr[INTEL_CFI_MFG] & 0xff) { - case (ushort) INTEL_MANUFACT: - info->flash_id = FLASH_MAN_INTEL; - value = addr[INTEL_CFI_PART]; - intel = 1; - break; - default: - printf("Unknown Flash\n"); - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - *addr = (FPW) INTEL_RESET; /* restore read mode */ - return (0); /* no or unknown flash */ - } - - switch (value) { - case (u16) INTEL_ID_28F160C3B: - info->flash_id += FLASH_28F160C3B; - break; - case (u16) INTEL_ID_28F160C3T: - info->flash_id += FLASH_28F160C3T; - break; - case (u16) INTEL_ID_28F320C3B: - info->flash_id += FLASH_28F320C3B; - break; - case (u16) INTEL_ID_28F320C3T: - info->flash_id += FLASH_28F320C3T; - break; - case (u16) INTEL_ID_28F640C3B: - info->flash_id += FLASH_28F640C3B; - break; - case (u16) INTEL_ID_28F640C3T: - info->flash_id += FLASH_28F640C3T; - break; - default: - info->flash_id = FLASH_UNKNOWN; - break; - } - - if (intel) { - /* Intel spec. under CFI section */ - u32 sz, size, offset; - int sec, sectors, bs; - int part, i, j, cnt; - - part = flash_cmd_rd(addr, INTEL_CFI_BANK); - - /* Geometry y1 = y1 + 1, y2 = y2 + 1, CFI spec. - * To be exact, Z = [0x2f 0x30] (LE) * 256 bytes * [0x2D 0x2E] block count - * Z = [0x33 0x34] (LE) * 256 bytes * [0x31 0x32] block count - */ - offset = (u32) addr; - sectors = sec = 0; - size = sz = cnt = 0; - for (i = 0; i < part; i++) { - bs = (((addr[INTEL_CFI_SZ1B + i * 4] << 8) | - addr[INTEL_CFI_SZ1A + i * 4]) * 0x100); - sec = addr[INTEL_CFI_BLK1 + i * 4] + 1; - sz = bs * sec; - - for (j = 0; j < sec; j++) { - info->start[cnt++] = offset; - offset += bs; - } - - sectors += sec; - size += sz; - } - info->sector_count = sectors; - info->size = size; - } - - if (info->sector_count > CFG_MAX_FLASH_SECT) { - printf("** ERROR: sector count %d > max (%d) **\n", - info->sector_count, CFG_MAX_FLASH_SECT); - info->sector_count = CFG_MAX_FLASH_SECT; - } - - *addr = (FPW) INTEL_RESET; /* restore read mode */ - - return (info->size); -} - -int flash_cmd_rd(FPWV * addr, int index) -{ - return (int)addr[index]; -} - -/* - * This function gets the u-boot flash sector protection status - * (flash_info_t.protect[]) in sync with the sector protection - * status stored in hardware. - */ -void flash_sync_real_protect(flash_info_t * info) -{ - int i; - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_28F160C3B: - case FLASH_28F160C3T: - case FLASH_28F320C3B: - case FLASH_28F320C3T: - case FLASH_28F640C3B: - case FLASH_28F640C3T: - for (i = 0; i < info->sector_count; ++i) { - info->protect[i] = intel_sector_protected(info, i); - } - break; - default: - /* no h/w protect support */ - break; - } -} - -/* - * checks if "sector" in bank "info" is protected. Should work on intel - * strata flash chips 28FxxxJ3x in 8-bit mode. - * Returns 1 if sector is protected (or timed-out while trying to read - * protection status), 0 if it is not. - */ -uchar intel_sector_protected(flash_info_t * info, ushort sector) -{ - FPWV *addr; - FPWV *lock_conf_addr; - ulong start; - unsigned char ret; - - /* - * first, wait for the WSM to be finished. The rationale for - * waiting for the WSM to become idle for at most - * CFG_FLASH_ERASE_TOUT is as follows. The WSM can be busy - * because of: (1) erase, (2) program or (3) lock bit - * configuration. So we just wait for the longest timeout of - * the (1)-(3), i.e. the erase timeout. - */ - - /* wait at least 35ns (W12) before issuing Read Status Register */ - /*udelay(1); */ - addr = (FPWV *) info->start[sector]; - *addr = (FPW) INTEL_STATUS; - - start = get_timer(0); - while ((*addr & (FPW) INTEL_FINISHED) != (FPW) INTEL_FINISHED) { - if (get_timer(start) > CFG_FLASH_UNLOCK_TOUT) { - *addr = (FPW) INTEL_RESET; /* restore read mode */ - printf("WSM busy too long, can't get prot status\n"); - return 1; - } - } - - /* issue the Read Identifier Codes command */ - *addr = (FPW) INTEL_READID; - - /* Intel example code uses offset of 4 for 8-bit flash */ - lock_conf_addr = (FPWV *) info->start[sector]; - ret = (lock_conf_addr[INTEL_CFI_LOCK] & (FPW) INTEL_PROTECT) ? 1 : 0; - - /* put flash back in read mode */ - *addr = (FPW) INTEL_RESET; - - return ret; -} - -int flash_erase(flash_info_t * info, int s_first, int s_last) -{ - int flag, prot, sect; - ulong type, start, last; - int rcode = 0; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) - printf("- missing\n"); - else - printf("- no sectors to erase\n"); - return 1; - } - - type = (info->flash_id & FLASH_VENDMASK); - if ((type != FLASH_MAN_INTEL)) { - type = (info->flash_id & FLASH_VENDMASK); - printf("Can't erase unknown flash type %08lx - aborted\n", - info->flash_id); - return 1; - } - - prot = 0; - for (sect = s_first; sect <= s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) - printf("- Warning: %d protected sectors will not be erased!\n", - prot); - else - printf("\n"); - - start = get_timer(0); - last = start; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - - FPWV *addr = (FPWV *) (info->start[sect]); - int min = 0; - - printf("Erasing sector %2d ... ", sect); - - /* arm simple, non interrupt dependent timer */ - start = get_timer(0); - - *addr = (FPW) INTEL_READID; - min = addr[INTEL_CFI_TERB]; - min = 1 << min; /* ms */ - min = (min / info->sector_count) * 1000; - - /* start erase block */ - *addr = (FPW) INTEL_CLEAR; /* clear status register */ - *addr = (FPW) INTEL_ERASE; /* erase setup */ - *addr = (FPW) INTEL_CONFIRM; /* erase confirm */ - - while ((*addr & (FPW) INTEL_FINISHED) != - (FPW) INTEL_FINISHED) { - - if (get_timer(start) > CFG_FLASH_ERASE_TOUT) { - printf("Timeout\n"); - *addr = (FPW) INTEL_SUSERASE; /* suspend erase */ - *addr = (FPW) INTEL_RESET; /* reset to read mode */ - - rcode = 1; - break; - } - } - - *addr = (FPW) INTEL_RESET; /* resest to read mode */ - - printf(" done\n"); - } - } - - return rcode; -} - -int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt) -{ - if (info->flash_id == FLASH_UNKNOWN) - return 4; - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_INTEL: - { - ulong cp, wp; - FPW data; - int i, l, rc, port_width; - - /* get lower word aligned address */ - wp = addr; - port_width = 1; - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i = 0, cp = wp; i < l; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - - for (; i < port_width && cnt > 0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - - for (; cnt == 0 && i < port_width; ++i, ++cp) - data = (data << 8) | (*(uchar *) cp); - - if ((rc = write_data(info, wp, data)) != 0) - return (rc); - - wp += port_width; - } - - /* handle word aligned part */ - while (cnt >= 2) { - data = *((FPW *) src); - - if ((rc = - write_data(info, (ulong) ((FPWV *) wp), - (FPW) data)) != 0) { - return (rc); - } - - src += sizeof(FPW); - wp += sizeof(FPW); - cnt -= sizeof(FPW); - } - - if (cnt == 0) - return ERR_OK; - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i = 0, cp = wp; i < 2 && cnt > 0; ++i, ++cp) { - data = (data >> 8) | (*src++ << 8); - --cnt; - } - for (; i < 2; ++i, ++cp) { - data |= (*(uchar *) cp); - } - - return write_data(info, (ulong) ((FPWV *) wp), - (FPW) data); - - } /* case FLASH_MAN_INTEL */ - - } /* switch */ - - return ERR_OK; -} - -/*----------------------------------------------------------------------- - * Write a word or halfword to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -int write_data(flash_info_t * info, ulong dest, FPW data) -{ - FPWV *addr = (FPWV *) dest; - ulong start; - int flag; - - /* Check if Flash is (sufficiently) erased */ - if ((*addr & data) != data) { - printf("not erased at %08lx (%lx)\n", (ulong) addr, - (ulong) * addr); - return (2); - } - - /* Disable interrupts which might cause a timeout here */ - flag = (int)disable_interrupts(); - - *addr = (FPW) INTEL_CLEAR; - *addr = (FPW) INTEL_RESET; - - *addr = (FPW) INTEL_WRSETUP; /* write setup */ - *addr = data; - - /* arm simple, non interrupt dependent timer */ - start = get_timer(0); - - /* wait while polling the status register */ - while ((*addr & (FPW) INTEL_OK) != (FPW) INTEL_OK) { - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { - *addr = (FPW) INTEL_SUSERASE; /* suspend mode */ - *addr = (FPW) INTEL_CLEAR; /* clear status */ - *addr = (FPW) INTEL_RESET; /* reset */ - return (1); - } - } - - *addr = (FPW) INTEL_CLEAR; /* clear status */ - *addr = (FPW) INTEL_RESET; /* restore read mode */ - - return (0); -} - -#ifdef CFG_FLASH_PROTECTION -/*----------------------------------------------------------------------- - */ -int flash_real_protect(flash_info_t * info, long sector, int prot) -{ - int rcode = 0; /* assume success */ - FPWV *addr; /* address of sector */ - FPW value; - - addr = (FPWV *) (info->start[sector]); - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_28F160C3B: - case FLASH_28F160C3T: - case FLASH_28F320C3B: - case FLASH_28F320C3T: - case FLASH_28F640C3B: - case FLASH_28F640C3T: - *addr = (FPW) INTEL_RESET; /* make sure in read mode */ - *addr = (FPW) INTEL_LOCKBIT; /* lock command setup */ - - if (prot) - *addr = (FPW) INTEL_PROTECT; /* lock sector */ - else - *addr = (FPW) INTEL_CONFIRM; /* unlock sector */ - - /* now see if it really is locked/unlocked as requested */ - *addr = (FPW) INTEL_READID; - - /* read sector protection at sector address, (A7 .. A0) = 0x02. - * D0 = 1 for each device if protected. - * If at least one device is protected the sector is marked - * protected, but return failure. Mixed protected and - * unprotected devices within a sector should never happen. - */ - value = addr[2] & (FPW) INTEL_PROTECT; - if (value == 0) - info->protect[sector] = 0; - else if (value == (FPW) INTEL_PROTECT) - info->protect[sector] = 1; - else { - /* error, mixed protected and unprotected */ - rcode = 1; - info->protect[sector] = 1; - } - if (info->protect[sector] != prot) - rcode = 1; /* failed to protect/unprotect as requested */ - - /* reload all protection bits from hardware for now */ - flash_sync_real_protect(info); - break; - - default: - /* no hardware protect that we support */ - info->protect[sector] = prot; - break; - } - - return rcode; -} -#endif /* CFG_FLASH_PROTECTION */ -#endif /* CFG_FLASH_CFI */ From 427c814104560e29bda14955c67703245aaaa5b4 Mon Sep 17 00:00:00 2001 From: TsiChungLiew Date: Thu, 5 Jul 2007 22:54:42 -0500 Subject: [PATCH 019/259] Removed MII functions and replaced immap_5329.h and m5329.h with immap.h. The removed MII routines will be placed in mii.c. Signed-off-by: TsiChungLiew --- board/freescale/m5329evb/m5329evb.c | 285 +--------------------------- 1 file changed, 3 insertions(+), 282 deletions(-) diff --git a/board/freescale/m5329evb/m5329evb.c b/board/freescale/m5329evb/m5329evb.c index 4ccea30d6..07a02c272 100644 --- a/board/freescale/m5329evb/m5329evb.c +++ b/board/freescale/m5329evb/m5329evb.c @@ -24,13 +24,9 @@ * MA 02111-1307 USA */ -#include -#include -#include -#include - #include -#include +#include +#include DECLARE_GLOBAL_DATA_PTR; @@ -97,280 +93,5 @@ void sync(void) /* This sync function is PowerPC intruction, coldfire does not have this instruction. Dummy function */ } -#endif +#endif /* CFG_FLASH_CFI */ -#if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(CONFIG_NET_MULTI) -#undef MII_DEBUG -#undef ET_DEBUG - -int fecpin_setclear(struct eth_device *dev, int setclear) -{ - volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; - - if (setclear) { - gpio->par_fec |= GPIO_PAR_FEC_7W_FEC | GPIO_PAR_FEC_MII_FEC; - gpio->par_feci2c |= - GPIO_PAR_FECI2C_MDC_EMDC | GPIO_PAR_FECI2C_MDIO_EMDIO; - } else { - gpio->par_fec &= ~(GPIO_PAR_FEC_7W_FEC | GPIO_PAR_FEC_MII_FEC); - gpio->par_feci2c &= - ~(GPIO_PAR_FECI2C_MDC_EMDC | GPIO_PAR_FECI2C_MDIO_EMDIO); - } - return 0; -} - -#if defined(CFG_DISCOVER_PHY) || (CONFIG_COMMANDS & CFG_CMD_MII) -#include - -/* Make MII read/write commands for the FEC. */ -#define mk_mii_read(ADDR, REG) (0x60020000 | ((ADDR << 23) | \ - (REG & 0x1f) << 18)) - -#define mk_mii_write(ADDR, REG, VAL) (0x50020000 | ((ADDR << 23) | \ - (REG & 0x1f) << 18) | \ - (VAL & 0xffff)) - -/* PHY identification */ -#define PHY_ID_LXT970 0x78100000 /* LXT970 */ -#define PHY_ID_LXT971 0x001378e0 /* LXT971 and 972 */ -#define PHY_ID_82555 0x02a80150 /* Intel 82555 */ -#define PHY_ID_QS6612 0x01814400 /* QS6612 */ -#define PHY_ID_AMD79C784 0x00225610 /* AMD 79C784 */ -#define PHY_ID_LSI80225 0x0016f870 /* LSI 80225 */ -#define PHY_ID_LSI80225B 0x0016f880 /* LSI 80225/B */ -#define PHY_ID_DP83848VV 0x20005C90 /* National 83848 */ -#define PHY_ID_DP83849 0x20005CA2 /* National 82849 */ - -#define STR_ID_LXT970 "LXT970" -#define STR_ID_LXT971 "LXT971" -#define STR_ID_82555 "Intel82555" -#define STR_ID_QS6612 "QS6612" -#define STR_ID_AMD79C784 "AMD79C784" -#define STR_ID_LSI80225 "LSI80225" -#define STR_ID_LSI80225B "LSI80225/B" -#define STR_ID_DP83848VV "N83848" -#define STR_ID_DP83849 "N83849" - -/**************************************************************************** - * mii_init -- Initialize the MII for MII command without ethernet - * This function is a subset of eth_init - **************************************************************************** - */ -void mii_reset(struct fec_info_s *info) -{ - volatile fec_t *fecp = (fec_t *) (info->miibase); - int i; - - fecp->ecr = FEC_ECR_RESET; - for (i = 0; (fecp->ecr & FEC_ECR_RESET) && (i < FEC_RESET_DELAY); ++i) { - udelay(1); - } - if (i == FEC_RESET_DELAY) { - printf("FEC_RESET_DELAY timeout\n"); - } -} - -/* send command to phy using mii, wait for result */ -uint mii_send(uint mii_cmd) -{ - struct fec_info_s *info; - struct eth_device *dev; - volatile fec_t *ep; - uint mii_reply; - int j = 0; - - /* retrieve from register structure */ - dev = eth_get_dev(); - info = dev->priv; - - ep = (fec_t *) info->miibase; - - ep->mmfr = mii_cmd; /* command to phy */ - - /* wait for mii complete */ - while (!(ep->eir & FEC_EIR_MII) && (j < MCFFEC_TOUT_LOOP)) { - udelay(1); - j++; - } - if (j >= MCFFEC_TOUT_LOOP) { - printf("MII not complete\n"); - return -1; - } - - mii_reply = ep->mmfr; /* result from phy */ - ep->eir = FEC_EIR_MII; /* clear MII complete */ -#ifdef ET_DEBUG - printf("%s[%d] %s: sent=0x%8.8x, reply=0x%8.8x\n", - __FILE__, __LINE__, __FUNCTION__, mii_cmd, mii_reply); -#endif - - return (mii_reply & 0xffff); /* data read from phy */ -} -#endif /* CFG_DISCOVER_PHY || (CONFIG_COMMANDS & CFG_CMD_MII) */ - -#if defined(CFG_DISCOVER_PHY) -int mii_discover_phy(struct eth_device *dev) -{ -#define MAX_PHY_PASSES 11 - struct fec_info_s *info = dev->priv; - int phyaddr, pass; - uint phyno, phytype; - - if (info->phyname_init) - return info->phy_addr; - - phyaddr = -1; /* didn't find a PHY yet */ - for (pass = 1; pass <= MAX_PHY_PASSES && phyaddr < 0; ++pass) { - if (pass > 1) { - /* PHY may need more time to recover from reset. - * The LXT970 needs 50ms typical, no maximum is - * specified, so wait 10ms before try again. - * With 11 passes this gives it 100ms to wake up. - */ - udelay(10000); /* wait 10ms */ - } - - for (phyno = 0; phyno < 32 && phyaddr < 0; ++phyno) { - - phytype = mii_send(mk_mii_read(phyno, PHY_PHYIDR1)); -#ifdef ET_DEBUG - printf("PHY type 0x%x pass %d type\n", phytype, pass); -#endif - if (phytype != 0xffff) { - phyaddr = phyno; - phytype <<= 16; - phytype |= - mii_send(mk_mii_read(phyno, PHY_PHYIDR2)); - - switch (phytype & 0xffffffff) { - case PHY_ID_DP83848VV: - strcpy(info->phy_name, - STR_ID_DP83848VV); - info->phyname_init = 1; - break; - default: - strcpy(info->phy_name, "unknown"); - info->phyname_init = 1; - break; - } - -#ifdef ET_DEBUG - printf("PHY @ 0x%x pass %d type ", phyno, pass); - switch (phytype & 0xffffffff) { - case PHY_ID_DP83848VV: - printf(STR_ID_DP83848VV); - break; - default: - printf("0x%08x\n", phytype); - break; - } -#endif - } - } - } - if (phyaddr < 0) - printf("No PHY device found.\n"); - - return phyaddr; -} -#endif /* CFG_DISCOVER_PHY */ - -void mii_init(void) -{ - volatile fec_t *fecp; - struct fec_info_s *info; - struct eth_device *dev; - int miispd = 0, i = 0; - u16 autoneg = 0; - - /* retrieve from register structure */ - dev = eth_get_dev(); - info = dev->priv; - - fecp = (fec_t *) info->miibase; - - fecpin_setclear(dev, 1); - - mii_reset(info); - - /* We use strictly polling mode only */ - fecp->eimr = 0; - - /* Clear any pending interrupt */ - fecp->eir = 0xffffffff; - - /* Set MII speed */ - miispd = (gd->bus_clk / 1000000) / 5; - fecp->mscr = miispd << 1; - - info->phy_addr = mii_discover_phy(dev); - -#define AUTONEGLINK (PHY_BMSR_AUTN_COMP | PHY_BMSR_LS) - while (i < MCFFEC_TOUT_LOOP) { - autoneg = 0; - miiphy_read(dev->name, info->phy_addr, PHY_BMSR, &autoneg); - i++; - - if ((autoneg & AUTONEGLINK) == AUTONEGLINK) - break; - - udelay(500); - } - if (i >= MCFFEC_TOUT_LOOP) { - printf("Auto Negotiation not complete\n"); - } - - /* adapt to the half/full speed settings */ - info->dup_spd = miiphy_duplex(dev->name, info->phy_addr) << 16; - info->dup_spd |= miiphy_speed(dev->name, info->phy_addr); -} - -/***************************************************************************** - * Read and write a MII PHY register, routines used by MII Utilities - * - * FIXME: These routines are expected to return 0 on success, but mii_send - * does _not_ return an error code. Maybe 0xFFFF means error, i.e. - * no PHY connected... - * For now always return 0. - * FIXME: These routines only work after calling eth_init() at least once! - * Otherwise they hang in mii_send() !!! Sorry! - *****************************************************************************/ - -int mcffec_miiphy_read(char *devname, unsigned char addr, - unsigned char reg, unsigned short *value) -{ - short rdreg; /* register working value */ - -#ifdef MII_DEBUG - printf("miiphy_read(0x%x) @ 0x%x = ", reg, addr); -#endif - rdreg = mii_send(mk_mii_read(addr, reg)); - - *value = rdreg; - -#ifdef MII_DEBUG - printf("0x%04x\n", *value); -#endif - - return 0; -} - -int mcffec_miiphy_write(char *devname, unsigned char addr, - unsigned char reg, unsigned short value) -{ - short rdreg; /* register working value */ - -#ifdef MII_DEBUG - printf("miiphy_write(0x%x) @ 0x%x = ", reg, addr); -#endif - - rdreg = mii_send(mk_mii_write(addr, reg, value)); - -#ifdef MII_DEBUG - printf("0x%04x\n", value); -#endif - - return 0; -} - -#endif /* CFG_CMD_NET, FEC_ENET & NET_MULTI */ From c5ded275d839e4ff79f41718d50a835d989f57bc Mon Sep 17 00:00:00 2001 From: TsiChungLiew Date: Thu, 5 Jul 2007 22:56:19 -0500 Subject: [PATCH 020/259] MII functions calls. Signed-off-by: TsiChungLiew --- board/freescale/m5329evb/mii.c | 304 +++++++++++++++++++++++++++++++++ 1 file changed, 304 insertions(+) create mode 100644 board/freescale/m5329evb/mii.c diff --git a/board/freescale/m5329evb/mii.c b/board/freescale/m5329evb/mii.c new file mode 100644 index 000000000..691b14459 --- /dev/null +++ b/board/freescale/m5329evb/mii.c @@ -0,0 +1,304 @@ +/* + * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(CONFIG_NET_MULTI) +#undef MII_DEBUG +#undef ET_DEBUG + +int fecpin_setclear(struct eth_device *dev, int setclear) +{ + volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; + + if (setclear) { + gpio->par_fec |= GPIO_PAR_FEC_7W_FEC | GPIO_PAR_FEC_MII_FEC; + gpio->par_feci2c |= + GPIO_PAR_FECI2C_MDC_EMDC | GPIO_PAR_FECI2C_MDIO_EMDIO; + } else { + gpio->par_fec &= ~(GPIO_PAR_FEC_7W_FEC | GPIO_PAR_FEC_MII_FEC); + gpio->par_feci2c &= + ~(GPIO_PAR_FECI2C_MDC_EMDC | GPIO_PAR_FECI2C_MDIO_EMDIO); + } + return 0; +} + +#if defined(CFG_DISCOVER_PHY) || (CONFIG_COMMANDS & CFG_CMD_MII) +#include + +/* Make MII read/write commands for the FEC. */ +#define mk_mii_read(ADDR, REG) (0x60020000 | ((ADDR << 23) | (REG & 0x1f) << 18)) + +#define mk_mii_write(ADDR, REG, VAL) (0x50020000 | ((ADDR << 23) | (REG & 0x1f) << 18) | (VAL & 0xffff)) + +/* PHY identification */ +#define PHY_ID_LXT970 0x78100000 /* LXT970 */ +#define PHY_ID_LXT971 0x001378e0 /* LXT971 and 972 */ +#define PHY_ID_82555 0x02a80150 /* Intel 82555 */ +#define PHY_ID_QS6612 0x01814400 /* QS6612 */ +#define PHY_ID_AMD79C784 0x00225610 /* AMD 79C784 */ +#define PHY_ID_LSI80225 0x0016f870 /* LSI 80225 */ +#define PHY_ID_LSI80225B 0x0016f880 /* LSI 80225/B */ +#define PHY_ID_DP83848VV 0x20005C90 /* National 83848 */ +#define PHY_ID_DP83849 0x20005CA2 /* National 82849 */ + +#define STR_ID_LXT970 "LXT970" +#define STR_ID_LXT971 "LXT971" +#define STR_ID_82555 "Intel82555" +#define STR_ID_QS6612 "QS6612" +#define STR_ID_AMD79C784 "AMD79C784" +#define STR_ID_LSI80225 "LSI80225" +#define STR_ID_LSI80225B "LSI80225/B" +#define STR_ID_DP83848VV "N83848" +#define STR_ID_DP83849 "N83849" + +/**************************************************************************** + * mii_init -- Initialize the MII for MII command without ethernet + * This function is a subset of eth_init + **************************************************************************** + */ +void mii_reset(struct fec_info_s *info) +{ + volatile fec_t *fecp = (fec_t *) (info->miibase); + int i; + + fecp->ecr = FEC_ECR_RESET; + for (i = 0; (fecp->ecr & FEC_ECR_RESET) && (i < FEC_RESET_DELAY); ++i) { + udelay(1); + } + if (i == FEC_RESET_DELAY) { + printf("FEC_RESET_DELAY timeout\n"); + } +} + +/* send command to phy using mii, wait for result */ +uint mii_send(uint mii_cmd) +{ + struct fec_info_s *info; + struct eth_device *dev; + volatile fec_t *ep; + uint mii_reply; + int j = 0; + + /* retrieve from register structure */ + dev = eth_get_dev(); + info = dev->priv; + + ep = (fec_t *) info->miibase; + + ep->mmfr = mii_cmd; /* command to phy */ + + /* wait for mii complete */ + while (!(ep->eir & FEC_EIR_MII) && (j < MCFFEC_TOUT_LOOP)) { + udelay(1); + j++; + } + if (j >= MCFFEC_TOUT_LOOP) { + printf("MII not complete\n"); + return -1; + } + + mii_reply = ep->mmfr; /* result from phy */ + ep->eir = FEC_EIR_MII; /* clear MII complete */ +#ifdef ET_DEBUG + printf("%s[%d] %s: sent=0x%8.8x, reply=0x%8.8x\n", + __FILE__, __LINE__, __FUNCTION__, mii_cmd, mii_reply); +#endif + + return (mii_reply & 0xffff); /* data read from phy */ +} +#endif /* CFG_DISCOVER_PHY || (CONFIG_COMMANDS & CFG_CMD_MII) */ + +#if defined(CFG_DISCOVER_PHY) +int mii_discover_phy(struct eth_device *dev) +{ +#define MAX_PHY_PASSES 11 + struct fec_info_s *info = dev->priv; + int phyaddr, pass; + uint phyno, phytype; + + if (info->phyname_init) + return info->phy_addr; + + phyaddr = -1; /* didn't find a PHY yet */ + for (pass = 1; pass <= MAX_PHY_PASSES && phyaddr < 0; ++pass) { + if (pass > 1) { + /* PHY may need more time to recover from reset. + * The LXT970 needs 50ms typical, no maximum is + * specified, so wait 10ms before try again. + * With 11 passes this gives it 100ms to wake up. + */ + udelay(10000); /* wait 10ms */ + } + + for (phyno = 0; phyno < 32 && phyaddr < 0; ++phyno) { + + phytype = mii_send(mk_mii_read(phyno, PHY_PHYIDR1)); +#ifdef ET_DEBUG + printf("PHY type 0x%x pass %d type\n", phytype, pass); +#endif + if (phytype != 0xffff) { + phyaddr = phyno; + phytype <<= 16; + phytype |= + mii_send(mk_mii_read(phyno, PHY_PHYIDR2)); + + switch (phytype & 0xffffffff) { + case PHY_ID_DP83848VV: + strcpy(info->phy_name, + STR_ID_DP83848VV); + info->phyname_init = 1; + break; + default: + strcpy(info->phy_name, "unknown"); + info->phyname_init = 1; + break; + } + +#ifdef ET_DEBUG + printf("PHY @ 0x%x pass %d type ", phyno, pass); + switch (phytype & 0xffffffff) { + case PHY_ID_DP83848VV: + printf(STR_ID_DP83848VV); + break; + default: + printf("0x%08x\n", phytype); + break; + } +#endif + } + } + } + if (phyaddr < 0) + printf("No PHY device found.\n"); + + return phyaddr; +} +#endif /* CFG_DISCOVER_PHY */ + +void mii_init(void) +{ + volatile fec_t *fecp; + struct fec_info_s *info; + struct eth_device *dev; + int miispd = 0, i = 0; + u16 autoneg = 0; + + /* retrieve from register structure */ + dev = eth_get_dev(); + info = dev->priv; + + fecp = (fec_t *) info->miibase; + + fecpin_setclear(dev, 1); + + mii_reset(info); + + /* We use strictly polling mode only */ + fecp->eimr = 0; + + /* Clear any pending interrupt */ + fecp->eir = 0xffffffff; + + /* Set MII speed */ + miispd = (gd->bus_clk / 1000000) / 5; + fecp->mscr = miispd << 1; + + info->phy_addr = mii_discover_phy(dev); + +#define AUTONEGLINK (PHY_BMSR_AUTN_COMP | PHY_BMSR_LS) + while (i < MCFFEC_TOUT_LOOP) { + autoneg = 0; + miiphy_read(dev->name, info->phy_addr, PHY_BMSR, &autoneg); + i++; + + if ((autoneg & AUTONEGLINK) == AUTONEGLINK) + break; + + udelay(500); + } + if (i >= MCFFEC_TOUT_LOOP) { + printf("Auto Negotiation not complete\n"); + } + + /* adapt to the half/full speed settings */ + info->dup_spd = miiphy_duplex(dev->name, info->phy_addr) << 16; + info->dup_spd |= miiphy_speed(dev->name, info->phy_addr); +} + +/***************************************************************************** + * Read and write a MII PHY register, routines used by MII Utilities + * + * FIXME: These routines are expected to return 0 on success, but mii_send + * does _not_ return an error code. Maybe 0xFFFF means error, i.e. + * no PHY connected... + * For now always return 0. + * FIXME: These routines only work after calling eth_init() at least once! + * Otherwise they hang in mii_send() !!! Sorry! + *****************************************************************************/ + +int mcffec_miiphy_read(char *devname, unsigned char addr, unsigned char reg, + unsigned short *value) +{ + short rdreg; /* register working value */ + +#ifdef MII_DEBUG + printf("miiphy_read(0x%x) @ 0x%x = ", reg, addr); +#endif + rdreg = mii_send(mk_mii_read(addr, reg)); + + *value = rdreg; + +#ifdef MII_DEBUG + printf("0x%04x\n", *value); +#endif + + return 0; +} + +int mcffec_miiphy_write(char *devname, unsigned char addr, unsigned char reg, + unsigned short value) +{ + short rdreg; /* register working value */ + +#ifdef MII_DEBUG + printf("miiphy_write(0x%x) @ 0x%x = ", reg, addr); +#endif + + rdreg = mii_send(mk_mii_write(addr, reg, value)); + +#ifdef MII_DEBUG + printf("0x%04x\n", value); +#endif + + return 0; +} + +#endif /* CFG_CMD_NET, FEC_ENET & NET_MULTI */ From 3b635492c95bd0d6e08f93f699821cba1f602a64 Mon Sep 17 00:00:00 2001 From: TsiChungLiew Date: Thu, 5 Jul 2007 22:57:46 -0500 Subject: [PATCH 021/259] Update for flash.o and mii.o Removed flash.o and added mii.o Signed-off-by: TsiChungLiew --- board/freescale/m5329evb/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/freescale/m5329evb/Makefile b/board/freescale/m5329evb/Makefile index f94ee9d13..74c252869 100644 --- a/board/freescale/m5329evb/Makefile +++ b/board/freescale/m5329evb/Makefile @@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a -COBJS = $(BOARD).o flash.o +COBJS = $(BOARD).o mii.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) From 7a17e759c7a8b58e910daf54df611e94fc8ca074 Mon Sep 17 00:00:00 2001 From: TsiChungLiew Date: Thu, 5 Jul 2007 23:01:22 -0500 Subject: [PATCH 022/259] Update header file and removed interrupt_init() Replace immap_5329.h and m5329.h with immap.h. Removed interrupt_init() and placed it in interrupts.c Signed-off-by: TsiChungLiew --- cpu/mcf532x/cpu.c | 19 ++----------------- 1 file changed, 2 insertions(+), 17 deletions(-) diff --git a/cpu/mcf532x/cpu.c b/cpu/mcf532x/cpu.c index 071c50304..520f5d693 100644 --- a/cpu/mcf532x/cpu.c +++ b/cpu/mcf532x/cpu.c @@ -29,8 +29,7 @@ #include #include -#include -#include +#include int do_reset(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char *argv[]) { @@ -117,18 +116,4 @@ int watchdog_init(void) return (0); } -#endif /* #ifdef CONFIG_WATCHDOG */ - -#ifdef CONFIG_MCFINTC -int interrupt_init(void) -{ - volatile int0_t *intp = (int0_t *) (CFG_INTR_BASE); - - /* Make sure all interrupts are disabled */ - intp->imrh0 |= 0xFFFFFFFF; - intp->imrl0 |= 0xFFFFFFFF; - - enable_interrupts(); - return 0; -} -#endif /* CONFIG_MCFINTC */ +#endif /* CONFIG_WATCHDOG */ From 84a015b52ec820a5ae173717d78516de731c89c2 Mon Sep 17 00:00:00 2001 From: TsiChungLiew Date: Thu, 5 Jul 2007 23:03:28 -0500 Subject: [PATCH 023/259] Update header file and enable icache Replaced immap_5329.h and m5329.h with immap.h. Enabled icache_enable() in cpu_init_r(). Signed-off-by: TsiChungLiew --- cpu/mcf532x/cpu_init.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/cpu/mcf532x/cpu_init.c b/cpu/mcf532x/cpu_init.c index 6319658c0..b056fbe31 100644 --- a/cpu/mcf532x/cpu_init.c +++ b/cpu/mcf532x/cpu_init.c @@ -3,7 +3,7 @@ * (C) Copyright 2000-2003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * - * (C) Copyright 2007 + * (C) Copyright 2007 Freescale Semiconductor, Inc. * TsiChung Liew (Tsi-Chung.Liew@freescale.com) * * See file CREDITS for list of people who contributed to this @@ -28,8 +28,7 @@ #include #include -#include -#include +#include /* * Breath some life into the CPU... @@ -121,6 +120,6 @@ void cpu_init_f(void) */ int cpu_init_r(void) { - /*icache_enable(); */ + icache_enable(); return (0); } From b9bf3de377b2bae70c983c9b97feae914999e735 Mon Sep 17 00:00:00 2001 From: TsiChungLiew Date: Thu, 5 Jul 2007 23:05:31 -0500 Subject: [PATCH 024/259] Update header file and some clean up Replaced immap_5329.h and m5329.h with immap.h. Removed whitespaces. Signed-off-by: TsiChungLiew --- cpu/mcf532x/speed.c | 30 ++++++++++++------------------ 1 file changed, 12 insertions(+), 18 deletions(-) diff --git a/cpu/mcf532x/speed.c b/cpu/mcf532x/speed.c index c4ba7ec66..cf72609b4 100644 --- a/cpu/mcf532x/speed.c +++ b/cpu/mcf532x/speed.c @@ -28,23 +28,22 @@ #include #include -#include -#include +#include /* PLL min/max specifications */ -#define MAX_FVCO 500000 /* KHz */ -#define MAX_FSYS 80000 /* KHz */ -#define MIN_FSYS 58333 /* KHz */ -#define FREF 16000 /* KHz */ -#define MAX_MFD 135 /* Multiplier */ -#define MIN_MFD 88 /* Multiplier */ -#define BUSDIV 6 /* Divider */ +#define MAX_FVCO 500000 /* KHz */ +#define MAX_FSYS 80000 /* KHz */ +#define MIN_FSYS 58333 /* KHz */ +#define FREF 16000 /* KHz */ +#define MAX_MFD 135 /* Multiplier */ +#define MIN_MFD 88 /* Multiplier */ +#define BUSDIV 6 /* Divider */ /* * Low Power Divider specifications */ -#define MIN_LPD (1 << 0) /* Divider (not encoded) */ -#define MAX_LPD (1 << 15) /* Divider (not encoded) */ -#define DEFAULT_LPD (1 << 1) /* Divider (not encoded) */ +#define MIN_LPD (1 << 0) /* Divider (not encoded) */ +#define MAX_LPD (1 << 15) /* Divider (not encoded) */ +#define DEFAULT_LPD (1 << 1) /* Divider (not encoded) */ /* * Get the value of the current system clock @@ -174,9 +173,6 @@ int clock_pll(int fsys, int flags) * If it has then the SDRAM needs to be put into self refresh * mode before reprogramming the PLL. */ - /* Put SDRAM into self refresh mode */ -/* if (MCF_SDRAMC_SDCR & MCF_SDRAMC_SDCR_REF) - MCF_SDRAMC_SDCR &= ~MCF_SDRAMC_SDCR_CKE;*/ /* * Initialize the PLL to generate the new system clock frequency. @@ -197,12 +193,10 @@ int clock_pll(int fsys, int flags) /* * Return the SDRAM to normal operation if it is in use. */ - /* Exit self refresh mode */ -/* if (MCF_SDRAMC_SDCR & MCF_SDRAMC_SDCR_REF) - MCF_SDRAMC_SDCR |= MCF_SDRAMC_SDCR_CKE;*/ /* software workaround for SDRAM opeartion after exiting LIMP mode errata */ *sdram_workaround = CFG_SDRAM_BASE; + /* wait for DQS logic to relock */ for (i = 0; i < 0x200; i++) ; From ddd104f1ed655eda50c06ba636237a83ed943f34 Mon Sep 17 00:00:00 2001 From: TsiChungLiew Date: Thu, 5 Jul 2007 23:06:55 -0500 Subject: [PATCH 025/259] Enable Icache Signed-off-by: TsiChungLiew --- cpu/mcf532x/start.S | 75 ++++++++++++++++++++++----------------------- 1 file changed, 37 insertions(+), 38 deletions(-) diff --git a/cpu/mcf532x/start.S b/cpu/mcf532x/start.S index d36d076cf..acd34941a 100644 --- a/cpu/mcf532x/start.S +++ b/cpu/mcf532x/start.S @@ -31,7 +31,6 @@ #define _START _start #define _FAULT _fault - #define SAVE_ALL \ move.w #0x2700,%sr; /* disable intrs */ \ subl #60,%sp; /* space for 15 regs */ \ @@ -42,7 +41,6 @@ addl #60,%sp; /* space for 15 regs */ \ rte; - .text /* * Vector table. This is used for initial platform startup. @@ -50,35 +48,35 @@ */ _vectors: -INITSP: .long 0x00000000 /* Initial SP */ -INITPC: .long _START /* Initial PC */ -vector02: .long _FAULT /* Access Error */ -vector03: .long _FAULT /* Address Error */ -vector04: .long _FAULT /* Illegal Instruction */ -vector05: .long _FAULT /* Reserved */ -vector06: .long _FAULT /* Reserved */ -vector07: .long _FAULT /* Reserved */ -vector08: .long _FAULT /* Privilege Violation */ -vector09: .long _FAULT /* Trace */ -vector0A: .long _FAULT /* Unimplemented A-Line */ -vector0B: .long _FAULT /* Unimplemented F-Line */ -vector0C: .long _FAULT /* Debug Interrupt */ -vector0D: .long _FAULT /* Reserved */ -vector0E: .long _FAULT /* Format Error */ -vector0F: .long _FAULT /* Unitialized Int. */ +INITSP: .long 0x00000000 /* Initial SP */ +INITPC: .long _START /* Initial PC */ +vector02: .long _FAULT /* Access Error */ +vector03: .long _FAULT /* Address Error */ +vector04: .long _FAULT /* Illegal Instruction */ +vector05: .long _FAULT /* Reserved */ +vector06: .long _FAULT /* Reserved */ +vector07: .long _FAULT /* Reserved */ +vector08: .long _FAULT /* Privilege Violation */ +vector09: .long _FAULT /* Trace */ +vector0A: .long _FAULT /* Unimplemented A-Line */ +vector0B: .long _FAULT /* Unimplemented F-Line */ +vector0C: .long _FAULT /* Debug Interrupt */ +vector0D: .long _FAULT /* Reserved */ +vector0E: .long _FAULT /* Format Error */ +vector0F: .long _FAULT /* Unitialized Int. */ -/* Reserved */ +/* Reserved */ vector10_17: .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -vector18: .long _FAULT /* Spurious Interrupt */ -vector19: .long _FAULT /* Autovector Level 1 */ -vector1A: .long _FAULT /* Autovector Level 2 */ -vector1B: .long _FAULT /* Autovector Level 3 */ -vector1C: .long _FAULT /* Autovector Level 4 */ -vector1D: .long _FAULT /* Autovector Level 5 */ -vector1E: .long _FAULT /* Autovector Level 6 */ -vector1F: .long _FAULT /* Autovector Level 7 */ +vector18: .long _FAULT /* Spurious Interrupt */ +vector19: .long _FAULT /* Autovector Level 1 */ +vector1A: .long _FAULT /* Autovector Level 2 */ +vector1B: .long _FAULT /* Autovector Level 3 */ +vector1C: .long _FAULT /* Autovector Level 4 */ +vector1D: .long _FAULT /* Autovector Level 5 */ +vector1E: .long _FAULT /* Autovector Level 6 */ +vector1F: .long _FAULT /* Autovector Level 7 */ /* TRAP #0 - #15 */ vector20_2F: @@ -126,9 +124,9 @@ vector192_255: _start: nop nop - move.w #0x2700,%sr /* Mask off Interrupt */ + move.w #0x2700,%sr /* Mask off Interrupt */ - /* Set vector base register at the beginning of the Flash */ + /* Set vector base register at the beginning of the Flash */ move.l #CFG_FLASH_BASE, %d0 movec %d0, %VBR @@ -149,14 +147,15 @@ _start: move.l %d0, (%a1) move.l %d0, (%a2) - /* set stackpointer to end of internal ram to get some stackspace for the first c-code */ + /* set stackpointer to end of internal ram to get some stackspace for the + first c-code */ move.l #(CFG_INIT_RAM_ADDR + CFG_INIT_SP_OFFSET), %sp clr.l %sp@- - move.l #__got_start, %a5 /* put relocation table address to a5 */ + move.l #__got_start, %a5 /* put relocation table address to a5 */ - bsr cpu_init_f /* run low-level CPU init code (from flash) */ - bsr board_init_f /* run low-level board init code (from flash) */ + bsr cpu_init_f /* run low-level CPU init code (from flash) */ + bsr board_init_f /* run low-level board init code (from flash) */ /* board_init_f() does not return */ @@ -269,14 +268,14 @@ _int_handler: icache_enable: move.l #0x01000000, %d0 /* Invalidate cache cmd */ movec %d0, %CACR /* Invalidate cache */ - move.l #(CFG_SDRAM_BASE + 0xc000), %d0 /* Setup cache mask */ + move.l #(CFG_SDRAM_BASE + 0xc000), %d0 /* Setup cache mask */ movec %d0, %ACR0 /* Enable cache */ - move.l #(CFG_CS0_BASE + 0xc000), %d0 /* Setup cache mask */ + move.l #(CFG_CS0_BASE + 0x0000), %d0 /* Setup cache mask */ movec %d0, %ACR1 /* Enable cache */ - /*move.l #0x81000100, %d0*/ /* Setup cache mask */ - move.l #0x81000100, %d0 /* Setup cache mask */ + move.l #0x80000200, %d0 /* Setup cache mask */ movec %d0, %CACR /* Enable cache */ + nop move.l #(CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END-8), %a1 moveq #1, %d0 @@ -304,7 +303,7 @@ icache_status: .globl icache_invalid icache_invalid: - move.l #0x00000100, %d0 /* Setup cache mask */ + move.l #0x01000000, %d0 /* Setup cache mask */ movec %d0, %CACR /* Enable cache */ rts From 2e3f25ae9082daa9f5d181db45dfbc2e52ce0f97 Mon Sep 17 00:00:00 2001 From: TsiChungLiew Date: Thu, 5 Jul 2007 23:10:40 -0500 Subject: [PATCH 026/259] Create interrupts.c and modify Makefile interrupt_init() and dtimer_intr_setup() are placed in interrupts.c. Added interrupts.o to Makefile Signed-off-by: TsiChungLiew --- cpu/mcf532x/Makefile | 2 +- cpu/mcf532x/interrupts.c | 49 ++++++++++++++++++++++++++++++++++++++++ 2 files changed, 50 insertions(+), 1 deletion(-) create mode 100644 cpu/mcf532x/interrupts.c diff --git a/cpu/mcf532x/Makefile b/cpu/mcf532x/Makefile index 452848d32..6790d90f2 100644 --- a/cpu/mcf532x/Makefile +++ b/cpu/mcf532x/Makefile @@ -28,7 +28,7 @@ include $(TOPDIR)/config.mk LIB = lib$(CPU).a START = -COBJS = cpu.o speed.o cpu_init.o +COBJS = cpu.o speed.o cpu_init.o interrupts.o SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) diff --git a/cpu/mcf532x/interrupts.c b/cpu/mcf532x/interrupts.c new file mode 100644 index 000000000..ff50d7ddf --- /dev/null +++ b/cpu/mcf532x/interrupts.c @@ -0,0 +1,49 @@ +/* + * + * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* CPU specific interrupt routine */ +#include +#include + +int interrupt_init(void) +{ + volatile int0_t *intp = (int0_t *) (CFG_INTR_BASE); + + /* Make sure all interrupts are disabled */ + intp->imrh0 |= 0xFFFFFFFF; + intp->imrl0 |= 0xFFFFFFFF; + + enable_interrupts(); + return 0; +} + +#if defined(CONFIG_MCFTMR) +void dtimer_intr_setup(void) +{ + volatile int0_t *intp = (int0_t *) (CFG_INTR_BASE); + + intp->icr0[CFG_TMRINTR_NO] = CFG_TMRINTR_PRI; + intp->imrh0 &= ~CFG_TMRINTR_MASK; +} +#endif From f2208fbc2eb9de3f4285bfaa021c6ebae16c9b0e Mon Sep 17 00:00:00 2001 From: TsiChungLiew Date: Thu, 5 Jul 2007 23:13:58 -0500 Subject: [PATCH 027/259] Header file update, clean up and cache handling Replaced immap_5329.h and m5329.h with immap.h. Included cache_invalid. Signed-off-by: TsiChungLiew --- drivers/net/mcffec.c | 66 ++++++++++++++++++++++---------------------- 1 file changed, 33 insertions(+), 33 deletions(-) diff --git a/drivers/net/mcffec.c b/drivers/net/mcffec.c index d1c84caee..609210de1 100644 --- a/drivers/net/mcffec.c +++ b/drivers/net/mcffec.c @@ -2,7 +2,7 @@ * (C) Copyright 2000-2004 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * - * (C) Copyright 2007 + * (C) Copyright 2007 Freescale Semiconductor, Inc. * TsiChung Liew (Tsi-Chung.Liew@freescale.com) * * See file CREDITS for list of people who contributed to this @@ -28,8 +28,7 @@ #include #include -#include -#include +#include #include #include @@ -41,17 +40,8 @@ #undef MII_DEBUG /* Ethernet Transmit and Receive Buffers */ -#define DBUF_LENGTH 1520 - -#define TX_BUF_CNT 2 - -/* - NOTE: PKT_MAXBUF_SIZE must be larger or equal to PKT_MAXBLR_SIZE, - see M54455 User Manual for MAX_FL of Receive Control Register for more - description. If PKT_MAXBUF_SIZE set to 1518, the FEC bandwidth will - reduce to about 20~40% of normal bandwidth. Changing PKT_MAXBLR_SIZE - will not make any improvement on speed -*/ +#define DBUF_LENGTH 1520 +#define TX_BUF_CNT 2 #define PKT_MAXBUF_SIZE 1518 #define PKT_MINBUF_SIZE 64 #define PKT_MAXBLR_SIZE 1520 @@ -102,12 +92,6 @@ struct fec_info_s fec_info[] = { #endif }; -/* - * FEC Ethernet Tx and Rx buffer descriptors allocated at the - * immr->udata_bd address on Dual-Port RAM - * Provide for Double Buffering - */ - int fec_send(struct eth_device *dev, volatile void *packet, int length); int fec_recv(struct eth_device *dev); int fec_init(struct eth_device *dev, bd_t * bd); @@ -166,15 +150,23 @@ int fec_send(struct eth_device *dev, volatile void *packet, int length) * Wait for ready */ j = 0; +#if (CONFIG_COMMANDS & CFG_CMD_CACHE) + icache_invalid(); +#endif while ((info->txbd[info->txIdx].cbd_sc & BD_ENET_TX_READY) && (j < MCFFEC_TOUT_LOOP)) { udelay(1); j++; +#if (CONFIG_COMMANDS & CFG_CMD_CACHE) + icache_invalid(); +#endif } if (j >= MCFFEC_TOUT_LOOP) { printf("TX not ready\n"); } - +#if (CONFIG_COMMANDS & CFG_CMD_CACHE) + icache_invalid(); +#endif info->txbd[info->txIdx].cbd_bufaddr = (uint) packet; info->txbd[info->txIdx].cbd_datlen = length; info->txbd[info->txIdx].cbd_sc |= BD_ENET_TX_RDY_LST; @@ -183,10 +175,16 @@ int fec_send(struct eth_device *dev, volatile void *packet, int length) fecp->tdar = 0x01000000; /* Descriptor polling active */ j = 0; +#if (CONFIG_COMMANDS & CFG_CMD_CACHE) + icache_invalid(); +#endif while ((info->txbd[info->txIdx].cbd_sc & BD_ENET_TX_READY) && (j < MCFFEC_TOUT_LOOP)) { udelay(1); j++; +#if (CONFIG_COMMANDS & CFG_CMD_CACHE) + icache_invalid(); +#endif } if (j >= MCFFEC_TOUT_LOOP) { printf("TX timeout\n"); @@ -199,6 +197,9 @@ int fec_send(struct eth_device *dev, volatile void *packet, int length) #endif /* return only status bits */ ; +#if (CONFIG_COMMANDS & CFG_CMD_CACHE) + icache_invalid(); +#endif rc = (info->txbd[info->txIdx].cbd_sc & BD_ENET_TX_STATS); info->txIdx = (info->txIdx + 1) % TX_BUF_CNT; @@ -257,12 +258,6 @@ int fec_recv(struct eth_device *dev) return length; } -/************************************************************** - * - * FEC Ethernet Initialization Routine - * - *************************************************************/ - #ifdef ET_DEBUG void dbgFecRegs(struct eth_device *dev) { @@ -419,7 +414,7 @@ int fec_init(struct eth_device *dev, bd_t * bd) struct fec_info_s *info = dev->priv; volatile fec_t *fecp = (fec_t *) (info->iobase); int i; - u8 *ea; + u8 *ea = NULL; fecpin_setclear(dev, 1); @@ -549,7 +544,9 @@ int mcffec_initialize(bd_t * bis) for (i = 0; i < sizeof(fec_info) / sizeof(fec_info[0]); i++) { - dev = (struct eth_device *)malloc(sizeof *dev); + dev = + (struct eth_device *)memalign(CFG_CACHELINE_SIZE, + sizeof *dev); if (dev == NULL) hang(); @@ -565,16 +562,19 @@ int mcffec_initialize(bd_t * bis) /* setup Receive and Transmit buffer descriptor */ fec_info[i].rxbd = - (cbd_t *) memalign(32, (PKTBUFSRX * sizeof(cbd_t) + 31)); + (cbd_t *) memalign(CFG_CACHELINE_SIZE, + (PKTBUFSRX * sizeof(cbd_t))); fec_info[i].txbd = - (cbd_t *) memalign(32, (TX_BUF_CNT * sizeof(cbd_t) + 31)); - fec_info[i].txbuf = (char *)memalign(32, DBUF_LENGTH + 31); + (cbd_t *) memalign(CFG_CACHELINE_SIZE, + (TX_BUF_CNT * sizeof(cbd_t))); + fec_info[i].txbuf = + (char *)memalign(CFG_CACHELINE_SIZE, DBUF_LENGTH); #ifdef ET_DEBUG printf("rxbd %x txbd %x\n", (int)fec_info[i].rxbd, (int)fec_info[i].txbd); #endif - fec_info[i].phy_name = (char *)malloc(32); + fec_info[i].phy_name = (char *)memalign(CFG_CACHELINE_SIZE, 32); eth_register(dev); From 2bd806fe4fc23958b8f78778199e7a6e3f8f6ad5 Mon Sep 17 00:00:00 2001 From: TsiChungLiew Date: Thu, 5 Jul 2007 23:17:36 -0500 Subject: [PATCH 028/259] Rename mcfserial.c. Update include header Renamed mcfserial.c to mcfuart.c. Modified Makefile for mcfuart.o from mcfserial.o. Replace immap_5329.h and m5329.h to immap.h Signed-off-by: TsiChungLiew --- drivers/serial/Makefile | 2 +- drivers/serial/{mcfserial.c => mcfuart.c} | 5 +++-- 2 files changed, 4 insertions(+), 3 deletions(-) rename drivers/serial/{mcfserial.c => mcfuart.c} (96%) diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile index 2208a08a7..93c68dd2e 100644 --- a/drivers/serial/Makefile +++ b/drivers/serial/Makefile @@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk LIB := $(obj)libserial.a -COBJS := mcfserial.o +COBJS := mcfuart.o SRCS := $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/drivers/serial/mcfserial.c b/drivers/serial/mcfuart.c similarity index 96% rename from drivers/serial/mcfserial.c rename to drivers/serial/mcfuart.c index a8ca78ad8..f54aabec2 100644 --- a/drivers/serial/mcfserial.c +++ b/drivers/serial/mcfuart.c @@ -1,5 +1,5 @@ /* - * (C) Copyright 2004, Freescale, Inc + * (C) Copyright 2004-2007 Freescale Semiconductor, Inc. * TsiChung Liew, Tsi-Chung.Liew@freescale.com. * * See file CREDITS for list of people who contributed to this @@ -28,7 +28,8 @@ */ #include -#include +#include +#include DECLARE_GLOBAL_DATA_PTR; From e04acb2eba4782489417240eff76e20e176aec10 Mon Sep 17 00:00:00 2001 From: TsiChungLiew Date: Thu, 5 Jul 2007 23:21:09 -0500 Subject: [PATCH 029/259] Rename mcfrtc to rtc Since it is already in m68k folder, un-necessary to pad mcf. Replaced immap_5329.h and m5329.h to immap.h Signed-off-by: TsiChungLiew --- include/asm-m68k/{mcfrtc.h => rtc.h} | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) rename include/asm-m68k/{mcfrtc.h => rtc.h} (98%) diff --git a/include/asm-m68k/mcfrtc.h b/include/asm-m68k/rtc.h similarity index 98% rename from include/asm-m68k/mcfrtc.h rename to include/asm-m68k/rtc.h index 70785354f..f955bc5fe 100644 --- a/include/asm-m68k/mcfrtc.h +++ b/include/asm-m68k/rtc.h @@ -1,7 +1,7 @@ /* * RealTime Clock * - * (C) Copyright 2007 + * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. * TsiChung Liew (Tsi-Chung.Liew@freescale.com) * * See file CREDITS for list of people who contributed to this From a90e79de8d99e9c9d69d60bfff9f24c337165900 Mon Sep 17 00:00:00 2001 From: TsiChungLiew Date: Thu, 5 Jul 2007 23:22:31 -0500 Subject: [PATCH 030/259] New timer structure and defines Seperated from mcftimer.h Signed-off-by: TsiChungLiew --- include/asm-m68k/timer.h | 104 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 104 insertions(+) create mode 100644 include/asm-m68k/timer.h diff --git a/include/asm-m68k/timer.h b/include/asm-m68k/timer.h new file mode 100644 index 000000000..d8f4e2a6a --- /dev/null +++ b/include/asm-m68k/timer.h @@ -0,0 +1,104 @@ +/* + * timer.h -- ColdFire internal TIMER support defines. + * + * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/****************************************************************************/ +#ifndef timer_h +#define timer_h +/****************************************************************************/ + +/****************************************************************************/ +/* Timer structure */ +/****************************************************************************/ +/* DMA Timer module registers */ +typedef struct dtimer_ctrl { + u16 tmr; /* 0x00 Mode register */ + u8 txmr; /* 0x02 Extended Mode register */ + u8 ter; /* 0x03 Event register */ + u32 trr; /* 0x04 Reference register */ + u32 tcr; /* 0x08 Capture register */ + u32 tcn; /* 0x0C Counter register */ +} dtmr_t; + +/*Programmable Interrupt Timer */ +typedef struct pit_ctrl { + u16 pcsr; /* 0x00 Control and Status Register */ + u16 pmr; /* 0x02 Modulus Register */ + u16 pcntr; /* 0x04 Count Register */ +} pit_t; + +/********************************************************************* +* DMA Timers (DTIM) +*********************************************************************/ +/* Bit definitions and macros for DTMR */ +#define DTIM_DTMR_RST (0x0001) /* Reset */ +#define DTIM_DTMR_CLK(x) (((x)&0x0003)<<1) /* Input clock source */ +#define DTIM_DTMR_FRR (0x0008) /* Free run/restart */ +#define DTIM_DTMR_ORRI (0x0010) /* Output reference request/interrupt enable */ +#define DTIM_DTMR_OM (0x0020) /* Output Mode */ +#define DTIM_DTMR_CE(x) (((x)&0x0003)<<6) /* Capture Edge */ +#define DTIM_DTMR_PS(x) (((x)&0x00FF)<<8) /* Prescaler value */ +#define DTIM_DTMR_RST_EN (0x0001) +#define DTIM_DTMR_RST_RST (0x0000) +#define DTIM_DTMR_CE_ANY (0x00C0) +#define DTIM_DTMR_CE_FALL (0x0080) +#define DTIM_DTMR_CE_RISE (0x0040) +#define DTIM_DTMR_CE_NONE (0x0000) +#define DTIM_DTMR_CLK_DTIN (0x0006) +#define DTIM_DTMR_CLK_DIV16 (0x0004) +#define DTIM_DTMR_CLK_DIV1 (0x0002) +#define DTIM_DTMR_CLK_STOP (0x0000) + +/* Bit definitions and macros for DTXMR */ +#define DTIM_DTXMR_MODE16 (0x01) /* Increment Mode */ +#define DTIM_DTXMR_DMAEN (0x80) /* DMA request */ + +/* Bit definitions and macros for DTER */ +#define DTIM_DTER_CAP (0x01) /* Capture event */ +#define DTIM_DTER_REF (0x02) /* Output reference event */ + +/********************************************************************* +* +* Programmable Interrupt Timer Modules (PIT) +* +*********************************************************************/ + +/* Bit definitions and macros for PCSR */ +#define PIT_PCSR_EN (0x0001) +#define PIT_PCSR_RLD (0x0002) +#define PIT_PCSR_PIF (0x0004) +#define PIT_PCSR_PIE (0x0008) +#define PIT_PCSR_OVW (0x0010) +#define PIT_PCSR_HALTED (0x0020) +#define PIT_PCSR_DOZE (0x0040) +#define PIT_PCSR_PRE(x) (((x)&0x000F)<<8) + +/* Bit definitions and macros for PMR */ +#define PIT_PMR_PM(x) (x) + +/* Bit definitions and macros for PCNTR */ +#define PIT_PCNTR_PC(x) (x) + +/****************************************************************************/ +#endif /* timer_h */ From 0cee9c66318602c856a899ae5fa7579ccba6443a Mon Sep 17 00:00:00 2001 From: TsiChungLiew Date: Thu, 5 Jul 2007 23:23:15 -0500 Subject: [PATCH 031/259] New uart structure and defines Seperated from mcfuart.h Signed-off-by: TsiChungLiew --- include/asm-m68k/uart.h | 171 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 171 insertions(+) create mode 100644 include/asm-m68k/uart.h diff --git a/include/asm-m68k/uart.h b/include/asm-m68k/uart.h new file mode 100644 index 000000000..9a528ea49 --- /dev/null +++ b/include/asm-m68k/uart.h @@ -0,0 +1,171 @@ +/* + * uart.h -- ColdFire internal UART support defines. + * + * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/****************************************************************************/ +#ifndef uart_h +#define uart_h +/****************************************************************************/ + +/* UART module registers */ +/* Register read/write struct */ +typedef struct uart { + u8 umr; /* 0x00 Mode Register */ + u8 resv0[0x3]; + union { + u8 usr; /* 0x04 Status Register */ + u8 ucsr; /* 0x04 Clock Select Register */ + }; + u8 resv1[0x3]; + u8 ucr; /* 0x08 Command Register */ + u8 resv2[0x3]; + union { + u8 utb; /* 0x0c Transmit Buffer */ + u8 urb; /* 0x0c Receive Buffer */ + }; + u8 resv3[0x3]; + union { + u8 uipcr; /* 0x10 Input Port Change Register */ + u8 uacr; /* 0x10 Auxiliary Control reg */ + }; + u8 resv4[0x3]; + union { + u8 uimr; /* 0x14 Interrupt Mask reg */ + u8 uisr; /* 0x14 Interrupt Status reg */ + }; + u8 resv5[0x3]; + u8 ubg1; /* 0x18 Counter Timer Upper Register */ + u8 resv6[0x3]; + u8 ubg2; /* 0x1c Counter Timer Lower Register */ + u8 resv7[0x17]; + u8 uip; /* 0x34 Input Port Register */ + u8 resv8[0x3]; + u8 uop1; /* 0x38 Output Port Set Register */ + u8 resv9[0x3]; + u8 uop0; /* 0x3c Output Port Reset Register */ +} uart_t; + +/********************************************************************* +* Universal Asynchronous Receiver Transmitter (UART) +*********************************************************************/ +/* Bit definitions and macros for UMR */ +#define UART_UMR_BC(x) (((x)&0x03)) +#define UART_UMR_PT (0x04) +#define UART_UMR_PM(x) (((x)&0x03)<<3) +#define UART_UMR_ERR (0x20) +#define UART_UMR_RXIRQ (0x40) +#define UART_UMR_RXRTS (0x80) +#define UART_UMR_SB(x) (((x)&0x0F)) +#define UART_UMR_TXCTS (0x10) /* Trsnsmit CTS */ +#define UART_UMR_TXRTS (0x20) /* Transmit RTS */ +#define UART_UMR_CM(x) (((x)&0x03)<<6) /* CM bits */ +#define UART_UMR_PM_MULTI_ADDR (0x1C) +#define UART_UMR_PM_MULTI_DATA (0x18) +#define UART_UMR_PM_NONE (0x10) +#define UART_UMR_PM_FORCE_HI (0x0C) +#define UART_UMR_PM_FORCE_LO (0x08) +#define UART_UMR_PM_ODD (0x04) +#define UART_UMR_PM_EVEN (0x00) +#define UART_UMR_BC_5 (0x00) +#define UART_UMR_BC_6 (0x01) +#define UART_UMR_BC_7 (0x02) +#define UART_UMR_BC_8 (0x03) +#define UART_UMR_CM_NORMAL (0x00) +#define UART_UMR_CM_ECH (0x40) +#define UART_UMR_CM_LOCAL_LOOP (0x80) +#define UART_UMR_CM_REMOTE_LOOP (0xC0) +#define UART_UMR_SB_STOP_BITS_1 (0x07) +#define UART_UMR_SB_STOP_BITS_15 (0x08) +#define UART_UMR_SB_STOP_BITS_2 (0x0F) + +/* Bit definitions and macros for USR */ +#define UART_USR_RXRDY (0x01) +#define UART_USR_FFULL (0x02) +#define UART_USR_TXRDY (0x04) +#define UART_USR_TXEMP (0x08) +#define UART_USR_OE (0x10) +#define UART_USR_PE (0x20) +#define UART_USR_FE (0x40) +#define UART_USR_RB (0x80) + +/* Bit definitions and macros for UCSR */ +#define UART_UCSR_TCS(x) (((x)&0x0F)) +#define UART_UCSR_RCS(x) (((x)&0x0F)<<4) +#define UART_UCSR_RCS_SYS_CLK (0xD0) +#define UART_UCSR_RCS_CTM16 (0xE0) +#define UART_UCSR_RCS_CTM (0xF0) +#define UART_UCSR_TCS_SYS_CLK (0x0D) +#define UART_UCSR_TCS_CTM16 (0x0E) +#define UART_UCSR_TCS_CTM (0x0F) + +/* Bit definitions and macros for UCR */ +#define UART_UCR_RXC(x) (((x)&0x03)) +#define UART_UCR_TXC(x) (((x)&0x03)<<2) +#define UART_UCR_MISC(x) (((x)&0x07)<<4) +#define UART_UCR_NONE (0x00) +#define UART_UCR_STOP_BREAK (0x70) +#define UART_UCR_START_BREAK (0x60) +#define UART_UCR_BKCHGINT (0x50) +#define UART_UCR_RESET_ERROR (0x40) +#define UART_UCR_RESET_TX (0x30) +#define UART_UCR_RESET_RX (0x20) +#define UART_UCR_RESET_MR (0x10) +#define UART_UCR_TX_DISABLED (0x08) +#define UART_UCR_TX_ENABLED (0x04) +#define UART_UCR_RX_DISABLED (0x02) +#define UART_UCR_RX_ENABLED (0x01) + +/* Bit definitions and macros for UIPCR */ +#define UART_UIPCR_CTS (0x01) +#define UART_UIPCR_COS (0x10) + +/* Bit definitions and macros for UACR */ +#define UART_UACR_IEC (0x01) + +/* Bit definitions and macros for UIMR */ +#define UART_UIMR_TXRDY (0x01) +#define UART_UIMR_RXRDY_FU (0x02) +#define UART_UIMR_DB (0x04) +#define UART_UIMR_COS (0x80) + +/* Bit definitions and macros for UISR */ +#define UART_UISR_TXRDY (0x01) +#define UART_UISR_RXRDY_FU (0x02) +#define UART_UISR_DB (0x04) +#define UART_UISR_RXFTO (0x08) +#define UART_UISR_TXFIFO (0x10) +#define UART_UISR_RXFIFO (0x20) +#define UART_UISR_COS (0x80) + +/* Bit definitions and macros for UIP */ +#define UART_UIP_CTS (0x01) + +/* Bit definitions and macros for UOP1 */ +#define UART_UOP1_RTS (0x01) + +/* Bit definitions and macros for UOP0 */ +#define UART_UOP0_RTS (0x01) + +/****************************************************************************/ +#endif /* mcfuart_h */ From 45a25bfd0c52f8a3fa137216bc94d32f90bedc5d Mon Sep 17 00:00:00 2001 From: TsiChungLiew Date: Thu, 5 Jul 2007 23:27:40 -0500 Subject: [PATCH 032/259] Update header file and clean up Include immap.h Signed-off-by: TsiChungLiew --- lib_m68k/interrupts.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/lib_m68k/interrupts.c b/lib_m68k/interrupts.c index 6b3ce8975..8919c0e8c 100644 --- a/lib_m68k/interrupts.c +++ b/lib_m68k/interrupts.c @@ -2,7 +2,7 @@ * (C) Copyright 2000-2004 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * - * (C) Copyright 2007 + * (C) Copyright 2007 Freescale Semiconductor Inc * TsiChung Liew (Tsi-Chung.Liew@freescale.com) * * See file CREDITS for list of people who contributed to this @@ -27,8 +27,8 @@ #include #include #include +#include -#ifdef CONFIG_MCFINTC #define NR_IRQS (CFG_NUM_IRQS) /* @@ -115,4 +115,3 @@ void int_handler (struct pt_regs *fp) printf ("\nBogus External Interrupt Vector %d\n", vec); } } -#endif /* CONFIG_MCFINTC */ \ No newline at end of file From 2870e98ac8e5553e9187b12a47e5f46babb53990 Mon Sep 17 00:00:00 2001 From: TsiChungLiew Date: Thu, 5 Jul 2007 23:29:21 -0500 Subject: [PATCH 033/259] Add mcffec_initialize() Added mcffec_initialize() in eth_initialize() Signed-off-by: TsiChungLiew --- net/eth.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/net/eth.c b/net/eth.c index cefd30ff2..4394b63de 100644 --- a/net/eth.c +++ b/net/eth.c @@ -268,6 +268,9 @@ int eth_initialize(bd_t *bis) #if defined(CONFIG_ATSTK1000) atstk1000_eth_initialize(bis); #endif +#if defined(CONFIG_MCFFEC) + mcffec_initialize(bis); +#endif if (!eth_devices) { puts ("No ethernet found.\n"); From 5cdc07c7ef8f08ea55d3c47ed9221d91aa6d5fac Mon Sep 17 00:00:00 2001 From: TsiChungLiew Date: Thu, 5 Jul 2007 23:31:25 -0500 Subject: [PATCH 034/259] Update header files Include immap.h and renamed mcfrtc.h to rtc.h Signed-off-by: TsiChungLiew --- rtc/mcfrtc.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/rtc/mcfrtc.c b/rtc/mcfrtc.c index c7eb53fb4..0be587426 100644 --- a/rtc/mcfrtc.c +++ b/rtc/mcfrtc.c @@ -1,6 +1,6 @@ /* - * (C) Copyright 2007 - * Freescale Semiconductor Tsi-Chung.Liew@freescale.com + * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew@freescale.com) * * See file CREDITS for list of people who contributed to this * project. @@ -25,7 +25,8 @@ #include #include -#include +#include +#include #if defined(CONFIG_MCFRTC) && (CONFIG_COMMANDS & CFG_CMD_DATE) From 52b017604a8f4d4a795880ef6e7861d7f2f1b005 Mon Sep 17 00:00:00 2001 From: TsiChungLiew Date: Thu, 5 Jul 2007 23:36:16 -0500 Subject: [PATCH 035/259] Update header file. Include dtimer_intr_setup(). Changed timer divider to global define. Include immap.h and timer.h. Moved dtimer interrupt setup to dtimer_intr_setup() from cpu/mcf532x/interrupts.c. Changed (CFG_CLK /1000000) -1 << 8 to CFG_TIMER_PRESCALER Signed-off-by: TsiChungLiew --- lib_m68k/time.c | 120 ++++++++++++++++++++++++++---------------------- 1 file changed, 64 insertions(+), 56 deletions(-) diff --git a/lib_m68k/time.c b/lib_m68k/time.c index 0e4efa473..267a3cdbc 100644 --- a/lib_m68k/time.c +++ b/lib_m68k/time.c @@ -26,6 +26,8 @@ #include #include +#include +#include #ifdef CONFIG_M5271 #include @@ -71,8 +73,10 @@ void udelay(unsigned long usec) timerp->timer_tmr = MCFTIMER_TMR_DISABLE; timerp->timer_tcn = 0; /* set period to 1 us */ - timerp->timer_tmr = (((CFG_CLK / 1000000) - 1) << 8) | MCFTIMER_TMR_CLK1 | - MCFTIMER_TMR_FREERUN | MCFTIMER_TMR_ENABLE; + timerp->timer_tmr = + (((CFG_CLK / 1000000) - + 1) << 8) | MCFTIMER_TMR_CLK1 | MCFTIMER_TMR_FREERUN | + MCFTIMER_TMR_ENABLE; start = now = timerp->timer_tcn; while (now < start + tmp) @@ -80,7 +84,8 @@ void udelay(unsigned long usec) } } -void mcf_timer_interrupt (void * not_used){ +void mcf_timer_interrupt(void *not_used) +{ volatile timer_t *timerp = (timer_t *) (CFG_MBAR + MCFTIMER_BASE4); volatile intctrl_t *intp = (intctrl_t *) (CFG_MBAR + MCFSIM_ICR1); @@ -91,10 +96,11 @@ void mcf_timer_interrupt (void * not_used){ /* reset timer */ timerp->timer_ter = MCFTIMER_TER_CAP | MCFTIMER_TER_REF; - timestamp ++; + timestamp++; } -void timer_init (void) { +void timer_init(void) +{ volatile timer_t *timerp = (timer_t *) (CFG_MBAR + MCFTIMER_BASE4); volatile intctrl_t *intp = (intctrl_t *) (CFG_MBAR + MCFSIM_ICR1); @@ -104,27 +110,29 @@ void timer_init (void) { timerp->timer_tmr = MCFTIMER_TMR_DISABLE; /* initialize and enable timer 4 interrupt */ - irq_install_handler (72, mcf_timer_interrupt, 0); + irq_install_handler(72, mcf_timer_interrupt, 0); intp->int_icr1 |= 0x0000000d; timerp->timer_tcn = 0; timerp->timer_trr = 1000; /* Interrupt every ms */ /* set a period of 1us, set timer mode to restart and enable timer and interrupt */ - timerp->timer_tmr = (((CFG_CLK / 1000000) - 1) << 8) | MCFTIMER_TMR_CLK1 | - MCFTIMER_TMR_RESTART | MCFTIMER_TMR_ENORI | MCFTIMER_TMR_ENABLE; + timerp->timer_tmr = + (((CFG_CLK / 1000000) - + 1) << 8) | MCFTIMER_TMR_CLK1 | MCFTIMER_TMR_RESTART | + MCFTIMER_TMR_ENORI | MCFTIMER_TMR_ENABLE; } -void reset_timer (void) +void reset_timer(void) { timestamp = 0; } -ulong get_timer (ulong base) +ulong get_timer(ulong base) { return (timestamp - base); } -void set_timer (ulong t) +void set_timer(ulong t) { timestamp = t; } @@ -137,7 +145,7 @@ void udelay(unsigned long usec) volatile unsigned short *timerp; uint tmp; - timerp = (volatile unsigned short *) (CFG_MBAR + MCFTIMER_BASE3); + timerp = (volatile unsigned short *)(CFG_MBAR + MCFTIMER_BASE3); while (usec > 0) { if (usec > 65000) @@ -152,21 +160,21 @@ void udelay(unsigned long usec) /* set period to 1 us */ timerp[MCFTIMER_PCSR] = #ifdef CONFIG_M5271 - (6 << 8) | MCFTIMER_PCSR_EN | MCFTIMER_PCSR_OVW; -#else /* !CONFIG_M5271 */ - (5 << 8) | MCFTIMER_PCSR_EN | MCFTIMER_PCSR_OVW; -#endif /* CONFIG_M5271 */ + (6 << 8) | MCFTIMER_PCSR_EN | MCFTIMER_PCSR_OVW; +#else /* !CONFIG_M5271 */ + (5 << 8) | MCFTIMER_PCSR_EN | MCFTIMER_PCSR_OVW; +#endif /* CONFIG_M5271 */ timerp[MCFTIMER_PMR] = tmp; - while (timerp[MCFTIMER_PCNTR] > 0); + while (timerp[MCFTIMER_PCNTR] > 0) ; } } -void timer_init (void) +void timer_init(void) { volatile unsigned short *timerp; - timerp = (volatile unsigned short *) (CFG_MBAR + MCFTIMER_BASE4); + timerp = (volatile unsigned short *)(CFG_MBAR + MCFTIMER_BASE4); timestamp = 0; /* Set up TIMER 4 as poll clock */ @@ -174,27 +182,27 @@ void timer_init (void) timerp[MCFTIMER_PMR] = lastinc = 0; timerp[MCFTIMER_PCSR] = #ifdef CONFIG_M5271 - (6 << 8) | MCFTIMER_PCSR_EN | MCFTIMER_PCSR_OVW; -#else /* !CONFIG_M5271 */ - (5 << 8) | MCFTIMER_PCSR_EN | MCFTIMER_PCSR_OVW; -#endif /* CONFIG_M5271 */ + (6 << 8) | MCFTIMER_PCSR_EN | MCFTIMER_PCSR_OVW; +#else /* !CONFIG_M5271 */ + (5 << 8) | MCFTIMER_PCSR_EN | MCFTIMER_PCSR_OVW; +#endif /* CONFIG_M5271 */ } -void set_timer (ulong t) +void set_timer(ulong t) { volatile unsigned short *timerp; - timerp = (volatile unsigned short *) (CFG_MBAR + MCFTIMER_BASE4); + timerp = (volatile unsigned short *)(CFG_MBAR + MCFTIMER_BASE4); timestamp = 0; timerp[MCFTIMER_PMR] = lastinc = 0; } -ulong get_timer (ulong base) +ulong get_timer(ulong base) { unsigned short now, diff; volatile unsigned short *timerp; - timerp = (volatile unsigned short *) (CFG_MBAR + MCFTIMER_BASE4); + timerp = (volatile unsigned short *)(CFG_MBAR + MCFTIMER_BASE4); now = timerp[MCFTIMER_PCNTR]; diff = -(now - lastinc); @@ -203,14 +211,13 @@ ulong get_timer (ulong base) return timestamp - base; } -void wait_ticks (unsigned long ticks) +void wait_ticks(unsigned long ticks) { - set_timer (0); - while (get_timer (0) < ticks); + set_timer(0); + while (get_timer(0) < ticks) ; } #endif - #if defined(CONFIG_M5249) /* * We use timer 1 which is running with a period of 1 us @@ -232,8 +239,10 @@ void udelay(unsigned long usec) timerp->timer_tcn = 0; /* set period to 1 us */ /* on m5249 the system clock is (cpu_clk / 2) -> divide by 2000000 */ - timerp->timer_tmr = (((CFG_CLK / 2000000) - 1) << 8) | MCFTIMER_TMR_CLK1 | - MCFTIMER_TMR_FREERUN | MCFTIMER_TMR_ENABLE; + timerp->timer_tmr = + (((CFG_CLK / 2000000) - + 1) << 8) | MCFTIMER_TMR_CLK1 | MCFTIMER_TMR_FREERUN | + MCFTIMER_TMR_ENABLE; start = now = timerp->timer_tcn; while (now < start + tmp) @@ -241,7 +250,8 @@ void udelay(unsigned long usec) } } -void mcf_timer_interrupt (void * not_used){ +void mcf_timer_interrupt(void *not_used) +{ volatile timer_t *timerp = (timer_t *) (CFG_MBAR + MCFTIMER_BASE2); /* check for timer 2 interrupts */ @@ -251,10 +261,11 @@ void mcf_timer_interrupt (void * not_used){ /* reset timer */ timerp->timer_ter = MCFTIMER_TER_CAP | MCFTIMER_TER_REF; - timestamp ++; + timestamp++; } -void timer_init (void) { +void timer_init(void) +{ volatile timer_t *timerp = (timer_t *) (CFG_MBAR + MCFTIMER_BASE2); timestamp = 0; @@ -263,29 +274,33 @@ void timer_init (void) { timerp->timer_tmr = MCFTIMER_TMR_DISABLE; /* initialize and enable timer 2 interrupt */ - irq_install_handler (31, mcf_timer_interrupt, 0); + irq_install_handler(31, mcf_timer_interrupt, 0); mbar_writeLong(MCFSIM_IMR, mbar_readLong(MCFSIM_IMR) & ~0x00000400); - mbar_writeByte(MCFSIM_TIMER2ICR, MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL7 | MCFSIM_ICR_PRI3); + mbar_writeByte(MCFSIM_TIMER2ICR, + MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL7 | + MCFSIM_ICR_PRI3); timerp->timer_tcn = 0; timerp->timer_trr = 1000; /* Interrupt every ms */ /* set a period of 1us, set timer mode to restart and enable timer and interrupt */ /* on m5249 the system clock is (cpu_clk / 2) -> divide by 2000000 */ - timerp->timer_tmr = (((CFG_CLK / 2000000) - 1) << 8) | MCFTIMER_TMR_CLK1 | - MCFTIMER_TMR_RESTART | MCFTIMER_TMR_ENORI | MCFTIMER_TMR_ENABLE; + timerp->timer_tmr = + (((CFG_CLK / 2000000) - + 1) << 8) | MCFTIMER_TMR_CLK1 | MCFTIMER_TMR_RESTART | + MCFTIMER_TMR_ENORI | MCFTIMER_TMR_ENABLE; } -void reset_timer (void) +void reset_timer(void) { timestamp = 0; } -ulong get_timer (ulong base) +ulong get_timer(ulong base) { return (timestamp - base); } -void set_timer (ulong t) +void set_timer(ulong t) { timestamp = t; } @@ -299,12 +314,7 @@ void set_timer (ulong t) #if !defined(CFG_TMR_BASE) || !defined(CFG_INTR_BASE) || !defined(CFG_TMRINTR_NO) || !defined(CFG_TMRINTR_MASK) # error "TMR_BASE, INTR_BASE, TMRINTR_NO or TMRINTR_MASk not defined!" #endif - -#include - -extern void dtimer_interrupt(void *not_used); -extern void dtimer_interrupt_setup(void); -extern void dtimer_interrupt_enable(void); +extern void dtimer_intr_setup(void); void udelay(unsigned long usec) { @@ -323,8 +333,8 @@ void udelay(unsigned long usec) timerp->tcn = 0; /* set period to 1 us */ timerp->tmr = - (((CFG_CLK / 1000000) - - 1) << 8) | DTIM_DTMR_CLK_DIV1 | DTIM_DTMR_FRR | DTIM_DTMR_RST_EN; + CFG_TIMER_PRESCALER | DTIM_DTMR_CLK_DIV1 | DTIM_DTMR_FRR | + DTIM_DTMR_RST_EN; start = now = timerp->tcn; while (now < start + tmp) @@ -348,7 +358,6 @@ void dtimer_interrupt(void *not_used) void timer_init(void) { volatile dtmr_t *timerp = (dtmr_t *) (CFG_TMR_BASE); - volatile int0_t *intp = (int0_t *) (CFG_INTR_BASE); timestamp = 0; @@ -358,14 +367,13 @@ void timer_init(void) /* Set up TIMER 4 as clock */ timerp->tmr = DTIM_DTMR_RST_RST; - /* initialize and enable timer 4 interrupt */ + /* initialize and enable timer interrupt */ irq_install_handler(CFG_TMRINTR_NO, dtimer_interrupt, 0); - intp->icr0[CFG_TMRINTR_NO] = CFG_TMRINTR_PRI; timerp->tcn = 0; timerp->trr = 1000; /* Interrupt every ms */ - intp->imrh0 &= ~CFG_TMRINTR_MASK; + dtimer_intr_setup(); /* set a period of 1us, set timer mode to restart and enable timer and interrupt */ timerp->tmr = CFG_TIMER_PRESCALER | DTIM_DTMR_CLK_DIV1 | @@ -470,7 +478,7 @@ unsigned long long get_ticks(void) * This function is derived from PowerPC code (timebase clock frequency). * On M68K it returns the number of timer ticks per second. */ -ulong get_tbclk (void) +ulong get_tbclk(void) { ulong tbclk; tbclk = CFG_HZ; From 0dca874db62718e41253659e60f3a1de7eb418ce Mon Sep 17 00:00:00 2001 From: TsiChung Date: Tue, 10 Jul 2007 15:45:43 -0500 Subject: [PATCH 036/259] Cache update and added CFG_UNIFY_CACHE Enabled cache in cpu_init_f() for faster flash to mem allocation. Updated cache handling in start.S. Applied cache invalidate in fec_send() and fec_recv(). Added CFG_UNIFY_CACHE for CF V3 only. Signed-off-by: TsiChung --- cpu/mcf532x/cpu_init.c | 3 ++- cpu/mcf532x/start.S | 12 +++++------- drivers/net/mcffec.c | 26 ++++++++------------------ include/configs/M5329EVB.h | 26 ++++++++++++++------------ 4 files changed, 29 insertions(+), 38 deletions(-) diff --git a/cpu/mcf532x/cpu_init.c b/cpu/mcf532x/cpu_init.c index b056fbe31..32711a174 100644 --- a/cpu/mcf532x/cpu_init.c +++ b/cpu/mcf532x/cpu_init.c @@ -113,6 +113,8 @@ void cpu_init_f(void) fbcs->cscr5 = CFG_CS5_CTRL; fbcs->csmr5 = CFG_CS5_MASK; #endif + + icache_enable(); } /* @@ -120,6 +122,5 @@ void cpu_init_f(void) */ int cpu_init_r(void) { - icache_enable(); return (0); } diff --git a/cpu/mcf532x/start.S b/cpu/mcf532x/start.S index acd34941a..ac44aaabe 100644 --- a/cpu/mcf532x/start.S +++ b/cpu/mcf532x/start.S @@ -270,8 +270,6 @@ icache_enable: movec %d0, %CACR /* Invalidate cache */ move.l #(CFG_SDRAM_BASE + 0xc000), %d0 /* Setup cache mask */ movec %d0, %ACR0 /* Enable cache */ - move.l #(CFG_CS0_BASE + 0x0000), %d0 /* Setup cache mask */ - movec %d0, %ACR1 /* Enable cache */ move.l #0x80000200, %d0 /* Setup cache mask */ movec %d0, %CACR /* Enable cache */ @@ -284,11 +282,11 @@ icache_enable: .globl icache_disable icache_disable: - move.l #0x00000100, %d0 /* Setup cache mask */ - movec %d0, %CACR /* Enable cache */ + move.l #0x01000000, %d0 /* Setup cache mask */ + movec %d0, %CACR /* Disable cache */ clr.l %d0 /* Setup cache mask */ - movec %d0, %ACR0 /* Enable cache */ - movec %d0, %ACR1 /* Enable cache */ + movec %d0, %ACR0 + movec %d0, %ACR1 move.l #(CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END-8), %a1 moveq #0, %d0 @@ -303,7 +301,7 @@ icache_status: .globl icache_invalid icache_invalid: - move.l #0x01000000, %d0 /* Setup cache mask */ + move.l #0x81000200, %d0 /* Setup cache mask */ movec %d0, %CACR /* Enable cache */ rts diff --git a/drivers/net/mcffec.c b/drivers/net/mcffec.c index 609210de1..11f672189 100644 --- a/drivers/net/mcffec.c +++ b/drivers/net/mcffec.c @@ -150,23 +150,15 @@ int fec_send(struct eth_device *dev, volatile void *packet, int length) * Wait for ready */ j = 0; -#if (CONFIG_COMMANDS & CFG_CMD_CACHE) - icache_invalid(); -#endif while ((info->txbd[info->txIdx].cbd_sc & BD_ENET_TX_READY) && (j < MCFFEC_TOUT_LOOP)) { udelay(1); j++; -#if (CONFIG_COMMANDS & CFG_CMD_CACHE) - icache_invalid(); -#endif } if (j >= MCFFEC_TOUT_LOOP) { printf("TX not ready\n"); } -#if (CONFIG_COMMANDS & CFG_CMD_CACHE) - icache_invalid(); -#endif + info->txbd[info->txIdx].cbd_bufaddr = (uint) packet; info->txbd[info->txIdx].cbd_datlen = length; info->txbd[info->txIdx].cbd_sc |= BD_ENET_TX_RDY_LST; @@ -174,21 +166,19 @@ int fec_send(struct eth_device *dev, volatile void *packet, int length) /* Activate transmit Buffer Descriptor polling */ fecp->tdar = 0x01000000; /* Descriptor polling active */ - j = 0; -#if (CONFIG_COMMANDS & CFG_CMD_CACHE) +#ifdef CFG_UNIFY_CACHE icache_invalid(); #endif + j = 0; while ((info->txbd[info->txIdx].cbd_sc & BD_ENET_TX_READY) && (j < MCFFEC_TOUT_LOOP)) { udelay(1); j++; -#if (CONFIG_COMMANDS & CFG_CMD_CACHE) - icache_invalid(); -#endif } if (j >= MCFFEC_TOUT_LOOP) { printf("TX timeout\n"); } + #ifdef ET_DEBUG printf("%s[%d] %s: cycles: %d status: %x retry cnt: %d\n", __FILE__, __LINE__, __FUNCTION__, j, @@ -196,10 +186,7 @@ int fec_send(struct eth_device *dev, volatile void *packet, int length) (info->txbd[info->txIdx].cbd_sc & 0x003C) >> 2); #endif - /* return only status bits */ ; -#if (CONFIG_COMMANDS & CFG_CMD_CACHE) - icache_invalid(); -#endif + /* return only status bits */ rc = (info->txbd[info->txIdx].cbd_sc & BD_ENET_TX_STATS); info->txIdx = (info->txIdx + 1) % TX_BUF_CNT; @@ -213,6 +200,9 @@ int fec_recv(struct eth_device *dev) int length; for (;;) { +#ifdef CFG_UNIFY_CACHE + icache_invalid(); +#endif /* section 16.9.23.2 */ if (info->rxbd[info->rxIdx].cbd_sc & BD_ENET_RX_EMPTY) { length = -1; diff --git a/include/configs/M5329EVB.h b/include/configs/M5329EVB.h index c90773c50..d1ac34004 100644 --- a/include/configs/M5329EVB.h +++ b/include/configs/M5329EVB.h @@ -47,18 +47,20 @@ #define CONFIG_WATCHDOG_TIMEOUT 5000 /* timeout in milliseconds, max timeout is 6.71sec */ #define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_CACHE | \ - CFG_CMD_DATE | \ - CFG_CMD_ELF | \ - CFG_CMD_FLASH | \ - (CFG_CMD_LOADB | CFG_CMD_LOADS) | \ - CFG_CMD_MEMORY | \ - CFG_CMD_MISC | \ - CFG_CMD_MII | \ - CFG_CMD_NET | \ - CFG_CMD_PING | \ - CFG_CMD_REGINFO \ - ) + CFG_CMD_CACHE | \ + CFG_CMD_DATE | \ + CFG_CMD_ELF | \ + CFG_CMD_FLASH | \ + (CFG_CMD_LOADB | CFG_CMD_LOADS) | \ + CFG_CMD_MEMORY | \ + CFG_CMD_MISC | \ + CFG_CMD_MII | \ + CFG_CMD_NET | \ + CFG_CMD_PING | \ + CFG_CMD_REGINFO \ + ) + +#define CFG_UNIFY_CACHE #define CONFIG_MCFFEC #ifdef CONFIG_MCFFEC From a2e1c7098cf9574386b0c96841dfc8ea5cc93578 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Thu, 12 Jul 2007 16:32:08 +0200 Subject: [PATCH 037/259] ppc4xx: Change receive buffer handling in the 4xx emac driver This change fixes a bug in the receive buffer handling, that could lead to problems upon high network traffic (broadcasts...). Signed-off-by: Stefan Roese --- cpu/ppc4xx/4xx_enet.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/cpu/ppc4xx/4xx_enet.c b/cpu/ppc4xx/4xx_enet.c index 1200d021a..b90363f47 100644 --- a/cpu/ppc4xx/4xx_enet.c +++ b/cpu/ppc4xx/4xx_enet.c @@ -1415,10 +1415,8 @@ static void enet_rcv (struct eth_device *dev, unsigned long malisr) if ((MAL_RX_CTRL_EMPTY & hw_p->rx[i].ctrl) || (loop_count >= NUM_RX_BUFF)) break; + loop_count++; - hw_p->rx_slot++; - if (NUM_RX_BUFF == hw_p->rx_slot) - hw_p->rx_slot = 0; handled++; data_len = (unsigned long) hw_p->rx[i].data_len; /* Get len */ if (data_len) { @@ -1468,6 +1466,10 @@ static void enet_rcv (struct eth_device *dev, unsigned long malisr) if (NUM_RX_BUFF == hw_p->rx_i_index) hw_p->rx_i_index = 0; + hw_p->rx_slot++; + if (NUM_RX_BUFF == hw_p->rx_slot) + hw_p->rx_slot = 0; + /* AS.HARNOIS * free receive buffer only when * buffer has been handled (eth_rx) From 5743a9207a370b90f09b20ebd61167c806b937f3 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Mon, 16 Jul 2007 08:53:51 +0200 Subject: [PATCH 038/259] ppc4xx: Add remove_tlb() function to remove a mem area from TLB setup The new function remove_tlb() can be used to remove the TLB's used to map a specific memory region. This is especially useful for the DDR(2) setup routines which configure the SDRAM area temporarily as a cached area (for speedup on auto-calibration and ECC generation) and later need this area uncached for normal usage. Signed-off-by: Stefan Roese --- cpu/ppc4xx/tlb.c | 62 ++++++++++++++++++++++++++++++++++++++++++- include/asm-ppc/mmu.h | 3 +++ 2 files changed, 64 insertions(+), 1 deletion(-) diff --git a/cpu/ppc4xx/tlb.c b/cpu/ppc4xx/tlb.c index 049a78549..098694caf 100644 --- a/cpu/ppc4xx/tlb.c +++ b/cpu/ppc4xx/tlb.c @@ -25,7 +25,6 @@ #if defined(CONFIG_440) -#include #include #include #include @@ -36,6 +35,67 @@ typedef struct region { unsigned long tlb_word2_i_value; } region_t; +void remove_tlb(u32 vaddr, u32 size) +{ + int i; + u32 tlb_word0_value; + u32 tlb_vaddr; + u32 tlb_size = 0; + + /* First, find the index of a TLB entry not being used */ + for (i=0; i= vaddr)) { + /* + * TLB is enabled and start address is lower or equal + * than the area we are looking for. Now we only have + * to check the size/end address for a match. + */ + switch (tlb_word0_value & TLB_WORD0_SIZE_MASK) { + case TLB_WORD0_SIZE_1KB: + tlb_size = 1 << 10; + break; + case TLB_WORD0_SIZE_4KB: + tlb_size = 4 << 10; + break; + case TLB_WORD0_SIZE_16KB: + tlb_size = 16 << 10; + break; + case TLB_WORD0_SIZE_64KB: + tlb_size = 64 << 10; + break; + case TLB_WORD0_SIZE_256KB: + tlb_size = 256 << 10; + break; + case TLB_WORD0_SIZE_1MB: + tlb_size = 1 << 20; + break; + case TLB_WORD0_SIZE_16MB: + tlb_size = 16 << 20; + break; + case TLB_WORD0_SIZE_256MB: + tlb_size = 256 << 20; + break; + } + + /* + * Now check the end-address if it's in the range + */ + if ((tlb_vaddr + tlb_size - 1) <= (vaddr + size - 1)) + /* + * Found a TLB in the range. + * Disable it by writing 0 to tlb0 word. + */ + mttlb1(i, 0); + } + } + + /* Execute an ISYNC instruction so that the new TLB entry takes effect */ + asm("isync"); +} + static int add_tlb_entry(unsigned long phys_addr, unsigned long virt_addr, unsigned long tlb_word0_size_value, diff --git a/include/asm-ppc/mmu.h b/include/asm-ppc/mmu.h index 48fd98295..b3cfa9b37 100644 --- a/include/asm-ppc/mmu.h +++ b/include/asm-ppc/mmu.h @@ -645,6 +645,9 @@ void mttlb3(unsigned long index, unsigned long value); unsigned long mftlb1(unsigned long index); unsigned long mftlb2(unsigned long index); unsigned long mftlb3(unsigned long index); + +void program_tlb(u32 phys_addr, u32 virt_addr, u32 size, u32 tlb_word2_i_value); +void remove_tlb(u32 vaddr, u32 size); #endif /* __ASSEMBLY__ */ #endif /* CONFIG_440 */ From 6ed14addf97c8cd8f531e9ae7b2d3e222fffd53e Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Mon, 16 Jul 2007 09:57:00 +0200 Subject: [PATCH 039/259] ppc4xx: Add new weak functions to support boardspecific DDR2 configuration The new "weak" functions ddr_wrdtr() and ddr_clktr() are added to better support non default, boardspecific DDR(2) controller configuration. Signed-off-by: Stefan Roese --- cpu/ppc4xx/44x_spd_ddr2.c | 58 +++++++++++++++++++++++++++++---------- 1 file changed, 44 insertions(+), 14 deletions(-) diff --git a/cpu/ppc4xx/44x_spd_ddr2.c b/cpu/ppc4xx/44x_spd_ddr2.c index 5fef27b98..18b90ba5a 100644 --- a/cpu/ppc4xx/44x_spd_ddr2.c +++ b/cpu/ppc4xx/44x_spd_ddr2.c @@ -109,7 +109,7 @@ /* Defines for the Read Cycle Delay test */ #define NUMMEMTESTS 8 #define NUMMEMWORDS 8 -#define NUMLOOPS 256 /* memory test loops */ +#define NUMLOOPS 64 /* memory test loops */ #undef CONFIG_ECC_ERROR_RESET /* test-only: see description below, at check_ecc() */ @@ -138,6 +138,26 @@ void __spd_ddr_init_hang (void) } void spd_ddr_init_hang (void) __attribute__((weak, alias("__spd_ddr_init_hang"))); +/* + * To provide an interface for board specific config values in this common + * DDR setup code, we implement he "weak" default functions here. They return + * the default value back to the caller. + * + * Please see include/configs/yucca.h for an example fora board specific + * implementation. + */ +u32 __ddr_wrdtr(u32 default_val) +{ + return default_val; +} +u32 ddr_wrdtr(u32) __attribute__((weak, alias("__ddr_wrdtr"))); + +u32 __ddr_clktr(u32 default_val) +{ + return default_val; +} +u32 ddr_clktr(u32) __attribute__((weak, alias("__ddr_clktr"))); + /* Private Structure Definitions */ @@ -154,7 +174,6 @@ typedef enum ddr_cas_id { * Prototypes *-----------------------------------------------------------------------------*/ static unsigned long sdram_memsize(void); -void program_tlb(u32 phys_addr, u32 virt_addr, u32 size, u32 tlb_word2_i_value); static void get_spd_info(unsigned long *dimm_populated, unsigned char *iic0_dimm_addr, unsigned long num_dimm_banks); @@ -216,9 +235,7 @@ static void test(void); #else static void DQS_calibration_process(void); #endif -#if defined(DEBUG) static void ppc440sp_sdram_register_dump(void); -#endif int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); void dcbz_area(u32 start_address, u32 num_bytes); void dflush(void); @@ -469,17 +486,14 @@ long int initdram(int board_type) *-----------------------------------------------------------------*/ mfsdram(SDRAM_WRDTR, val); mtsdram(SDRAM_WRDTR, (val & ~(SDRAM_WRDTR_LLWP_MASK | SDRAM_WRDTR_WTR_MASK)) | - (SDRAM_WRDTR_LLWP_1_CYC | SDRAM_WRDTR_WTR_90_DEG_ADV)); + ddr_wrdtr(SDRAM_WRDTR_LLWP_1_CYC | SDRAM_WRDTR_WTR_90_DEG_ADV)); /*------------------------------------------------------------------ * Set the SDRAM Clock Timing Register *-----------------------------------------------------------------*/ mfsdram(SDRAM_CLKTR, val); -#ifdef CFG_44x_DDR2_CKTR_180 - mtsdram(SDRAM_CLKTR, (val & ~SDRAM_CLKTR_CLKP_MASK) | SDRAM_CLKTR_CLKP_180_DEG_ADV); -#else - mtsdram(SDRAM_CLKTR, (val & ~SDRAM_CLKTR_CLKP_MASK) | SDRAM_CLKTR_CLKP_0_DEG); -#endif + mtsdram(SDRAM_CLKTR, (val & ~SDRAM_CLKTR_CLKP_MASK) | + ddr_clktr(SDRAM_CLKTR_CLKP_0_DEG)); /*------------------------------------------------------------------ * Program the BxCF registers. @@ -538,7 +552,12 @@ long int initdram(int board_type) dram_size = sdram_memsize(); /* and program tlb entries for this size (dynamic) */ - program_tlb(0, 0, dram_size, MY_TLB_WORD2_I_ENABLE); + + /* + * Program TLB entries with caches enabled, for best performace + * while auto-calibrating and ECC generation + */ + program_tlb(0, 0, dram_size, 0); /*------------------------------------------------------------------ * DQS calibration. @@ -549,12 +568,18 @@ long int initdram(int board_type) /*------------------------------------------------------------------ * If ecc is enabled, initialize the parity bits. *-----------------------------------------------------------------*/ - program_ecc(dimm_populated, iic0_dimm_addr, num_dimm_banks, MY_TLB_WORD2_I_ENABLE); + program_ecc(dimm_populated, iic0_dimm_addr, num_dimm_banks, 0); #endif -#ifdef DEBUG + /* + * Now after initialization (auto-calibration and ECC generation) + * remove the TLB entries with caches enabled and program again with + * desired cache functionality + */ + remove_tlb(0, dram_size); + program_tlb(0, 0, dram_size, MY_TLB_WORD2_I_ENABLE); + ppc440sp_sdram_register_dump(); -#endif return dram_size; } @@ -2703,6 +2728,7 @@ calibration_loop: printf("\nERROR: Cannot determine a common read delay for the " "DIMM(s) installed.\n"); debug("%s[%d] ERROR : \n", __FUNCTION__,__LINE__); + ppc440sp_sdram_register_dump(); spd_ddr_init_hang (); } @@ -3028,5 +3054,9 @@ static void ppc440sp_sdram_register_dump(void) dcr_data = mfdcr(SDRAM_R3BAS); printf(" MQ3_B0BAS = 0x%08X\n", dcr_data); } +#else +static void ppc440sp_sdram_register_dump(void) +{ +} #endif #endif /* CONFIG_SPD_EEPROM */ From df3f17422aeb03fb81a7ac8c78d2b05d05aa4cf9 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Mon, 16 Jul 2007 10:00:43 +0200 Subject: [PATCH 040/259] ppc4xx: Support for Yucca board with 440SPe Rev A added to 44x_spd_ddr2.c The new boardspecific DDR2 controller configuration is used for the Yucca board. Now the Yucca board with 440SPe Rev. A chips is also supported. Signed-off-by: Stefan Roese --- board/amcc/yucca/yucca.c | 34 ++++++++++++++++++++++++++++++++++ 1 file changed, 34 insertions(+) diff --git a/board/amcc/yucca/yucca.c b/board/amcc/yucca/yucca.c index 7316c34b4..d08fcf356 100644 --- a/board/amcc/yucca/yucca.c +++ b/board/amcc/yucca/yucca.c @@ -562,6 +562,40 @@ int checkboard (void) return 0; } +/* + * Override the default functions in cpu/ppc4xx/44x_spd_ddr2.c with + * board specific values. + */ +static int ppc440spe_rev_a(void) +{ + if ((get_pvr() == PVR_440SPe_6_RA) || (get_pvr() == PVR_440SPe_RA)) + return 1; + else + return 0; +} + +u32 ddr_wrdtr(u32 default_val) { + /* + * Yucca boards with 440SPe rev. A need a slightly different setup + * for the MCIF0_WRDTR register. + */ + if (ppc440spe_rev_a()) + return (SDRAM_WRDTR_LLWP_1_CYC | SDRAM_WRDTR_WTR_270_DEG_ADV); + + return default_val; +} + +u32 ddr_clktr(u32 default_val) { + /* + * Yucca boards with 440SPe rev. A need a slightly different setup + * for the MCIF0_CLKTR register. + */ + if (ppc440spe_rev_a()) + return (SDRAM_CLKTR_CLKP_180_DEG_ADV); + + return default_val; +} + #if defined(CFG_DRAM_TEST) int testdram (void) { From 2a49fc17d09020e7ebd9536694d99d20e419fcb8 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Mon, 16 Jul 2007 10:01:38 +0200 Subject: [PATCH 041/259] ppc4xx: AMCC Luan uses the new boardspecific DDR2 controller setup Signed-off-by: Stefan Roese --- board/amcc/luan/luan.c | 7 +++++++ include/configs/luan.h | 1 - 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/board/amcc/luan/luan.c b/board/amcc/luan/luan.c index 2eff3b33f..7b16f8a39 100644 --- a/board/amcc/luan/luan.c +++ b/board/amcc/luan/luan.c @@ -104,6 +104,13 @@ int checkboard(void) return 0; } +/* + * Override the default functions in cpu/ppc4xx/44x_spd_ddr2.c with + * board specific values. + */ +u32 ddr_clktr(u32 default_val) { + return (SDRAM_CLKTR_CLKP_180_DEG_ADV); +} /************************************************************************* * int testdram() diff --git a/include/configs/luan.h b/include/configs/luan.h index cbb59c50e..e192d0692 100644 --- a/include/configs/luan.h +++ b/include/configs/luan.h @@ -136,7 +136,6 @@ #define CONFIG_SPD_EEPROM 1 /* Use SPD EEPROM for setup */ #define SPD_EEPROM_ADDRESS {0x53, 0x52} /* SPD i2c spd addresses*/ #define CONFIG_DDR_ECC 1 /* with ECC support */ -#define CFG_44x_DDR2_CKTR_180 1 /* use 180 deg advance */ /*----------------------------------------------------------------------- * I2C From 8848ec858f74ed6dab06fb6d5ddc933e0a1328bf Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Mon, 16 Jul 2007 10:02:12 +0200 Subject: [PATCH 042/259] ppc4xx: Code cleanup Signed-off-by: Stefan Roese --- board/lwmon5/sdram.c | 1 - cpu/ppc4xx/44x_spd_ddr.c | 1 - 2 files changed, 2 deletions(-) diff --git a/board/lwmon5/sdram.c b/board/lwmon5/sdram.c index 9a4a8eea8..b6863b6a7 100644 --- a/board/lwmon5/sdram.c +++ b/board/lwmon5/sdram.c @@ -54,7 +54,6 @@ #define MY_TLB_WORD2_I_ENABLE TLB_WORD2_I_ENABLE /* disable caching on SDRAM */ #endif -void program_tlb(u32 phys_addr, u32 virt_addr, u32 size, u32 tlb_word2_i_value); void dcbz_area(u32 start_address, u32 num_bytes); void dflush(void); diff --git a/cpu/ppc4xx/44x_spd_ddr.c b/cpu/ppc4xx/44x_spd_ddr.c index 8c18d0f4e..0b0c55a44 100644 --- a/cpu/ppc4xx/44x_spd_ddr.c +++ b/cpu/ppc4xx/44x_spd_ddr.c @@ -271,7 +271,6 @@ typedef struct bank_param BANKPARMS; #ifdef CFG_SIMULATE_SPD_EEPROM extern unsigned char cfg_simulate_spd_eeprom[128]; #endif -void program_tlb(u32 phys_addr, u32 virt_addr, u32 size, u32 tlb_word2_i_value); static unsigned char spd_read(uchar chip, uint addr); static void get_spd_info(unsigned long *dimm_populated, From c883f6ea32dce91f07670b3aafecf6c99b1e5341 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Mon, 16 Jul 2007 13:11:12 +0200 Subject: [PATCH 043/259] Coding style cleanup Signed-off-by: Stefan Roese --- MAKEALL | 2 +- board/freescale/m5329evb/m5329evb.c | 1 - include/asm-m68k/immap.h | 4 ++-- 3 files changed, 3 insertions(+), 4 deletions(-) diff --git a/MAKEALL b/MAKEALL index 6771ea6e9..2cdf10c28 100755 --- a/MAKEALL +++ b/MAKEALL @@ -315,7 +315,7 @@ LIST_microblaze=" \ LIST_coldfire=" \ cobra5272 EB+MCF-EV123 EB+MCF-EV123_internal \ idmr M5271EVB M5272C3 M5282EVB \ - TASREG r5200 M5271EVB M5329EVB \ + M5329EVB r5200 TASREG \ " ######################################################################### diff --git a/board/freescale/m5329evb/m5329evb.c b/board/freescale/m5329evb/m5329evb.c index 07a02c272..d180b6f43 100644 --- a/board/freescale/m5329evb/m5329evb.c +++ b/board/freescale/m5329evb/m5329evb.c @@ -94,4 +94,3 @@ void sync(void) coldfire does not have this instruction. Dummy function */ } #endif /* CFG_FLASH_CFI */ - diff --git a/include/asm-m68k/immap.h b/include/asm-m68k/immap.h index 495459e83..4e238c3f5 100644 --- a/include/asm-m68k/immap.h +++ b/include/asm-m68k/immap.h @@ -25,7 +25,7 @@ #ifndef __IMMAP_H #define __IMMAP_H - + #ifdef CONFIG_M5329 #include #include @@ -53,5 +53,5 @@ #define CFG_INTR_BASE (MMAP_INTC0) #define CFG_NUM_IRQS (128) #endif /* CONFIG_M5329 */ - + #endif /* __IMMAP_H */ From 531e3e8b831f357056448fa573137d5fb37000fd Mon Sep 17 00:00:00 2001 From: Pavel Kolesnikov Date: Fri, 20 Jul 2007 15:03:03 +0200 Subject: [PATCH 044/259] POST: Add ECC POST for the lwmon5 board This patch adds ECC Post test for the Lwmon5 board based on PPC440EPx to U-Boot. Signed-off-by: Pavel Kolesnikov Acked-by: Yuri Tikhonov Acked-by: Stefan Roese --- board/lwmon5/lwmon5.c | 11 ++ include/configs/lwmon5.h | 8 +- include/post.h | 1 + post/board/lwmon5/Makefile | 29 +++++ post/board/lwmon5/ecc.c | 257 +++++++++++++++++++++++++++++++++++++ post/tests.c | 13 ++ 6 files changed, 318 insertions(+), 1 deletion(-) create mode 100644 post/board/lwmon5/Makefile create mode 100644 post/board/lwmon5/ecc.c diff --git a/board/lwmon5/lwmon5.c b/board/lwmon5/lwmon5.c index d91628475..b7dbba3e8 100644 --- a/board/lwmon5/lwmon5.c +++ b/board/lwmon5/lwmon5.c @@ -463,3 +463,14 @@ void hw_watchdog_reset(void) val = gpio_read_out_bit(CFG_GPIO_WATCHDOG) == 0 ? 1 : 0; gpio_write_bit(CFG_GPIO_WATCHDOG, val); } + +#ifdef CONFIG_POST +/* + * Returns 1 if keys pressed to start the power-on long-running tests + * Called from board_init_f(). + */ +int post_hotkeys_pressed(void) +{ + return (ctrlc()); +} +#endif diff --git a/include/configs/lwmon5.h b/include/configs/lwmon5.h index c4b7c4ee5..36ead2301 100644 --- a/include/configs/lwmon5.h +++ b/include/configs/lwmon5.h @@ -74,11 +74,13 @@ /* 440EPx/440GRx have 16KB of internal SRAM, so no need for D-Cache */ #define CFG_INIT_RAM_OCM 1 /* OCM as init ram */ #define CFG_INIT_RAM_ADDR CFG_OCM_BASE /* OCM */ +#define CFG_OCM_DATA_ADDR CFG_OCM_BASE #define CFG_INIT_RAM_END (4 << 10) #define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */ #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET +#define CFG_POST_WORD_ADDR (CFG_GBL_DATA_OFFSET - 0x4) +#define CFG_INIT_SP_OFFSET CFG_POST_WORD_ADDR /*----------------------------------------------------------------------- * Serial Port @@ -133,6 +135,10 @@ #define CONFIG_DDR_DATA_EYE 1 /* use DDR2 optimization */ #if 0 /* test-only: disable ECC for now */ #define CONFIG_DDR_ECC 1 /* enable ECC */ + +/* POST support */ +#define CONFIG_POST (CFG_POST_ECC) + #endif /*----------------------------------------------------------------------- diff --git a/include/post.h b/include/post.h index 8259e5d2e..c8062bbbc 100644 --- a/include/post.h +++ b/include/post.h @@ -92,6 +92,7 @@ extern int post_hotkeys_pressed(void); #define CFG_POST_DSP 0x00001000 #define CFG_POST_CODEC 0x00002000 #define CFG_POST_FPU 0x00004000 +#define CFG_POST_ECC 0x00008000 #endif /* CONFIG_POST */ diff --git a/post/board/lwmon5/Makefile b/post/board/lwmon5/Makefile new file mode 100644 index 000000000..c3f54e37b --- /dev/null +++ b/post/board/lwmon5/Makefile @@ -0,0 +1,29 @@ +# +# (C) Copyright 2002-2007 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + + +LIB = libpostlwmon5.a + +COBJS = ecc.o + +include $(TOPDIR)/post/rules.mk diff --git a/post/board/lwmon5/ecc.c b/post/board/lwmon5/ecc.c new file mode 100644 index 000000000..7f04f9abe --- /dev/null +++ b/post/board/lwmon5/ecc.c @@ -0,0 +1,257 @@ +/* + * (C) Copyright 2007 + * Developed for DENX Software Engineering GmbH. + * + * Author: Pavel Kolesnikov + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* define DEBUG for debugging output (obviously ;-)) */ +#if 0 +#define DEBUG +#endif + +#include +#include + +#ifdef CONFIG_POST + +#include + +#if CONFIG_POST & CFG_POST_ECC + +/* + * MEMORY ECC test + * + * This test performs the checks ECC facility of memory. + */ +#include +#include +#include +#include + +#include "../../../board/lwmon5/sdram.h" + +DECLARE_GLOBAL_DATA_PTR; + +const static unsigned char syndrome_codes[] = { + 0xF4, 0XF1, 0XEC ,0XEA, 0XE9, 0XE6, 0XE5, 0XE3, + 0XDC, 0XDA, 0XD9, 0XD6, 0XD5, 0XD3, 0XCE, 0XCB, + 0xB5, 0XB0, 0XAD, 0XAB, 0XA8, 0XA7, 0XA4, 0XA2, + 0X9D, 0X9B, 0X98, 0X97, 0X94, 0X92, 0X8F, 0X8A, + 0x75, 0x70, 0X6D, 0X6B, 0X68, 0X67, 0X64, 0X62, + 0X5E, 0X5B, 0X58, 0X57, 0X54, 0X52, 0X4F, 0X4A, + 0x34, 0x31, 0X2C, 0X2A, 0X29, 0X26, 0X25, 0X23, + 0X1C, 0X1A, 0X19, 0X16, 0X15, 0X13, 0X0E, 0X0B, + 0x80, 0x40, 0x20, 0x10, 0x08, 0x04, 0x02, 0x01 +}; + +#define ECC_START_ADDR 0x10 +#define ECC_STOP_ADDR 0x2000 +#define ECC_PATTERN 0x0101010101010101ull +#define ECC_PATTERN_CORR 0x0101010101010100ull +#define ECC_PATTERN_UNCORR 0x010101010101010Full + +static int test_ecc_error(void) +{ + unsigned long value; + unsigned long hdata, ldata, haddr, laddr; + unsigned int bit; + + int ret = 0; + + mfsdram(DDR0_23, value); + + for (bit = 0; bit < sizeof(syndrome_codes); bit++) + if (syndrome_codes[bit] == ((value >> 16) & 0xff)) + break; + + mfsdram(DDR0_00, value); + + if (value & DDR0_00_INT_STATUS_BIT0) { + debug("Bit0. A single access outside the defined PHYSICAL" + " memory space detected\n"); + mfsdram(DDR0_32, laddr); + mfsdram(DDR0_33, haddr); + debug(" addr = 0x%08x%08x\n", haddr, laddr); + ret = 1; + } + if (value & DDR0_00_INT_STATUS_BIT1) { + debug("Bit1. Multiple accesses outside the defined PHYSICAL" + " memory space detected\n"); + ret = 2; + } + if (value & DDR0_00_INT_STATUS_BIT2) { + debug("Bit2. Single correctable ECC event detected\n"); + mfsdram(DDR0_38, laddr); + mfsdram(DDR0_39, haddr); + mfsdram(DDR0_40, ldata); + mfsdram(DDR0_41, hdata); + debug(" 0x%08x - 0x%08x%08x, bit - %d\n", + laddr, hdata, ldata, bit); + ret = 3; + } + if (value & DDR0_00_INT_STATUS_BIT3) { + debug("Bit3. Multiple correctable ECC events detected\n"); + mfsdram(DDR0_38, laddr); + mfsdram(DDR0_39, haddr); + mfsdram(DDR0_40, ldata); + mfsdram(DDR0_41, hdata); + debug(" 0x%08x - 0x%08x%08x, bit - %d\n", + laddr, hdata, ldata, bit); + ret = 4; + } + if (value & DDR0_00_INT_STATUS_BIT4) { + debug("Bit4. Single uncorrectable ECC event detected\n"); + mfsdram(DDR0_34, laddr); + mfsdram(DDR0_35, haddr); + mfsdram(DDR0_36, ldata); + mfsdram(DDR0_37, hdata); + debug(" 0x%08x - 0x%08x%08x, bit - %d\n", + laddr, hdata, ldata, bit); + ret = 5; + } + if (value & DDR0_00_INT_STATUS_BIT5) { + debug("Bit5. Multiple uncorrectable ECC events detected\n"); + mfsdram(DDR0_34, laddr); + mfsdram(DDR0_35, haddr); + mfsdram(DDR0_36, ldata); + mfsdram(DDR0_37, hdata); + debug(" 0x%08x - 0x%08x%08x, bit - %d\n", + laddr, hdata, ldata, bit); + ret = 6; + } + if (value & DDR0_00_INT_STATUS_BIT6) { + debug("Bit6. DRAM initialization complete\n"); + ret = 7; + } + + /* error status cleared */ + mfsdram(DDR0_00, value); + mtsdram(DDR0_00, value | DDR0_00_INT_ACK_ALL); + + return ret; +} + +static int test_ecc(unsigned long ecc_addr) +{ + volatile unsigned long long *ecc_mem; + unsigned long value; + unsigned long ecc_data; + volatile unsigned long *lecc_mem; + int pret, ret = 0; + + sync(); + eieio(); + WATCHDOG_RESET(); + + ecc_mem = (unsigned long long *)ecc_addr; + lecc_mem = (ulong *)ecc_addr; + *ecc_mem = ECC_PATTERN; + pret = test_ecc_error(); + if (pret != 0) + ret = 1; + + /* disconnect ecc */ + mfsdram(DDR0_22, value); + mtsdram(DDR0_22, (value &~ DDR0_22_CTRL_RAW_MASK) + | DDR0_22_CTRL_RAW_ECC_DISABLE); + + /* injecting error */ + *ecc_mem = ECC_PATTERN_CORR; + + /* enable ecc */ + mfsdram(DDR0_22, value); + mtsdram(DDR0_22, (value &~ DDR0_22_CTRL_RAW_MASK) + | DDR0_22_CTRL_RAW_ECC_ENABLE); + + ecc_data = *lecc_mem; + pret = test_ecc_error(); + /* if read data ok, 1 correctable error must be fixed */ + if (pret != 3) + ret = 1; + + /* test for uncorrectable error */ + /* disconnect from ecc storage */ + mfsdram(DDR0_22, value); + mtsdram(DDR0_22, (value &~ DDR0_22_CTRL_RAW_MASK) + | DDR0_22_CTRL_RAW_NO_ECC_RAM); + + /* injecting multiply bit error */ + + *ecc_mem = ECC_PATTERN_UNCORR; + + /* enable ecc */ + mfsdram(DDR0_22, value); + mtsdram(DDR0_22, (value &~ DDR0_22_CTRL_RAW_MASK) + | DDR0_22_CTRL_RAW_ECC_ENABLE); + + ecc_data = *lecc_mem; + /* what the data should be read? */ + + pret = test_ecc_error(); + /* info about uncorrectable error must appear */ + if (pret != 5) + ret = 1; + + sync(); + eieio(); + + return ret; +} + +int ecc_post_test (int flags) +{ + int ret = 0; + unsigned long value; + unsigned long iaddr; + +#if CONFIG_DDR_ECC + sync(); + eieio(); + + /* mask all int */ + mfsdram(DDR0_01, value); + mtsdram(DDR0_01, (value &~ DDR0_01_INT_MASK_MASK) + | DDR0_01_INT_MASK_ALL_OFF); + + /* clear error status */ + mfsdram(DDR0_00, value); + mtsdram(DDR0_00, value | DDR0_00_INT_ACK_ALL); + + + /* enable full support of ECC */ + mfsdram(DDR0_22, value); + mtsdram(DDR0_22, (value &~ DDR0_22_CTRL_RAW_MASK) + | DDR0_22_CTRL_RAW_ECC_ENABLE); + + for (iaddr = ECC_START_ADDR; iaddr < ECC_STOP_ADDR; iaddr += iaddr) { + ret = test_ecc(iaddr); + if (ret) + break; + } +#endif + + return ret; + +} + +#endif /* CONFIG_POST & CFG_POST_ECC */ +#endif /* CONFIG_POST */ diff --git a/post/tests.c b/post/tests.c index f3604b249..e1c3d28f5 100644 --- a/post/tests.c +++ b/post/tests.c @@ -46,6 +46,7 @@ extern int spr_post_test (int flags); extern int sysmon_post_test (int flags); extern int dsp_post_test (int flags); extern int codec_post_test (int flags); +extern int ecc_post_test (int flags); extern int sysmon_init_f (void); @@ -236,6 +237,18 @@ struct post_test post_list[] = CFG_POST_CODEC }, #endif +#if CONFIG_POST & CFG_POST_ECC + { + "ECC test", + "ecc", + "This test checks ECC facility of memory.", + POST_ROM | POST_ALWAYS, + &ecc_post_test, + NULL, + NULL, + CFG_POST_ECC + }, +#endif }; unsigned int post_list_size = sizeof (post_list) / sizeof (struct post_test); From a71d96eac8130b53a91f93cd10c70fca0db18d52 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Fri, 20 Jul 2007 15:03:44 +0200 Subject: [PATCH 045/259] ppc4xx: Fix bug with default GPIO output value As spotted by Matthias Fuchs, the default output values for all GPIO1 outputs were not setup correctly. This patch fixes this issue. Signed-off-by: Stefan Roese --- cpu/ppc4xx/gpio.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/cpu/ppc4xx/gpio.c b/cpu/ppc4xx/gpio.c index 5235203ea..0d0e273fc 100644 --- a/cpu/ppc4xx/gpio.c +++ b/cpu/ppc4xx/gpio.c @@ -193,12 +193,12 @@ void gpio_set_chip_configuration(void) * 0 -> low level * else -> don't touch */ - reg = in32(GPIO0_OR); + reg = in32(GPIO1_OR); if (gpio_tab[gpio_core][i].out_val == GPIO_OUT_1) reg |= (0x80000000 >> (i)); else if (gpio_tab[gpio_core][i].out_val == GPIO_OUT_0) reg &= ~(0x80000000 >> (i)); - out32(GPIO0_OR, reg); + out32(GPIO1_OR, reg); reg = in32(GPIO1_TCR) | (0x80000000 >> (i)); out32(GPIO1_TCR, reg); From aedf5bde179ecfbd0a96130d18996a96518b785f Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Tue, 24 Jul 2007 07:20:09 +0200 Subject: [PATCH 046/259] ppc4xx: Fix lwmon5 interrupt controller setup (polarity, trigger...) As suggested by Hakan Eryigit, here an updated setup for the lwmon5 interrupt controller. Signed-off-by: Stefan Roese --- board/lwmon5/lwmon5.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/board/lwmon5/lwmon5.c b/board/lwmon5/lwmon5.c index b7dbba3e8..5c4cf9d25 100644 --- a/board/lwmon5/lwmon5.c +++ b/board/lwmon5/lwmon5.c @@ -45,16 +45,16 @@ int board_early_init_f(void) mtdcr(uic0sr, 0xffffffff); /* clear all. if write with 1 then the status is cleared */ mtdcr(uic0er, 0x00000000); /* disable all */ mtdcr(uic0cr, 0x00000000); /* we have not critical interrupts at the moment */ - mtdcr(uic0pr, 0xfffff7ff); /* Adjustment of the polarity */ - mtdcr(uic0tr, 0x00000810); /* per ref-board manual */ + mtdcr(uic0pr, 0xFFBFF1EF); /* Adjustment of the polarity */ + mtdcr(uic0tr, 0x00000900); /* per ref-board manual */ mtdcr(uic0vr, 0x00000000); /* int31 highest, base=0x000 is within DDRAM */ mtdcr(uic0sr, 0xffffffff); /* clear all */ mtdcr(uic1sr, 0xffffffff); /* clear all */ mtdcr(uic1er, 0x00000000); /* disable all */ mtdcr(uic1cr, 0x00000000); /* all non-critical */ - mtdcr(uic1pr, 0xFFFFC7AD); /* Adjustment of the polarity */ - mtdcr(uic1tr, 0x0600384A); /* per ref-board manual */ + mtdcr(uic1pr, 0xFFFFC6A5); /* Adjustment of the polarity */ + mtdcr(uic1tr, 0x60000040); /* per ref-board manual */ mtdcr(uic1vr, 0x00000000); /* int31 highest, base=0x000 is within DDRAM */ mtdcr(uic1sr, 0xffffffff); /* clear all */ @@ -62,9 +62,9 @@ int board_early_init_f(void) mtdcr(uic2er, 0x00000000); /* disable all */ mtdcr(uic2cr, 0x00000000); /* all non-critical */ mtdcr(uic2pr, 0x27C00000); /* Adjustment of the polarity */ - mtdcr(uic2tr, 0xDFC00000); /* per ref-board manual */ + mtdcr(uic2tr, 0x3C000000); /* per ref-board manual */ mtdcr(uic2vr, 0x00000000); /* int31 highest, base=0x000 is within DDRAM */ - mtdcr(uic2sr, 0xffffffff); /* clear all. Why this??? */ + mtdcr(uic2sr, 0xffffffff); /* clear all */ /* Trace Pins are disabled. SDR0_PFC0 Register */ mtsdr(SDR0_PFC0, 0x0); From 9f24a808f17fc0f37b7fb4805f734741335caecc Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Tue, 24 Jul 2007 09:52:52 +0200 Subject: [PATCH 047/259] ppc4xx: lwmon5: Support for 128 MByte NOR FLASH added The used Intel NOR FLASH chips have internally two dies, and are now treated as two seperate chips. Signed-off-by: Stefan Roese --- board/lwmon5/lwmon5.c | 4 ++-- include/configs/lwmon5.h | 10 ++++++---- 2 files changed, 8 insertions(+), 6 deletions(-) diff --git a/board/lwmon5/lwmon5.c b/board/lwmon5/lwmon5.c index 5c4cf9d25..66cef2fdd 100644 --- a/board/lwmon5/lwmon5.c +++ b/board/lwmon5/lwmon5.c @@ -158,13 +158,13 @@ int misc_init_r(void) (void)flash_protect(FLAG_PROTECT_SET, -CFG_MONITOR_LEN, 0xffffffff, - &flash_info[0]); + &flash_info[1]); /* Env protection ON by default */ (void)flash_protect(FLAG_PROTECT_SET, CFG_ENV_ADDR_REDUND, CFG_ENV_ADDR_REDUND + 2*CFG_ENV_SECT_SIZE - 1, - &flash_info[0]); + &flash_info[1]); /* * USB suff... diff --git a/include/configs/lwmon5.h b/include/configs/lwmon5.h index 36ead2301..55e2c94d6 100644 --- a/include/configs/lwmon5.h +++ b/include/configs/lwmon5.h @@ -46,7 +46,7 @@ #define CFG_BOOT_BASE_ADDR 0xf0000000 #define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */ -#define CFG_FLASH_BASE 0xfc000000 /* start of FLASH */ +#define CFG_FLASH_BASE 0xf8000000 /* start of FLASH */ #define CFG_MONITOR_BASE TEXT_BASE #define CFG_LIME_BASE_0 0xc0000000 #define CFG_LIME_BASE_1 0xc1000000 @@ -105,9 +105,11 @@ #define CFG_FLASH_CFI /* The flash is CFI compatible */ #define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */ -#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE } +#define CFG_FLASH0 0xFC000000 +#define CFG_FLASH1 0xF8000000 +#define CFG_FLASH_BANKS_LIST { CFG_FLASH1, CFG_FLASH0 } -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ #define CFG_MAX_FLASH_SECT 512 /* max number of sectors on one chip */ #define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ @@ -319,7 +321,7 @@ /* Memory Bank 0 (NOR-FLASH) initialization */ #define CFG_EBC_PB0AP 0x03050200 -#define CFG_EBC_PB0CR (CFG_FLASH | 0xdc000) +#define CFG_EBC_PB0CR (CFG_FLASH | 0xfc000) /* Memory Bank 1 (Lime) initialization */ #define CFG_EBC_PB1AP 0x01004380 From b66091de6c7390620312c2501db23d8391e7cabb Mon Sep 17 00:00:00 2001 From: Anatolij Gustschin Date: Thu, 26 Jul 2007 15:08:01 +0200 Subject: [PATCH 048/259] ppc4xx: lwmon5: Update Lime initialization Change Lime SDRAM initialization to now support 100MHz and 133MHz (if enabled). Also the framebuffer is initialized to display a blue rectangle with a white border. Signed-off-by: Anatolij Gustschin Signed-off-by: Stefan Roese --- board/lwmon5/lwmon5.c | 62 ++++++++++++++++++++++++++++++++++++++-- include/configs/lwmon5.h | 16 +++++++++-- 2 files changed, 73 insertions(+), 5 deletions(-) diff --git a/board/lwmon5/lwmon5.c b/board/lwmon5/lwmon5.c index 66cef2fdd..830ec1911 100644 --- a/board/lwmon5/lwmon5.c +++ b/board/lwmon5/lwmon5.c @@ -221,8 +221,8 @@ int misc_init_r(void) udelay(500); gpio_write_bit(CFG_GPIO_LIME_RST, 1); - /* Lime memory clock adjusted to 133MHz */ - out_be32((void *)CFG_LIME_SDRAM_CLOCK, CFG_LIME_CLOCK_133MHZ); + /* Lime memory clock adjusted to 100MHz */ + out_be32((void *)CFG_LIME_SDRAM_CLOCK, CFG_LIME_CLOCK_100MHZ); /* Wait untill time expired. Because of requirements in lime manual */ udelay(300); /* Write lime controller memory parameters */ @@ -237,6 +237,64 @@ int misc_init_r(void) gpio_write_bit(CFG_GPIO_PHY0_RST, 1); gpio_write_bit(CFG_GPIO_PHY1_RST, 1); + /* + * Init display controller + */ + /* Setup dot clock (internal PLL, division rate 1/16) */ + out_be32((void *)0xc1fd0100, 0x00000f00); + + /* Lime L0 init (16 bpp, 640x480) */ + out_be32((void *)0xc1fd0020, 0x801401df); + out_be32((void *)0xc1fd0024, 0x0); + out_be32((void *)0xc1fd0028, 0x0); + out_be32((void *)0xc1fd002c, 0x0); + out_be32((void *)0xc1fd0110, 0x0); + out_be32((void *)0xc1fd0114, 0x0); + out_be32((void *)0xc1fd0118, 0x01df0280); + + /* Display timing init */ + out_be32((void *)0xc1fd0004, 0x031f0000); + out_be32((void *)0xc1fd0008, 0x027f027f); + out_be32((void *)0xc1fd000c, 0x015f028f); + out_be32((void *)0xc1fd0010, 0x020c0000); + out_be32((void *)0xc1fd0014, 0x01df01ea); + out_be32((void *)0xc1fd0018, 0x0); + out_be32((void *)0xc1fd001c, 0x01e00280); + +#if 1 + /* + * Clear framebuffer using Lime's drawing engine + * (draw blue rect. with white border around it) + */ + /* Setup mode and fbbase, xres, fg, bg */ + out_be32((void *)0xc1ff0420, 0x8300); + out_be32((void *)0xc1ff0440, 0x0000); + out_be32((void *)0xc1ff0444, 0x0280); + out_be32((void *)0xc1ff0480, 0x7fff); + out_be32((void *)0xc1ff0484, 0x0000); + /* Reset clipping rectangle */ + out_be32((void *)0xc1ff0454, 0x0000); + out_be32((void *)0xc1ff0458, 0x0280); + out_be32((void *)0xc1ff045c, 0x0000); + out_be32((void *)0xc1ff0460, 0x01e0); + /* Draw white rect. */ + out_be32((void *)0xc1ff04a0, 0x09410000); + out_be32((void *)0xc1ff04a0, 0x00000000); + out_be32((void *)0xc1ff04a0, 0x01e00280); + udelay(2000); + /* Draw blue rect. */ + out_be32((void *)0xc1ff0480, 0x001f); + out_be32((void *)0xc1ff04a0, 0x09410000); + out_be32((void *)0xc1ff04a0, 0x00010001); + out_be32((void *)0xc1ff04a0, 0x01de027e); +#endif + /* Display enable, L0 layer */ + out_be32((void *)0xc1fd0100, 0x80010f00); + + /* TFT-LCD enable - PWM duty, lamp on */ + out_be32((void *)0xc4000024, 0x64); + out_be32((void *)0xc4000020, 0x701); + return 0; } diff --git a/include/configs/lwmon5.h b/include/configs/lwmon5.h index 55e2c94d6..b09b47830 100644 --- a/include/configs/lwmon5.h +++ b/include/configs/lwmon5.h @@ -341,14 +341,24 @@ * Graphics (Fujitsu Lime) *----------------------------------------------------------------------*/ /* SDRAM Clock frequency adjustment register */ -#define CFG_LIME_SDRAM_CLOCK 0xC1FC0000 -/* Lime Clock frequency is to set 133MHz */ +#define CFG_LIME_SDRAM_CLOCK 0xC1FC0038 +/* Lime Clock frequency is to set 100MHz */ +#define CFG_LIME_CLOCK_100MHZ 0x00000 +#if 0 +/* Lime Clock frequency for 133MHz */ #define CFG_LIME_CLOCK_133MHZ 0x10000 +#endif /* SDRAM Parameter register */ #define CFG_LIME_MMR 0xC1FCFFFC -/* SDRAM parameter value */ +/* SDRAM parameter value; was 0x414FB7F2, caused several vertical bars + and pixel flare on display when 133MHz was configured. According to + SDRAM chip datasheet CAS Latency is 3 for 133MHz and -75 Speed Grade */ +#ifdef CFG_LIME_CLOCK_133MHZ +#define CFG_LIME_MMR_VALUE 0x414FB7F3 +#else #define CFG_LIME_MMR_VALUE 0x414FB7F2 +#endif /*----------------------------------------------------------------------- * GPIO Setup From d4024bb72dd81695ec099b2199eda0d27c623e62 Mon Sep 17 00:00:00 2001 From: John Otken Date: Thu, 26 Jul 2007 17:49:11 +0200 Subject: [PATCH 049/259] ppc4xx: Add support for AMCC 405EP Taihu board Signed-off-by: John Otken --- MAINTAINERS | 1 + MAKEALL | 8 +- Makefile | 3 + board/amcc/taihu/Makefile | 49 ++ board/amcc/taihu/config.mk | 24 + board/amcc/taihu/flash.c | 1083 +++++++++++++++++++++++++++++++++++ board/amcc/taihu/lcd.c | 257 +++++++++ board/amcc/taihu/taihu.c | 234 ++++++++ board/amcc/taihu/u-boot.lds | 150 +++++ board/amcc/taihu/update.c | 132 +++++ common/soft_spi.c | 2 + cpu/ppc4xx/gpio.c | 2 + cpu/ppc4xx/sdram.c | 11 +- cpu/ppc4xx/start.S | 33 ++ dtt/Makefile | 2 +- dtt/ds1775.c | 156 +++++ include/configs/taihu.h | 473 +++++++++++++++ include/dtt.h | 8 + 18 files changed, 2622 insertions(+), 6 deletions(-) create mode 100644 board/amcc/taihu/Makefile create mode 100644 board/amcc/taihu/config.mk create mode 100644 board/amcc/taihu/flash.c create mode 100644 board/amcc/taihu/lcd.c create mode 100644 board/amcc/taihu/taihu.c create mode 100644 board/amcc/taihu/u-boot.lds create mode 100644 board/amcc/taihu/update.c create mode 100644 dtt/ds1775.c create mode 100644 include/configs/taihu.h diff --git a/MAINTAINERS b/MAINTAINERS index 693b11572..6dd43f861 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -248,6 +248,7 @@ Tolunay Orkun John Otken luan PPC440SP + taihu PPC405EP Keith Outwater diff --git a/MAKEALL b/MAKEALL index 127faa83a..f69134a63 100755 --- a/MAKEALL +++ b/MAKEALL @@ -88,10 +88,10 @@ LIST_4xx=" \ ml300 ocotea OCRTC ORSG \ p3p440 PCI405 pcs440ep PIP405 \ PLU405 PMC405 PPChameleonEVB sbc405 \ - sc3 sequoia sequoia_nand taishan \ - VOH405 VOM405 W7OLMC W7OLMG \ - walnut WUH405 XPEDITE1K yellowstone \ - yosemite yucca \ + sc3 sequoia sequoia_nand taihu \ + taishan VOH405 VOM405 W7OLMC \ + W7OLMG walnut WUH405 XPEDITE1K \ + yellowstone yosemite yucca \ " ######################################################################### diff --git a/Makefile b/Makefile index 3af9962e6..d4fd34e43 100644 --- a/Makefile +++ b/Makefile @@ -1254,6 +1254,9 @@ rainier_nand_config: unconfig sc3_config:unconfig @./mkconfig $(@:_config=) ppc ppc4xx sc3 +taihu_config: unconfig + @$(MKCONFIG) $(@:_config=) ppc ppc4xx taihu amcc + taishan_config: unconfig @$(MKCONFIG) $(@:_config=) ppc ppc4xx taishan amcc diff --git a/board/amcc/taihu/Makefile b/board/amcc/taihu/Makefile new file mode 100644 index 000000000..9731c6e33 --- /dev/null +++ b/board/amcc/taihu/Makefile @@ -0,0 +1,49 @@ +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS = $(BOARD).o flash.o lcd.o update.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) + +$(LIB): $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +clean: + rm -f $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/amcc/taihu/config.mk b/board/amcc/taihu/config.mk new file mode 100644 index 000000000..1bdf5e4fc --- /dev/null +++ b/board/amcc/taihu/config.mk @@ -0,0 +1,24 @@ +# +# (C) Copyright 2000 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +TEXT_BASE = 0xFFFC0000 diff --git a/board/amcc/taihu/flash.c b/board/amcc/taihu/flash.c new file mode 100644 index 000000000..290259e73 --- /dev/null +++ b/board/amcc/taihu/flash.c @@ -0,0 +1,1083 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * Modified 4/5/2001 + * Wait for completion of each sector erase command issued + * 4/5/2001 + * Chris Hallinan - DS4.COM, Inc. - clh@net1plus.com + */ + +#include +#include +#include + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ + +#undef DEBUG +#ifdef DEBUG +#define DEBUGF(x...) printf(x) +#else +#define DEBUGF(x...) +#endif /* DEBUG */ + +#define CFG_FLASH_CHAR_SIZE unsigned char +#define CFG_FLASH_CHAR_ADDR0 (0x0aaa) +#define CFG_FLASH_CHAR_ADDR1 (0x0555) +/*----------------------------------------------------------------------- + * Functions + */ +static ulong flash_get_size(vu_long * addr, flash_info_t * info); +static void flash_get_offsets(ulong base, flash_info_t * info); +static int write_word(flash_info_t * info, ulong dest, ulong data); +#ifdef FLASH_BASE1_PRELIM +static int write_word_1(flash_info_t * info, ulong dest, ulong data); +static int write_word_2(flash_info_t * info, ulong dest, ulong data); +static int flash_erase_1(flash_info_t * info, int s_first, int s_last); +static int flash_erase_2(flash_info_t * info, int s_first, int s_last); +static ulong flash_get_size_1(vu_long * addr, flash_info_t * info); +static ulong flash_get_size_2(vu_long * addr, flash_info_t * info); +#endif + +unsigned long flash_init(void) +{ + unsigned long size_b0, size_b1=0; + int i; + + /* Init: no FLASHes known */ + for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) { + flash_info[i].flash_id = FLASH_UNKNOWN; + } + + /* Static FLASH Bank configuration here - FIXME XXX */ + + size_b0 = + flash_get_size((vu_long *) FLASH_BASE0_PRELIM, &flash_info[0]); + + if (flash_info[0].flash_id == FLASH_UNKNOWN) { + printf("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", + size_b0, size_b0 << 20); + } + + if (size_b0) { + /* Setup offsets */ + flash_get_offsets(FLASH_BASE0_PRELIM, &flash_info[0]); + /* Monitor protection ON by default */ + (void)flash_protect(FLAG_PROTECT_SET, + CFG_MONITOR_BASE, + CFG_MONITOR_BASE + CFG_MONITOR_LEN - 1, + &flash_info[0]); +#ifdef CFG_ENV_IS_IN_FLASH + (void)flash_protect(FLAG_PROTECT_SET, CFG_ENV_ADDR, + CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1, + &flash_info[0]); + (void)flash_protect(FLAG_PROTECT_SET, CFG_ENV_ADDR_REDUND, + CFG_ENV_ADDR_REDUND + CFG_ENV_SECT_SIZE - 1, + &flash_info[0]); +#endif + /* Also protect sector containing initial power-up instruction */ + /* (flash_protect() checks address range - other call ignored) */ + (void)flash_protect(FLAG_PROTECT_SET, + 0xFFFFFFFC, 0xFFFFFFFF, &flash_info[0]); + + flash_info[0].size = size_b0; + } +#ifdef FLASH_BASE1_PRELIM + size_b1 = + flash_get_size((vu_long *) FLASH_BASE1_PRELIM, &flash_info[1])*2; + + if (flash_info[1].flash_id == FLASH_UNKNOWN) { + printf("## Unknown FLASH on Bank 1 - Size = 0x%08lx = %ld MB\n", + size_b1, size_b1 << 20); + } + + if (size_b1) { + /* Setup offsets */ + flash_get_offsets(FLASH_BASE1_PRELIM, &flash_info[1]); + flash_info[1].size = size_b1; + } +#endif + return (size_b0 + size_b1); +} + +static void flash_get_offsets(ulong base, flash_info_t * info) +{ + int i; + + /* set up sector start address table */ + if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) || + (info->flash_id == FLASH_AM040)) { + for (i = 0; i < info->sector_count; i++) + info->start[i] = base + (i * 0x00010000); + } else if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMLV128U) { + for (i = 0; i < info->sector_count; i++) { + info->start[i] = base + (i * 0x00010000*2); + } + } else if ((info->flash_id & FLASH_TYPEMASK) == FLASH_S29GL128N ) { + for (i = 0; i < info->sector_count; i++) { + info->start[i] = base + (i * 0x00020000*2); + } + } else { + if (info->flash_id & FLASH_BTYPE) { + /* set sector offsets for bottom boot block type */ + info->start[0] = base + 0x00000000; + info->start[1] = base + 0x00004000; + info->start[2] = base + 0x00006000; + info->start[3] = base + 0x00008000; + for (i = 4; i < info->sector_count; i++) { + info->start[i] = + base + (i * 0x00010000) - 0x00030000; + } + } else { + /* set sector offsets for top boot block type */ + i = info->sector_count - 1; + info->start[i--] = base + info->size - 0x00004000; + info->start[i--] = base + info->size - 0x00006000; + info->start[i--] = base + info->size - 0x00008000; + for (; i >= 0; i--) { + info->start[i] = base + i * 0x00010000; + } + } + } +} + + +void flash_print_info(flash_info_t * info) +{ + int i; + int k; + int size; + int erased; + volatile unsigned long *flash; + + if (info->flash_id == FLASH_UNKNOWN) { + printf("missing or unknown FLASH type\n"); + return; + } + + switch (info->flash_id & FLASH_VENDMASK) { + case FLASH_MAN_AMD: + printf("AMD "); + break; + case FLASH_MAN_STM: + printf("STM "); + break; + case FLASH_MAN_FUJ: + printf("FUJITSU "); + break; + case FLASH_MAN_SST: + printf("SST "); + break; + default: + printf("Unknown Vendor "); + break; + } + + switch (info->flash_id & FLASH_TYPEMASK) { + case FLASH_AM040: + printf("AM29F040 (512 Kbit, uniform sector size)\n"); + break; + case FLASH_AM400B: + printf("AM29LV400B (4 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM400T: + printf("AM29LV400T (4 Mbit, top boot sector)\n"); + break; + case FLASH_AM800B: + printf("AM29LV800B (8 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM800T: + printf("AM29LV800T (8 Mbit, top boot sector)\n"); + break; + case FLASH_AMD016: + printf("AM29F016D (16 Mbit, uniform sector size)\n"); + break; + case FLASH_AM160B: + printf("AM29LV160B (16 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM160T: + printf("AM29LV160T (16 Mbit, top boot sector)\n"); + break; + case FLASH_AM320B: + printf("AM29LV320B (32 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM320T: + printf("AM29LV320T (32 Mbit, top boot sector)\n"); + break; + case FLASH_AM033C: + printf("AM29LV033C (32 Mbit, top boot sector)\n"); + break; + case FLASH_AMLV128U: + printf("AM29LV128U (128 Mbit * 2, top boot sector)\n"); + break; + case FLASH_SST800A: + printf("SST39LF/VF800 (8 Mbit, uniform sector size)\n"); + break; + case FLASH_SST160A: + printf("SST39LF/VF160 (16 Mbit, uniform sector size)\n"); + break; + case FLASH_STMW320DT: + printf ("M29W320DT (32 M, top sector)\n"); + break; + case FLASH_S29GL128N: + printf ("S29GL128N (256 Mbit, uniform sector size)\n"); + break; + default: + printf("Unknown Chip Type\n"); + break; + } + + printf(" Size: %ld KB in %d Sectors\n", + info->size >> 10, info->sector_count); + + printf(" Sector Start Addresses:"); + for (i = 0; i < info->sector_count; ++i) { + /* + * Check if whole sector is erased + */ + if (i != (info->sector_count - 1)) + size = info->start[i + 1] - info->start[i]; + else + size = info->start[0] + info->size - info->start[i]; + erased = 1; + flash = (volatile unsigned long *)info->start[i]; + size = size >> 2; /* divide by 4 for longword access */ + for (k = 0; k < size; k++) { + if (*flash++ != 0xffffffff) { + erased = 0; + break; + } + } + + if ((i % 5) == 0) + printf("\n "); + printf(" %08lX%s%s", + info->start[i], + erased ? " E" : " ", info->protect[i] ? "RO " : " "); + } + printf("\n"); + return; +} + + +/* + * The following code cannot be run from FLASH! + */ +#ifdef FLASH_BASE1_PRELIM +static ulong flash_get_size(vu_long * addr, flash_info_t * info) +{ + if ((ulong)addr == FLASH_BASE1_PRELIM) { + return flash_get_size_2(addr, info); + } else { + return flash_get_size_1(addr, info); + } +} + +static ulong flash_get_size_1(vu_long * addr, flash_info_t * info) +#else +static ulong flash_get_size(vu_long * addr, flash_info_t * info) +#endif +{ + short i; + CFG_FLASH_WORD_SIZE value; + ulong base = (ulong) addr; + volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *) addr; + + DEBUGF("FLASH ADDR: %08x\n", (unsigned)addr); + + /* Write auto select command: read Manufacturer ID */ + addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA; + addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055; + addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00900090; + udelay(1000); + + value = addr2[0]; + DEBUGF("FLASH MANUFACT: %x\n", value); + + switch (value) { + case (CFG_FLASH_WORD_SIZE) AMD_MANUFACT: + info->flash_id = FLASH_MAN_AMD; + break; + case (CFG_FLASH_WORD_SIZE) FUJ_MANUFACT: + info->flash_id = FLASH_MAN_FUJ; + break; + case (CFG_FLASH_WORD_SIZE) SST_MANUFACT: + info->flash_id = FLASH_MAN_SST; + break; + case (CFG_FLASH_WORD_SIZE) STM_MANUFACT: + info->flash_id = FLASH_MAN_STM; + break; + default: + info->flash_id = FLASH_UNKNOWN; + info->sector_count = 0; + info->size = 0; + return 0; /* no or unknown flash */ + } + + value = addr2[1]; /* device ID */ + DEBUGF("\nFLASH DEVICEID: %x\n", value); + + switch (value) { + case (CFG_FLASH_WORD_SIZE) AMD_ID_LV040B: + info->flash_id += FLASH_AM040; + info->sector_count = 8; + info->size = 0x0080000; /* => 512 ko */ + break; + + case (CFG_FLASH_WORD_SIZE) AMD_ID_F040B: + info->flash_id += FLASH_AM040; + info->sector_count = 8; + info->size = 0x0080000; /* => 512 ko */ + break; + + case (CFG_FLASH_WORD_SIZE) STM_ID_M29W040B: + info->flash_id += FLASH_AM040; + info->sector_count = 8; + info->size = 0x0080000; /* => 512 ko */ + break; + + case (CFG_FLASH_WORD_SIZE) AMD_ID_F016D: + info->flash_id += FLASH_AMD016; + info->sector_count = 32; + info->size = 0x00200000; + break; /* => 2 MB */ + + case (CFG_FLASH_WORD_SIZE) AMD_ID_LV033C: + info->flash_id += FLASH_AMDLV033C; + info->sector_count = 64; + info->size = 0x00400000; + break; /* => 4 MB */ + + case (CFG_FLASH_WORD_SIZE) AMD_ID_LV400T: + info->flash_id += FLASH_AM400T; + info->sector_count = 11; + info->size = 0x00080000; + break; /* => 0.5 MB */ + + case (CFG_FLASH_WORD_SIZE) AMD_ID_LV400B: + info->flash_id += FLASH_AM400B; + info->sector_count = 11; + info->size = 0x00080000; + break; /* => 0.5 MB */ + + case (CFG_FLASH_WORD_SIZE) AMD_ID_LV800T: + info->flash_id += FLASH_AM800T; + info->sector_count = 19; + info->size = 0x00100000; + break; /* => 1 MB */ + + case (CFG_FLASH_WORD_SIZE) AMD_ID_LV800B: + info->flash_id += FLASH_AM800B; + info->sector_count = 19; + info->size = 0x00100000; + break; /* => 1 MB */ + + case (CFG_FLASH_WORD_SIZE) AMD_ID_LV160T: + info->flash_id += FLASH_AM160T; + info->sector_count = 35; + info->size = 0x00200000; + break; /* => 2 MB */ + + case (CFG_FLASH_WORD_SIZE) AMD_ID_LV160B: + info->flash_id += FLASH_AM160B; + info->sector_count = 35; + info->size = 0x00200000; + break; /* => 2 MB */ + default: + info->flash_id = FLASH_UNKNOWN; + return 0; /* => no or unknown flash */ + } + + /* set up sector start address table */ + if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) || + ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) || + ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMD016)) { + for (i = 0; i < info->sector_count; i++) + info->start[i] = base + (i * 0x00010000); + } + else if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMLV128U) { + for (i = 0; i < info->sector_count; i++) + info->start[i] = base + (i * 0x00010000 * 2); + } else { + if (info->flash_id & FLASH_BTYPE) { + /* set sector offsets for bottom boot block type */ + info->start[0] = base + 0x00000000; + info->start[1] = base + 0x00004000; + info->start[2] = base + 0x00006000; + info->start[3] = base + 0x00008000; + for (i = 4; i < info->sector_count; i++) { + info->start[i] = + base + (i * 0x00010000) - 0x00030000; + } + } else { + /* set sector offsets for top boot block type */ + i = info->sector_count - 1; + info->start[i--] = base + info->size - 0x00004000; + info->start[i--] = base + info->size - 0x00006000; + info->start[i--] = base + info->size - 0x00008000; + for (; i >= 0; i--) { + info->start[i] = base + i * 0x00010000; + } + } + } + + /* check for protected sectors */ + for (i = 0; i < info->sector_count; i++) { + /* read sector protection at sector address, (A7 .. A0) = 0x02 */ + /* D0 = 1 if protected */ + addr2 = (volatile CFG_FLASH_WORD_SIZE *)(info->start[i]); + + /* For AMD29033C flash we need to resend the command of * + * reading flash protection for upper 8 Mb of flash */ + if (i == 32) { + addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0xAAAAAAAA; + addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x55555555; + addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x90909090; + } + + if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) + info->protect[i] = 0; + else + info->protect[i] = addr2[2] & 1; + } + + /* issue bank reset to return to read mode */ + addr2[0] = (CFG_FLASH_WORD_SIZE) 0x00F000F0; + + return info->size; +} + +static int wait_for_DQ7_1(flash_info_t * info, int sect) +{ + ulong start, now, last; + volatile CFG_FLASH_WORD_SIZE *addr = + (CFG_FLASH_WORD_SIZE *) (info->start[sect]); + + start = get_timer(0); + last = start; + while ((addr[0] & (CFG_FLASH_WORD_SIZE) 0x00800080) != + (CFG_FLASH_WORD_SIZE) 0x00800080) { + if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + printf("Timeout\n"); + return -1; + } + /* show that we're waiting */ + if ((now - last) > 1000) { /* every second */ + putc('.'); + last = now; + } + } + return 0; +} + +#ifdef FLASH_BASE1_PRELIM +int flash_erase(flash_info_t * info, int s_first, int s_last) +{ + if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320B) || + ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320T) || + ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMLV128U) || + ((info->flash_id & FLASH_TYPEMASK) == FLASH_S29GL128N) || + ((info->flash_id & FLASH_TYPEMASK) == FLASH_STMW320DT)) { + return flash_erase_2(info, s_first, s_last); + } else { + return flash_erase_1(info, s_first, s_last); + } +} + +static int flash_erase_1(flash_info_t * info, int s_first, int s_last) +#else +int flash_erase(flash_info_t * info, int s_first, int s_last) +#endif +{ + volatile CFG_FLASH_WORD_SIZE *addr = (CFG_FLASH_WORD_SIZE *) (info->start[0]); + volatile CFG_FLASH_WORD_SIZE *addr2; + int flag, prot, sect, l_sect; + int i; + + if ((s_first < 0) || (s_first > s_last)) { + if (info->flash_id == FLASH_UNKNOWN) { + printf("- missing\n"); + } else { + printf("- no sectors to erase\n"); + } + return 1; + } + + if (info->flash_id == FLASH_UNKNOWN) { + printf("Can't erase unknown flash type - aborted\n"); + return 1; + } + + prot = 0; + for (sect = s_first; sect <= s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + + if (prot) { + printf("- Warning: %d protected sectors will not be erased!\n", + prot); + } else { + printf("\n"); + } + + l_sect = -1; + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + /* Start erase on unprotected sectors */ + for (sect = s_first; sect <= s_last; sect++) { + if (info->protect[sect] == 0) { /* not protected */ + addr2 = (CFG_FLASH_WORD_SIZE *) (info->start[sect]); + + if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) { + addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA; + addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055; + addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00800080; + addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA; + addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055; + addr2[0] = (CFG_FLASH_WORD_SIZE) 0x00500050; /* block erase */ + for (i = 0; i < 50; i++) + udelay(1000); /* wait 1 ms */ + } else { + addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA; + addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055; + addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00800080; + addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA; + addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055; + addr2[0] = (CFG_FLASH_WORD_SIZE) 0x00300030; /* sector erase */ + } + l_sect = sect; + /* + * Wait for each sector to complete, it's more + * reliable. According to AMD Spec, you must + * issue all erase commands within a specified + * timeout. This has been seen to fail, especially + * if printf()s are included (for debug)!! + */ + wait_for_DQ7_1(info, sect); + } + } + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + /* wait at least 80us - let's wait 1 ms */ + udelay(1000); + + /* reset to read mode */ + addr = (CFG_FLASH_WORD_SIZE *) info->start[0]; + addr[0] = (CFG_FLASH_WORD_SIZE) 0x00F000F0; /* reset bank */ + + printf(" done\n"); + return 0; +} + +/*----------------------------------------------------------------------- + * Copy memory to flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt) +{ + ulong cp, wp, data; + int i, l, rc; + + wp = (addr & ~3); /* get lower word aligned address */ + + /* + * handle unaligned start bytes + */ + if ((l = addr - wp) != 0) { + data = 0; + for (i = 0, cp = wp; i < l; ++i, ++cp) { + data = (data << 8) | (*(uchar *) cp); + } + for (; i < 4 && cnt > 0; ++i) { + data = (data << 8) | *src++; + --cnt; + ++cp; + } + for (; cnt == 0 && i < 4; ++i, ++cp) { + data = (data << 8) | (*(uchar *) cp); + } + + if ((rc = write_word(info, wp, data)) != 0) { + return rc; + } + wp += 4; + } + + /* + * handle word aligned part + */ + while (cnt >= 4) { + data = 0; + for (i = 0; i < 4; ++i) { + data = (data << 8) | *src++; + } + if ((rc = write_word(info, wp, data)) != 0) { + return rc; + } + wp += 4; + cnt -= 4; + } + + if (cnt == 0) { + return 0; + } + + /* + * handle unaligned tail bytes + */ + data = 0; + for (i = 0, cp = wp; i < 4 && cnt > 0; ++i, ++cp) { + data = (data << 8) | *src++; + --cnt; + } + for (; i < 4; ++i, ++cp) { + data = (data << 8) | (*(uchar *) cp); + } + + return (write_word(info, wp, data)); +} + +/*----------------------------------------------------------------------- + * Copy memory to flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +#ifdef FLASH_BASE1_PRELIM +static int write_word(flash_info_t * info, ulong dest, ulong data) +{ + if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320B) || + ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320T) || + ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMLV128U) || + ((info->flash_id & FLASH_TYPEMASK) == FLASH_S29GL128N) || + ((info->flash_id & FLASH_TYPEMASK) == FLASH_STMW320DT)) { + return write_word_2(info, dest, data); + } else { + return write_word_1(info, dest, data); + } +} + +static int write_word_1(flash_info_t * info, ulong dest, ulong data) +#else +static int write_word(flash_info_t * info, ulong dest, ulong data) +#endif +{ + volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *) (info->start[0]); + volatile CFG_FLASH_WORD_SIZE *dest2 = (CFG_FLASH_WORD_SIZE *) dest; + volatile CFG_FLASH_WORD_SIZE *data2 = (CFG_FLASH_WORD_SIZE *) & data; + ulong start; + int i; + + /* Check if Flash is (sufficiently) erased */ + if ((*((vu_long *)dest) & data) != data) { + return 2; + } + + for (i = 0; i < 4 / sizeof(CFG_FLASH_WORD_SIZE); i++) { + int flag; + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA; + addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055; + addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00A000A0; + + dest2[i] = data2[i]; + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + /* data polling for D7 */ + start = get_timer(0); + while ((dest2[i] & (CFG_FLASH_WORD_SIZE) 0x00800080) != + (data2[i] & (CFG_FLASH_WORD_SIZE) 0x00800080)) { + + if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + return 1; + } + } + } + + return 0; +} + +#ifdef FLASH_BASE1_PRELIM + +/* + * The following code cannot be run from FLASH! + */ +static ulong flash_get_size_2(vu_long * addr, flash_info_t * info) +{ + short i; + CFG_FLASH_CHAR_SIZE value; + ulong base = (ulong) addr; + volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *) addr; + + DEBUGF("FLASH ADDR: %08x\n", (unsigned)addr); + + /* Write auto select command: read Manufacturer ID */ + addr2[CFG_FLASH_CHAR_ADDR0] = (CFG_FLASH_WORD_SIZE) 0xAAAAAAAA; + addr2[CFG_FLASH_CHAR_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x55555555; + addr2[CFG_FLASH_CHAR_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x90909090; + udelay(1000); + + value = (CFG_FLASH_CHAR_SIZE)addr2[0]; + DEBUGF("FLASH MANUFACT: %x\n", value); + + switch (value) { + case (CFG_FLASH_CHAR_SIZE) AMD_MANUFACT: + info->flash_id = FLASH_MAN_AMD; + break; + case (CFG_FLASH_CHAR_SIZE) FUJ_MANUFACT: + info->flash_id = FLASH_MAN_FUJ; + break; + case (CFG_FLASH_CHAR_SIZE) SST_MANUFACT: + info->flash_id = FLASH_MAN_SST; + break; + case (CFG_FLASH_CHAR_SIZE) STM_MANUFACT: + info->flash_id = FLASH_MAN_STM; + break; + default: + info->flash_id = FLASH_UNKNOWN; + info->sector_count = 0; + info->size = 0; + return 0; /* no or unknown flash */ + } + + value = (CFG_FLASH_CHAR_SIZE)addr2[2]; /* device ID */ + DEBUGF("\nFLASH DEVICEID: %x\n", value); + + switch (value) { + case (CFG_FLASH_CHAR_SIZE) AMD_ID_LV040B: + info->flash_id += FLASH_AM040; + info->sector_count = 8; + info->size = 0x0080000; /* => 512 ko */ + break; + + case (CFG_FLASH_CHAR_SIZE) AMD_ID_F040B: + info->flash_id += FLASH_AM040; + info->sector_count = 8; + info->size = 0x0080000; /* => 512 ko */ + break; + + case (CFG_FLASH_CHAR_SIZE) STM_ID_M29W040B: + info->flash_id += FLASH_AM040; + info->sector_count = 8; + info->size = 0x0080000; /* => 512 ko */ + break; + + case (CFG_FLASH_CHAR_SIZE) AMD_ID_F016D: + info->flash_id += FLASH_AMD016; + info->sector_count = 32; + info->size = 0x00200000; + break; /* => 2 MB */ + + case (CFG_FLASH_CHAR_SIZE) AMD_ID_LV033C: + info->flash_id += FLASH_AMDLV033C; + info->sector_count = 64; + info->size = 0x00400000; + break; /* => 4 MB */ + + case (CFG_FLASH_CHAR_SIZE) AMD_ID_LV400T: + info->flash_id += FLASH_AM400T; + info->sector_count = 11; + info->size = 0x00080000; + break; /* => 0.5 MB */ + + case (CFG_FLASH_CHAR_SIZE) AMD_ID_LV400B: + info->flash_id += FLASH_AM400B; + info->sector_count = 11; + info->size = 0x00080000; + break; /* => 0.5 MB */ + + case (CFG_FLASH_CHAR_SIZE) AMD_ID_LV800T: + info->flash_id += FLASH_AM800T; + info->sector_count = 19; + info->size = 0x00100000; + break; /* => 1 MB */ + + case (CFG_FLASH_CHAR_SIZE) AMD_ID_LV800B: + info->flash_id += FLASH_AM800B; + info->sector_count = 19; + info->size = 0x00100000; + break; /* => 1 MB */ + + case (CFG_FLASH_CHAR_SIZE) AMD_ID_LV160T: + info->flash_id += FLASH_AM160T; + info->sector_count = 35; + info->size = 0x00200000; + break; /* => 2 MB */ + + case (CFG_FLASH_CHAR_SIZE) AMD_ID_LV160B: + info->flash_id += FLASH_AM160B; + info->sector_count = 35; + info->size = 0x00200000; + break; /* => 2 MB */ + case (CFG_FLASH_CHAR_SIZE) AMD_ID_MIRROR: + if ((CFG_FLASH_CHAR_SIZE)addr2[0x1c] == (CFG_FLASH_CHAR_SIZE)AMD_ID_LV128U_2 + && (CFG_FLASH_CHAR_SIZE)addr2[0x1e] == (CFG_FLASH_CHAR_SIZE)AMD_ID_LV128U_3) { + info->flash_id += FLASH_AMLV128U; + info->sector_count = 256; + info->size = 0x01000000; + } else if ((CFG_FLASH_CHAR_SIZE)addr2[0x1c] == (CFG_FLASH_CHAR_SIZE)AMD_ID_GL128N_2 + && (CFG_FLASH_CHAR_SIZE)addr2[0x1e] == (CFG_FLASH_CHAR_SIZE)AMD_ID_GL128N_3 ) { + info->flash_id += FLASH_S29GL128N; + info->sector_count = 128; + info->size = 0x01000000; + } + else + info->flash_id = FLASH_UNKNOWN; + break; /* => 2 MB */ + + default: + info->flash_id = FLASH_UNKNOWN; + return 0; /* => no or unknown flash */ + } + + /* set up sector start address table */ + if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) || + ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) || + ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMD016)) { + for (i = 0; i < info->sector_count; i++) + info->start[i] = base + (i * 0x00010000); + } else if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMLV128U) { + for (i = 0; i < info->sector_count; i++) + info->start[i] = base + (i * 0x00010000); + } else if ((info->flash_id & FLASH_TYPEMASK) == FLASH_S29GL128N ) { + for (i = 0; i < info->sector_count; i++) + info->start[i] = base + (i * 0x00020000); + } else { + if (info->flash_id & FLASH_BTYPE) { + /* set sector offsets for bottom boot block type */ + info->start[0] = base + 0x00000000; + info->start[1] = base + 0x00004000; + info->start[2] = base + 0x00006000; + info->start[3] = base + 0x00008000; + for (i = 4; i < info->sector_count; i++) { + info->start[i] = + base + (i * 0x00010000) - 0x00030000; + } + } else { + /* set sector offsets for top boot block type */ + i = info->sector_count - 1; + info->start[i--] = base + info->size - 0x00004000; + info->start[i--] = base + info->size - 0x00006000; + info->start[i--] = base + info->size - 0x00008000; + for (; i >= 0; i--) { + info->start[i] = base + i * 0x00010000; + } + } + } + + /* check for protected sectors */ + for (i = 0; i < info->sector_count; i++) { + /* read sector protection at sector address, (A7 .. A0) = 0x02 */ + /* D0 = 1 if protected */ + addr2 = (volatile CFG_FLASH_WORD_SIZE *)(info->start[i]); + + /* For AMD29033C flash we need to resend the command of * + * reading flash protection for upper 8 Mb of flash */ + if (i == 32) { + addr2[CFG_FLASH_CHAR_ADDR0] = (CFG_FLASH_WORD_SIZE) 0xAAAAAAAA; + addr2[CFG_FLASH_CHAR_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x55555555; + addr2[CFG_FLASH_CHAR_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x90909090; + } + + if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) + info->protect[i] = 0; + else + info->protect[i] = (CFG_FLASH_CHAR_SIZE)addr2[4] & 1; + } + + /* issue bank reset to return to read mode */ + addr2[0] = (CFG_FLASH_WORD_SIZE) 0xF0F0F0F0; + return info->size; +} + +static int wait_for_DQ7_2(flash_info_t * info, int sect) +{ + ulong start, now, last; + volatile CFG_FLASH_WORD_SIZE *addr = + (CFG_FLASH_WORD_SIZE *) (info->start[sect]); + + start = get_timer(0); + last = start; + while (((CFG_FLASH_WORD_SIZE)addr[0] & (CFG_FLASH_WORD_SIZE) 0x80808080) != + (CFG_FLASH_WORD_SIZE) 0x80808080) { + if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + printf("Timeout\n"); + return -1; + } + /* show that we're waiting */ + if ((now - last) > 1000) { /* every second */ + putc('.'); + last = now; + } + } + return 0; +} + +static int flash_erase_2(flash_info_t * info, int s_first, int s_last) +{ + volatile CFG_FLASH_WORD_SIZE *addr = (CFG_FLASH_WORD_SIZE *) (info->start[0]); + volatile CFG_FLASH_WORD_SIZE *addr2; + int flag, prot, sect, l_sect; + int i; + + if ((s_first < 0) || (s_first > s_last)) { + if (info->flash_id == FLASH_UNKNOWN) { + printf("- missing\n"); + } else { + printf("- no sectors to erase\n"); + } + return 1; + } + + if (info->flash_id == FLASH_UNKNOWN) { + printf("Can't erase unknown flash type - aborted\n"); + return 1; + } + + prot = 0; + for (sect = s_first; sect <= s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + + if (prot) { + printf("- Warning: %d protected sectors will not be erased!\n", + prot); + } else { + printf("\n"); + } + + l_sect = -1; + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + /* Start erase on unprotected sectors */ + for (sect = s_first; sect <= s_last; sect++) { + if (info->protect[sect] == 0) { /* not protected */ + addr2 = (CFG_FLASH_WORD_SIZE *) (info->start[sect]); + + if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) { + addr[CFG_FLASH_CHAR_ADDR0] = (CFG_FLASH_WORD_SIZE) 0xAAAAAAAA; + addr[CFG_FLASH_CHAR_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x55555555; + addr[CFG_FLASH_CHAR_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x80808080; + addr[CFG_FLASH_CHAR_ADDR0] = (CFG_FLASH_WORD_SIZE) 0xAAAAAAAA; + addr[CFG_FLASH_CHAR_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x55555555; + addr2[0] = (CFG_FLASH_WORD_SIZE) 0x50505050; /* block erase */ + for (i = 0; i < 50; i++) + udelay(1000); /* wait 1 ms */ + } else { + addr[CFG_FLASH_CHAR_ADDR0] = (CFG_FLASH_WORD_SIZE) 0xAAAAAAAA; + addr[CFG_FLASH_CHAR_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x55555555; + addr[CFG_FLASH_CHAR_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x80808080; + addr[CFG_FLASH_CHAR_ADDR0] = (CFG_FLASH_WORD_SIZE) 0xAAAAAAAA; + addr[CFG_FLASH_CHAR_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x55555555; + addr2[0] = (CFG_FLASH_WORD_SIZE) 0x30303030; /* sector erase */ + } + l_sect = sect; + /* + * Wait for each sector to complete, it's more + * reliable. According to AMD Spec, you must + * issue all erase commands within a specified + * timeout. This has been seen to fail, especially + * if printf()s are included (for debug)!! + */ + wait_for_DQ7_2(info, sect); + } + } + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + /* wait at least 80us - let's wait 1 ms */ + udelay(1000); + + /* reset to read mode */ + addr = (CFG_FLASH_WORD_SIZE *) info->start[0]; + addr[0] = (CFG_FLASH_WORD_SIZE) 0xF0F0F0F0; /* reset bank */ + + printf(" done\n"); + return 0; +} + +static int write_word_2(flash_info_t * info, ulong dest, ulong data) +{ + volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *) (info->start[0]); + volatile CFG_FLASH_WORD_SIZE *dest2 = (CFG_FLASH_WORD_SIZE *) dest; + volatile CFG_FLASH_WORD_SIZE *data2 = (CFG_FLASH_WORD_SIZE *) & data; + ulong start; + int i; + + /* Check if Flash is (sufficiently) erased */ + if ((*((vu_long *)dest) & data) != data) { + return 2; + } + + for (i = 0; i < 4 / sizeof(CFG_FLASH_WORD_SIZE); i++) { + int flag; + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + addr2[CFG_FLASH_CHAR_ADDR0] = (CFG_FLASH_WORD_SIZE) 0xAAAAAAAA; + addr2[CFG_FLASH_CHAR_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x55555555; + addr2[CFG_FLASH_CHAR_ADDR0] = (CFG_FLASH_WORD_SIZE) 0xA0A0A0A0; + + dest2[i] = data2[i]; + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + /* data polling for D7 */ + start = get_timer(0); + while ((dest2[i] & (CFG_FLASH_WORD_SIZE) 0x80808080) != + (data2[i] & (CFG_FLASH_WORD_SIZE) 0x80808080)) { + + if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + return 1; + } + } + } + + return 0; +} + +#endif /* FLASH_BASE1_PRELIM */ diff --git a/board/amcc/taihu/lcd.c b/board/amcc/taihu/lcd.c new file mode 100644 index 000000000..3d042dfa7 --- /dev/null +++ b/board/amcc/taihu/lcd.c @@ -0,0 +1,257 @@ +/* + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include + +#define LCD_CMD_ADDR 0x50100002 +#define LCD_DATA_ADDR 0x50100003 +#define LCD_BLK_CTRL CPLD_REG1_ADDR + +static char *amcc_logo = "AMCC 405EP TAIHU EVALUATION KIT"; +static int addr_flag = 0x80; + +static void lcd_bl_ctrl(char val) +{ + out_8((u8 *) LCD_BLK_CTRL, in_8((u8 *) LCD_BLK_CTRL) | val); +} + +static void lcd_putc(int val) +{ + int i = 100; + char addr; + + while (i--) { + if ((in_8((u8 *) LCD_CMD_ADDR) & 0x80) != 0x80) { /*BF = 1 ?*/ + udelay(50); + break; + } + udelay(50); + } + + if (in_8((u8 *) LCD_CMD_ADDR) & 0x80) { + printf("LCD is busy\n"); + return; + } + + addr = in_8((u8 *) LCD_CMD_ADDR); + udelay(50); + if ((addr != 0) && (addr % 0x10 == 0)) { + addr_flag ^= 0x40; + out_8((u8 *) LCD_CMD_ADDR, addr_flag); + } + + udelay(50); + out_8((u8 *) LCD_DATA_ADDR, val); + udelay(50); +} + +static void lcd_puts(char *s) +{ + char *p = s; + int i = 100; + + while (i--) { + if ((in_8((u8 *) LCD_CMD_ADDR) & 0x80) != 0x80) { /*BF = 1 ?*/ + udelay(50); + break; + } + udelay(50); + } + + if (in_8((u8 *) LCD_CMD_ADDR) & 0x80) { + printf("LCD is busy\n"); + return; + } + + while (*p) + lcd_putc(*p++); +} + +static void lcd_put_logo(void) +{ + int i = 100; + char *p = amcc_logo; + + while (i--) { + if ((in_8((u8 *) LCD_CMD_ADDR) & 0x80) != 0x80) { /*BF = 1 ?*/ + udelay(50); + break; + } + udelay(50); + } + + if (in_8((u8 *) LCD_CMD_ADDR) & 0x80) { + printf("LCD is busy\n"); + return; + } + + out_8((u8 *) LCD_CMD_ADDR, 0x80); + while (*p) + lcd_putc(*p++); +} + +int lcd_init(void) +{ + puts("LCD: "); + out_8((u8 *) LCD_CMD_ADDR, 0x38); /* set function:8-bit,2-line,5x7 font type */ + udelay(50); + out_8((u8 *) LCD_CMD_ADDR, 0x0f); /* set display on,cursor on,blink on */ + udelay(50); + out_8((u8 *) LCD_CMD_ADDR, 0x01); /* display clear */ + udelay(2000); + out_8((u8 *) LCD_CMD_ADDR, 0x06); /* set entry */ + udelay(50); + lcd_bl_ctrl(0x02); /* set backlight on */ + lcd_put_logo(); + puts("ready\n"); + + return 0; +} + +static int do_lcd_clear (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) +{ + out_8((u8 *) LCD_CMD_ADDR, 0x01); + udelay(2000); + + return 0; +} + +static int do_lcd_puts (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) +{ + if (argc < 2) { + printf("%s", cmdtp->usage); + return 1; + } + lcd_puts(argv[1]); + + return 0; +} + +static int do_lcd_putc (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) +{ + if (argc < 2) { + printf("%s", cmdtp->usage); + return 1; + } + lcd_putc((char)argv[1][0]); + + return 0; +} + +static int do_lcd_cur (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) +{ + ulong count; + ulong dir; + char cur_addr; + + if (argc < 3) { + printf("%s", cmdtp->usage); + return 1; + } + + count = simple_strtoul(argv[1], NULL, 16); + if (count > 31) { + printf("unable to shift > 0x20\n"); + count = 0; + } + + dir = simple_strtoul(argv[2], NULL, 16); + cur_addr = in_8((u8 *) LCD_CMD_ADDR); + udelay(50); + + if (dir == 0x0) { + if (addr_flag == 0x80) { + if (count >= (cur_addr & 0xf)) { + out_8((u8 *) LCD_CMD_ADDR, 0x80); + udelay(50); + count = 0; + } + } else { + if (count >= ((cur_addr & 0x0f) + 0x0f)) { + out_8((u8 *) LCD_CMD_ADDR, 0x80); + addr_flag = 0x80; + udelay(50); + count = 0x0; + } else if (count >= ( cur_addr & 0xf)) { + count -= cur_addr & 0xf ; + out_8((u8 *) LCD_CMD_ADDR, 0x80 | 0xf); + addr_flag = 0x80; + udelay(50); + } + } + } else { + if (addr_flag == 0x80) { + if (count >= (0x1f - (cur_addr & 0xf))) { + count = 0x0; + addr_flag = 0xc0; + out_8((u8 *) LCD_CMD_ADDR, 0xc0 | 0xf); + udelay(50); + } else if ((count + (cur_addr & 0xf ))>= 0x0f) { + count = count + (cur_addr & 0xf) - 0x0f; + addr_flag = 0xc0; + out_8((u8 *) LCD_CMD_ADDR, 0xc0); + udelay(50); + } + } else if ((count + (cur_addr & 0xf )) >= 0x0f) { + count = 0x0; + out_8((u8 *) LCD_CMD_ADDR, 0xC0 | 0x0F); + udelay(50); + } + } + while (count--) { + if (dir == 0) + out_8((u8 *) LCD_CMD_ADDR, 0x10); + else + out_8((u8 *) LCD_CMD_ADDR, 0x14); + udelay(50); + } + + return 0; +} + +U_BOOT_CMD( + lcd_cls, 1, 1, do_lcd_clear, + "lcd_cls - lcd clear display\n", + NULL + ); + +U_BOOT_CMD( + lcd_puts, 2, 1, do_lcd_puts, + "lcd_puts - display string on lcd\n", + " - to be displayed\n" + ); + +U_BOOT_CMD( + lcd_putc, 2, 1, do_lcd_putc, + "lcd_putc - display char on lcd\n", + " - to be displayed\n" + ); + +U_BOOT_CMD( + lcd_cur, 3, 1, do_lcd_cur, + "lcd_cur - shift cursor on lcd\n", + " - shift cursor on lcd times, direction is \n" + " - 0..31\n" + " - 0=backward 1=forward\n" + ); diff --git a/board/amcc/taihu/taihu.c b/board/amcc/taihu/taihu.c new file mode 100644 index 000000000..ee9d3b544 --- /dev/null +++ b/board/amcc/taihu/taihu.c @@ -0,0 +1,234 @@ +/* + * (C) Copyright 2000-2005 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * (C) Copyright 2005-2007 + * Beijing UD Technology Co., Ltd., taihusupport@amcc.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include +#include +#include +#include +#include +#include + +extern int lcd_init(void); + +/* + * board_early_init_f + */ +int board_early_init_f(void) +{ + lcd_init(); + + mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ + mtdcr(uicer, 0x00000000); /* disable all ints */ + mtdcr(uiccr, 0x00000000); + mtdcr(uicpr, 0xFFFF7F00); /* set int polarities */ + mtdcr(uictr, 0x00000000); /* set int trigger levels */ + mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ + mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority */ + + mtebc(pb3ap, CFG_EBC_PB3AP); /* memory bank 3 (CPLD_LCM) initialization */ + mtebc(pb3cr, CFG_EBC_PB3CR); + + return 0; +} + +/* + * Check Board Identity: + */ +int checkboard(void) +{ + char *s = getenv("serial#"); + + puts("Board: Taihu - AMCC PPC405EP Evaluation Board"); + + if (s != NULL) { + puts(", serial# "); + puts(s); + } + putc('\n'); + + return 0; +} + +/************************************************************************* + * long int initdram + * + ************************************************************************/ +long int initdram(int board) +{ + return CFG_SDRAM_SIZE_PER_BANK * CFG_SDRAM_BANKS; /* 128Mbytes */ +} + +static int do_sw_stat(cmd_tbl_t* cmd_tp, int flags, int argc, char *argv[]) +{ + char stat; + int i; + + stat = in_8((u8 *) CPLD_REG0_ADDR); + printf("SW2 status: "); + for (i=0; i<4; i++) /* 4-position */ + printf("%d:%s ", i, stat & (0x08 >> i)?"on":"off"); + printf("\n"); + return 0; +} + +U_BOOT_CMD ( + sw2_stat, 1, 1, do_sw_stat, + "sw2_stat - show status of switch 2\n", + NULL + ); + +static int do_led_ctl(cmd_tbl_t* cmd_tp, int flags, int argc, char *argv[]) +{ + int led_no; + + if (argc != 3) { + printf("%s", cmd_tp->usage); + return -1; + } + + led_no = simple_strtoul(argv[1], NULL, 16); + if (led_no != 1 && led_no != 2) { + printf("%s", cmd_tp->usage); + return -1; + } + + if (strcmp(argv[2],"off") == 0x0) { + if (led_no == 1) + gpio_write_bit(30, 1); + else + gpio_write_bit(31, 1); + } else if (strcmp(argv[2],"on") == 0x0) { + if (led_no == 1) + gpio_write_bit(30, 0); + else + gpio_write_bit(31, 0); + } else { + printf("%s", cmd_tp->usage); + return -1; + } + + return 0; +} + +U_BOOT_CMD ( + led_ctl, 3, 1, do_led_ctl, + "led_ctl - make led 1 or 2 on or off\n", + " - make led on/off,\n" + "\tled_no is 1 or 2\t" + ); + +#define SPI_CS_GPIO0 0 +#define SPI_SCLK_GPIO14 14 +#define SPI_DIN_GPIO15 15 +#define SPI_DOUT_GPIO16 16 + +void spi_scl(int bit) +{ + gpio_write_bit(SPI_SCLK_GPIO14, bit); +} + +void spi_sda(int bit) +{ + gpio_write_bit(SPI_DOUT_GPIO16, bit); +} + +unsigned char spi_read(void) +{ + return (unsigned char)gpio_read_out_bit(SPI_DIN_GPIO15); +} + +void taihu_spi_chipsel(int cs) +{ + gpio_write_bit(SPI_CS_GPIO0, cs); +} + +spi_chipsel_type spi_chipsel[]= { + taihu_spi_chipsel +}; + +int spi_chipsel_cnt = sizeof(spi_chipsel) / sizeof(spi_chipsel[0]); + +#ifdef CONFIG_PCI +static unsigned char int_lines[32] = { + 29, 30, 27, 28, 29, 30, 25, 27, + 29, 30, 27, 28, 29, 30, 27, 28, + 29, 30, 27, 28, 29, 30, 27, 28, + 29, 30, 27, 28, 29, 30, 27, 28}; + +static void taihu_pci_fixup_irq(struct pci_controller *hose, pci_dev_t dev) +{ + unsigned char int_line = int_lines[PCI_DEV(dev) & 31]; + + pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, int_line); +} + +int pci_pre_init(struct pci_controller *hose) +{ + hose->fixup_irq = taihu_pci_fixup_irq; + return 1; +} +#endif /* CONFIG_PCI */ + +#ifdef CFG_DRAM_TEST +int testdram(void) +{ + unsigned long *mem = (unsigned long *)0; + const unsigned long kend = (1024 / sizeof(unsigned long)); + unsigned long k, n; + unsigned long msr; + unsigned long total_kbytes = CFG_SDRAM_SIZE_PER_BANK * CFG_SDRAM_BANKS / 1024; + + msr = mfmsr(); + mtmsr(msr & ~(MSR_EE)); + + for (k = 0; k < total_kbytes ; + ++k, mem += (1024 / sizeof(unsigned long))) { + if ((k & 1023) == 0) + printf("%3d MB\r", k / 1024); + + memset(mem, 0xaaaaaaaa, 1024); + for (n = 0; n < kend; ++n) { + if (mem[n] != 0xaaaaaaaa) { + printf("SDRAM test fails at: %08x\n", + (uint) & mem[n]); + return 1; + } + } + + memset(mem, 0x55555555, 1024); + for (n = 0; n < kend; ++n) { + if (mem[n] != 0x55555555) { + printf("SDRAM test fails at: %08x\n", + (uint) & mem[n]); + return 1; + } + } + } + printf("SDRAM test passes\n"); + mtmsr(msr); + + return 0; +} +#endif /* CFG_DRAM_TEST */ diff --git a/board/amcc/taihu/u-boot.lds b/board/amcc/taihu/u-boot.lds new file mode 100644 index 000000000..be030923b --- /dev/null +++ b/board/amcc/taihu/u-boot.lds @@ -0,0 +1,150 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + .resetvec 0xFFFFFFFC : + { + *(.resetvec) + } = 0xffff + + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/ppc4xx/start.o (.text) + cpu/ppc4xx/kgdb.o (.text) + cpu/ppc4xx/traps.o (.text) + cpu/ppc4xx/interrupts.o (.text) + cpu/ppc4xx/serial.o (.text) + cpu/ppc4xx/cpu_init.o (.text) + cpu/ppc4xx/speed.o (.text) + common/dlmalloc.o (.text) + lib_generic/crc32.o (.text) + lib_ppc/extable.o (.text) + lib_generic/zlib.o (.text) + +/* . = env_offset;*/ +/* common/environment.o(.text)*/ + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/amcc/taihu/update.c b/board/amcc/taihu/update.c new file mode 100644 index 000000000..55ad535c8 --- /dev/null +++ b/board/amcc/taihu/update.c @@ -0,0 +1,132 @@ +/* + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include + +#define PCI_M66EN 0x10 + +static uchar buf_33[] = +{ + 0xb5, /* 0x00:hce =1, bss = 0, pae=1, ppdv= 0b10,spe = 1,ebw=0b01*/ + 0x80, /* 0x01~0x03:ptm1ms =0x80000001 */ + 0x00, + 0x00, + 0x00, /* 0x04~0x06:ptm1la = 0x00000000 */ + 0x00, + 0x00, + 0x00, /* 0x07~0x09:ptm2ma = 0x00000000 */ + 0x00, + 0x00, + 0x00, /* 0x0a~0x0c:ptm2la = 0x00000000 */ + 0x00, + 0x00, + 0x10, /* 0x0d~0x0e:vendor id 0x1014*/ + 0x14, + 0x00, /* 0x0f~0x10:device id 0x0000*/ + 0x00, + 0x00, /* 0x11:revision 0x00 */ + 0x00, /* 0x12~0x14:class 0x000000 */ + 0x00, + 0x00, + 0x10, /* 0x15~0x16:subsystem vendor id */ + 0xe8, + 0x00, /* 0x17~0x18:subsystem device id */ + 0x00, + 0x61, /* 0x19: opdv=0b01,cbdv=0b10,ccdv=0b00,ptm2ms_ena=0, ptm1ms_ena=1 */ + 0x68, /* 0x1a: rpci=1,fbmul=0b1010,epdv=0b00 */ + 0x2d, /* 0x1b: fwdvb=0b101,fwdva=0b101 */ + 0x82, /* 0x1c: pllr=1,sscs=0,mpdv=0b00,tun[22-23]=0b10 */ + 0xbe, /* 0x1d: tun[24-31]=0xbe */ + 0x00, + 0x00 +}; + +static uchar buf_66[] = +{ + 0xb5, /* 0x00:hce =1, bss = 0, pae=1, ppdv= 0b10,spe = 1,ebw=0b01*/ + 0x80, /* 0x01~0x03:ptm1ms =0x80000001 */ + 0x00, + 0x00, + 0x00, /* 0x04~0x06:ptm1la = 0x00000000 */ + 0x00, + 0x00, + 0x00, /* 0x07~0x09:ptm2ma = 0x00000000 */ + 0x00, + 0x00, + 0x00, /* 0x0a~0x0c:ptm2la = 0x00000000 */ + 0x00, + 0x00, + 0x10, /* 0x0d~0x0e:vendor id 0x1014*/ + 0x14, + 0x00, /* 0x0f~0x10:device id 0x0000*/ + 0x00, + 0x00, /* 0x11:revision 0x00 */ + 0x00, /* 0x12~0x14:class 0x000000 */ + 0x00, + 0x00, + 0x10, /* 0x15~0x16:subsystem vendor id */ + 0xe8, + 0x00, /* 0x17~0x18:subsystem device id */ + 0x00, + 0x61, /* 0x19: opdv=0b01,cbdv=0b10,ccdv=0b00,ptm2ms_ena=0, ptm1ms_ena=1 */ + 0x68, /* 0x1a: rpci=1,fbmul=0b1010,epdv=0b00 */ + 0x2d, /* 0x1b: fwdvb=0b101,fwdva=0b101 */ + 0x82, /* 0x1c: pllr=1,sscs=0,mpdv=0b00,tun[22-23]=0b10 */ + 0xbe, /* 0x1d: tun[24-31]=0xbe */ + 0x00, + 0x00 +}; + +static int update_boot_eeprom(cmd_tbl_t* cmdtp, int flag, int argc, char *argv[]) +{ + ulong len = 0x20; + uchar chip = CFG_I2C_EEPROM_ADDR; + uchar *pbuf; + uchar base; + int i; + + if ((*(volatile char*)CPLD_REG0_ADDR & PCI_M66EN) != PCI_M66EN) { + pbuf = buf_33; + base = 0x00; + } else { + pbuf = buf_66; + base = 0x40; + } + + for (i = 0; i< len; i++, base++) { + if (i2c_write(chip, base, 1, &pbuf[i],1)!= 0) { + printf("i2c_write fail\n"); + return 1; + } + udelay(11000); + } + + return 0; +} + +U_BOOT_CMD ( + update_boot_eeprom, 1, 1, update_boot_eeprom, + "update_boot_eeprom - update boot eeprom content\n", + NULL + ); diff --git a/common/soft_spi.c b/common/soft_spi.c index 00a57de8a..e4250616c 100644 --- a/common/soft_spi.c +++ b/common/soft_spi.c @@ -79,7 +79,9 @@ void spi_init (void) */ int spi_xfer(spi_chipsel_type chipsel, int bitlen, uchar *dout, uchar *din) { +#ifdef CFG_IMMR volatile immap_t *immr = (immap_t *)CFG_IMMR; +#endif uchar tmpdin = 0; uchar tmpdout = 0; int j; diff --git a/cpu/ppc4xx/gpio.c b/cpu/ppc4xx/gpio.c index 0d0e273fc..50f2fdf11 100644 --- a/cpu/ppc4xx/gpio.c +++ b/cpu/ppc4xx/gpio.c @@ -186,6 +186,7 @@ void gpio_set_chip_configuration(void) out32(GPIO0_TCR, reg); } +#ifdef GPIO1 if (gpio_core == GPIO1) { /* * Setup output value @@ -203,6 +204,7 @@ void gpio_set_chip_configuration(void) reg = in32(GPIO1_TCR) | (0x80000000 >> (i)); out32(GPIO1_TCR, reg); } +#endif /* GPIO1 */ reg = in32(GPIO_OS(core_add+offs)) & ~(GPIO_MASK >> (j*2)); diff --git a/cpu/ppc4xx/sdram.c b/cpu/ppc4xx/sdram.c index d520cd3ff..3a0ca17d9 100644 --- a/cpu/ppc4xx/sdram.c +++ b/cpu/ppc4xx/sdram.c @@ -209,8 +209,17 @@ void sdram_init(void) if (get_ram_size(0, mb0cf[i].size) == mb0cf[i].size) { /* - * OK, size detected -> all done + * OK, size detected. Enable second bank if + * defined (assumes same type as bank 0) */ +#ifdef CONFIG_SDRAM_BANK1 + u32 b1cr = mb0cf[i].size | mb0cf[i].reg; + + mtsdram0(mem_mcopt1, 0x00000000); + mtsdram0(mem_mb1cf, b1cr); /* SDRAM0_B1CR */ + mtsdram0(mem_mcopt1, 0x80800000); + udelay(10000); +#endif return; } } diff --git a/cpu/ppc4xx/start.S b/cpu/ppc4xx/start.S index 8ecaaea4d..18d344560 100644 --- a/cpu/ppc4xx/start.S +++ b/cpu/ppc4xx/start.S @@ -1869,6 +1869,11 @@ ppc405ep_init: ori r3,r3,CFG_EBC_PB4CR@l mtdcr ebccfgd,r3 #endif +#ifdef CONFIG_TAIHU + mfdcr r4, CPC0_BOOT + andi. r5, r4, CPC0_BOOT_SEP@l + bne strap_0 /* serial eeprom present */ +#endif #ifndef CFG_CPC0_PCI li r3,CPC0_PCI_HOST_CFG_EN @@ -1886,12 +1891,16 @@ ppc405ep_init: beq ..pci_cfg_set /* if not set, then bypass reg write*/ #endif ori r3,r3,CPC0_PCI_ARBIT_EN +#ifdef CONFIG_TAIHU + ori r3,r3,CPC0_PCI_SPE +#endif #else /* CFG_CPC0_PCI */ li r3,CFG_CPC0_PCI #endif /* CFG_CPC0_PCI */ ..pci_cfg_set: mtdcr CPC0_PCI, r3 /* Enable internal arbiter*/ +strap_0: /* !----------------------------------------------------------------------- ! Check to see if chip is in bypass mode. @@ -1947,11 +1956,35 @@ ppc405ep_init: ..no_pllset: #endif /* CONFIG_BUBINGA */ +#ifdef CONFIG_TAIHU + mfdcr r4, CPC0_BOOT + andi. r5, r4, CPC0_BOOT_SEP@l + bne strap_1 /* serial eeprom present */ + addis r5,0,CPLD_REG0_ADDR@h + ori r5,r5,CPLD_REG0_ADDR@l + andi. r5, r5, 0x10 + bne _pci_66mhz +#endif /* CONFIG_TAIHU */ + addis r3,0,PLLMR0_DEFAULT@h /* PLLMR0 default value */ ori r3,r3,PLLMR0_DEFAULT@l /* */ addis r4,0,PLLMR1_DEFAULT@h /* PLLMR1 default value */ ori r4,r4,PLLMR1_DEFAULT@l /* */ +#ifdef CONFIG_TAIHU + b 1f +_pci_66mhz: + addis r3,0,PLLMR0_DEFAULT_PCI66@h + ori r3,r3,PLLMR0_DEFAULT_PCI66@l + addis r4,0,PLLMR1_DEFAULT_PCI66@h + ori r4,r4,PLLMR1_DEFAULT_PCI66@l + b 1f +strap_1: + mfdcr r3, CPC0_PLLMR0 + mfdcr r4, CPC0_PLLMR1 +1: +#endif /* CONFIG_TAIHU */ + b pll_write /* Write the CPC0_PLLMR with new value */ pll_done: diff --git a/dtt/Makefile b/dtt/Makefile index e6cb128f3..c6a670af1 100644 --- a/dtt/Makefile +++ b/dtt/Makefile @@ -30,7 +30,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)libdtt.a -COBJS = lm75.o ds1621.o adm1021.o lm81.o +COBJS = lm75.o ds1621.o adm1021.o lm81.o ds1775.o SRCS := $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/dtt/ds1775.c b/dtt/ds1775.c new file mode 100644 index 000000000..e44cee327 --- /dev/null +++ b/dtt/ds1775.c @@ -0,0 +1,156 @@ +/* + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * Dallas Semiconductor's DS1775 Digital Thermometer and Thermostat + */ + +#include + +#ifdef CONFIG_DTT_DS1775 +#include +#include + +#define DTT_I2C_DEV_CODE 0x49 /* Dallas Semi's DS1775 device code */ + +int dtt_read(int sensor, int reg) +{ + int dlen; + uchar data[2]; + + /* + * Calculate sensor address and command + */ + sensor = DTT_I2C_DEV_CODE + (sensor & 0x07); /* Calculate addr of ds1775 */ + + /* + * Prepare to handle 2 byte result + */ + if ((reg == DTT_READ_TEMP) || + (reg == DTT_TEMP_OS) || (reg == DTT_TEMP_HYST)) + dlen = 2; + else + dlen = 1; + + /* + * Now try to read the register + */ + if (i2c_read(sensor, reg, 1, data, dlen) != 0) + return 1; + + /* + * Handle 2 byte result + */ + if (dlen == 2) + return ((int)((short)data[1] + (((short)data[0]) << 8))); + + return (int) data[0]; +} + + +int dtt_write(int sensor, int reg, int val) +{ + int dlen; + uchar data[2]; + + /* + * Calculate sensor address and register + */ + sensor = DTT_I2C_DEV_CODE + (sensor & 0x07); + + /* + * Handle various data sizes + */ + if ((reg == DTT_READ_TEMP) || + (reg == DTT_TEMP_OS) || (reg == DTT_TEMP_HYST)) { + dlen = 2; + data[0] = (char)((val >> 8) & 0xff); /* MSB first */ + data[1] = (char)(val & 0xff); + } else { + dlen = 1; + data[0] = (char)(val & 0xff); + } + + /* + * Write value to device + */ + if (i2c_write(sensor, reg, 1, data, dlen) != 0) + return 1; + + return 0; +} + + +static int _dtt_init(int sensor) +{ + int val; + + /* + * Setup High Temp + */ + val = ((CFG_DTT_MAX_TEMP * 2) << 7) & 0xff80; + if (dtt_write(sensor, DTT_TEMP_OS, val) != 0) + return 1; + udelay(50000); /* Max 50ms */ + + /* + * Setup Low Temp - hysteresis + */ + val = (((CFG_DTT_MAX_TEMP - CFG_DTT_HYSTERESIS) * 2) << 7) & 0xff80; + if (dtt_write(sensor, DTT_TEMP_HYST, val) != 0) + return 1; + udelay(50000); /* Max 50ms */ + + /* + * Setup configuraton register + * + * Fault Tolerance limits 4, Thermometer resolution bits is 9, + * Polarity = Active Low,continuous conversion mode, Thermostat + * mode is interrupt mode + */ + val = 0xa; + if (dtt_write(sensor, DTT_CONFIG, val) != 0) + return 1; + udelay(50000); /* Max 50ms */ + + return 0; +} + + +int dtt_init (void) +{ + int i; + unsigned char sensors[] = CONFIG_DTT_SENSORS; + + for (i = 0; i < sizeof(sensors); i++) { + if (_dtt_init(sensors[i]) != 0) + printf("DTT%d: FAILED\n", i+1); + else + printf("DTT%d: %i C\n", i+1, dtt_get_temp(sensors[i])); + } + + return (0); +} + + +int dtt_get_temp(int sensor) +{ + return (dtt_read(sensor, DTT_READ_TEMP) / 256); +} + + +#endif /* CONFIG_DTT_DS1775 */ diff --git a/include/configs/taihu.h b/include/configs/taihu.h new file mode 100644 index 000000000..61814a809 --- /dev/null +++ b/include/configs/taihu.h @@ -0,0 +1,473 @@ +/* + * (C) Copyright 2000-2005 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * (C) Copyright 2005-2007 + * Beijing UD Technology Co., Ltd., taihusupport@amcc.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + + +#define CONFIG_405EP 1 /* this is a PPC405 CPU */ +#define CONFIG_4xx 1 /* member of PPC4xx family */ +#define CONFIG_TAIHU 1 /* on a taihu board */ + +#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f */ + +#define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */ + +#define CONFIG_NO_SERIAL_EEPROM + +/*----------------------------------------------------------------------------*/ +#ifdef CONFIG_NO_SERIAL_EEPROM + +/* +!------------------------------------------------------------------------------- +! PLL settings for 333MHz CPU, 111MHz PLB/SDRAM, 55MHz EBC, 33MHz PCI, +! assuming a 33MHz input clock to the 405EP from the C9531. +!------------------------------------------------------------------------------- +*/ +#define PLLMR0_333_111_55_37 (PLL_CPUDIV_1 | PLL_PLBDIV_3 | \ + PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 | \ + PLL_MALDIV_1 | PLL_PCIDIV_3) +#define PLLMR1_333_111_55_37 (PLL_FBKDIV_10 | \ + PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \ + PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI) +#define PLLMR0_333_111_55_111 (PLL_CPUDIV_1 | PLL_PLBDIV_3 | \ + PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 | \ + PLL_MALDIV_1 | PLL_PCIDIV_1) +#define PLLMR1_333_111_55_111 (PLL_FBKDIV_10 | \ + PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \ + PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI) + +#define PLLMR0_DEFAULT PLLMR0_333_111_55_37 +#define PLLMR1_DEFAULT PLLMR1_333_111_55_37 +#define PLLMR0_DEFAULT_PCI66 PLLMR0_333_111_55_111 +#define PLLMR1_DEFAULT_PCI66 PLLMR1_333_111_55_111 + +#endif +/*----------------------------------------------------------------------------*/ + +#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ + +#define CONFIG_ENV_OVERWRITE 1 +#define CONFIG_PREBOOT "echo;" \ + "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ + "echo" + +#undef CONFIG_BOOTARGS +#define CONFIG_EXTRA_ENV_SETTINGS \ + "bootfile=/tftpboot/taihu/uImage\0" \ + "rootpath=/opt/eldk/ppc_4xx\0" \ + "netdev=eth0\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=${serverip}:${rootpath}\0" \ + "ramargs=setenv bootargs root=/dev/ram rw\0" \ + "addip=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:${netdev}:off panic=1\0" \ + "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ + "flash_nfs=run nfsargs addip addtty;" \ + "bootm ${kernel_addr}\0" \ + "flash_self=run ramargs addip addtty;" \ + "bootm ${kernel_addr} ${ramdisk_addr}\0" \ + "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ + "bootm\0" \ + "kernel_addr=FC000000\0" \ + "ramdisk_addr=FC180000\0" \ + "load=tftp 200000 /tftpboot/taihu/u-boot.bin\0" \ + "update=protect off FFFC0000 FFFFFFFF;era FFFC0000 FFFFFFFF;" \ + "cp.b 200000 FFFC0000 40000\0" \ + "upd=run load;run update\0" \ + "" +#define CONFIG_BOOTCOMMAND "run flash_self" + +#if 0 +#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ +#else +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ +#endif + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +#define CONFIG_MII 1 /* MII PHY management */ +#define CONFIG_PHY_ADDR 0x14 /* PHY address */ +#define CONFIG_HAS_ETH1 +#define CONFIG_PHY1_ADDR 0x10 /* EMAC1 PHY address */ +#define CONFIG_NET_MULTI 1 +#define CFG_RX_ETH_BUFFER 16 /* Number of ethernet rx buffers & descriptors */ +#define CONFIG_PHY_RESET 1 + +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ + CFG_CMD_ASKENV | \ + CFG_CMD_CACHE | \ + CFG_CMD_DHCP | \ + CFG_CMD_EEPROM | \ + CFG_CMD_ELF | \ + CFG_CMD_I2C | \ + CFG_CMD_SPI | \ + CFG_CMD_IRQ | \ + CFG_CMD_MII | \ + CFG_CMD_NET | \ + CFG_CMD_PCI | \ + CFG_CMD_PING | \ + CFG_CMD_REGINFO | \ + CFG_CMD_SDRAM ) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +#undef CONFIG_SPD_EEPROM /* use SPD EEPROM for setup */ +#define CFG_SDRAM_SIZE_PER_BANK 0x04000000 /* 64MB */ +#define CFG_SDRAM_BANKS 2 + +/* + * SDRAM configuration (please see cpu/ppc/sdram.[ch]) + */ +#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ +#define CONFIG_SDRAM_BANK1 1 /* init onboard SDRAM bank 1 */ + +/* SDRAM timings used in datasheet */ +#define CFG_SDRAM_CL 3 /* CAS latency */ +#define CFG_SDRAM_tRP 20 /* PRECHARGE command period */ +#define CFG_SDRAM_tRC 66 /* ACTIVE-to-ACTIVE command period */ +#define CFG_SDRAM_tRCD 20 /* ACTIVE-to-READ delay */ +#define CFG_SDRAM_tRFC 66 /* Auto refresh period */ + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* print buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ +#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ + +/* + * If CFG_EXT_SERIAL_CLOCK, then the UART divisor is 1. + * If CFG_405_UART_ERRATA_59, then UART divisor is 31. + * Otherwise, UART divisor is determined by CPU Clock and CFG_BASE_BAUD value. + * The Linux BASE_BAUD define should match this configuration. + * baseBaud = cpuClock/(uartDivisor*16) + * If CFG_405_UART_ERRATA_59 and 200MHz CPU clock, + * set Linux BASE_BAUD to 403200. + */ +#undef CONFIG_SERIAL_SOFTWARE_FIFO +#undef CFG_EXT_SERIAL_CLOCK /* external serial clock */ +#undef CFG_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */ +#define CFG_BASE_BAUD 691200 + +#define CONFIG_BAUDRATE 115200 + +#define CONFIG_UART1_CONSOLE 1 + + +/* The following table includes the supported baudrates */ +#define CFG_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400} + +#define CFG_LOAD_ADDR 0x100000 /* default load address */ +#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */ +#define CONFIG_LOOPW 1 /* enable loopw command */ +#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ +#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ + +/*----------------------------------------------------------------------- + * I2C stuff + *----------------------------------------------------------------------- + */ +#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ +#undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CFG_I2C_SLAVE 0x7F + +#define CFG_I2C_NOPROBES { 0x69 } /* avoid iprobe hangup (why?) */ +#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 6 /* 24C02 requires 5ms delay */ + +#if (CONFIG_COMMANDS & CFG_CMD_EEPROM) +#define CFG_I2C_EEPROM_ADDR 0x50 /* I2C boot EEPROM (24C02W) */ +#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ +#endif + + +#define CONFIG_SOFT_SPI +#define SPI_SCL spi_scl +#define SPI_SDA spi_sda +#define SPI_READ spi_read() +#define SPI_DELAY udelay(2) +#ifndef __ASSEMBLY__ +void spi_scl(int); +void spi_sda(int); +unsigned char spi_read(void); +#endif + +/* standard dtt sensor configuration */ +#define CONFIG_DTT_DS1775 1 +#define CONFIG_DTT_SENSORS { 0 } + +/*----------------------------------------------------------------------- + * PCI stuff + *----------------------------------------------------------------------- + */ +#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */ +#define PCI_HOST_FORCE 1 /* configure as pci host */ +#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ + +#define CONFIG_PCI /* include pci support */ +#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */ +#define CONFIG_PCI_PNP /* do pci plug-and-play */ + /* resource configuration */ +#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ + +#define CFG_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */ +#define CFG_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */ +#define CFG_PCI_CLASSCODE 0x0600 /* PCI Class Code: bridge/host */ +#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */ +#define CFG_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */ +#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ +#define CFG_PCI_PTM2LA 0x00000000 /* disabled */ +#define CFG_PCI_PTM2MS 0x00000000 /* disabled */ +#define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */ +#define CONFIG_EEPRO100 1 + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + */ +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_FLASH_BASE 0xFFE00000 +#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */ +#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */ +#define CFG_MONITOR_BASE (-CFG_MONITOR_LEN) + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/*----------------------------------------------------------------------- + * FLASH organization + */ + +#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ + +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ + +#define CFG_FLASH_ADDR0 0x555 +#define CFG_FLASH_ADDR1 0x2aa +#define CFG_FLASH_WORD_SIZE unsigned short + +#ifdef CFG_ENV_IS_IN_FLASH +#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */ +#define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE) +#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ + +/* Address and size of Redundant Environment Sector */ +#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE) +#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) +#endif /* CFG_ENV_IS_IN_FLASH */ + +/*----------------------------------------------------------------------- + * NVRAM organization + */ +#define CFG_NVRAM_BASE_ADDR 0xf0000000 /* NVRAM base address */ +#define CFG_NVRAM_SIZE 0x1ff8 /* NVRAM size */ + +#ifdef CFG_ENV_IS_IN_NVRAM +#define CFG_ENV_SIZE 0x0ff8 /* Size of Environment vars */ +#define CFG_ENV_ADDR \ + (CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-CFG_ENV_SIZE) /* Env*/ +#endif + +/*----------------------------------------------------------------------- + * PPC405 GPIO Configuration + */ +#define CFG_440_GPIO_TABLE { /* GPIO Alternate1 */ \ +{ \ +/* GPIO Core 0 */ \ +{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO0 PerBLast SPI CS */ \ +{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO1 TS1E */ \ +{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO2 TS2E */ \ +{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO3 TS1O */ \ +{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO4 TS2O */ \ +{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO5 TS3 */ \ +{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO6 TS4 */ \ +{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO7 TS5 */ \ +{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO8 TS6 */ \ +{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO9 TrcClk */ \ +{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO10 PerCS1 */ \ +{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO11 PerCS2 */ \ +{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO12 PerCS3 */ \ +{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO13 PerCS4 */ \ +{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO14 PerAddr03 SPI SCLK */ \ +{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO15 PerAddr04 SPI DI */ \ +{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO16 PerAddr05 SPI DO */ \ +{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO17 IRQ0 PCI INTA */ \ +{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO18 IRQ1 PCI INTB */ \ +{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO19 IRQ2 PCI INTC */ \ +{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO20 IRQ3 PCI INTD */ \ +{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO21 IRQ4 USB */ \ +{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO22 IRQ5 EBC */ \ +{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO23 IRQ6 unused */ \ +{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO24 UART0_DCD UART1 */ \ +{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO25 UART0_DSR */ \ +{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO26 UART0_RI */ \ +{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO27 UART0_DTR */ \ +{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO28 UART1_Rx UART0 */ \ +{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO29 UART1_Tx */ \ +{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO30 RejectPkt0 User LED1 */ \ +{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO31 RejectPkt1 User LED2 */ \ +} \ +} + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_DCACHE_SIZE 16384 /* For IBM 405EP CPU */ +#define CFG_CACHELINE_SIZE 32 +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + +/* + * Init Memory Controller: + * + * BR0/1 and OR0/1 (FLASH) + */ + +#define FLASH_BASE0_PRELIM CFG_FLASH_BASE /* FLASH bank #0 */ +#define FLASH_BASE1_PRELIM 0xFC000000 /* FLASH bank #1 */ + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area (in data cache) + */ +/* use on chip memory (OCM) for temperary stack until sdram is tested */ +#define CFG_TEMP_STACK_OCM 1 + +/* On Chip Memory location */ +#define CFG_OCM_DATA_ADDR 0xF8000000 +#define CFG_OCM_DATA_SIZE 0x1000 +#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of SDRAM */ +#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM */ + +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +/*----------------------------------------------------------------------- + * External Bus Controller (EBC) Setup + */ + +/* Memory Bank 0 (Flash/SRAM) initialization */ +#define CFG_EBC_PB0AP 0x03815600 +#define CFG_EBC_PB0CR 0xFFE3A000 /* BAS=0xFFE,BS=2MB,BU=R/W,BW=16bit */ + +/* Memory Bank 1 (NVRAM/RTC) initialization */ +#define CFG_EBC_PB1AP 0x05815600 +#define CFG_EBC_PB1CR 0xFC0BA000 /* BAS=0xFc0,BS=32MB,BU=R/W,BW=16bit */ + +/* Memory Bank 2 (USB device) initialization */ +#define CFG_EBC_PB2AP 0x03016600 +#define CFG_EBC_PB2CR 0x50018000 /* BAS=0x500,BS=1MB,BU=R/W,BW=8bit */ + +/* Memory Bank 3 (LCM and D-flip-flop) initialization */ +#define CFG_EBC_PB3AP 0x158FF600 +#define CFG_EBC_PB3CR 0x50118000 /* BAS=0x501,BS=1MB,BU=R/W,BW=8bit */ + +/* Memory Bank 4 (not install) initialization */ +#define CFG_EBC_PB4AP 0x158FF600 +#define CFG_EBC_PB4CR 0x5021A000 + +/*----------------------------------------------------------------------- + * Definitions for GPIO setup (PPC405EP specific) + * + * GPIO0[0] - External Bus Controller BLAST output + * GPIO0[1-9] - Instruction trace outputs + * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs + * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs + * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs + * GPIO0[24-27] - UART0 control signal inputs/outputs + * GPIO0[28-29] - UART1 data signal input/output + * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs + */ +#define CFG_GPIO0_OSRH 0x15555550 /* output select high/low */ +#define CFG_GPIO0_OSRL 0x00000110 +#define CFG_GPIO0_ISR1H 0x00000001 /* input select high/low */ +#define CFG_GPIO0_ISR1L 0x15545440 +#define CFG_GPIO0_TSRH 0x00000000 /* three-state select high/low */ +#define CFG_GPIO0_TSRL 0x00000000 +#define CFG_GPIO0_TCR 0xFFFE8117 /* three-state control */ +#define CFG_GPIO0_ODR 0x00000000 /* open drain */ + +#define GPIO0 0 /* GPIO controller 0 */ + +/* the GPIO macros in include/ppc405.h for High/Low registers are backwards */ + +#define GPIOx_OSL (GPIO0_OSRH-GPIO_BASE) +#define GPIOx_TSL (GPIO0_TSRH-GPIO_BASE) +#define GPIOx_IS1L (GPIO0_ISR1H-GPIO_BASE) +#define GPIOx_IS2L (GPIO0_ISR1H-GPIO_BASE) +#define GPIOx_IS3L (GPIO0_ISR1H-GPIO_BASE) + +#define GPIO_OS(x) (x+GPIOx_OSL) /* GPIO output select */ +#define GPIO_TS(x) (x+GPIOx_TSL) /* GPIO three-state select */ +#define GPIO_IS1(x) (x+GPIOx_IS1L) /* GPIO input select */ +#define GPIO_IS2(x) (x+GPIOx_IS1L) +#define GPIO_IS3(x) (x+GPIOx_IS1L) + +#define CPLD_REG0_ADDR 0x50100000 +#define CPLD_REG1_ADDR 0x50100001 +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif + +#endif /* __CONFIG_H */ diff --git a/include/dtt.h b/include/dtt.h index 842a761c9..2e8c69015 100644 --- a/include/dtt.h +++ b/include/dtt.h @@ -29,6 +29,7 @@ #if defined(CONFIG_DTT_LM75) || \ defined(CONFIG_DTT_DS1621) || \ + defined(CONFIG_DTT_DS1775) || \ defined(CONFIG_DTT_LM81) || \ defined(CONFIG_DTT_ADM1021) @@ -78,6 +79,13 @@ extern int dtt_get_temp(int sensor); #define DTT_CONFIG 0xAC #endif +#if defined(CONFIG_DTT_DS1775) +#define DTT_READ_TEMP 0x0 +#define DTT_CONFIG 0x1 +#define DTT_TEMP_HYST 0x2 +#define DTT_TEMP_OS 0x3 +#endif + #if defined(CONFIG_DTT_ADM1021) #define DTT_READ_LOC_VALUE 0x00 #define DTT_READ_REM_VALUE 0x01 From e36220a4baf1f188ba60f17e9d0f043069b1362a Mon Sep 17 00:00:00 2001 From: Matthias Fuchs Date: Fri, 27 Jul 2007 16:44:31 +0200 Subject: [PATCH 050/259] new FPGA image for PLU405 board new FPGA image for PLU405 board with improved CompactFlash timing Signed-off-by: Matthias Fuchs --- board/esd/plu405/fpgadata.c | 2339 ++++++++++++++++++----------------- 1 file changed, 1179 insertions(+), 1160 deletions(-) diff --git a/board/esd/plu405/fpgadata.c b/board/esd/plu405/fpgadata.c index f6656c150..dc8c88b0e 100644 --- a/board/esd/plu405/fpgadata.c +++ b/board/esd/plu405/fpgadata.c @@ -1,1160 +1,1179 @@ - 0x1f,0x8b,0x08,0x08,0x9d,0x76,0x5c,0x3f,0x00,0x03,0x70,0x6c,0x75,0x34,0x30,0x35, - 0x5f,0x31,0x5f,0x30,0x30,0x2e,0x62,0x69,0x74,0x00,0x94,0x9b,0x7f,0x6c,0x1d,0x55, - 0x76,0xc7,0xcf,0xfc,0xb0,0x3d,0xf6,0x7b,0xf1,0x9b,0x24,0x76,0xeb,0x6e,0x82,0x33, - 0xfe,0x41,0xf4,0x48,0x9f,0x5f,0x5e,0x9c,0x1f,0x18,0x63,0xec,0x89,0x13,0xed,0x5a, - 0x4b,0xda,0x58,0x2a,0xad,0x56,0x15,0x62,0x0d,0x9b,0xad,0xa2,0xca,0x44,0xa6,0xdb, - 0x56,0x51,0xba,0x0d,0xd7,0x71,0x20,0x06,0x7b,0x89,0xa1,0x48,0x04,0x9a,0xd2,0x17, - 0x88,0x84,0x05,0xd6,0xea,0xe5,0x47,0x89,0x21,0x29,0x4c,0x8c,0x81,0x07,0x4d,0x83, - 0x9b,0xa0,0x2a,0x1b,0x68,0x78,0x50,0x2f,0x98,0x10,0xb2,0xce,0x8f,0x06,0x93,0x38, - 0x71,0xef,0x9d,0x99,0x7b,0xe7,0xce,0xaf,0x67,0xaf,0xf7,0x8f,0x3d,0x99,0x77,0x35, - 0xdc,0x73,0xde,0x9d,0x73,0x3e,0xf3,0x3d,0xe7,0x41,0x71,0x6c,0xd2,0xfa,0x1f,0x80, - 0xf0,0x20,0xa8,0x5d,0x9d,0x7f,0xb7,0x2a,0xb5,0xfa,0xa7,0x2b,0x7e,0x9a,0x4a,0x25, - 0xb7,0xfc,0x6c,0x13,0x3c,0x04,0x91,0xfa,0x5f,0xac,0x4e,0xfd,0xfc,0x6f,0x1f,0x59, - 0xb1,0x6a,0x15,0xfc,0x0c,0xff,0x2b,0x95,0x5a,0xb9,0x3c,0x75,0xd7,0xf2,0x54,0x03, - 0x6c,0x82,0xe2,0x15,0xab,0x1a,0x57,0xae,0x68,0xac,0x5f,0x05,0x3f,0x07,0x61,0xe5, - 0xfe,0x19,0xfc,0xf7,0xea,0xf3,0x7f,0xfe,0x57,0x29,0x40,0x02,0x00,0x14,0xa5,0x84, - 0x0e,0xf2,0xff,0x91,0x94,0xa0,0x09,0x80,0x5a,0xea,0x52,0x60,0x90,0x7f,0x83,0xfd, - 0x79,0x71,0x0a,0x34,0xfe,0xdf,0x42,0x0a,0x74,0x68,0x07,0xbd,0x1f,0x16,0xa8,0x30, - 0xeb,0x9f,0xa0,0xcb,0x88,0xda,0xbf,0xe7,0xfa,0x99,0x0f,0x51,0xe8,0x32,0xe7,0xaf, - 0xe5,0x72,0x9a,0x9a,0x62,0x6a,0x2e,0xf7,0x07,0x76,0xff,0xb3,0x73,0xba,0xff,0x35, - 0x7a,0xff,0xdf,0x77,0x3d,0x2c,0x98,0xc3,0x72,0x00,0x99,0xed,0xc7,0x0a,0x8f,0x0c, - 0x78,0x87,0x1d,0xa0,0x42,0x21,0x08,0xc4,0xa8,0x00,0xd1,0x75,0xff,0x51,0xba,0xfe, - 0x78,0xc1,0x2d,0x98,0x41,0x2d,0xe3,0xa5,0x5b,0xa5,0x2d,0xea,0x0d,0xf4,0x07,0xb9, - 0xd8,0x94,0x84,0xaf,0xec,0x6c,0xb1,0x8c,0xcf,0x90,0x69,0x4c,0xca,0x5d,0xf6,0xfa, - 0x91,0x8a,0x8b,0x70,0x14,0x25,0x0d,0x65,0x8f,0x98,0x94,0xb1,0xf1,0x79,0xdf,0xb0, - 0x68,0x5e,0xc9,0x45,0x1c,0x43,0xca,0xc8,0x34,0x8a,0x59,0xe8,0x87,0x43,0x10,0xcf, - 0xfe,0x20,0x25,0x9e,0xc0,0x46,0xad,0xb1,0xc8,0x32,0x12,0x46,0x84,0x18,0xff,0x64, - 0x19,0x97,0x05,0x7a,0x7f,0x03,0x86,0xe0,0x28,0xbe,0xa8,0x0c,0x8b,0xc4,0x48,0x1a, - 0x91,0x8c,0x78,0xc1,0x6d,0xf4,0x65,0x60,0x12,0xbb,0x64,0xfd,0xad,0x2d,0xbf,0x00, - 0x37,0xa0,0xd1,0x28,0xcd,0x48,0xc4,0x58,0x63,0xc4,0x2c,0xa3,0xd9,0x32,0x3e,0xb1, - 0x8c,0x31,0xa0,0xf7,0x4f,0x0b,0xc7,0x60,0x06,0x5a,0x8c,0xd8,0xa4,0xf4,0x4b,0x6a, - 0x4c,0xfb,0x8c,0x41,0x76,0x7f,0x43,0x1d,0x32,0xef,0x16,0x7d,0x53,0x4a,0x10,0xe3, - 0x38,0x7f,0x5b,0xfa,0x1f,0x5a,0x78,0x15,0x34,0xba,0xbe,0x20,0x61,0x6e,0x52,0x59, - 0x05,0x09,0xf8,0x46,0xb4,0xb7,0x7d,0xb7,0xc7,0x91,0xcb,0xf8,0xf4,0xdb,0xeb,0xe5, - 0x0d,0x66,0x34,0x8a,0xcb,0xc4,0xa8,0x2f,0x2c,0x2c,0x50,0x53,0x72,0xbb,0xbd,0x7e, - 0x4a,0x7d,0x00,0x8e,0xa0,0xba,0x5c,0xf1,0x4f,0xc4,0x4a,0x78,0x05,0xd5,0x4d,0x44, - 0xb6,0x8a,0xe7,0x10,0xb9,0x42,0x0c,0xb0,0x8d,0x5b,0xec,0xfe,0x6d,0xca,0x06,0xb8, - 0x82,0x37,0x39,0x4f,0x95,0x4a,0x8d,0x2b,0xdd,0x4d,0x13,0xb1,0x54,0xcd,0x49,0x38, - 0x0d,0x4d,0x46,0x2c,0x25,0x9d,0xc0,0x1f,0x35,0x8d,0x62,0xe3,0x14,0x3b,0x1d,0x7a, - 0xf9,0x31,0x99,0x04,0x21,0x99,0x21,0xd1,0x50,0x5b,0x46,0x63,0x97,0x2c,0xc3,0x15, - 0x9f,0xb1,0x42,0x1a,0x1f,0x45,0xb6,0xe2,0x13,0x1b,0xa8,0x21,0xd1,0x48,0x7a,0xe2, - 0x6f,0x1b,0xe7,0x59,0xfc,0x4f,0x54,0xec,0x85,0x23,0x50,0x67,0x44,0xba,0xc4,0x4f, - 0x4d,0xa3,0x94,0x1a,0x11,0xce,0xb8,0x2c,0xd3,0xfb,0x6b,0xf0,0x22,0x76,0xea,0xe1, - 0x5c,0xe4,0x27,0xe2,0x39,0x81,0x78,0xd7,0xc7,0xb9,0xc9,0x8c,0x1c,0x8b,0x7f,0xa7, - 0xdc,0x6f,0x05,0x6d,0x58,0x3c,0x21,0x10,0xe3,0x07,0xae,0xf3,0x66,0x1b,0xa7,0xd8, - 0xf9,0x9c,0x28,0x9f,0x80,0xeb,0xd0,0x8c,0x62,0x83,0x3d,0xb6,0x91,0x96,0x88,0xb1, - 0x9d,0x1a,0xe6,0x95,0xeb,0x6c,0x3f,0x6d,0x42,0x1a,0xa6,0xa0,0x19,0x62,0x48,0xca, - 0x99,0x46,0x29,0x31,0x86,0xf9,0x2b,0xd8,0x38,0x05,0xf4,0xfe,0x8a,0xba,0x1f,0xbe, - 0x87,0x66,0x3d,0x36,0x20,0x6d,0xb2,0x8d,0x75,0xe3,0xf4,0x0a,0x33,0x46,0xd8,0x7e, - 0x10,0x4e,0xb5,0x6f,0x40,0x52,0x8f,0xec,0x91,0x6c,0x63,0x40,0x1c,0x17,0xa8,0x61, - 0x5e,0x29,0x1d,0xc0,0xfe,0xd2,0x2c,0xd8,0x50,0x50,0x6b,0x2d,0x7b,0x46,0xac,0x65, - 0xeb,0x65,0xd7,0x7a,0x6c,0xbc,0xc7,0xce,0x83,0x56,0x26,0xc3,0x01,0x48,0xb4,0xf7, - 0x0d,0x2c,0x58,0x4f,0x0c,0x3d,0xa2,0x8a,0xa3,0x6e,0xa3,0x44,0x15,0x47,0x04,0x7a, - 0x1e,0xb6,0xce,0xeb,0xa0,0x4e,0x69,0x8e,0xe3,0x5e,0x7f,0x4f,0x4a,0xf4,0x7c,0xee, - 0x29,0xb7,0x9d,0x1a,0xb3,0xbd,0xdb,0x8d,0xdd,0x94,0x5d,0xfe,0x96,0x0e,0x48,0x5f, - 0x16,0xd2,0xf3,0x50,0x51,0x60,0x5d,0x5c,0x32,0x56,0x53,0xeb,0x0b,0x0b,0x33,0xde, - 0x63,0xe7,0xa7,0x41,0xc9,0xc9,0xc3,0x90,0x54,0x22,0x48,0xd4,0xcc,0x6d,0x60,0x83, - 0xec,0x27,0xe9,0x32,0x4e,0xb2,0x78,0xb6,0x95,0xef,0x24,0x4e,0xb5,0x46,0xd4,0xc2, - 0x9d,0xca,0x01,0xa1,0xd3,0x76,0x53,0x20,0xfe,0x16,0x32,0xc7,0x4f,0xb1,0xfc,0xb3, - 0x47,0xde,0x6f,0x06,0x6d,0xd1,0x40,0x09,0x31,0x96,0xb9,0xc2,0xe8,0xc4,0x93,0x9d, - 0x87,0xb4,0xed,0x6f,0x44,0x95,0xc8,0x17,0x9d,0x0c,0xde,0xff,0x04,0xcb,0x9f,0x59, - 0xc1,0x3a,0x0f,0xbb,0x9f,0xe9,0xc1,0xe7,0x41,0x60,0xcb,0xb6,0xbb,0xd6,0x5f,0x67, - 0xf9,0x47,0x51,0xed,0xf3,0xd6,0x2d,0x79,0x0e,0x1e,0x6f,0x7c,0x28,0xd3,0xf3,0x1f, - 0x2f,0x88,0xc3,0x9b,0x90,0x44,0xf7,0x8e,0x8b,0x13,0xc4,0xe8,0x8e,0xa4,0xc5,0x09, - 0xf9,0x4d,0xd8,0x82,0xee,0x4d,0x5b,0x57,0x50,0x24,0x2d,0x3d,0xc9,0xce,0x43,0xdc, - 0xce,0x3f,0x8b,0x34,0xb5,0x5f,0xf5,0x3e,0x26,0xcc,0xf8,0x10,0xe8,0xf7,0x8b,0xe0, - 0x7e,0xf2,0x90,0x9e,0x88,0x74,0x04,0x3c,0xb6,0xcc,0x18,0x64,0xf7,0xef,0x45,0x0f, - 0xa8,0xdf,0xa1,0x7b,0x72,0xb1,0xcd,0xd2,0x8b,0x60,0x1a,0x5b,0xa5,0x73,0xd8,0xa8, - 0xa3,0x86,0x79,0xe5,0x3c,0xcb,0x3f,0x4a,0xb9,0x9d,0x4f,0xd2,0x5c,0x1a,0x91,0xbd, - 0xf9,0x64,0x84,0xe5,0x1f,0x90,0xdf,0x22,0xf5,0xeb,0x6a,0xec,0x6b,0x69,0x3b,0x31, - 0x72,0xa5,0x66,0xfd,0x1a,0xb0,0xeb,0xd7,0x8c,0x55,0xbf,0x0c,0x76,0x7e,0x06,0x2b, - 0xf6,0xea,0x78,0x93,0x13,0x91,0x6d,0xe2,0x62,0xba,0xdb,0x93,0xbd,0xde,0xfd,0x9f, - 0x67,0xdf,0x2f,0x20,0x3b,0x5f,0xe9,0xa2,0xe9,0xb8,0x51,0x82,0x97,0xa1,0x23,0xf0, - 0xb0,0x6b,0xbd,0xc1,0xf2,0x8f,0x46,0xf3,0x8f,0xca,0xe7,0x73,0xaf,0x91,0x65,0xe7, - 0x73,0xd0,0xf4,0x17,0x27,0xd5,0x5e,0xa9,0xd3,0xf4,0xae,0x34,0x30,0x7f,0xb2,0xfd, - 0x20,0xc1,0xbe,0x38,0x58,0x94,0xf0,0x2d,0x63,0x46,0x8e,0xe5,0x9f,0x2a,0xf5,0x98, - 0x62,0x26,0x6d,0x63,0xdd,0x2f,0xe1,0x77,0xb4,0xcc,0x7d,0xe6,0xa9,0x77,0x68,0x3d, - 0x5d,0xbf,0x4f,0xee,0xb4,0x8a,0x54,0x5c,0x4c,0xd8,0xf9,0xdc,0x5b,0x7f,0xb1,0xe1, - 0xe4,0x1f,0x24,0x58,0xf5,0x2e,0xd2,0xdb,0x9a,0x08,0xa9,0xd7,0xd8,0x48,0xb3,0xf3, - 0xa0,0x94,0x99,0x61,0xc9,0x46,0x32,0x49,0x6c,0xa8,0x89,0xb1,0x7b,0x53,0xe2,0x7f, - 0x22,0x6f,0x7c,0x9c,0xfc,0x03,0xbf,0x22,0xfb,0x69,0xc9,0xe2,0x43,0xfe,0x30,0x7c, - 0xa3,0x37,0x8f,0x11,0x37,0x91,0xa7,0xfe,0x4a,0x88,0xe5,0x9f,0x74,0xf9,0x34,0x3c, - 0x0a,0x78,0xd9,0x7c,0xe9,0x98,0x46,0xfc,0x2d,0x9d,0x94,0xbe,0x45,0xde,0xfa,0x3e, - 0x21,0x32,0xde,0x30,0xf9,0xa7,0x39,0x17,0xfb,0xa2,0xa7,0x99,0x9e,0x96,0x21,0xf4, - 0x11,0x72,0x9f,0x9f,0x49,0x76,0x7e,0x90,0x6a,0x43,0xce,0x90,0x98,0x2c,0x30,0x8d, - 0xcc,0x43,0x33,0x7a,0x9f,0x9b,0x7f,0xc4,0x1c,0xfb,0x7e,0x95,0x82,0x13,0x8a,0xe9, - 0x14,0xf0,0xe7,0xa1,0x47,0xf4,0xfa,0xcb,0xf6,0x53,0x6e,0x61,0x8f,0x94,0x16,0x69, - 0x3c,0x5b,0x2f,0x88,0x7d,0x9e,0x78,0x4e,0x3a,0xe7,0xf3,0xd9,0x21,0x1a,0x04,0xb2, - 0xde,0x34,0x86,0xe0,0x3f,0xdc,0xf1,0x11,0x0d,0x96,0x7f,0x3e,0x07,0x9b,0x7f,0xb4, - 0x08,0x8b,0xc6,0xa7,0x3e,0xfe,0x99,0xe2,0xf8,0xc7,0x3e,0x66,0x03,0x52,0x82,0x7b, - 0x1e,0x45,0x77,0xfc,0x27,0x59,0xfe,0xc9,0xca,0xf6,0xb6,0x9d,0xfd,0x8b,0xd3,0xbe, - 0xf3,0xe0,0xf0,0x4f,0xae,0x80,0xe4,0x9f,0xb8,0x11,0xb9,0x23,0x2f,0xff,0xb0,0xfc, - 0xd3,0x21,0x54,0x5a,0x45,0x7f,0x33,0xe6,0x9f,0x23,0x3b,0xb1,0xb1,0xad,0xda,0xcf, - 0x03,0x67,0x38,0xfe,0x89,0xea,0x57,0xa0,0x21,0x17,0x83,0x48,0x14,0xd3,0xce,0x62, - 0x23,0xd6,0x28,0x9d,0x84,0x2b,0x99,0xa6,0x1c,0xe5,0x1f,0xc3,0xcd,0x3f,0xb7,0x99, - 0xf1,0x19,0x8d,0xe5,0x38,0xfe,0xd1,0xcd,0x2b,0x81,0xfc,0x33,0x58,0xe0,0x7f,0xfa, - 0x2e,0xa0,0x6f,0x42,0xf9,0x27,0x3b,0xdf,0xce,0x27,0x7c,0xfe,0x4c,0x87,0xf3,0x8f, - 0x61,0xf2,0x4f,0x9d,0xc9,0x3f,0xcc,0x4d,0xfd,0x15,0x8f,0xbf,0x93,0x2c,0xff,0xb4, - 0x95,0xd9,0x41,0xab,0x0d,0x48,0x3b,0x81,0xfc,0x33,0x68,0x41,0x4e,0x87,0xc4,0xf1, - 0xcf,0x79,0x07,0x84,0xbc,0xfc,0x03,0xb4,0xe8,0xf4,0xe4,0x60,0x2b,0x6c,0x0f,0xae, - 0x47,0x3c,0xff,0xd8,0x45,0x6d,0x8f,0x84,0xeb,0xbb,0xe4,0xaf,0xef,0x8d,0x21,0xfc, - 0xf3,0x34,0xc7,0x3f,0x3e,0xc3,0xc9,0x3f,0x15,0x72,0x2d,0xa5,0xa3,0xda,0xc0,0x7a, - 0xbd,0xcc,0xcd,0x3f,0x8a,0x2c,0x5b,0x45,0x9f,0xf1,0x4f,0x99,0x97,0x7f,0x22,0x3c, - 0xff,0x0c,0x17,0x7b,0xf8,0xe7,0x23,0x8f,0xbf,0x8d,0xc4,0xb8,0xe8,0xf0,0xcf,0x6d, - 0xb6,0x77,0x1f,0x3b,0x6e,0xfe,0xd6,0xc7,0x03,0x0e,0xff,0xec,0x31,0xf9,0xa7,0x45, - 0x4f,0x8c,0xf5,0x8c,0xc3,0x4d,0xf2,0xe9,0xb3,0xd2,0xd5,0x1d,0x1f,0x58,0x98,0xe4, - 0xac,0x67,0xf9,0xa1,0x41,0x35,0xf9,0x07,0x94,0x9d,0x8c,0x76,0x5a,0x73,0xd0,0x1b, - 0xca,0x3f,0x00,0x96,0x53,0x0a,0xe7,0xdd,0xbb,0x4a,0xb7,0x85,0x79,0x8e,0xbf,0xec, - 0xfb,0xaa,0x28,0xb7,0xf8,0x47,0x71,0x85,0xf1,0x89,0x70,0xfe,0x29,0xb3,0x78,0x26, - 0xba,0xc7,0xc6,0x98,0x08,0xd9,0x36,0xde,0xff,0xda,0xa7,0x02,0xf9,0x67,0x10,0x6c, - 0x1e,0x7e,0x86,0x7c,0x2a,0x58,0xd8,0x23,0x92,0x2b,0x1b,0xb9,0xf5,0xe7,0x59,0xfe, - 0x89,0x53,0xfe,0x41,0xeb,0x3c,0xc7,0x6c,0x49,0x30,0xff,0xc8,0x84,0x7f,0x12,0x28, - 0x32,0x48,0x68,0x47,0x48,0xe2,0xd3,0x2b,0x66,0x6d,0xec,0x61,0xfc,0x83,0x79,0x86, - 0x9e,0x87,0xf8,0x63,0x16,0xff,0x44,0x1a,0x0a,0xf3,0x3c,0x2f,0x0e,0xff,0x54,0x09, - 0x36,0x36,0xdc,0x47,0x9f,0xd6,0x5f,0x04,0xf0,0xcf,0x84,0x73,0x7f,0xa5,0x52,0x3d, - 0xe2,0x60,0x0f,0x36,0xb6,0xf5,0x58,0x46,0x24,0x98,0x7f,0xe6,0xd1,0xf7,0x29,0x3b, - 0x7b,0x94,0xbe,0x9e,0x97,0x7f,0xf4,0x02,0xf6,0x92,0x9e,0xd4,0xbf,0x43,0x2b,0x89, - 0x81,0x0f,0xe9,0x40,0xcb,0x38,0x5f,0xbf,0x9c,0xf7,0xdf,0xc1,0xf9,0x26,0xff,0xe0, - 0x4d,0x4a,0x0f,0x60,0x8c,0xa9,0xc2,0xd9,0x58,0x7a,0xc0,0x38,0x4d,0xdc,0xe4,0xf9, - 0x87,0xc5,0x7f,0x00,0xf6,0x52,0x7f,0x89,0xe3,0x55,0xe4,0xd3,0x0d,0xb0,0x4b,0xa8, - 0x33,0x24,0x6e,0xfd,0x7b,0x2c,0xff,0xfc,0x35,0xcd,0x3f,0x16,0xff,0x68,0x86,0x94, - 0xc2,0xeb,0x49,0x3e,0x2f,0xe6,0xe2,0x79,0x86,0x9d,0xcf,0x84,0xcd,0x7b,0xf8,0x22, - 0xa9,0x2f,0x07,0x71,0x76,0x2d,0xea,0xf4,0xd6,0x2f,0xfc,0xfd,0xea,0x6c,0x3f,0xf6, - 0xc5,0x3d,0x01,0xd8,0xc3,0x8c,0x71,0x76,0x9e,0x1f,0x53,0xa7,0x55,0x33,0x69,0x67, - 0x84,0xa6,0xf0,0x17,0x7f,0xa7,0x5e,0x1f,0xdf,0x69,0xf3,0xcf,0x00,0xd3,0x1f,0x24, - 0xcb,0xe0,0x41,0x28,0xa7,0x33,0xfe,0x91,0x59,0x99,0xb3,0xd7,0xa7,0x0a,0xad,0x2b, - 0x8b,0x5c,0xbc,0x44,0xf7,0xaf,0x80,0x59,0xe6,0x46,0xb1,0xbf,0xfd,0x04,0x7b,0x8e, - 0x13,0xc3,0x20,0x57,0x4a,0x9c,0xf8,0x54,0x8f,0x14,0xd0,0xf3,0x80,0x94,0x4e,0x0b, - 0xc3,0x06,0xa4,0xa1,0xb4,0x59,0xdf,0xaf,0x92,0x42,0xac,0x36,0x93,0x8d,0x39,0xbc, - 0xc7,0xf2,0x55,0xfa,0x36,0xd3,0xa9,0x2c,0x7e,0xff,0xb2,0x1d,0xbf,0xdc,0x8d,0xf9, - 0x47,0xc3,0x57,0x78,0xfe,0x29,0x70,0xf3,0x0f,0xa3,0x9d,0xbb,0x89,0xf1,0x16,0x7f, - 0x85,0x18,0x0b,0x1d,0xfe,0x31,0x30,0xff,0x7c,0x43,0x69,0xe7,0x1b,0xa4,0x11,0xef, - 0x12,0x5e,0xfd,0x07,0xd7,0x23,0xa6,0xff,0x14,0xb8,0x9e,0xa6,0x38,0x31,0xfa,0xe9, - 0x95,0x0d,0xd4,0xb8,0x5c,0xc0,0xf3,0xcf,0x6b,0x94,0x16,0x5e,0x83,0x6a,0x62,0x24, - 0x7d,0xfc,0xe0,0xf0,0x8f,0x5e,0xce,0x7d,0xfb,0x57,0xa0,0x91,0x18,0xaf,0xb8,0xcf, - 0x43,0x51,0x46,0x1a,0x63,0xf9,0x27,0xe3,0xe8,0x3f,0x2c,0x1a,0x57,0xdd,0x57,0x76, - 0xe3,0xf8,0xf8,0xf4,0x1f,0xfb,0x6e,0x8d,0x46,0x34,0xd3,0x73,0xbb,0xe8,0x3d,0x9f, - 0x0e,0xff,0x9c,0x29,0x70,0x61,0x70,0xf5,0x74,0x49,0x23,0x2e,0x4c,0x5e,0x7e,0xbb, - 0xe6,0xe1,0x1f,0x27,0x3e,0x39,0x25,0x85,0x1f,0x9c,0x97,0x43,0xf9,0x67,0x92,0xf2, - 0xcf,0x36,0xf1,0x1c,0x4e,0x2c,0x55,0xb9,0x92,0xad,0x96,0x10,0x14,0xaa,0xff,0x44, - 0x2d,0xc8,0x69,0x34,0x69,0xa7,0x01,0xef,0x5f,0xaa,0x83,0xff,0x75,0xf4,0x9f,0xc5, - 0x26,0xff,0xd0,0xe3,0x43,0xf9,0xc7,0x8c,0x86,0x4c,0x84,0xa3,0xd8,0xa5,0xc8,0xb4, - 0xfe,0x99,0x97,0x7f,0x58,0xfc,0x31,0xff,0xe0,0xec,0x54,0x69,0xc7,0xbf,0xbb,0xde, - 0xd8,0x9d,0x91,0xa2,0xae,0xe7,0xf7,0x78,0x30,0xff,0x58,0xd9,0x63,0xb5,0x11,0x99, - 0x14,0x2b,0xe0,0x95,0x50,0xfe,0x41,0x94,0x7f,0x4c,0xef,0xba,0xab,0x88,0xfe,0xd3, - 0x0c,0xbb,0x42,0xf5,0x1f,0xc6,0x3f,0x56,0xf4,0x96,0x62,0xa3,0xa4,0x14,0x79,0xe3, - 0x19,0xc0,0x3f,0x16,0xed,0xd4,0x13,0xe3,0x6e,0x9c,0xef,0x67,0xe7,0x1f,0xab,0xfa, - 0xa8,0xc4,0xd0,0xa7,0x3c,0x20,0x14,0xc0,0x3f,0x76,0x75,0xeb,0x58,0x4c,0x40,0xe8, - 0x83,0x70,0xfd,0x47,0xe6,0xb1,0xc7,0x48,0xea,0xf1,0xbd,0xd5,0xb2,0x53,0x7f,0xbf, - 0xf6,0xf1,0x4f,0x01,0x93,0x7d,0x70,0xe1,0x56,0x93,0xeb,0x4b,0xe6,0xef,0xa8,0xf5, - 0xd7,0x6b,0x3f,0xff,0xd8,0xd5,0xbf,0x5d,0x29,0x2b,0xb9,0x1d,0xba,0xe9,0x95,0x7d, - 0x5e,0xfe,0x69,0x70,0xf4,0x9f,0xb4,0x19,0x8d,0x2c,0x06,0x21,0x5c,0x51,0x43,0xf5, - 0x9f,0xdb,0x5c,0xfe,0x56,0x92,0xb2,0x7e,0x15,0xbe,0x17,0xed,0x2b,0x5f,0x7b,0xf9, - 0xa7,0x42,0x18,0x87,0xdf,0xd8,0xeb,0x95,0x9b,0xd0,0xd2,0x5e,0xfa,0xb1,0x24,0xfb, - 0xe2,0xf3,0x5e,0x39,0x8d,0x7f,0x03,0x78,0xd4,0x9e,0x38,0x12,0x35,0x31,0x9c,0x7f, - 0xda,0x0a,0x3c,0x74,0x87,0x41,0xa8,0x30,0xed,0xf5,0xf7,0x94,0xe0,0xe5,0x1f,0x3b, - 0x7a,0x78,0x7d,0x4a,0x24,0xf1,0x2f,0x0d,0xd7,0x7f,0xa2,0xcf,0x0b,0xcd,0x6b,0x8b, - 0x06,0x04,0xa6,0x6e,0x91,0xef,0xb7,0xd2,0xad,0xff,0xb0,0xf3,0x3f,0x21,0xec,0x87, - 0xbb,0xdc,0xde,0x45,0x7c,0x7a,0x51,0xcd,0x75,0x8e,0x7f,0x34,0x4a,0x3b,0xe4,0x8b, - 0xa8,0x87,0x28,0x8e,0xbf,0x9c,0x95,0x3d,0xfa,0x0f,0x3b,0xff,0x54,0xff,0xc1,0x90, - 0xb3,0x19,0xde,0xd2,0xef,0xec,0x56,0xbe,0x58,0x16,0x87,0xb3,0x60,0x82,0x50,0x10, - 0xff,0x38,0xf9,0x67,0x03,0x64,0x52,0x9a,0x11,0x6f,0x68,0x8d,0x42,0x4f,0x28,0xff, - 0xa4,0x05,0x26,0x9b,0xdc,0x0f,0xc7,0xd0,0xed,0x08,0xba,0x0a,0x9b,0xf4,0xe7,0x6c, - 0x61,0xc4,0xcf,0x3f,0x83,0x50,0x49,0x69,0xe7,0x01,0xf8,0x77,0xcc,0x27,0xd1,0xf3, - 0x52,0xa5,0xf1,0x7e,0x38,0xff,0xdc,0xe6,0xe4,0x5b,0x99,0x80,0x71,0x6c,0x1f,0x7e, - 0x7f,0xf7,0xd4,0xf7,0x1f,0x71,0xfa,0x0f,0x5f,0xbf,0x6e,0x0d,0xb4,0xe4,0xa2,0x67, - 0x22,0x04,0xd2,0x43,0xf5,0x1f,0xc1,0xe6,0x9f,0x15,0x78,0xb7,0xaf,0xa3,0xba,0xc1, - 0xde,0x47,0xc4,0x26,0xd8,0x15,0xae,0xff,0x00,0x97,0xaf,0x0e,0x6b,0x75,0x59,0xa5, - 0x43,0xbc,0x5f,0xf4,0xae,0xe7,0xf4,0x1f,0x3e,0xff,0x64,0xc8,0xf9,0xd1,0xc4,0x3f, - 0xf1,0xc5,0xd3,0xab,0xff,0xd8,0xde,0x65,0x48,0xa3,0xc1,0x10,0xff,0xd1,0xc7,0x3f, - 0x9c,0xfe,0x03,0x5c,0xbd,0x9b,0x22,0xd9,0xe9,0x59,0x69,0xc8,0xc7,0x3f,0x8e,0xfe, - 0x23,0xa8,0x5c,0x77,0xe3,0x5b,0x7d,0x65,0x7b,0x2c,0x1b,0x69,0xd2,0x3e,0xf2,0x54, - 0x40,0x63,0xbd,0x93,0x7f,0x3a,0x9d,0xfa,0xf5,0x86,0xb8,0x46,0x8f,0xfc,0x0a,0xd7, - 0x77,0x6f,0xfd,0xe2,0xf4,0x1f,0xbe,0xde,0x0d,0x93,0x7a,0x4d,0x84,0x0e,0xb2,0xbe, - 0x24,0x98,0x7f,0x64,0xee,0x35,0x3f,0xa3,0xd5,0xf6,0x9a,0xa0,0xe8,0x8d,0x0f,0xa7, - 0xff,0x14,0x74,0x3a,0xde,0x4d,0x68,0x29,0x7d,0x23,0x14,0x35,0xf9,0xea,0xaf,0xe1, - 0xe8,0x3f,0x7f,0x44,0x9d,0xea,0x99,0x86,0x29,0xb5,0x79,0x7d,0xcc,0x08,0xe8,0xef, - 0x70,0xfa,0x4f,0x39,0x3b,0x24,0xd7,0xe0,0x77,0x96,0x71,0xd1,0xcb,0x3f,0x41,0xfa, - 0xcf,0xb0,0xf8,0x25,0x1c,0xed,0x76,0x63,0x4f,0xb0,0xfe,0x43,0x9d,0x1a,0xf5,0x95, - 0xf5,0x20,0xfd,0xa7,0x80,0xb5,0xbd,0xc6,0xc3,0xf5,0x34,0x8e,0x7f,0x1c,0xfd,0x61, - 0x5c,0xf7,0xca,0x0e,0xcc,0x70,0xf8,0x27,0xe7,0xf0,0xcf,0xad,0xf0,0xfe,0x17,0xa7, - 0xff,0xc0,0x90,0x03,0xd5,0xfc,0xfd,0x73,0xd1,0x60,0xfd,0xa7,0x20,0x4c,0x06,0x54, - 0x82,0xf5,0x9f,0xf2,0x0d,0xbe,0x68,0x58,0x46,0x3c,0xbf,0xfe,0xe3,0xb4,0xbd,0x0a, - 0x2d,0x0c,0x50,0xc2,0xf4,0x1f,0x2a,0xf2,0x9c,0x44,0xd4,0x30,0xaf,0x44,0xf3,0xe9, - 0x3f,0x66,0x34,0x74,0x16,0x96,0x1b,0x70,0x4f,0x48,0xff,0x8b,0xd3,0x7f,0xbe,0x14, - 0xbc,0xc7,0x32,0x9f,0xfe,0xd3,0x25,0xed,0xf5,0x61,0xcf,0xa7,0xf0,0x15,0xe5,0x1f, - 0xba,0x7f,0xc3,0xe1,0x9f,0x6b,0x3e,0xec,0xc9,0xa7,0xff,0x10,0xcc,0x76,0x9d,0x37, - 0xf3,0xfd,0xeb,0xe5,0xbc,0xfc,0xe3,0xc5,0x9e,0x60,0xfe,0x91,0x19,0x0f,0x10,0xa3, - 0x08,0x2d,0xe4,0x88,0x68,0x62,0x36,0xfe,0x09,0x36,0xbc,0xfc,0xb3,0x34,0x58,0xf6, - 0x09,0xd2,0x7f,0x1c,0xfe,0x71,0x2f,0xeb,0xc8,0xc7,0x3f,0xb5,0x36,0x0f,0xc8,0x41, - 0xfd,0xaf,0x30,0xfe,0xf1,0xcb,0x5c,0xa1,0xfc,0xb3,0x86,0x38,0xf5,0xb1,0xed,0xdd, - 0x02,0xbf,0xbf,0xfe,0xfe,0x17,0xbe,0xd8,0xc9,0x2f,0x6b,0xd1,0x13,0xc1,0xfd,0x2f, - 0xd5,0xdf,0xed,0xb2,0x0c,0x25,0x90,0x7f,0x14,0x87,0x7f,0x68,0xbf,0xaf,0xd5,0xaf, - 0x08,0x39,0xf9,0xc7,0xc3,0x3f,0xd4,0x10,0xdc,0x8a,0x90,0xbf,0xff,0xc5,0xf5,0x37, - 0xed,0x6d,0x47,0x83,0xf5,0x1f,0x61,0x3f,0xb7,0x4c,0x68,0xd6,0x97,0x04,0x9d,0x07, - 0xb7,0xfe,0x33,0x11,0x18,0xf6,0x44,0xde,0xfe,0x97,0xa5,0xf6,0xc8,0xc4,0x68,0x25, - 0x42,0x50,0x22,0xad,0x84,0xf1,0x8f,0x12,0x9c,0x96,0x95,0x60,0xfe,0x59,0xbb,0x98, - 0x7b,0x7f,0x91,0xd9,0xf3,0x3b,0x6f,0x4c,0x09,0xe6,0x1f,0xa5,0x12,0xbe,0x72,0xe9, - 0x3f,0xd4,0x88,0xce,0xca,0x3f,0xcc,0x50,0x6f,0x40,0x93,0x1e,0xd2,0xff,0xb2,0xfa, - 0x17,0x8e,0xda,0xb3,0xfb,0x7b,0xe9,0xa2,0xee,0xad,0x5f,0x8e,0xfe,0x3f,0x68,0xe5, - 0x9f,0x09,0xbc,0xc9,0x13,0x70,0x44,0xad,0x1b,0x2d,0x36,0x13,0x29,0xd4,0x8d,0xe7, - 0xe5,0x9f,0xac,0xf3,0xe9,0xdf,0x98,0xfd,0xaf,0x3a,0xa3,0x6f,0x76,0xfe,0x61,0x69, - 0xe7,0x10,0x39,0x66,0x3c,0xff,0x80,0x9f,0x7f,0x5a,0x2f,0x68,0xc4,0xd8,0x68,0xb9, - 0xb9,0xdd,0x93,0x3f,0xe9,0x7e,0x5c,0xfc,0x43,0x8c,0x79,0xf9,0xfb,0x5f,0x1c,0xff, - 0xb8,0x5f,0xfc,0x73,0x4b,0x78,0xfe,0xd1,0xe9,0xfa,0x6e,0x9e,0x7f,0x78,0x43,0x8f, - 0x04,0xeb,0x3f,0xee,0x7a,0xb7,0x94,0xad,0xcf,0xba,0xd6,0xb3,0x7c,0x6e,0xf3,0x4f, - 0xb6,0xcf,0x8c,0x86,0x4c,0xa2,0x31,0x72,0x42,0xf3,0xf1,0x00,0x8b,0x3e,0xcc,0x33, - 0xf9,0x27,0x4b,0xbc,0xd3,0x4d,0xef,0x0e,0x5a,0x3c,0x9c,0x8d,0xb8,0xf8,0x87,0xee, - 0xc7,0xd6,0x7f,0xde,0x8d,0x4d,0x0a,0xd3,0x56,0xdb,0x2b,0x23,0x4d,0xa7,0x67,0x48, - 0x47,0x8c,0xe7,0x9f,0xa2,0x60,0xfd,0xe7,0xf1,0x96,0xdc,0xbc,0x29,0xbc,0x6c,0x0e, - 0xfd,0x2f,0x93,0x76,0x20,0x99,0xc3,0x65,0xfd,0x16,0xe1,0xbd,0xd9,0xf9,0xc7,0x5f, - 0x86,0xf2,0xf4,0xbf,0xdc,0xd8,0xf0,0x5a,0x28,0xff,0x40,0xd9,0x50,0xc0,0x79,0xf0, - 0x82,0x50,0x40,0xff,0xcb,0x85,0x3d,0xde,0x7e,0xe8,0x54,0x98,0xfe,0x63,0x19,0xba, - 0xf7,0x4a,0x40,0xff,0xcb,0xda,0x6d,0x22,0x87,0x8d,0x73,0xb3,0xf6,0xbf,0x9c,0x68, - 0xe4,0xfa,0x82,0xf8,0x30,0x98,0x7f,0x88,0x71,0xdd,0xcf,0x03,0x7d,0x21,0xfc,0x73, - 0x42,0xb9,0x82,0xc8,0xfc,0x0f,0xc1,0x1e,0xd5,0x99,0xff,0x99,0x0b,0xff,0x78,0x8d, - 0x59,0xfa,0x5f,0x86,0x07,0x84,0x16,0x86,0xea,0x3f,0xa6,0x71,0xa2,0xda,0xfb,0x3e, - 0xc5,0xf7,0xbf,0x2a,0x7d,0xb4,0x73,0x0e,0x79,0x41,0x68,0x52,0xa7,0xf1,0x6f,0xf3, - 0xe6,0x1f,0xab,0xdf,0xea,0xd5,0x7f,0x6a,0x43,0xf4,0x9f,0x10,0x10,0x0a,0xd7,0x7f, - 0x88,0x61,0xcc,0xa5,0xff,0x85,0xab,0x5b,0xd4,0x36,0x96,0x8a,0x73,0xd5,0x7f,0x20, - 0xd9,0x8a,0x8d,0xa5,0x3e,0x3d,0x87,0xef,0x7f,0x71,0xf5,0xfa,0x79,0x62,0xa8,0x25, - 0xb5,0x7a,0x1e,0xfd,0x47,0xe5,0xf4,0x9f,0x15,0x7a,0x94,0xf4,0xbf,0x64,0xe8,0xd6, - 0x43,0xf9,0x47,0xf1,0xf3,0x8f,0x06,0x5e,0xfd,0xe7,0xa2,0x7f,0xfe,0x87,0xf3,0x2e, - 0x5f,0xff,0xab,0xa2,0x80,0xe7,0x01,0xbc,0x23,0x6c,0x5c,0xd5,0xbc,0xf1,0xf9,0x32, - 0x80,0x7f,0x30,0x7f,0x0e,0xc3,0x4b,0x10,0x11,0xc5,0xcf,0xf3,0xf5,0xbf,0x64,0x9e, - 0xee,0x14,0x0d,0x1b,0x3b,0x46,0xa1,0x5b,0x71,0xfb,0x6b,0x04,0xf1,0x0f,0x31,0xaa, - 0xb1,0x51,0x9d,0xaf,0xff,0xf5,0x52,0x19,0xb7,0xff,0x4b,0x50,0x6f,0xce,0x77,0xf9, - 0xbe,0xdf,0x89,0x9d,0xbe,0xfe,0x17,0xd1,0xbb,0xec,0xb1,0x9f,0xd1,0x59,0xf8,0x87, - 0x8b,0x7f,0xbd,0x18,0x45,0x35,0x56,0xfc,0x77,0xe7,0xe9,0x7f,0xd9,0xfc,0xd3,0x2c, - 0xfc,0xf1,0x00,0xc6,0x9e,0xb8,0xf8,0x64,0x78,0xff,0xcb,0x9d,0x7f,0xb4,0x47,0x4c, - 0xbd,0x2b,0x5c,0xff,0x61,0xfd,0x2f,0xfc,0xb4,0xaa,0x47,0xb4,0x3b,0x1e,0x51,0xb6, - 0x95,0x44,0x61,0x97,0xe6,0xe9,0x7f,0xe9,0xec,0xfe,0x4a,0x25,0xc3,0x1e,0x79,0x26, - 0xbd,0xa2,0x23,0xb1,0x5d,0xaa,0x84,0xf7,0x7b,0xef,0x09,0x9b,0xff,0x71,0xf1,0xcf, - 0x66,0x1c,0x8d,0xc3,0xc4,0xe8,0x70,0xe7,0x93,0x11,0x91,0xc6,0x47,0x2f,0xb8,0x65, - 0xd1,0xce,0x30,0xa9,0x56,0x4f,0xb6,0x74,0x44,0xa7,0xa5,0xbf,0x87,0x99,0xde,0x95, - 0x21,0xf5,0x6b,0x90,0xe6,0x9f,0x6d,0xe2,0xa7,0x3a,0xc1,0x12,0x65,0x52,0x5c,0xac, - 0x1f,0xd9,0xbf,0x9a,0xdf,0x7f,0x2b,0xaf,0xb7,0xec,0x55,0x29,0xf6,0x90,0x4f,0x65, - 0xa5,0xab,0x04,0x47,0x40,0xab,0x72,0xf9,0x3b,0xca,0xf8,0xa7,0x83,0xe5,0x1f,0xab, - 0x9f,0x08,0xa6,0x9e,0x7f,0x14,0x6a,0x5d,0xf1,0x74,0xfa,0x5f,0x71,0x5e,0xff,0x99, - 0x11,0x9b,0x51,0x74,0x32,0x92,0xc0,0x69,0xb6,0xde,0x95,0x51,0xcf,0x05,0xeb,0x3f, - 0x37,0xc8,0x69,0x99,0x33,0xff,0x10,0x63,0xe5,0x20,0x35,0x5c,0xf9,0x7c,0xd2,0xe9, - 0x7f,0xb9,0xf8,0x47,0x5c,0xb6,0xd5,0x2e,0x5b,0xcb,0x5c,0xf5,0x6b,0x3c,0xa8,0xff, - 0x75,0x01,0x7b,0x57,0x6d,0x62,0x12,0x3a,0x6a,0x35,0x6e,0xf2,0xe9,0x3f,0xf5,0x56, - 0xbf,0xc3,0xc6,0x42,0x2d,0x1e,0xa6,0xff,0x28,0x74,0xec,0xa4,0x07,0xc7,0x47,0xaf, - 0x2f,0x8b,0x4d,0xae,0xbb,0x00,0xdf,0xc5,0xdd,0xf1,0xc9,0x39,0xfa,0xcf,0x6d,0xbc, - 0xbf,0xf1,0x7b,0x14,0xfb,0xfd,0xdd,0xa3,0xff,0x14,0xfa,0xf8,0x67,0x42,0xda,0xae, - 0x5f,0x45,0xcb,0xf1,0x69,0x29,0x9a,0x81,0x1b,0x5a,0xcb,0x48,0x34,0xf0,0xfc,0x18, - 0xea,0x16,0x0b,0x72,0x06,0xc5,0x04,0xbc,0x81,0x8d,0xd2,0x61,0xe2,0xa6,0x91,0x18, - 0x53,0xf8,0xfe,0x57,0xa1,0xaf,0xff,0x95,0x16,0x37,0xf4,0x66,0xec,0x17,0x73,0x74, - 0x48,0x4f,0xfe,0x98,0xef,0x87,0x5e,0xf6,0xf3,0xcf,0x4b,0x62,0x27,0xc9,0x66,0x4c, - 0x46,0x6b,0xe5,0xf5,0x13,0x67,0xfe,0x79,0x74,0xbe,0x1d,0x84,0x57,0xf1,0xfb,0xe3, - 0x14,0x9d,0xff,0xc1,0x57,0xda,0x13,0x5c,0x7c,0x3e,0x66,0xfc,0xc3,0xe6,0x9f,0x73, - 0xc2,0x31,0xe5,0xa6,0xba,0x84,0x85,0xa5,0x8d,0xe7,0xe1,0x80,0xfe,0x17,0x99,0xc7, - 0x9b,0xb0,0xfa,0x6b,0xf8,0x7d,0x04,0xd5,0xb7,0x07,0xeb,0x3f,0xac,0xff,0xa5,0x49, - 0x43,0xea,0x30,0x3d,0x36,0x6f,0x83,0xf6,0x17,0x9b,0xf3,0xf7,0xbf,0x34,0xa2,0x07, - 0x66,0x34,0xeb,0x18,0xac,0x84,0x34,0xf0,0xfa,0xcf,0x25,0x56,0xef,0x58,0xff,0x6b, - 0xb3,0xf8,0x22,0xdc,0x83,0xee,0xa0,0xfa,0x4f,0xd5,0xa6,0x5e,0x8e,0x07,0xa6,0x65, - 0xba,0xde,0xe6,0x9f,0x5c,0xac,0x7a,0xdd,0xc9,0xf6,0x9c,0xd6,0x60,0x0b,0x41,0x28, - 0x35,0x9a,0xe0,0xf8,0xe7,0xb4,0x48,0xd7,0xeb,0xff,0xc2,0xf8,0xe7,0xc2,0xfc,0x69, - 0x78,0xd4,0x02,0xa1,0xef,0xa0,0x65,0x74,0xb9,0x13,0x9f,0x85,0x4e,0xff,0xeb,0x55, - 0xca,0x3f,0x38,0x3e,0x05,0x93,0xa2,0x79,0x2c,0x2f,0x62,0x7e,0xae,0x37,0xf8,0xf8, - 0x8c,0x38,0xfc,0xf3,0x34,0x9d,0xff,0x91,0xf6,0xc2,0xbf,0xc1,0x6a,0x32,0xff,0x3c, - 0x0d,0xbb,0x50,0x95,0xc1,0xde,0x1f,0xf1,0x95,0xcb,0x8c,0xaf,0x58,0xff,0xab,0x0d, - 0x7b,0x77,0x78,0x67,0x95,0x85,0x3d,0xcf,0x21,0x6d,0x92,0xd7,0xbb,0xb2,0x8e,0xfe, - 0xa3,0xda,0x41,0xbb,0x4b,0xec,0x87,0x83,0xa8,0xd6,0x28,0xb1,0xe6,0xa9,0xaa,0x27, - 0xd9,0xfb,0x2c,0xbe,0x72,0x16,0x38,0xfe,0x51,0x4c,0xc8,0x99,0xc0,0x5f,0xfa,0xad, - 0xf4,0x41,0x32,0x1d,0x3a,0x01,0x67,0xe1,0x50,0x3a,0xe1,0xe2,0x1f,0xba,0x7f,0x8b, - 0x7f,0xb6,0x3b,0xfa,0x4f,0xa9,0x2d,0xfb,0x88,0xfc,0x44,0xf4,0x29,0x6e,0x7e,0xd5, - 0x2a,0x6a,0x1b,0x07,0x16,0x62,0x63,0xa0,0x3e,0x58,0x1f,0x18,0x61,0xe7,0xc7,0xe2, - 0x9f,0x46,0xab,0xda,0x1e,0x50,0x96,0xe9,0x7d,0xd8,0x50,0x70,0xd9,0x6d,0x8f,0xcf, - 0x45,0xff,0x59,0x6a,0xcf,0x4b,0xa3,0x64,0x3b,0xaf,0x57,0x9c,0x64,0xe7,0x0d,0x4c, - 0xfd,0x27,0x6e,0x8e,0xc1,0xf0,0x46,0xa2,0x3d,0xce,0xf1,0xc0,0x87,0xac,0xff,0xee, - 0xd6,0x7f,0xc4,0x7a,0x6c,0xd4,0x10,0xa3,0x99,0x34,0x62,0x02,0xf4,0x9f,0x33,0xb4, - 0xff,0x35,0x66,0xf6,0xb3,0x6c,0x7d,0xe3,0x92,0xde,0xd2,0xee,0xe2,0x19,0xd9,0xe1, - 0x1f,0x0e,0x93,0xfe,0x4f,0x58,0xa3,0xff,0x2b,0x59,0x76,0x73,0xf0,0xc0,0xb6,0x68, - 0xa0,0xfe,0xb3,0x95,0xf2,0x4f,0x5a,0xcc,0xa1,0x37,0x31,0xff,0x2c,0x42,0xa2,0x81, - 0x86,0xf5,0xea,0x54,0xdc,0x1a,0xcc,0x36,0xd1,0xe8,0x29,0x96,0x7f,0x38,0xfd,0x67, - 0x14,0xbd,0x61,0x0b,0x5f,0xa9,0x7d,0xa0,0xb5,0xf1,0xfa,0xcf,0x29,0x76,0x7e,0x28, - 0xff,0xfc,0xf3,0x33,0x44,0x7f,0x16,0xaa,0x69,0x60,0xab,0x7f,0xcc,0xc7,0xf3,0x71, - 0xb6,0xde,0xd1,0x7f,0xfe,0x6c,0x5c,0xbe,0xa4,0xaf,0xb1,0xe6,0x7f,0xbe,0x86,0xfa, - 0xf6,0x44,0xa0,0xfe,0x33,0x41,0xf5,0x1f,0x73,0x5e,0x48,0x6b,0xd6,0x8b,0xac,0x65, - 0x4d,0x64,0x19,0x43,0xa3,0xcb,0x7e,0xfe,0xd9,0xb9,0x30,0x27,0x66,0xd7,0x36,0xc3, - 0x46,0xe2,0x66,0x76,0x41,0xe3,0x02,0x3e,0xfe,0x23,0xc1,0xfa,0xcf,0x53,0xb9,0x65, - 0xa8,0x94,0x18,0x8f,0xa3,0x1a,0x14,0xaa,0xff,0x38,0xfc,0xd3,0xdd,0xcb,0xde,0x17, - 0xe2,0x61,0xfa,0x0f,0xe3,0x9f,0xc2,0x73,0xa8,0x1f,0xaa,0x8e,0xe3,0xea,0x7f,0x0e, - 0xf5,0x40,0x95,0xce,0xeb,0x3f,0xce,0xfb,0xfe,0x60,0x2f,0xc9,0x57,0x04,0x72,0x16, - 0xce,0x08,0xa3,0x16,0xed,0x7c,0xa6,0xbd,0x8f,0xee,0x1a,0xe7,0xf5,0x9f,0x2f,0x18, - 0xff,0x94,0xd0,0xf9,0x9f,0x4c,0xd1,0x05,0x61,0xca,0xfa,0x61,0xcb,0xb7,0x44,0x28, - 0x6b,0x5b,0xce,0xe7,0x13,0x96,0x7f,0xc4,0xc7,0x6e,0xd1,0xb1,0xe7,0x66,0xfd,0x1a, - 0x7a,0x1b,0x57,0xab,0x1a,0x53,0xff,0x49,0x47,0xb9,0x41,0x0e,0x47,0x9f,0xb1,0xf8, - 0x87,0x4c,0xfb,0x48,0x7f,0x8a,0x0e,0xc3,0xea,0xd1,0x45,0x5d,0xf8,0xe9,0x38,0x02, - 0x0f,0x2b,0x4a,0x97,0xe4,0xe8,0x3f,0x85,0x74,0x3d,0xed,0x7f,0x95,0x60,0x4c,0x82, - 0xc3,0xba,0x83,0x79,0x69,0x25,0xaf,0xfe,0xd3,0xd7,0x80,0xeb,0x57,0x86,0x62,0xcf, - 0x01,0xfc,0xfc,0xf2,0xf1,0x74,0xf2,0x15,0xd5,0x7f,0x4a,0x53,0x52,0x13,0x4c,0x1a, - 0xa6,0x77,0xd3,0x26,0xd8,0x44,0x33,0x4e,0x63,0x2b,0xa0,0xff,0x75,0x80,0xf4,0xbf, - 0x90,0x8d,0x3d,0xff,0x00,0xcd,0x23,0xbb,0xb9,0xf5,0x41,0xfc,0xd3,0xd3,0x04,0x27, - 0xe0,0x4e,0xbb,0xde,0x0d,0x34,0xeb,0xa5,0x5c,0xbd,0xcb,0x3a,0xfd,0x2f,0xa0,0xfc, - 0x83,0xef,0xd6,0x8b,0xd6,0xd8,0x8d,0x30,0x94,0x1c,0xe7,0xeb,0xef,0x84,0x4f,0xff, - 0x59,0x44,0xc6,0x60,0x7a,0x91,0xa3,0xff,0x80,0x92,0x59,0x90,0xf0,0xf3,0x4f,0x89, - 0x6c,0xcf,0xff,0x64,0xc4,0x7e,0xbd,0xd7,0x8c,0x4f,0xab,0x39,0xff,0x8c,0xf8,0x7a, - 0xe7,0xcc,0xff,0xd8,0xfa,0xcf,0x98,0x39,0xdf,0x9b,0xb5,0x7e,0xdf,0x74,0x13,0x6e, - 0xdc,0xd7,0x02,0xc9,0x8c,0xc0,0xce,0x83,0xd1,0xc3,0xce,0xe7,0xf3,0x96,0x53,0x1b, - 0xbb,0x16,0x0e,0x65,0xa7,0xe1,0x6e,0xec,0x5d,0xcd,0x4d,0x98,0xd1,0x3c,0xfc,0xb3, - 0x9e,0xf1,0x86,0x60,0x43,0xce,0xb0,0xf4,0xba,0x3a,0x53,0xd5,0x02,0x7b,0x39,0xec, - 0xc9,0xab,0xff,0x48,0x5b,0xa0,0x6f,0xb4,0x26,0xfd,0x97,0x73,0xeb,0x7f,0x95,0x90, - 0xb1,0xa8,0x43,0x6a,0x12,0x71,0x63,0x4e,0xf9,0xf5,0x9f,0xc2,0x2d,0xf1,0x3e,0xb9, - 0x1a,0x95,0xf8,0x1a,0x49,0x81,0xf3,0x3f,0xf8,0x31,0x29,0x25,0x3f,0x74,0xaa,0x5d, - 0x36,0xe7,0xfe,0x17,0x19,0x03,0x7b,0x0b,0xcd,0xd6,0xff,0x72,0xf4,0x9f,0x6f,0xc5, - 0x4f,0x94,0xca,0x2f,0x4c,0x7d,0x89,0xcd,0x9f,0x7f,0x12,0xda,0xff,0x5a,0x0d,0xdf, - 0xc2,0x6e,0x71,0x95,0x11,0x0f,0xda,0x7f,0x80,0xfe,0xb3,0x4a,0xdc,0xa0,0xf7,0xa8, - 0x09,0xa4,0x59,0xf5,0xda,0xee,0xe0,0x98,0x3f,0xcd,0x08,0xd1,0x7f,0x3e,0x33,0x76, - 0xa1,0xdb,0xf7,0x2b,0x3e,0xfd,0xe7,0xde,0x40,0xfd,0xa7,0x41,0xda,0x80,0xde,0x81, - 0xa6,0x9d,0xd1,0x7a,0x8c,0x3d,0xa7,0x33,0xb6,0xfe,0x73,0x3a,0x8f,0xfe,0x73,0xa6, - 0xf7,0xab,0x05,0x2d,0x3b,0xad,0xc7,0xa4,0x20,0xbf,0xfe,0x83,0xb1,0x70,0x18,0x9f, - 0xcf,0xd3,0xa8,0xe1,0x85,0xe0,0xdf,0x2f,0x78,0xf4,0x9f,0xbb,0x48,0xd2,0x58,0x0c, - 0xbb,0x1e,0xaa,0x42,0x7c,0x1a,0x09,0x9d,0x7f,0xc6,0x98,0x37,0x25,0xbe,0xa8,0x3d, - 0xd7,0x7d,0x47,0xee,0x05,0xea,0xe6,0xa2,0x3c,0xfd,0x2f,0xf3,0x6d,0xe2,0x29,0xad, - 0x07,0xb4,0x31,0x25,0xe8,0xbc,0x79,0xfb,0x5f,0x8d,0x18,0x72,0x4a,0x8e,0xca,0x67, - 0x71,0xed,0x2c,0xf1,0xf5,0xbf,0x22,0x81,0xfa,0xcf,0x4e,0xf1,0x41,0x65,0x4a,0x2f, - 0x14,0x03,0xfb,0x41,0x81,0xfa,0xcf,0x97,0xd1,0x0f,0x50,0xf3,0xda,0xfe,0x81,0x1a, - 0x67,0xe2,0x25,0xaf,0xfe,0xf3,0xae,0xfc,0x1b,0x31,0xb1,0x49,0x99,0xa5,0xff,0x25, - 0x30,0xfe,0xf9,0xad,0xfe,0xc4,0x83,0x76,0x9b,0xe6,0xf9,0xd9,0xe7,0x7f,0x52,0xe2, - 0xb8,0xfc,0xb4,0x90,0xd0,0x79,0xec,0x99,0xad,0xff,0x95,0xc5,0xe0,0xd7,0x4f,0x8c, - 0x33,0xb3,0xcf,0xff,0xb4,0x93,0xfe,0x17,0xc6,0x9e,0xdd,0x41,0xfd,0x1d,0x7f,0xff, - 0xab,0x74,0x4c,0xba,0x4f,0xfd,0x9f,0x65,0x77,0xba,0xb0,0xd0,0xe1,0x1f,0x81,0xc6, - 0x9f,0xd3,0x7f,0x34,0xe8,0xd5,0xab,0xc9,0xfc,0x4f,0xbe,0xdf,0x7f,0x51,0xfe,0x29, - 0x51,0x4b,0x46,0xe1,0x69,0x61,0x7f,0x7b,0x71,0xb0,0xbf,0x01,0xf3,0x3f,0xfb,0x1f, - 0x7f,0x02,0xbf,0xcf,0x16,0x0f,0xb4,0xce,0xe5,0xf7,0x5f,0xa5,0x78,0x93,0xe8,0xbf, - 0x60,0xcd,0x0f,0xe7,0x39,0xdb,0x16,0x99,0x11,0xd8,0xff,0xda,0xa4,0x92,0x79,0xb0, - 0xd2,0x20,0x7f,0x03,0xf4,0x9f,0x1d,0x98,0xb7,0xb3,0x4a,0x99,0x3a,0xc7,0xdf,0x7f, - 0x45,0x36,0xa1,0x86,0xaa,0x5f,0xa3,0x97,0x07,0x19,0xf6,0x2c,0xc9,0xcf,0x3f,0xb5, - 0x62,0x0f,0xda,0x81,0x34,0x34,0xcb,0xfc,0x33,0xe3,0x9f,0x0e,0xfc,0xca,0xf4,0x92, - 0x52,0x43,0xb1,0xe7,0xe1,0xb0,0xf9,0x1f,0xaa,0xff,0x6c,0x96,0x5e,0xc0,0x18,0xb6, - 0x42,0x63,0xb2,0xcf,0x2c,0xf3,0x3f,0x9a,0x94,0x53,0xae,0x8b,0x0d,0x7a,0x2c,0xb3, - 0xce,0x9f,0x4f,0x02,0xe6,0x7f,0xb2,0x18,0x1a,0xcf,0xa6,0x53,0xb5,0x51,0x6e,0x90, - 0x35,0x68,0xfe,0x87,0xea,0x3f,0x7a,0xfd,0x18,0xfa,0xef,0xf4,0xbe,0xae,0x62,0xb2, - 0xed,0x43,0x92,0xd9,0x91,0xcf,0x37,0xff,0xa3,0x8b,0x93,0xea,0xe3,0x6a,0x8d,0x52, - 0x11,0x94,0xaf,0x02,0xfa,0x5f,0x20,0xbe,0x03,0xcf,0x40,0x5a,0xbf,0xc3,0x0e,0xe3, - 0x71,0x7e,0xf0,0x35,0x60,0xfe,0x47,0x15,0xdf,0xd1,0x46,0x40,0xc3,0xaf,0x8d,0x3f, - 0xc2,0x6e,0x0a,0xe4,0x45,0x5b,0xcc,0x37,0xff,0x83,0x8a,0x72,0x08,0x67,0xa7,0xae, - 0x52,0x0c,0x8a,0x74,0xcc,0x35,0x9f,0xfe,0x63,0x48,0x5d,0xf2,0xc9,0xf4,0x21,0xbd, - 0x7f,0x72,0xa1,0x75,0x65,0x1e,0x37,0x08,0xed,0xcc,0xff,0x74,0x53,0xfe,0xe9,0xef, - 0xd9,0x57,0xfd,0x64,0x5b,0x75,0x7b,0x60,0xfd,0xf2,0xf6,0xbf,0xf0,0x6b,0x7e,0xaf, - 0xd8,0xb1,0xae,0x0f,0x3f,0x2f,0x4a,0xe0,0x7a,0xbf,0xfe,0x23,0x88,0x9b,0x60,0x07, - 0x54,0xb7,0x55,0x04,0xf3,0x00,0x0b,0xbf,0xc9,0x3f,0x38,0x1a,0xe8,0x0f,0x3b,0xe4, - 0x2c,0xd4,0xeb,0xd6,0x6b,0xb5,0x6e,0x36,0x7a,0xd8,0x68,0x90,0xe1,0xd7,0x7f,0x46, - 0xa4,0x01,0xb8,0xd6,0xfa,0x68,0xbb,0x2d,0x04,0xcd,0xaa,0xff,0x4c,0x49,0xbf,0x26, - 0xc6,0xe7,0xb8,0x90,0x35,0xc3,0x8c,0x12,0xa6,0x1f,0xf2,0xfd,0x2f,0xc5,0x9e,0xff, - 0x49,0xc2,0xdb,0x7a,0xf5,0xec,0xfd,0xaf,0xfe,0xb2,0x43,0x22,0x01,0xa1,0x1f,0x6e, - 0x80,0x4c,0x3c,0xcd,0xfb,0xbb,0x34,0xac,0xff,0x55,0x68,0x1a,0x9d,0xd6,0x60,0xd5, - 0x6c,0xf3,0xcf,0xf8,0x20,0xc9,0xa6,0x81,0xc3,0x62,0xb8,0xf5,0xb1,0x40,0xfe,0xc1, - 0xd1,0x10,0x89,0x11,0x39,0x06,0x57,0x06,0xde,0x9e,0x9d,0x7f,0x86,0xe8,0x34,0xef, - 0x05,0xf8,0xbe,0xeb,0x60,0x58,0xff,0xcb,0x37,0xff,0x93,0x22,0xfc,0x6c,0x54,0x1f, - 0x9f,0x5b,0xff,0xcb,0xb0,0x07,0xe7,0xb4,0x39,0xf6,0xbf,0x2c,0x0c,0x38,0x8c,0xaa, - 0xc2,0x7f,0xff,0xc5,0xe6,0x7f,0xf4,0x2b,0x6a,0x53,0x0e,0x83,0xd0,0x49,0xb8,0xdc, - 0x91,0xe2,0xfa,0x5f,0x2b,0x7c,0xfc,0xd3,0xec,0xea,0x7f,0x5d,0xd0,0x6f,0xa1,0x59, - 0x7e,0xff,0x95,0xb3,0xdb,0xd0,0x4d,0xb9,0x68,0x03,0x06,0xa1,0xef,0x3b,0xdc,0xf1, - 0xf1,0xf2,0xcf,0x72,0x47,0xed,0x51,0x08,0x08,0x1d,0x50,0xf7,0xe5,0xe5,0x9f,0xe5, - 0xb9,0x62,0xea,0x9d,0x42,0xe6,0xbd,0x8f,0x78,0xfc,0xf5,0xcf,0xff,0x30,0xec,0xb1, - 0xf5,0x67,0x77,0x3c,0xfd,0xf3,0x3f,0xf3,0x48,0x75,0x20,0x46,0x22,0x1d,0x89,0xc3, - 0x2d,0xfd,0xe0,0xef,0xd1,0xff,0xc2,0x86,0xfe,0xd6,0x1c,0xe7,0x9f,0x6d,0x63,0xb0, - 0x7e,0x76,0xfe,0xe1,0xcb,0xae,0x51,0x1d,0xc6,0x3f,0x21,0xf3,0x3f,0xd5,0xb3,0xf1, - 0xcf,0xff,0xb3,0x77,0xfd,0xc1,0x51,0x94,0x69,0xfa,0x9d,0x9e,0x06,0x3a,0xc9,0x24, - 0x69,0x02,0xdc,0x61,0x89,0xda,0x4c,0x58,0x1d,0xdc,0xc9,0x0f,0x03,0x22,0xc5,0x85, - 0xa4,0x09,0xfc,0xc1,0x09,0x77,0xe4,0xb6,0xf6,0x8f,0xfb,0x63,0xcb,0xcd,0x79,0x96, - 0xe5,0xd5,0xe1,0x16,0xe7,0x5d,0xd5,0xb1,0xee,0x95,0xdb,0x09,0xc1,0x4d,0x0c,0x4a, - 0x5c,0xbd,0x5d,0xbc,0xb2,0x76,0x27,0x91,0xb3,0xb0,0x8a,0xad,0x0a,0xc1,0x55,0x64, - 0xf7,0x70,0xc2,0x06,0x6f,0x80,0x08,0x51,0xd9,0x2d,0xd6,0x73,0xdd,0x81,0x4b,0x69, - 0xd0,0xc8,0x05,0x44,0x0d,0x10,0xe0,0xfa,0xfb,0xba,0xfb,0xfb,0xd1,0xfd,0x76,0xcf, - 0xa0,0xe5,0x95,0x55,0xe7,0xfc,0xf5,0x55,0xd2,0x35,0xd5,0xdf,0x3b,0x5f,0x7f,0xdf, - 0xd3,0xcf,0xfb,0xbc,0xcf,0x2b,0xc3,0x00,0x33,0x73,0x5d,0xfa,0x9f,0x4b,0x30,0x58, - 0x9c,0xfe,0xd9,0x1d,0x5c,0x59,0x5d,0x84,0xfe,0x87,0xd4,0x7f,0x35,0x3b,0x85,0xf3, - 0x57,0xac,0x2a,0x5e,0x41,0x4f,0xf0,0x0f,0x7b,0x7e,0x43,0xf4,0x3f,0xf9,0x64,0x18, - 0xfe,0x01,0x1b,0xf6,0xd0,0x49,0x35,0x38,0xb3,0xbb,0x91,0x4e,0x73,0x6d,0xc6,0x1d, - 0x14,0xa5,0xff,0x51,0x5f,0x59,0xe3,0x8f,0xa7,0xb7,0x1e,0x08,0xfe,0x11,0xd0,0xac, - 0x5b,0xc6,0x7e,0xce,0x92,0x7f,0xdf,0x71,0x40,0xf0,0x8f,0x18,0x28,0xa3,0xc8,0xfc, - 0x97,0x37,0x58,0x98,0x2c,0xac,0x7f,0xb6,0xd1,0x8e,0x52,0xeb,0xf0,0x3f,0x07,0x5a, - 0x92,0x05,0xf3,0x5f,0xac,0xfe,0xab,0x85,0x26,0xc2,0xb2,0xeb,0x9c,0x81,0x83,0x7f, - 0xd4,0x00,0xfe,0x71,0x9f,0xd6,0x21,0x0a,0x7b,0x5e,0x05,0x39,0x1f,0x24,0xe3,0x1f, - 0xa9,0xfe,0x6b,0x16,0x19,0x7c,0x62,0xdd,0x51,0x44,0xfe,0x4b,0x67,0xb0,0xe7,0x1c, - 0x1c,0x28,0x84,0x7f,0xec,0xd3,0xca,0xa9,0xff,0x22,0x89,0xb0,0xcb,0x56,0xc3,0x98, - 0xfd,0xb5,0x4d,0xa1,0xf8,0x27,0x4f,0x69,0xab,0x97,0xc1,0x18,0x3e,0xfa,0x83,0xaa, - 0x63,0xf0,0xea,0xde,0x85,0xe3,0x65,0x34,0xb1,0x15,0x86,0x7f,0x6e,0x74,0x66,0x47, - 0xa6,0xf9,0xad,0x77,0xe0,0x97,0xce,0x7c,0x17,0x44,0xe0,0x9f,0xfa,0x5b,0x9d,0x30, - 0xba,0xfc,0x0f,0x3d,0xef,0x12,0xe1,0xf8,0x67,0xbb,0x33,0x3b,0xb6,0x6d,0x92,0xf3, - 0xab,0x2c,0x1d,0x81,0x7f,0xa4,0xd7,0xcc,0x8b,0x11,0xf9,0x2f,0x07,0xe4,0x94,0x49, - 0xaf,0xf9,0x9f,0xf8,0xf2,0x5f,0x02,0xfe,0x41,0xf5,0x3f,0xfb,0x47,0x93,0x91,0xf8, - 0x27,0xa0,0x17,0x32,0x0b,0xe4,0xbf,0x0e,0x96,0xb9,0x65,0xef,0x04,0x16,0x8e,0x68, - 0x7b,0x12,0xc6,0xc1,0x28,0xfc,0x43,0xf5,0x3f,0x1f,0x91,0xc1,0x6f,0x2b,0x5f,0x5a, - 0xf2,0x51,0xf6,0xa2,0x31,0x98,0x0b,0xd1,0x3f,0x53,0xfc,0x43,0xcf,0x2f,0x5a,0xf6, - 0x9e,0xab,0xfc,0x78,0xcb,0x44,0x36,0xa0,0x7f,0xc6,0xf0,0xcf,0x24,0x1c,0x6d,0x6f, - 0xca,0x6e,0x2b,0x96,0xff,0xb1,0x27,0xd5,0x63,0x1f,0x4c,0x5a,0xd1,0xfa,0xe7,0x2c, - 0xb4,0xc7,0x68,0x3e,0x34,0x9a,0xff,0xe1,0xa4,0x99,0xd2,0x63,0xd5,0x66,0x50,0x3c, - 0x89,0xe2,0x9f,0xff,0x86,0xa3,0x56,0xd3,0x43,0x69,0x69,0x61,0x44,0xe1,0x9f,0x4f, - 0xed,0xf8,0xac,0x34,0x8b,0xe7,0x7f,0x26,0x95,0x1c,0xa9,0xbf,0xc0,0xbe,0x3f,0x04, - 0xff,0xf4,0x58,0xfd,0x06,0x7a,0xff,0x28,0xfe,0x19,0x87,0xa7,0x3a,0x8c,0x61,0x34, - 0x3e,0x28,0xfe,0x79,0x5b,0xfb,0xf9,0x3e,0x18,0x0f,0xf2,0x3f,0x61,0xf8,0xe7,0x0c, - 0xbc,0xd5,0x57,0x3f,0x2e,0xa6,0xbd,0x30,0xfd,0x4f,0x39,0x8b,0xcf,0x94,0xfa,0x3e, - 0x34,0x8f,0xa2,0xf1,0xc1,0xf5,0x3f,0xd6,0xc7,0xb1,0x86,0x51,0x34,0x3e,0xb8,0xfe, - 0xc7,0x24,0xf5,0x5f,0xa9,0x62,0xf8,0x1f,0x67,0x76,0x8b,0x9e,0xb7,0x61,0x0f,0x3a, - 0x5f,0x54,0xff,0x7c,0x5c,0xdb,0xbb,0x66,0x51,0xbe,0x28,0xfe,0x87,0x80,0x1c,0xe5, - 0x03,0xb8,0x0a,0x4b,0xac,0x84,0xc4,0xff,0xec,0x0f,0xe2,0x1f,0x86,0x07,0xb2,0xd6, - 0x54,0x5b,0xa3,0x5a,0x3c,0xff,0x73,0xd6,0x3a,0x6c,0x1f,0x8b,0x28,0xbf,0x81,0xe3, - 0x1f,0xad,0xbd,0x35,0xb9,0xaa,0xf4,0x3a,0xf4,0xcf,0xdd,0xb1,0xe4,0x9a,0x2e,0xd4, - 0xaf,0x06,0xc3,0x3f,0x87,0x94,0x12,0x30,0xcc,0x52,0x9c,0x0f,0xf1,0xd6,0x83,0x84, - 0x7f,0xee,0xb6,0x61,0xcf,0xb6,0x62,0xf4,0xcf,0x6e,0x3e,0xeb,0x0a,0xac,0x6c,0xad, - 0xc4,0xe6,0x2b,0xe3,0x1f,0x07,0x3f,0xc4,0x2e,0x18,0x87,0x62,0x4b,0xfc,0xc0,0x20, - 0x5c,0xff,0x1c,0xef,0xd3,0xba,0x62,0xc9,0x42,0xfe,0x3f,0x84,0xff,0x79,0xd2,0x9d, - 0x5d,0xe6,0x19,0x30,0x5a,0x43,0xf4,0xde,0x98,0xfe,0xa7,0xe3,0x99,0x64,0xb2,0xb5, - 0x08,0xff,0x1f,0x86,0x7f,0xde,0x30,0x06,0xf1,0xfb,0x97,0xf8,0x1f,0xcd,0xfb,0xaf, - 0x7e,0x26,0xd6,0xb4,0x16,0xbd,0x3e,0x04,0xff,0xe4,0x9c,0xfa,0xaf,0x42,0xfc,0xcf, - 0x0a,0x96,0xff,0xea,0xab,0xee,0xbb,0x5d,0x80,0x3d,0xd1,0xf9,0xaf,0xb3,0xd0,0x61, - 0x64,0x4c,0xf4,0x79,0x41,0xeb,0xbf,0xfe,0x00,0x9d,0xb0,0xf0,0x74,0x07,0xf6,0xfc, - 0x22,0xfc,0xcf,0xe6,0xf8,0x31,0xe5,0x50,0xfb,0x1d,0xa7,0xd4,0x80,0x10,0x3a,0x5c, - 0xff,0x73,0x91,0xec,0x4e,0xd8,0x7e,0x22,0xe0,0x1f,0xb1,0x7e,0x67,0xaa,0xb7,0x29, - 0x9f,0x98,0x5a,0x1d,0x3c,0xbf,0x10,0xfe,0xe7,0x61,0xe5,0x04,0x8c,0x0d,0xd4,0x4c, - 0x94,0x63,0xf7,0x8f,0xf0,0x3f,0x44,0xff,0xb3,0x33,0x55,0x93,0x43,0xf9,0x6a,0xd1, - 0xff,0x87,0x05,0xed,0x23,0x2d,0x93,0x4d,0xe7,0x4b,0xb0,0x78,0x0a,0xf8,0x67,0x06, - 0x9f,0xaf,0x79,0xaa,0xb7,0xe9,0x20,0xdb,0x3f,0x6f,0x11,0xf7,0x4f,0x0c,0xff,0x9c, - 0x85,0x33,0x2d,0x8d,0x9e,0x5e,0x3a,0x14,0xff,0x80,0xb0,0x7b,0xbf,0x0e,0x0d,0x93, - 0x09,0x6c,0x3f,0x0f,0xc1,0x3f,0xdd,0x56,0x32,0x5f,0x88,0xff,0xe1,0xe7,0xf5,0x18, - 0xec,0x78,0xec,0xf6,0xa1,0x62,0xf9,0x1f,0x52,0x0f,0xd5,0xa5,0x1b,0xb9,0x10,0x3c, - 0xc0,0xc2,0x5f,0x2e,0xd4,0x7f,0x9d,0x34,0x1a,0x4e,0xa0,0xe7,0x0b,0xc2,0xff,0xec, - 0x89,0x4f,0x2b,0xd3,0x6d,0x21,0xe7,0x97,0xdf,0xff,0xa7,0xd9,0x2d,0xfb,0xda,0xd2, - 0x3c,0xb6,0xe1,0xa2,0xbd,0x6c,0x8e,0xf7,0x16,0x81,0x7f,0x1c,0x23,0xc4,0xb2,0x41, - 0x65,0xc4,0xe8,0x31,0x8a,0xd5,0x3f,0x1f,0x26,0xc2,0x27,0x6b,0x4b,0x2c,0x9d,0xed, - 0x09,0xc1,0x3f,0x41,0xdb,0xc3,0x91,0x99,0xe1,0xfe,0x3f,0x52,0xfd,0x3b,0x1b,0xf8, - 0x0b,0x91,0xc2,0xf8,0x1f,0x96,0x0f,0xbd,0x3e,0xfd,0x33,0x1c,0x55,0x8b,0xc2,0x3f, - 0x1c,0x08,0x15,0xc4,0x3f,0xf2,0x63,0xe2,0xd7,0x1f,0xca,0xf8,0xe7,0x2e,0xe9,0xf4, - 0x7f,0xd8,0x1e,0xf8,0xf5,0xc0,0x41,0xfc,0x53,0xde,0xe0,0x96,0x7d,0xd1,0x42,0xf8, - 0xdf,0x40,0xe3,0x44,0x61,0xfd,0xb3,0x33,0x38,0x67,0x4f,0xf3,0x7a,0xf4,0xcf,0xfb, - 0x04,0xa3,0xa4,0x68,0xfc,0xe3,0x0d,0x82,0x7f,0xc1,0xf1,0x8f,0x37,0x08,0x2a,0xa2, - 0x51,0xfc,0x23,0x14,0x82,0x15,0x83,0x7f,0x38,0xec,0x49,0x45,0xd7,0x7f,0x15,0x51, - 0x0f,0x85,0xe1,0x9f,0x39,0xd7,0x51,0xff,0x25,0x94,0x1d,0x7d,0xde,0xfa,0xaf,0x62, - 0xeb,0xdf,0xcb,0xe6,0x12,0xfd,0x4f,0xb8,0xfe,0x39,0xc0,0xff,0x40,0x51,0xf8,0x87, - 0xba,0xd9,0x7c,0x3f,0x6c,0xbe,0x21,0xfc,0x8f,0x3d,0x68,0x9d,0xe5,0xfa,0xe7,0x44, - 0xe0,0x9f,0x71,0xa8,0x8d,0x79,0x68,0xc7,0x58,0x67,0xef,0xd1,0xd0,0xd5,0x57,0x28, - 0xff,0x45,0x66,0xa7,0xd1,0x41,0x55,0xc7,0x70,0x86,0xe9,0x9f,0xfb,0x30,0xfc,0xf3, - 0x42,0x20,0x8c,0x11,0xfe,0x3f,0x4c,0xff,0xb3,0x9a,0x4f,0x24,0xa8,0x7f,0x46,0xf2, - 0x5f,0x10,0xb1,0x30,0x42,0xf0,0x8f,0x53,0x08,0x36,0xa7,0xa8,0xfc,0x17,0x06,0x7b, - 0x0a,0xd5,0xbf,0xbb,0x44,0xd0,0x44,0x71,0xf8,0xc7,0x7b,0x5a,0x93,0x4e,0x3d,0x54, - 0x41,0xfc,0xf3,0xae,0x53,0x08,0xf6,0xfd,0xf8,0x1f,0xad,0x22,0xf1,0xcf,0x65,0xb0, - 0x4f,0x9f,0x3d,0xf6,0x8b,0xff,0x35,0x2b,0x14,0xff,0xcc,0xf0,0xa3,0x9d,0x7d,0xf1, - 0x66,0xe0,0x8a,0x68,0x17,0xff,0xb0,0xf8,0x77,0x79,0xfb,0xcf,0x3f,0x38,0xd5,0xa6, - 0xe3,0x65,0xfb,0xe3,0xdf,0x81,0x97,0xf5,0x34,0x55,0x44,0x17,0xa8,0x7f,0xb7,0x07, - 0xc3,0x36,0x10,0x5a,0xc0,0x11,0x51,0x74,0xfd,0xd7,0x73,0x0e,0xff,0xbf,0x9e,0x3a, - 0xfa,0x16,0xaa,0xff,0xa2,0xb3,0xab,0x23,0xbb,0x6b,0xa3,0xc3,0x60,0x48,0xfb,0xa7, - 0x77,0x3f,0x12,0xff,0x13,0x5a,0xef,0x1c,0xaa,0x7f,0x6e,0xce,0x26,0x9c,0xfc,0x97, - 0x8f,0xff,0x09,0xaf,0xff,0x22,0xfa,0x13,0x35,0xa0,0x67,0x0e,0xe7,0x7f,0x5c,0xfc, - 0xe3,0xbb,0xde,0x5f,0xff,0x45,0x82,0xf0,0x3a,0x19,0xe4,0x1e,0xbb,0xa3,0xc3,0x25, - 0xca,0x1a,0x0a,0xe0,0x1f,0xca,0xff,0xe4,0x12,0xe7,0xa9,0x3e,0x6a,0xf0,0xc4,0xf6, - 0xc1,0x2d,0x51,0xf8,0xc7,0x99,0xdd,0x23,0xc3,0xdb,0xcf,0xc7,0x5d,0x47,0xa0,0x82, - 0xfc,0x8f,0x3e,0x64,0xad,0x30,0x12,0x45,0xf3,0x3f,0x39,0x82,0x0f,0x21,0x85,0xf1, - 0x3f,0xdc,0xff,0x27,0x25,0xf2,0x3f,0xdd,0xb1,0x14,0xce,0xff,0x20,0xfa,0xe7,0x01, - 0x65,0x3c,0xd9,0x6d,0x19,0x38,0x7f,0x22,0xd4,0x7f,0xa9,0x6c,0xfd,0x9c,0x86,0x6c, - 0x6e,0x45,0x03,0xca,0xff,0x70,0xfc,0xdf,0xa7,0xb3,0xf3,0xfd,0xb2,0x0d,0x8d,0x9b, - 0xcd,0x3a,0x0c,0xff,0x4c,0xf0,0xf3,0x97,0xe3,0x9f,0x21,0xc8,0xe9,0x0d,0x90,0x96, - 0xf4,0x3f,0xee,0xbf,0x2e,0x60,0xf5,0x5f,0x1f,0x18,0x5d,0xa3,0xc9,0xb6,0x02,0xfc, - 0x4f,0x96,0xaf,0x87,0xac,0xd1,0xde,0x61,0xf4,0x6b,0x82,0xfe,0x87,0xc5,0x67,0x92, - 0x2d,0x87,0x36,0x9d,0x9d,0xfe,0xbf,0x53,0x3a,0xad,0xbe,0x7e,0x94,0x0f,0x99,0x66, - 0xd7,0x0b,0xfc,0xcf,0x30,0x0c,0x59,0x0d,0xe9,0xb4,0x20,0xfb,0xe1,0xf8,0x67,0xa6, - 0x77,0xbd,0x39,0x97,0xc5,0xe7,0x02,0x5c,0x89,0x85,0xd6,0x7f,0x79,0xf3,0xd5,0x66, - 0x08,0x0f,0x5d,0x8e,0xf8,0xe7,0xa0,0xef,0x6b,0xdc,0xff,0x84,0xe3,0x9f,0x69,0xf2, - 0xfe,0x28,0x6d,0x9b,0x08,0xfe,0x01,0x8e,0x7f,0x7e,0x07,0xcf,0x5b,0x7d,0x06,0x5a, - 0xff,0x9e,0xc3,0xf0,0xcf,0x31,0xb3,0x5f,0x31,0x72,0xa8,0x9e,0xe1,0x6d,0x8e,0x7f, - 0x54,0x86,0x7f,0x2e,0xc1,0x7b,0xd6,0x92,0x90,0xfa,0x77,0x41,0x5f,0xcd,0xce,0xa3, - 0x6c,0xe9,0xc9,0x13,0x38,0xfe,0xa9,0x7e,0x93,0xad,0x07,0xc1,0xff,0xf9,0x3d,0xe5, - 0x70,0x7f,0x28,0xff,0xe3,0x5d,0x6f,0x09,0xf5,0x5c,0x4a,0x77,0x26,0xd5,0x12,0xc2, - 0xff,0x78,0x9f,0xf9,0x2a,0xc7,0x3f,0x66,0x37,0x24,0xff,0x06,0xd5,0x0b,0xe1,0xfc, - 0x8f,0xfd,0x3c,0x96,0xb6,0xe2,0xfc,0x0f,0xd7,0x3f,0x8b,0xf5,0x5f,0x39,0xa8,0xc2, - 0xf9,0x07,0x5e,0xff,0xb5,0xef,0x26,0x36,0xdf,0x4f,0xf4,0x4f,0xc8,0x6a,0xc1,0xe6, - 0x7b,0x96,0xe7,0xb3,0x38,0xfe,0xb9,0x60,0xbc,0x0e,0x4b,0x5a,0xd1,0xf8,0x9c,0x65, - 0xeb,0x67,0x3e,0x64,0x3c,0x90,0x73,0x4a,0xe9,0x82,0x7e,0x4d,0xc3,0xf8,0x9f,0xd7, - 0xd8,0xef,0x6b,0xaa,0x9d,0x6c,0x76,0x99,0xf6,0x76,0x63,0xd5,0x62,0x6c,0xbe,0x82, - 0xfe,0x79,0x2e,0x8f,0x7f,0xb2,0xa7,0x9a,0xe8,0x7f,0x50,0xfe,0xc7,0xbb,0xbe,0x5f, - 0x15,0xf2,0x59,0x43,0xd0,0xd0,0x56,0x8e,0xdd,0xff,0x38,0xfb,0xfe,0x71,0xbe,0x1e, - 0x86,0x89,0xac,0xf7,0x6e,0x4c,0xff,0x33,0xeb,0x12,0xc7,0x33,0x7c,0xbd,0xf5,0x75, - 0xe5,0xa0,0x49,0x4f,0x47,0xf3,0x3f,0x1a,0xaf,0xff,0xba,0x04,0x4f,0x24,0xea,0x06, - 0x34,0x0c,0xff,0xf0,0xfa,0x62,0x8d,0xe3,0x9f,0xed,0xf4,0xbc,0x76,0xf7,0x67,0x5f, - 0x3d,0x0e,0x56,0xff,0x75,0x22,0xb9,0x15,0x6a,0x46,0x51,0x3e,0x24,0xc7,0xf1,0xd5, - 0x7c,0x86,0x7f,0x0e,0x28,0x87,0xac,0x66,0x23,0x81,0xf1,0x3f,0x47,0x30,0xfc,0x33, - 0x66,0xbf,0xf6,0xb9,0x7a,0x83,0x70,0xfe,0xa7,0x4d,0x3d,0x60,0xba,0x87,0xd4,0x25, - 0xe5,0xf5,0xce,0x25,0x99,0x1a,0xec,0xfc,0x3a,0xc9,0xf5,0xc6,0x1c,0xcf,0x8c,0xc2, - 0x56,0x20,0xfa,0xc3,0x38,0xc2,0xff,0xb0,0xeb,0x2d,0xdd,0xad,0xff,0xb2,0xaf,0x37, - 0xb7,0xea,0x21,0x7a,0x45,0x5e,0xff,0x65,0xce,0xdd,0xc6,0xcf,0x3b,0xcb,0x4c,0xf6, - 0x6a,0xd8,0xfb,0xd7,0xa8,0x80,0x57,0xbd,0xf9,0x2a,0x67,0xb4,0xdf,0xc0,0xa0,0x99, - 0x76,0x8e,0x09,0x79,0xbe,0x47,0x78,0xbe,0x55,0x67,0x78,0xe0,0x3d,0xeb,0xb2,0xd9, - 0xf4,0xb7,0xc1,0xf8,0x90,0x54,0x9a,0x2a,0xe0,0x9f,0x98,0xbb,0x69,0x7f,0x00,0xc7, - 0xb5,0x25,0x06,0xca,0xff,0x8c,0x31,0xfe,0x47,0xa8,0xff,0x7a,0x4f,0xe9,0xc9,0x26, - 0x57,0x95,0xa3,0x7c,0x4e,0x1b,0xc3,0x3f,0xfc,0xbc,0xcb,0xb5,0xf5,0x58,0x49,0x0d, - 0x3b,0xef,0xaa,0xf2,0x6c,0xfd,0xb8,0xfe,0x87,0x76,0x10,0x5a,0x4c,0x65,0xcb,0xaa, - 0xa4,0x5e,0x22,0xd8,0x00,0x62,0xf5,0xef,0x54,0x8f,0x44,0x67,0x37,0x0e,0x47,0x5b, - 0xea,0x67,0xaf,0x1f,0x98,0x33,0x11,0x0b,0xe0,0xbd,0x99,0xde,0xfd,0x10,0xff,0x67, - 0x67,0x52,0xd5,0x93,0xf0,0xd9,0xc2,0x57,0x35,0x9c,0xff,0xb9,0x15,0xc1,0x3f,0x57, - 0xe1,0xaa,0x35,0x98,0x4b,0x9c,0x8c,0x1f,0xf0,0x8c,0x80,0x38,0xfe,0x61,0xfa,0x43, - 0x6b,0xbe,0x80,0x76,0xf6,0x5b,0xd5,0x27,0x53,0x3b,0x94,0x5a,0xf0,0xfb,0x3f,0x73, - 0xfc,0xe3,0xf0,0x3f,0xee,0xd3,0x34,0x08,0xc6,0xa3,0xa9,0x01,0xbf,0x31,0x0b,0xc5, - 0x3f,0xf5,0xec,0x7e,0x04,0xfe,0x67,0x3f,0x24,0xad,0xb5,0xbd,0x4a,0x1a,0xca,0x8a, - 0xe3,0x7f,0xce,0x43,0x43,0x7d,0x5a,0x8f,0xef,0x0e,0xd6,0xbf,0x63,0xfd,0x2f,0xa6, - 0xe1,0x2a,0x34,0xd5,0xa3,0xf8,0x67,0x1c,0xc3,0x3f,0x13,0xf6,0x69,0x58,0x6f,0xe3, - 0x9f,0xd5,0x13,0x26,0x17,0x1a,0x39,0xff,0x3a,0x27,0xf2,0x3f,0x3a,0xbf,0x7f,0xe3, - 0x76,0xb0,0xd7,0xc3,0x48,0xc0,0x3f,0xf3,0x53,0x01,0xff,0x08,0xbf,0xbe,0x1d,0x9f, - 0x16,0x4d,0x9f,0x79,0xcc,0xff,0x46,0x26,0xe1,0x9f,0x7b,0xf8,0xe9,0x7f,0xc0,0x5a, - 0xdc,0xa6,0xfd,0x75,0x95,0x03,0x03,0x4a,0x1f,0xc6,0xf1,0xcf,0x7a,0x9e,0xed,0x1a, - 0x84,0xfa,0x4d,0xe9,0xe5,0xd5,0x0e,0xec,0x29,0x5b,0x11,0x5f,0x8f,0xe0,0x9f,0x19, - 0x4e,0x7c,0x66,0xd9,0xd1,0x50,0x3f,0x85,0xbb,0x36,0xd9,0xdb,0xf2,0xb4,0x33,0x4d, - 0x81,0x11,0x42,0xf1,0x0f,0x8d,0xff,0x68,0xba,0x37,0x12,0xff,0xe4,0x4a,0x84,0xf7, - 0xa9,0x97,0x40,0x28,0xfb,0x12,0xf7,0x93,0x8f,0xd9,0xf3,0x6e,0xe8,0x9c,0xff,0x51, - 0x97,0x59,0x46,0x3e,0xf5,0x2f,0x91,0xf8,0xe7,0x01,0x75,0x44,0x8c,0x67,0x72,0x8c, - 0xe9,0xeb,0x44,0x86,0xed,0xbf,0x82,0xfd,0x2f,0x08,0xda,0xf9,0x14,0x96,0xf4,0x26, - 0x0a,0xe0,0x1f,0xb7,0xff,0xc5,0x06,0xe7,0xf4,0x39,0xa0,0xe1,0xfc,0x8f,0x80,0x7f, - 0x16,0xd1,0x43,0x8d,0x96,0x05,0x5d,0xb4,0x1a,0xcc,0x34,0xd2,0xff,0x62,0x8e,0xbf, - 0xfe,0xcb,0x3b,0x6d,0x7b,0xfb,0xef,0x0d,0xd1,0x3f,0x7b,0x1f,0xd6,0xff,0xc2,0x95, - 0xfd,0xac,0x29,0x80,0x7f,0x52,0x32,0xff,0x63,0x48,0x65,0x5f,0x02,0xff,0x63,0xb0, - 0xef,0x97,0xf8,0x9f,0x90,0xfc,0xcb,0xd9,0x59,0x8c,0xff,0x91,0xea,0xdf,0x95,0xe6, - 0x56,0x51,0xc6,0xc3,0xa8,0xa1,0xb3,0xa1,0xfa,0x9f,0x4d,0x09,0xea,0x97,0x18,0x8a, - 0x7f,0x96,0xcf,0x77,0x40,0x4e,0x05,0xa1,0x7d,0xf6,0xc1,0x0a,0xc3,0xc1,0x3f,0x31, - 0x1f,0xfe,0x61,0xfb,0xcf,0xda,0x19,0x9d,0xe2,0xec,0x36,0x52,0xfd,0x73,0x2c,0x02, - 0xff,0xb8,0xf8,0xb3,0xd4,0x91,0x3d,0xdf,0x5e,0x08,0xff,0x08,0xfe,0x3f,0x63,0x73, - 0x2f,0xaa,0x4d,0x6b,0x6b,0x76,0x44,0xe2,0x1f,0xaf,0xff,0x85,0x0b,0x7b,0x56,0xb4, - 0xd4,0x3e,0x83,0xf0,0x3f,0x97,0x84,0xf5,0x23,0xeb,0x7f,0xf4,0x22,0xf2,0x5f,0x1e, - 0xda,0x51,0x0f,0x24,0xea,0x2c,0x2d,0x53,0x35,0x6e,0x7c,0x10,0x8a,0x7f,0xe4,0xfa, - 0xf7,0x58,0xc5,0x1b,0xe4,0x31,0x51,0xf7,0x42,0x22,0x04,0xff,0x58,0xb3,0x25,0xfe, - 0x67,0xe3,0x68,0x89,0x0d,0x84,0x02,0x46,0x5e,0x1c,0xff,0x74,0x69,0x37,0xcb,0x6a, - 0xe7,0x1a,0x14,0xff,0xb0,0xfd,0x47,0x9b,0xb1,0x5b,0xde,0x3d,0x2a,0x6c,0x20,0x14, - 0xd8,0xcf,0x03,0xfd,0x2f,0xf8,0x69,0xb5,0xe0,0x22,0x86,0x7f,0x58,0x7c,0x76,0xf9, - 0xfa,0xef,0x1c,0xb2,0xf1,0xc9,0x3b,0xc4,0x08,0x88,0x4c,0x13,0xc1,0x3f,0x7e,0xfe, - 0xc7,0xd4,0x36,0x75,0x04,0xf7,0xab,0xd7,0x98,0xff,0x06,0xeb,0x7f,0xe1,0x46,0xcf, - 0x4c,0x2d,0x47,0xde,0xbf,0x46,0xad,0x10,0xfe,0xa7,0xd1,0xd4,0x10,0xbc,0xa7,0x1c, - 0x0b,0xf5,0xff,0x31,0x09,0x50,0x04,0x47,0xff,0xcc,0xb7,0xe2,0x71,0xa1,0xff,0x85, - 0x78,0xba,0x19,0xcd,0x9b,0xd2,0xbe,0xf3,0x8e,0x66,0x40,0xf2,0x8c,0xff,0xe9,0x93, - 0xf8,0x1f,0xab,0xb6,0x3e,0xe5,0x19,0xf1,0x55,0x16,0xe6,0x7f,0xec,0xe7,0xa5,0xd5, - 0x3e,0xef,0xde,0xf3,0xfe,0xb2,0xdb,0x2b,0x0d,0xcb,0x33,0xfd,0x98,0xdb,0xff,0x22, - 0xeb,0x95,0xc5,0xad,0xd1,0x96,0xde,0x3f,0x0c,0x8e,0x30,0xb8,0x60,0xfe,0xeb,0x15, - 0x20,0xfe,0xc3,0xee,0x7c,0xcb,0x5e,0xa4,0x8a,0x5c,0x52,0x11,0xf6,0xa7,0xf9,0x47, - 0x83,0xf8,0x87,0xce,0x6e,0xa5,0xf3,0x22,0xef,0x18,0x41,0x3f,0xc5,0xcf,0xf7,0xd5, - 0x6c,0xfd,0x80,0xd2,0x09,0x7d,0x90,0x32,0xed,0xf7,0xc0,0xf0,0x01,0x88,0x1f,0x15, - 0xec,0xbb,0x33,0x41,0x8f,0x1a,0x88,0x1f,0xfb,0x2d,0x1f,0x34,0x53,0xd1,0xa3,0x06, - 0x5f,0xe4,0xfb,0x2d,0x7b,0xb1,0x6a,0xa4,0xbf,0x59,0xc4,0x40,0xf8,0x44,0x5f,0xe8, - 0x0c,0xbe,0xc8,0xf7,0x5f,0xef,0xe7,0x2b,0x16,0x7f,0x9d,0xf4,0xf2,0x1b,0x81,0x7f, - 0x84,0x05,0xd9,0x88,0x81,0xfa,0xb9,0xbf,0xff,0x4b,0x8e,0xbf,0xaa,0x5b,0x45,0xc4, - 0x3c,0xc6,0xf6,0xc3,0xeb,0xfd,0x34,0x36,0x16,0x73,0x55,0x65,0xe5,0xe7,0xfc,0xfa, - 0xff,0x83,0x4f,0xf3,0xb5,0x6b,0xd7,0xb2,0x05,0x06,0xff,0x9f,0xaf,0xff,0x8a,0x3d, - 0x8f,0x5f,0xef,0x87,0x5f,0xef,0x87,0x5f,0x20,0xfe,0x5f,0xef,0x87,0x85,0x3e,0x5f, - 0xb5,0xfd,0xe7,0xab,0x75,0xbd,0xc4,0x8f,0x5d,0xb1,0xee,0x20,0xfe,0x90,0x81,0xf7, - 0x8b,0x59,0x58,0x7e,0xb0,0x65,0x84,0xea,0xc7,0xb4,0x7d,0x0e,0x90,0x0e,0xe5,0xc7, - 0xd8,0xfb,0xc2,0x36,0xd8,0x13,0x33,0x86,0x6e,0x88,0xce,0x0f,0xe6,0xe7,0x09,0xec, - 0x62,0xb7,0x91,0xcc,0x17,0xc8,0x0f,0xc6,0xb8,0x3f,0xe4,0x36,0xed,0x1c,0x3c,0x94, - 0xc5,0xfc,0x42,0x15,0xce,0x8f,0xb5,0x8b,0xfe,0x90,0xd3,0x6a,0x48,0xfe,0x2b,0x84, - 0x1f,0x3b,0xec,0x1a,0x75,0x06,0xf8,0x1f,0x34,0x3f,0x38,0xd1,0xd9,0x15,0x4b,0x4f, - 0x26,0x8a,0xd6,0x87,0xff,0x25,0x69,0xd3,0x70,0x01,0xcd,0x9f,0x9e,0x63,0xbf,0x17, - 0xd7,0x87,0xcf,0x7c,0x17,0xb6,0x5a,0x35,0x63,0x68,0x7e,0xf0,0x2a,0xbb,0x9e,0xe4, - 0x07,0xf7,0x7a,0xfc,0xd8,0x10,0x34,0x0e,0x57,0x60,0xfa,0xf0,0xb7,0xd8,0xfb,0x69, - 0x9b,0xa0,0x8f,0x52,0xec,0xd9,0x0d,0x6f,0x38,0x87,0xe5,0x07,0x15,0x6f,0xbe,0x5e, - 0x7f,0x58,0x1a,0xf6,0xa1,0x58,0x03,0xb1,0x0d,0x3f,0x4b,0xfd,0xdb,0x2b,0x70,0x7e, - 0x4c,0x17,0xde,0x37,0x3b,0xe1,0xce,0x2c,0xd5,0x67,0x06,0xfc,0x21,0xd9,0xfb,0x20, - 0x88,0xfa,0xa8,0xad,0xd9,0xea,0x36,0x6d,0x73,0xd5,0xbb,0xea,0x8f,0xda,0x6b,0xf2, - 0x4a,0x48,0x7e,0x90,0xad,0xb7,0x09,0xb0,0x72,0x8b,0x1c,0x5a,0xcc,0xaf,0x37,0x7b, - 0x3b,0xa0,0x8f,0x2a,0x27,0x6c,0xd8,0x6b,0xd0,0xd0,0xa1,0x79,0xfe,0x90,0x15,0x38, - 0x3f,0xc6,0xf5,0x51,0xa7,0x94,0x29,0x15,0xef,0x8f,0x36,0xe7,0x4d,0x76,0x5e,0x88, - 0xfe,0x00,0x70,0x38,0xd3,0xd0,0xba,0x81,0xf8,0x03,0x44,0xe5,0x07,0x39,0x3f,0x66, - 0x95,0x9c,0x52,0x02,0x7a,0xa7,0xa6,0xd0,0xfc,0xe0,0x7d,0x66,0x37,0xf4,0x17,0xd2, - 0x47,0x81,0x9c,0x1f,0x4c,0x99,0x9e,0x3f,0x52,0x88,0x3e,0x6a,0x33,0xef,0x8f,0x96, - 0xa5,0xf9,0xdf,0x5b,0x2c,0x25,0xe8,0x87,0x29,0xf0,0x63,0x42,0x7d,0x9c,0x72,0x05, - 0xee,0x0c,0xe8,0xa3,0x56,0x50,0xbe,0x4b,0xe4,0xc7,0x3c,0xbd,0xf4,0x6f,0xe1,0x2f, - 0xe0,0x87,0x8e,0xb0,0x3c,0x82,0x1f,0x73,0xfb,0xa3,0x51,0x36,0xcc,0xb3,0x85,0xb4, - 0x02,0xf9,0x41,0xb6,0xff,0x98,0xa2,0x3f,0x52,0x7b,0xcc,0xfe,0xf5,0xa3,0xf3,0x83, - 0x3b,0xe6,0x89,0xf9,0xd9,0x58,0xed,0xda,0x10,0x7d,0xb8,0x77,0xbd,0xc8,0x8f,0xc1, - 0x61,0xdd,0xeb,0x0f,0xab,0x3c,0x12,0x96,0x1f,0xc4,0xeb,0xe3,0x8a,0xc9,0x0f,0x66, - 0x20,0x57,0xda,0x50,0x6c,0x7f,0xd8,0xb2,0x8c,0x72,0xb9,0xed,0x09,0xf3,0x9b,0x4f, - 0xa3,0xfa,0xa8,0x83,0x9c,0x2f,0xed,0x64,0xfb,0x4f,0x1d,0x74,0x0c,0x1b,0x43,0x65, - 0x05,0xf2,0x83,0xc0,0xf9,0xb1,0xaa,0x47,0xbb,0x16,0xe3,0xf9,0x7d,0x21,0x3f,0xd8, - 0x75,0xb3,0xee,0x92,0x60,0xff,0x06,0xff,0xd9,0x49,0xcb,0xe2,0xfe,0x18,0xc5,0x8f, - 0x2d,0x60,0xfb,0xed,0x29,0xda,0xd8,0x9a,0x6c,0xb3,0x46,0x78,0x7e,0xd0,0xe4,0xe7, - 0xd7,0x0f,0xe0,0xb8,0x25,0x97,0x75,0x63,0xf9,0x41,0xd6,0x1f,0x4d,0xd9,0x6c,0xfe, - 0x68,0xfe,0x9d,0x16,0x7a,0xff,0x1f,0xf0,0xe7,0xd1,0x22,0xfb,0x15,0x9d,0xe6,0x49, - 0xf8,0x39,0x2c,0x94,0x6c,0x10,0x78,0x7e,0x90,0xf1,0x63,0xdc,0x1f,0x52,0x59,0x0b, - 0x4f,0x65,0x17,0x39,0x1b,0x51,0x80,0x1f,0xeb,0x64,0xbf,0x17,0x3f,0xbf,0x36,0x56, - 0xfd,0xde,0x6a,0x68,0xab,0x18,0xf0,0xf2,0x11,0x68,0x7e,0xd0,0xe2,0xfd,0x1a,0x36, - 0xc2,0x99,0xb6,0xa6,0x49,0xf4,0x3c,0x12,0xf3,0x83,0xbc,0xde,0x07,0x58,0x5b,0x90, - 0xe3,0x8e,0x3f,0x00,0x9a,0x1f,0xf4,0xce,0x2f,0xc8,0xaa,0x1f,0x66,0x49,0xff,0xd3, - 0xf8,0xee,0x80,0x3f,0xb3,0xc0,0x8f,0xc5,0xd8,0xf5,0xe3,0xb1,0x9e,0x6c,0xed,0xa4, - 0xa3,0x07,0x56,0x7c,0xfc,0x18,0xcf,0x0f,0x52,0x3d,0xcc,0x46,0x12,0x84,0x9c,0xfe, - 0x9c,0x07,0x0c,0x9e,0x13,0xf9,0xd8,0x1b,0xed,0xf5,0xc6,0xf1,0x36,0xe5,0xc7,0x68, - 0xdb,0xf1,0x29,0x38,0xaa,0xd0,0x7c,0xf1,0x34,0xd5,0x3f,0x97,0x8b,0x7e,0x50,0x1d, - 0x8c,0x1f,0xbb,0x69,0x5a,0xff,0xa1,0x37,0xdf,0xf7,0xc3,0xfc,0x8d,0x05,0x7f,0x24, - 0xc7,0x5f,0x2b,0x9b,0x58,0x1b,0x6f,0x80,0xd7,0xed,0xd5,0x72,0x0b,0xd6,0x5f,0x58, - 0xf0,0x87,0xd4,0x1c,0x90,0xa3,0x59,0x4a,0x0a,0x4e,0x31,0x5b,0x6c,0x59,0x1f,0x1e, - 0x1f,0xe0,0xfd,0xd1,0x60,0x9b,0xba,0x37,0x96,0x36,0xbb,0x08,0x6a,0x6f,0x67,0xcb, - 0xc0,0x08,0xd5,0x47,0x01,0x0d,0x5a,0x4b,0xaa,0xb3,0x34,0x45,0x84,0x9a,0xfe,0xc2, - 0xc3,0x00,0xfe,0x71,0x48,0xd1,0xc9,0x44,0xb7,0xb2,0xd0,0xe8,0xae,0xf7,0xda,0xc6, - 0xc5,0x1f,0x91,0x12,0xeb,0x42,0x7e,0x70,0x36,0xad,0x7f,0x1f,0xaf,0xcb,0xda,0xf1, - 0xf9,0xc8,0x72,0xc2,0xa2,0xfb,0xe3,0xb3,0xcb,0x87,0x7f,0x1a,0x5b,0x13,0x9d,0x65, - 0x86,0xbd,0xbf,0x35,0x0c,0xb9,0xf5,0x08,0xb2,0xff,0x00,0xcf,0x0f,0x66,0x9d,0xfc, - 0xa0,0xa9,0x3d,0xa6,0xfc,0x3d,0xfc,0x9e,0xcb,0xe4,0x64,0xbd,0x1c,0xcf,0x0f,0xe6, - 0xe8,0x7a,0x30,0x2c,0x1b,0x46,0xde,0xaf,0xfc,0x18,0x5c,0xdb,0x84,0xa7,0x7c,0xf5, - 0xec,0x1c,0xff,0x4c,0x52,0x7d,0xd4,0x83,0x3b,0x53,0x53,0xca,0x77,0xcd,0x9f,0xd0, - 0x32,0x79,0xc7,0x1f,0x32,0x4c,0x1f,0x35,0x9f,0xe8,0xa3,0xea,0x87,0x13,0xf5,0xf1, - 0xfb,0xf3,0x6f,0x82,0x6b,0x0b,0x70,0x19,0xea,0x43,0xf0,0x8f,0xab,0x8f,0x22,0x6d, - 0x61,0x77,0xc3,0x55,0xcb,0xf1,0x57,0xb7,0xff,0xf2,0xaa,0x37,0xf0,0xe9,0xc3,0x5d, - 0xfc,0x63,0xd9,0xb0,0x67,0x11,0x81,0x0d,0x3c,0x2c,0x1b,0x06,0xaa,0x11,0xfc,0x33, - 0xa2,0x51,0x7f,0x36,0x22,0x33,0x68,0x84,0xe7,0x03,0xfd,0x41,0x02,0xf8,0xc7,0x70, - 0xf1,0x8f,0x36,0xa5,0xfc,0x09,0x3c,0x6a,0x7d,0xc3,0x99,0xa6,0xdb,0x0f,0xee,0x9e, - 0x20,0xfe,0xd9,0xe8,0xea,0xcd,0xa8,0x2d,0x40,0xbf,0x6f,0xdb,0xc1,0xf0,0x0f,0x10, - 0xfc,0xd3,0x6c,0xa5,0x8c,0x39,0x1a,0x6b,0x8b,0x16,0x2b,0xa4,0x8f,0x6a,0x84,0x0d, - 0x56,0x59,0x1e,0xa6,0x43,0xf5,0xe1,0x01,0x7d,0x54,0xa2,0x77,0xce,0xfd,0x96,0x5f, - 0x36,0x3c,0xe6,0xa5,0x0e,0x83,0xf8,0x27,0xd1,0xab,0xdc,0x06,0xdd,0x66,0xa8,0x3e, - 0xdc,0xfb,0x78,0xf9,0xc1,0x6f,0x3e,0xad,0x2c,0x85,0xc7,0x0b,0xeb,0xc3,0x8d,0xb9, - 0x0e,0xfe,0x29,0x3d,0x51,0xfa,0xcf,0xca,0xd6,0xac,0x57,0x2f,0x1f,0xaa,0x0f,0xdf, - 0x7c,0x93,0xd0,0x1f,0x76,0x24,0x6c,0xbe,0x1c,0xff,0xec,0xa3,0x78,0xa0,0xae,0x75, - 0xbd,0x1e,0x0f,0x3f,0xe8,0xe7,0x70,0xfc,0xb3,0x9c,0x5e,0xbf,0xcc,0xac,0x18,0x8d, - 0x2f,0x85,0x3f,0x80,0x57,0x56,0x6f,0xca,0x78,0x40,0xd4,0x47,0x51,0x90,0x33,0x57, - 0xeb,0x50,0x0c,0xab,0xcb,0x20,0x65,0xf2,0x04,0xf6,0x2c,0x0c,0xcd,0x0f,0x42,0xa7, - 0xeb,0x8f,0xd4,0xd1,0x69,0x38,0xfe,0xd8,0xca,0x9a,0x28,0xfc,0x03,0x6e,0x7f,0x58, - 0xbd,0x94,0xb4,0x99,0x53,0x4c,0x85,0x08,0xb9,0x23,0xf0,0x8f,0x4a,0x6f,0xf2,0xde, - 0x0a,0xc7,0xdd,0xf1,0xc7,0x6e,0x22,0x58,0x9e,0xaf,0x22,0xe4,0x07,0x1d,0x7f,0x6c, - 0xbc,0x2c,0x0e,0xcb,0x0f,0x02,0x5d,0x6f,0x34,0x2d,0x68,0x90,0xfa,0x38,0x16,0xf6, - 0x72,0x1e,0xff,0x59,0x41,0x7d,0x94,0x96,0x57,0x2e,0xc2,0xbb,0x66,0x12,0xd7,0x87, - 0x73,0xfc,0xa3,0xcd,0x5d,0xef,0x3d,0x2f,0xbf,0x30,0x5f,0xc8,0x0b,0xb0,0xa7,0x04, - 0xc5,0x3f,0xa0,0x7f,0x07,0x7e,0x0a,0x0f,0x66,0xb5,0x56,0xe5,0x02,0xbc,0x6c,0x7a, - 0xf8,0x47,0xf5,0xe3,0x1f,0xef,0x93,0xd8,0x71,0x8f,0x0d,0x72,0x1a,0xf3,0x89,0x07, - 0xe2,0x07,0x60,0xc2,0x7a,0xc5,0x85,0x3d,0x03,0x37,0xe5,0xcb,0x39,0xfe,0x51,0x38, - 0xfe,0x29,0x75,0xf3,0x65,0x75,0x96,0xfd,0x9a,0xf0,0xb6,0xe3,0x07,0x68,0x6f,0x23, - 0x9b,0x96,0x49,0xfb,0xed,0xc1,0x59,0xde,0x7c,0xef,0xe5,0xf9,0xc1,0x47,0xec,0x41, - 0x83,0xd7,0x28,0xc4,0x06,0x42,0x42,0xa2,0xf0,0x24,0xf3,0xd3,0xde,0xa5,0x39,0xef, - 0x5f,0x95,0xad,0xf1,0xad,0xd6,0xab,0xb0,0x30,0xef,0xc8,0xc2,0xf5,0xc5,0xb2,0x3e, - 0x9c,0xe7,0x07,0x2d,0xcf,0xcf,0x56,0x79,0xc7,0x78,0xd9,0x5c,0x98,0x73,0x65,0xe1, - 0x0b,0x25,0x7d,0xb8,0xa0,0x8f,0xf2,0xf4,0x09,0x60,0x2f,0xc2,0xbd,0x16,0xdb,0xc6, - 0x65,0x3c,0x29,0xea,0xa3,0xdc,0x49,0xd5,0xc7,0x4f,0xc3,0x45,0xc3,0xf5,0x07,0xb8, - 0x66,0xbf,0xc8,0x8b,0xfd,0x2f,0x8e,0x09,0xfa,0x28,0x7a,0x1e,0x65,0x2b,0x5e,0x8c, - 0xff,0x3b,0xf0,0x36,0x22,0x62,0xbd,0xd2,0xf6,0x01,0xfb,0xfd,0xdd,0x9f,0x1f,0x4c, - 0x5c,0x8a,0x13,0x7f,0xc8,0x25,0x38,0x1e,0xc8,0x30,0xfc,0xe3,0xe5,0x07,0xb5,0x17, - 0x4b,0x67,0x11,0xff,0xa2,0x6c,0x89,0x73,0x6c,0xad,0x90,0xf2,0x83,0xa7,0xb8,0x3e, - 0x6a,0x86,0x73,0x7d,0xea,0x45,0xe5,0x7b,0xd0,0xe3,0x3b,0xe6,0x98,0x3e,0x2a,0xc3, - 0xf1,0x8f,0x9b,0x1f,0xd4,0x06,0x94,0xfb,0x5a,0x7a,0xc0,0xc8,0x95,0x34,0xcc,0x24, - 0xf9,0x68,0x2d,0x5b,0x8a,0xeb,0xc3,0x6f,0xd8,0xa8,0x91,0x49,0x25,0x88,0x4d,0x50, - 0x0f,0x0c,0x1e,0xa9,0x24,0xb2,0xf0,0xcf,0xec,0xbf,0xdc,0x38,0xc8,0xe3,0xc3,0xbf, - 0xbf,0x9f,0xe7,0x07,0x5f,0xb4,0x88,0xff,0x4f,0x39,0x3b,0xb6,0xf6,0x08,0xf8,0xe7, - 0x1b,0xde,0x7e,0x32,0x34,0xe3,0xaa,0x2e,0xa0,0xe5,0x95,0x79,0x4c,0x1f,0xbe,0x5a, - 0xc0,0x3f,0xf3,0x7d,0x6a,0x70,0x5c,0x1f,0x3e,0x53,0xc0,0x3f,0xf2,0xe9,0xa3,0xd5, - 0x57,0x8d,0xe8,0x11,0xfc,0x8f,0xba,0x5b,0x97,0xa2,0x87,0xf3,0x3f,0x6c,0x3d,0xac, - 0x9a,0x27,0xa8,0xe9,0x7e,0x45,0xda,0x7e,0x61,0x78,0x78,0x34,0xe8,0x8f,0xed,0xfd, - 0xfa,0xb7,0xf8,0xd7,0xc3,0x50,0xa5,0xcf,0x1f,0x5b,0xfd,0x50,0x5c,0x5d,0x58,0xfe, - 0x5a,0xc0,0x3f,0x72,0x7f,0xd8,0x58,0xed,0x69,0xd4,0xdf,0x32,0x44,0x1f,0x65,0x0f, - 0xf2,0x5d,0xd8,0x79,0x3d,0xc5,0x28,0xee,0x29,0x51,0x1f,0x65,0x0f,0xc6,0x4a,0x51, - 0x7d,0xb8,0xe0,0x8f,0x2d,0xe8,0xa3,0x3e,0xb6,0xe4,0xb6,0x68,0x6c,0xf0,0x36,0xf7, - 0xc7,0x9e,0x27,0xc5,0xa7,0x69,0x08,0xd7,0x87,0x33,0x7c,0x98,0x92,0xf5,0x0c,0x8d, - 0x59,0x35,0x5a,0x1f,0x9e,0xd3,0x16,0x78,0x26,0xd8,0xce,0xb6,0x49,0xf8,0x1f,0x35, - 0x80,0x7f,0xb8,0xfe,0xc1,0x5f,0x1f,0x87,0xf2,0x5d,0xa2,0x3e,0xca,0x59,0x6f,0xa5, - 0xd8,0x36,0xce,0xeb,0xe3,0x04,0x7f,0x6c,0x49,0x0d,0x55,0x6b,0xe1,0xfa,0x28,0x5e, - 0x1f,0x17,0x43,0xfd,0x6a,0x02,0xf5,0x71,0xde,0xf5,0x82,0x3e,0x7c,0xcc,0x05,0x42, - 0x05,0xf4,0xe1,0x82,0x3e,0xea,0x22,0x2c,0x37,0x53,0x28,0xfe,0xe1,0xf5,0x6b,0x31, - 0x5f,0x7d,0x1c,0xaa,0xe7,0xe1,0xfe,0xd8,0x06,0xe5,0x7f,0x36,0xd2,0xd3,0x5f,0xbd, - 0xc3,0x3e,0xfd,0x51,0xbf,0x44,0xee,0x8f,0x2d,0xe0,0x1f,0x3a,0x3b,0xab,0x5c,0x9a, - 0xef,0xbe,0x40,0x7d,0xdc,0x0d,0x7c,0x76,0xda,0x19,0x58,0xe1,0x09,0x81,0xa4,0xf9, - 0x56,0xa3,0xfe,0xd8,0x64,0xb0,0xd2,0xd4,0xa4,0xeb,0xdd,0x7e,0xb2,0xaf,0xcd,0x15, - 0xf4,0x51,0x9c,0xff,0x19,0xb7,0x07,0xe5,0x88,0x3e,0xbc,0x45,0xe8,0x0f,0x0b,0x9d, - 0xf2,0xec,0x50,0x3d,0xd8,0x8f,0x39,0xfe,0x11,0xfb,0xad,0xbc,0x40,0xe3,0x89,0xfa, - 0x43,0x7a,0xd7,0x67,0xe4,0x7e,0x28,0x8d,0xf8,0xef,0xbb,0x8b,0xaf,0xff,0xd8,0xce, - 0xf0,0xb2,0x41,0x6f,0x70,0xdb,0x79,0x9d,0xaf,0x1f,0x81,0xff,0xb1,0x07,0x0a,0xaa, - 0x8f,0x3a,0x18,0xe2,0x8f,0x04,0x75,0x5d,0x98,0x3e,0xfc,0x5b,0x42,0x7d,0x9c,0xba, - 0x5e,0x76,0xa3,0x95,0xf5,0xe1,0xee,0x1b,0x3a,0xaf,0x8f,0xb3,0x6c,0xfc,0x23,0x3d, - 0xad,0xa8,0xbe,0x91,0xd7,0x43,0x75,0x75,0xdd,0xe3,0xf1,0x3f,0x3f,0x23,0x68,0x27, - 0x23,0xeb,0xc3,0xdf,0xf7,0xfb,0x63,0x6b,0xb2,0x5e,0xa8,0xc9,0xaa,0xc3,0xf7,0x13, - 0xb6,0x3f,0xa8,0xbf,0x96,0x4e,0x2b,0x23,0x3d,0x55,0x8d,0xf9,0x03,0x78,0xf1,0x91, - 0xf4,0x51,0x7b,0xa1,0xa6,0x0b,0xf7,0x07,0xe0,0xfe,0xd8,0xd6,0xb3,0xd2,0x7f,0xa1, - 0x90,0x3f,0xa4,0x4f,0x1f,0x65,0x2d,0xc6,0xf6,0x1f,0xd1,0x1f,0x5b,0x9c,0x9d,0x1a, - 0x72,0x7e,0x09,0xfe,0x00,0x31,0xac,0x5e,0x3b,0xbc,0x3e,0x6e,0xa1,0xfe,0x6b,0x4d, - 0xdc,0xbd,0x2d,0x54,0x1f,0x9e,0x0b,0xe0,0x1f,0xef,0xb4,0xca,0xa0,0xe7,0x57,0xd0, - 0x1f,0xbb,0xcc,0x6d,0xe3,0xc5,0xfd,0x7c,0x42,0xfa,0xc3,0x8a,0xfa,0x28,0x12,0x1f, - 0xdc,0x2f,0x9a,0xfb,0x63,0x3f,0x2e,0xe8,0xa3,0x3e,0x34,0xe9,0x8b,0x36,0x52,0xff, - 0x55,0xcd,0xea,0xe3,0x24,0x7d,0x54,0x6a,0xa5,0x85,0x9d,0x5f,0x73,0x78,0xbd,0xaa, - 0x9b,0xff,0x1a,0xa9,0x70,0x57,0xcb,0xa6,0xf2,0x7d,0x08,0x7f,0x18,0xc8,0x7f,0x9d, - 0x74,0x6c,0x91,0x3a,0xed,0x17,0xa5,0x7d,0x2d,0xf6,0x40,0x93,0xf1,0xcf,0xb8,0x50, - 0x9f,0x4b,0x27,0x35,0xe9,0x4e,0xb3,0x76,0x6d,0x09,0xc6,0xff,0x04,0xfc,0x01,0x86, - 0xdd,0xe8,0x55,0x98,0xda,0x40,0x32,0x18,0xff,0x29,0xb6,0x1e,0x0c,0x67,0xfd,0xb4, - 0x55,0x0c,0xcc,0x99,0xb0,0x81,0x62,0xe3,0x18,0x49,0xc4,0xe8,0x81,0xf8,0xf8,0xfc, - 0x01,0x9a,0x4c,0x8f,0xfd,0xcb,0x17,0xe5,0x0f,0xd0,0xd8,0x26,0xa5,0xd5,0x34,0xff, - 0xf7,0x4b,0xfe,0x00,0x0e,0xff,0x83,0x2d,0x1b,0xac,0x3e,0xce,0xc9,0x7f,0x59,0xde, - 0x31,0x6d,0xa2,0x7c,0x45,0xc0,0x1f,0xc9,0xeb,0x8e,0xf1,0x60,0x1b,0x5a,0x2f,0xc6, - 0xfd,0x01,0x1e,0x20,0xf5,0x71,0x5a,0xa3,0x55,0xee,0xa2,0x9d,0xf1,0xca,0x3f,0x8b, - 0xf6,0x47,0xe2,0xf9,0xaf,0x09,0x87,0x08,0x72,0x07,0x32,0xfe,0xf1,0xfb,0x03,0xb4, - 0x7b,0xcb,0xb2,0x0d,0x5d,0x9f,0xa7,0x43,0xfc,0x21,0xd5,0x3a,0xb3,0x28,0x7f,0xec, - 0x9a,0x8c,0x16,0x89,0x7f,0xfc,0xfe,0x00,0xac,0xcc,0x27,0x8d,0xfb,0x4d,0xc9,0xfe, - 0x00,0xe7,0xc9,0xb6,0xe0,0xa2,0x9d,0x4c,0x21,0xfc,0xe3,0xe6,0xbf,0xea,0x0a,0xe0, - 0x1f,0xb6,0xfe,0x49,0xfe,0xab,0x77,0x50,0xea,0x76,0x5a,0xd8,0x1f,0x20,0x69,0xa2, - 0x32,0xef,0x50,0x7f,0x80,0x42,0xd7,0xfb,0xeb,0xe3,0x8c,0x56,0xaf,0x3b,0x86,0xeb, - 0x17,0x54,0xc0,0x1f,0x80,0xc8,0xc2,0x57,0x47,0xcc,0xf7,0xac,0xec,0x0f,0xa0,0xb2, - 0x6e,0x20,0xcd,0xe8,0x7c,0x57,0xcb,0xfe,0x00,0x57,0xa0,0xf9,0x60,0x42,0xee,0xaf, - 0xaa,0xfb,0xfc,0x04,0x02,0xfe,0x48,0xbe,0xb2,0x38,0xab,0x80,0x3f,0x40,0x8b,0xe6, - 0xd2,0x3e,0x77,0x3b,0xd3,0x34,0x0a,0xf9,0x23,0x79,0xf1,0x5c,0x53,0xc8,0x1f,0xc9, - 0xed,0x8f,0x96,0xf6,0xee,0x7f,0x16,0x5a,0x1f,0xc7,0xf5,0xc9,0x0e,0xff,0xd3,0xe2, - 0xfd,0xb7,0x0d,0x8b,0x4f,0x35,0xe7,0x1f,0x52,0x2e,0xdf,0xe8,0x45,0x3b,0xc6,0x84, - 0xfa,0x21,0xf9,0x2f,0xc2,0xff,0x74,0xd6,0x71,0xb4,0x53,0xe2,0x0c,0x96,0xf9,0xfc, - 0x01,0xbc,0x0f,0xd5,0x87,0xf7,0x92,0x87,0xc2,0x94,0x1e,0x13,0x99,0x7f,0xe6,0xf8, - 0xc7,0xf0,0xfb,0x03,0xdc,0x40,0x07,0x1d,0x33,0xc2,0xf2,0x5f,0xcc,0x1f,0x40,0xa1, - 0xb0,0x67,0x9c,0xc2,0x9e,0x6b,0xd6,0xec,0xc2,0xf5,0x71,0x74,0xf7,0x78,0xd3,0xe1, - 0x43,0x2c,0xf2,0x97,0xd5,0xe1,0xf9,0x2f,0xd2,0x0d,0xe4,0xaa,0x69,0x0f,0x4e,0x27, - 0x5e,0x89,0xfb,0x3a,0xc6,0xda,0x83,0x51,0xbf,0x3f,0xd2,0x70,0x6a,0x53,0xfc,0x67, - 0x16,0x69,0x14,0xa2,0xb9,0xb4,0x4f,0x3e,0xd2,0x1f,0x89,0x97,0xc5,0x79,0x83,0x9c, - 0x78,0x3d,0xe7,0x7f,0xee,0x9b,0x4b,0x64,0xcf,0x14,0x46,0x4a,0x78,0x52,0xde,0x7f, - 0x02,0xfd,0xd1,0xbe,0xed,0x6e,0x9b,0xcd,0xd9,0xb4,0xc3,0xff,0xf8,0xf2,0x5f,0x01, - 0x7f,0xa4,0x3a,0x21,0xfb,0x23,0xef,0xb7,0x43,0x54,0x31,0x2e,0xf9,0x03,0x18,0x2b, - 0x37,0x39,0xb0,0x27,0xac,0xde,0x39,0x2f,0xfa,0x23,0xa9,0x34,0xbf,0x33,0x50,0x45, - 0xcf,0x5f,0xfc,0xfc,0x1a,0xf3,0xf3,0x3f,0x10,0x79,0xde,0x21,0xf5,0x71,0x4e,0x58, - 0x54,0x1e,0x16,0xa9,0x90,0x59,0xa8,0x8f,0xd3,0x6c,0xfc,0xa3,0x34,0xd2,0xb2,0x2c, - 0xeb,0x32,0xac,0x1c,0xad,0x7c,0x19,0xc3,0x7b,0xec,0xfd,0x5d,0xf0,0x07,0x98,0x20, - 0xfe,0xc6,0x47,0x2a,0x2f,0x54,0x4f,0x7b,0x07,0x59,0xb4,0x3f,0x00,0xf3,0x97,0x38, - 0x5b,0x18,0xff,0x70,0xb4,0xb3,0xae,0x68,0x7f,0xc8,0x88,0x41,0xb4,0x3f,0x52,0xa4, - 0x3f,0x00,0xea,0x8f,0xe4,0x1f,0xe4,0xc2,0xfc,0x91,0x42,0x06,0x85,0xfc,0x91,0x22, - 0xf1,0x4f,0x11,0xf7,0x5f,0xc8,0x1f,0xdb,0x3f,0x98,0x0c,0xf7,0xc7,0xa6,0xfd,0x52, - 0x23,0xfd,0x21,0x35,0x11,0xed,0x50,0x7f,0x6c,0x2b,0xc8,0xff,0x78,0xe1,0x94,0xfd, - 0x91,0x14,0x5a,0x0d,0x57,0xac,0x3f,0xa4,0x97,0xa8,0x45,0xde,0x5f,0x22,0xfd,0x91, - 0xa2,0xf0,0xcf,0x10,0xe2,0x8f,0x54,0xa4,0x3f,0x64,0xc4,0x40,0xc0,0x3f,0xff,0x8a, - 0xf5,0x87,0xfd,0x32,0xfc,0x91,0xe2,0xd4,0x48,0x70,0xd5,0x75,0xf9,0x23,0xd9,0x83, - 0x75,0x5f,0xae,0x3f,0x12,0x3e,0xe0,0xf8,0x67,0x9f,0xe8,0x8f,0xe4,0xb4,0x05,0xa9, - 0x2e,0x88,0x7f,0x0a,0xf1,0x1b,0x82,0x3f,0xd2,0x0e,0x99,0xff,0xc1,0xf1,0x12,0xda, - 0x1f,0xd6,0x45,0x3b,0xeb,0xa2,0xfd,0x21,0x61,0x46,0xc4,0x34,0x8b,0xf5,0xc7,0x2e, - 0xa2,0x3f,0x88,0xd0,0x0d,0x24,0x1a,0xff,0xc4,0x16,0x15,0x11,0x1f,0x09,0xff,0xa8, - 0x53,0x2a,0x8b,0x76,0xed,0x75,0xe8,0x7f,0x28,0xda,0x69,0x5f,0x87,0xfb,0x23,0x79, - 0x9f,0xd4,0xd6,0x62,0xf6,0x1f,0x8e,0x7f,0xfa,0x44,0xfc,0x73,0x17,0xc8,0x6d,0xe2, - 0x11,0xfc,0xb3,0x4b,0x63,0xfa,0x1f,0x8a,0x76,0x4e,0x55,0x16,0xed,0x0f,0x80,0xef, - 0xb7,0xcb,0x64,0xfc,0x23,0x9d,0x5f,0x97,0x7b,0x1b,0xf3,0xe9,0xa9,0xd8,0x81,0xc0, - 0xf9,0x25,0xe1,0x1f,0x93,0xdf,0x6d,0x26,0x3d,0xa1,0x4d,0x55,0x05,0x1c,0x9f,0x84, - 0xfe,0xb0,0xba,0xaf,0x3e,0x2e,0xa7,0x4d,0xce,0x0c,0xee,0x60,0x58,0x7f,0x58,0x96, - 0xef,0xa0,0xb6,0xd8,0x72,0xbd,0x21,0xc7,0x3f,0x9b,0x65,0xbe,0xeb,0x66,0x1b,0xff, - 0x2c,0xd9,0x1d,0xd8,0x48,0x8f,0x85,0xfb,0x63,0x6f,0x08,0x04,0x6a,0xbb,0xc8,0xff, - 0x64,0xfd,0xfe,0x48,0x05,0xf0,0xcf,0x56,0xd4,0x1f,0x3b,0x0a,0xff,0x14,0x71,0xde, - 0x55,0xf9,0xf5,0x3f,0x4e,0x7c,0xb4,0xbd,0x5a,0xfa,0x8d,0xb2,0xa5,0x1d,0x08,0x1e, - 0x60,0xeb,0xd3,0x12,0xeb,0xe3,0x2e,0x1b,0x4d,0x27,0xb7,0xbf,0xe4,0x18,0x25,0x15, - 0xc6,0x3f,0x74,0x30,0x61,0xe3,0x99,0xe9,0xcc,0x35,0xb7,0xd1,0x27,0x86,0x7f,0xa6, - 0x33,0xc7,0x8d,0x66,0x6e,0x8b,0x94,0x18,0xa7,0x42,0xe8,0xbd,0x63,0x21,0xfa,0x9f, - 0x1d,0xff,0x03,0x65,0xa3,0xb5,0xdc,0x16,0xbb,0x74,0x97,0x3d,0x78,0x45,0x4b,0x66, - 0x05,0xfc,0xd3,0xc2,0xf3,0x5f,0x47,0xa0,0x93,0xca,0x7e,0x5c,0x3c,0x6c,0xbf,0x98, - 0x93,0x46,0xa8,0xfb,0x0d,0xd9,0xb8,0x46,0xd0,0xff,0xa8,0x69,0xe2,0xa6,0x98,0xd7, - 0x06,0x3d,0x1a,0x2d,0x43,0x07,0xfd,0x21,0xf9,0xaf,0xbf,0x9a,0xf7,0x77,0xd6,0x51, - 0x73,0xc1,0x79,0x27,0xed,0xa2,0x34,0x65,0x13,0xa4,0x91,0xeb,0xe5,0x4c,0x58,0x7f, - 0x90,0x4c,0x6c,0x17,0x85,0xc1,0x1b,0xa6,0x68,0x34,0xea,0xb2,0x95,0x79,0x7b,0x70, - 0x65,0x97,0x4f,0x1f,0xc5,0xbe,0x7f,0x54,0x6f,0x87,0xc3,0xd0,0x70,0x3a,0xe1,0xc6, - 0x3f,0x5b,0x99,0xb1,0x5f,0x43,0x8e,0xa8,0x4d,0x59,0xd1,0x88,0x49,0xd0,0x3f,0xdb, - 0xfb,0x4f,0x4f,0xac,0x61,0xd4,0xc1,0xc3,0xa6,0x7d,0xb7,0xbb,0xed,0xc1,0x5b,0x39, - 0x39,0x91,0x27,0xf0,0x3f,0xb0,0x1e,0x3a,0xec,0x20,0xdc,0xed,0x44,0xe3,0xd6,0x6c, - 0x59,0xca,0x1e,0x74,0xf8,0x5e,0x1c,0xce,0xf3,0xfe,0xb0,0xfa,0x77,0xa1,0xa3,0xe3, - 0x85,0xb1,0xc7,0xd8,0xe9,0xbf,0x51,0xb9,0x0a,0x3f,0xf5,0x11,0x23,0x62,0xfe,0x6b, - 0x0d,0x95,0x3d,0x97,0x32,0xb4,0x63,0x6c,0x99,0x80,0x83,0x24,0xa3,0x2a,0xf1,0x3f, - 0x72,0xfe,0xeb,0xce,0x43,0x2e,0x3f,0xd6,0x44,0xe2,0x33,0x11,0xc0,0xcf,0x3c,0xff, - 0x45,0xf4,0x3f,0x97,0xa4,0x6e,0xb0,0x24,0xfe,0x97,0xc0,0xd7,0x1f,0x96,0xf9,0x3f, - 0x8c,0xcc,0x7f,0xd6,0xb1,0x05,0x68,0x75,0x77,0x8f,0x8a,0x36,0x3a,0xa8,0x96,0x88, - 0xf4,0xf3,0x8c,0x7f,0x36,0xcc,0x9f,0xe8,0x7b,0xac,0xdb,0xf2,0x8b,0xd9,0xec,0x1e, - 0xa0,0xc6,0x08,0xb2,0x51,0xb6,0xa8,0xff,0x79,0xdc,0x0e,0xda,0xce,0xbc,0xe6,0x95, - 0xe5,0x96,0x92,0xf5,0xf6,0x2b,0xab,0x5f,0x8a,0xa7,0xd8,0x1f,0x76,0x0a,0xae,0xc2, - 0x5d,0x99,0x9a,0x54,0x3c,0xe7,0xa0,0x9d,0x3c,0x6d,0x14,0x9b,0xb4,0x42,0xfa,0xc3, - 0xd2,0xfc,0xd7,0x8a,0x45,0x4f,0xb4,0xcb,0xc7,0x90,0xbf,0x3f,0x08,0x8b,0x8f,0xbe, - 0x33,0x79,0xd8,0x49,0x7b,0x2d,0x22,0x0b,0xc9,0x4c,0x3c,0x1b,0x77,0x14,0x2f,0x42, - 0xa2,0x64,0x96,0x98,0xff,0x5a,0x03,0xdd,0xab,0xd2,0x84,0x7f,0x58,0x04,0x6f,0xc0, - 0x52,0x8f,0x88,0x18,0x94,0x18,0x1e,0x8e,0x7f,0x48,0xfe,0xab,0xa7,0xb4,0xd6,0xb9, - 0x9e,0xf4,0xf3,0x72,0xf2,0x65,0x66,0xbf,0x89,0xf7,0x87,0x25,0xfa,0x9f,0x76,0xf8, - 0x9e,0x39,0x5f,0x2f,0x55,0xe1,0x49,0xb8,0xd5,0x74,0x88,0x20,0x33,0x13,0xd2,0x1f, - 0x76,0x73,0x79,0x9b,0x9a,0x53,0x9a,0x20,0x6d,0x29,0x86,0xe8,0xcf,0xfc,0x90,0x68, - 0x14,0xa0,0x08,0xf9,0xaf,0xd9,0x9f,0xc0,0x95,0x55,0x2b,0xbd,0xee,0x1e,0x2e,0x9e, - 0xf9,0xcc,0x8f,0x67,0x78,0xfe,0x6b,0xde,0x98,0x71,0x11,0xea,0xcd,0x84,0x4e,0xe3, - 0xb3,0xd4,0x09,0xcb,0x27,0x3e,0xa3,0x24,0xc9,0x1f,0x52,0x5f,0x6e,0x26,0xa1,0xcb, - 0x52,0xda,0x60,0x17,0x31,0x0a,0xc8,0x52,0xfe,0xc7,0x30,0x44,0x46,0xe8,0x18,0xdb, - 0x7f,0x48,0xfe,0xeb,0x97,0xd9,0x6a,0xf3,0xcf,0x5b,0x95,0x6f,0xc3,0x56,0xa8,0x31, - 0x4b,0x5a,0xc9,0x34,0x53,0x86,0x3d,0x71,0x03,0xd3,0xff,0xcc,0xdd,0x09,0xff,0xa1, - 0x3e,0xd7,0x52,0x32,0xaa,0xfc,0x13,0xfc,0x02,0xea,0xcc,0xd2,0x51,0x12,0x46,0xc3, - 0x20,0xf1,0xbc,0x8f,0xe3,0x49,0xef,0xfa,0x0c,0xc1,0x6f,0xab,0xea,0x5b,0x6b,0xf4, - 0x32,0xd5,0xbe,0xff,0x65,0xa6,0xe3,0x8f,0x64,0xca,0x8c,0x1f,0xe7,0xdb,0x73,0xb3, - 0x9f,0x37,0xcf,0x3d,0xdd,0xb4,0xb6,0xe2,0xc9,0x08,0x7d,0x94,0xd0,0x1f,0x56,0xd3, - 0x33,0xb1,0x29,0xe5,0x21,0x3d,0x61,0x95,0x19,0x30,0xa5,0x37,0xd9,0x07,0xe9,0x6a, - 0x43,0x9f,0x32,0x06,0xed,0x5f,0x24,0xce,0x52,0x63,0x62,0x7f,0xd8,0x5d,0xd4,0x56, - 0x45,0xcb,0xb4,0x10,0x20,0xb4,0xa8,0xa3,0x3c,0x13,0x7f,0x00,0x0e,0xac,0x4f,0x86, - 0xf5,0x87,0xfd,0x5f,0xf6,0xae,0x3e,0x36,0xae,0xea,0xca,0x9f,0x3b,0x73,0x9f,0xf3, - 0xec,0x8c,0x9d,0x37,0xf6,0x4c,0x18,0xc0,0x89,0x9e,0xed,0x10,0x4c,0x30,0x66,0x92, - 0x90,0x90,0x26,0x10,0x3f,0x8f,0x3f,0x70,0x42,0x80,0x69,0x3e,0xbd,0x95,0x57,0x7a, - 0x64,0xbd,0xbb,0x41,0x62,0x91,0x93,0x4a,0x4b,0x76,0xa9,0xda,0x3b,0x66,0x48,0x4d, - 0x48,0xc5,0x28,0x44,0x10,0xb4,0xd1,0xd6,0xd0,0xb4,0x65,0x51,0xda,0x0d,0x9f,0x81, - 0xa6,0x4b,0xc6,0x51,0x1c,0x4c,0x1b,0xba,0x11,0x9b,0x56,0xd1,0x2a,0x02,0x47,0xf2, - 0x4a,0xd9,0x12,0x08,0x6c,0x61,0x9b,0x90,0x26,0xd9,0x7b,0xdf,0xe7,0xbd,0xef,0x63, - 0x3c,0x66,0xcb,0x2e,0x95,0x98,0xbf,0x7e,0xba,0x73,0xfd,0x7c,0xdf,0x9d,0xfb,0xce, - 0xfd,0xbd,0xdf,0x39,0xf7,0x1c,0xbc,0x0a,0xb3,0x30,0x95,0x79,0x76,0xf5,0x0a,0x6a, - 0x9f,0x63,0xd4,0x70,0xa9,0x6e,0x62,0xf9,0x6b,0x05,0xff,0x57,0xb6,0x17,0x0e,0x68, - 0x4d,0x60,0xd4,0x4b,0x7d,0x95,0x3e,0xad,0x95,0x9b,0x22,0x7d,0xf0,0x2f,0xd0,0x70, - 0x5c,0x1e,0x00,0xf3,0xf9,0xbd,0xd3,0xe3,0xff,0x82,0x17,0xc9,0x33,0xe3,0xad,0x5b, - 0xa3,0x4c,0x08,0x9a,0x35,0x1e,0xeb,0x31,0xc0,0xfc,0xf1,0x16,0xcb,0x23,0x66,0xfa, - 0xbf,0xec,0xf1,0x57,0xb1,0xf3,0x08,0xa8,0x15,0xaa,0x59,0xf4,0xe0,0x67,0x8c,0xed, - 0x40,0xd4,0xa8,0x7f,0x71,0x5c,0xf0,0x7f,0xb9,0xf5,0x61,0xf3,0x6f,0xb0,0x30,0xce, - 0x89,0x7a,0xa6,0xff,0x5c,0x22,0x6d,0xfa,0xe3,0x67,0x0c,0x21,0x68,0xe1,0x40,0x8c, - 0xcf,0x0f,0xc9,0xf9,0xbf,0x76,0xb3,0x65,0x10,0x1b,0x62,0xd1,0x3b,0x2f,0x43,0x75, - 0x0f,0x0b,0xec,0x61,0xf5,0x3e,0x3a,0xe5,0x87,0x02,0xfd,0x5f,0x94,0xff,0xec,0xa5, - 0xdb,0xc4,0x0d,0x03,0x3b,0x59,0xb7,0x9b,0xb4,0x7f,0xe8,0x89,0x9c,0x52,0x0e,0x40, - 0x83,0x2e,0x73,0x89,0x6d,0x79,0xff,0xd7,0x76,0xca,0x51,0x5a,0xd4,0x4a,0x66,0x7f, - 0xf6,0xb3,0xd5,0x05,0x14,0xbc,0xa0,0x34,0x0a,0x89,0xc7,0x5d,0x7b,0xb5,0x2f,0xf9, - 0x21,0x79,0x9f,0x2c,0x3f,0x5f,0x3d,0x44,0x9f,0xa6,0xdf,0x31,0x6b,0x63,0xdc,0x66, - 0x96,0x25,0x4a,0x0a,0xf6,0x7f,0x0d,0xc1,0x45,0xb2,0x5c,0x36,0xca,0x52,0x53,0xeb, - 0x54,0x98,0xf1,0xb2,0x39,0x3f,0xda,0x0c,0x2b,0x5f,0xcd,0x88,0xc7,0xff,0xb5,0x0f, - 0xde,0x65,0xb2,0x52,0x11,0xfd,0x17,0xb9,0x02,0x0b,0x09,0x7d,0x30,0xa9,0x19,0x7f, - 0xb6,0xad,0x33,0xb8,0x3e,0xec,0x33,0x78,0x13,0x6c,0x87,0x16,0x90,0xf3,0xb5,0xa7, - 0xd5,0x9f,0xc1,0xe2,0xdd,0xd3,0x9f,0xa4,0xdb,0xd6,0x6b,0xe3,0xad,0x5a,0xf5,0x7e, - 0x08,0xf1,0x7f,0x3d,0x8d,0xe8,0xee,0xb6,0x8d,0x3e,0x7d,0xaf,0x43,0x23,0x58,0x89, - 0x02,0x5a,0xed,0xc0,0x21,0x8b,0xff,0xd8,0xeb,0x41,0x4e,0xc8,0xd4,0xfe,0xb4,0xc2, - 0x12,0xba,0xd5,0xb1,0xfa,0xb9,0xe0,0x14,0xa6,0xb9,0x2f,0xd8,0xff,0x55,0x7d,0xbf, - 0x7c,0x12,0xd1,0xdd,0x96,0xdd,0xef,0xeb,0x4c,0xf6,0x2c,0x18,0xf7,0x7b,0x7b,0xb1, - 0x66,0xff,0xc3,0xae,0x7f,0xc7,0xb1,0x3f,0xcf,0xc6,0xcf,0xc3,0x1f,0xe0,0x76,0x98, - 0x51,0xa4,0xa4,0xe5,0x0f,0xd0,0x06,0xc6,0xfd,0x3e,0x48,0x6f,0x93,0xbf,0xdf,0x33, - 0x73,0xfc,0xfa,0xcf,0x34,0x46,0x7b,0x8c,0x42,0xc3,0x1f,0xc2,0xfb,0xe5,0xe9,0x3f, - 0xaf,0xdb,0x85,0xd2,0x1e,0xdb,0x56,0x96,0xfe,0xf3,0x82,0x19,0x98,0x71,0xd6,0x97, - 0x1f,0xa9,0xa4,0xfe,0x53,0x71,0x56,0x29,0x27,0x3f,0x36,0xfd,0xf6,0x02,0x31,0x8f, - 0x1d,0x29,0x66,0xc4,0x0e,0x0a,0xe0,0x3f,0x82,0xfe,0x73,0xa9,0x30,0x15,0xfd,0x67, - 0x1f,0xab,0xe7,0xf8,0x85,0xea,0x3f,0x2f,0x80,0x75,0x70,0x69,0x52,0xff,0x97,0xa9, - 0x7e,0xbc,0x42,0xcc,0xfa,0x68,0xe4,0xc0,0x70,0x09,0xfd,0xc7,0xf5,0x76,0x7d,0x0c, - 0xb7,0x8d,0x98,0xfa,0xcf,0x70,0x19,0xfe,0x2f,0x3a,0x3f,0x8a,0x49,0x7b,0xb4,0x8b, - 0x4a,0x59,0xfa,0x4f,0xe8,0xfc,0x84,0xe8,0x3f,0xaf,0x4c,0xae,0xff,0x08,0xf9,0xb1, - 0x5f,0x99,0xa2,0xfe,0xf3,0x42,0x19,0xfa,0x8f,0x71,0xfe,0xab,0xf5,0xf3,0xe9,0x3f, - 0xaf,0x85,0xbd,0x8f,0x97,0xa8,0x8f,0x76,0xcf,0xa4,0xfa,0x0f,0x9e,0x5c,0x7f,0xf8, - 0xbf,0xd3,0x7f,0x4c,0xff,0x57,0xf0,0x31,0x37,0x17,0x84,0xd4,0x47,0xbb,0x34,0xb9, - 0xfe,0xe3,0x89,0xff,0x99,0x1d,0xdc,0x3f,0xa8,0x3e,0x48,0x80,0xec,0x33,0x49,0x7e, - 0xec,0x2f,0x5e,0xff,0x21,0xa1,0xfa,0x8f,0xa3,0x3f,0x08,0xe7,0xbf,0xb4,0x50,0xfd, - 0xc7,0xbe,0xbe,0x90,0x1f,0x9b,0x45,0x5b,0x3d,0xce,0x02,0xd1,0xa7,0x90,0x1f,0xfb, - 0xce,0xe1,0x6b,0xfc,0x19,0xb3,0x03,0xf3,0x63,0x3b,0x4f,0x47,0xcc,0xd7,0x52,0x2a, - 0x3f,0xf6,0xf9,0x88,0x4f,0x3f,0x09,0xcb,0x8f,0x6d,0x80,0xf3,0x51,0x6f,0x4b,0x78, - 0x7e,0x6c,0x14,0x62,0x4f,0x42,0xf2,0x63,0x5f,0x2c,0x2c,0x30,0x0b,0xa5,0x1d,0xf2, - 0xc5,0xff,0x78,0xfc,0x5f,0xe6,0x68,0x7f,0x3f,0xdc,0x70,0x76,0xfa,0x12,0xd3,0x8c, - 0x14,0x4b,0xfa,0xbf,0xcc,0x6f,0x59,0x19,0x38,0xca,0xee,0xfc,0xf9,0xc0,0xc3,0xf2, - 0x63,0x13,0xeb,0x3c,0x8b,0x2f,0x3f,0xb6,0xbf,0x3e,0x2c,0xbb,0xbb,0x83,0xb2,0xfd, - 0xda,0x1e,0xb1,0x76,0x34,0x3f,0xff,0x09,0xac,0x8f,0x16,0x1e,0xff,0xe3,0xcd,0x8f, - 0x6d,0xc7,0x73,0x1a,0x69,0x91,0x1c,0x53,0x3f,0x59,0x7d,0xb4,0x29,0xe4,0xc7,0xb6, - 0xc0,0x5c,0xb7,0xe5,0xda,0x90,0xfa,0x20,0x56,0x18,0xcc,0x2d,0x99,0xb7,0xd5,0x83, - 0x29,0xd3,0xdf,0x8a,0x4a,0xe7,0x47,0xba,0x28,0x2f,0x1f,0x9b,0xf1,0x6a,0xf4,0x1c, - 0xb9,0xa8,0x8a,0xf1,0xf0,0x21,0xf9,0xb1,0x7f,0xcf,0xea,0x5b,0xfd,0xdc,0x10,0x2e, - 0xc2,0xeb,0xa3,0xd1,0xc6,0xe2,0xc2,0x63,0xb1,0xe3,0x7c,0xd8,0xcf,0xa7,0x85,0xa6, - 0x23,0xb1,0x10,0xfe,0x73,0x8e,0xcd,0xc6,0x0e,0x79,0x37,0xef,0xf6,0x7a,0x0d,0x9a, - 0x4e,0x54,0x85,0xf0,0x9f,0xb7,0xe9,0x6d,0x3e,0x37,0x46,0x5f,0x33,0x8f,0xc1,0x42, - 0xfb,0xc6,0xe9,0x15,0x84,0xc2,0x28,0x02,0xff,0x51,0x58,0xbd,0x5d,0xfa,0xb6,0x25, - 0xcc,0xe7,0xb3,0x42,0x3c,0x15,0xcf,0x7f,0x58,0xb6,0xa8,0xa5,0xc5,0x96,0xd7,0x85, - 0x65,0xa0,0x2f,0x10,0x02,0x51,0xbc,0xfc,0x67,0x91,0x27,0x2c,0xea,0x72,0x61,0x79, - 0x7f,0x18,0xff,0xd9,0xcb,0x2e,0xa2,0x79,0xc2,0x5a,0xb4,0x05,0x02,0x3f,0x17,0xf8, - 0x0f,0x39,0x98,0xad,0xd1,0x9e,0x13,0xc2,0x96,0x5e,0x82,0xc6,0x6f,0x05,0xeb,0x3f, - 0x94,0xff,0xe0,0x83,0x24,0xe6,0x71,0x13,0xbf,0x08,0xe2,0xfb,0x82,0x8f,0xff,0xec, - 0x15,0xc3,0x60,0x7e,0x4e,0xe8,0xfb,0x48,0x38,0xff,0x91,0x97,0x7b,0xc3,0x9e,0x71, - 0x5a,0x6b,0x99,0x9c,0xff,0x18,0xc0,0x3c,0x8f,0xf9,0x46,0x7f,0x18,0xff,0xa1,0xf3, - 0x4f,0x96,0x16,0x2b,0x58,0x59,0x10,0x27,0x8d,0xdb,0x67,0xb0,0xe0,0x24,0x3f,0x63, - 0x22,0xff,0x39,0x64,0xa6,0xa5,0xe5,0x02,0x29,0x5f,0x05,0xf5,0x88,0x1c,0xc2,0x7f, - 0x9e,0xa4,0x37,0xd5,0xac,0x57,0x2d,0x89,0xcc,0xb6,0x8f,0x7d,0xbd,0x0b,0x87,0x86, - 0x44,0xfd,0xc7,0xcb,0x7f,0xd4,0x4e,0x79,0x49,0xc6,0x32,0xec,0xfb,0xd9,0x63,0x45, - 0x1a,0x27,0xe4,0x10,0xfe,0xb3,0x9d,0x8e,0x76,0xd9,0x70,0xcd,0xb3,0xd1,0x66,0xf8, - 0xad,0x4d,0x7b,0x2e,0xc3,0x02,0x8f,0xfe,0x63,0x8f,0x87,0xf2,0x1f,0xed,0xbc,0xe6, - 0xa7,0x01,0x6f,0x08,0x11,0x41,0x22,0xff,0x79,0xcb,0x13,0xf6,0xcc,0x3c,0x20,0x62, - 0xa2,0x6c,0x81,0xff,0xc8,0x8f,0x6e,0x6c,0xe5,0xd5,0x9b,0x68,0x3f,0xdd,0xa6,0x1b, - 0xb3,0xcd,0xa1,0xfc,0xe7,0xd1,0x48,0x8b,0xa0,0xf6,0x18,0x11,0x41,0x59,0x39,0x94, - 0xff,0xe4,0xb4,0x16,0x27,0xfe,0x87,0x7e,0x0b,0x9d,0xf0,0x35,0x4d,0x4c,0x14,0x29, - 0xf2,0x9f,0x31,0x4a,0x2a,0x5a,0x38,0xb7,0x17,0xdb,0x7f,0x5f,0x14,0x12,0x45,0xf2, - 0xfc,0xe7,0xd3,0xc8,0x05,0x68,0xcb,0xce,0x38,0xc1,0x6f,0xeb,0x9f,0x42,0x5b,0x36, - 0x8c,0xff,0x7c,0x02,0x6f,0x6b,0x6d,0xbd,0x9e,0xb0,0x61,0xed,0xf6,0xad,0x31,0x2e, - 0x51,0x00,0xcf,0x7f,0x4e,0xd3,0x3d,0xa0,0x15,0x9a,0x05,0xda,0xf3,0x33,0xd2,0xaa, - 0x36,0x87,0xf0,0x9f,0xb7,0x21,0xa7,0xb6,0x9c,0x94,0x13,0x9e,0xb4,0x90,0xd9,0x79, - 0xa1,0xfc,0xe7,0x51,0x68,0xed,0xf1,0xc7,0x53,0x55,0x85,0xf1,0x1f,0x56,0x0d,0x64, - 0x93,0x30,0x7e,0x74,0x21,0xbb,0x5c,0x6b,0x0d,0xe1,0x3f,0x79,0xf9,0x42,0xc4,0x17, - 0xf6,0x43,0x6e,0xd3,0xaa,0x4b,0xf0,0x9f,0x34,0x54,0x93,0x69,0xc2,0x7a,0x5b,0x20, - 0xc7,0x42,0xf9,0xcf,0x1b,0xea,0x0f,0x0a,0xde,0xb0,0xe7,0xb6,0xfd,0x30,0x9c,0x09, - 0xe5,0x3f,0xea,0x49,0xef,0x31,0x01,0x95,0x6e,0xa1,0xc1,0xfc,0x27,0x41,0x1f,0x3a, - 0x6f,0x5a,0xd7,0x43,0xe4,0xa6,0x8c,0x1c,0xca,0x7f,0xfe,0x9b,0xa4,0xc7,0xab,0xad, - 0xf8,0x9f,0x71,0x2b,0xfe,0xc7,0xd0,0x7f,0x02,0xf9,0xcf,0xde,0x80,0x6d,0xfd,0x0a, - 0x59,0xac,0x85,0xf3,0x9f,0xb7,0xc9,0x32,0x9d,0xee,0x56,0x82,0xdb,0x6b,0xa1,0x79, - 0x90,0xe7,0x5c,0x10,0xff,0xf9,0x2e,0x34,0x68,0xf2,0x00,0x4f,0xdb,0x0e,0xe1,0x06, - 0x21,0x10,0x51,0xe4,0x3f,0x79,0xb8,0x41,0x93,0x3d,0x65,0x8c,0xf6,0x0a,0x33,0x20, - 0xf2,0x9f,0x87,0x59,0x9a,0x5f,0x91,0x46,0x2a,0x73,0xb5,0xe6,0x10,0xfe,0xf3,0x53, - 0xf8,0x25,0x2c,0x65,0x61,0xbd,0x1c,0x11,0xba,0x02,0x8b,0x8b,0x2d,0x4c,0x01,0x7b, - 0x3f,0x80,0xff,0x68,0x17,0x1d,0x99,0xc8,0x75,0x0c,0x2d,0xcd,0x72,0x2d,0x4d,0x3c, - 0xff,0x39,0x4b,0xad,0xd9,0xed,0xc3,0x31,0xfb,0x18,0x94,0x2d,0x83,0x4c,0xf0,0x89, - 0x22,0x7d,0xfc,0x87,0xf8,0xe2,0x79,0x36,0xc9,0x21,0xfc,0xa7,0x95,0x3d,0x14,0x47, - 0x7c,0xfd,0x85,0x08,0x58,0x1f,0xff,0xe1,0xcb,0x56,0x02,0x05,0x91,0x58,0xf1,0x39, - 0x9e,0x0f,0xc4,0x9d,0xe9,0xa7,0xfc,0xe7,0x23,0xfe,0x58,0x93,0x9d,0x56,0x45,0x28, - 0x54,0xea,0xf2,0x9f,0xbd,0xb3,0xfc,0x6a,0x46,0xc0,0xf9,0xf7,0xb0,0xf8,0x9f,0x85, - 0xe3,0xd3,0x4b,0xd7,0x07,0x29,0x8a,0xf1,0x3f,0xf3,0x04,0xd9,0xc7,0xe5,0x3f,0xee, - 0xf9,0x2f,0xe9,0x98,0xfc,0x92,0x4b,0x7b,0xc4,0xb0,0xba,0xc9,0xf5,0x9f,0x79,0x21, - 0xf1,0x3f,0x8e,0x7d,0xf0,0xd4,0x47,0x5b,0x50,0x0c,0xe4,0xc3,0x61,0xe7,0xbf,0x42, - 0xf3,0xff,0x7c,0xee,0xf8,0x1f,0xf1,0xfc,0xd7,0xe4,0xfa,0xcf,0x19,0xfe,0xfd,0x8b, - 0x7b,0x4d,0x88,0x59,0x1e,0x52,0xb3,0xe5,0x63,0xd7,0xff,0x15,0x14,0xff,0xe3,0x8f, - 0x7f,0xe6,0xfc,0x5f,0x31,0xcd,0x1b,0xed,0x13,0x90,0xff,0xc7,0xf5,0x7f,0x59,0xfc, - 0x67,0x7a,0xc9,0xf5,0xe3,0xfa,0xbf,0x04,0xfd,0x27,0xb4,0x5e,0xcf,0xe1,0xd2,0xf1, - 0x3f,0xb2,0xe5,0x76,0x0f,0x38,0xff,0x45,0x78,0xfd,0xe7,0xc7,0x61,0xf7,0x1b,0x58, - 0x1f,0xa4,0x04,0xe0,0xfc,0x5f,0x71,0x2e,0xfe,0xe7,0xb7,0x61,0x42,0x10,0xe7,0xff, - 0x2a,0x33,0xfe,0xc7,0x1e,0xbf,0xa9,0xff,0x2c,0xb5,0xdf,0xee,0x97,0x06,0xbf,0xef, - 0xfb,0xcf,0x7f,0xd5,0x4c,0x49,0xff,0x99,0x17,0xbc,0x4d,0x4f,0x58,0xa5,0xbe,0x2a, - 0x7e,0xe5,0xd3,0x7f,0xaa,0x78,0x19,0xc4,0x97,0x2f,0xda,0xf5,0x7f,0x99,0xfa,0xcf, - 0x52,0xf7,0xee,0x6a,0xca,0xd3,0x7f,0x82,0x8e,0x7d,0x05,0xfa,0xbf,0xa4,0x12,0xdd, - 0xa6,0xae,0xff,0x9c,0x31,0xc0,0x46,0xce,0xff,0x55,0x8e,0xfe,0xb3,0x91,0xcb,0x8f, - 0x5d,0x9e,0xfe,0xe3,0xfa,0xbf,0xca,0x8c,0xff,0xb1,0xc7,0x3f,0x49,0xfe,0x9f,0xff, - 0xf4,0xfa,0xbf,0x9a,0x3d,0xf9,0xb1,0xa1,0x2a,0xf0,0xfc,0x57,0xb8,0xfe,0xe3,0x07, - 0x8f,0x95,0xd4,0x7f,0x02,0xcf,0xe3,0x94,0xac,0x8f,0x66,0x80,0xbf,0x11,0x5a,0x5c, - 0xff,0x97,0x4f,0xff,0xa9,0xd9,0xda,0xe4,0x12,0xa1,0x4a,0xc7,0xff,0x65,0xaf,0x37, - 0x5e,0xff,0xc1,0x66,0x34,0x4b,0x5d,0x80,0x3d,0xe1,0xe2,0x3f,0xf9,0xdd,0xaa,0xd0, - 0x36,0x5e,0x75,0x21,0x7a,0x59,0x3b,0x47,0x96,0x85,0x9d,0xff,0xba,0x7a,0x8f,0x11, - 0xb6,0x64,0x8d,0xf6,0xe6,0x33,0x55,0xac,0x50,0xd1,0xe3,0x9e,0x42,0x45,0xa2,0xff, - 0xcb,0xbd,0x4d,0x74,0xf3,0xd8,0x10,0xed,0x2f,0xff,0x73,0x89,0xf3,0x5f,0xe2,0xec, - 0x8d,0x5c,0xc3,0xc0,0xc3,0x30,0x47,0xd4,0x7f,0xdc,0xf1,0xf0,0xe7,0x67,0xd9,0x41, - 0x66,0x39,0xc8,0x90,0x86,0xe9,0x3f,0xae,0x3e,0xb6,0x34,0x4c,0xff,0x81,0x60,0x33, - 0x7e,0xb3,0xd0,0xe2,0xfa,0xbf,0x48,0x59,0xf1,0x3f,0x21,0xe7,0xbf,0xb8,0x63,0x5f, - 0x0f,0x88,0x7a,0x51,0x88,0xfe,0x83,0x9c,0xb0,0xe7,0xfb,0x8d,0x16,0xcc,0xbe,0x8a, - 0xa6,0x41,0xf0,0x7f,0x09,0xbf,0xfe,0x58,0x4d,0xd0,0xfe,0xc2,0xe9,0x3f,0xd5,0xc2, - 0x6d,0x2e,0x3f,0x12,0xbc,0xbf,0xbb,0xe7,0xbf,0x90,0x9f,0xed,0x98,0x8e,0xb0,0xe0, - 0xf3,0xef,0xbe,0xf8,0x67,0xc1,0x11,0x36,0xd5,0xf8,0x67,0x1c,0xa2,0xff,0x84,0x84, - 0x51,0x95,0x1d,0xff,0xec,0x75,0xc4,0x78,0xcf,0x7f,0x99,0xf5,0x2f,0xfc,0x0b,0x03, - 0x59,0x0a,0x61,0x89,0xf8,0xe7,0x1a,0xee,0xfa,0x2d,0xb2,0x8f,0xff,0x78,0xfc,0x5f, - 0xcb,0xf9,0xf1,0xd7,0xdd,0xef,0xe7,0x3f,0xbe,0xf8,0xe7,0x2a,0xce,0x71,0xe3,0x2c, - 0x15,0x9f,0xfe,0x73,0xfa,0x5a,0x73,0xf7,0xbf,0x81,0x73,0x0c,0x9d,0x77,0xf3,0xe1, - 0x84,0xf8,0xbf,0x7e,0x47,0xaf,0xe6,0xe6,0x3f,0xdc,0x1f,0x8d,0x95,0xab,0xff,0x88, - 0x20,0xd8,0xff,0xd5,0x51,0x62,0xfe,0x3f,0x7f,0xfc,0x73,0x50,0x7d,0x58,0xbf,0x23, - 0x2c,0xc8,0xff,0x95,0x09,0x58,0x6f,0x76,0xe2,0x85,0xd2,0xf5,0x61,0x29,0x18,0xfa, - 0x42,0xe2,0x9f,0xcb,0x38,0xff,0x35,0xec,0x8d,0x7f,0x9e,0x84,0xff,0x78,0xea,0x83, - 0xfc,0xd1,0xfd,0x5f,0x29,0x5f,0x7d,0xd8,0x32,0xce,0x7f,0xf9,0x6e,0xd3,0xeb,0x08, - 0x0b,0xaf,0x0f,0x6b,0x82,0x8f,0xf9,0x96,0x69,0x7c,0xfc,0x73,0xea,0xcb,0xe6,0xff, - 0x32,0xea,0xa9,0xf9,0x7e,0x56,0xe2,0xe5,0x3f,0xf6,0xfa,0x1c,0x02,0x9b,0xff,0x08, - 0x65,0x41,0x86,0x4b,0xf9,0xbf,0xce,0x04,0x4c,0xbb,0x70,0xfe,0xab,0xc3,0x73,0xfe, - 0x2b,0x80,0xf6,0x38,0x89,0x80,0x1e,0x30,0xf4,0x1f,0x64,0xaf,0x87,0x30,0xfe,0x63, - 0x3a,0x6e,0xb0,0x19,0xa8,0x50,0x51,0xe2,0xfc,0x97,0xa5,0xff,0x08,0xfc,0xa1,0x36, - 0xe8,0xfc,0x97,0x18,0xf6,0x3c,0xdf,0x06,0x37,0x4d,0x25,0xfe,0xd9,0x2e,0x8c,0x15, - 0x98,0xff,0x30,0x18,0xdc,0x3c,0x31,0xe3,0x82,0xff,0xfc,0x97,0x3d,0xda,0xdb,0xb9, - 0x61,0xff,0x7d,0xe3,0x64,0xfe,0x2f,0x11,0xd8,0xf9,0x7f,0xee,0x1c,0xa8,0x2d,0x11, - 0xff,0xcc,0xf4,0x67,0x78,0x89,0x88,0x86,0xc8,0x77,0xfe,0x6b,0x92,0xf7,0x6b,0xff, - 0xf9,0x2f,0x0f,0xed,0x51,0xc4,0xfe,0xff,0xe1,0xf1,0x7f,0x89,0xd1,0xbf,0xb7,0xf9, - 0xe3,0x9f,0xfb,0x4b,0xf8,0xbf,0xa2,0x7e,0x46,0xc4,0xeb,0x3f,0xfe,0x6f,0xfd,0x0a, - 0x40,0x70,0xfc,0xb3,0x3d,0x3f,0xd6,0x0a,0xe4,0xf3,0xff,0x38,0xb3,0x0f,0x95,0xf7, - 0xfb,0xa2,0xc1,0x5b,0x4c,0xc0,0xd5,0x87,0xf5,0xc4,0x3f,0x07,0xcb,0x1a,0xee,0xfe, - 0x55,0xe7,0xea,0x3f,0x23,0x93,0xac,0x9f,0x41,0xaf,0xfe,0x03,0x3f,0xb5,0x49,0xce, - 0x03,0x01,0x44,0xc8,0xc7,0x7f,0xc6,0x84,0x7c,0x08,0x38,0x84,0x08,0xb9,0xf6,0x67, - 0x3c,0xb1,0x2f,0x31,0x95,0xf3,0x5f,0x12,0x2e,0x67,0xfd,0xb8,0xfa,0xcf,0x33,0x6e, - 0xfe,0xe7,0x6f,0xf9,0xf9,0x0f,0x4b,0x84,0x38,0xf2,0xf8,0x47,0x7f,0xe1,0xf2,0x9f, - 0x71,0xd8,0x87,0x4d,0x6f,0x6c,0x99,0xfa,0x0f,0x76,0x7f,0x7d,0xb9,0x9c,0xf3,0xef, - 0xbe,0xf5,0x10,0x04,0x5c,0xfe,0x73,0x1c,0x78,0xfd,0xc7,0x0a,0xfb,0x21,0x4e,0x05, - 0x31,0x3f,0xff,0x49,0xf1,0xfc,0x87,0xdc,0x76,0x96,0x82,0x5f,0x11,0x96,0x08,0x28, - 0x24,0xfe,0xa7,0x7e,0x1f,0x3c,0x14,0x74,0x9b,0x47,0x84,0xf9,0x74,0xec,0x4f,0x73, - 0x59,0xf3,0xcf,0xf1,0x1f,0x65,0x6a,0xfc,0xc7,0x97,0xff,0x67,0xd2,0xf8,0x9f,0x1d, - 0x65,0xcc,0xe7,0x3b,0xdc,0xfa,0x7c,0x0e,0x7f,0x86,0x96,0xe7,0xca,0x8f,0xff,0x09, - 0xc8,0xff,0x23,0x97,0xe0,0x3f,0x10,0xf8,0xbe,0x8f,0xc2,0xe3,0x7f,0xca,0xe1,0x33, - 0x9c,0xfe,0xe3,0xed,0xff,0x98,0x01,0x22,0xa1,0xf9,0x9f,0x95,0x52,0xfc,0x07,0xfb, - 0xf8,0x4f,0xaf,0x5c,0x0e,0xff,0xe1,0xf4,0x9f,0x64,0x20,0xcd,0xab,0x08,0xe5,0x3f, - 0xd5,0x9e,0xfe,0xa6,0x1b,0x08,0x3b,0x2d,0xad,0xa2,0xfe,0x63,0xe5,0x3f,0x14,0x69, - 0x8f,0x1c,0xce,0x7f,0x74,0xc8,0x4f,0x89,0xff,0xbc,0x86,0x83,0xf9,0x4f,0x4d,0x08, - 0xff,0x11,0xea,0xc3,0xba,0x20,0x12,0xa6,0xff,0x8c,0xc1,0x5e,0xec,0xeb,0xaf,0x78, - 0x81,0xcb,0x7f,0xe4,0xa0,0xf5,0x56,0xaa,0x3e,0x6c,0x62,0x52,0xfd,0x47,0xf0,0x7f, - 0xf9,0xf7,0xa3,0xd2,0xfa,0x0f,0x02,0x9e,0xff,0x44,0x42,0x9e,0x5f,0xd7,0xff,0x25, - 0x93,0x60,0xfe,0x23,0x80,0x0e,0xd7,0xff,0xc5,0xe5,0x43,0x0e,0xb7,0x27,0x0b,0x39, - 0xfe,0x13,0x7b,0x43,0xe3,0xf4,0x9f,0x65,0xa7,0xcd,0x40,0xa0,0xd0,0xf8,0x9f,0xe7, - 0x61,0x8f,0x9b,0x6d,0xec,0x20,0x51,0x59,0x3c,0x0f,0xbd,0xcd,0x61,0x7e,0xfc,0x9b, - 0x39,0xfe,0x33,0x0c,0x4e,0x7d,0x58,0x4a,0xf3,0x54,0x3b,0xdf,0xa3,0x1a,0xa6,0xff, - 0x68,0x62,0xfe,0x1f,0x27,0x9f,0x36,0x37,0x9f,0x8f,0xf1,0xfe,0x2f,0x59,0xb0,0x9f, - 0x88,0xf1,0x99,0x88,0x78,0xbf,0x23,0x1e,0xfd,0xc7,0xed,0x6f,0xb1,0xc1,0xa6,0x92, - 0xf1,0x3f,0x7c,0xbd,0x03,0xe3,0x3c,0xaf,0x08,0xbc,0xfe,0xaf,0x91,0x84,0xc8,0x5e, - 0x46,0x78,0xd9,0xe1,0xac,0x52,0x9a,0xff,0x2c,0xf3,0x6e,0x7c,0xb2,0x5f,0xff,0x01, - 0x7e,0xbd,0xa9,0x3e,0x10,0xf1,0xc4,0xff,0x44,0x80,0xd7,0x7f,0x8a,0x46,0x18,0xfc, - 0x07,0xda,0xc5,0xe3,0xac,0xc5,0x8d,0xef,0x75,0xf5,0x9f,0x41,0x3e,0xff,0xcf,0xc5, - 0x25,0x6d,0xbf,0xa0,0xe0,0x72,0xfe,0xca,0xae,0x50,0xff,0x97,0xa5,0x1f,0xfe,0xeb, - 0xf9,0x8e,0x00,0xfe,0xa3,0xf8,0xe3,0x7f,0x52,0x1f,0x2a,0xd6,0x21,0x2f,0x1b,0x04, - 0xf0,0x9f,0xf3,0x62,0x7d,0x58,0xa9,0x79,0xe4,0x4e,0x3b,0xcc,0xdb,0xb3,0x1e,0x4c, - 0x46,0xc4,0x9d,0xff,0x92,0xf6,0x29,0x07,0x31,0x9b,0xf6,0xb9,0x25,0xf8,0xcf,0x79, - 0x6e,0x7f,0xdc,0x67,0xc8,0x80,0xf7,0xec,0xaf,0x33,0xf5,0x52,0x6e,0x19,0xd4,0x39, - 0x89,0x80,0x46,0x9c,0xf1,0x9f,0x2e,0x84,0x9f,0x7f,0xcf,0x70,0xfa,0x98,0x7d,0x7d, - 0x53,0xff,0x31,0x69,0xb6,0x9b,0x56,0xe8,0x60,0x28,0xff,0xf9,0x05,0x66,0xf9,0x7f, - 0x96,0x16,0x8d,0xb4,0xe1,0x9e,0x61,0x67,0xce,0x62,0x5f,0xfe,0xc3,0x71,0x64,0xbf, - 0x7f,0xad,0xf6,0x97,0x65,0x74,0xc0,0x47,0xce,0xdd,0xea,0x68,0x76,0xdc,0xda,0xf4, - 0xff,0x11,0x85,0xf2,0x01,0xbe,0x3e,0xac,0xc5,0x7f,0xe6,0x77,0xb8,0x6e,0x2f,0x9f, - 0x47,0x8c,0xab,0x0f,0xcb,0xf4,0x1f,0xf4,0x50,0x91,0x4f,0xfb,0x73,0xd6,0x97,0x1f, - 0xdb,0xad,0x0f,0x6b,0xe8,0x3f,0x78,0x32,0xfe,0x13,0xec,0xff,0x52,0xc2,0xf9,0x8f, - 0xab,0xbf,0x59,0xfc,0xe7,0xce,0xad,0x99,0x12,0xfc,0xa7,0xe8,0xd3,0x7f,0xae,0x2d, - 0xa9,0xff,0xf8,0xeb,0x5f,0x4c,0xc2,0x7f,0x82,0xea,0x5f,0x94,0xd2,0x7f,0xb8,0xfc, - 0xcf,0xe5,0xe9,0x3f,0x76,0x7f,0xdf,0xf9,0xf7,0x49,0xf2,0x3f,0xfb,0xf8,0xcf,0x1f, - 0x43,0xff,0x69,0xe4,0xce,0xbf,0xcb,0xfe,0x68,0xdb,0x92,0xf5,0x61,0xcb,0x3a,0xff, - 0xee,0xe6,0x7f,0x0e,0xe6,0x4b,0x6f,0x19,0x81,0xe2,0x1d,0x6e,0x7f,0xd7,0xff,0x15, - 0xc4,0x7f,0x8c,0x83,0x60,0xc1,0xf9,0x9f,0x21,0xe9,0xbf,0xcd,0x09,0x76,0x22,0x55, - 0x68,0xe1,0xfc,0x5f,0xc8,0xe5,0x3f,0x6e,0x20,0xfa,0x3f,0x85,0xe7,0x3f,0xcc,0x07, - 0xf1,0x1f,0x6f,0xa2,0x6f,0xb7,0x5e,0xe7,0xf3,0xc1,0xfa,0x8f,0x87,0x2f,0xb9,0xf9, - 0x9f,0xe7,0xf1,0xfc,0x87,0x1d,0xc4,0x9b,0xec,0xfc,0x3b,0xaf,0xff,0xfc,0x7b,0x18, - 0xff,0x71,0xdf,0xaf,0x9b,0x93,0x9c,0xfe,0x63,0x95,0x89,0xf1,0x9f,0xbf,0xe0,0xea, - 0x5f,0xb8,0xfa,0xcf,0x65,0x78,0x2a,0xe4,0xf9,0x6d,0xe4,0xf4,0x1f,0x98,0x6d,0x1f, - 0x7b,0xbf,0x0c,0x6f,0x86,0x11,0x21,0xae,0xfe,0x85,0xa8,0x87,0x78,0xf2,0x69,0xd8, - 0x16,0x78,0x0a,0xfa,0x8f,0x01,0xb8,0xfa,0xb0,0xc8,0xcc,0xff,0xe3,0x8c,0x76,0x86, - 0x0d,0x2a,0xdd,0xf1,0x47,0x9f,0x77,0xd6,0xc3,0xce,0xb2,0xde,0xd7,0x3c,0xf5,0x2f, - 0x22,0xd6,0xec,0x3d,0xc1,0x4f,0x23,0x1f,0x61,0x55,0x70,0xea,0x5f,0xa8,0x1e,0xfd, - 0x67,0x24,0xd0,0x7e,0xba,0xfa,0x4f,0xde,0x1b,0xff,0xec,0xf8,0x83,0xa6,0x0b,0x7f, - 0x68,0x5f,0x3f,0x67,0xc5,0x3f,0x3f,0x1e,0xb0,0xdf,0x35,0x05,0x9c,0x7f,0x1f,0x61, - 0xfa,0x0f,0xe2,0xb6,0xad,0x1a,0xcf,0xfe,0x6b,0x64,0x04,0x3a,0xdd,0x6e,0xff,0x5e, - 0x04,0xfb,0xd5,0x1e,0x07,0xec,0xf3,0xeb,0x3f,0x31,0x81,0xff,0xe0,0x20,0x7f,0xeb, - 0xb5,0xc2,0xf9,0x77,0xb8,0x5f,0x3e,0x68,0xb8,0x41,0x03,0xa6,0x65,0x9f,0xbd,0x11, - 0xbb,0xf5,0x61,0xf7,0x32,0xfe,0x83,0x66,0x4c,0x16,0xff,0xd3,0x3d,0xe0,0xfc,0x07, - 0xa1,0xfa,0xde,0xb1,0xe6,0x85,0x55,0x5f,0xa6,0x7a,0x88,0xc7,0xa6,0x50,0x0f,0x51, - 0xb6,0x40,0x6c,0xec,0xab,0x7a,0x88,0x9f,0x7f,0xfe,0x43,0xea,0x21,0x82,0xdb,0xa2, - 0x4d,0xa9,0x1e,0xe2,0xb1,0xa9,0xd5,0x43,0xcc,0x4d,0x71,0xfe,0x1b,0xbe,0xaa,0x87, - 0x38,0xc5,0xcf,0x97,0xab,0xfe,0xe0,0x97,0xaf,0xff,0x97,0xec,0x79,0x9c,0xf2,0xf5, - 0x65,0x12,0x51,0x8f,0x0d,0x41,0xa3,0x01,0xc0,0xa8,0x3b,0xe4,0x82,0x3f,0x61,0x7b, - 0xf8,0xcd,0xff,0x47,0x7b,0xc8,0xac,0x5f,0x90,0x61,0x34,0x76,0xa8,0xaf,0xea,0xc3, - 0x4e,0xfa,0xf9,0xca,0x1e,0xfe,0xc9,0xf6,0x1f,0x6d,0x8f,0x0e,0x68,0xa7,0x94,0x5b, - 0x41,0x1a,0x31,0x01,0x96,0xbe,0x1b,0xdd,0xac,0xf5,0x29,0x57,0x25,0xaa,0x47,0xa7, - 0x51,0x90,0xbd,0x0a,0x57,0x17,0xe7,0x3b,0xfd,0xbb,0x3a,0xa5,0xcd,0xa8,0x4f,0xdb, - 0x40,0x17,0xbb,0x01,0xd6,0x29,0x89,0x23,0x66,0x4b,0x2a,0x79,0x14,0x99,0x5f,0x25, - 0x8b,0xf3,0x6d,0x3e,0x4c,0x6d,0x13,0x52,0x49,0x8f,0x5a,0x2b,0xe3,0x41,0x1f,0xd8, - 0xc6,0x80,0x4e,0x01,0x51,0x9d,0xeb,0x13,0x40,0x3a,0xf4,0xc2,0x4c,0xd8,0x45,0x2c, - 0x90,0xcc,0xa3,0x7b,0x73,0xbd,0xb0,0x5e,0x91,0x08,0xba,0x17,0xf5,0xaa,0xeb,0x41, - 0xe2,0xfa,0x77,0xf5,0x5e,0xb7,0x18,0xdd,0x45,0xd6,0xb4,0xe3,0x1d,0xd2,0x16,0xd4, - 0x57,0xdc,0xa0,0x26,0xc7,0xa4,0x6f,0xa2,0x3e,0x62,0x80,0x2d,0x39,0x03,0x70,0xe3, - 0x19,0xd5,0x34,0x55,0x91,0x71,0x04,0xd1,0xff,0xa4,0x43,0x4a,0xa9,0x00,0x64,0x00, - 0xa0,0x20,0x6f,0x03,0xe2,0xde,0xef,0x68,0x0f,0xde,0x88,0x52,0xa4,0x9b,0x5a,0x58, - 0xdc,0x88,0x64,0x92,0x01,0x65,0x08,0x37,0x50,0x8b,0x91,0x51,0x95,0x3c,0x56,0x91, - 0x0c,0x99,0xb4,0xc2,0xf7,0x5f,0x29,0xad,0xce,0xad,0x1d,0x5e,0xd7,0x8c,0x6b,0xa4, - 0x4c,0x2e,0x3b,0xbc,0x56,0x96,0xaa,0x24,0x8d,0x64,0xd5,0x44,0x73,0x32,0x62,0x82, - 0x96,0x24,0x70,0xf3,0x53,0x8f,0xa6,0xc1,0xba,0x62,0x32,0x8b,0x63,0x68,0x03,0xac, - 0x23,0xf1,0x01,0xa9,0x0f,0xad,0x81,0xb5,0xc5,0x64,0x5a,0xfa,0x73,0x14,0x65,0x60, - 0x09,0x76,0x5e,0xbf,0xa8,0xf5,0x61,0x16,0xa0,0x16,0x30,0xa1,0xc6,0x86,0x5a,0x3e, - 0x0d,0xa9,0x74,0x2c,0x1d,0xa0,0x10,0xac,0x20,0x4c,0x4d,0x03,0x03,0xd0,0xee,0xf6, - 0x1f,0xd5,0x23,0x32,0x0c,0x82,0x4a,0x52,0xaa,0x01,0x1a,0x88,0xac,0x5a,0x2d,0x72, - 0x43,0x85,0x05,0xda,0xb9,0xf9,0x51,0xa4,0x39,0xe8,0xcf,0x60,0xbd,0x56,0x4f,0xa4, - 0x7e,0x0a,0x9e,0xd4,0x66,0x15,0x24,0x1d,0x9d,0x84,0xbf,0x85,0x64,0x41,0x52,0x4d, - 0xc0,0xdf,0xaf,0x16,0xd5,0xe1,0x24,0x2c,0x86,0x18,0x99,0x66,0xfc,0x5e,0xaa,0x44, - 0xa2,0x1b,0x51,0x2f,0x99,0xc9,0x2a,0x38,0x6d,0x04,0x13,0x70,0xeb,0x27,0x83,0xd3, - 0x8f,0xc4,0xd4,0x0e,0xfa,0x9f,0x2b,0xe8,0x58,0xd5,0xa8,0xac,0x1c,0xc6,0xe9,0x1c, - 0x6b,0x51,0x0e,0x03,0x05,0x69,0x0a,0xb8,0xdf,0x8b,0x7e,0xd2,0xf4,0x9d,0x2a,0xca, - 0x56,0x86,0x05,0x8a,0x36,0x18,0x73,0x5a,0xb8,0xf5,0x13,0x41,0x69,0xb2,0x4a,0xad, - 0x93,0x13,0x83,0x26,0x88,0x25,0x0e,0xa3,0x74,0x71,0x55,0x7a,0x8d,0x8c,0x7f,0x89, - 0xd2,0x23,0xab,0x54,0x0a,0xb8,0xfe,0xa3,0x19,0x49,0xcf,0xd1,0x45,0xc5,0x96,0xa5, - 0x09,0x92,0x83,0x92,0x3e,0xd2,0x9b,0xa6,0xe0,0x61,0xa4,0x9a,0x80,0xc4,0xdd,0xf9, - 0xc9,0xb0,0x09,0x73,0xa6,0x90,0x81,0xc3,0x14,0xc4,0xe8,0x8d,0xc0,0x20,0xb6,0x00, - 0x7f,0xbf,0xab,0xb1,0x9e,0x4b,0xa9,0xdd,0x3d,0xb0,0x13,0xf4,0xdc,0xd5,0x6a,0x77, - 0x8c,0xde,0x6f,0x3f,0xbb,0xdf,0x9e,0xf8,0x4e,0xac,0x9a,0x80,0xef,0xaf,0x4b,0xbd, - 0x68,0x3d,0x5d,0x08,0x74,0x6d,0x59,0x80,0xb5,0x74,0x43,0x9c,0xac,0xd3,0x25,0x19, - 0x18,0x48,0x6a,0xdc,0xfa,0xa9,0x40,0x5f,0x27,0x6b,0x75,0x69,0x37,0xae,0x40,0xed, - 0x24,0xab,0xe3,0x94,0x64,0x82,0x04,0x07,0x9c,0xd7,0x65,0xda,0xbf,0xd6,0xd8,0x46, - 0x22,0x1a,0xec,0xa4,0x8f,0x40,0x7b,0x83,0xf1,0x2c,0xe0,0x3c,0x7d,0x28,0x7a,0x70, - 0x2d,0x6d,0x31,0x00,0xd7,0x7f,0xb4,0x3b,0x12,0x27,0x79,0xbd,0x41,0x81,0xee,0x28, - 0xfb,0x47,0xc9,0x54,0x35,0x03,0x27,0xf4,0x45,0x14,0x4c,0xb3,0x00,0x37,0x9e,0xd1, - 0x6e,0x69,0x73,0xae,0x4f,0xdf,0x90,0x92,0x8e,0x52,0xb0,0x47,0xff,0xeb,0xd4,0x2c, - 0x06,0x4e,0xe9,0x0f,0x52,0xfb,0x60,0x83,0xa2,0x7b,0xfe,0xa5,0xab,0x1b,0x6d,0x26, - 0xa7,0xf4,0x5b,0x53,0xd5,0x47,0xa3,0x26,0x90,0x18,0xe8,0xd3,0xaf,0xa2,0x2d,0xd3, - 0x2c,0x50,0x44,0x5c,0x7f,0xf3,0xfa,0xbd,0x70,0xd4,0xfa,0x47,0x0a,0x03,0x31,0xbd, - 0x83,0x5e,0x1f,0x1a,0x72,0xf5,0x0c,0x14,0xe3,0xdc,0xfa,0x41,0x2a,0xf4,0xd0,0x27, - 0x06,0x6c,0xb3,0x23,0x1d,0xa6,0xa0,0x4f,0xbd,0xca,0x34,0x44,0xab,0x18,0x20,0xae, - 0xff,0x94,0x4e,0xe3,0xbd,0xa4,0x57,0x9f,0x99,0x4a,0x6c,0x03,0x06,0x2a,0x52,0xc9, - 0x6d,0xcc,0xfe,0xe8,0xeb,0x53,0xd2,0x36,0xa9,0xc1,0x04,0xc4,0xbd,0x7a,0xbb,0xb6, - 0x28,0x8d,0x56,0xc1,0x1a,0xc0,0x45,0x69,0x00,0xf5,0xc1,0x06,0x48,0x72,0x20,0x6d, - 0x01,0x77,0x3c,0xed,0x1d,0x44,0x1d,0x96,0x9b,0x23,0x55,0x74,0xfd,0xe8,0xf4,0xa1, - 0xac,0x90,0x11,0x07,0x54,0x13,0x10,0x6e,0x7e,0x56,0xe6,0xf5,0x67,0xe8,0xfa,0xa9, - 0x62,0xab,0x2b,0x27,0xab,0x19,0x59,0xe1,0x80,0x6e,0x02,0xbe,0x7f,0x46,0xca,0x8e, - 0xac,0x5d,0xb0,0x4e,0x7e,0x84,0x5a,0x9b,0x5c,0x56,0xa5,0xf6,0x87,0x82,0x3c,0x35, - 0x3b,0x72,0x32,0x8a,0xb2,0xc4,0x00,0xc0,0xcd,0x4f,0x15,0xca,0x8e,0xad,0x4d,0x27, - 0x65,0xdc,0x81,0xb2,0xc5,0xb5,0x6a,0x32,0x26,0x19,0x20,0x4d,0x41,0x06,0x0c,0x20, - 0x4b,0xce,0xec,0xb0,0x8f,0xa6,0x29,0x0a,0xc6,0x88,0x32,0xce,0x0c,0xb3,0x36,0x86, - 0x09,0x34,0x01,0xb8,0x80,0x1b,0x4f,0xa4,0x91,0x90,0x61,0xb5,0x67,0x77,0x24,0x02, - 0x84,0xe5,0xb1,0x92,0x5d,0x50,0x61,0x01,0x6e,0x3c,0x5d,0xda,0x34,0x1d,0x51,0x6b, - 0x1f,0x4d,0x10,0x89,0x81,0x99,0x30,0x8b,0xd8,0xf6,0xc7,0x05,0xee,0xfd,0x8e,0x6a, - 0xe6,0x36,0x11,0xcd,0x93,0x28,0x05,0x68,0x31,0x48,0xc5,0xa8,0x8e,0xfb,0xe0,0x2a, - 0x66,0x7f,0x54,0x30,0x01,0x3f,0x7e,0xcb,0x68,0x10,0x82,0x19,0xe8,0xa0,0xcf,0x13, - 0x4e,0xa3,0x14,0x7d,0xb0,0x94,0x22,0xa8,0x0c,0x60,0x0a,0xdc,0x0f,0x36,0xfb,0x6b, - 0xf4,0xa9,0x99,0x0f,0x31,0x2d,0xda,0x0b,0xbb,0xe0,0x16,0xa8,0x84,0x88,0x06,0x27, - 0x60,0x0e,0x03,0xcc,0x22,0x71,0xfd,0x73,0xf3,0xb5,0x55,0xd9,0xba,0xc2,0xae,0x51, - 0x44,0x81,0x56,0x97,0x48,0x50,0xd0,0xbe,0x2a,0xbb,0x26,0x81,0x8f,0xda,0x80,0xef, - 0xdf,0x24,0x6d,0x1a,0xf9,0x46,0x7a,0xfd,0x90,0xd4,0x84,0xef,0x63,0x60,0x47,0xf2, - 0x07,0x66,0xcb,0x8e,0xe4,0x8f,0x91,0x05,0x88,0x30,0x1e,0x83,0xfa,0x6b,0x26,0x19, - 0xcc,0x46,0xb2,0x74,0x3c,0x73,0xcc,0xf1,0x14,0xb0,0x35,0x1e,0xe1,0x7e,0x3b,0xf5, - 0x78,0x0a,0x77,0xd3,0xdf,0xab,0xd3,0xdc,0xc8,0xe2,0x43,0x78,0x63,0x3c,0x95,0xef, - 0x6e,0x88,0x93,0x7e,0x1b,0x70,0xdd,0xd1,0x5f,0x66,0xe3,0x6b,0xf1,0x3a,0x84,0x35, - 0xe9,0xeb,0x06,0x90,0x3a,0xbb,0xb2,0xb0,0x16,0x27,0x21,0xa9,0x75,0x65,0xd3,0x14, - 0xa0,0x24,0xbf,0x1e,0xe4,0x86,0x88,0xac,0x0d,0x2a,0x6a,0x5e,0x6e,0xc8,0xc8,0x59, - 0xba,0x36,0x1f,0x91,0x51,0xa6,0x39,0x3b,0x98,0x50,0x25,0xb9,0x61,0xb5,0x9c,0xdd, - 0x9e,0x50,0x1f,0xe1,0x87,0x53,0x85,0x23,0x39,0x6d,0x58,0x6b,0x56,0xaa,0x50,0x84, - 0x68,0xc3,0x4a,0x33,0xae,0x8a,0x53,0xb0,0x9f,0x01,0xd5,0x6a,0xe1,0xfb,0xc7,0x2a, - 0xea,0xd0,0xae,0xe2,0xbd,0xe9,0xd4,0xaa,0x28,0xdd,0x16,0x0f,0x2f,0x4a,0x57,0x33, - 0x70,0xa2,0xc8,0xc0,0xdc,0x3a,0x03,0x7c,0x8f,0x1f,0x4f,0xa5,0xb4,0xa5,0xbd,0xaf, - 0x60,0xee,0xfe,0x68,0x0f,0xdd,0xfd,0x67,0x31,0x70,0xaa,0xf0,0xa0,0xd9,0x72,0x8a, - 0x50,0xc0,0xcf,0xff,0xf4,0x95,0x99,0xdf,0x14,0x5e,0xd9,0x7b,0x53,0xe5,0x8d,0x0c, - 0xbc,0xbc,0xf7,0xa6,0x15,0xd3,0x57,0xaf,0x3c,0xbe,0xf3,0x95,0x39,0x3f,0xa9,0x9c, - 0x9e,0x59,0x79,0x82,0x81,0x1b,0xf8,0xf1,0x2c,0xfb,0xce,0xdd,0x57,0xfe,0xed,0xd0, - 0x27,0x1f,0x5c,0x68,0x63,0xe0,0xc0,0x27,0xe7,0x2e,0x2c,0xbb,0x7c,0xcf,0x7b,0x4f, - 0x5c,0x99,0xb8,0x74,0x61,0xd9,0xb7,0xef,0xb9,0xc2,0xc0,0x25,0xf8,0x5f,0x7c,0x96, - 0x3f,0x5d,0x39,0x37,0xb3,0xa2,0xb0,0xb3,0xff,0xba,0x0b,0x33,0x7e,0xd4,0x71,0xa5, - 0xf0,0x59,0xff,0xf2,0xef,0xaf,0xf8,0xce,0x3b,0x2b,0x0a,0x4f,0x5d,0x6a,0xbb,0xb2, - 0xe2,0xfa,0x77,0x56,0x7c,0xf2,0xd4,0x04,0xdf,0xbf,0xed,0xdb,0x77,0xbf,0xf7,0xc4, - 0x81,0x89,0x0f,0xdc,0x61,0x98,0x03,0x9b,0x38,0x47,0xfb,0xdf,0xfd,0x9e,0x31,0x42, - 0xbe,0x7f,0xd3,0xec,0x9e,0xf7,0x76,0xde,0x3a,0xb1,0xe3,0xde,0x65,0xec,0x0f,0x5f, - 0x98,0xf8,0xe0,0x34,0x05,0xef,0xd6,0x1d,0xc8,0x7f,0x70,0xa1,0x29,0x65,0x80,0xb3, - 0x7f,0x27,0x0c,0x68,0x70,0x40,0xdb,0xa3,0x5c,0xaf,0x54,0x17,0x29,0x3f,0xdc,0x03, - 0x8b,0x71,0xe5,0x9b,0x91,0x01,0xad,0x5e,0xb9,0x3e,0x51,0x39,0x1a,0x19,0x68,0xdf, - 0xc3,0x00,0x3f,0x9f,0xd8,0xe2,0x87,0xb9,0x23,0xd7,0xcd,0xa7,0x60,0x8d,0x92,0x64, - 0xfc,0xf0,0x14,0xa3,0x85,0x16,0x51,0x54,0x84,0xf9,0xe7,0xf8,0xa1,0xce,0xd1,0x42, - 0xb5,0x36,0x65,0x13,0xc5,0x14,0x26,0xc2,0x80,0x0c,0x92,0x16,0xcf,0x39,0xb4,0xcd, - 0x01,0xdb,0xdc,0x16,0xf7,0x23,0x77,0x6e,0xa9,0x8c,0x0d,0x76,0x20,0x18,0xeb,0x5c, - 0x80,0xea,0xf3,0x77,0xa8,0xf1,0x31,0xbc,0x05,0xd5,0x13,0x13,0x80,0x01,0x8a,0xc2, - 0xf5,0x37,0xb2,0x3d,0x51,0x22,0x39,0xca,0xba,0xc4,0xeb,0x5b,0x40,0x16,0xae,0x0f, - 0xd4,0xde,0xd1,0xc7,0x6a,0x13,0xe5,0x87,0x1b,0x19,0x3f,0x54,0x95,0xdd,0x78,0x0e, - 0x03,0x5b,0x95,0x3d,0x98,0x3d,0xaa,0x19,0x5d,0x78,0x47,0xbb,0x19,0xaf,0xcc,0xcd, - 0x1c,0xee,0x7a,0x2d,0x7e,0x03,0xfe,0x46,0xae,0x76,0xb8,0xf3,0xb9,0xf8,0x3c,0xdc, - 0x53,0xb4,0xc0,0x4a,0x62,0x00,0x6e,0xf4,0xc5,0x19,0x50,0x07,0x89,0xe3,0xd2,0x2e, - 0xa8,0xa1,0x46,0x2b,0x71,0x1c,0x9c,0xdd,0xc6,0x00,0x28,0xc1,0x80,0xe6,0xfe,0x41, - 0x31,0x46,0xdf,0x64,0xe9,0x9b,0x71,0x2f,0xb0,0x33,0x3a,0xec,0x4d,0x14,0x29,0xd0, - 0x89,0x62,0xb4,0x05,0xcd,0x34,0x5f,0x9a,0x35,0xe4,0xba,0x8f,0xe4,0x62,0x4f,0xa4, - 0x16,0x88,0xa2,0x62,0xf3,0x4d,0x55,0xb1,0x5e,0x30,0xf3,0xe2,0x2b,0x27,0xd7,0x5f, - 0xc3,0xba,0x69,0x2d,0x99,0xa1,0x4f,0x51,0x8b,0x8f,0x88,0xd5,0x12,0x77,0x81,0xd3, - 0x5f,0x41,0x5a,0x44,0x87,0xdd,0x30,0x97,0xd9,0x2c,0x13,0x54,0x32,0x90,0x32,0x00, - 0x58,0x2d,0x83,0xce,0xf0,0x35,0xc6,0x0f,0x29,0x29,0x6a,0x5f,0x45,0xf7,0x3b,0x9b, - 0x16,0x52,0xb0,0xc3,0xe1,0x87,0x0c,0xb8,0xfb,0x29,0xbb,0x73,0x3f,0x3f,0x5c,0x60, - 0x01,0xcd,0x69,0x71,0xae,0x4f,0xef,0x29,0x6d,0xb1,0x35,0x1b,0x1c,0x66,0xd9,0x3c, - 0x4d,0x60,0xb5,0xb8,0x7c,0x83,0x8d,0xc7,0xe0,0x6f,0x74,0x77,0xb6,0x40,0x9c,0x82, - 0x11,0x1b,0x98,0x2d,0x2e,0x3f,0xd4,0x90,0x9f,0x1f,0x32,0x50,0x2f,0xb4,0xb8,0xeb, - 0x21,0x8b,0xec,0xeb,0x03,0x7f,0x7d,0xba,0xad,0x0b,0xd7,0xe7,0xe6,0x47,0xc3,0x59, - 0x94,0x80,0x2e,0x4a,0xfd,0x2d,0x10,0xa7,0x00,0x3a,0x0d,0x30,0xc7,0x6a,0xc9,0x38, - 0xe3,0xe9,0xa1,0xeb,0xb6,0x9d,0xd4,0xeb,0x52,0x8a,0x3e,0x1d,0x9b,0x89,0x42,0xf9, - 0x21,0x62,0x2d,0x22,0x70,0x97,0x4f,0x0f,0x0b,0x29,0xa1,0xbf,0xb9,0x29,0x61,0x10, - 0xba,0x5e,0x8c,0x77,0xa5,0x9c,0xf9,0xd2,0x24,0x19,0xfc,0x50,0xee,0x04,0x6e,0x3c, - 0xeb,0x29,0x1b,0xcc,0xeb,0xd7,0x65,0x61,0x3d,0x25,0x8a,0xbf,0x36,0x68,0xa1,0xc3, - 0x0f,0x91,0xcd,0x0f,0xdd,0xfd,0x1d,0x75,0xe3,0xcd,0x94,0xa4,0x6d,0x48,0xc5,0x8f, - 0x1a,0xe0,0x8e,0x20,0xc0,0xfd,0x5e,0xa8,0x3b,0xb2,0x99,0xec,0xd1,0xaf,0x4f,0x55, - 0x1e,0x35,0xc0,0xad,0x26,0xa8,0x77,0x5b,0xae,0x4f,0x71,0xfb,0x7b,0xd6,0xe6,0x87, - 0x29,0x8b,0x1f,0xae,0x31,0x69,0xe7,0x0e,0x7d,0x83,0x09,0xd8,0x57,0x89,0xc3,0xdc, - 0xfa,0xa9,0x45,0x06,0x3f,0xa4,0xbb,0x27,0xb5,0x36,0x2b,0xd4,0x99,0xcc,0x10,0xcd, - 0xa1,0x3f,0x53,0x6d,0x0f,0x2e,0x18,0xf6,0x47,0x61,0xfc,0xd0,0x5d,0x3f,0x73,0x29, - 0x2d,0x4c,0xe9,0x15,0xbb,0xe1,0x47,0x14,0x5c,0x43,0xf9,0x21,0x62,0x44,0x51,0xb6, - 0x41,0x8a,0x01,0xb7,0x3f,0xe5,0xf3,0x78,0x2b,0xaa,0x81,0x8e,0x41,0x18,0xce,0x2f, - 0x41,0xb3,0xa1,0x83,0xc4,0xc7,0x69,0xcb,0x6c,0xb8,0x83,0x03,0xdc,0x7a,0x46,0xab, - 0x41,0x67,0xfc,0x70,0x25,0xec,0x24,0x2a,0xb9,0x3a,0x1d,0x61,0xb4,0xb0,0x9f,0xd1, - 0xc2,0x1e,0xb4,0xd3,0x26,0x8a,0xdc,0x78,0xe8,0xfa,0x51,0x73,0xa9,0x66,0xca,0x0f, - 0xb7,0xb3,0x65,0x33,0xdc,0x2d,0xf0,0x43,0x0b,0xf0,0xeb,0x27,0x83,0xb5,0xb7,0x12, - 0x0b,0xba,0x64,0x25,0x82,0xb3,0x39,0x25,0xdd,0x25,0xc7,0x23,0x58,0xa3,0xcf,0x7d, - 0xa7,0x01,0x72,0x06,0x00,0x6e,0x7e,0xa8,0x7d,0x2e,0x26,0xd2,0xf4,0xcd,0xe3,0x31, - 0x4a,0x90,0x12,0xc3,0x28,0x86,0x3a,0x20,0x4b,0x68,0x0b,0x05,0x6a,0xb6,0x68,0x00, - 0x8d,0x9b,0x1f,0x19,0x14,0x93,0x1f,0x82,0x46,0xdf,0x46,0x01,0x19,0xfc,0x10,0x99, - 0x44,0x51,0xb3,0xf9,0x21,0xca,0xba,0xe3,0x69,0x8c,0x30,0x7e,0x58,0x45,0xa2,0x8d, - 0x94,0x93,0x35,0x36,0xf0,0xfc,0xd0,0x06,0xa0,0xb8,0xf3,0xa3,0xe5,0x0d,0x23,0x13, - 0xb5,0xec,0x8f,0x60,0x76,0x1c,0xe0,0x48,0x82,0xb4,0xff,0x60,0x3f,0x3c,0x0d,0x15, - 0x1d,0x72,0x61,0x50,0xc7,0x4f,0xc3,0x5f,0x99,0xf6,0x47,0x66,0x66,0xa7,0xe0,0x58, - 0x24,0x6e,0x7e,0x74,0xbc,0xc4,0xf8,0xbd,0x08,0xfb,0xbd,0x6a,0xe4,0x0e,0xa2,0x8c, - 0xc3,0x12,0xb4,0x1d,0x18,0x30,0xbf,0x22,0x9c,0xfd,0xc9,0xd2,0x1b,0xfc,0x5a,0xb6, - 0x66,0x6d,0xf4,0x49,0xf8,0xa1,0x99,0xe6,0x15,0xc3,0x08,0x05,0x32,0x03,0x6f,0x52, - 0x80,0x19,0xe0,0xd6,0x33,0xe5,0x6f,0x8b,0x8a,0xd5,0xd9,0x28,0xa3,0x6d,0xf3,0xb5, - 0x6a,0x2d,0x9a,0x80,0x51,0x4a,0x2c,0xe5,0x2c,0x05,0xbf,0xa6,0x2d,0x31,0x06,0x0e, - 0x73,0xe3,0xe9,0x60,0xd6,0x26,0xdd,0x9d,0x82,0x87,0x0d,0x50,0x11,0x8b,0x9b,0xa0, - 0x3b,0x16,0x7f,0xca,0x06,0xbc,0xfd,0xd1,0xa0,0x89,0x5a,0xe9,0x08,0xf6,0x9a,0x70, - 0x11,0xb8,0xeb,0xa7,0xc7,0xe6,0x87,0xf9,0x4e,0xca,0x06,0x71,0x45,0x43,0x7c,0xa8, - 0xd3,0xa2,0x85,0xbb,0xb1,0x8f,0x1f,0x52,0xfb,0xd3,0xb9,0x36,0x9e,0xec,0xec,0x6a, - 0x57,0x94,0xfe,0x6c,0x3c,0x81,0x25,0x14,0xd7,0x3a,0xb3,0x4a,0x02,0x9b,0x86,0x88, - 0xb6,0x74,0xd1,0x16,0x77,0x3c,0x98,0x2d,0x40,0x47,0x77,0x50,0x06,0xbb,0xe8,0x92, - 0x04,0x73,0x6d,0x22,0x07,0xb8,0x8f,0x0b,0x60,0x46,0x0b,0x81,0xf2,0x43,0xa8,0x02, - 0xc6,0x06,0xa1,0x99,0xb5,0xe4,0x18,0xe8,0x74,0x18,0x23,0x35,0x7e,0xce,0x78,0xee, - 0x8a,0xae,0xd1,0xf2,0xc7,0x1b,0x6e,0x81,0xbb,0x22,0x75,0xda,0x09,0x0a,0xaa,0xef, - 0x42,0x6b,0x28,0x98,0x4f,0x41,0x94,0x81,0x45,0xb7,0x70,0xf6,0x87,0xde,0xaf,0xb6, - 0xa5,0xbd,0xbe,0x70,0x47,0x63,0xfc,0xad,0x4e,0x97,0x06,0x50,0xb0,0x81,0x02,0x70, - 0xf8,0x80,0xbb,0xa2,0x6f,0xb4,0xf9,0xe1,0xf4,0x95,0x2b,0x19,0x3f,0xfc,0xc9,0x7d, - 0x37,0x1a,0xfc,0x70,0xaf,0xc1,0x0f,0x7f,0xc3,0xc0,0x8a,0xff,0x69,0xdf,0xfe,0x51, - 0x10,0x86,0xa1,0x38,0x8e,0x47,0xfc,0x83,0x83,0x9b,0xbb,0x8b,0x1e,0x20,0xce,0x1d, - 0x2a,0x38,0xb9,0xd4,0xdd,0xbb,0x68,0x3d,0x82,0x78,0x01,0x3d,0x8d,0x17,0x10,0x5c, - 0x45,0x70,0xd0,0xbd,0x20,0x0e,0x52,0xfb,0x5e,0x5b,0x6d,0x1d,0x0a,0xed,0xa0,0x20, - 0xdf,0xcf,0xd2,0x10,0x92,0xf0,0x96,0xc0,0xef,0x51,0x92,0xa9,0xdf,0xb8,0x69,0x3e, - 0x74,0xfc,0xa9,0xe4,0xc3,0xf0,0xe1,0x6a,0x30,0x0b,0xe2,0x7c,0xb8,0x0f,0x83,0x30, - 0x97,0xc7,0xca,0xd2,0x58,0x78,0x5d,0x45,0xc7,0xde,0x93,0xa0,0x38,0xd8,0x4c,0x64, - 0xa0,0xf9,0x50,0x67,0xe6,0xd9,0xf5,0x1a,0x0b,0x6f,0x67,0x29,0x23,0x0d,0x8a,0xbe, - 0x0e,0xe2,0x7c,0x28,0x33,0xb9,0xbc,0xea,0xa4,0xf9,0xb0,0xdf,0xf3,0x8e,0xeb,0xa1, - 0xac,0x5f,0x78,0xbb,0xae,0x6c,0x7c,0x45,0xcd,0xea,0xd5,0xdb,0xa8,0xc5,0x8a,0xae, - 0x75,0xf4,0x1d,0x77,0xaa,0x9f,0x02,0x00,0x00,0x00,0xe0,0xdf,0x69,0xef,0xd0,0xa0, - 0x77,0x00,0x00,0x00,0x00,0x50,0x4c,0x7b,0x87,0x16,0xbd,0x03,0x00,0x00,0x00,0x80, - 0x62,0xda,0x3b,0xb4,0xb5,0x77,0xf8,0x75,0x29,0x00,0x00,0x00,0x00,0xbe,0xc8,0xca, - 0xfb,0x38,0x73,0xb8,0x58,0xb3,0x94,0x57,0x2b,0x75,0x6b,0x46,0xa5,0xff,0x27,0x24, - 0x7b,0x9b,0xd6,0x6c,0x6b,0xef,0x33,0x4f,0xb3,0xcf,0x75,0x4f,0xaa,0x75,0xf0,0xc5, - 0xf1,0x33,0x01,0x00, + 0x1f,0x8b,0x08,0x08,0x04,0x44,0x9f,0x46,0x00,0x03,0x70,0x6c,0x75,0x34,0x30,0x35, + 0x5f,0x31,0x5f,0x31,0x2e,0x62,0x69,0x74,0x00,0x94,0x9a,0x0f,0x70,0x14,0x55,0x9e, + 0xc7,0x7f,0xfd,0xba,0x93,0x74,0xa6,0x3b,0xe9,0x36,0x7f,0x30,0xb7,0x08,0xd7,0x19, + 0x07,0x76,0xc4,0x61,0x18,0x42,0x80,0x98,0x0d,0x49,0x33,0xa4,0xac,0x71,0xc9,0x1e, + 0xf1,0xce,0xbb,0xe2,0xf6,0xbc,0xdd,0x11,0x71,0x8f,0xbb,0xe2,0x2c,0xd6,0xdd,0xb3, + 0xb8,0x3b,0x4b,0x5f,0x66,0xa2,0x04,0x92,0x92,0x01,0x39,0x37,0xba,0xac,0x35,0x40, + 0x6e,0x8d,0x4a,0x59,0x11,0x75,0x8d,0x82,0xbb,0x4d,0x0c,0x3a,0x60,0xd4,0xb9,0x94, + 0x7b,0x8b,0x7f,0x8e,0x6d,0xd8,0xc0,0x46,0x89,0x3a,0xcb,0xa2,0x06,0x65,0xcd,0xbd, + 0xd7,0x3d,0xdd,0xd3,0x99,0x9e,0x04,0x37,0x5a,0xc5,0x2f,0xaf,0x1f,0x8f,0xf7,0xfb, + 0xcd,0xef,0xfd,0x7e,0x9f,0xfe,0xbe,0x81,0x52,0x29,0x63,0xfe,0x07,0xc0,0xdc,0x06, + 0xd2,0x96,0xcd,0xff,0x56,0x1f,0x5a,0xfe,0xfd,0xa5,0xdf,0x5f,0x1a,0xbc,0xf3,0xf6, + 0x8d,0xb0,0x01,0x84,0xba,0x1f,0x2d,0x0f,0xdd,0xf1,0xe3,0x1f,0x2e,0xad,0xaf,0x87, + 0xdb,0xc9,0x6f,0xa1,0xd0,0xca,0x25,0xe4,0xff,0xa5,0x37,0xc0,0x46,0x28,0x5d,0x5a, + 0xd7,0xb8,0xfc,0x86,0xc6,0xa5,0x2b,0xe1,0x0e,0x60,0x96,0xf5,0x4d,0x91,0x9f,0x27, + 0x1f,0xf9,0xdb,0x1f,0x84,0x00,0x33,0x00,0x50,0x12,0x62,0xa2,0xf4,0x4f,0x21,0xc4, + 0x28,0x0c,0xe0,0x96,0xc5,0x21,0xd0,0xe8,0xef,0x90,0x7d,0x5e,0x1a,0x02,0xc5,0xf9, + 0x3b,0x13,0x02,0x15,0xda,0x41,0xed,0x81,0x0a,0x19,0xae,0xf8,0xc3,0xa8,0x1c,0xb6, + 0xec,0x3f,0x73,0xfe,0xd4,0x09,0x3c,0xe3,0xb4,0xdc,0x4f,0xcb,0x85,0xa4,0x65,0xa2, + 0xd0,0xd7,0x59,0x1f,0xec,0xf5,0xdf,0xfd,0x5a,0xeb,0x7f,0x66,0xad,0xff,0xe7,0xce, + 0x87,0x8a,0xaf,0x31,0x1d,0x80,0xb3,0xf7,0x63,0x86,0x87,0x03,0x06,0x43,0x14,0x64, + 0x28,0xa6,0x86,0x42,0x46,0x10,0x80,0x69,0x18,0xeb,0x0f,0x5b,0xf3,0x87,0x8a,0xbe, + 0x82,0x29,0xdc,0xa2,0x8a,0x1a,0x5b,0x8f,0x76,0xe2,0x16,0x5d,0x4a,0xb1,0x75,0xf0, + 0x16,0x35,0x26,0x59,0xe3,0x11,0x35,0x32,0xb0,0xc5,0x9a,0x5f,0xf3,0x31,0x1c,0xc6, + 0x4b,0xa2,0x91,0x2e,0x4f,0x33,0xbc,0x17,0x0b,0xea,0x42,0x17,0xda,0x0f,0x4f,0x61, + 0x62,0x0c,0x22,0xfa,0xc8,0x30,0x32,0x9c,0x15,0xc5,0x13,0x45,0x3d,0xdc,0x01,0x10, + 0x55,0xbf,0xec,0xe9,0x84,0x18,0x04,0x34,0x41,0xae,0x68,0x85,0x38,0x35,0x42,0x68, + 0x04,0x9e,0x35,0x8d,0x43,0x8c,0xb5,0xbe,0xc6,0x1d,0x84,0xc3,0x10,0x8c,0x96,0xf6, + 0xc6,0xbe,0x89,0x1e,0x85,0xe0,0x51,0xa1,0x17,0xfd,0x1e,0x9e,0x82,0xa0,0x26,0x0c, + 0xa0,0x09,0xfa,0x88,0x18,0xde,0x0c,0x17,0xcd,0xce,0x5f,0x7d,0xd5,0x04,0x9c,0x87, + 0xe6,0x0d,0xa2,0xcc,0x2e,0x14,0x53,0xbb,0x9a,0xef,0x28,0xe9,0x89,0x6f,0x80,0xd7, + 0xa1,0x59,0x93,0x06,0xd8,0x09,0xf8,0xd2,0x34,0xd2,0x9c,0xb5,0x7e,0x92,0x39,0x02, + 0x53,0xd0,0xb4,0xba,0x3c,0x73,0xed,0x08,0x4c,0xf1,0xf7,0xa9,0x25,0x1a,0x3b,0x40, + 0x46,0x5a,0x34,0x29,0xc3,0x5e,0xb6,0x8c,0x71,0xb0,0xd6,0xd7,0xe4,0x83,0x74,0x91, + 0xa8,0xf8,0x73,0x76,0x81,0x7a,0x02,0x35,0xab,0x52,0x62,0xcd,0x59,0x6b,0x59,0x7b, + 0xfd,0x8b,0x9c,0x15,0xd9,0x93,0x45,0x01,0x63,0x93,0xfc,0x41,0xf6,0x9f,0xa0,0x3b, + 0x19,0x8c,0xfc,0x43,0x05,0x7a,0x4d,0x3b,0x6c,0xed,0xff,0xbc,0x69,0x5c,0x20,0xd9, + 0x6f,0xfe,0xa4,0xb8,0x36,0x1a,0x04,0x58,0xc4,0xdd,0x05,0x38,0xce,0x04,0x46,0x05, + 0x40,0x47,0xad,0xb0,0xd8,0xf1,0x99,0x24,0x67,0xc5,0xfc,0xc9,0xc8,0xdf,0x83,0x17, + 0xf0,0xe2,0xa8,0xff,0x9f,0xd1,0x77,0x61,0x5b,0xc7,0x62,0x5d,0x88,0xa0,0x77,0xe9, + 0x88,0x2e,0x6c,0x45,0xa7,0xe0,0x71,0xd3,0xf8,0xca,0x5e,0x3f,0xc2,0xb7,0xc1,0x1f, + 0xa1,0x49,0x2d,0x67,0x1e,0x82,0xd8,0x10,0x34,0x91,0xd5,0x58,0x8d,0x8e,0x68,0x52, + 0x88,0x1d,0x31,0x8d,0xa5,0xec,0x28,0xb2,0x12,0x49,0xad,0xa6,0xf1,0x69,0x51,0xa5, + 0x9b,0xd9,0x0c,0x59,0x86,0x44,0x23,0xcd,0x4e,0xaa,0xf9,0xf1,0x49,0x17,0x5b,0xf1, + 0xe1,0x39,0x23,0x3e,0x29,0x31,0xc6,0xfa,0xb0,0x16,0xa9,0xd3,0x24,0xcc,0x7a,0x5d, + 0xf1,0xff,0xd0,0xce,0x9f,0x54,0xcd,0x5e,0x78,0x01,0x02,0x61,0x3e,0xb4,0x5b,0x54, + 0xee,0x67,0x6a,0x35,0x41,0x0d,0xcb,0xb0,0x0d,0x16,0x6b,0xc2,0x16,0xf4,0x3e,0x79, + 0x64,0x18,0x17,0xec,0xcf,0x57,0x81,0xc7,0x0c,0xef,0xf8,0x4d,0x9e,0x0a,0x78,0x00, + 0xd7,0xea,0x82,0x1e,0x5b,0x01,0xdb,0x2c,0x7f,0xb3,0x8e,0xeb,0x76,0x66,0x6f,0xe2, + 0x7a,0x68,0xd0,0x46,0xfb,0x15,0x54,0x96,0x88,0x47,0xf4,0x31,0xa1,0x7e,0x7f,0x19, + 0xce,0xcf,0xb7,0x51,0x3b,0x3f,0xc7,0xab,0xc7,0xe1,0x0b,0x68,0xc1,0x62,0x92,0xbd, + 0xa1,0xf8,0x44,0xa4,0x0e,0x4b,0x3a,0x6a,0x44,0x27,0xa0,0x19,0x4b,0x49,0x96,0x3e, + 0x32,0x8c,0x2f,0xec,0xfd,0x44,0x98,0x24,0x4c,0x42,0x33,0x48,0xbc,0x70,0x5a,0x9d, + 0x54,0x89,0x81,0x59,0x5d,0x35,0x46,0x88,0x01,0x59,0x63,0x14,0xac,0xf5,0x79,0xb9, + 0x0f,0x2e,0x91,0xf8,0x8b,0xcf,0x55,0x2e,0x0c,0xbf,0x0e,0x75,0xaa,0xb4,0xbb,0x64, + 0x4c,0xbd,0x04,0x34,0x91,0xd8,0x31,0xc8,0x1a,0x43,0xf6,0x7e,0x30,0xb7,0x11,0x5e, + 0x84,0x60,0x7b,0x57,0xc2,0x53,0x02,0x1d,0x09,0xaf,0x4a,0xf2,0xff,0x2c,0x26,0x23, + 0xaa,0x90,0x40,0x63,0xe4,0x51,0x23,0x35,0x74,0xb0,0xaa,0x60,0x43,0x91,0x8f,0xce, + 0x0f,0xfb,0xf7,0x78,0x7c,0xb0,0x1d,0xbc,0xe1,0xb5,0xe6,0x34,0x7b,0xbe,0x61,0xbc, + 0x6a,0xe7,0x83,0x52,0xc5,0xc1,0x33,0x10,0x50,0x79,0x19,0xf9,0xc8,0x31,0x54,0x54, + 0x41,0x46,0xc3,0xc6,0x48,0xd6,0xf0,0x53,0x63,0x88,0xb1,0xf2,0x61,0x6b,0x59,0xd4, + 0x70,0x4a,0xc4,0x82,0x1f,0x52,0x50,0x47,0xbc,0x43,0xb6,0x9b,0xb6,0xf1,0x26,0x6b, + 0xe5,0x67,0x6f,0x11,0x75,0xaa,0xa5,0x7d,0xc9,0x1e,0xf6,0x53,0x62,0xfc,0x4a,0x95, + 0xda,0xd9,0xf7,0x2d,0x37,0x37,0x12,0xa3,0x91,0x1a,0xe7,0x8a,0xad,0x7c,0xa8,0x21, + 0xf3,0xdf,0x81,0x55,0x43,0x62,0x26,0x5e,0xcf,0xbc,0x41,0x13,0x2f,0x5d,0x72,0x11, + 0xf2,0xe3,0xf3,0xaa,0x5d,0x1f,0x1a,0x6a,0x74,0x18,0x84,0xa0,0x1c,0xe9,0x44,0xb5, + 0x6a,0x17,0x17,0x04,0x81,0xee,0x87,0x8c,0x4c,0x33,0xde,0xe4,0xac,0xf8,0x44,0xa0, + 0x93,0x38,0x15,0x54,0xf9,0x10,0xf1,0xb7,0x03,0x7c,0xea,0x5a,0xc3,0x4d,0x26,0xa0, + 0xb2,0x0e,0xc7,0x73,0x9f,0x57,0x2f,0xd7,0x07,0x2f,0x32,0xc1,0x28,0xbf,0x47,0x09, + 0x90,0x78,0x92,0xe8,0x3d,0x5c,0x28,0x9e,0x76,0x3e,0x24,0xab,0xc7,0xc4,0x77,0xb8, + 0xa6,0x4d,0x81,0x44,0x69,0xb1,0x77,0xbb,0xde,0xac,0xae,0x4b,0xa0,0xb3,0xf0,0xef, + 0x79,0xfb,0x1f,0xb7,0xeb,0x4f,0x8a,0xe9,0x83,0x1b,0xe8,0xe0,0x23,0xc2,0x39,0xf5, + 0x52,0xc2,0x78,0xfa,0x7b,0x97,0xbf,0x5f,0xd8,0xf5,0x87,0x97,0x8d,0x7c,0x93,0x45, + 0xb4,0xa6,0x16,0xa5,0xd4,0xe6,0x52,0xa9,0x93,0x3d,0xed,0x8a,0xff,0x09,0xbb,0xfe, + 0xf8,0x8b,0xfc,0xf0,0x12,0x2c,0xe9,0xe7,0x75,0xf4,0x2d,0xfc,0xe0,0xea,0x25,0x0f, + 0x09,0xfb,0xd1,0x97,0xa1,0x97,0x20,0x88,0xe7,0x26,0xd1,0x38,0x50,0x43,0x48,0x92, + 0xfc,0xb6,0xf2,0xc1,0x6f,0xd6,0x9f,0x49,0x8f,0x0f,0x49,0x4a,0xbc,0x8b,0x9c,0x8e, + 0x06,0xf4,0x86,0xef,0x59,0x66,0xfa,0x79,0x39,0x61,0xd7,0x1f,0x2c,0xdf,0x6a,0x1c, + 0x52,0xcf,0x16,0x6f,0x0f,0x6c,0x53,0x17,0x63,0xd6,0x71,0x6c,0x6d,0x63,0xdc,0x5e, + 0xbf,0xab,0xeb,0x94,0xfc,0x39,0x5e,0xa5,0x07,0x1b,0x84,0x39,0xf0,0x1a,0x31,0xa4, + 0xf5,0xe4,0x74,0xd0,0x11,0x61,0x2b,0x7b,0xca,0x30,0xa4,0xad,0xec,0x87,0x76,0xfd, + 0xe1,0xab,0x8d,0x7a,0xa2,0x95,0x0d,0x54,0x6e,0xa4,0x06,0x76,0x96,0x11,0xdb,0x18, + 0xb2,0xeb,0x0f,0x14,0xfd,0x92,0x36,0xa9,0x64,0xf9,0x49,0x76,0xbe,0xfc,0x5a,0x82, + 0x11,0xdb,0xde,0x59,0xf3,0x99,0x3a,0x95,0x98,0xde,0xbf,0x34,0xbb,0xfe,0xf4,0xd7, + 0xec,0x55,0xc9,0x26,0x3b,0xcb,0x6e,0x66,0x6f,0xc5,0xdb,0xa0,0x76,0x8f,0xa7,0x1d, + 0xbd,0x9d,0xbf,0x7f,0xf6,0x49,0xfb,0xf3,0x05,0xbc,0xd7,0xf4,0x57,0x46,0xff,0xe8, + 0x7b,0x90,0xaf,0x6d,0x2d,0x6d,0x7f,0xf5,0x6d,0xee,0x05,0xf8,0xd7,0x69,0xfe,0x6a, + 0x76,0xfd,0x51,0xcc,0xfa,0x93,0xb9,0x49,0x42,0x6d,0xc5,0x31,0x55,0xc1,0xc2,0x7c, + 0x78,0x55,0xcd,0xaf,0xe7,0x5d,0xf6,0x79,0xef,0xaf,0x9e,0xe0,0x89,0x53,0x99,0xf2, + 0xe7,0xd8,0xdb,0xe1,0x75,0xed,0x10,0x33,0xef,0x08,0xf9,0x58,0xbf,0x84,0x7b,0xa7, + 0xd7,0x4f,0x7b,0x3f,0x98,0x31,0xe2,0xd3,0xb6,0xae,0xaa,0x92,0x3c,0x8d,0x34,0x43, + 0xf9,0x00,0xc9,0x87,0xfc,0xf8,0xe4,0xea,0x61,0xad,0x6c,0xf4,0x3b,0x4d,0xcc,0xb0, + 0x7f,0x87,0xdf,0xc0,0x12,0xf4,0xa4,0x49,0x37,0xcf,0xaf,0xe7,0x5a,0xab,0xb5,0x9f, + 0x7d,0xdc,0x66,0xf8,0x29,0x04,0xb7,0xf6,0x1f,0x79,0xe9,0x71,0xe8,0xd7,0x03,0x0a, + 0x3f,0x80,0x7e,0x07,0x87,0xa7,0xf7,0x5f,0xa4,0xdb,0xf5,0x01,0x93,0x7e,0x47,0xba, + 0xb3,0xce,0xef,0x42,0x3e,0xb9,0x5b,0x09,0x2a,0xa5,0x89,0x8a,0x33,0x8a,0x6b,0xbe, + 0x9d,0x0f,0x7c,0x95,0x68,0x04,0x81,0x07,0xd4,0x03,0xfb,0xc8,0x69,0x2d,0x95,0x49, + 0xf4,0xf2,0xe3,0x93,0xab,0x3f,0x50,0xb6,0x99,0xf6,0x77,0x4d,0xc4,0x95,0x3e,0x44, + 0xda,0x0a,0x94,0x25,0x8c,0xf8,0x64,0xfd,0x3d,0x6c,0x1a,0x9a,0x5d,0x7f,0xf6,0x15, + 0x5d,0x86,0xdf,0x12,0xa7,0x96,0x68,0xc4,0xbb,0xcb,0xd0,0x02,0x4f,0x17,0xf2,0xf7, + 0x03,0xbb,0xfe,0x68,0x45,0xd9,0x24,0xd1,0x2b,0x9b,0xe1,0x32,0x5e,0x59,0xdb,0x93, + 0x62,0x2f,0xc0,0x6f,0x67,0xe4,0x1f,0x2c,0x53,0xc8,0x69,0x4c,0x76,0x77,0xb1,0x01, + 0xf8,0x00,0x7b,0xc1,0xd3,0x85,0xf4,0x64,0x77,0x1e,0xff,0xe8,0xb9,0xfa,0x5f,0xd4, + 0x96,0x75,0xaa,0xb8,0x8d,0x56,0x27,0x95,0x38,0x3e,0xec,0xea,0x47,0x43,0x39,0xfe, + 0xa9,0xa6,0xfc,0xb3,0x08,0x93,0xa0,0x05,0xe0,0x09,0x6d,0xd1,0x06,0x4f,0x4f,0xc5, + 0x39,0xa5,0x3b,0x2f,0x9e,0x39,0xfe,0x81,0xaa,0x00,0x8d,0x46,0x72,0xe7,0x13,0xc2, + 0x66,0xc8,0x68,0x4d,0x21,0xbe,0x8b,0xfd,0x9d,0xab,0xff,0x6a,0x76,0xfd,0x39,0x0d, + 0x46,0x7f,0xdf,0x25,0xe9,0xec,0x11,0xf8,0x13,0xac,0x04,0x49,0xab,0x74,0xc7,0x67, + 0xd2,0xc9,0x3f,0xf2,0x7b,0xd0,0x3c,0x22,0xfa,0x0e,0x4c,0xa0,0x14,0x5e,0xa1,0x92, + 0xfa,0x73,0x16,0xd6,0x9a,0xcb,0x6e,0xb6,0xd6,0xcf,0xd8,0xf5,0x27,0xd5,0x6a,0xf0, + 0x4f,0x82,0x1f,0x24,0xbb,0x25,0xfd,0x48,0x2d,0xc7,0x68,0x8c,0x99,0xb6,0xff,0x72, + 0x27,0xff,0x9c,0x31,0xe3,0x93,0xf6,0x28,0xe1,0x11,0x02,0xa8,0x3e,0x20,0xf5,0x59, + 0x97,0x69,0x7c,0x3c,0x05,0xf9,0x67,0x03,0x33,0x9f,0x36,0xfd,0xa4,0x27,0x52,0x7c, + 0x4a,0x2e,0xc2,0xb5,0x8a,0xb0,0x9e,0xf0,0xcf,0x34,0x1e,0xf0,0x6c,0x45,0x27,0x1d, + 0xfc,0x43,0xf3,0xad,0x29,0x5d,0xce,0x6d,0x9b,0x80,0x30,0x54,0x69,0x52,0x05,0x29, + 0xb3,0x71,0x72,0x22,0xca,0x43,0x6c,0x9b,0x05,0x42,0xa3,0x76,0xba,0xa9,0xf3,0x68, + 0x7c,0x56,0xa5,0x17,0xff,0x9a,0x44,0xe3,0x22,0x01,0x83,0x72,0x92,0x3f,0xea,0x94, + 0x3c,0x13,0xff,0xf4,0x17,0x19,0x41,0x96,0x49,0x58,0x48,0xfc,0xa1,0x99,0x21,0xd1, + 0x38,0x33,0x1b,0xff,0x5c,0x65,0xd4,0x13,0x2c,0x00,0x7b,0x2b,0xf7,0x3c,0xda,0x07, + 0x82,0x4a,0x76,0xfb,0xf8,0x8c,0xfc,0xa3,0x99,0xfc,0xb3,0x81,0x60,0xde,0x7c,0xf8, + 0x85,0xb6,0xf8,0xb6,0xb9,0x5b,0xd1,0x67,0x2e,0xfe,0xc9,0xd8,0xe7,0x3d,0x52,0x65, + 0x04,0x2d,0xd3,0x7d,0x0d,0x6a,0xe3,0x9f,0x55,0x95,0xb4,0x50,0x1f,0x7b,0x13,0x0e, + 0xcc,0xc2,0x3f,0xfd,0x14,0x72,0x12,0xd2,0x41,0xd6,0xcf,0x7f,0x06,0xf7,0xc5,0x05, + 0x1d,0x5d,0x52,0xf2,0xf8,0x07,0x39,0xf8,0x07,0x8c,0xa6,0x23,0xb3,0x45,0xb4,0xfb, + 0xdc,0x64,0xb6,0xa1,0xce,0xd9,0xf8,0xc7,0x68,0x6a,0x43,0x65,0x03,0x71,0x1f,0x73, + 0x09,0xd7,0x85,0xa5,0xc4,0xed,0xb4,0x8d,0xce,0xcc,0x3f,0x46,0x93,0x6d,0x17,0xf6, + 0xee,0xf0,0x95,0xbe,0xb8,0x9e,0xf0,0x4f,0xc2,0x6b,0xb6,0x5d,0xc9,0xd1,0x7f,0x73, + 0xfc,0x53,0x93,0xe5,0x1f,0x61,0x37,0xda,0x28,0xbf,0x08,0xfb,0x57,0xcf,0x4d,0xa0, + 0x3e,0x63,0xda,0xdc,0x82,0xfc,0xc3,0x03,0x97,0x6d,0xfa,0x75,0x45,0xc4,0x50,0xda, + 0xe7,0xca,0xe8,0x18,0x47,0x47,0x3c,0x0e,0x1e,0xc8,0xd5,0x9f,0x41,0x3e,0x6a,0x39, + 0x15,0x85,0x41,0xa6,0x02,0x76,0x62,0xd6,0x24,0x40,0xc1,0xe1,0xef,0xc7,0xac,0xb5, + 0x9f,0xde,0x79,0x59,0xa7,0xf6,0x10,0xef,0xfe,0x44,0x78,0x66,0x67,0xfa,0x6f,0xde, + 0xaf,0xc9,0xef,0xef,0xe7,0x4a,0xac,0x78,0xf6,0x56,0x1b,0xbc,0xa4,0x8a,0xe9,0x6d, + 0x63,0xf0,0x29,0x1c,0x6a,0xaf,0x19,0x60,0x17,0xb8,0x78,0xe0,0x9c,0x9d,0x3f,0x0d, + 0x72,0x94,0xa3,0x90,0xe3,0xef,0x44,0x7a,0x62,0x12,0xbc,0x50,0x86,0x11,0x2e,0xc0, + 0x3f,0xb9,0xb7,0xd8,0x56,0xe2,0x9d,0xa8,0xf2,0x35,0x68,0x58,0x79,0x86,0xe9,0x57, + 0xf9,0x04,0xe2,0x18,0x07,0xef,0x65,0xfd,0xcd,0xf1,0x98,0x11,0x3d,0x0d,0x76,0x91, + 0xe8,0x3d,0xc1,0xfb,0xd5,0xed,0x89,0x70,0x9f,0xea,0x8a,0x67,0x8e,0x7f,0x38,0xca, + 0xb7,0xcd,0x61,0x6e,0x2f,0x79,0xfa,0x4c,0xc5,0xbf,0xac,0xe7,0xe7,0xd8,0xfb,0x5f, + 0x53,0x80,0x7f,0xfa,0xc1,0x98,0xbf,0x3a,0xeb,0xdd,0xdd,0x11,0xe9,0x51,0xe2,0x5d, + 0xbe,0xbf,0x1f,0xda,0xf5,0xc7,0x0f,0x26,0xff,0x48,0x78,0x8d,0x22,0xa6,0xda,0x56, + 0x80,0xd4,0xb9,0x46,0x87,0x14,0x9a,0x91,0x7f,0x38,0xca,0x3f,0x8b,0x7b,0x05,0x7d, + 0x87,0xbf,0xf8,0xc1,0xa3,0x5e,0x4a,0x3b,0xe3,0xf0,0x2e,0x49,0x63,0x21,0xc7,0x3f, + 0xec,0x8e,0x1c,0xff,0xfc,0x97,0x51,0x7f,0x06,0x05,0x2f,0x12,0x21,0xae,0xb6,0x1e, + 0xa5,0xc7,0x84,0xbc,0x2b,0x05,0xb4,0x52,0x67,0x7d,0xb6,0xeb,0x4f,0x2d,0x73,0x8d, + 0x79,0x7e,0x37,0xa1,0xf9,0x91,0x6d,0x7c,0x6d,0x6a,0xee,0x16,0x74,0xaa,0xe3,0x27, + 0x70,0xdd,0xb4,0xf3,0x9b,0xcc,0xad,0xcf,0xcf,0x97,0x3f,0xef,0x58,0xb5,0x4f,0xf0, + 0x7b,0x9b,0xf1,0x8d,0x78,0xf9,0x05,0x89,0x62,0xcf,0x6f,0xc8,0xb1,0x95,0x4c,0xfe, + 0x99,0x97,0xc7,0x3f,0x65,0x26,0xff,0x90,0xd3,0x37,0x41,0x4e,0xdf,0x2f,0x53,0xd2, + 0xc0,0x9a,0x8f,0xe4,0x99,0xf9,0x47,0x35,0xfb,0x57,0xb2,0x2c,0xc5,0xde,0x03,0xaf, + 0xe2,0x65,0xfa,0xba,0x49,0x76,0x4a,0x99,0x72,0xf6,0xaf,0x75,0x93,0x95,0xe9,0x1c, + 0xff,0x5c,0x65,0xf0,0x0f,0xe6,0x55,0xd4,0xa4,0xfe,0xaf,0x72,0xdd,0x90,0x44,0xb6, + 0xad,0xe6,0xf3,0x5b,0x8e,0x37,0x12,0x60,0xd4,0xab,0x4e,0x7e,0x0b,0xba,0x06,0x1e, + 0xe6,0x6e,0x33,0xa6,0x29,0xf9,0xf3,0x87,0xed,0xfa,0x13,0xad,0x1a,0xe1,0x49,0xd0, + 0x74,0x1e,0x76,0x04,0x60,0xb7,0xb8,0x28,0x13,0x5b,0x8e,0xde,0x72,0xf5,0xf7,0x93, + 0x76,0x7e,0xfa,0x0d,0xde,0x6b,0x92,0xc5,0x27,0xd9,0x26,0xc2,0x3f,0x3f,0xba,0x28, + 0xbc,0xcc,0x4e,0xa9,0xf9,0xfe,0x9e,0x70,0xec,0xc7,0x18,0xdc,0xf3,0xa0,0xc2,0x1e, + 0x64,0xbe,0xc4,0xd3,0xa7,0xd9,0xc6,0x98,0x5d,0x1f,0x76,0xc9,0x97,0x19,0x52,0xb4, + 0xef,0x12,0xf5,0xca,0x26,0xfe,0x14,0xb3,0x4c,0xbb,0x26,0x53,0x69,0x96,0xf1,0x32, + 0x47,0x3d,0xd7,0xed,0xfd,0x1c,0xed,0xdc,0x4c,0x9b,0x54,0x9a,0xef,0x47,0x07,0x8b, + 0x63,0x8c,0x97,0x74,0x2b,0x30,0xdb,0x96,0xe4,0x78,0x7f,0x3f,0xad,0x5a,0xeb,0x13, + 0xfe,0x91,0xc9,0x53,0xcc,0xf7,0x17,0x07,0x60,0x87,0xe2,0x3d,0xca,0x0f,0x78,0x27, + 0xdc,0xbc,0x94,0xab,0x3f,0x1c,0xed,0x47,0x41,0x1c,0x81,0xf2,0x1e,0x88,0x81,0xa2, + 0xad,0x0d,0x15,0x9b,0x61,0x31,0xfa,0xdd,0x81,0x7c,0xfe,0xc1,0x22,0xed,0xa7,0xcd, + 0x58,0x1c,0x20,0xbc,0xb1,0x83,0x59,0x76,0xf4,0xe4,0x00,0xd9,0x3f,0x75,0x53,0x70, + 0xf8,0x3b,0x6e,0xd7,0x9f,0xe4,0xbc,0xcb,0x32,0xe9,0x5f,0x5a,0x99,0x4a,0xbc,0x9b, + 0x80,0x5f,0x69,0xdf,0x73,0xb8,0x79,0x19,0x3e,0xc9,0xfa,0xcb,0x5a,0xf1,0xd4,0xb2, + 0xfc,0x2c,0x9d,0x61,0xeb,0x60,0x18,0xaf,0xc4,0xa2,0x86,0x1a,0xe1,0x93,0x19,0xf9, + 0x47,0x33,0xf8,0x27,0x98,0x14,0x0e,0x22,0x45,0xee,0xc2,0xde,0x24,0xdf,0x8b,0x9e, + 0x86,0x7c,0xfe,0xc9,0xe9,0x3f,0x29,0x6e,0x84,0x7b,0x16,0x44,0x10,0xfa,0xc2,0x1b, + 0xa1,0x0b,0x6d,0xec,0x28,0x0d,0x55,0xf0,0xae,0x7e,0x74,0x21,0x8f,0x7f,0x8c,0x97, + 0x94,0x3b,0xe9,0xfa,0x89,0xeb,0xe8,0xfa,0x4f,0xcd,0xc8,0x3f,0x6a,0xb5,0x11,0x84, + 0xb0,0x74,0x2d,0x0a,0xc7,0xb4,0xd4,0x8a,0x8e,0xb2,0x9e,0xf8,0xb5,0xca,0xf9,0x2b, + 0xe8,0x3f,0x2d,0x37,0x4a,0xe3,0x95,0x83,0x84,0x0f,0xef,0xd1,0xca,0x35,0xf6,0xa2, + 0x41,0x8c,0xce,0xfe,0x3e,0xe1,0xd2,0x7f,0x48,0x91,0xe9,0x83,0x94,0x6c,0x7c,0x10, + 0x63,0xf8,0x8a,0xfa,0xcf,0x6d,0x42,0x27,0xe1,0xb7,0x6e,0xec,0x1d,0x27,0x85,0xf7, + 0x98,0x2b,0x1f,0x72,0xfc,0x33,0x6e,0xf1,0xe1,0xf5,0x28,0x06,0xb1,0xa4,0xff,0x03, + 0xbe,0xd4,0x3b,0xab,0xfe,0x93,0xe5,0x1f,0x61,0x3c,0xdc,0x08,0x0f,0x24,0xf6,0x25, + 0xf9,0x4d,0xde,0xd1,0x9c,0xfe,0x93,0x35,0x2e,0x4f,0xe3,0x1f,0x02,0x39,0x20,0xc9, + 0x6c,0xa7,0x77,0x48,0x6e,0xd0,0x02,0x4a,0xbe,0xfe,0x53,0x12,0x72,0xea,0x3f,0x06, + 0xff,0xb4,0x80,0xd4,0x5e,0x79,0x12,0xbe,0x92,0xbf,0xd5,0x29,0xfd,0xa1,0x00,0x3f, + 0xbb,0xf8,0x27,0x42,0x82,0xa0,0xc0,0x93,0x50,0xa7,0xf5,0x60,0xd2,0x94,0xf2,0xe2, + 0xbf,0xc6,0xc5,0x3f,0x43,0xc2,0x16,0x4f,0x0d,0x3c,0x00,0xfb,0x34,0x3e,0x8a,0x12, + 0x6e,0xfd,0xc7,0x8e,0x3f,0x36,0xf9,0x27,0x2a,0xac,0x8f,0xcd,0xe1,0x7f,0x8e,0x95, + 0x8f,0x78,0x3f,0xba,0x5b,0x7e,0x3c,0x5f,0xff,0xb1,0xe3,0x9f,0xe5,0x9f,0xbf,0x16, + 0xe4,0x0a,0x0f,0xc4,0x38,0x25,0xed,0xaf,0x8f,0x1d,0x53,0x66,0xd3,0x7f,0xfa,0x4d, + 0xc8,0x89,0xb2,0x8d,0xf2,0xc7,0x5b,0xea,0x70,0x60,0x4c,0xf8,0x4f,0xfc,0xe1,0xcc, + 0xfa,0x0f,0xd8,0x4d,0xe7,0x74,0x78,0x52,0x6d,0xae,0x20,0xc6,0x3e,0xee,0x8a,0xfc, + 0xa3,0x49,0x7b,0xe3,0x0b,0xe1,0x78,0xc7,0x40,0xab,0xf8,0x0d,0x02,0xb9,0x57,0xd4, + 0x7f,0x56,0x0b,0xbd,0xe1,0x05,0xd0,0xa1,0x79,0x27,0x3d,0x89,0x8a,0x6f,0x1a,0xfa, + 0x4f,0xf9,0x6c,0xfc,0x43,0x06,0x3d,0x9c,0xba,0xbd,0xd6,0x4b,0xfa,0xbb,0xa7,0x0f, + 0xe7,0xe9,0x15,0x15,0x0e,0xfe,0xe1,0x0c,0xfe,0x89,0x0a,0x35,0xa8,0x08,0x3a,0x40, + 0x21,0xd8,0x53,0xde,0x09,0x33,0xf3,0x4f,0x43,0x99,0xcd,0x3f,0xa4,0xa4,0x33,0x75, + 0x54,0x08,0x4a,0x4e,0xd7,0x1f,0x4a,0x30,0xfb,0x26,0x63,0xeb,0x3f,0xf3,0xb2,0xfe, + 0xde,0xc2,0x5e,0x44,0xcf,0x43,0x73,0xbb,0xf4,0xb6,0x70,0x8b,0xe1,0x66,0xb9,0x93, + 0x67,0xb8,0x1c,0x6f,0x18,0xfc,0xa3,0x49,0xe9,0xb8,0x0f,0x8e,0x41,0x5d,0x44,0x4c, + 0xb3,0xf5,0x6e,0xfd,0xc7,0xc1,0x3f,0x59,0xc8,0x49,0x22,0x1e,0x4e,0x92,0x54,0xe3, + 0xef,0x27,0xdd,0x76,0x66,0xfe,0x89,0x14,0xd9,0x4e,0xb5,0xd6,0x6e,0x47,0x4a,0xbb, + 0x47,0x0e,0x73,0x90,0xcf,0x3f,0xa3,0x39,0xfe,0xa9,0xee,0xb3,0x82,0xdc,0xba,0xfa, + 0xa7,0xb2,0x57,0xf5,0x3c,0x8c,0xfe,0x7b,0x76,0xfd,0x87,0x6e,0xf2,0x87,0x52,0x42, + 0xf8,0x01,0x3a,0x7e,0xa6,0x4e,0x5d,0x94,0x60,0x1d,0x9f,0xef,0x8b,0xf9,0xfc,0x33, + 0xce,0xf4,0x71,0x97,0xe8,0x79,0xf9,0x06,0x7b,0x10,0x2e,0xc5,0x8e,0xa8,0x65,0x35, + 0x39,0x37,0x0b,0xe8,0x3f,0x7e,0xd9,0xe2,0x9f,0x78,0x2d,0x9c,0xe4,0xe7,0x90,0xf8, + 0xb3,0x8a,0x72,0x45,0xfd,0x67,0x0f,0xc1,0xf8,0x45,0xe4,0x7c,0x79,0x71,0x38,0x59, + 0xb9,0xd5,0x92,0x7d,0x0a,0xe9,0x3f,0xd9,0xf7,0x2f,0x81,0x41,0x25,0xc3,0x0f,0x81, + 0x6f,0x12,0x42,0xc5,0xa5,0xae,0xfa,0x93,0xd3,0x7f,0x92,0x26,0xff,0xa8,0x64,0xf0, + 0x1a,0xe6,0x27,0xbc,0x82,0x3c,0xa1,0xe2,0x5b,0x99,0x99,0xf5,0x9f,0x7e,0x7e,0x3e, + 0x81,0x1c,0x42,0x3b,0x11,0x61,0x0e,0xfc,0x1a,0x2f,0xf7,0x8a,0xeb,0xd9,0x0a,0x4b, + 0xf6,0x29,0xa4,0xff,0xcc,0x33,0xea,0xad,0x4a,0xaa,0xc7,0xd9,0xe2,0xa7,0x4c,0x63, + 0x0c,0xde,0x9b,0x45,0xff,0xa1,0x4d,0x6a,0x55,0x5f,0xf9,0xf8,0x9a,0x6f,0xc1,0xb1, + 0x7d,0xcb,0xa2,0x81,0x49,0xb6,0x19,0xa6,0xf2,0xfa,0x97,0xe6,0xe4,0x1f,0xba,0xc9, + 0x39,0xfc,0x86,0xf0,0x55,0xf8,0x7e,0xe5,0x3a,0xd5,0x00,0x9b,0x99,0xf9,0x07,0x4c, + 0xfe,0x39,0xfa,0x5d,0x0d,0xd5,0x54,0xdd,0xdf,0x74,0x1b,0xe6,0x6f,0x41,0x55,0xae, + 0xf9,0x0e,0xfd,0xc7,0xac,0x3f,0x54,0x6f,0xf4,0x40,0x07,0xf6,0x03,0xdf,0x40,0x0e, + 0x5a,0x7e,0x3c,0x53,0x0e,0xfd,0xc7,0xec,0x2f,0xe4,0x74,0x5f,0xef,0x3d,0x9e,0xa8, + 0x6b,0x0f,0x0c,0x74,0xd7,0xba,0x78,0xe6,0x7c,0x4e,0xff,0x31,0xf9,0x07,0x49,0x49, + 0xe1,0x03,0xb8,0xa4,0x12,0x83,0xa6,0x8d,0x5b,0xff,0xb1,0xd6,0x67,0xe4,0xcb,0xa6, + 0x9e,0xaf,0xb1,0x17,0x94,0x11,0xa6,0x1e,0x44,0x99,0x0d,0x29,0x33,0xeb,0x3f,0x18, + 0x0c,0xfe,0x89,0xde,0xd4,0xf7,0x4a,0x12,0x25,0x87,0xbc,0xbc,0x3f,0x81,0x16,0x16, + 0xe0,0x19,0x07,0xff,0x30,0x74,0x3e,0x19,0x4c,0xe1,0xed,0x38,0x78,0x13,0xff,0x4c, + 0x85,0xb7,0xf6,0x4a,0xfc,0x13,0x80,0x52,0x85,0x04,0xad,0x1f,0xfc,0x54,0x88,0xe6, + 0xae,0xa0,0xff,0x18,0xf9,0x80,0x49,0xb7,0x4a,0x31,0xcd,0x10,0xa0,0xe7,0x2b,0xdf, + 0xdf,0x9c,0xfe,0x43,0xf8,0xc7,0xf0,0xb7,0x2c,0xca,0x1e,0x21,0xfd,0xfd,0x05,0x58, + 0x92,0x26,0xfd,0xdd,0x75,0xbf,0x83,0x6c,0xde,0xb8,0xea,0x2b,0x94,0xbd,0xed,0xda, + 0x0d,0x13,0x78,0x99,0xd2,0x33,0xc2,0x36,0xe1,0x4f,0xf0,0xaa,0x94,0x78,0x31,0x97, + 0x48,0x19,0xbb,0x3e,0x60,0xf8,0xd8,0xa2,0x9d,0x0d,0xd0,0x85,0x57,0x28,0x04,0xdb, + 0x5a,0x54,0x32,0x92,0x21,0x85,0x28,0x68,0xeb,0x3f,0xf6,0x79,0xe4,0x8b,0x46,0x20, + 0x0e,0x7e,0xea,0x14,0x86,0x43,0xb0,0x08,0x78,0x44,0x5e,0x34,0x08,0xff,0xa4,0xf9, + 0x43,0x48,0xcc,0xf9,0x6b,0xc5,0x9f,0xf2,0x4f,0x56,0x2d,0xd9,0xc0,0x3f,0x8a,0xef, + 0xf4,0xee,0x48,0x90,0x68,0xd1,0x11,0xff,0x2e,0x14,0x28,0xc0,0x3f,0xa4,0xff,0x66, + 0xd5,0x86,0x03,0x90,0xc1,0x0d,0xb5,0xe2,0xcf,0x4a,0x03,0x70,0x1e,0xdd,0xa3,0x89, + 0x8f,0x0a,0x01,0x37,0xff,0xe8,0x26,0xff,0xd0,0x20,0x64,0x48,0x2a,0xad,0x84,0x5c, + 0x58,0x26,0x0b,0xea,0x3f,0x70,0xd0,0x3a,0x7d,0xfb,0xd4,0x13,0x77,0xd5,0x55,0x49, + 0x7d,0xac,0xb9,0xac,0x98,0x10,0x82,0xd6,0x3f,0xed,0xd0,0x7f,0x8a,0x44,0x35,0xbb, + 0x49,0x0d,0x76,0x84,0xe7,0x28,0x6b,0x07,0xd0,0xcf,0xf0,0x61,0x58,0x32,0x5a,0x13, + 0xf2,0x04,0x2c,0xd7,0x72,0xfc,0xa3,0x17,0x7d,0xc7,0x0a,0x42,0x4c,0xc1,0x9a,0x2f, + 0xba,0x36,0x89,0xa4,0xc0,0x43,0x4c,0x60,0x92,0x24,0x86,0x88,0xe2,0xf9,0xfc,0x13, + 0x35,0xf9,0x87,0x36,0xfd,0x51,0xb5,0x13,0x2f,0x20,0x86,0xd7,0xbc,0x21,0xf2,0xff, + 0x3d,0x7a,0xcc,0x12,0x46,0x1c,0xfa,0x0f,0x88,0x16,0xed,0x60,0xd0,0xd4,0xfa,0x56, + 0xa9,0x9e,0x35,0x47,0xf8,0x5d,0x82,0x08,0xaf,0x64,0xf5,0x9f,0x69,0xfc,0x73,0x5f, + 0x36,0x3e,0x1e,0xaa,0xff,0xec,0xb4,0xe3,0xf3,0x3f,0xec,0xad,0x33,0xf2,0x8f,0x01, + 0xe1,0x48,0x67,0x56,0xa8,0x3b,0x07,0xd8,0x8f,0x92,0xaf,0x13,0x02,0x37,0x88,0x7d, + 0x26,0xfd,0x87,0x16,0x8d,0x93,0x70,0x3f,0xaa,0x55,0x89,0xf1,0x7f,0x98,0xf0,0x8f, + 0xee,0x2c,0x44,0x2e,0xfd,0xc7,0xa4,0x9d,0xa7,0xf1,0x82,0x28,0x31,0xde,0x34,0xdc, + 0x24,0x85,0xc5,0x0e,0x85,0x4b,0xff,0x31,0x8a,0xb6,0x12,0x8b,0x24,0xff,0x20,0xac, + 0x40,0x23,0x46,0x18,0xf9,0x7a,0x8f,0x38,0x0b,0xff,0x24,0xd9,0x4b,0xf8,0x5c,0x74, + 0xe5,0x11,0xe9,0x1c,0xc1,0x9e,0x13,0xd0,0x84,0xc5,0x71,0xc1,0x5f,0x88,0x7f,0xf2, + 0x6e,0x1f,0x76,0x62,0xf6,0xa8,0xd1,0xa1,0x96,0x74,0xc4,0x67,0xe6,0x1f,0xda,0xd4, + 0xce,0xc2,0xf1,0x64,0x5d,0x54,0x4a,0x20,0x1f,0x7c,0x00,0xcd,0xad,0x62,0x15,0xbb, + 0x10,0xcf,0xc4,0x3f,0xb4,0xc9,0x0e,0x2b,0x4f,0x84,0x57,0xb4,0x0a,0xb4,0xfe,0x6c, + 0x27,0x15,0x86,0x4f,0x78,0x17,0xce,0xc6,0x3f,0x59,0xbd,0x91,0x74,0xf3,0x3e,0xfc, + 0x04,0x15,0x5a,0xe9,0x3f,0xe4,0xd6,0x7f,0xb8,0x5c,0xf7,0x17,0x0f,0x80,0x4f,0x15, + 0xaa,0x2a,0x44,0x02,0x42,0xa4,0x62,0x57,0x79,0xb8,0x42,0xfc,0xb3,0x29,0xe7,0xaf, + 0x79,0xff,0x45,0xf8,0x67,0x9c,0x84,0x25,0x40,0x1a,0x71,0x81,0xfb,0xaf,0xbf,0xb0, + 0xfd,0x7d,0xdb,0xd0,0x7f,0xa4,0x34,0x71,0xfc,0x92,0x01,0x42,0x0e,0xfe,0x71,0xdc, + 0x7f,0x5d,0x84,0x77,0xac,0xf9,0x6f,0xc0,0xd5,0x86,0x81,0x8f,0x43,0x4b,0x54,0x7a, + 0x9f,0xad,0x47,0xc7,0x0b,0xf0,0x0f,0xd7,0x65,0x42,0xce,0xb8,0xc1,0x3f,0x42,0x0c, + 0xe9,0xc8,0x18,0xe1,0x91,0x02,0x5d,0xf9,0xfc,0xc3,0x13,0xfe,0xd9,0x65,0xd1,0xce, + 0x76,0xc6,0xa7,0xce,0x95,0x63,0xc7,0xa8,0xbf,0xed,0x42,0x15,0x29,0xbc,0x1d,0x2e, + 0xfd,0x87,0xf0,0xcf,0x76,0x8b,0x76,0x1e,0x01,0xef,0x8d,0xc2,0xc3,0x46,0x60,0x83, + 0x74,0x9a,0xcf,0x7a,0xe4,0xe4,0x9f,0x61,0x6b,0xff,0xc7,0xe0,0x68,0x64,0x85,0x89, + 0x31,0xc6,0xb6,0x1f,0x16,0x7c,0x70,0xdc,0xa5,0xff,0x30,0x7d,0x0e,0xda,0xe9,0xa5, + 0xf7,0x65,0xec,0x70,0x76,0x44,0x28,0xa4,0xff,0xc8,0x36,0x6d,0x9e,0x96,0x53,0xd0, + 0x08,0x7f,0x49,0xef,0x97,0x53,0xc6,0x8d,0x64,0x2e,0xfe,0x4e,0xfe,0x69,0x50,0xb2, + 0x90,0x33,0xc9,0x3d,0xa8,0x53,0xfd,0xc7,0xd3,0x80,0x76,0xc0,0x92,0x1e,0x0f,0x25, + 0xc6,0x0f,0xdd,0xfc,0xf3,0x57,0x4a,0xf6,0x50,0xbc,0x11,0x8d,0x0f,0x19,0x85,0x5a, + 0xa4,0xdf,0x4f,0xd0,0xc9,0x5f,0x13,0x67,0xe4,0x1f,0x7a,0x48,0xd3,0x68,0x27,0x57, + 0xab,0x91,0xd3,0x57,0x45,0xde,0x5f,0xc8,0xfc,0x1f,0xa3,0x79,0x96,0x90,0x9b,0xcf, + 0x3f,0x06,0xe4,0x8c,0xc2,0x6b,0xf8,0x86,0xa8,0x70,0x89,0x9d,0x0f,0xaf,0x75,0xac, + 0x4a,0x06,0xd6,0x0b,0xf3,0x0b,0xf1,0x4f,0x7f,0xae,0x89,0xff,0x91,0x23,0xc6,0x33, + 0x66,0x7f,0xc7,0x65,0x7b,0x0a,0xf2,0x4f,0xf5,0x17,0xc6,0xb7,0x35,0xc8,0xb2,0x17, + 0xc8,0x6b,0xfb,0x52,0xbd,0x6d,0x2b,0x6d,0x5b,0xf4,0xfe,0xeb,0xfd,0x5c,0xff,0x72, + 0xf2,0x4f,0xaf,0xfa,0x1b,0xb2,0xc9,0x72,0xb2,0x7f,0x52,0x76,0x96,0x6b,0x9e,0x2d, + 0x16,0xcf,0xdc,0x1c,0xab,0x2a,0xc4,0x3f,0xbd,0xd9,0xb7,0xb3,0x8a,0x0c,0x3c,0x2e, + 0xd7,0x86,0xf9,0x0c,0x2d,0x53,0xdc,0x62,0x5c,0xba,0x35,0x57,0xaf,0x9c,0xfc,0x93, + 0x82,0x87,0x4c,0x35,0xe3,0x28,0xc4,0xa3,0xbe,0x34,0x09,0x63,0xb6,0xbf,0xd7,0xe7, + 0x1a,0xbd,0x83,0x7f,0x8a,0xfa,0xad,0x26,0xa2,0xc3,0x7e,0xb5,0x4e,0x17,0x3f,0x5b, + 0x9b,0x2d,0x9b,0x83,0xb9,0xfe,0xe5,0xb8,0xff,0x22,0xb5,0xc3,0x1c,0xbc,0xf6,0xb4, + 0xf2,0xa5,0xfa,0x1f,0x61,0x69,0x20,0x3e,0x9e,0x1d,0x89,0x17,0xe2,0x1f,0x92,0x22, + 0x9f,0x58,0xfd,0xee,0x2d,0x58,0x16,0x25,0x46,0x3d,0x2d,0xe3,0x03,0x65,0xed,0x6c, + 0x33,0x9e,0x82,0xab,0xa7,0xf3,0x4f,0x07,0xf7,0xed,0x70,0xb6,0x49,0xbd,0xc2,0x75, + 0x6b,0xde,0x8d,0x02,0xbd,0x38,0x36,0x14,0x89,0x44,0xae,0xff,0xea,0x0e,0xfd,0x47, + 0x51,0xb2,0xea,0xc4,0x19,0xa5,0x7b,0xbb,0x97,0x1a,0x4f,0xd3,0x69,0x6a,0x76,0xfe, + 0xc2,0x7c,0xfe,0x01,0x43,0xfd,0x98,0x1b,0x22,0x41,0xa3,0xef,0x5f,0xa4,0x3f,0x76, + 0x19,0xc4,0x28,0xc8,0xdf,0xe6,0x0a,0xf0,0x8f,0x18,0x95,0xcf,0x5b,0x4e,0xbd,0x0e, + 0x87,0xd4,0x75,0x99,0x35,0x49,0xea,0x26,0x94,0x6d,0x31,0xfa,0xcb,0x8a,0x3c,0xfe, + 0xf9,0x4e,0xc2,0x52,0x33,0xd2,0x9e,0xcf,0x09,0x9a,0x10,0x63,0x8b,0x9b,0x7f,0xdc, + 0xf7,0x5f,0x93,0xec,0xbd,0x70,0x39,0xb6,0x4c,0x27,0xa0,0x78,0xaf,0x8b,0x9f,0xf3, + 0xef,0xbf,0x82,0xa7,0x09,0xe4,0x04,0x61,0x10,0x7b,0xe9,0xf7,0x7f,0x6c,0xec,0xc9, + 0xdd,0x7f,0x39,0xea,0x8f,0xdd,0x8f,0xda,0x60,0x10,0x91,0xf3,0x05,0xa8,0xad,0x00, + 0xef,0xe5,0xe9,0x3f,0x24,0x68,0xc5,0x01,0x18,0x1c,0x5e,0xa4,0x91,0xf5,0x03,0x2e, + 0xfe,0x74,0xdc,0x7f,0x55,0x67,0x3f,0xf4,0xd0,0xd5,0x9b,0xe5,0x0c,0x6e,0xd4,0xa4, + 0xbe,0x92,0xcd,0xd3,0xf9,0x50,0x28,0x70,0xff,0x65,0x44,0x83,0xa0,0xf1,0x0b,0x9a, + 0x84,0x4b,0x2e,0xcf,0x7e,0xff,0x45,0x16,0x69,0xa4,0xc7,0x70,0x02,0xc6,0x55,0x62, + 0x3c,0x97,0x4b,0x4b,0x3b,0xdf,0x1c,0xfc,0xc3,0x99,0xbb,0x5d,0xfb,0x32,0x9a,0xa8, + 0x1a,0xd4,0x48,0x3e,0xcc,0x29,0xb0,0x7f,0x27,0xff,0xd0,0x68,0x90,0xb0,0x34,0x91, + 0x68,0x24,0x65,0x5e,0x13,0x50,0xb6,0xec,0x14,0xbe,0xff,0x72,0xf0,0xcf,0x29,0xe6, + 0xf9,0x74,0xad,0xde,0x1d,0xc9,0x61,0x80,0xad,0x87,0x9c,0xcc,0xd3,0x7f,0x1a,0x4c, + 0xb5,0x47,0xa7,0x86,0x8f,0x15,0xf3,0xbe,0xff,0x53,0x40,0xff,0xd1,0x0c,0xec,0xf9, + 0x94,0x46,0xe3,0x34,0xeb,0x8e,0x4f,0x41,0xfe,0x99,0x80,0x0c,0xcd,0x46,0xcc,0xba, + 0xe3,0x53,0x90,0x7f,0xe8,0xdb,0x13,0xfd,0xfe,0x0f,0xda,0xeb,0x7a,0x9f,0x2a,0xc4, + 0x3f,0xc5,0xa7,0xe0,0x17,0xda,0x02,0xdd,0x53,0x53,0xc0,0xdf,0x82,0xfc,0x33,0xc2, + 0x3f,0x8b,0x15,0x4d,0x08,0xc4,0x7a,0x5c,0xf9,0x56,0x90,0x7f,0xc6,0xe1,0x33,0x7c, + 0x37,0x2e,0x1f,0x43,0xfe,0xdc,0xc8,0xcc,0xfa,0x4f,0xa7,0xf5,0xf6,0xdd,0xc1,0xba, + 0xbf,0x0f,0xe3,0xe6,0x1f,0xa6,0x97,0xf6,0x3b,0x8d,0xf4,0x47,0xf9,0xfa,0xd9,0xf5, + 0x9f,0xac,0xc8,0xb0,0xcb,0x50,0x1b,0xbc,0x6a,0xb7,0x03,0x63,0x0a,0xe9,0x3f,0x9c, + 0xf9,0xb4,0xd4,0x78,0xca,0x2f,0xa4,0x7f,0xd1,0xc7,0xcc,0xfc,0xfd,0x1f,0x3e,0xfb, + 0xfd,0x1f,0x52,0x7f,0xa8,0xfa,0x01,0xaa,0x50,0xe3,0x71,0xeb,0x21,0x0e,0xfe,0x29, + 0x35,0xf5,0x9f,0x32,0xd3,0xbb,0x15,0xcc,0x4e,0x2c,0x28,0x2e,0x7f,0x3f,0xce,0xf1, + 0x4f,0xb5,0x43,0xcd,0x78,0x99,0x18,0x3b,0xdf,0x2e,0xa0,0x6f,0x38,0xf9,0x27,0xcb, + 0x03,0x69,0x96,0xde,0x7f,0x11,0x63,0x34,0xee,0x73,0xeb,0x45,0x6e,0xfd,0xc7,0x50, + 0x7b,0x48,0xe9,0x11,0x3a,0x67,0xd5,0x7f,0x80,0x1b,0x76,0x79,0xd7,0x5a,0x40,0xef, + 0x2a,0xa0,0xff,0x64,0xa3,0xb7,0x7b,0xd6,0xef,0xff,0xec,0xaf,0xea,0x9b,0xee,0xdd, + 0xba,0x3d,0xdd,0x1b,0x0d,0xd9,0xc7,0xb1,0x7f,0xe4,0xba,0xff,0xca,0xce,0xef,0x27, + 0x86,0xcc,0xf6,0xb9,0xe2,0x53,0x90,0x7f,0x68,0xb4,0x1b,0x41,0x8a,0xb3,0x49,0x57, + 0xfc,0xf3,0xef,0xbf,0x48,0xb7,0xd2,0x09,0x84,0x3c,0xa6,0x12,0xfe,0x19,0x47,0xfe, + 0x2b,0xeb,0x3f,0x9a,0xf0,0xff,0xec,0x5d,0x6f,0x70,0x1c,0x45,0x76,0xef,0x9d,0x1d, + 0xcb,0x63,0x69,0xa5,0x1d,0xdb,0x12,0x25,0x62,0xe3,0x5b,0xaf,0x05,0xa7,0xa3,0xd6, + 0x6b,0x59,0x0a,0x3e,0xfe,0x08,0x69,0x2c,0xa8,0x94,0x8c,0x55,0xe5,0x2d,0xc2,0x07, + 0x92,0xa2,0xa8,0x2d,0xca,0x1f,0x9c,0x2a,0x1d,0x51,0x25,0xf9,0xe0,0xba,0x23,0x66, + 0x2c,0x0b,0x22,0x63,0x5d,0xd0,0x01,0x97,0x38,0x09,0xa1,0xd6,0x2e,0x7f,0x30,0x57, + 0xae,0x8a,0x64,0x63,0x63,0xd9,0x17,0xdd,0x58,0x08,0x4e,0x18,0x63,0x94,0x40,0x11, + 0x03,0x2e,0x6e,0x21,0x22,0x27,0x40,0xe7,0x08,0x63,0x1b,0xdb,0xc8,0x76,0xba,0x7b, + 0xa6,0xbb,0x5f,0xcf,0xf4,0xec,0x8e,0x8f,0x4a,0x8a,0xaa,0xa0,0x4f,0xaf,0x76,0xbb, + 0xd6,0xd3,0xcf,0x33,0xef,0xfd,0xe6,0xf7,0x7e,0xef,0x75,0x0a,0x3f,0x1d,0x43,0x0e, + 0x0e,0x44,0x4b,0xb5,0xe0,0xf3,0x72,0xdc,0x5f,0xff,0x72,0xfe,0x89,0x3c,0xad,0x3f, + 0x77,0xf0,0xf3,0xeb,0x28,0xf8,0x93,0x69,0x58,0xff,0x72,0x41,0x4e,0x67,0xfc,0x43, + 0xfd,0xbc,0x7d,0x07,0x36,0x16,0xbf,0x60,0x96,0xe5,0x7f,0xdc,0xfa,0xd7,0x8d,0x31, + 0x6c,0x20,0x95,0xfe,0x47,0x63,0xfe,0xb1,0xe6,0x5d,0xb5,0x68,0x92,0xda,0x14,0x6b, + 0xb3,0xae,0xd8,0x3f,0x9c,0x4a,0x9e,0x52,0xf0,0x3f,0x93,0xb5,0x3e,0xfe,0x87,0x5c, + 0xe4,0x52,0x74,0x90,0xc4,0x9f,0xfc,0xb6,0x87,0x4a,0xd4,0xbf,0x6c,0xf4,0xbc,0x49, + 0x3f,0xb4,0xb4,0xa5,0xb1,0x83,0xe8,0x66,0x67,0xc9,0x03,0x8a,0x78,0x25,0xd5,0xbf, + 0x3c,0x7f,0x56,0x24,0xd0,0xb0,0x91,0x72,0x96,0xd4,0x0b,0x37,0x72,0xe3,0x3d,0x5f, + 0xfd,0x8b,0xee,0x37,0x83,0x2e,0xd9,0x38,0x7e,0xf6,0xc5,0xf7,0x05,0xf4,0x2d,0xc7, + 0x01,0x1f,0xee,0x39,0x61,0x0f,0xfe,0xf6,0x52,0x0e,0x1b,0x83,0x55,0xdd,0x01,0xff, + 0x4c,0xf9,0xf9,0x1f,0x22,0xe3,0x9c,0x23,0xef,0x23,0xc4,0x9f,0xad,0x81,0x78,0x2e, + 0xf0,0xd2,0x31,0xbd,0xdb,0x4d,0x52,0x7b,0x7a,0x67,0xf4,0x11,0x1b,0x27,0xb2,0x81, + 0xa7,0x82,0xf9,0x0b,0xd4,0xbf,0xbc,0x7c,0x87,0x6f,0xaa,0x19,0x34,0xd2,0x8f,0x8d, + 0xbd,0x8a,0x7c,0x17,0xe0,0x7f,0xdc,0xfb,0x0d,0x1b,0xc7,0x28,0xde,0x2e,0xc1,0xff, + 0x18,0x5e,0x36,0x19,0x24,0xfb,0xd5,0xa8,0x91,0x09,0xd4,0x43,0x8b,0x7e,0xfe,0xc7, + 0x49,0x16,0xe3,0x73,0xc6,0x79,0xb6,0xf1,0x48,0xf8,0xe7,0x2a,0xc2,0xf7,0x4f,0x11, + 0x7f,0xcb,0xef,0x9f,0xb9,0xd4,0x5b,0x21,0xf5,0x2f,0x02,0x72,0x66,0xec,0x11,0x82, + 0x7f,0xae,0x70,0xfc,0xb3,0xe8,0x4d,0xed,0x0d,0xaf,0xfe,0x55,0xc1,0xeb,0x5f,0xf3, + 0xba,0x0c,0xb6,0x3b,0xfc,0xa2,0xd1,0xe0,0xc0,0xfd,0x8e,0xef,0x7e,0x36,0xa4,0xfe, + 0xe5,0x7a,0x0f,0xff,0xbe,0x43,0x85,0x40,0xde,0x27,0x53,0x69,0x0f,0x9a,0xce,0x0a, + 0x7c,0x52,0x07,0xf3,0xaf,0x4d,0xd1,0x60,0x26,0xc6,0xdc,0x62,0x7d,0x10,0x52,0xff, + 0x92,0xbc,0xc1,0x8d,0x0b,0x5a,0x98,0xfe,0xd9,0xa9,0xe1,0xde,0x6e,0xda,0x26,0xf2, + 0x7b,0xca,0x83,0xee,0x5f,0x48,0xf5,0xaf,0xcf,0xf9,0xff,0xbe,0x99,0x75,0x76,0xcc, + 0x8a,0xeb,0x3f,0xc3,0xf8,0x9f,0x0b,0x81,0xfa,0x97,0x8b,0x76,0x2c,0xec,0x8d,0xdb, + 0x84,0x7f,0x3e,0x61,0xfc,0xcf,0x2c,0xcf,0x77,0xa4,0xfe,0x25,0x57,0x7f,0x00,0x0d, + 0xf2,0x2e,0xe3,0x7f,0xe6,0xb8,0xfe,0x73,0x9d,0x91,0xb0,0xbe,0x74,0xd5,0x3e,0x04, + 0xed,0x2c,0x25,0x68,0x87,0xe1,0x9f,0x7b,0xc6,0x53,0x9c,0xff,0x61,0xeb,0xad,0x1b, + 0x81,0x7f,0x08,0x90,0x7e,0xfa,0xfc,0x0e,0xee,0x1f,0x4e,0x24,0x4e,0xf2,0xf8,0xf0, + 0x0b,0x88,0x7f,0x2e,0xa3,0xe6,0x63,0xc9,0xfd,0xf1,0x19,0x71,0x7f,0x7a,0xfe,0x19, + 0x13,0xf8,0xe7,0x67,0x52,0xb4,0x3c,0x28,0x85,0x91,0xd3,0xf8,0x55,0xeb,0x0e,0x8a, + 0x7f,0x38,0xbe,0xb2,0xad,0x17,0x0c,0x80,0x76,0x96,0x17,0xab,0x7e,0x5c,0xc1,0x61, + 0xcf,0x49,0xcd,0xdb,0xef,0x84,0x0a,0xff,0xcc,0xa0,0x03,0x76,0x83,0x78,0xac,0x76, + 0x60,0x23,0xed,0x51,0x91,0xef,0x23,0x35,0xfe,0x31,0x9b,0x25,0xd8,0x73,0x09,0x1d, + 0x67,0xf8,0x87,0x5d,0x3f,0xa8,0x7f,0x61,0x23,0x27,0xa7,0x21,0x22,0x84,0xbe,0xd3, + 0xc5,0x3f,0xec,0xfa,0x01,0xff,0x43,0x68,0x81,0x66,0x2b,0xf9,0x07,0xb4,0x3e,0x02, + 0x89,0x02,0x82,0x7f,0xd8,0xf5,0x03,0xfe,0x67,0x0a,0x6d,0x37,0x88,0xfe,0xb9,0x43, + 0xe0,0x9f,0xd4,0xf6,0x12,0xfc,0xcf,0x14,0xe5,0x7f,0xd6,0x03,0xbc,0x34,0x6e,0x7a, + 0xeb,0x4f,0xf2,0xfb,0x0d,0x09,0xfe,0xe7,0x55,0xfc,0x72,0x48,0xf5,0xcf,0xe2,0x13, + 0xcd,0xe3,0x43,0x8e,0xcf,0x63,0xcb,0x41,0xfd,0x8b,0xf3,0x3f,0x04,0xff,0xac,0x61, + 0x9f,0xf8,0xf8,0x9f,0x53,0x37,0x89,0xfd,0x6a,0xe7,0xd1,0x28,0xc6,0x03,0x22,0xad, + 0x9f,0xf7,0x8c,0xc5,0xfe,0xfa,0x97,0xa7,0x8e,0x3e,0x4f,0xd4,0xd1,0x93,0xdb,0xf8, + 0x27,0xef,0xa2,0x00,0xff,0xb3,0xd9,0x2c,0xea,0x00,0xed,0xec,0x26,0xf8,0x87,0xc3, + 0x9e,0xff,0xb4,0x19,0xff,0xc3,0xe3,0x8f,0x01,0xea,0x5f,0xa9,0x11,0xbb,0x51,0x02, + 0x42,0xaf,0xa6,0xb6,0x32,0xfd,0x33,0xf3,0xbf,0x84,0x7f,0x8e,0x12,0x3e,0x8d,0x18, + 0x77,0xb8,0x08,0x93,0xfb,0xf3,0x35,0xbe,0xbe,0x50,0x07,0xae,0x9f,0xa8,0xbb,0xe7, + 0x03,0x18,0xf3,0x5b,0x27,0xc0,0xff,0x4c,0x4b,0xfc,0x8f,0xc3,0x8c,0x98,0xe7,0x31, + 0xef,0xab,0xb3,0x21,0xf8,0xc7,0x6e,0x8e,0x6d,0x80,0xf7,0x9b,0xed,0xf9,0x7f,0xcc, + 0x57,0xff,0xf2,0xd0,0xce,0x21,0xb4,0xdb,0x05,0x42,0xde,0x27,0x97,0xd0,0x53,0xa1, + 0xf8,0xa7,0xc9,0x3c,0xa1,0xef,0x27,0xef,0x0b,0xb7,0xf7,0xf2,0x27,0xe8,0x24,0x6b, + 0x54,0x79,0x43,0xc5,0xff,0x9c,0xb6,0x47,0x0d,0x82,0x1f,0x7a,0xc9,0xf3,0x5b,0x4d, + 0x19,0xa1,0x94,0x57,0xc8,0x2e,0xf2,0xf8,0xb0,0xb7,0x7f,0x19,0x43,0x3b,0xbf,0xb1, + 0x2f,0xd8,0xab,0x89,0xfe,0x99,0xcb,0x7e,0x3e,0xb4,0x7e,0xed,0x7e,0xf5,0x71,0x50, + 0xff,0xe3,0xc6,0x93,0x36,0xe7,0xe9,0x02,0x12,0x69,0x4e,0x63,0xf8,0x47,0xbc,0xff, + 0x32,0xfc,0x83,0xf3,0x97,0x79,0xce,0x6e,0x29,0x56,0xfd,0x49,0x95,0x9b,0xbf,0xde, + 0xba,0xb8,0xe2,0x02,0x6b,0xe4,0x11,0xfc,0x8c,0xa7,0xff,0x71,0xa3,0xcd,0x41,0x13, + 0x5f,0x7f,0x2e,0xce,0x77,0x74,0xca,0xf2,0xae,0xff,0xb3,0x0a,0xb6,0x1e,0x39,0x4b, + 0x0d,0xbe,0xfe,0x97,0x68,0x17,0x5e,0x2f,0xf0,0xde,0xbb,0xac,0x70,0x1f,0xa8,0x7f, + 0xb9,0x61,0x67,0x88,0xf8,0xd3,0x04,0xf9,0x9d,0xc5,0x73,0x11,0xaf,0xf6,0xd6,0xf1, + 0xfd,0xce,0xa1,0xb3,0x6e,0xff,0x08,0xcf,0x2f,0x6f,0xb2,0xf8,0xf9,0x99,0xbf,0xfe, + 0xe5,0xf9,0x27,0x35,0x4a,0xd6,0x0b,0xff,0x30,0x61,0x86,0x54,0xff,0x32,0x78,0x3c, + 0xbf,0x8a,0x7e,0xe8,0x24,0x1d,0x28,0xf3,0x78,0xcb,0x35,0x26,0x00,0xff,0xd3,0x2d, + 0xf2,0xef,0x11,0xfb,0x56,0x67,0xc7,0x40,0x2f,0xd7,0xff,0x14,0xd1,0x8e,0x79,0xf4, + 0xab,0x69,0xa8,0xff,0x81,0xeb,0x6f,0x71,0x76,0xf4,0x6b,0x33,0x31,0x96,0xaf,0xcd, + 0x1d,0xa1,0xf8,0x87,0xf8,0xe7,0x08,0x89,0xc6,0x68,0x11,0xd7,0xff,0x4c,0x33,0xff, + 0x8c,0xf1,0xf8,0x83,0x7e,0x0a,0xd0,0xdd,0x11,0x74,0x83,0xf3,0x34,0xdb,0x6f,0xd5, + 0x10,0xce,0x47,0xc4,0x3f,0x1b,0x86,0x16,0x3b,0x42,0xff,0x53,0x0d,0xd2,0x3a,0xed, + 0xdf,0x71,0x54,0xf8,0x67,0x2b,0xf3,0x27,0xc7,0x3f,0x13,0xf1,0xab,0xfa,0xb5,0x86, + 0x16,0x09,0x36,0x87,0xf3,0x3f,0x84,0xf6,0x39,0x83,0x0e,0x4f,0xa6,0x25,0xda,0x27, + 0x9c,0xff,0xb1,0xaa,0x1a,0xb5,0x13,0xd8,0x2d,0x29,0x09,0xe6,0x85,0xf3,0x3f,0x39, + 0x82,0xaf,0xf0,0x6b,0x6c,0x5a,0x82,0x91,0xe1,0xfa,0x9f,0x9e,0x64,0x3f,0x71,0x4b, + 0x47,0xb3,0x04,0x0b,0x39,0x7e,0x0e,0xd4,0xbf,0x72,0x14,0x16,0xce,0x99,0xbf,0x52, + 0x03,0x21,0x3f,0xff,0x83,0x83,0x12,0xfe,0x7d,0xfd,0x27,0x56,0x88,0xde,0x0c,0xd6, + 0xbf,0x32,0x2e,0xfb,0xb7,0x13,0xdf,0xa8,0xc3,0xbe,0xcb,0x0e,0xe5,0x7f,0x48,0x5b, + 0x9c,0xc2,0x2d,0xa5,0xf8,0x9f,0x07,0x31,0x1e,0x38,0xe8,0xa3,0x41,0x42,0xf9,0x1f, + 0x0c,0x72,0x4c,0x82,0x7f,0xac,0xd6,0x09,0x48,0xfb,0x84,0xf3,0x3f,0xc8,0x85,0xcd, + 0x66,0x08,0x50,0x0c,0xf0,0x3f,0xc5,0xc4,0xa0,0xc2,0x2d,0x25,0xf8,0x1f,0x23,0x47, + 0xe2,0x8f,0xef,0x35,0x2a,0x94,0xff,0x59,0x55,0x34,0x1e,0xec,0x08,0x6e,0x33,0x9c, + 0xff,0xb9,0xdf,0xb8,0x01,0x7b,0x6f,0xd8,0x0e,0xf1,0xa7,0x9f,0xff,0x69,0x2f,0x24, + 0x66,0x30,0xec,0xb9,0x9a,0xc8,0xda,0x4f,0x03,0xfc,0x43,0x8c,0xac,0x92,0xff,0xd1, + 0xff,0xc5,0xa5,0x7d,0x6a,0x64,0xfc,0x53,0xa2,0xfe,0xf5,0x0c,0x4e,0x73,0x5f,0xe8, + 0xcd,0x6b,0xe1,0x6b,0x7e,0xb8,0xfe,0x87,0xb1,0x0d,0xbb,0x25,0xda,0xa1,0xa4,0xfe, + 0xa7,0xd4,0x7a,0x75,0xfd,0x0b,0x0d,0xc7,0x82,0xfd,0x5f,0xe1,0xfa,0x1f,0xb2,0xbb, + 0x66,0xf5,0x7e,0x41,0xfd,0x8b,0xe2,0x9f,0xbb,0x29,0x9f,0xa3,0x5f,0xb3,0xe4,0x6d, + 0x2a,0xf9,0x1f,0xd2,0xff,0xd5,0xb6,0x36,0x81,0xd7,0x9b,0x97,0x8c,0x66,0xf5,0xfa, + 0xa0,0xfe,0xc7,0x20,0x32,0x6c,0x8a,0x7f,0xd4,0xfd,0x5f,0x72,0xfd,0x2b,0x4b,0x64, + 0x06,0x64,0x77,0xa1,0xfb,0xf5,0xf1,0x3f,0x1d,0x8d,0xae,0x8c,0x3c,0xbd,0x56,0xed, + 0x4f,0x49,0xff,0x83,0xaf,0x3f,0x97,0x78,0x8e,0xc0,0x36,0x2b,0xe4,0xfa,0x03,0xf5, + 0xaf,0x75,0xee,0xfd,0x50,0x08,0xf1,0x4f,0x80,0xff,0x31,0x5d,0x6f,0x5b,0x21,0xfe, + 0xf7,0xeb,0x7f,0x32,0x6e,0x91,0xf2,0x08,0xc1,0x3f,0x80,0xf6,0x29,0xc5,0xff,0xb8, + 0x34,0x45,0xea,0x98,0xf2,0x79,0x51,0xe1,0x1f,0x0c,0x7b,0x0e,0xa0,0xe5,0x4e,0x99, + 0xfe,0x2f,0x5e,0xff,0xc2,0xb0,0xc7,0xf8,0x8a,0xe0,0x1f,0x40,0xfb,0x94,0xe2,0x7f, + 0x4a,0xc6,0x13,0xbf,0xfe,0xa7,0x7d,0x2a,0x79,0x4a,0xdb,0x62,0xfd,0x6a,0xf0,0x80, + 0x3a,0x7f,0x05,0xf4,0x3f,0x04,0xf6,0x3c,0x84,0x5e,0x6e,0x5a,0xad,0x8e,0x3f,0xb2, + 0xfe,0x87,0x14,0xf5,0x96,0x4c,0x6a,0x18,0x08,0x69,0x37,0xb3,0x65,0xb2,0xde,0x3b, + 0x80,0x7f,0xce,0x2e,0xa9,0xad,0xe8,0xd2,0x0f,0x0c,0x86,0xe4,0x3b,0x59,0xff,0xf3, + 0x39,0x6a,0x1b,0x4b,0xd6,0x12,0xd8,0x63,0x91,0xf7,0x77,0x6d,0xc6,0xad,0x38,0xa8, + 0xfb,0xbf,0x20,0xfe,0xf9,0x3a,0x15,0xe2,0x9f,0x80,0xfe,0x87,0xe8,0xeb,0x5a,0x71, + 0xb4,0x6f,0x51,0xc7,0x73,0x27,0x88,0x7f,0x06,0x35,0x92,0x88,0x49,0xfe,0xed,0x50, + 0xe8,0x99,0x03,0xf8,0xa7,0xd2,0xad,0x76,0x85,0xe4,0x6b,0x05,0xfe,0x31,0x29,0xcd, + 0x58,0x0c,0xc3,0x03,0xdc,0xfd,0xae,0xfe,0xc7,0xa9,0x19,0xa4,0xb0,0xd0,0x9f,0xdf, + 0xc3,0xf4,0x3f,0x4e,0x32,0xa7,0xd8,0x66,0x39,0xfe,0xe7,0x1a,0xe1,0x7f,0x88,0x0c, + 0x86,0xf7,0x7f,0x05,0xf8,0x1f,0xdb,0x0c,0xa0,0x9d,0x8e,0x6b,0x96,0xab,0x08,0x4a, + 0xcf,0xd8,0xa4,0x11,0xbe,0x26,0xa4,0xfe,0xc5,0x8d,0x81,0xd8,0xb3,0x8c,0x11,0xda, + 0x16,0x82,0x7f,0x7c,0x6e,0xac,0xf2,0x0c,0x93,0x94,0x1a,0x2b,0x15,0xf8,0x87,0x79, + 0x63,0x8d,0x6b,0x30,0xbd,0x9c,0xf9,0x46,0x09,0xfd,0x0f,0xf1,0xc6,0xf7,0x22,0xe2, + 0x1f,0xc9,0xdb,0x99,0xd4,0x07,0x5a,0x19,0xfc,0x03,0xae,0x7f,0x3f,0x7e,0x5f,0x88, + 0x80,0x7f,0x80,0x7f,0x12,0xe8,0x59,0xce,0x60,0x94,0xaa,0x7f,0xa1,0x97,0xfb,0x56, + 0x7e,0x8c,0x8d,0x65,0x56,0x04,0xfc,0x83,0xd1,0x8e,0xfe,0xa5,0xd6,0x3a,0x9e,0x6c, + 0x5a,0x91,0xb0,0xde,0x2e,0x5b,0xff,0x12,0xde,0xe8,0x89,0x5f,0xb9,0xf7,0x1a,0x5a, + 0x15,0xa5,0xfe,0x75,0x14,0x6d,0xc1,0x68,0x5c,0xd0,0x3e,0x65,0xeb,0x5f,0x31,0xda, + 0x6d,0xfa,0xd3,0x12,0xfd,0xef,0x92,0xfe,0xe7,0xe5,0xde,0x95,0xc5,0x1d,0x9b,0x6f, + 0xf9,0xd0,0xfe,0x9b,0xbe,0xf2,0xf5,0x2f,0xaf,0xad,0x60,0x09,0xbe,0xdf,0xfc,0xf3, + 0x16,0x6e,0x09,0xa9,0x7f,0x31,0xa3,0x54,0xff,0xbb,0xc4,0xff,0xc4,0x68,0x21,0x2c, + 0x58,0x8f,0x50,0xea,0x7f,0xa6,0x5c,0x19,0x0c,0x11,0x8a,0xbc,0x1e,0x11,0xff,0xc4, + 0x68,0xff,0xf5,0x27,0xc6,0x7b,0x51,0xf1,0xcf,0xa3,0x6e,0xe1,0x6c,0x7b,0x44,0xfc, + 0xe3,0x1a,0x27,0x98,0x42,0xe6,0xd5,0x70,0xfc,0xc3,0xbb,0xbd,0x28,0xff,0xe0,0xef, + 0x3f,0xf2,0xe3,0x1f,0x79,0x77,0x9f,0x94,0xc1,0x3f,0xe0,0x5b,0xaa,0x17,0x3a,0x57, + 0x78,0x1d,0x5f,0x76,0x35,0xc4,0x3f,0xba,0x1f,0xff,0xb8,0x68,0x27,0x46,0x8d,0x8f, + 0xd0,0x29,0xf7,0x93,0x8f,0x6d,0xf7,0xab,0xd8,0xdf,0x4a,0xf8,0x87,0xed,0x77,0x01, + 0x35,0x9a,0xd2,0xe3,0x68,0x6b,0x2c,0x63,0x2d,0x30,0x49,0x47,0x58,0x78,0xfd,0xab, + 0xc2,0xf3,0xa7,0x2b,0x04,0x92,0xfd,0xf9,0x24,0x8f,0x0f,0x80,0xff,0x99,0xd2,0x2f, + 0x69,0x9e,0x9e,0xe7,0x75,0xb4,0x45,0xba,0xfe,0x69,0xe4,0xc3,0x3f,0x6c,0xbf,0xcb, + 0x98,0xb1,0xa5,0x7c,0xfd,0xab,0xe0,0x0d,0x22,0x10,0xb4,0x8f,0xc0,0x3f,0xfc,0xfe, + 0x97,0xf8,0x9f,0x23,0x5a,0xb6,0x70,0x1f,0xe9,0x67,0x7c,0xaa,0x3c,0xfe,0x69,0x72, + 0xcb,0x5e,0xe3,0x37,0x36,0xf5,0x72,0x9a,0x42,0xd4,0xbf,0x74,0x15,0xff,0x43,0x8c, + 0x62,0x55,0x8e,0xd2,0xb6,0x65,0xf1,0xcf,0xe6,0xf8,0x0b,0xd4,0xa8,0xde,0x14,0x3f, + 0x89,0x7e,0x5d,0x1e,0xff,0xd0,0xe8,0xa1,0xb5,0x3a,0x35,0x80,0xdf,0xb8,0x1a,0x8a, + 0x7f,0x00,0xda,0x39,0xb5,0xf8,0x02,0x7a,0xbc,0x3c,0xfe,0xa1,0x57,0xbb,0xf0,0x47, + 0x13,0x55,0x0f,0x78,0xfd,0xef,0x0b,0xc8,0x27,0xbf,0x75,0xbf,0xfa,0x5c,0xc2,0x3f, + 0x12,0x3a,0x5a,0x92,0x0f,0xf6,0xcb,0x87,0xf1,0x3f,0xd4,0x40,0x5e,0x7f,0xf7,0x02, + 0xd0,0xdf,0x14,0xd0,0x3f,0x83,0x68,0x09,0xf6,0x3b,0x57,0x0e,0xff,0x10,0xa3,0x6f, + 0x3e,0xf8,0xe4,0x73,0x35,0xfe,0xb9,0x8b,0x47,0xef,0x7c,0xd2,0x89,0x9f,0x67,0x61, + 0xfc,0xb1,0x12,0xf8,0xc7,0xcb,0x56,0x56,0xcd,0x80,0x36,0x65,0x97,0xc3,0x3f,0xb7, + 0x12,0xbd,0x0a,0xfd,0x76,0xa2,0x6a,0x27,0xfe,0xdf,0x8f,0x80,0x7f,0x3c,0xff,0x58, + 0x95,0xe6,0xa2,0x89,0x32,0xf8,0xe7,0xa8,0x84,0x06,0x6d,0xa1,0xf7,0xee,0x2e,0x81, + 0x7f,0xbc,0xfd,0x5a,0x35,0x4e,0x2c,0xd8,0xbf,0x03,0xf0,0x4f,0x9d,0x54,0xff,0xba, + 0xab,0x73,0x40,0xc9,0xff,0xc4,0xb8,0xff,0x21,0xfe,0x39,0x6c,0xa7,0xbb,0x8c,0x28, + 0xfc,0x4f,0xa3,0xbb,0xbb,0xfd,0xe8,0xd6,0x8e,0x46,0x35,0xde,0xe3,0xfa,0xe7,0x79, + 0x00,0xff,0x1c,0x46,0xe9,0xbc,0x51,0x86,0xff,0x81,0xf9,0xf7,0x52,0xae,0x31,0x9f, + 0x50,0xe1,0xc3,0x30,0xfc,0x63,0xb7,0xa3,0x72,0xf8,0x07,0x81,0xfb,0xf3,0xe2,0xbd, + 0x6d,0x56,0x02,0xe2,0x2b,0x05,0xfe,0xa9,0x03,0xf8,0x67,0xc8,0xc9,0x76,0x36,0x46, + 0xe4,0x7f,0x28,0x5f,0xea,0x36,0x0e,0x9c,0x60,0xf8,0xa7,0x8c,0xfe,0x07,0x1d,0x1a, + 0x5b,0xb9,0xa9,0x33,0x22,0xff,0x43,0xd0,0xce,0x6c,0x67,0x9b,0x95,0x21,0xc6,0xdb, + 0xee,0x20,0x20,0x15,0xfe,0xa9,0x16,0xfe,0x21,0xc4,0x69,0x67,0x34,0xfe,0xc7,0xf3, + 0x3f,0x8e,0xde,0x88,0xb9,0xa5,0xa6,0x3c,0xfe,0x79,0x09,0xad,0x44,0x46,0x14,0xfe, + 0xc7,0xdb,0xdd,0x41,0x7b,0x55,0xde,0x88,0xc4,0xff,0x78,0xfe,0xec,0xc8,0x9e,0x33, + 0xa2,0xf0,0x3f,0x1e,0xda,0xb9,0x5a,0x68,0x1f,0xcc,0xf8,0xf8,0x9f,0x10,0xfc,0xe3, + 0x96,0x21,0x3a,0xda,0xb4,0x0d,0x11,0xf9,0x1f,0x9a,0xdd,0x1a,0xb1,0xff,0xaf,0x87, + 0xff,0x69,0xa0,0x32,0xe6,0xeb,0xe0,0x7f,0xb2,0x9d,0xca,0xf5,0xa1,0xfc,0x4f,0x26, + 0xd7,0x78,0x5d,0xfc,0x4f,0x1b,0x1a,0x88,0xc2,0xff,0x78,0xbb,0xbb,0x12,0xbb,0x3b, + 0x17,0x81,0xff,0x11,0xeb,0x51,0x7b,0xce,0x88,0xc6,0xff,0x54,0x11,0x3c,0x30,0x4d, + 0x1a,0xe1,0xcb,0xf3,0x3f,0xee,0xa6,0x3a,0x88,0x91,0xcd,0x19,0x91,0xf8,0x1f,0xe2, + 0xb4,0x3d,0xb1,0x17,0x53,0xd9,0x0e,0xb5,0x3f,0xfd,0xfd,0x5f,0xee,0xd5,0x8e,0xac, + 0x6b,0xcd,0x25,0x22,0xf1,0x3f,0xde,0xb7,0xbd,0x6d,0x7f,0x11,0x8d,0xff,0xf1,0xbc, + 0x6d,0xb5,0x99,0x35,0x51,0xf8,0x9f,0xac,0xbd,0x83,0xa0,0x9d,0x51,0xb4,0xaa,0xdf, + 0x88,0xc8,0xff,0x90,0xa7,0x63,0xd8,0xc8,0xe4,0x2a,0x55,0xcf,0x8b,0x52,0xff,0x7c, + 0x1a,0x1d,0xd4,0x57,0x3a,0xca,0xe7,0x57,0x89,0x7f,0x3e,0x44,0xe7,0xed,0xd6,0x7c, + 0x4d,0x44,0xfe,0x87,0xc6,0x13,0x9d,0xf6,0x7f,0x95,0xe4,0x7f,0x40,0xfe,0xd2,0x5b, + 0x9f,0x59,0x9d,0xe2,0xf9,0xab,0x3a,0x14,0xff,0x7c,0xc5,0xaf,0x3f,0x77,0x9b,0xa1, + 0xba,0x7e,0x14,0xe8,0xff,0xf2,0xd6,0xc7,0xbf,0xaf,0x8e,0x57,0x70,0xfe,0x0f,0x05, + 0x39,0x2e,0x8d,0x36,0x6c,0x35,0x20,0x65,0xbe,0x83,0xfa,0xe7,0x7d,0xb4,0x48,0xe1, + 0x76,0x73,0x9f,0xba,0xa5,0x4f,0x99,0xbf,0x42,0xf0,0x0f,0xbe,0x5b,0x86,0xca,0xf1, + 0x3f,0xc8,0x0d,0xda,0x35,0xb3,0x54,0xff,0xd3,0x62,0x27,0xca,0xf0,0x3f,0xb5,0x02, + 0xff,0xe8,0xc3,0x63,0x8d,0x7b,0xfd,0xf9,0xeb,0x16,0x35,0xff,0xe3,0x7e,0x6b,0x3f, + 0x52,0xec,0x57,0xf2,0x45,0x12,0xfe,0xe1,0xd9,0x6d,0x44,0xbf,0xd5,0xf1,0xc7,0xe7, + 0x06,0x35,0xff,0xe3,0xed,0xb7,0xd9,0xc9,0x94,0xe1,0x7f,0x40,0xfd,0x4b,0x3f,0x7f, + 0x1d,0xfc,0xcf,0x29,0x57,0xf6,0x9c,0x4a,0x74,0xc6,0xdb,0xcc,0x08,0xf8,0x67,0x67, + 0x3c,0x8b,0x8e,0xf6,0x66,0x53,0x95,0x7b,0xa3,0xe9,0x9f,0x07,0xb5,0x2e,0x7c,0x63, + 0x64,0x71,0x42,0x50,0xe8,0xeb,0xe4,0xfe,0x2f,0x8f,0x7f,0xa3,0x8e,0x6d,0xaa,0x7c, + 0x4e,0x0b,0x30,0x42,0x1d,0x0a,0xfe,0xc7,0x8c,0x93,0x41,0x49,0xad,0xa9,0x2e,0x57, + 0x3f,0xb6,0x45,0x9a,0x0f,0xa0,0xc0,0x3f,0x9e,0x2c,0x0a,0x25,0x8b,0x02,0x06,0x87, + 0xf0,0x3f,0x1f,0xb8,0x7c,0x2c,0x7d,0x30,0x73,0x4a,0x7d,0x6f,0x38,0xff,0x63,0x55, + 0xa5,0x62,0xdd,0x62,0x7e,0x42,0xa9,0xfa,0x17,0x75,0x8b,0x8d,0xdf,0x17,0x82,0x7a, + 0xb0,0x90,0xfa,0x17,0x6d,0x84,0x9f,0xa9,0xa0,0x13,0x11,0xc9,0xd8,0x9f,0x50,0xfc, + 0x93,0x21,0xfe,0xc1,0xbf,0xaf,0x3d,0x86,0x36,0x98,0x71,0x57,0x11,0x14,0x82,0x7f, + 0x6e,0x82,0xfe,0x89,0x3d,0x6e,0x27,0xff,0x2d,0x1a,0xfe,0xf1,0xf8,0x6a,0x3b,0xd9, + 0x5f,0x5a,0xff,0x1c,0x63,0xfc,0x33,0x89,0x1e,0xda,0x4a,0xbb,0x2a,0xaf,0xd0,0x4f, + 0x02,0xfc,0x63,0xbe,0x20,0xed,0x97,0xcc,0x3b,0x8a,0xaa,0x7f,0xc6,0x46,0xf7,0x44, + 0x55,0xab,0xc2,0x9f,0xa1,0xfc,0x4f,0xbb,0x9d,0x2c,0xee,0x88,0xa4,0x7f,0x16,0xb2, + 0xe7,0x6d,0x45,0xb4,0x39,0x32,0xff,0x63,0x25,0x77,0x5e,0x4f,0xfd,0x8b,0x14,0x52, + 0xaf,0x0b,0xff,0x84,0xcc,0xeb,0x2b,0xc9,0xff,0x94,0xc4,0x3f,0xf3,0xf2,0x81,0x6c, + 0x5b,0x12,0xff,0x30,0x3c,0x30,0x19,0xf7,0x1a,0xdb,0x73,0x51,0xf1,0x0f,0x95,0x3d, + 0xaf,0xdd,0x30,0x49,0x85,0x34,0xe5,0xf1,0x8f,0x96,0xa2,0x46,0x0d,0x33,0x28,0xfe, + 0x99,0x0e,0xc5,0x3f,0x83,0x9e,0xec,0x59,0x18,0xe5,0xf0,0x8f,0xfb,0x1f,0x51,0x29, + 0xe9,0xcf,0x5f,0xa4,0x46,0x87,0x02,0xff,0xd4,0xbb,0x97,0x9d,0xab,0xfa,0x3b,0xc5, + 0xf5,0x2b,0xf0,0xcf,0xf3,0xae,0xec,0xb9,0x93,0x16,0xc2,0x22,0xeb,0x9f,0x43,0x8c, + 0x20,0xfe,0xf1,0xd0,0x4e,0x0d,0x19,0xd4,0x13,0x19,0xff,0x50,0x03,0xe8,0x7f,0x4a, + 0xe1,0x9f,0xcd,0xec,0x69,0xdd,0x18,0x0d,0xff,0xf4,0x28,0x60,0x4f,0x59,0xfe,0x87, + 0xf1,0xf9,0x65,0xeb,0x5f,0x24,0x49,0xb5,0xb1,0x44,0xa6,0xa8,0x7f,0xe9,0x10,0xff, + 0x78,0x43,0x0e,0x1f,0x22,0x6d,0x5c,0x44,0xd8,0x5c,0xba,0xfe,0xe5,0xed,0x77,0x56, + 0x11,0xa6,0x4a,0xf1,0x3f,0xb7,0xbb,0x6d,0x3e,0xef,0xa8,0xeb,0x5f,0x3c,0x3e,0x70, + 0xfe,0xe7,0x30,0x93,0x95,0x16,0x14,0xfa,0x8d,0xcf,0x83,0xfa,0x67,0xee,0x8d,0xbd, + 0x8b,0x5d,0x63,0xbe,0xfb,0x49,0x56,0x5d,0xff,0x9a,0xef,0x45,0xef,0x31,0x22,0x0c, + 0x96,0xe3,0xf9,0x86,0xd9,0x15,0x8e,0xe5,0xe7,0x7f,0xd6,0xf1,0x6c,0x55,0xe8,0x8d, + 0x52,0xff,0xa2,0xdf,0xd2,0x46,0xb0,0xc1,0x8a,0x19,0x23,0xb0,0x5e,0x67,0xf7,0x03, + 0xe3,0x7f,0xc4,0x74,0x29,0x44,0x0c,0xbd,0x5c,0xfd,0x0b,0xb2,0x5b,0x91,0xf0,0x4f, + 0x8f,0xaa,0xfe,0x15,0x2b,0x51,0xff,0x9a,0xbf,0x05,0xcd,0x99,0x2d,0x4d,0x89,0x88, + 0xfa,0x1f,0xca,0xff,0x58,0x69,0x5b,0xc9,0xff,0xcc,0x72,0xff,0x37,0xc2,0xfa,0xd7, + 0x90,0x99,0x36,0x94,0xef,0xe3,0xa1,0xfa,0xe7,0xdd,0x05,0x54,0x9a,0xff,0x41,0x74, + 0xfe,0xb0,0x87,0x2e,0x46,0xec,0xa6,0x66,0x5d,0xe9,0x1f,0x7e,0xfd,0xbb,0x4c,0xc0, + 0xff,0xe0,0xf8,0x6c,0xaf,0x52,0xe2,0x43,0x90,0x7f,0xc5,0xf3,0xa8,0x5f,0x4a,0xdc, + 0x99,0x52,0xe2,0x73,0xa1,0x7f,0x66,0xfd,0x5f,0x2e,0x7f,0x95,0x48,0xf7,0x29,0xf9, + 0x2b,0xa1,0x7f,0x76,0x20,0x1f,0x78,0xc4,0x4e,0x2d,0x54,0xbe,0x7f,0xcd,0xf2,0xdb, + 0x21,0x8f,0x20,0xff,0x63,0xaf,0x28,0x54,0xaa,0xf8,0x90,0x39,0xbe,0x5e,0xe2,0x7f, + 0xce,0xa2,0xc3,0x7a,0x8d,0x52,0xff,0x53,0xc1,0xd6,0x5b,0x4b,0x21,0x3f,0x66,0xfe, + 0xeb,0x13,0xd5,0x5f,0x28,0xf1,0x0f,0xdb,0xaf,0x01,0xf9,0x9f,0xaf,0xed,0x66,0xa4, + 0x8e,0x57,0x42,0xff,0x09,0xf9,0x1f,0xda,0x7f,0x51,0x9a,0xff,0x41,0x90,0xff,0x39, + 0xd0,0xbf,0xbc,0x49,0xa9,0xff,0x81,0xfa,0x67,0x10,0xcf,0xf7,0x5b,0xe9,0x07,0x95, + 0xf1,0xe7,0x7d,0x81,0x7f,0x74,0x86,0x7f,0x70,0xd0,0xbe,0x8a,0xbe,0x1c,0x4a,0x2a, + 0xf9,0x1f,0xf1,0xfb,0x52,0x3e,0xea,0x0c,0xc9,0x47,0x42,0x4f,0xeb,0xce,0x7f,0x16, + 0x7a,0xd7,0xdc,0x09,0x25,0xff,0xc3,0xd7,0xdb,0xba,0xc8,0xb6,0xe6,0x88,0x1d,0xc6, + 0xff,0xb0,0xf0,0xc3,0xfb,0xbf,0xf8,0x74,0xbe,0xfe,0x32,0xfc,0x4f,0x2d,0xc4,0x3f, + 0x56,0x26,0x8c,0x0f,0x61,0xbf,0xcf,0xfa,0xbf,0xe8,0xee,0x2e,0xa3,0x65,0xa4,0xed, + 0x3d,0xb8,0x5f,0xd1,0xff,0x75,0x18,0xf2,0x21,0xd7,0xac,0x76,0xeb,0x69,0xd5,0x7e, + 0xcf,0xf0,0xf8,0x73,0x7b,0x1d,0xf0,0xcf,0x5f,0x1b,0x2d,0x6a,0x3d,0xcc,0x19,0xfe, + 0xfc,0xd6,0x23,0xa0,0x7f,0xbe,0x88,0xd2,0xc6,0x12,0x15,0xff,0x23,0xf4,0xc9,0x96, + 0xde,0x07,0x76,0x67,0x14,0x3a,0x94,0x78,0xef,0xdf,0x63,0x6c,0x7d,0xbd,0xbe,0x07, + 0xa2,0x9d,0x74,0x88,0x9e,0x8a,0x3f,0xef,0xde,0xfc,0x43,0x8f,0xff,0x19,0x6c,0xc6, + 0xdf,0xaa,0xf8,0x1f,0x7e,0x3d,0xd3,0x52,0xff,0x97,0xdd,0xd6,0xa3,0xdc,0xef,0x65, + 0x81,0x67,0x10,0xb8,0xdf,0xa6,0xad,0x66,0xc4,0xfd,0x5f,0xad,0xc4,0x3f,0x86,0x0e, + 0xf0,0xcf,0xe8,0xe4,0x8a,0x5d,0x4a,0xfe,0x67,0x8c,0x3f,0x5d,0xc6,0xcf,0xc1,0xf3, + 0x32,0x82,0x52,0x5b,0x79,0x7c,0x86,0x81,0x28,0xd8,0xff,0x45,0x9f,0xd6,0x43,0xc6, + 0xf2,0x47,0x42,0xf8,0x10,0x76,0xbf,0x35,0xd6,0x73,0xfd,0xf3,0x87,0xfa,0xdc,0x93, + 0x2d,0x1f,0x25,0x18,0xec,0xa9,0x06,0xf8,0xe7,0x38,0x8f,0x3f,0x92,0xfe,0xf9,0x22, + 0x1a,0x2d,0xc7,0xff,0xe4,0xf5,0x51,0x91,0xad,0xe6,0xec,0x96,0x86,0xe4,0x25,0x45, + 0xfe,0x9a,0x14,0x7a,0x63,0x04,0xf4,0xcf,0x2f,0xd5,0x2f,0xef,0x52,0xc5,0x9f,0x45, + 0x9f,0x89,0xe7,0x51,0xf0,0x3f,0xcf,0xa3,0xe7,0xd0,0x72,0x6b,0x7d,0x4f,0x45,0x70, + 0xbf,0xaf,0x59,0xfc,0x7e,0xab,0x75,0xdf,0xee,0xe3,0x34,0xdf,0x39,0xa9,0x9e,0x1d, + 0xaa,0xf8,0x33,0x09,0xf0,0xaa,0xbb,0xdf,0xef,0x0d,0xc5,0xf6,0xa1,0x23,0x83,0xcd, + 0x7f,0x15,0x57,0xed,0xf7,0xa4,0xa8,0xb7,0x2e,0x84,0xdd,0x5e,0xd6,0xe8,0x03,0x4a, + 0xff,0x4c,0xeb,0x02,0xff,0x80,0x78,0xfe,0x35,0x35,0xb4,0xe0,0xfb,0xfe,0x34,0xe7, + 0x7f,0x8e,0x49,0xf5,0x2f,0x27,0xdb,0xa3,0xd2,0xf3,0xa4,0x8b,0xc1,0xfe,0x2f,0xfa, + 0x6d,0x7f,0x76,0x16,0x1b,0xdd,0x0a,0xfe,0x87,0xdd,0x3f,0x86,0xe9,0xab,0x7f,0xa9, + 0xe2,0x73,0x87,0xb8,0x3f,0x51,0xbd,0xdc,0xdd,0x66,0xc1,0xb2,0x97,0xe0,0xbb,0x2a, + 0xb8,0xfe,0xb9,0xce,0x57,0xff,0x52,0xf3,0x3f,0x7f,0x14,0xa2,0xff,0x69,0x77,0x12, + 0xeb,0x14,0xfd,0x83,0x00,0xff,0xd4,0x4b,0x68,0x67,0xd5,0x69,0xa3,0x77,0x51,0x90, + 0xff,0x11,0xf8,0x47,0xd6,0xff,0xe8,0xdd,0xaf,0x18,0x2a,0x7e,0x03,0x9c,0x7f,0x01, + 0xeb,0x5f,0x47,0xb5,0x47,0x1d,0xa3,0x74,0xff,0xbb,0x4f,0xff,0xd3,0x96,0xef,0x1a, + 0xb8,0x27,0xc8,0x3f,0x8c,0xf3,0xeb,0xf7,0xf5,0x7f,0xb5,0x6d,0x54,0xeb,0xc3,0x95, + 0xf8,0x07,0x1b,0xad,0x6b,0xbb,0xfa,0xe2,0x99,0x80,0xbe,0xe5,0x5c,0x38,0xff,0x63, + 0xd8,0xf1,0x47,0x6d,0xff,0xfc,0xea,0xb3,0x00,0xff,0x74,0x49,0x78,0x18,0xaf,0xd7, + 0x6a,0x02,0xe7,0x83,0x00,0xfc,0xe3,0x9e,0x7f,0xc1,0xb3,0x7f,0xde,0x38,0xa5,0x3d, + 0x1c,0x98,0x87,0x0c,0xf1,0x4f,0x97,0xcb,0xff,0x50,0xb4,0x63,0xb6,0x5a,0x89,0x86, + 0x78,0x42,0x7b,0x05,0xc9,0x42,0x68,0x80,0x7f,0xea,0xa0,0x7f,0xf4,0xf6,0x8d,0xd8, + 0x38,0x5d,0x0a,0xff,0xd4,0xc9,0x6a,0xbd,0x89,0x84,0x8a,0xff,0x19,0x0b,0xeb,0x7f, + 0xcf,0x8c,0x19,0x4e,0xfc,0xa1,0x20,0xfe,0xe1,0xcf,0x7b,0x0a,0xe2,0x1f,0x7a,0x10, + 0x46,0xa7,0xf6,0x70,0x09,0xfc,0xb3,0x89,0xf3,0x3f,0x1d,0xd4,0x28,0xf6,0xdf,0xa6, + 0x98,0xb7,0xf0,0xbe,0x82,0xff,0x99,0x4f,0xd1,0xce,0xde,0xcc,0x74,0x7c,0x53,0x29, + 0xfc,0x13,0x0b,0x64,0x7f,0x3a,0xf6,0x27,0x2b,0xe3,0x1f,0x91,0x8f,0x24,0xfc,0x43, + 0x0e,0xc2,0x60,0x69,0x0e,0x02,0x83,0x90,0xfe,0xaf,0x11,0x04,0xf0,0xcf,0x32,0x91, + 0x7f,0xd3,0x45,0xfe,0xff,0x7b,0xbb,0x9f,0xff,0x31,0xa8,0x70,0x25,0x16,0x86,0x7f, + 0x1a,0x6b,0x65,0xfe,0x27,0x67,0xd4,0x7a,0x30,0xa0,0x52,0x8d,0x7f,0x60,0xfd,0xeb, + 0x30,0x36,0x78,0xfe,0x95,0xe6,0x3f,0xcf,0x67,0xeb,0x77,0xfa,0xf4,0x3c,0xb9,0xe4, + 0xec,0x3d,0x0a,0x3c,0x13,0x57,0xf6,0x7f,0x61,0x63,0x23,0xf6,0x4f,0xf0,0xfc,0x8b, + 0x33,0xe0,0xfc,0x0b,0xd0,0xed,0x8e,0xdd,0xfe,0x87,0x9e,0x10,0xda,0x8f,0x7f,0xd8, + 0xff,0x6f,0xa7,0x84,0x7f,0x50,0xa6,0xd3,0x58,0xd4,0x1b,0xc4,0x3f,0x6f,0x73,0x7e, + 0xbb,0x1e,0xf9,0xfd,0xb9,0xd3,0x9d,0xa7,0xbd,0x36,0x04,0xff,0xc8,0xfd,0x5f,0x5b, + 0xac,0x06,0x25,0xfe,0x89,0xb1,0xf5,0x13,0xa2,0xfe,0xb5,0x91,0x8c,0x81,0xb2,0xde, + 0x1a,0x54,0xf4,0xbf,0x5f,0x06,0xf7,0x8f,0xc4,0xff,0xb4,0xc6,0x36,0xf4,0x45,0xe7, + 0x7f,0x3e,0x83,0xb0,0x27,0xa9,0xc4,0x3f,0x80,0xff,0x71,0x0d,0x3e,0x8f,0x57,0x7a, + 0x1f,0x17,0xe7,0x5f,0x2c,0x04,0xf8,0xc7,0x9b,0xf6,0xf3,0x0e,0xed,0xff,0xaa,0x04, + 0xcf,0xef,0x84,0x38,0xff,0x02,0xd6,0xbf,0x5e,0xf6,0xda,0xbe,0xc4,0xf9,0x17,0x2f, + 0x07,0xf0,0x0f,0x8e,0xff,0x3f,0x11,0xef,0xfb,0x38,0xfb,0x1c,0x8a,0x07,0xe7,0xfb, + 0xc1,0xfa,0xd7,0xa8,0x94,0xad,0x26,0xde,0xba,0xb2,0x2d,0x98,0xbf,0x4e,0x09,0xfc, + 0x63,0xc2,0xf8,0xa3,0x53,0xa3,0xd6,0x13,0x22,0x8a,0xeb,0xff,0x98,0xaf,0xf7,0xeb, + 0x7f,0xc6,0xab,0x7a,0x5e,0x0b,0xc6,0xab,0xd7,0x6c,0xb6,0x3e,0x55,0x2b,0x55,0x37, + 0xb2,0x84,0x08,0xba,0xb7,0x04,0xfe,0xf1,0xe9,0x7f,0x68,0x74,0x0d,0xe6,0xf7,0x89, + 0x12,0xfc,0xcf,0x50,0x7c,0x9f,0xff,0x93,0x7b,0x04,0xfe,0x59,0x6e,0xfa,0xb2,0x5b, + 0x62,0x76,0x5b,0x9b,0x15,0xe8,0x7f,0x97,0xce,0xbf,0x80,0xf9,0xeb,0x58,0xe5,0x90, + 0x57,0x7f,0x49,0xaa,0xf1,0x8f,0x2f,0xdf,0x91,0x44,0xa6,0xea,0x7f,0xe7,0xf8,0xa7, + 0x36,0x90,0xfd,0x2b,0x06,0x02,0x78,0x3b,0x84,0xff,0x21,0x6c,0x98,0x37,0xf6,0x47, + 0x9e,0xff,0x5c,0xac,0xe0,0xfc,0x8f,0x0f,0xff,0xb8,0x85,0xbf,0x40,0x7e,0xff,0x7e, + 0x0f,0xff,0x07,0xb4,0x3e,0xb4,0x0b,0x35,0x92,0xf0,0x17,0x6e,0x20,0xf8,0xa7,0x23, + 0x7c,0x75,0x16,0x32,0x4b,0x19,0xf0,0xaf,0x0f,0x2d,0x47,0x86,0xa5,0x99,0xa5,0x8c, + 0x6f,0xf2,0xfb,0xe4,0x58,0x33,0x83,0x9d,0x6f,0x16,0x62,0x80,0xbf,0xd2,0x0b,0x5d, + 0xe3,0x9b,0xfc,0xfe,0xf5,0xfe,0x7d,0xcb,0xfc,0x6f,0x92,0xb3,0xfc,0x4e,0xa0,0xbf, + 0x44,0x4b,0x9d,0x12,0x86,0xfe,0x7b,0xff,0xfe,0xff,0xb2,0xff,0x75,0xd3,0x8e,0xe0, + 0xf3,0x18,0x8f,0x3f,0xd7,0xfb,0xd7,0xda,0x1a,0x65,0x55,0x32,0xf9,0x7b,0xfe,0xfc, + 0xff,0xc1,0x5f,0xfb,0xb5,0x6b,0xd7,0x9c,0x32,0xc6,0xff,0xe7,0xf5,0xdf,0xb2,0xe7, + 0xf1,0xbb,0x78,0xf8,0x5d,0x3c,0xfc,0x06,0xfe,0xff,0x2e,0x1e,0x96,0xfb,0xfb,0xb6, + 0xc5,0x9f,0x6f,0xd7,0x7a,0xc8,0x8f,0xc5,0xae,0xd9,0x2d,0xbb,0x12,0x17,0x5d,0xe1, + 0x74,0x84,0xfa,0xe0,0x82,0xa3,0xf6,0xee,0x62,0xf5,0x90,0x76,0xb5,0x14,0x3f,0x86, + 0x06,0x12,0x07,0x62,0x19,0xd6,0x76,0x9a,0xf6,0xf4,0x60,0xb1,0x50,0x7e,0xac,0x4e, + 0x62,0x23,0xd3,0xce,0x02,0x05,0x3f,0x09,0xf4,0x51,0xb1,0x5a,0xf0,0x76,0x70,0x20, + 0xd6,0xf4,0x8e,0xb2,0x7e,0xb7,0x35,0x96,0xf2,0xd6,0xef,0x42,0x90,0xff,0xa9,0x6c, + 0xcf,0x7b,0xb0,0xf9,0xf1,0x32,0xfc,0x58,0x0d,0x7d,0x0d,0x89,0xb5,0x4d,0x56,0xe3, + 0x9f,0x75,0xfc,0xbf,0x7f,0x4e,0x5d,0x1f,0x3c,0x6a,0x65,0x7b,0xb1,0x31,0x17,0x4d, + 0x1f,0x4e,0x8c,0x6e,0x84,0x8d,0x37,0x4b,0xd5,0x07,0xa5,0xfe,0x38,0xfb,0x47,0x96, + 0xb2,0x5e,0x26,0xd5,0x07,0xd9,0x7c,0xa4,0x01,0xc2,0x86,0x4d,0x56,0xc3,0xfa,0xa0, + 0x7e,0x20,0xd6,0xea,0x6c,0x68,0x5a,0x0c,0xf8,0x31,0x5f,0x7f,0x1c,0xd5,0x87,0x07, + 0xe6,0xc9,0x0b,0x7e,0x8c,0xf0,0xdb,0x1f,0xa0,0x35,0x4e,0xb5,0xeb,0x8d,0xdb,0x89, + 0x3e,0xff,0x77,0x29,0x3f,0x7f,0x08,0xf8,0x31,0xe9,0xfd,0x14,0xdd,0x86,0xdf,0x77, + 0xb4,0x13,0x76,0xf8,0xf9,0x68,0x48,0xe6,0xc7,0x56,0x2c,0xa7,0xfa,0x70,0x3f,0x1f, + 0x08,0xeb,0x83,0xd2,0xfb,0x69,0x43,0x02,0xb6,0xa5,0x84,0xf0,0x63,0xef,0xa3,0x35, + 0x76,0xb5,0xcb,0x86,0xdd,0x55,0x18,0x28,0xd0,0xf9,0xd8,0x84,0x16,0x8b,0xa9,0xf8, + 0x31,0xa9,0x3f,0xce,0x0a,0xab,0x0f,0x02,0x7e,0x03,0xb0,0x25,0x77,0x14,0xbc,0xfe, + 0xf1,0xed,0x01,0x7d,0x14,0x5b,0xcf,0xe7,0x43,0x0e,0x6a,0x53,0xfa,0x70,0x7f,0x7a, + 0x23,0x65,0xb7,0x5e,0x2c,0x3b,0x1f,0x12,0xcc,0x07,0x48,0x4f,0xd9,0xfe,0xf5,0x82, + 0x1f,0x23,0xe9,0x54,0x3e,0x0d,0xb6,0x36,0x3d,0x8e,0x9f,0x0a,0x5f,0x7d,0x90,0xcf, + 0x27,0xd9,0x6c,0xe4,0xe1,0xee,0x9a,0xc9,0x69,0x20,0x44,0x86,0x14,0x3a,0x1f,0x12, + 0xea,0xc3,0xbf,0x70,0xe7,0x5d,0x07,0xfb,0xe3,0xce,0x48,0xf3,0x91,0xde,0x13,0xfa, + 0xf0,0xbb,0xac,0xe4,0xcf,0xe2,0xe7,0x52,0xfe,0xfe,0xc1,0x33,0xd2,0x7c,0x6c,0xc0, + 0x86,0xa5,0xed,0xf5,0x76,0x7c,0x97,0xd6,0x1f,0xca,0x8f,0x59,0xf3,0xc6,0x7d,0xfb, + 0x5d,0xd4,0x31,0xce,0xc6,0x62,0x83,0xf3,0x61,0x99,0xff,0x77,0xca,0xf3,0x21,0xe9, + 0xf9,0x74,0x7b,0xd0,0x82,0xf0,0xfa,0x60,0x1d,0xb8,0xfe,0x2f,0xd0,0x9d,0x54,0x0f, + 0xaf,0xaf,0xd3,0xe4,0x7e,0x37,0x50,0x1f,0x8c,0xed,0x91,0x4e,0x8f,0xfd,0xb3,0xa4, + 0x98,0x8f,0xcd,0xd7,0xcf,0x07,0xf5,0x41,0xa9,0x3f,0x2e,0x45,0x8d,0xe0,0x7c,0x4e, + 0xc8,0x8f,0xed,0x05,0xf5,0xc1,0x42,0xd6,0x5e,0x5f,0xd0,0xee,0x4a,0x85,0xd7,0x07, + 0x1b,0xfb,0xb8,0x5e,0x37,0x41,0xe6,0xb3,0xe5,0xb1,0x91,0xb4,0x79,0x47,0x4f,0x80, + 0x1f,0x5b,0x8e,0x64,0x99,0x50,0x2e,0xfe,0x63,0x85,0x70,0x48,0xf0,0x63,0x8d,0x62, + 0x3e,0xd2,0x0b,0x3a,0x19,0x8b,0x34,0xff,0xe2,0xb6,0x1b,0x02,0xfa,0x28,0xc0,0x8f, + 0x2d,0x05,0xf1,0xfc,0x32,0xf1,0xc6,0xf0,0xfa,0x52,0xf5,0x41,0x0b,0xd6,0x77,0xce, + 0xdb,0xab,0xf3,0x03,0x17,0xef,0x29,0xc9,0x8f,0x49,0xf3,0x91,0x2c,0x1a,0x7f,0x4c, + 0x7c,0xd9,0x77,0xb8,0x9f,0x7c,0xc5,0xf4,0x51,0xfc,0x79,0xb4,0x25,0x3d,0xc3,0xcd, + 0xe3,0x0b,0x7a,0x14,0xe7,0x83,0x8c,0xf3,0xfa,0x20,0x99,0x0f,0xd9,0xc2,0xa2,0xcd, + 0x6a,0xb4,0xb1,0x07,0xc7,0x1f,0x84,0xfc,0xfe,0x04,0xf5,0x41,0x2f,0x7f,0x55,0x91, + 0x63,0xc8,0x2e,0xa3,0x35,0xf9,0xea,0xd9,0x2a,0xc3,0xbf,0x5f,0x0d,0xce,0x87,0x14, + 0xfe,0x21,0x07,0xcb,0x76,0x61,0xe3,0x53,0xb1,0x9e,0x29,0x88,0x02,0xf5,0xc1,0x9a, + 0x59,0x7a,0x1e,0x68,0xcb,0xbd,0xd5,0xee,0xa0,0x6c,0x39,0x9e,0x4f,0x81,0xfa,0x20, + 0xc8,0x5f,0xc3,0x76,0xca,0x32,0x86,0xb4,0x4f,0x03,0xe7,0x73,0x85,0xf1,0x63,0x5b, + 0x1f,0x71,0x6e,0x1c,0xd2,0x7e,0x87,0xfc,0xf5,0x20,0xc0,0x8f,0x41,0x3d,0xcc,0x01, + 0xed,0x11,0x6b,0x27,0x19,0x94,0xed,0x8b,0xcf,0xb0,0x3e,0xe8,0xd7,0x87,0x57,0xf7, + 0xe0,0xc7,0xc4,0x9f,0x5f,0x8a,0x1c,0x72,0x4b,0xfd,0x71,0xf4,0x7c,0xc6,0xd9,0xe0, + 0xf9,0x56,0xf3,0x45,0x7d,0x70,0x0c,0xde,0x3f,0x5f,0xd9,0xed,0x4e,0xa6,0x93,0xd6, + 0x07,0x6f,0x7b,0x5d,0xc2,0x3f,0xfc,0x3c,0x91,0x31,0x43,0x56,0x43,0xf5,0x54,0xf7, + 0x57,0x66,0x0a,0x47,0xed,0x15,0xb3,0x6a,0xfc,0x33,0x81,0xa4,0x7c,0xd4,0x78,0x2f, + 0xa9,0x0f,0xe2,0xe7,0xab,0x61,0x32,0x44,0x1f,0xa5,0xb3,0xfa,0x20,0x39,0x66,0x4e, + 0xcb,0x76,0x78,0xf5,0xc1,0x74,0x48,0x7d,0x70,0xa1,0xa4,0xcf,0x41,0xad,0xa6,0x31, + 0x20,0xc6,0x86,0x2b,0xf4,0x51,0x85,0x85,0xfc,0xfc,0x0b,0x5a,0x1f,0x84,0xf3,0xa3, + 0xb4,0x92,0xf5,0x41,0x6d,0x46,0x27,0xf3,0x19,0xa8,0xfe,0xfc,0x0d,0xa3,0xed,0x15, + 0x08,0xb4,0xe4,0xf9,0x90,0xa0,0x5f,0x20,0x3d,0x61,0x2c,0xc0,0xd7,0xbf,0xa2,0x73, + 0xd5,0xa9,0x6a,0xa5,0x3e,0xaa,0x28,0xdd,0x0f,0xa8,0xc1,0xe9,0x6c,0xc4,0xc6,0x62, + 0x27,0x83,0x81,0xe2,0xa2,0xae,0x20,0xfe,0x99,0x35,0x21,0xfe,0xe9,0xdf,0x95,0x37, + 0xa6,0x9f,0x74,0xeb,0x65,0x0b,0x94,0xf8,0x67,0x53,0xbd,0xa7,0x8f,0x5a,0x8d,0x61, + 0xcf,0x01,0xb3,0xc9,0xca,0x34,0xe0,0xcb,0x26,0xfd,0x71,0x09,0x01,0x84,0x34,0x70, + 0x3e,0x6c,0xad,0x8c,0x7f,0x2c,0x7a,0x90,0xee,0x7f,0xa3,0xf6,0x71,0x09,0xff,0xcc, + 0x63,0xfb,0x35,0x74,0x89,0x9d,0x7e,0xcc,0x62,0x83,0x92,0x26,0x13,0x4a,0xfc,0x73, + 0xc2,0xf0,0xf5,0xdb,0x26,0xac,0x38,0xf9,0x24,0x73,0xc2,0xe8,0xe9,0x60,0xf1,0x24, + 0xbe,0x1f,0xd6,0x07,0x4d,0x88,0xee,0x66,0xd7,0x6d,0x4e,0x53,0x63,0xca,0x50,0xe2, + 0x9f,0x2e,0x5d,0xee,0x3e,0x98,0x6c,0x6c,0xd5,0xf6,0xd1,0x4f,0x0c,0x35,0xfe,0xd1, + 0x65,0x7d,0x78,0xa1,0xfa,0x23,0x6a,0xb4,0xda,0x99,0x08,0xfa,0x28,0x72,0x50,0xd1, + 0x56,0x05,0x10,0x7a,0x46,0x5d,0x1f,0xfc,0x14,0xb5,0x6e,0xca,0xfc,0x43,0xdc,0x1d, + 0x0b,0x59,0x13,0xa9,0x3e,0x98,0x33,0x76,0x6a,0x53,0xc6,0x76,0x74,0xe7,0xfd,0x86, + 0x84,0x7f,0xd8,0x1f,0xab,0x0f,0xba,0xf3,0xb1,0x2d,0xbc,0x9e,0x0e,0x8a,0x5c,0x4b, + 0x85,0xcd,0x0a,0xfc,0x93,0x82,0xf5,0x41,0x32,0x16,0xc0,0x20,0x63,0x01,0xb6,0x22, + 0x7a,0x50,0x91,0xa2,0x3e,0xb8,0xf9,0x26,0xb6,0x29,0xaa,0xbe,0x5e,0x46,0xfb,0xd3, + 0xe9,0x7c,0x00,0xd8,0xa8,0x75,0x66,0xbe,0x52,0x1f,0x75,0xc9,0x1d,0x44,0x46,0xc7, + 0x1e,0xc2,0x46,0xb9,0xc5,0x50,0x1f,0x45,0x3e,0x5c,0xe3,0x76,0xd3,0xe3,0xf8,0xfc, + 0x48,0x82,0x08,0xcb,0xdf,0x44,0xed,0xf7,0x25,0x94,0xf8,0xa7,0x1e,0x81,0xfe,0xb8, + 0x8b,0x68,0x8d,0x99,0x29,0x68,0x45,0x32,0x16,0xd2,0x34,0xd4,0xf5,0x41,0x24,0xd5, + 0x07,0x53,0x79,0x7c,0x1b,0x8c,0xd3,0xb1,0x90,0x86,0x1a,0xff,0xd4,0x8a,0xfe,0x38, + 0x0c,0x3b,0x2b,0xf2,0xd8,0x9f,0xe3,0xda,0x76,0x24,0x0b,0xd5,0x64,0x7d,0xd4,0x08, + 0xbd,0x48,0xfa,0x6d,0xb3,0xd5,0xba,0xd3,0xfb,0xff,0xcd,0x28,0xf1,0xcf,0x84,0xbf, + 0x5e,0x5c,0xf3,0x8f,0x9e,0x11,0x5e,0x1f,0x9c,0x66,0xf8,0x67,0x1a,0xe3,0x9f,0x95, + 0xb4,0x3e,0x68,0xb4,0x19,0x19,0x25,0xfe,0x91,0xf4,0x51,0x87,0x9c,0x55,0xcf,0x19, + 0x64,0x3e,0xe4,0x68,0x6a,0xd5,0xa0,0xa1,0xd6,0x47,0xe9,0x72,0xf5,0xbc,0x68,0x34, + 0x3d,0x89,0x0d,0x87,0x18,0xde,0x8b,0xc3,0xfa,0xa6,0xb4,0xc0,0x3f,0xc8,0x04,0xd5, + 0xb1,0x83,0xd6,0xca,0x31,0x23,0x97,0x3a,0x6d,0x1f,0x44,0x2b,0x7b,0x81,0x50,0x6a, + 0x91,0xc0,0x3f,0xc6,0xce,0x87,0x05,0xda,0xf9,0x2f,0x57,0x16,0xf5,0x1b,0xe7,0x82, + 0xdd,0x5a,0x4c,0xa8,0xf1,0x4f,0xdd,0x3e,0x31,0x5d,0xf6,0x22,0x89,0x4e,0x83,0xd4, + 0x58,0x63,0x87,0xe8,0xa3,0xfa,0x46,0x4d,0x6f,0x9a,0x0d,0xed,0x6f,0x2a,0x24,0x26, + 0x68,0xda,0x6a,0x29,0xe8,0x6e,0xfe,0xba,0x8b,0xe2,0x1f,0x51,0x8f,0xf3,0xc5,0x1f, + 0xbb,0x3a,0x47,0x81,0xcd,0x0f,0x4c,0x03,0x54,0x0c,0x85,0x3e,0xca,0x5f,0x1f,0x1c, + 0x34,0xf2,0x9a,0x3b,0xd8,0x7f,0x81,0xb2,0x3e,0x68,0xf9,0xe2,0x8f,0xdd,0x48,0x07, + 0xb5,0xa1,0x46,0xf4,0x83,0x10,0x7d,0x14,0x17,0x75,0xd3,0xfc,0xe5,0x18,0x36,0x0e, + 0xb3,0x97,0xf1,0x8d,0xe4,0xbd,0x51,0x52,0xe9,0xc5,0x84,0xe8,0x47,0x58,0x08,0xfb, + 0x07,0xc9,0xc1,0x9d,0x7d,0x54,0x28,0x85,0xe3,0xc9,0x50,0x4c,0xd4,0x07,0xf9,0xfd, + 0xbf,0x9c,0xe2,0x1f,0x6f,0x3e,0x00,0x99,0x97,0x98,0x20,0xf9,0xee,0xa4,0xdd,0x96, + 0x8f,0x50,0x1f,0x24,0xe7,0xb9,0x37,0x3e,0x85,0x8d,0x5f,0xe4,0xb3,0x79,0x50,0x1f, + 0x5c,0x04,0xf1,0x4f,0xb7,0x09,0xdf,0xee,0x0b,0xf7,0xf5,0x6b,0x03,0xa8,0x3f,0x95, + 0xed,0x8f,0xa4,0x8f,0xca,0xa6,0xfa,0x51,0xc5,0x09,0xf2,0xfe,0x85,0xfe,0x54,0x5d, + 0x1f,0x84,0xfa,0x28,0x52,0x1f,0xac,0x20,0xfe,0x99,0x08,0xaf,0x0f,0xfe,0x5c,0xaa, + 0x06,0xde,0xed,0x54,0x93,0xfd,0x9e,0xf7,0x09,0xa5,0x44,0x7d,0xd0,0x79,0x42,0xd6, + 0x47,0xa5,0xca,0xcc,0x87,0x1c,0x93,0xf5,0x51,0xd9,0x14,0x19,0xe4,0x18,0xe4,0x7f, + 0xf8,0x7c,0xda,0xe3,0x68,0xc0,0x84,0xf7,0x03,0x52,0xea,0x75,0x05,0xfe,0x29,0x72, + 0xfc,0xe3,0x7a,0x0f,0xa9,0xe7,0x43,0xf2,0xfc,0xb8,0xd6,0xa7,0x8f,0xba,0x41,0xa9, + 0x97,0x0b,0x9f,0x8f,0x6d,0xab,0xf5,0x63,0xa1,0xf3,0x91,0x72,0xca,0xdf,0x0f,0xc3, + 0x3f,0x66,0xc8,0x7c,0x48,0x81,0x7f,0x26,0xa4,0xf8,0x63,0xca,0x6e,0x01,0xfd,0x71, + 0xec,0x7e,0x9b,0x95,0xf4,0x51,0x4f,0xc8,0x34,0x88,0xc0,0x3f,0x7c,0x3e,0x76,0xa7, + 0xd1,0x65,0x09,0x35,0x78,0xaa,0xd5,0x56,0xce,0x87,0x7c,0x5f,0xcc,0xc7,0xae,0xfb, + 0xa5,0x59,0xde,0x3f,0x62,0x3e,0x76,0x23,0xc4,0x3f,0x5f,0xda,0x4d,0x84,0xff,0x39, + 0x13,0xc0,0xe7,0x80,0xff,0xa9,0x0f,0xf2,0x3f,0x73,0xe8,0x3f,0xfc,0xfc,0x8f,0xd0, + 0x3f,0xf8,0xf8,0x9f,0x7c,0x19,0xfe,0x67,0x93,0x1c,0x7f,0x1a,0x66,0x29,0xff,0xe3, + 0x9f,0xb7,0x20,0xfa,0xd7,0xa6,0xeb,0x24,0x35,0x78,0xcb,0x9e,0x84,0xe0,0x7f,0x60, + 0x7f,0x1c,0xbb,0xfe,0xce,0x98,0x8c,0x7f,0xf4,0x10,0x7d,0x38,0xbb,0x7e,0xbf,0x3e, + 0x5c,0xad,0x7f,0x0e,0xc3,0x3f,0x76,0x56,0xad,0x4f,0x16,0xfc,0x4f,0x40,0x1f,0xa5, + 0x34,0x4e,0xaa,0xf1,0xcf,0xb0,0x2d,0x8f,0x45,0xe2,0x78,0x40,0xcc,0xc7,0xde,0xec, + 0x9f,0x0f,0x10,0xb5,0x3f,0x8e,0xd0,0x20,0xb4,0x3f,0x4e,0xb1,0xdf,0x15,0xca,0xf9, + 0xd8,0x04,0xff,0x78,0x86,0x9f,0xff,0x01,0xfd,0x71,0xf5,0x41,0x35,0x78,0x91,0xcd, + 0x47,0x12,0xf3,0x01,0x2a,0x42,0xf0,0x8f,0x6b,0x14,0x4a,0xf0,0x3f,0xfa,0x1e,0xbf, + 0xf7,0xd2,0xe3,0x81,0xf9,0x48,0xd2,0x7c,0x6c,0x43,0xe8,0xc3,0xf9,0xf5,0xfb,0xf9, + 0x1f,0xbe,0x5f,0xa2,0x8f,0x1a,0x41,0x21,0xb7,0x01,0xe7,0x7f,0xce,0x82,0xfb,0x07, + 0xf0,0x3f,0xd3,0x7c,0x50,0xa4,0xcf,0xff,0x21,0xf3,0xb1,0x47,0x7d,0xb4,0x0f,0x33, + 0xee,0x07,0xfd,0x71,0x22,0xfe,0x0c,0xa0,0x5d,0x34,0xfe,0x54,0xb8,0x13,0x5d,0x3c, + 0xbd,0x4a,0xb7,0x23,0xe9,0xc3,0x6d,0x88,0x7f,0x5e,0xa2,0x46,0xfa,0xb4,0xfd,0xf7, + 0xbe,0xe7,0x57,0xf4,0x43,0xf5,0xf7,0x3f,0xcc,0xf9,0x1f,0xf4,0x09,0x1b,0x94,0xed, + 0xe7,0x7f,0xc0,0x7c,0xec,0x3a,0x39,0xbf,0x93,0x6c,0x0e,0xe2,0xed,0x07,0xac,0xdf, + 0x84,0xc7,0x07,0xa8,0x0f,0xbf,0x32,0xd8,0x5e,0xac,0xb9,0x18,0xbf,0x06,0xf3,0xd7, + 0xaa,0xa9,0xe4,0x25,0x38,0x1f,0xdb,0x00,0xfc,0xcf,0x21,0xb4,0xf2,0x35,0x02,0x7b, + 0x82,0xe7,0x83,0x88,0xf9,0xd8,0x82,0xff,0x79,0x1e,0xc3,0xa4,0x3f,0x97,0x64,0x60, + 0xae,0xb1,0xbe,0x27,0x0d,0xe7,0x03,0x80,0xf8,0x33,0xec,0x7b,0xed,0x02,0xfd,0x71, + 0xfc,0x7a,0x44,0xfe,0xda,0x47,0xf6,0x5b,0xac,0x01,0x63,0x91,0x54,0xf3,0x01,0x62, + 0x92,0x7e,0x3e,0xa4,0x5f,0xac,0xe8,0xc3,0x3f,0x5e,0xf4,0x9e,0x0b,0x9b,0x0f,0x29, + 0xe6,0x63,0xef,0x42,0x0c,0xff,0xe0,0xeb,0x19,0xb2,0x6e,0x55,0xe7,0xaf,0x90,0xf9, + 0xd8,0x23,0x46,0xd9,0xf9,0x90,0x95,0x3a,0xe8,0x8f,0xdb,0xef,0xa3,0xc5,0x04,0xfe, + 0x11,0xf3,0xb1,0x6f,0xea,0x86,0xfb,0xa5,0xf3,0x21,0x83,0xfe,0x71,0x56,0x70,0xfc, + 0xf3,0xcf,0x7c,0x53,0xe4,0x7c,0xd8,0xbb,0x95,0xfb,0xfd,0x63,0xf1,0x3c,0xfe,0x0f, + 0x7b,0xd7,0x1e,0x1c,0xc5,0x71,0xe6,0x7b,0x1e,0x2b,0x8d,0xb4,0x2b,0x34,0x7a,0x2c, + 0xac,0x1d,0x20,0xa3,0x07,0xa0,0x73,0x84,0x58,0x0b,0xbf,0x72,0x70,0x30,0x5a,0x01, + 0x11,0x8f,0x98,0x8d,0xc1,0xa0,0xa4,0x54,0x57,0x63,0x17,0x55,0xf1,0x1f,0x9c,0x4b, + 0x38,0x57,0x17,0xe7,0x1e,0x76,0xaf,0x1e,0x80,0x2d,0xe7,0xbc,0xc1,0x9c,0xad,0x3b, + 0x53,0x75,0x22,0x21,0x39,0xd7,0x95,0xcf,0x07,0xc4,0x0f,0xce,0x76,0xd9,0x23,0x59, + 0x38,0x32,0xa7,0xc3,0x9c,0x8f,0x72,0x11,0x9b,0x32,0xb2,0x8b,0x4a,0x54,0x65,0xfb, + 0xac,0xe3,0xc8,0x19,0x12,0x1b,0xae,0x7b,0x5e,0xdd,0x33,0xd3,0xbd,0x3b,0x6b,0xec, + 0x4b,0x72,0xf6,0xfe,0xf5,0x63,0xb6,0x19,0x75,0x7f,0xdb,0xf3,0xf5,0x6f,0xbe,0xa7, + 0x59,0x15,0x66,0x3b,0x05,0xf3,0xe3,0xc0,0x13,0x72,0x90,0xed,0x14,0xac,0x8f,0x24, + 0x4f,0x86,0xac,0x7f,0x36,0x78,0xd4,0xc7,0xf7,0x98,0xf9,0x71,0x5c,0xe0,0xeb,0x8f, + 0xa6,0x04,0xa4,0xd1,0xe4,0x02,0x52,0x38,0xcb,0xf4,0xd5,0x07,0x78,0xd1,0x2f,0x0d, + 0x31,0xbc,0x1f,0x0a,0xd7,0x87,0x0c,0x83,0x42,0xf5,0x21,0x83,0x60,0xb4,0x50,0x7d, + 0x48,0x47,0x50,0xc4,0x22,0xed,0xf2,0x1f,0xf7,0xf7,0x0d,0xf8,0xbf,0x58,0xe0,0x4b, + 0x9c,0xfe,0xb0,0x7e,0xda,0x33,0xce,0xa9,0x0f,0x99,0x7c,0x3e,0x24,0x0d,0xaa,0xc2, + 0x7c,0xe1,0xfa,0x48,0xb8,0x2c,0xc3,0x2e,0x96,0x7c,0xb8,0xfd,0xd1,0x22,0xd6,0xc7, + 0xa6,0x56,0xb7,0xde,0xb2,0xff,0x44,0xa8,0x0f,0xc9,0x78,0xac,0x8a,0xd7,0x07,0xe0, + 0x00,0x5e,0x7d,0x48,0x1e,0x28,0x54,0x1f,0x80,0xcd,0x7f,0xdc,0xf1,0xe1,0xfa,0x00, + 0xa5,0xd5,0x47,0x2a,0xad,0x3e,0x76,0x84,0xfa,0x00,0x91,0xf8,0x0f,0xc7,0xff,0xc5, + 0x03,0x9d,0xdc,0xfa,0x90,0x14,0xa0,0xeb,0x2b,0xf2,0xfa,0xa3,0xf1,0x00,0xab,0x3e, + 0x92,0xb3,0xba,0x47,0xd9,0xeb,0xf5,0xe6,0x13,0xea,0x8f,0x16,0x00,0xb3,0x02,0xf5, + 0x91,0x82,0xfd,0xd1,0x82,0xf3,0x9f,0x6f,0xf3,0x1f,0x77,0x7f,0xfa,0xfb,0xa3,0xf1, + 0x00,0xb1,0x3f,0x14,0xad,0x0f,0x70,0x03,0xa7,0x3f,0x1a,0x2b,0x2d,0x8e,0xaa,0x0f, + 0xe0,0x7e,0xc2,0xf5,0x01,0x02,0xc0,0xaa,0x57,0x43,0xea,0x63,0x6b,0x42,0xd8,0xdb, + 0x15,0x06,0x94,0xff,0x4b,0x99,0x5f,0xc1,0x2d,0x0b,0x80,0xc1,0xf5,0x08,0x34,0x1d, + 0xe3,0xd5,0x07,0xb8,0x87,0xad,0x6f,0x29,0xff,0x57,0x32,0xca,0xf9,0x75,0x82,0xd4, + 0x47,0xba,0x8a,0xd2,0x3f,0xbf,0xa4,0x0a,0xd5,0x8e,0xf3,0xeb,0x63,0x17,0x5f,0x2f, + 0xe5,0xff,0x92,0x29,0xe9,0x05,0xdd,0xee,0x93,0x4e,0x04,0x3e,0x65,0x7f,0x6e,0x09, + 0xd5,0x87,0x0c,0x82,0xd1,0x8d,0x07,0xeb,0x8e,0xb1,0xeb,0x23,0xf9,0xf2,0xe5,0x37, + 0x52,0xff,0x91,0xd1,0x1f,0x2d,0x44,0x03,0xbe,0x4c,0xae,0xd4,0x11,0xfb,0x0f,0xae, + 0x0f,0xb0,0x8c,0x79,0x7e,0x49,0x1c,0xff,0xd7,0x76,0xf0,0x68,0xa1,0xf3,0x6e,0x56, + 0xc0,0xfe,0x03,0xc2,0xd9,0x61,0x0c,0xfe,0x43,0xec,0x3f,0x4a,0x38,0x5a,0xfe,0xbd, + 0x70,0x7c,0xb8,0xe8,0xf1,0x9f,0x79,0xbc,0xf5,0x7a,0xe0,0xc1,0x19,0x69,0xba,0x9c, + 0x97,0x1f,0x17,0xb9,0x3f,0x48,0x54,0xfe,0xc3,0xa8,0x8f,0xcd,0x5a,0xef,0x15,0xf0, + 0x9f,0x08,0xfc,0x64,0x82,0x57,0x1f,0x9b,0x03,0x3e,0x4b,0xfe,0x53,0xa0,0x3e,0x24, + 0x17,0xcc,0x94,0xc2,0x7f,0xf8,0xf5,0x21,0xb9,0xe0,0x8d,0x02,0xf5,0xb1,0x99,0xf6, + 0x1f,0x9a,0xff,0x84,0xba,0xf5,0x7d,0x9a,0xfc,0x67,0x14,0x44,0x59,0x2f,0xc5,0x7f, + 0xf6,0x7e,0xbe,0xf9,0x0f,0xa7,0x9f,0xc5,0x27,0xe6,0x3f,0x47,0xfc,0xfc,0x67,0xfe, + 0xa7,0xc2,0x7f,0xa8,0xfa,0x48,0xc3,0x5c,0xfe,0x53,0xfd,0xa9,0xf0,0x1f,0x10,0xe4, + 0x3f,0xc5,0xfa,0x83,0xd4,0x14,0xe1,0x3f,0xc1,0xfe,0xb0,0xc9,0x28,0xf3,0xa7,0xf8, + 0x8f,0xf0,0x29,0xf3,0x9f,0xc8,0xf9,0x71,0x9f,0x90,0xff,0xb4,0xfa,0xed,0x3f,0xfb, + 0x69,0xfe,0x13,0x0c,0xdb,0x63,0xf0,0x1f,0x5f,0x7d,0x48,0x2e,0xe0,0xf2,0x1f,0x0e, + 0x20,0xfc,0xc7,0xa4,0xfa,0xa3,0x45,0xe2,0x3f,0x91,0xf4,0x0f,0xe1,0x3f,0xaa,0xdb, + 0x1f,0xb6,0x30,0xff,0xf1,0x7e,0x2f,0x23,0xd2,0xfb,0x17,0xe1,0x3f,0x46,0x98,0xff, + 0x88,0xe1,0xf5,0x1e,0xf7,0xe6,0x33,0xc0,0xc8,0x8f,0xa3,0x81,0x1c,0xb0,0xff,0x98, + 0x5c,0xfe,0xe3,0xf3,0x7f,0x6d,0xa3,0xf9,0x4f,0xf1,0xf3,0xab,0x40,0x7e,0x5c,0x18, + 0xac,0x3f,0x58,0xcb,0x8b,0xff,0xe1,0xf2,0x01,0x6f,0x7f,0xc2,0x2a,0x1e,0xff,0x89, + 0x10,0xff,0xc3,0x03,0x75,0xd3,0x22,0xc5,0x7f,0x14,0x7b,0x93,0x74,0xd2,0x81,0x40, + 0xda,0xd2,0xf1,0x04,0x93,0xff,0x8c,0x0d,0x33,0x69,0x8f,0xd9,0x74,0x42,0xe1,0xf9, + 0xbf,0x58,0xcb,0xd4,0xb5,0x6e,0xda,0x30,0xc8,0x8a,0xff,0xf1,0x8b,0xf1,0x87,0x3a, + 0x5d,0x68,0x88,0xef,0xff,0xb2,0xc1,0x7f,0x83,0x5e,0x9d,0x2e,0xa4,0xf9,0xef,0x45, + 0xfb,0xc3,0xae,0xf0,0xfb,0x07,0x8b,0xf2,0x9f,0x76,0x93,0x8e,0x6f,0x99,0x09,0xf9, + 0xbf,0x24,0xdf,0xfc,0x5f,0x1c,0x69,0x7f,0x9d,0x9e,0x3f,0x5d,0x1f,0x89,0xa9,0x7f, + 0xa0,0x36,0x45,0xcb,0x87,0xf4,0x87,0xbd,0x10,0xa8,0x0f,0xe0,0x82,0xfd,0x53,0x74, + 0x3c,0x8c,0xcf,0xff,0xe5,0x06,0xf9,0xf8,0x68,0x4f,0xda,0x2e,0x94,0xed,0xd9,0x7f, + 0x28,0xff,0x17,0x53,0x3e,0xcb,0x7c,0xfe,0x62,0xe2,0xff,0x0a,0xc4,0xff,0x38,0xe0, + 0x43,0xd0,0xde,0xed,0xd3,0x57,0x5e,0xfd,0xcf,0xc9,0x14,0x53,0xff,0xc0,0x86,0x8c, + 0xdf,0xff,0xe5,0xca,0x33,0x54,0x1f,0x80,0x34,0x8a,0x65,0xfa,0xbf,0xb6,0xcb,0xcc, + 0xfd,0x06,0x1a,0xcf,0xfa,0xf4,0x0f,0xcf,0xff,0xe5,0x80,0x73,0x80,0x34,0x8a,0xcd, + 0x15,0xf4,0x7f,0xb9,0xe0,0x85,0x48,0xfe,0x2f,0x0f,0xe4,0xdb,0x75,0x2a,0xbe,0xa5, + 0xbc,0x40,0x7d,0x00,0x07,0x88,0x77,0xb7,0x94,0xe2,0xff,0xd2,0x17,0xfa,0x0a,0x65, + 0xf3,0xfc,0x5f,0x04,0x34,0x3b,0x85,0xb2,0x25,0xab,0x94,0x74,0x71,0xff,0xd7,0xd3, + 0x76,0x20,0x90,0x13,0x1a,0xc4,0xf6,0x7f,0x51,0x40,0x5f,0xe6,0x2b,0x94,0x4d,0xf9, + 0xbf,0xa8,0xf1,0x2a,0x71,0x84,0xc1,0x95,0xbd,0x74,0xfc,0x0f,0xb3,0x3e,0xa4,0xe1, + 0xa3,0x3d,0x5a,0x4b,0x74,0xff,0x17,0x38,0x14,0x28,0x0c,0xc5,0x8c,0xff,0xf1,0xff, + 0x10,0xe3,0x0a,0xdb,0xff,0xc5,0xe3,0x6f,0x86,0x2f,0xfe,0x87,0xf8,0xbf,0x6a,0xd8, + 0xfc,0x67,0xf9,0xed,0x4b,0xa8,0x2b,0x4c,0xff,0x57,0x80,0xf6,0xd0,0xf1,0x3f,0x2c, + 0xff,0x17,0xa0,0x68,0xcf,0x0b,0xea,0x92,0x7c,0x0b,0xbb,0x3e,0xa4,0xa7,0x7f,0x74, + 0x9f,0x7e,0x6e,0x9d,0xa1,0xf5,0x0f,0xc7,0xff,0x45,0x80,0xb2,0x38,0xdb,0xc2,0xf3, + 0x7f,0x31,0x69,0xcf,0xf2,0xa9,0x56,0xae,0xff,0xeb,0x2f,0x02,0xa7,0xb9,0xa5,0x46, + 0x74,0x9f,0x3e,0x21,0xef,0xbf,0x7b,0x5f,0x08,0x55,0x33,0xbe,0x04,0x2e,0xc1,0x9f, + 0x4e,0xd1,0xe7,0x97,0x49,0xf8,0xa7,0x9d,0x7f,0x31,0xea,0x9f,0xff,0xd3,0xa0,0x69, + 0x55,0x8b,0x8f,0xff,0xb8,0xe3,0xd9,0xf6,0x9f,0xa7,0x41,0x83,0x4e,0x17,0x86,0xa2, + 0xeb,0x43,0xb2,0xf4,0xcf,0x61,0x2f,0xf1,0xc7,0xbe,0xf2,0x0a,0x55,0x1f,0x20,0xe4, + 0xbf,0x60,0x9c,0x2f,0x1c,0xff,0x17,0xed,0x28,0xf4,0x05,0x66,0x70,0xfc,0x5f,0xa4, + 0x50,0x92,0x89,0x0b,0x05,0x30,0xfd,0x5f,0x4c,0xfe,0xf3,0x2f,0x46,0x5b,0x96,0x3e, + 0xbf,0x38,0xfe,0x2f,0x0f,0xa0,0x6d,0x66,0xd2,0xe3,0xa9,0xfa,0xd8,0xe1,0xfa,0x00, + 0x96,0x7c,0x5a,0x75,0xaa,0x90,0x78,0x86,0xf2,0x7f,0xf1,0xf8,0x0f,0xa0,0xe5,0x43, + 0xea,0x43,0xee,0x0f,0xd6,0x07,0xb0,0x03,0xa1,0x85,0x60,0x3d,0x28,0x86,0xfd,0xe7, + 0x9e,0xdf,0x47,0xfb,0x4f,0xb0,0x3e,0x12,0x1b,0x70,0xfb,0xa3,0xfd,0x5f,0xd9,0x7f, + 0xe4,0x2b,0xb3,0xff,0x14,0xf7,0x7f,0x55,0x5d,0x91,0xfd,0xa7,0x50,0x7f,0xb4,0xa2, + 0xf6,0x9f,0x08,0xf2,0xf9,0x14,0xfd,0x5f,0xd1,0xfa,0xc3,0x7e,0x6e,0xed,0x3f,0xbf, + 0x1d,0xff,0x57,0xe1,0xfe,0x68,0x85,0xec,0x3f,0x7c,0xff,0x17,0x27,0xfe,0xe7,0x4a, + 0xfd,0x5f,0xd1,0xfa,0xc3,0x46,0xb6,0xff,0x90,0xfa,0x48,0x62,0x41,0xfb,0x8f,0x67, + 0x7f,0x88,0x68,0xff,0x71,0xef,0x7f,0x85,0xf5,0xb1,0xb9,0xf6,0x1f,0xdd,0x1b,0x5f, + 0x9a,0xfd,0x27,0xd8,0x1f,0x8d,0x0d,0x38,0xfd,0x41,0x4a,0xaf,0x8f,0x5d,0xd4,0xfe, + 0x13,0xee,0x8f,0x16,0xb1,0x3f,0x6c,0x44,0xfb,0x0f,0x9b,0xff,0x04,0xe3,0x9d,0x0a, + 0xf5,0x47,0x63,0x01,0x56,0x7f,0x34,0x91,0x0a,0x84,0x7e,0x33,0xa8,0x3f,0x0b,0xf4, + 0x47,0x23,0xa0,0x9c,0xc1,0x7f,0x28,0xff,0x57,0x81,0xc0,0x06,0x7e,0x7f,0xb4,0x12, + 0xed,0x3f,0x9c,0x78,0x21,0x7e,0x7f,0x34,0xdc,0xbf,0x32,0x20,0x1f,0x89,0x5b,0x1f, + 0x29,0xd8,0x36,0x97,0xc1,0x7f,0x22,0xd9,0x7f,0xf8,0xfd,0x61,0x09,0xd8,0x96,0x38, + 0x4f,0x0a,0x45,0x06,0xf9,0xcf,0x2c,0x1f,0xdb,0xb9,0x13,0x3c,0xd7,0x77,0x27,0x54, + 0x7e,0x4c,0x1a,0x85,0x14,0xe3,0x3f,0x3f,0xc2,0xf9,0x14,0xb5,0x5e,0xa3,0x90,0x4c, + 0x61,0xfe,0x63,0xfd,0x22,0x3b,0x5b,0xf2,0xa4,0x51,0x48,0x71,0xfe,0xd3,0x06,0x13, + 0x0f,0xc5,0xbd,0x47,0xa9,0x28,0xff,0x91,0x57,0xc2,0xea,0xee,0xf8,0x5f,0x96,0xc0, + 0x7f,0x54,0xc4,0x3f,0x5b,0xd5,0xa8,0xfc,0x07,0xbd,0xad,0x29,0x07,0x2b,0xed,0xaf, + 0x86,0xa2,0xf1,0x1f,0x45,0xad,0x2c,0x21,0xfe,0x67,0xc9,0x54,0xcb,0x37,0x49,0xe3, + 0x8c,0x53,0xaa,0x7b,0x7f,0x3e,0xff,0x49,0x1c,0x8c,0x27,0xa2,0xf3,0x1f,0x7f,0x20, + 0x59,0x14,0xfe,0x93,0xc8,0xc7,0x5b,0x4b,0xe1,0x3f,0x4a,0xd6,0x4b,0xa4,0x6d,0x64, + 0xf3,0x9f,0x94,0x6f,0xbd,0x95,0xcb,0xc9,0x7a,0x23,0xf0,0x9f,0x93,0x95,0xd7,0x91, + 0x78,0xaa,0xe2,0xfc,0x67,0xc9,0xc8,0xac,0x69,0xa9,0x85,0xd8,0x7f,0xdc,0xf9,0x70, + 0xf8,0x8f,0xb8,0x02,0x2c,0x86,0xfd,0xa5,0xf0,0x9f,0x4c,0x62,0x6f,0xbc,0x39,0x3a, + 0xff,0x69,0xc5,0xf9,0x47,0xcd,0xa5,0xf0,0x1f,0x45,0x25,0xe3,0x8b,0xf3,0x1f,0xf4, + 0x7e,0x57,0x5f,0x89,0xbe,0x12,0x23,0xf3,0x9f,0x56,0x2a,0x11,0xbb,0x38,0xff,0xf9, + 0x2b,0xbd,0xfa,0x64,0x49,0xfc,0x27,0x5b,0x7d,0x5a,0x6a,0x2e,0x81,0xff,0x68,0xf1, + 0xdd,0xa4,0x51,0x48,0x24,0xfe,0x53,0x2f,0xca,0x25,0xf0,0x9f,0xae,0x38,0x2d,0xcf, + 0x20,0xff,0xe9,0x78,0x30,0x4c,0x63,0x86,0x87,0x9a,0x4b,0xe2,0x3f,0x7b,0x4a,0xe4, + 0x3f,0x03,0x44,0xfe,0x2c,0xfe,0x93,0x09,0xd3,0x9e,0x96,0x92,0xf8,0xcf,0x4d,0xe4, + 0x79,0x89,0xc4,0x7f,0x66,0xfa,0xe6,0xba,0xa6,0x95,0x48,0xfc,0xa7,0x3b,0x6e,0x7f, + 0xb5,0xf1,0xee,0x4e,0x1e,0xff,0x21,0xf6,0x1f,0x74,0x0c,0xd5,0x97,0xc8,0x7f,0x4e, + 0x7b,0xe7,0x57,0x53,0x24,0xfe,0xe3,0xe8,0x9f,0xf1,0xf8,0x8e,0x28,0xf1,0x3f,0x63, + 0x48,0xed,0xcc,0x8d,0xce,0x7f,0xd0,0x41,0xd0,0x6e,0xc9,0x73,0x3b,0x8f,0xff,0xf8, + 0xf5,0x27,0x52,0xb3,0x4f,0x5a,0xfa,0xf3,0x1e,0x7c,0xe5,0xdd,0x48,0xfc,0x87,0x65, + 0xff,0x61,0xc5,0xff,0x58,0x1a,0x7e,0x2c,0x91,0x95,0x96,0x83,0x12,0xf8,0x4f,0x65, + 0x9e,0x14,0x7e,0x8c,0xe2,0xff,0x52,0xe8,0xf1,0x7c,0xfe,0xe3,0x81,0x4a,0xea,0xbc, + 0xe3,0xf2,0x1f,0x0b,0xd8,0x12,0x4b,0xf4,0x92,0x42,0xc4,0x2c,0xfe,0xd3,0xe9,0x3f, + 0xdf,0xf9,0xfc,0x47,0xbd,0x0c,0x6f,0x8c,0x1c,0xff,0x63,0x62,0xfe,0x03,0x1a,0x8b, + 0xd9,0x7f,0x3c,0xfb,0xf3,0x44,0xcc,0x0b,0xa2,0x8b,0x6a,0xff,0x11,0x82,0xd9,0xee, + 0x04,0xb8,0xa9,0x76,0xc4,0xff,0x65,0xf1,0x1f,0x91,0xd3,0x46,0x87,0x61,0xff,0xe1, + 0xf9,0xbf,0xa2,0xe6,0x7f,0x15,0xb3,0xff,0x9c,0x62,0xef,0x87,0x82,0xf6,0x9f,0xe7, + 0x8a,0xbe,0x2f,0x50,0xfe,0xaf,0x68,0xf1,0x3f,0x94,0xff,0x2b,0x9a,0xfd,0xc7,0xf3, + 0x7f,0x05,0xfa,0xc3,0x72,0xec,0x3f,0xde,0xf3,0x18,0xcd,0xfe,0xc3,0xad,0x8f,0xcd, + 0xb3,0xff,0x78,0xfa,0x0d,0xfa,0xed,0x3f,0x7f,0x62,0x81,0x8a,0x42,0xfd,0x41,0x22, + 0xf9,0xdf,0x41,0x31,0xfe,0xc3,0xcd,0xff,0x8a,0x68,0xff,0x71,0xe7,0x1f,0xd5,0xfe, + 0xe3,0xce,0xff,0xb3,0xb1,0xff,0x1c,0xf7,0xf3,0x1f,0xbd,0x98,0x3d,0x84,0xf8,0xbf, + 0x3e,0x23,0xfb,0x8f,0x3f,0xff,0x4b,0x0f,0x0c,0x53,0xbc,0x0c,0xa9,0xef,0x7d,0x42, + 0xfb,0x0f,0xf1,0x7f,0x61,0xfe,0xa3,0x05,0x96,0x59,0x11,0xea,0x0f,0xe2,0xed,0x9f, + 0xc2,0xf6,0x1f,0x85,0x95,0xff,0x45,0xec,0x3f,0xdc,0xc4,0x2e,0xc2,0x7f,0xa6,0x23, + 0xd9,0x7f,0xce,0x95,0x68,0xff,0xe1,0xe4,0x7f,0x7d,0x36,0xf6,0x1f,0xa5,0xf8,0xf3, + 0x4b,0xfc,0x5f,0xd1,0xec,0x3f,0xef,0xd0,0xfc,0x47,0xf9,0x8d,0x5a,0x54,0x9f,0x10, + 0x7e,0x12,0xbb,0x24,0x5c,0xfe,0xc1,0xca,0xa9,0xf2,0x22,0xf6,0x1f,0x57,0x3e,0xbe, + 0xfe,0xb0,0x7c,0xfb,0x0f,0xc9,0xff,0xf2,0xf3,0x9f,0x05,0xec,0xf1,0x3e,0xfe,0xa3, + 0x50,0x61,0xcf,0x09,0x8e,0xfd,0x87,0xca,0xff,0x7a,0x5c,0x59,0x49,0x56,0xb7,0x90, + 0x63,0x3f,0x27,0xfc,0x47,0xbf,0x72,0xfe,0x53,0x28,0xff,0x0b,0x46,0xb2,0xff,0x14, + 0xf3,0x7f,0xb9,0x40,0x29,0xce,0x7f,0xd6,0x87,0xe4,0xb3,0x3e,0xc0,0x7f,0x98,0xfe, + 0x41,0x0c,0xbc,0x7c,0x7f,0x9a,0xff,0x7c,0xfd,0xa3,0x9a,0x52,0xed,0x3f,0x97,0xe0, + 0xd2,0xe6,0xc4,0x64,0x79,0x3b,0x98,0x84,0xd7,0x6a,0x55,0x93,0xd2,0xec,0x22,0xfe, + 0xaf,0x67,0x61,0x23,0x50,0xfa,0x44,0x6d,0x64,0xb7,0x82,0x00,0xc8,0x2c,0xb4,0x68, + 0xcf,0x2c,0xae,0xff,0xeb,0x59,0xc1,0x50,0x94,0x5a,0x51,0x86,0x10,0x34,0x6a,0x0a, + 0xa8,0x95,0x83,0xfb,0x21,0x60,0xff,0x79,0x56,0x46,0xb7,0x55,0xc5,0x55,0x60,0x37, + 0x40,0x00,0xa2,0xd7,0xae,0x82,0xf1,0xcf,0xea,0x6f,0x40,0xbb,0xd1,0xba,0x5b,0x6a, + 0x04,0xaf,0xc0,0xc3,0x30,0x71,0xb0,0xba,0x25,0x6c,0x1f,0x0b,0xe4,0x7f,0xbd,0xb8, + 0xaa,0x7a,0x54,0x3a,0xa8,0x7f,0xac,0xae,0x84,0xb3,0x66,0xe6,0x5c,0x08,0x15,0x12, + 0x0f,0xda,0x7f,0xfe,0xdc,0x48,0x0c,0x4b,0x0b,0xd5,0x57,0x60,0x3b,0x4c,0x1c,0x91, + 0x5a,0x42,0xf9,0xdd,0x7e,0xfb,0x0f,0x62,0xfb,0x86,0x32,0x8c,0xa6,0x7d,0x1f,0xd4, + 0xa0,0x72,0xa4,0xb6,0xc5,0x5f,0x0f,0x2a,0x64,0xff,0x39,0x0c,0xae,0x81,0x8a,0x26, + 0x2a,0xe0,0x7e,0xa0,0xe1,0xfe,0x20,0xb2,0x2a,0x59,0x62,0x51,0x27,0xdd,0xd2,0x01, + 0x7e,0xfb,0xcf,0xd3,0x70,0xf1,0x88,0x72,0x87,0xf8,0x25,0xb0,0x13,0xe7,0x83,0x77, + 0x89,0x37,0x84,0xf2,0xc1,0xfd,0xfe,0xaf,0x73,0xe0,0x0f,0x91,0x58,0xca,0x5b,0xc1, + 0x31,0x90,0xd6,0x13,0x20,0x2e,0xe3,0xfe,0x20,0x05,0xfc,0x5f,0x97,0x9c,0xb6,0x71, + 0xc2,0x25,0x5c,0x36,0xc1,0x94,0xfe,0xa7,0xb8,0xff,0x6b,0x2a,0xf1,0x58,0x27,0x12, + 0x0b,0xb4,0xf2,0x13,0x8f,0x89,0x41,0xf9,0x84,0xed,0x3f,0x2d,0x46,0x65,0x4a,0xdc, + 0x05,0xf6,0x63,0xed,0x71,0x0a,0xec,0x2a,0xea,0xff,0x52,0xee,0x16,0xe7,0x83,0x47, + 0xec,0xb0,0x9f,0x37,0x42,0xeb,0x0d,0xd8,0x7f,0xf4,0x56,0xb3,0x0b,0x67,0xcf,0x3d, + 0x84,0x89,0xf4,0x57,0x6b,0x5f,0x31,0x83,0xfd,0x56,0x02,0xf6,0x1f,0x75,0x45,0x3e, + 0x31,0x22,0x29,0xe0,0x0d,0xbd,0x1d,0x56,0x1f,0x90,0xde,0x65,0xe4,0xbf,0xbb,0xf3, + 0x41,0xfc,0x47,0xb5,0xca,0xfe,0x58,0x65,0x00,0x15,0xab,0x3f,0xc8,0x4c,0x34,0xff, + 0xd7,0x2f,0x20,0x4e,0xeb,0x4e,0xb0,0xf9,0x8f,0xdf,0xfe,0x73,0x67,0x36,0xbe,0x57, + 0xfc,0x25,0xb8,0x4f,0x6f,0xd3,0x2b,0xf7,0xd6,0x15,0xe7,0x3f,0x4b,0xf4,0xf8,0x09, + 0xf1,0x3c,0xf8,0x3e,0x02,0x0a,0x06,0xc5,0xfc,0x5f,0x8b,0x7b,0xe3,0x3d,0xe2,0x87, + 0x60,0xd0,0x5c,0x9c,0xad,0xec,0x11,0x4f,0x16,0xf5,0x7f,0xb5,0x82,0x6a,0xd0,0x64, + 0x22,0x35,0xbf,0x02,0x87,0xfd,0x84,0xd7,0x5b,0x38,0xfe,0x39,0x7c,0xe2,0x07,0xed, + 0x3f,0x2b,0xf5,0xc4,0x49,0xe9,0x57,0xb8,0xfe,0x8f,0x99,0x38,0x21,0x5d,0xe7,0x1f, + 0xbf,0x8b,0x11,0xff,0xac,0xe0,0x6a,0x36,0xea,0x11,0xa4,0x1f,0xaa,0xa0,0x18,0xea, + 0x0f,0xd2,0x18,0xb2,0xff,0x64,0x70,0xb4,0x0f,0x3c,0x34,0x4b,0x43,0xa0,0x2f,0x6c, + 0x01,0x0b,0xda,0x7f,0x5a,0xed,0x6a,0x3f,0x87,0x40,0xa3,0x5e,0x91,0x16,0xc3,0x8c, + 0x28,0x9c,0xff,0x95,0xd8,0x6b,0x95,0x79,0x3c,0x8c,0x7f,0xdf,0x66,0x06,0xff,0x71, + 0xf7,0xa7,0x93,0xff,0x95,0x59,0x52,0x90,0xff,0x30,0xe2,0x9f,0x07,0xe2,0x0d,0xe8, + 0xd8,0x64,0xd7,0x3f,0xec,0x0c,0xe6,0x7f,0x2d,0xf9,0x61,0x7c,0x4a,0xbc,0x09,0xfc, + 0x35,0x68,0x43,0x40,0xba,0x3b,0xd0,0x31,0x96,0x19,0xff,0x7c,0x5d,0x5f,0x02,0xf4, + 0x83,0xb6,0xa9,0xf5,0xe9,0x5a,0xa5,0x00,0xff,0x71,0xf2,0xbf,0x74,0xdc,0xa6,0xb9, + 0x66,0xd0,0x36,0x9b,0x74,0x17,0xce,0xff,0x42,0x24,0x67,0xf1,0x48,0xf5,0xb4,0xd4, + 0x0e,0x5e,0xc6,0x6c,0x67,0x5a,0xba,0xba,0x78,0xfc,0x33,0x5e,0xdd,0x7b,0xb8,0xed, + 0xb2,0x89,0xc0,0x74,0x01,0xff,0x17,0xce,0xff,0x3a,0x43,0x9f,0x56,0xb3,0x2e,0x48, + 0xbf,0x0e,0x9d,0x5f,0xa1,0xfc,0xaf,0x71,0xdc,0x9f,0x5a,0x7f,0x0a,0x2c,0x19,0x55, + 0xb2,0x48,0xff,0x78,0xf3,0xf7,0xea,0x1f,0xba,0xf7,0xc7,0xfc,0xc7,0xf1,0x76,0x9d, + 0xc0,0xf9,0xf2,0x66,0xa5,0x21,0xfe,0xbc,0x50,0xfc,0xb3,0x9b,0xff,0xa5,0x22,0xe9, + 0x1d,0xc4,0x66,0x10,0x80,0xa4,0x41,0xe4,0x69,0x37,0x42,0x3d,0xe5,0xcb,0xff,0x7a, + 0x93,0xf8,0xbf,0xac,0x42,0xbb,0xef,0x42,0x7e,0xfc,0xb3,0x63,0xff,0xd1,0xed,0x6f, + 0x75,0xeb,0x5b,0x4a,0x3e,0x76,0x46,0x58,0xd3,0xdb,0x41,0xfe,0x03,0xab,0xa7,0x84, + 0x19,0x2c,0x8d,0xe9,0xaa,0xf3,0x12,0x3e,0xef,0x96,0xf8,0xf4,0x39,0x95,0xff,0x65, + 0xe7,0xbf,0x83,0xf5,0xb8,0x4d,0xed,0x73,0x23,0x56,0x18,0xcf,0x74,0xd8,0x9f,0x65, + 0x10,0xfe,0xb3,0x5d,0xb0,0x2e,0x1e,0xc2,0xdf,0x6a,0x6d,0x7a,0x05,0x73,0x3c,0x33, + 0xfe,0x59,0x45,0xd2,0xd0,0x95,0xb4,0x25,0x9f,0xed,0xb6,0x7c,0x96,0x86,0xec,0x3f, + 0x8a,0x6b,0xe4,0x29,0x9f,0xb2,0x16,0x5e,0xe5,0xae,0xb7,0x58,0xfe,0x57,0xe7,0xf3, + 0x76,0xfd,0xba,0x19,0xe9,0x42,0x98,0xff,0x90,0xfc,0xaf,0xef,0x5f,0x00,0xaf,0x82, + 0xa5,0xf4,0x6e,0xe9,0x2c,0x68,0xff,0x41,0xf2,0x1f,0x2a,0x6e,0xff,0xf1,0x7e,0xdf, + 0x09,0xf0,0x80,0xda,0x2f,0x97,0x60,0xff,0x91,0x9f,0xa8,0x1d,0xd2,0x16,0x72,0xed, + 0x3f,0x62,0xb0,0xfe,0xa1,0xfc,0x04,0x62,0x23,0x4f,0x47,0xb6,0xff,0xe4,0xc0,0x93, + 0x68,0x51,0xcb,0x3c,0x69,0x8c,0x62,0xa0,0xb9,0xf2,0x49,0x85,0xf9,0x0f,0xc0,0xf7, + 0x6f,0x77,0xef,0xc6,0x30,0x34,0x8d,0xfa,0xf8,0xcf,0x85,0xfa,0x85,0xd9,0xa1,0xe1, + 0x90,0xfd,0x8a,0x6b,0xff,0x31,0xe5,0xc5,0x60,0xc8,0xd4,0x7c,0xd2,0x38,0x5e,0x20, + 0xfe,0x67,0x06,0xcc,0x17,0x73,0x81,0xe8,0xdf,0xb7,0x34,0x7e,0xfe,0xd7,0x1d,0x60, + 0x31,0x18,0x03,0x07,0x5d,0xb6,0x73,0x5d,0xd0,0xfe,0xa3,0x06,0xf9,0x4f,0xfd,0xe3, + 0xfc,0xb2,0x12,0x44,0x9e,0x9e,0xfe,0x51,0xe4,0x03,0x89,0x63,0x44,0x3e,0x45,0xe3, + 0x7f,0xa6,0xd5,0x7d,0xe8,0x19,0xe6,0xb4,0x85,0x65,0xd6,0x7f,0x7e,0x58,0xde,0xd5, + 0xb7,0xbf,0x84,0xf8,0x9f,0x7f,0x06,0x39,0x5d,0x2b,0xb2,0xdf,0x08,0xff,0x99,0x90, + 0x9f,0x85,0xc7,0xa9,0x68,0x67,0x07,0x88,0x7c,0xfe,0x33,0x22,0x06,0xdb,0xc2,0xbe, + 0xad,0x14,0xe0,0x3f,0xe0,0x27,0xc6,0x28,0x68,0xf7,0x9f,0xfe,0x05,0xf9,0xcf,0x02, + 0x78,0xdf,0x54,0xa3,0xd3,0x1f,0xd6,0x39,0x76,0x61,0x01,0xfe,0x23,0x37,0x8b,0x43, + 0x6a,0xa0,0x8d,0xa9,0xfe,0x55,0x91,0x5f,0xff,0x39,0x26,0xe6,0xf4,0x91,0xc8,0xf1, + 0x3f,0xdd,0x8a,0x89,0xf4,0x53,0x3b,0xc3,0xdf,0xc7,0xb3,0xff,0x20,0x1a,0x13,0xb4, + 0xe7,0x84,0xf9,0x8f,0x97,0x7f,0x91,0xaa,0xfa,0x55,0xdf,0xbf,0x19,0x7e,0xf9,0x84, + 0xfb,0xa3,0xbd,0x4c,0xd5,0x3f,0x9c,0x80,0xbb,0xb5,0x46,0xbf,0xd9,0x47,0xe6,0xc7, + 0xff,0x18,0x60,0x10,0xe6,0x0c,0x2d,0x72,0xfc,0xcf,0x11,0xc4,0x67,0xee,0xd3,0x39, + 0x6d,0x61,0x59,0xfc,0x47,0xfe,0x31,0x78,0x05,0xd1,0x1e,0x6b,0xb6,0x11,0xec,0x3f, + 0x13,0x60,0xa0,0xac,0x94,0xf8,0x1f,0x05,0xec,0x6f,0x34,0xc3,0xf2,0xe7,0xc6,0xff, + 0x28,0x03,0x5f,0x45,0xb4,0xa7,0xd1,0x67,0xed,0xb9,0xa8,0xf3,0xed,0x3f,0x8a,0x5c, + 0x0d,0xfa,0x60,0xb1,0xe7,0x85,0xf0,0x1f,0x01,0xcc,0x5d,0xb8,0x53,0x2f,0xf6,0xfc, + 0x12,0xff,0x97,0x02,0xaf,0x46,0xaf,0xd5,0x87,0x7c,0x6c,0xe7,0xf5,0x02,0xf1,0x3f, + 0x2d,0xf2,0x01,0x86,0x35,0xc3,0xbd,0xa2,0x86,0xf9,0x8f,0xfc,0x42,0xd7,0x24,0xf4, + 0x9d,0x5f,0xd2,0x1b,0xe0,0x83,0x3e,0x5e,0xfc,0xcf,0x3f,0x82,0xe7,0xdf,0xd9,0x69, + 0xbf,0x76,0x79,0xb3,0x3d,0xa5,0xbb,0xef,0x5f,0x72,0x28,0xfe,0x67,0x04,0x0c,0xab, + 0x3b,0x03,0xfa,0xea,0x64,0x28,0xf1,0x8d,0xd8,0x7f,0x70,0x7f,0xd8,0xfe,0x80,0x3c, + 0xcd,0x50,0xbf,0x4b,0xe2,0xff,0x52,0xd0,0xf9,0x75,0x6c,0x77,0x50,0x7f,0x06,0x1b, + 0xc1,0xd3,0xf1,0x3f,0x8f,0x63,0xa5,0xe4,0x7c,0x2b,0x58,0x20,0xd0,0x3f,0xee,0xcb, + 0x3e,0xfb,0x0f,0x38,0xd2,0x72,0x2e,0x54,0xf6,0xe7,0x4c,0x80,0x0f,0x10,0xff,0xd7, + 0xa8,0xbc,0x20,0xff,0x1c,0xf4,0x9f,0x5f,0x63,0xce,0xfb,0x7b,0xa3,0x7b,0xa5,0x9d, + 0xee,0x0f,0xdb,0x02,0x8e,0x04,0xc6,0x4f,0xeb,0x81,0x8c,0xf8,0x0c,0x65,0xff,0x51, + 0x13,0xe8,0x7d,0x7f,0xa4,0x88,0x7c,0x28,0xfe,0x33,0xbc,0x1d,0x6d,0xf2,0xc3,0x01, + 0xf9,0xbc,0x49,0xef,0x87,0x72,0xda,0xfe,0x03,0xc3,0xf1,0xcf,0x9d,0x81,0xfa,0xcf, + 0x0f,0x32,0xe2,0x7f,0x26,0xac,0xdd,0xf2,0x2a,0x06,0x33,0xc5,0xe3,0x9f,0xfb,0xda, + 0xb6,0x59,0x6c,0x67,0x08,0xb6,0xcd,0xc4,0x9f,0x67,0xf0,0x9f,0x50,0x7f,0xd8,0x51, + 0xdc,0xaf,0x53,0xe9,0x17,0x5a,0x4f,0xc4,0x9b,0x19,0xcf,0xd7,0xb9,0x60,0xfc,0x8f, + 0x8e,0xa5,0x9d,0x41,0x62,0x9f,0xb0,0x89,0x25,0xdf,0xfe,0x43,0xfa,0x5f,0x58,0x65, + 0xf7,0x5e,0xab,0x3e,0xd2,0x14,0x3e,0x7f,0x47,0xbd,0xf9,0xbf,0x8d,0xfb,0x5f,0x88, + 0xf7,0x9a,0xf6,0x32,0xb1,0x5b,0xf9,0x20,0xcb,0x3e,0xc6,0xee,0x0f,0x6b,0x99,0x35, + 0x46,0x3c,0xb7,0x63,0x8d,0x17,0xba,0x4f,0xf8,0xcf,0x31,0xb9,0xd5,0x2a,0x53,0x39, + 0x74,0xb8,0xf6,0xb8,0xb3,0x6d,0x32,0xad,0x2a,0xe1,0x6f,0xc1,0xfc,0xaf,0x77,0x04, + 0xcf,0xfe,0xfc,0x2a,0xec,0xcf,0xe1,0xfa,0x90,0x99,0xb0,0x87,0x74,0xc6,0xdb,0x0e, + 0xb7,0x0b,0xf3,0x65,0xdc,0x16,0x16,0x9f,0xfe,0x99,0x5d,0x36,0x08,0x7b,0xc4,0x7c, + 0xfd,0x2f,0x9c,0xfa,0xcf,0x9d,0x93,0xc6,0x4b,0xca,0x72,0x58,0xad,0x79,0x61,0x3f, + 0x9d,0xac,0xfe,0xb0,0x56,0xfc,0xcf,0x32,0x4c,0x9b,0x4f,0xeb,0x97,0xd5,0x95,0xe3, + 0xd5,0xff,0x45,0xc9,0x47,0xf7,0xec,0x3f,0xee,0x7a,0x9d,0xfa,0x5d,0x53,0xe8,0xb5, + 0x65,0x12,0xbc,0x04,0x91,0xa2,0xce,0xb3,0xfa,0xc3,0x12,0xfd,0xef,0xd4,0xdf,0x50, + 0xb0,0x1a,0xd9,0x05,0x1a,0xf0,0xe9,0x13,0x8e,0x28,0x38,0x47,0xf1,0x4f,0x6c,0xff, + 0x69,0x9d,0xaa,0xb4,0xcb,0x1e,0x36,0x8c,0xc4,0xbb,0x18,0xeb,0xa5,0xfc,0x5f,0xf6, + 0xfb,0xd7,0xb8,0x95,0x6d,0xd1,0x0f,0x90,0x22,0xba,0x4a,0xa4,0xdf,0x38,0x1c,0xff, + 0x57,0x30,0xfe,0x67,0xa4,0x4c,0x43,0x2f,0xa1,0xc7,0xc4,0x9f,0xa2,0x17,0xa5,0xb8, + 0x15,0xf6,0x03,0xcb,0x7d,0xfc,0xc7,0xbb,0xbf,0xe3,0xff,0x7a,0x10,0xd1,0x1e,0xfd, + 0x02,0x58,0xce,0xf3,0x7f,0xb9,0xe3,0x3d,0xfb,0xcf,0xdf,0x49,0xcd,0xe8,0xa0,0x6c, + 0xd3,0x37,0xa8,0x94,0x7d,0x40,0xf5,0xf8,0x8f,0x3b,0x9e,0xf2,0x7f,0x2d,0x02,0xb8, + 0xec,0x70,0x55,0xbe,0x32,0xec,0xe1,0x9a,0xf6,0x7e,0x5f,0xd2,0xff,0xe2,0xea,0x85, + 0xc0,0x29,0x53,0x1c,0x1e,0x4f,0xf9,0xbf,0x80,0x6b,0xfd,0x28,0x93,0x6b,0x71,0x19, + 0xc0,0x0a,0x55,0x0c,0xd9,0x43,0x1a,0xa9,0xfc,0x77,0xc5,0xb0,0xda,0xc2,0xa2,0x45, + 0xb5,0xe0,0xb2,0xab,0xd8,0xfe,0x13,0xee,0xbf,0x40,0xea,0x3f,0xdb,0xf6,0x9f,0x95, + 0xd9,0xea,0x7c,0xd3,0x79,0x1b,0x90,0xb0,0x9f,0x3a,0x56,0xfe,0xbb,0xed,0x3f,0xca, + 0x54,0x9f,0x90,0xfe,0x14,0xbc,0x8f,0x41,0xbe,0x3f,0xcc,0x07,0xa8,0xfe,0x17,0x4e, + 0xfd,0xc3,0x21,0xc4,0x76,0x70,0xdb,0x0b,0x35,0x3e,0xc0,0xf2,0x7f,0x91,0xfa,0xbd, + 0x6e,0xfc,0x4f,0x5a,0x0c,0xb7,0xf9,0xb0,0xc1,0x7a,0x35,0xf3,0x9a,0xe0,0x8e,0x4f, + 0xc5,0x6c,0x6b,0xcf,0x50,0x5e,0xfc,0x05,0x96,0xa7,0x21,0xe5,0x81,0x2b,0xc6,0x5a, + 0x4e,0xfd,0x67,0x67,0x92,0x76,0xbf,0xd7,0xf2,0x87,0x05,0x06,0xff,0x21,0xfe,0x0e, + 0x2f,0x1f,0x50,0xd8,0x56,0xc0,0xff,0xc5,0xe8,0x7f,0x51,0x37,0xd5,0x88,0xe4,0x2f, + 0x4c,0x52,0x61,0x3f,0x96,0x29,0x32,0x10,0xff,0x33,0xe0,0xf9,0xbf,0x7e,0x0e,0xef, + 0xd7,0xda,0xa0,0x32,0x22,0xdd,0x41,0xd9,0x7f,0xc4,0x36,0x5e,0x7f,0xd8,0xc6,0xe3, + 0x42,0x3f,0xb4,0xda,0x74,0x86,0x33,0x98,0xa8,0xfe,0x17,0x5e,0xfc,0xcf,0x5d,0xa7, + 0xd1,0xf3,0x8b,0x1e,0xcc,0x9b,0x18,0xfc,0x27,0x64,0xff,0x99,0xda,0x78,0xf7,0xa6, + 0xb7,0xc0,0xcf,0x72,0x7f,0x34,0xd5,0x86,0x0b,0x21,0x7e,0xe8,0x34,0x8a,0x55,0xc3, + 0xf5,0x9f,0xe7,0xb9,0xf9,0x5f,0x4d,0x93,0x22,0xd6,0x1e,0x55,0xac,0x7e,0xe8,0xbe, + 0xfe,0x17,0x56,0xfe,0x57,0xe2,0xc2,0xa6,0xb7,0x6a,0x5f,0xed,0xc3,0xc0,0x09,0xfb, + 0xd9,0x78,0xa1,0xee,0x92,0x9b,0x1a,0xe6,0xeb,0x7f,0xe1,0xea,0x9f,0xd3,0x70,0xd0, + 0x06,0x44,0xff,0xb8,0x85,0x10,0x89,0xfd,0xed,0x07,0xb6,0xff,0x6b,0x4c,0xd9,0x21, + 0x9e,0x56,0x10,0x4d,0x3a,0x81,0x14,0x4b,0x58,0x5f,0x11,0xfb,0x8f,0xd5,0x9f,0x5a, + 0xc0,0xf6,0xe7,0xda,0x49,0xdc,0x66,0x65,0x54,0x49,0xdf,0xef,0xea,0x9f,0x5a,0x57, + 0x9e,0x8d,0x54,0xfd,0xe7,0xe4,0xe3,0xf8,0x10,0x99,0x6a,0x45,0xfa,0xd3,0x32,0x9b, + 0xe3,0xb0,0xd2,0xd0,0x7a,0x8f,0x7b,0xfa,0x30,0x0f,0xde,0x4b,0xd8,0x17,0x9b,0x3e, + 0x00,0xb8,0x5e,0x34,0xeb,0x7d,0xb3,0x89,0xf4,0x87,0xcd,0xa9,0x1f,0x29,0x97,0xcb, + 0xd0,0xc5,0x99,0xba,0x8f,0xc0,0xab,0xf8,0xfe,0x0c,0x7f,0x50,0xf9,0x01,0x8a,0xff, + 0x6c,0x77,0x8a,0xd4,0x65,0x3e,0x90,0x87,0x02,0x69,0x5c,0x2c,0xfb,0x0f,0x3e,0xef, + 0xf0,0xdb,0xfd,0xb0,0xf8,0x9f,0x1a,0xe2,0x03,0x9c,0xf1,0xcc,0xfa,0x3f,0x65,0x98, + 0xf6,0x30,0xeb,0x43,0x52,0xf9,0xef,0x74,0xfd,0x9f,0x7f,0x95,0x57,0x98,0xcc,0xfe, + 0x56,0x23,0x65,0xee,0x7c,0x2c,0xfb,0x8f,0x68,0xd3,0x1e,0x95,0xef,0xff,0x5a,0xd8, + 0xeb,0xfd,0x05,0xbb,0xe9,0xde,0x77,0x2a,0xe7,0x8e,0x21,0x30,0xd9,0xb2,0xb4,0xf2, + 0x77,0xa2,0x1f,0xa2,0xdd,0x74,0x4f,0x98,0x2c,0x7e,0x7f,0x05,0x8a,0x74,0x77,0xbc, + 0xa5,0xd8,0x65,0xf6,0x45,0x3f,0xc4,0x4f,0x2c,0xff,0x70,0x3f,0x44,0x56,0x87,0x44, + 0xb9,0xc0,0xfd,0xe7,0x9a,0xa5,0xf5,0x43,0x54,0x4b,0x94,0xbf,0x5a,0x48,0xfe,0x8c, + 0x7e,0x88,0x09,0x33,0x24,0xf3,0x2f,0xfa,0x21,0x16,0x06,0x9f,0xe7,0xf1,0xbf,0x63, + 0xcf,0xe3,0x27,0xeb,0x0f,0xeb,0x44,0x0e,0x04,0xc0,0xef,0x8d,0x3e,0x9c,0x24,0xd2, + 0xfe,0x4e,0x40,0xfe,0x93,0xbf,0x2d,0x7d,0x68,0xdd,0xed,0x8b,0xfe,0xb0,0x81,0xcf, + 0x17,0xfa,0xf0,0xff,0xf9,0xf8,0xa3,0x1d,0x52,0xaf,0x7e,0x5a,0xbd,0x11,0x54,0x8d, + 0x5a,0x60,0x91,0x1c,0xfb,0x99,0xb4,0xc3,0xec,0x51,0xe7,0xd4,0x57,0x1d,0xc5,0x20, + 0x3b,0x47,0xae,0x32,0xaf,0xf5,0xc6,0xaf,0x5e,0x25,0xef,0x10,0x7a,0xf4,0xad,0x2a, + 0x18,0x8f,0xd9,0x20,0x49,0x80,0xe0,0x00,0xf3,0x5a,0x97,0x0f,0x03,0x28,0x0a,0x1a, + 0xec,0xd2,0x6a,0x15,0xd0,0xe7,0x00,0x99,0x02,0x0d,0xb0,0xcb,0x40,0xc0,0x6b,0x2f, + 0x83,0xb7,0xb8,0xd0,0x0b,0xba,0xc1,0x6c,0x30,0x08,0x05,0xc3,0x02,0xc9,0x01,0xe1, + 0x36,0xa1,0x1b,0x6c,0x49,0xc5,0x76,0x0a,0x06,0x06,0x20,0x46,0x8d,0x3f,0xda,0x1d, + 0xbb,0x41,0xf8,0x3a,0xdc,0xd4,0x21,0xef,0x8e,0xdd,0x25,0xf4,0xc0,0xad,0x5a,0x72, + 0xc2,0x03,0x02,0x02,0x23,0x08,0x50,0xf3,0x39,0xaa,0xeb,0x5a,0x56,0x91,0xc5,0x18, + 0xfa,0x4b,0x06,0x48,0x81,0x32,0x20,0x10,0x20,0xbb,0x80,0xac,0xf7,0x68,0x97,0x7c, + 0xbb,0x90,0x82,0x6b,0x34,0x70,0x9f,0xdc,0x28,0x28,0xf9,0x0c,0x50,0x77,0xcb,0x0d, + 0x82,0x02,0x32,0x9a,0x3a,0x20,0x6b,0x36,0xa0,0xc7,0xaf,0x8b,0xdd,0x32,0xba,0x79, + 0xe4,0xd6,0xd6,0xfa,0x59,0xb1,0x4c,0x2e,0x9b,0xdf,0xac,0xc4,0x2a,0x63,0x3a,0xcc, + 0x6a,0xf5,0x2d,0x49,0xd1,0x06,0xcb,0x93,0x80,0x92,0xcf,0x5c,0xa1,0x1c,0xdc,0x6a, + 0x26,0xb3,0x72,0x42,0xd8,0x8a,0x40,0x4d,0x6f,0xac,0x47,0xd8,0x04,0x36,0x9b,0xc9, + 0x74,0xec,0x8f,0x05,0x09,0x83,0x9b,0x64,0xaf,0xfc,0x2a,0x1a,0xaf,0xe9,0x0a,0xa8, + 0x05,0x32,0x44,0xca,0x06,0x69,0x3e,0x5d,0xd0,0x90,0x0a,0xec,0x84,0x2a,0x94,0x55, + 0x41,0x46,0xaa,0x01,0x03,0xd0,0x41,0xc9,0xc7,0x10,0x91,0xe8,0x81,0x86,0x54,0x87, + 0x05,0x1a,0xec,0x50,0x2c,0x7c,0x45,0xd1,0xca,0x1c,0xd0,0x41,0xc9,0x27,0x1b,0x6b, + 0x16,0xbe,0x09,0xb6,0xe8,0xf5,0x30,0xb6,0xcd,0x02,0xf3,0xf2,0x31,0x43,0x38,0x05, + 0xfe,0x0c,0x24,0xf3,0x31,0xcd,0x06,0xf4,0x7a,0xf5,0xb8,0x01,0x4e,0x81,0x1b,0xb0, + 0xe1,0xc4,0xfa,0xbd,0xb4,0x24,0x94,0x6e,0x07,0xdd,0x70,0x36,0xa8,0x22,0x80,0xda, + 0x3f,0x9d,0x72,0x3a,0x97,0xd0,0x3a,0xd1,0x5f,0x96,0xd3,0x30,0xa1,0x49,0x8a,0x3a, + 0x56,0x9f,0x1e,0xc5,0x57,0xd4,0x97,0x80,0x03,0xa8,0xdf,0x0b,0x7d,0xd2,0xe8,0x9d, + 0x4a,0xc2,0x3b,0xc3,0x01,0xa6,0x0b,0x26,0xbc,0x2b,0x94,0x7c,0x24,0x21,0x0d,0x37, + 0x68,0x75,0x78,0x77,0x59,0x20,0x51,0x3f,0x26,0xa4,0x73,0x1b,0xd2,0x9b,0x14,0xf9, + 0x98,0x0b,0xa8,0xf1,0x47,0x33,0x31,0x23,0xd7,0xad,0x6d,0x41,0xe3,0x1d,0x10,0x43, + 0x60,0x14,0x83,0x64,0xbf,0xa0,0xd9,0x00,0x52,0xf2,0xc9,0x58,0x92,0xf3,0x44,0x88, + 0xc0,0x18,0x02,0x78,0x21,0x68,0x45,0x0e,0xa0,0xd7,0x7b,0x8b,0x6c,0xe4,0x52,0xda, + 0x9a,0x2e,0xb0,0x07,0x81,0xab,0xb4,0x35,0x09,0x30,0x26,0x6f,0xcb,0x25,0xd2,0x9d, + 0x5d,0x35,0x7b,0x64,0xcd,0x06,0xb4,0x3c,0x8d,0x58,0xb7,0xb0,0x05,0xdc,0x0a,0xeb, + 0x35,0x07,0xc8,0xe8,0x0a,0x58,0x03,0x6a,0x60,0xd2,0x88,0xa5,0x6c,0xa0,0x53,0xfb, + 0xa7,0x4c,0xf8,0x06,0xec,0x31,0x92,0xc3,0xb1,0x32,0xa1,0x03,0xaa,0x86,0x9c,0x8a, + 0x95,0x81,0x0e,0x98,0x35,0xea,0x53,0xd6,0x15,0x0b,0x10,0x73,0x11,0x30,0x6b,0xad, + 0xbd,0x50,0xab,0xcb,0xb5,0x02,0x80,0x1d,0x9a,0x8a,0x9e,0x85,0x1a,0x79,0x40,0xd7, + 0xd4,0x2e,0xeb,0x8a,0x05,0xd0,0x31,0xe6,0xcd,0x67,0x8d,0x58,0x03,0x07,0x8c,0x05, + 0xaa,0xb0,0x46,0xfa,0x06,0xdc,0x6c,0x24,0x53,0x55,0x18,0x9c,0x34,0xae,0x47,0xa0, + 0xdc,0x01,0xd4,0x7c,0xc6,0xd7,0xc4,0x76,0xf4,0xf5,0x18,0x5b,0x53,0xc9,0x97,0x63, + 0x3b,0x72,0xfb,0x8c,0x6f,0xa7,0xe6,0x61,0x70,0xda,0xf8,0xae,0x7d,0xc5,0x02,0xb4, + 0x3e,0x59,0x23,0xec,0x80,0xa7,0x8d,0x1b,0x53,0x55,0x2f,0x4b,0x36,0x10,0x30,0xe8, + 0x31,0xe6,0xd8,0x57,0x2c,0x60,0xd6,0x50,0xe3,0xd1,0x4d,0xd0,0xfd,0xbb,0xc1,0xcb, + 0x36,0x48,0xa9,0x18,0x24,0x8c,0x4e,0x74,0x7f,0xd0,0x60,0x03,0xb3,0x86,0xda,0x3f, + 0x82,0x06,0xba,0xd0,0x13,0xe3,0xe9,0x9f,0xd8,0x18,0x02,0x3d,0xda,0x1c,0x5b,0x11, + 0x59,0x00,0x52,0xbb,0xad,0x4c,0xb8,0x0d,0x76,0x1b,0xb3,0x53,0xc9,0x9d,0x1e,0x00, + 0xb7,0xe5,0xba,0x0d,0x4b,0xff,0x34,0xd8,0x80,0x1a,0xbf,0x5a,0x4f,0xa6,0x85,0x0d, + 0x60,0x13,0x90,0x61,0xac,0x57,0xe8,0x01,0x5b,0x41,0xd2,0xf4,0x80,0x90,0x76,0x00, + 0x99,0xcf,0x6a,0xb4,0x7f,0x46,0x94,0x16,0xb1,0x12,0xed,0x1f,0x03,0xa6,0xd0,0x23, + 0x28,0x78,0xa0,0x1f,0xed,0x1f,0x0b,0x40,0x6a,0xbd,0xeb,0x64,0x63,0x3f,0xda,0x3f, + 0x95,0x78,0x77,0xe5,0x14,0x3b,0xc0,0xcb,0x03,0x86,0x0d,0xe8,0xf1,0x9d,0x0b,0xb2, + 0xa3,0x9b,0xdb,0x6f,0x55,0x06,0x91,0xb6,0xc9,0x65,0x35,0xa4,0x7f,0x10,0x18,0x40, + 0x6a,0x47,0x41,0xfa,0x27,0x0b,0x2d,0x00,0x28,0xf9,0x54,0x0a,0xd9,0x89,0xcd,0xe9, + 0xa4,0x22,0x77,0x0a,0x59,0x13,0x81,0x44,0x2c,0x0c,0x74,0x4a,0x3e,0x40,0x37,0x54, + 0x55,0x96,0x05,0xc4,0x38,0x33,0x58,0xdb,0x58,0x2a,0xd0,0x06,0x80,0x00,0x32,0x9f, + 0x8c,0xd8,0x08,0xe1,0x88,0xd6,0x35,0x2c,0x8a,0x00,0xc2,0xb4,0xa6,0x28,0x16,0xd0, + 0x10,0x90,0xca,0x2c,0x90,0x50,0xa8,0xf9,0xac,0xd6,0xcb,0x2d,0x25,0x2f,0x25,0x61, + 0xcc,0xd6,0xf6,0xf3,0xa0,0xab,0x7f,0x08,0x20,0xeb,0x1d,0xd4,0xe7,0x58,0xfa,0x47, + 0x1a,0x84,0x12,0x06,0xe8,0x74,0x30,0x25,0x43,0xee,0x01,0x73,0x90,0xda,0xa9,0xd1, + 0x80,0x0d,0xe8,0xf9,0xcb,0x69,0x21,0x01,0x3a,0xd1,0x5f,0xb6,0x80,0x84,0x9e,0x27, + 0x39,0x0d,0xf0,0x83,0xa5,0x9a,0x40,0x13,0x1c,0x40,0x0d,0xb7,0x95,0x8c,0x8e,0xf4, + 0xcf,0xb5,0x30,0x61,0x48,0xdd,0x60,0x2f,0xb8,0x0e,0x54,0x00,0x51,0x07,0x27,0xf5, + 0x66,0x0c,0xb0,0x46,0xa2,0xc6,0xcb,0xd7,0xea,0x1b,0xb2,0x75,0xf9,0xbd,0x47,0x05, + 0x04,0x3a,0x36,0xd5,0xd7,0x23,0xd0,0xb1,0x21,0xbb,0xa9,0x5e,0x1e,0xcf,0x35,0x60, + 0xa0,0xca,0xf4,0xf8,0x45,0xb1,0x3b,0x46,0xbf,0x95,0xde,0xb2,0x3b,0xf6,0x23,0x0b, + 0xcc,0xde,0x97,0xb4,0xc1,0x96,0x07,0x92,0xff,0x90,0x73,0x80,0x6f,0xfe,0x36,0xe3, + 0xc7,0xf3,0xb1,0xc8,0xa6,0x8e,0xe6,0xd3,0x6c,0xcf,0x27,0x2f,0x3b,0xf3,0xf1,0x8d, + 0xdf,0x66,0xd4,0xa4,0xe4,0x35,0xe8,0xf7,0x5a,0x85,0x0f,0xb2,0x32,0xad,0x66,0xb7, + 0x7c,0x7b,0x4d,0x6a,0x60,0x4d,0x43,0xcd,0xc0,0x2a,0x07,0xd0,0xe3,0xe5,0x8e,0x6c, + 0xcd,0x66,0xf9,0x56,0x74,0x98,0xc4,0x10,0x88,0x25,0x85,0xd8,0xaa,0xd5,0x59,0xb0, + 0x59,0x4e,0x82,0xa4,0xbe,0x3a,0xab,0x6e,0x4e,0x24,0x85,0x24,0xbd,0x1f,0x94,0x06, + 0x51,0xd1,0xfb,0x54,0x6d,0x50,0x69,0xc8,0x28,0xd9,0xbe,0x7a,0x04,0x84,0x4c,0x0a, + 0x83,0x98,0x72,0xdb,0x2d,0xf6,0x15,0x7a,0x3a,0x95,0x40,0x84,0x60,0x04,0xb4,0xa0, + 0x8d,0x27,0x42,0x7d,0x44,0x6d,0x91,0x11,0xc8,0xdb,0xc0,0x14,0x87,0xf5,0x03,0xea, + 0x35,0x34,0xdb,0x06,0x09,0xb1,0x0e,0x0c,0x98,0x0d,0xe9,0xd4,0x06,0x69,0x13,0x38, + 0x39,0x96,0x4c,0x57,0x21,0xa0,0x6e,0x36,0xaf,0x47,0xc0,0xac,0x53,0x4f,0x9a,0xd7, + 0xb7,0x57,0xd1,0xf3,0xa9,0x10,0xee,0xea,0xe8,0xc9,0x6f,0xd5,0xe6,0x61,0x1a,0x30, + 0x17,0x7e,0xdb,0x06,0xfb,0xe0,0x77,0x11,0x1f,0x58,0x73,0x97,0x70,0x1a,0x81,0xbf, + 0xa1,0xe5,0x1f,0x5f,0x97,0x79,0x3d,0xff,0xd4,0x81,0xc5,0x15,0x5f,0xc1,0xe0,0xc9, + 0x03,0x8b,0xd7,0xc6,0x6f,0x59,0x77,0x62,0xcf,0x53,0xcd,0xff,0x54,0x11,0xcf,0xac, + 0x3b,0x89,0xc1,0x1f,0xd0,0xf3,0x59,0x76,0xef,0xcd,0x97,0xff,0xe3,0xc5,0xf3,0xef, + 0x5f,0x5c,0x89,0xc1,0x33,0xe7,0x3f,0xb8,0xb8,0xec,0xd2,0xc6,0x33,0x0f,0x5d,0x3e, + 0xfb,0xf1,0xc5,0x65,0xf7,0x6c,0xbc,0x8c,0xc1,0xc7,0xe0,0x0a,0x3e,0x2b,0xfe,0xb6, + 0x62,0x61,0x66,0x6d,0x7e,0xcf,0xb6,0x05,0x17,0xab,0x7f,0xd2,0x79,0x39,0xff,0xeb, + 0x6d,0x2b,0xfe,0x7e,0xed,0xbd,0xaf,0xad,0xcd,0x3f,0xf2,0xf1,0xca,0xcb,0x6b,0x17, + 0xbd,0xb6,0xf6,0xfc,0x23,0x67,0xe9,0xf1,0x2b,0xef,0xb9,0xf9,0xcc,0x43,0xcf,0x9c, + 0x7d,0x9f,0x4c,0xc3,0x9e,0xd8,0xd9,0x0f,0xd0,0xf8,0x9b,0xcf,0x58,0x33,0xa4,0xc7, + 0x37,0xcd,0xef,0x3a,0xb3,0xe7,0xc6,0xb3,0x0f,0xdc,0xb6,0x0c,0xff,0xc7,0x43,0x67, + 0xdf,0x7f,0x1b,0x81,0xb7,0xea,0x9e,0x19,0x78,0xff,0x62,0x53,0xca,0x02,0xef,0x7d, + 0xcf,0x37,0xa1,0xbe,0x5e,0x7d,0x9f,0xba,0x48,0xbd,0x6f,0xb4,0x11,0x01,0x70,0xa3, + 0x5c,0x71,0x54,0xec,0xd5,0xe7,0xaa,0x8b,0xea,0x2d,0x80,0xbe,0x9a,0x5b,0x41,0xcb, + 0x53,0x1e,0xdc,0x01,0x10,0x09,0xac,0x05,0xe3,0x83,0x98,0x0d,0x6e,0xb2,0xf8,0x21, + 0x38,0xed,0x23,0x8a,0xf4,0x78,0x87,0x1f,0x5e,0x05,0xfa,0x73,0x18,0xcc,0x56,0xe4, + 0x9d,0x2e,0x3f,0xf4,0x00,0xf4,0x4d,0xc8,0x26,0x69,0xb9,0x20,0x7f,0x53,0x69,0x40, + 0x3e,0xca,0xaa,0xbb,0x84,0x04,0xec,0x8c,0xc3,0x89,0x6d,0xed,0xc2,0xdc,0x81,0xaf, + 0x69,0x35,0xc7,0x64,0xbc,0x31,0xbe,0x76,0x53,0xcd,0x84,0x0d,0xb4,0x1a,0xd3,0x7f, + 0x7f,0x55,0x29,0x43,0xfc,0x70,0x10,0xb1,0x2e,0xef,0xfe,0x0a,0x06,0x7d,0xe4,0x2f, + 0x92,0x4f,0x15,0xa2,0x85,0x88,0x1f,0x1a,0x00,0x3d,0x56,0x82,0x02,0x11,0x1b,0x1c, + 0x96,0x9b,0xd1,0x95,0x4c,0xaf,0xba,0x0f,0x33,0x46,0x98,0x31,0x7c,0xef,0x68,0x5f, + 0x91,0xd7,0x0d,0xce,0x7e,0x6c,0xf5,0x11,0x75,0xc9,0xc0,0xb7,0x72,0xb5,0x23,0xab, + 0x1e,0xab,0xb9,0x46,0xee,0x32,0x6f,0xb1,0xc1,0x3a,0xfb,0x0a,0x35,0x7b,0xb3,0x0a, + 0xd4,0x81,0xfa,0x89,0xd8,0xc3,0x60,0x12,0x4a,0xa0,0x1e,0x71,0x1f,0xfb,0xb4,0x31, + 0x63,0x36,0xa8,0xc7,0x40,0x27,0xff,0x01,0xbd,0xaa,0xaa,0x2a,0x7a,0x97,0xed,0x06, + 0xf8,0x29,0xc2,0x6f,0xa2,0x82,0x0a,0x56,0xa1,0x7f,0xc8,0x59,0x61,0xb6,0x6a,0xbd, + 0x34,0xeb,0x82,0xe7,0xbe,0x46,0xf7,0xb7,0x5f,0x57,0x35,0xd9,0xff,0xa6,0x2a,0xfb, + 0x5f,0x39,0xe9,0xf1,0xb2,0x61,0x2b,0x49,0xac,0xe8,0x53,0x48,0xe3,0x23,0xfd,0x69, + 0x08,0xc3,0x16,0x31,0x71,0xbe,0xaa,0x81,0xde,0x78,0x55,0xd0,0x45,0x03,0x0c,0x83, + 0xff,0x6d,0xdf,0x7c,0x5e,0xa4,0xb8,0x82,0x38,0x5e,0x6f,0xe6,0xed,0xa4,0xc5,0xd9, + 0xa5,0x7b,0x33,0x0b,0xad,0x2c,0x32,0xa3,0xab,0x1e,0xbc,0xf4,0x2c,0x0a,0x8a,0x07, + 0x9f,0xbb,0x33,0xeb,0xac,0xb0,0xda,0x44,0x54,0x08,0x39,0xb4,0xc1,0x8b,0xb7,0xec, + 0xcd,0x4b,0xe2,0x9b,0xcd,0x45,0xc4,0xc3,0xa2,0x22,0x0a,0x82,0x7b,0xd0,0xdc,0x84, + 0xfc,0x09,0x33,0x0b,0x19,0x48,0x4e,0x42,0x62,0x6e,0x21,0x1b,0xc8,0xc5,0xbb,0x10, + 0x72,0x90,0xb5,0xea,0xbd,0xfe,0xf1,0x7a,0xc7,0x08,0x7a,0x88,0x20,0xf5,0xbd,0xec, + 0x97,0xda,0x37,0x4d,0x75,0xbf,0x9a,0xea,0x4f,0xf5,0xcc,0x1c,0xa2,0x9e,0x65,0xcd, + 0x2e,0x32,0x61,0x66,0x4c,0x64,0x2d,0x4f,0x5f,0x75,0x17,0x2c,0x1f,0xf6,0x88,0x0f, + 0x0d,0x28,0xfa,0x9b,0x68,0x6e,0x67,0xc6,0xf2,0x61,0x7e,0xbf,0xa0,0x33,0x1f,0xe7, + 0xc3,0xf9,0xd4,0xa8,0x3c,0xa2,0xf2,0xf5,0x15,0xb0,0xd8,0x89,0xd8,0x96,0x9b,0xf9, + 0x41,0x39,0x32,0x28,0xe5,0x63,0xf8,0xad,0x0e,0x6b,0xd6,0x78,0x01,0x9a,0xe1,0x57, + 0xa9,0xb1,0x11,0x5d,0xe4,0x23,0xc6,0xf9,0x70,0xdc,0x14,0xf5,0x10,0x8b,0xb7,0x1e, + 0x1f,0x4f,0xb3,0x74,0x7c,0x27,0x1f,0x85,0x1b,0xd9,0x80,0x2e,0xa2,0x7f,0x6a,0x02, + 0x34,0xb8,0x5f,0x64,0xe6,0xd2,0xc8,0x42,0x9e,0x4f,0x4f,0x11,0x0d,0xce,0x26,0x9f, + 0x85,0xa2,0x06,0xab,0x86,0x0f,0x05,0x45,0xca,0xa6,0x28,0x9f,0x1e,0x7d,0xa5,0x44, + 0x67,0xf3,0x86,0xc6,0x7a,0x41,0x3e,0x14,0xf4,0x95,0x3b,0x6b,0xb4,0x31,0xe0,0xe4, + 0x73,0x09,0x69,0x50,0x27,0xad,0x18,0x2e,0x21,0x28,0xbe,0x30,0x58,0x98,0xf3,0x61, + 0x66,0x54,0x71,0x7f,0x17,0x4b,0x72,0xb5,0x3f,0x9b,0x9c,0x09,0x83,0xd1,0x7f,0x1b, + 0xe7,0xfa,0x23,0x76,0xae,0xea,0x47,0xc9,0x61,0x4b,0x83,0x64,0x76,0x8d,0xf0,0x44, + 0x66,0x8d,0xa9,0xa4,0x91,0x62,0x7d,0x8c,0x7c,0xd8,0x36,0x58,0x28,0x46,0xa9,0x99, + 0x19,0x89,0xd5,0xfe,0x6d,0x34,0x17,0x33,0x62,0x9c,0xd9,0x74,0xea,0x67,0x1a,0xc7, + 0x4c,0xe4,0x43,0x25,0xd7,0x45,0xa2,0x97,0xed,0x58,0x3a,0x87,0xdb,0x34,0xdd,0xc3, + 0x08,0xf5,0x1f,0xdf,0xed,0x3f,0x0a,0xcb,0xf5,0x8a,0x0e,0x93,0xda,0x03,0xf8,0x01, + 0xcd,0xde,0xa4,0x16,0x0a,0xe4,0x43,0xed,0x65,0x26,0x24,0x53,0xac,0x87,0x6e,0x22, + 0xaf,0xb7,0xa6,0xbc,0xc5,0x35,0xd8,0x90,0xc7,0xc5,0x3e,0x1c,0xd5,0x82,0x2d,0x79, + 0x1d,0xcd,0x19,0xc7,0x38,0xf5,0x2c,0xbe,0x40,0x1a,0xf4,0xa2,0x0a,0xce,0x0b,0x58, + 0x2d,0x7b,0xb0,0x5a,0xb0,0xed,0x5c,0x25,0x2c,0xec,0x89,0x3b,0x19,0x28,0x3a,0xf9, + 0x60,0xfd,0x34,0x4d,0x91,0xc0,0x2d,0xa2,0xc1,0x8d,0xa5,0x12,0x1f,0xa6,0xc6,0xad, + 0x9f,0x05,0xa9,0x86,0x8d,0x66,0xd7,0xf3,0x2b,0x32,0xee,0xfb,0x68,0x82,0x8a,0x54, + 0xda,0x6f,0x76,0x8c,0xe9,0x1b,0x03,0xce,0xf5,0xc1,0xf7,0xcb,0xa0,0x11,0x4d,0x78, + 0xf0,0x4b,0x13,0x06,0x8d,0x1f,0x45,0x5d,0x2c,0x42,0xac,0x31,0x82,0xa6,0x19,0x0f, + 0x8c,0x51,0xce,0xf5,0xf1,0xa8,0xff,0x10,0x1f,0x82,0xc2,0x69,0x14,0x70,0x3e,0xf5, + 0xe4,0x82,0xb0,0xa0,0xa8,0xc6,0xf8,0x10,0xf3,0xd9,0x3f,0x4d,0x7c,0x88,0xcd,0x60, + 0x3f,0x32,0xd9,0x7c,0x0b,0xf9,0x10,0x52,0x3e,0xcc,0x41,0xd1,0xc9,0x47,0xec,0xe8, + 0x3f,0xa5,0xb6,0x93,0x1b,0xe7,0xfa,0xa8,0xca,0x55,0x78,0x08,0x35,0xfa,0xe2,0x40, + 0x32,0xf1,0x30,0x6b,0x3b,0x1e,0x99,0xf5,0xbc,0x23,0x39,0xf9,0x24,0xb8,0x4d,0x53, + 0xb8,0x4d,0x9a,0xf6,0x0b,0x37,0x4e,0xfb,0x5b,0x70,0x5c,0xdc,0xc2,0x48,0xbc,0x95, + 0xfe,0xcb,0xe9,0x3f,0x31,0x9e,0xe0,0x09,0x35,0xf5,0x4d,0xf5,0x91,0x7e,0xba,0x11, + 0xa9,0xba,0x5f,0x95,0x30,0x84,0x48,0x79,0x64,0x7e,0x82,0x34,0xe2,0xd4,0x33,0xbe, + 0x53,0x8f,0xa9,0xc9,0xb8,0x1a,0xcb,0xfb,0xd0,0x3e,0x3d,0xa9,0xaa,0x0d,0x5c,0xd6, + 0x06,0x2f,0x46,0xf3,0x02,0xda,0xaa,0x4e,0x66,0xd3,0xc9,0x67,0x51,0x5e,0x19,0x86, + 0xd1,0x52,0x08,0xdf,0xcb,0x64,0x80,0xa6,0x1e,0xa0,0x19,0x1a,0x73,0x37,0x33,0x6e, + 0xff,0x51,0xc4,0x87,0x83,0x0a,0x3d,0xa7,0xdc,0xf9,0xd4,0xd0,0x89,0x14,0xd7,0xa7, + 0xd7,0x49,0xf6,0x84,0xb5,0x25,0xa1,0x75,0xe7,0x6b,0x1f,0x41,0xb1,0x15,0xdc,0xcc, + 0xb0,0xf0,0x81,0x1c,0xe3,0x43,0xec,0x3f,0x9d,0x8b,0xc1,0x8c,0xec,0x9e,0xf6,0xfd, + 0x4e,0xec,0x37,0x64,0x57,0x04,0xca,0x1a,0x08,0x3a,0x32,0x0e,0x6c,0xc4,0xa9,0x1f, + 0x2a,0xc0,0xfc,0xb9,0x83,0xbf,0x36,0x81,0x25,0x09,0xb6,0x36,0x45,0x6e,0x8a,0x7a, + 0x00,0x69,0xb1,0x50,0x95,0xf9,0xb0,0x9f,0x19,0x1b,0x71,0xeb,0x67,0xa5,0x7a,0x41, + 0xdd,0x7b,0xde,0x3a,0xaa,0x57,0x2a,0x55,0xf5,0xdb,0xf3,0x83,0x47,0x27,0x57,0xc4, + 0x05,0x34,0xc7,0xd0,0x54,0x53,0xe3,0xe4,0x23,0x90,0x07,0x90,0x0f,0xf1,0xa6,0xff, + 0xf3,0x1c,0xdd,0xfd,0x2f,0x37,0x0b,0x0c,0x78,0x2b,0x0f,0x1c,0xc9,0xf8,0x70,0xf7, + 0xd9,0xb3,0xc4,0x87,0xcf,0xae,0x1d,0x31,0x7c,0xf8,0xc4,0xf0,0xe1,0xef,0x64,0x96, + 0x9d,0xe5,0x70,0x2a,0xe3,0xc3,0x93,0x37,0xce,0x13,0x1f,0x6e,0xbf,0x3e,0x65,0xc0, + 0xec,0x95,0xe5,0xc3,0x5f,0xb7,0x5f,0x6d,0x97,0x78,0xec,0x7d,0x65,0xb0,0xf0,0xe5, + 0x3a,0x1e,0xf6,0xdf,0x14,0x14,0xe7,0x1e,0x2f,0x93,0x31,0x7c,0x68,0x22,0xdf,0xba, + 0xeb,0x0d,0x16,0xfe,0xf3,0x37,0xa5,0x91,0x81,0xe2,0x0d,0x63,0x2c,0x1f,0x52,0xa4, + 0xc4,0xab,0x27,0x33,0x3e,0x3c,0xb0,0xef,0xdc,0x9f,0x77,0xda,0xb4,0xfe,0xbb,0x73, + 0xa3,0xcf,0xe9,0x85,0x39,0x6a,0x7e,0x78,0xf6,0x11,0x8e,0x58,0xf8,0xb6,0xc6,0xbf, + 0x8b,0xf5,0x0f,0x3f,0x0a,0x8b,0xc5,0x62,0xb1,0x58,0x2c,0x16,0x8b,0xc5,0xfa,0xd4, + 0x65,0x66,0x07,0xc9,0xb3,0x03,0x8b,0xc5,0x62,0xb1,0x58,0x2c,0x16,0x8b,0xc5,0x7a, + 0xb7,0xcc,0xec,0x50,0xe3,0xd9,0x81,0xc5,0x62,0xb1,0x58,0x2c,0x16,0x8b,0xc5,0x62, + 0xbd,0x5b,0x66,0x76,0xf0,0xcc,0xec,0xf0,0xb1,0x53,0x61,0xb1,0x58,0x2c,0x16,0x8b, + 0xc5,0x62,0xb1,0x58,0xff,0xa3,0x22,0xfa,0x7d,0x1c,0x3c,0xfb,0x23,0x02,0x4d,0xbf, + 0x5a,0xa9,0x46,0xa0,0xde,0xfb,0xf3,0x84,0xf4,0xb5,0x13,0x11,0x6c,0x88,0xe2,0x98, + 0x7f,0x7d,0xb9,0x73,0xdd,0x1b,0x3b,0x1c,0x29,0xc2,0xf0,0x33,0x01,0x00, From 27a528fb41433c4c1e2b5d6bd3fd8d78606fc724 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Mon, 30 Jul 2007 11:04:57 +0200 Subject: [PATCH 051/259] ppc4xx: Only print ECC related info when the error bis are set Signed-off-by: Stefan Roese --- cpu/ppc4xx/traps.c | 38 ++++++++++++++++++++++++-------------- 1 file changed, 24 insertions(+), 14 deletions(-) diff --git a/cpu/ppc4xx/traps.c b/cpu/ppc4xx/traps.c index eb9420e57..2fcce3de8 100755 --- a/cpu/ppc4xx/traps.c +++ b/cpu/ppc4xx/traps.c @@ -147,6 +147,8 @@ MachineCheckException(struct pt_regs *regs) unsigned long fixup, val; #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) u32 value2; + int corr_ecc = 0; + int uncorr_ecc = 0; #endif /* Probing PCI using config cycles cause this exception @@ -214,14 +216,22 @@ MachineCheckException(struct pt_regs *regs) printf("DDR0: At least one interrupt active\n"); if (val & 0x40) printf("DDR0: DRAM initialization complete.\n"); - if (val & 0x20) + if (val & 0x20) { printf("DDR0: Multiple uncorrectable ECC events.\n"); - if (val & 0x10) + uncorr_ecc = 1; + } + if (val & 0x10) { printf("DDR0: Single uncorrectable ECC event.\n"); - if (val & 0x08) + uncorr_ecc = 1; + } + if (val & 0x08) { printf("DDR0: Multiple correctable ECC events.\n"); - if (val & 0x04) + corr_ecc = 1; + } + if (val & 0x04) { printf("DDR0: Single correctable ECC event.\n"); + corr_ecc = 1; + } if (val & 0x02) printf("Multiple accesses outside the defined" " physical memory space detected\n"); @@ -252,11 +262,11 @@ MachineCheckException(struct pt_regs *regs) printf("DDR0: No DDR0 error know 0x%x %p\n", val, value2); } mfsdram(DDR0_23, val); - if ( (val >> 16) & 0xff) + if (((val >> 16) & 0xff) && corr_ecc) printf("DDR0: Syndrome for correctable ECC event 0x%x\n", (val >> 16) & 0xff); mfsdram(DDR0_23, val); - if ( (val >> 8) & 0xff) + if (((val >> 8) & 0xff) && uncorr_ecc) printf("DDR0: Syndrome for uncorrectable ECC event 0x%x\n", (val >> 8) & 0xff); mfsdram(DDR0_33, val); @@ -264,28 +274,28 @@ MachineCheckException(struct pt_regs *regs) printf("DDR0: Address of command that caused an " "Out-of-Range interrupt %p\n", val); mfsdram(DDR0_34, val); - if (val) + if (val && uncorr_ecc) printf("DDR0: Address of uncorrectable ECC event %p\n", val); mfsdram(DDR0_35, val); - if (val) + if (val && uncorr_ecc) printf("DDR0: Address of uncorrectable ECC event %p\n", val); mfsdram(DDR0_36, val); - if (val) + if (val && uncorr_ecc) printf("DDR0: Data of uncorrectable ECC event 0x%08x\n", val); mfsdram(DDR0_37, val); - if (val) + if (val && uncorr_ecc) printf("DDR0: Data of uncorrectable ECC event 0x%08x\n", val); mfsdram(DDR0_38, val); - if (val) + if (val && corr_ecc) printf("DDR0: Address of correctable ECC event %p\n", val); mfsdram(DDR0_39, val); - if (val) + if (val && corr_ecc) printf("DDR0: Address of correctable ECC event %p\n", val); mfsdram(DDR0_40, val); - if (val) + if (val && corr_ecc) printf("DDR0: Data of correctable ECC event 0x%08x\n", val); mfsdram(DDR0_41, val); - if (val) + if (val && corr_ecc) printf("DDR0: Data of correctable ECC event 0x%08x\n", val); #endif /* CONFIG_440EPX */ #endif /* CONFIG_440 */ From ea9f6bce383cc9fbcdee28b5836109b1a6dba574 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Tue, 31 Jul 2007 08:37:01 +0200 Subject: [PATCH 052/259] ppc4xx: Update 440EPx lwmon5 board support - Clear ECC status regs after ECC POST test - Set dcbz for ECC generation with caches enabled as default - Code cleanup Signed-off-by: Stefan Roese --- board/lwmon5/sdram.c | 37 +++++++++++++------------------------ include/configs/lwmon5.h | 1 - include/ppc440.h | 13 +++++++++++++ post/board/lwmon5/ecc.c | 12 +++++++++++- post/cpu/ppc4xx/fpu.c | 2 +- 5 files changed, 38 insertions(+), 27 deletions(-) diff --git a/board/lwmon5/sdram.c b/board/lwmon5/sdram.c index b6863b6a7..f906b859a 100644 --- a/board/lwmon5/sdram.c +++ b/board/lwmon5/sdram.c @@ -473,7 +473,7 @@ static void program_ecc(u32 start_address, blank_string(strlen(str)); } else { /* ECC bit set method for cached memory */ -#if 1 /* test-only: will remove this define later, when ECC problems are solved! */ +#if 0 /* test-only: will remove this define later, when ECC problems are solved! */ /* * Some boards (like lwmon5) need to preserve the memory * content upon ECC generation (for the log-buffer). @@ -486,6 +486,11 @@ static void program_ecc(u32 start_address, current_address = start_address; while (current_address < end_address) { + /* + * TODO: Th following sequence doesn't work correctly. + * Just invalidating and flushing the cache doesn't + * seem to trigger the re-write of the memory. + */ ppcDcbi(current_address); ppcDcbf(current_address); current_address += CFG_CACHELINE_SIZE; @@ -514,19 +519,6 @@ static void program_ecc(u32 start_address, } #endif -static __inline__ u32 get_mcsr(void) -{ - u32 val; - - asm volatile("mfspr %0, 0x23c" : "=r" (val) :); - return val; -} - -static __inline__ void set_mcsr(u32 val) -{ - asm volatile("mtspr 0x23c, %0" : "=r" (val) :); -} - /************************************************************************* * * initdram -- 440EPx's DDR controller is a DENALI Core @@ -534,8 +526,6 @@ static __inline__ void set_mcsr(u32 val) ************************************************************************/ long int initdram (int board_type) { - u32 val; - #if 0 /* test-only: will remove this define later, when ECC problems are solved! */ /* CL=3 */ mtsdram(DDR0_02, 0x00000000); @@ -640,14 +630,6 @@ long int initdram (int board_type) * Perform data eye search if requested. */ denali_core_search_data_eye(CFG_DDR_CACHED_ADDR, CFG_MBYTES_SDRAM << 20); - - /* - * Clear possible errors resulting from data-eye-search. - * If not done, then we could get an interrupt later on when - * exceptions are enabled. - */ - val = get_mcsr(); - set_mcsr(val); #endif #ifdef CONFIG_DDR_ECC @@ -657,5 +639,12 @@ long int initdram (int board_type) program_ecc(CFG_DDR_CACHED_ADDR, CFG_MBYTES_SDRAM << 20, 0); #endif + /* + * Clear possible errors resulting from data-eye-search. + * If not done, then we could get an interrupt later on when + * exceptions are enabled. + */ + set_mcsr(get_mcsr()); + return (CFG_MBYTES_SDRAM << 20); } diff --git a/include/configs/lwmon5.h b/include/configs/lwmon5.h index b09b47830..5ebe4404d 100644 --- a/include/configs/lwmon5.h +++ b/include/configs/lwmon5.h @@ -140,7 +140,6 @@ /* POST support */ #define CONFIG_POST (CFG_POST_ECC) - #endif /*----------------------------------------------------------------------- diff --git a/include/ppc440.h b/include/ppc440.h index 93c10f120..38809f34b 100644 --- a/include/ppc440.h +++ b/include/ppc440.h @@ -3354,6 +3354,19 @@ typedef struct { unsigned long pciClkSync; /* PCI clock is synchronous */ } PPC440_SYS_INFO; +static inline u32 get_mcsr(void) +{ + u32 val; + + asm volatile("mfspr %0, 0x23c" : "=r" (val) :); + return val; +} + +static inline void set_mcsr(u32 val) +{ + asm volatile("mtspr 0x23c, %0" : "=r" (val) :); +} + #endif /* _ASMLANGUAGE */ #define RESET_VECTOR 0xfffffffc diff --git a/post/board/lwmon5/ecc.c b/post/board/lwmon5/ecc.c index 7f04f9abe..3fa3ba624 100644 --- a/post/board/lwmon5/ecc.c +++ b/post/board/lwmon5/ecc.c @@ -236,7 +236,6 @@ int ecc_post_test (int flags) mfsdram(DDR0_00, value); mtsdram(DDR0_00, value | DDR0_00_INT_ACK_ALL); - /* enable full support of ECC */ mfsdram(DDR0_22, value); mtsdram(DDR0_22, (value &~ DDR0_22_CTRL_RAW_MASK) @@ -247,6 +246,17 @@ int ecc_post_test (int flags) if (ret) break; } + + /* clear error status */ + mfsdram(DDR0_00, value); + mtsdram(DDR0_00, value | DDR0_00_INT_ACK_ALL); + + /* + * Clear possible errors resulting from ECC testing. + * If not done, then we could get an interrupt later on when + * exceptions are enabled. + */ + set_mcsr(get_mcsr()); #endif return ret; diff --git a/post/cpu/ppc4xx/fpu.c b/post/cpu/ppc4xx/fpu.c index 27e9ed01a..0c26fe00e 100644 --- a/post/cpu/ppc4xx/fpu.c +++ b/post/cpu/ppc4xx/fpu.c @@ -29,8 +29,8 @@ #if defined(CONFIG_440EP) || \ defined(CONFIG_440EPX) -#include #include +#include int fpu_status(void) From d2f68006627eda6cb6c7f364bddf621dbfd2fc68 Mon Sep 17 00:00:00 2001 From: Eugene OBrien Date: Tue, 31 Jul 2007 10:24:56 +0200 Subject: [PATCH 053/259] ppc4xx: Update AMCC Bamboo 440EP support Changed storage type of cfg_simulate_spd_eeprom to const Changed storage type of gpio_tab to stack storage (Cannot access global data declarations in .bss until afer code relocation) Improved SDRAM tests to catch problems where data is not uniquely addressable (e.g. incorrectly programmed SDRAM row or columns) Added CONFIG_PROG_SDRAM_TLB to support Bamboo SIMM/DIMM modules Fixed AM29LV320DT (OpCode Flash) sector map Signed-off-by: Eugene OBrien Signed-off-by: Stefan Roese --- board/amcc/bamboo/bamboo.c | 321 ++++++++++++++++++++++++----------- board/amcc/bamboo/init.S | 3 +- board/amcc/bamboo/u-boot.lds | 2 - board/amcc/common/flash.c | 18 +- common/flash.c | 10 +- cpu/ppc4xx/44x_spd_ddr.c | 2 +- include/configs/bamboo.h | 2 + 7 files changed, 248 insertions(+), 110 deletions(-) diff --git a/board/amcc/bamboo/bamboo.c b/board/amcc/bamboo/bamboo.c index caf66909b..00c793afd 100644 --- a/board/amcc/bamboo/bamboo.c +++ b/board/amcc/bamboo/bamboo.c @@ -32,9 +32,170 @@ void ext_bus_cntlr_init(void); void configure_ppc440ep_pins(void); int is_nand_selected(void); -unsigned char cfg_simulate_spd_eeprom[128]; +#if !(defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)) +/************************************************************************* + * + * Bamboo has one bank onboard sdram (plus DIMM) + * + * Fixed memory is composed of : + * MT46V16M16TG-75 from Micron (x 2), 256Mb, 16 M x16, DDR266, + * 13 row add bits, 10 column add bits (but 12 row used only). + * ECC device: MT46V16M8TG-75 from Micron (x 1), 128Mb, x8, DDR266, + * 12 row add bits, 10 column add bits. + * Prepare a subset (only the used ones) of SPD data + * + * Note : if the ECC is enabled (SDRAM_ECC_ENABLE) the size of + * the corresponding bank is divided by 2 due to number of Row addresses + * 12 in the ECC module + * + * Assumes: 64 MB, ECC, non-registered + * PLB @ 133 MHz + * + ************************************************************************/ +const unsigned char cfg_simulate_spd_eeprom[128] = { + 0x80, /* number of SPD bytes used: 128 */ + 0x08, /* total number bytes in SPD device = 256 */ + 0x07, /* DDR ram */ +#ifdef CONFIG_DDR_ECC + 0x0C, /* num Row Addr: 12 */ +#else + 0x0D, /* num Row Addr: 13 */ +#endif + 0x09, /* numColAddr: 9 */ + 0x01, /* numBanks: 1 */ + 0x20, /* Module data width: 32 bits */ + 0x00, /* Module data width continued: +0 */ + 0x04, /* 2.5 Volt */ + 0x75, /* SDRAM Cycle Time (cas latency 2.5) = 7.5 ns */ +#ifdef CONFIG_DDR_ECC + 0x02, /* ECC ON : 02 OFF : 00 */ +#else + 0x00, /* ECC ON : 02 OFF : 00 */ +#endif + 0x82, /* refresh Rate Type: Normal (15.625us) + Self refresh */ + 0, + 0, + 0, + 0x01, /* wcsbc = 1 */ + 0, + 0, + 0x0C, /* casBit (2,2.5) */ + 0, + 0, + 0x00, /* not registered: 0 registered : 0x02*/ + 0, + 0xA0, /* SDRAM Cycle Time (cas latency 2) = 10 ns */ + 0, + 0x00, /* SDRAM Cycle Time (cas latency 1.5) = N.A */ + 0, + 0x50, /* tRpNs = 20 ns */ + 0, + 0x50, /* tRcdNs = 20 ns */ + 45, /* tRasNs */ +#ifdef CONFIG_DDR_ECC + 0x08, /* bankSizeID: 32MB */ +#else + 0x10, /* bankSizeID: 64MB */ +#endif + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0 +}; +#endif -gpio_param_s gpio_tab[GPIO_GROUP_MAX][GPIO_MAX]; #if 0 { /* GPIO Alternate1 Alternate2 Alternate3 */ { @@ -291,73 +452,12 @@ int checkboard(void) return (0); } -#if !(defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)) -/************************************************************************* - * - * init_spd_array -- Bamboo has one bank onboard sdram (plus DIMM) - * - * Fixed memory is composed of : - * MT46V16M16TG-75 from Micron (x 2), 256Mb, 16 M x16, DDR266, - * 13 row add bits, 10 column add bits (but 12 row used only). - * ECC device: MT46V16M8TG-75 from Micron (x 1), 128Mb, x8, DDR266, - * 12 row add bits, 10 column add bits. - * Prepare a subset (only the used ones) of SPD data - * - * Note : if the ECC is enabled (SDRAM_ECC_ENABLE) the size of - * the corresponding bank is divided by 2 due to number of Row addresses - * 12 in the ECC module - * - * Assumes: 64 MB, ECC, non-registered - * PLB @ 133 MHz - * - ************************************************************************/ -static void init_spd_array(void) -{ - cfg_simulate_spd_eeprom[8] = 0x04; /* 2.5 Volt */ - cfg_simulate_spd_eeprom[2] = 0x07; /* DDR ram */ - -#ifdef CONFIG_DDR_ECC - cfg_simulate_spd_eeprom[11] = 0x02; /* ECC ON : 02 OFF : 00 */ - cfg_simulate_spd_eeprom[31] = 0x08; /* bankSizeID: 32MB */ - cfg_simulate_spd_eeprom[3] = 0x0C; /* num Row Addr: 12 */ -#else - cfg_simulate_spd_eeprom[11] = 0x00; /* ECC ON : 02 OFF : 00 */ - cfg_simulate_spd_eeprom[31] = 0x10; /* bankSizeID: 64MB */ - cfg_simulate_spd_eeprom[3] = 0x0D; /* num Row Addr: 13 */ -#endif - - cfg_simulate_spd_eeprom[4] = 0x09; /* numColAddr: 9 */ - cfg_simulate_spd_eeprom[5] = 0x01; /* numBanks: 1 */ - cfg_simulate_spd_eeprom[0] = 0x80; /* number of SPD bytes used: 128 */ - cfg_simulate_spd_eeprom[1] = 0x08; /* total number bytes in SPD device = 256 */ - cfg_simulate_spd_eeprom[21] = 0x00; /* not registered: 0 registered : 0x02*/ - cfg_simulate_spd_eeprom[6] = 0x20; /* Module data width: 32 bits */ - cfg_simulate_spd_eeprom[7] = 0x00; /* Module data width continued: +0 */ - cfg_simulate_spd_eeprom[15] = 0x01; /* wcsbc = 1 */ - cfg_simulate_spd_eeprom[27] = 0x50; /* tRpNs = 20 ns */ - cfg_simulate_spd_eeprom[29] = 0x50; /* tRcdNs = 20 ns */ - - cfg_simulate_spd_eeprom[30] = 45; /* tRasNs */ - - cfg_simulate_spd_eeprom[18] = 0x0C; /* casBit (2,2.5) */ - - cfg_simulate_spd_eeprom[9] = 0x75; /* SDRAM Cycle Time (cas latency 2.5) = 7.5 ns */ - cfg_simulate_spd_eeprom[23] = 0xA0; /* SDRAM Cycle Time (cas latency 2) = 10 ns */ - cfg_simulate_spd_eeprom[25] = 0x00; /* SDRAM Cycle Time (cas latency 1.5) = N.A */ - cfg_simulate_spd_eeprom[12] = 0x82; /* refresh Rate Type: Normal (15.625us) + Self refresh */ -} -#endif long int initdram (int board_type) { #if !(defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)) long dram_size; - /* - * First write simulated values in eeprom array for onboard bank 0 - */ - init_spd_array(); - dram_size = spd_sdram(); return dram_size; @@ -371,11 +471,12 @@ int testdram(void) { unsigned long *mem = (unsigned long *)0; const unsigned long kend = (1024 / sizeof(unsigned long)); - unsigned long k, n; + unsigned long k, n, *p32, ctr; + const unsigned long bend = CFG_MBYTES_SDRAM * 1024 * 1024; mtmsr(0); - for (k = 0; k < CFG_KBYTES_SDRAM; + for (k = 0; k < CFG_MBYTES_SDRAM*1024; ++k, mem += (1024 / sizeof(unsigned long))) { if ((k & 1023) == 0) { printf("%3d MB\r", k / 1024); @@ -399,6 +500,34 @@ int testdram(void) } } } + + /* + * Perform a sequence test to ensure that all + * memory locations are uniquely addressable + */ + ctr = 0; + p32 = 0; + while ((unsigned long)p32 != bend) { + if (0 == ((unsigned long)p32 & ((1<<20)-1))) + printf("Writing %3d MB\r", (unsigned long)p32 >> 20); + *p32++ = ctr++; + } + + ctr = 0; + p32 = 0; + while ((unsigned long)p32 != bend) { + if (0 == ((unsigned long)p32 & ((1<<20)-1))) + printf("Verifying %3d MB\r", (unsigned long)p32 >> 20); + + if (*p32 != ctr) { + printf("SDRAM test fails at: %08x\n", p32); + return 1; + } + + ctr++; + p32++; + } + printf("SDRAM test passes\n"); return 0; } @@ -1211,7 +1340,7 @@ void uart_selection_in_fpga(uart_config_nb_t uart_config) /*----------------------------------------------------------------------------+ | init_default_gpio +----------------------------------------------------------------------------*/ -void init_default_gpio(void) +void init_default_gpio(gpio_param_s (*gpio_tab)[GPIO_MAX]) { int i; @@ -1281,7 +1410,7 @@ void init_default_gpio(void) | +----------------------------------------------------------------------------*/ -void update_uart_ios(uart_config_nb_t uart_config) +void update_uart_ios(uart_config_nb_t uart_config, gpio_param_s (*gpio_tab)[GPIO_MAX]) { switch (uart_config) { @@ -1409,7 +1538,7 @@ void update_uart_ios(uart_config_nb_t uart_config) /*----------------------------------------------------------------------------+ | update_ndfc_ios(void). +----------------------------------------------------------------------------*/ -void update_ndfc_ios(void) +void update_ndfc_ios(gpio_param_s (*gpio_tab)[GPIO_MAX]) { /* Update GPIO Configuration Table */ gpio_tab[GPIO0][6].in_out = GPIO_OUT; /* EBC_CS_N(1) */ @@ -1427,7 +1556,7 @@ void update_ndfc_ios(void) /*----------------------------------------------------------------------------+ | update_zii_ios(void). +----------------------------------------------------------------------------*/ -void update_zii_ios(void) +void update_zii_ios(gpio_param_s (*gpio_tab)[GPIO_MAX]) { /* Update GPIO Configuration Table */ gpio_tab[GPIO0][12].in_out = GPIO_IN; /* ZII_p0Rxd(0) */ @@ -1477,7 +1606,7 @@ void update_zii_ios(void) /*----------------------------------------------------------------------------+ | update_uic_0_3_irq_ios(). +----------------------------------------------------------------------------*/ -void update_uic_0_3_irq_ios(void) +void update_uic_0_3_irq_ios(gpio_param_s (*gpio_tab)[GPIO_MAX]) { gpio_tab[GPIO1][8].in_out = GPIO_IN; /* UIC_IRQ(0) */ gpio_tab[GPIO1][8].alt_nb = GPIO_ALT1; @@ -1495,7 +1624,7 @@ void update_uic_0_3_irq_ios(void) /*----------------------------------------------------------------------------+ | update_uic_4_9_irq_ios(). +----------------------------------------------------------------------------*/ -void update_uic_4_9_irq_ios(void) +void update_uic_4_9_irq_ios(gpio_param_s (*gpio_tab)[GPIO_MAX]) { gpio_tab[GPIO1][12].in_out = GPIO_IN; /* UIC_IRQ(4) */ gpio_tab[GPIO1][12].alt_nb = GPIO_ALT1; @@ -1516,7 +1645,7 @@ void update_uic_4_9_irq_ios(void) /*----------------------------------------------------------------------------+ | update_dma_a_b_ios(). +----------------------------------------------------------------------------*/ -void update_dma_a_b_ios(void) +void update_dma_a_b_ios(gpio_param_s (*gpio_tab)[GPIO_MAX]) { gpio_tab[GPIO1][12].in_out = GPIO_OUT; /* DMA_ACK(1) */ gpio_tab[GPIO1][12].alt_nb = GPIO_ALT2; @@ -1537,7 +1666,7 @@ void update_dma_a_b_ios(void) /*----------------------------------------------------------------------------+ | update_dma_c_d_ios(). +----------------------------------------------------------------------------*/ -void update_dma_c_d_ios(void) +void update_dma_c_d_ios(gpio_param_s (*gpio_tab)[GPIO_MAX]) { gpio_tab[GPIO0][0].in_out = GPIO_IN; /* DMA_REQ(2) */ gpio_tab[GPIO0][0].alt_nb = GPIO_ALT2; @@ -1562,7 +1691,7 @@ void update_dma_c_d_ios(void) /*----------------------------------------------------------------------------+ | update_ebc_master_ios(). +----------------------------------------------------------------------------*/ -void update_ebc_master_ios(void) +void update_ebc_master_ios(gpio_param_s (*gpio_tab)[GPIO_MAX]) { gpio_tab[GPIO0][27].in_out = GPIO_IN; /* EXT_EBC_REQ */ gpio_tab[GPIO0][27].alt_nb = GPIO_ALT1; @@ -1580,7 +1709,7 @@ void update_ebc_master_ios(void) /*----------------------------------------------------------------------------+ | update_usb2_device_ios(). +----------------------------------------------------------------------------*/ -void update_usb2_device_ios(void) +void update_usb2_device_ios(gpio_param_s (*gpio_tab)[GPIO_MAX]) { gpio_tab[GPIO0][26].in_out = GPIO_IN; /* USB2D_RXVALID */ gpio_tab[GPIO0][26].alt_nb = GPIO_ALT2; @@ -1611,20 +1740,21 @@ void update_usb2_device_ios(void) /*----------------------------------------------------------------------------+ | update_pci_patch_ios(). +----------------------------------------------------------------------------*/ -void update_pci_patch_ios(void) +void update_pci_patch_ios(gpio_param_s (*gpio_tab)[GPIO_MAX]) { gpio_tab[GPIO0][29].in_out = GPIO_OUT; /* EBC_EXT_HDLA */ gpio_tab[GPIO0][29].alt_nb = GPIO_ALT1; } /*----------------------------------------------------------------------------+ - | set_chip_gpio_configuration(unsigned char gpio_core) + | set_chip_gpio_configuration(unsigned char gpio_core, + | gpio_param_s (*gpio_tab)[GPIO_MAX]) | Put the core impacted by clock modification and sharing in reset. | Config the select registers to resolve the sharing depending of the config. | Configure the GPIO registers. | +----------------------------------------------------------------------------*/ -void set_chip_gpio_configuration(unsigned char gpio_core) +void set_chip_gpio_configuration(unsigned char gpio_core, gpio_param_s (*gpio_tab)[GPIO_MAX]) { unsigned char i=0, j=0, reg_offset = 0; unsigned long gpio_reg, gpio_core_add; @@ -1778,11 +1908,12 @@ void configure_ppc440ep_pins(void) CORE_NOT_SELECTED /* PCI_PATCH */ }; + gpio_param_s gpio_tab[GPIO_GROUP_MAX][GPIO_MAX]; /* Table Default Initialisation + FPGA Access */ - init_default_gpio(); - set_chip_gpio_configuration(GPIO0); - set_chip_gpio_configuration(GPIO1); + init_default_gpio(gpio_tab); + set_chip_gpio_configuration(GPIO0, gpio_tab); + set_chip_gpio_configuration(GPIO1, gpio_tab); /* Update Table */ force_bup_core_selection(ppc440ep_core_selection, &config_val); @@ -1817,7 +1948,7 @@ void configure_ppc440ep_pins(void) /* UIC 0:3 Selection */ if (ppc440ep_core_selection[UIC_0_3] == CORE_SELECTED) { - update_uic_0_3_irq_ios(); + update_uic_0_3_irq_ios(gpio_tab); dma_a_b_unselect_in_fpga(); } @@ -1825,21 +1956,21 @@ void configure_ppc440ep_pins(void) if (ppc440ep_core_selection[UIC_4_9] == CORE_SELECTED) { sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_DIS_MASK) | SDR0_PFC1_DIS_UICIRQ5_SEL; - update_uic_4_9_irq_ios(); + update_uic_4_9_irq_ios(gpio_tab); } /* DMA AB Selection */ if (ppc440ep_core_selection[DMA_CHANNEL_AB] == CORE_SELECTED) { sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_DIS_MASK) | SDR0_PFC1_DIS_DMAR_SEL; - update_dma_a_b_ios(); + update_dma_a_b_ios(gpio_tab); dma_a_b_selection_in_fpga(); } /* DMA CD Selection */ if (ppc440ep_core_selection[DMA_CHANNEL_CD] == CORE_SELECTED) { - update_dma_c_d_ios(); + update_dma_c_d_ios(gpio_tab); dma_c_d_selection_in_fpga(); } @@ -1848,14 +1979,14 @@ void configure_ppc440ep_pins(void) { sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_ERE_MASK) | SDR0_PFC1_ERE_EXTR_SEL; sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UES_MASK) | SDR0_PFC1_UES_EBCHR_SEL; - update_ebc_master_ios(); + update_ebc_master_ios(gpio_tab); } /* PCI Patch Enable */ if (ppc440ep_core_selection[PCI_PATCH] == CORE_SELECTED) { sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UES_MASK) | SDR0_PFC1_UES_EBCHR_SEL; - update_pci_patch_ios(); + update_pci_patch_ios(gpio_tab); } /* USB2 Host Selection - Not Implemented in PowerPC 440EP Pass1 */ @@ -1871,7 +2002,7 @@ void configure_ppc440ep_pins(void) /* USB2.0 Device Selection */ if (ppc440ep_core_selection[USB2_DEVICE] == CORE_SELECTED) { - update_usb2_device_ios(); + update_usb2_device_ios(gpio_tab); sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UES_MASK) | SDR0_PFC1_UES_USB2D_SEL; sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UPR_MASK) | SDR0_PFC1_UPR_DISABLE; @@ -1904,7 +2035,7 @@ void configure_ppc440ep_pins(void) /* NAND Flash Selection */ if (ppc440ep_core_selection[NAND_FLASH] == CORE_SELECTED) { - update_ndfc_ios(); + update_ndfc_ios(gpio_tab); #if !(defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)) mtsdr(sdr_cust0, SDR0_CUST0_MUX_NDFC_SEL | @@ -1933,7 +2064,7 @@ void configure_ppc440ep_pins(void) /* MII Selection */ if (ppc440ep_core_selection[MII_SEL] == CORE_SELECTED) { - update_zii_ios(); + update_zii_ios(gpio_tab); mfsdr(sdr_mfr, sdr0_mfr); sdr0_mfr = (sdr0_mfr & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_MII; mtsdr(sdr_mfr, sdr0_mfr); @@ -1944,7 +2075,7 @@ void configure_ppc440ep_pins(void) /* RMII Selection */ if (ppc440ep_core_selection[RMII_SEL] == CORE_SELECTED) { - update_zii_ios(); + update_zii_ios(gpio_tab); mfsdr(sdr_mfr, sdr0_mfr); sdr0_mfr = (sdr0_mfr & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_RMII_10M; mtsdr(sdr_mfr, sdr0_mfr); @@ -1955,7 +2086,7 @@ void configure_ppc440ep_pins(void) /* SMII Selection */ if (ppc440ep_core_selection[SMII_SEL] == CORE_SELECTED) { - update_zii_ios(); + update_zii_ios(gpio_tab); mfsdr(sdr_mfr, sdr0_mfr); sdr0_mfr = (sdr0_mfr & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_SMII; mtsdr(sdr_mfr, sdr0_mfr); @@ -1992,7 +2123,7 @@ void configure_ppc440ep_pins(void) sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U1ME_MASK) | SDR0_PFC1_U1ME_DSR_DTR; break; } - update_uart_ios(uart_configuration); + update_uart_ios(uart_configuration, gpio_tab); /* UART Selection in all cases */ uart_selection_in_fpga(uart_configuration); @@ -2014,8 +2145,8 @@ void configure_ppc440ep_pins(void) /* Perform effective access to hardware */ mtsdr(sdr_pfc1, sdr0_pfc1); - set_chip_gpio_configuration(GPIO0); - set_chip_gpio_configuration(GPIO1); + set_chip_gpio_configuration(GPIO0, gpio_tab); + set_chip_gpio_configuration(GPIO1, gpio_tab); /* USB2.0 Device Reset must be done after GPIO setting */ if (ppc440ep_core_selection[USB2_DEVICE] == CORE_SELECTED) diff --git a/board/amcc/bamboo/init.S b/board/amcc/bamboo/init.S index 1459eec36..f4d2ae3f4 100644 --- a/board/amcc/bamboo/init.S +++ b/board/amcc/bamboo/init.S @@ -51,13 +51,12 @@ tlbtab: tlbentry(CFG_BOOT_BASE_ADDR, SZ_256M, CFG_BOOT_BASE_ADDR, 0, AC_R|AC_W|AC_X|SA_G) #else tlbentry(CFG_NAND_BOOT_SPL_SRC, SZ_4K, CFG_NAND_BOOT_SPL_SRC, 0, AC_R|AC_W|AC_X|SA_G) + tlbentry(CFG_SDRAM_BASE, SZ_256M, CFG_SDRAM_BASE, 0, AC_R|AC_W|AC_X|SA_G|SA_I) #endif /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */ tlbentry(CFG_INIT_RAM_ADDR, SZ_4K, CFG_INIT_RAM_ADDR, 0, AC_R|AC_W|AC_X|SA_G) - tlbentry(CFG_SDRAM_BASE, SZ_256M, CFG_SDRAM_BASE, 0, AC_R|AC_W|AC_X|SA_G|SA_I) - /* PCI base & peripherals */ tlbentry(CFG_PCI_BASE, SZ_256M, CFG_PCI_BASE, 0, AC_R|AC_W|SA_G|SA_I) diff --git a/board/amcc/bamboo/u-boot.lds b/board/amcc/bamboo/u-boot.lds index f6d718319..0375618d7 100644 --- a/board/amcc/bamboo/u-boot.lds +++ b/board/amcc/bamboo/u-boot.lds @@ -141,8 +141,6 @@ SECTIONS *(COMMON) } - ppcenv_assert = ASSERT(. < 0xFFFF8000, ".bss section too big, overlaps .ppcenv section. Please update your confguration: CFG_MONITOR_BASE, CFG_MONITOR_LEN and TEXT_BASE may need to be modified."); - _end = . ; PROVIDE (end = .); } diff --git a/board/amcc/common/flash.c b/board/amcc/common/flash.c index e6429ecd1..eba0511f2 100644 --- a/board/amcc/common/flash.c +++ b/board/amcc/common/flash.c @@ -745,19 +745,27 @@ static ulong flash_get_size_2(vu_long * addr, flash_info_t * info) if (info->flash_id & FLASH_BTYPE) { /* set sector offsets for bottom boot block type */ info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00004000; - info->start[2] = base + 0x00006000; - info->start[3] = base + 0x00008000; - for (i = 4; i < info->sector_count; i++) { + info->start[1] = base + 0x00002000; + info->start[2] = base + 0x00004000; + info->start[3] = base + 0x00006000; + info->start[4] = base + 0x00008000; + info->start[5] = base + 0x0000a000; + info->start[6] = base + 0x0000c000; + info->start[7] = base + 0x0000e000; + for (i = 8; i < info->sector_count; i++) { info->start[i] = - base + (i * 0x00010000) - 0x00030000; + base + ((i-7) * 0x00010000); } } else { /* set sector offsets for top boot block type */ i = info->sector_count - 1; + info->start[i--] = base + info->size - 0x00002000; info->start[i--] = base + info->size - 0x00004000; info->start[i--] = base + info->size - 0x00006000; info->start[i--] = base + info->size - 0x00008000; + info->start[i--] = base + info->size - 0x0000a000; + info->start[i--] = base + info->size - 0x0000c000; + info->start[i--] = base + info->size - 0x0000e000; for (; i >= 0; i--) { info->start[i] = base + i * 0x00010000; } diff --git a/common/flash.c b/common/flash.c index a64bc9852..888ff9c67 100644 --- a/common/flash.c +++ b/common/flash.c @@ -47,16 +47,16 @@ flash_protect (int flag, ulong from, ulong to, flash_info_t *info) short s_end = info->sector_count - 1; /* index of last sector */ int i; - debug ("flash_protect %s: from 0x%08lX to 0x%08lX\n", - (flag & FLAG_PROTECT_SET) ? "ON" : - (flag & FLAG_PROTECT_CLEAR) ? "OFF" : "???", - from, to); - /* Do nothing if input data is bad. */ if (info->sector_count == 0 || info->size == 0 || to < from) { return; } + debug ("flash_protect %s: from 0x%08lX to 0x%08lX\n", + (flag & FLAG_PROTECT_SET) ? "ON" : + (flag & FLAG_PROTECT_CLEAR) ? "OFF" : "???", + from, to); + /* There is nothing to do if we have no data about the flash * or the protect range and flash range don't overlap. */ diff --git a/cpu/ppc4xx/44x_spd_ddr.c b/cpu/ppc4xx/44x_spd_ddr.c index e5f296eb0..4a4c6f29e 100644 --- a/cpu/ppc4xx/44x_spd_ddr.c +++ b/cpu/ppc4xx/44x_spd_ddr.c @@ -269,7 +269,7 @@ struct bank_param { typedef struct bank_param BANKPARMS; #ifdef CFG_SIMULATE_SPD_EEPROM -extern unsigned char cfg_simulate_spd_eeprom[128]; +extern const unsigned char cfg_simulate_spd_eeprom[128]; #endif static unsigned char spd_read(uchar chip, uint addr); diff --git a/include/configs/bamboo.h b/include/configs/bamboo.h index d58344d71..4e00b9f77 100644 --- a/include/configs/bamboo.h +++ b/include/configs/bamboo.h @@ -222,6 +222,8 @@ #define CFG_SIMULATE_SPD_EEPROM 0xff /* simulate spd eeprom on this address */ #define SPD_EEPROM_ADDRESS {CFG_SIMULATE_SPD_EEPROM, 0x50, 0x51} #define CFG_MBYTES_SDRAM (64) /* 64MB fixed size for early-sdram-init */ +#define CONFIG_PROG_SDRAM_TLB +#undef CFG_DRAM_TEST /*----------------------------------------------------------------------- * I2C From dec99558b9ea75a37940d07f41a3565a50b54ad1 Mon Sep 17 00:00:00 2001 From: Rafal Jaworowski Date: Tue, 31 Jul 2007 18:19:54 +0200 Subject: [PATCH 054/259] [ppc4xx] Separate settings for PCIe bus numbering on 440SPe rev.A This brings back separate settings for PCIe bus numbers depending on chip revision, which got eliminated in 2b393b0f0af8402ef43b25c1968bfd29714ddffa commit. 440SPe rev. A does NOT work properly with the same settings as for the rev. B (no devices are seen on the bus during enumeration). Signed-off-by: Rafal Jaworowski --- cpu/ppc4xx/440spe_pcie.c | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/cpu/ppc4xx/440spe_pcie.c b/cpu/ppc4xx/440spe_pcie.c index d6c4be5f1..7b27e8707 100644 --- a/cpu/ppc4xx/440spe_pcie.c +++ b/cpu/ppc4xx/440spe_pcie.c @@ -783,9 +783,14 @@ void ppc440spe_setup_pcie_rootpoint(struct pci_controller *hose, int port) /* * Set bus numbers on our root port */ - out_8((u8 *)mbase + PCI_PRIMARY_BUS, 0); - out_8((u8 *)mbase + PCI_SECONDARY_BUS, 1); - out_8((u8 *)mbase + PCI_SUBORDINATE_BUS, 1); + if (ppc440spe_revB()) { + out_8((u8 *)mbase + PCI_PRIMARY_BUS, 0); + out_8((u8 *)mbase + PCI_SECONDARY_BUS, 1); + out_8((u8 *)mbase + PCI_SUBORDINATE_BUS, 1); + } else { + out_8((u8 *)mbase + PCI_PRIMARY_BUS, 0); + out_8((u8 *)mbase + PCI_SECONDARY_BUS, 0); + } /* * Set up outbound translation to hose->mem_space from PLB From c92409812206ac67a7fa7aae298539a9c3804a46 Mon Sep 17 00:00:00 2001 From: Grzegorz Bernacki Date: Tue, 31 Jul 2007 18:51:48 +0200 Subject: [PATCH 055/259] [ppc440SPe] Graceful recovery from machine check during PCIe configuration During config transactions on the PCIe bus an attempt to scan for a non-existent device can lead to a machine check exception with certain peripheral devices. In order to avoid crashing in such scenarios the instrumented versions of the config cycle read routines are introduced, so the exceptions fixups framework can gracefully recover. Signed-off-by: Grzegorz Bernacki Acked-by: Rafal Jaworowski --- cpu/ppc4xx/440spe_pcie.c | 36 ++++++++++++++++++++++++++++++++---- cpu/ppc4xx/440spe_pcie.h | 19 +++++++++++++++++-- cpu/ppc4xx/traps.c | 11 ++++++++--- lib_ppc/extable.c | 2 +- 4 files changed, 58 insertions(+), 10 deletions(-) diff --git a/cpu/ppc4xx/440spe_pcie.c b/cpu/ppc4xx/440spe_pcie.c index 7b27e8707..bf68cc1e9 100644 --- a/cpu/ppc4xx/440spe_pcie.c +++ b/cpu/ppc4xx/440spe_pcie.c @@ -1,5 +1,5 @@ /* - * (C) Copyright 2006 + * (C) Copyright 2006 - 2007 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * * Copyright (c) 2005 Cisco Systems. All rights reserved. @@ -40,6 +40,34 @@ enum { LNKW_X8 = 0x8 }; +static inline int pcie_in_8(const volatile unsigned char __iomem *addr) +{ + int ret; + + PCIE_IN(lbzx, ret, addr); + + return ret; +} + +static inline int pcie_in_le16(const volatile unsigned short __iomem *addr) +{ + int ret; + + PCIE_IN(lhbrx, ret, addr) + + return ret; +} + +static inline unsigned pcie_in_le32(const volatile unsigned __iomem *addr) +{ + unsigned ret; + + PCIE_IN(lwbrx, ret, addr); + + return ret; +} + + static int pcie_read_config(struct pci_controller *hose, unsigned int devfn, int offset, int len, u32 *val) { @@ -55,13 +83,13 @@ static int pcie_read_config(struct pci_controller *hose, unsigned int devfn, switch (len) { case 1: - *val = in_8(hose->cfg_data + offset); + *val = pcie_in_8(hose->cfg_data + offset); break; case 2: - *val = in_le16((u16 *)(hose->cfg_data + offset)); + *val = pcie_in_le16((u16 *)(hose->cfg_data + offset)); break; default: - *val = in_le32((u32 *)(hose->cfg_data + offset)); + *val = pcie_in_le32((u32*)(hose->cfg_data + offset)); break; } return 0; diff --git a/cpu/ppc4xx/440spe_pcie.h b/cpu/ppc4xx/440spe_pcie.h index 2becc7772..eb7cecf82 100644 --- a/cpu/ppc4xx/440spe_pcie.h +++ b/cpu/ppc4xx/440spe_pcie.h @@ -145,8 +145,8 @@ #define PECFG_PIMEN 0x33c #define PECFG_PIM0LAL 0x340 #define PECFG_PIM0LAH 0x344 -#define PECFG_PIM1LAL 0x348 -#define PECFG_PIM1LAH 0x34c +#define PECFG_PIM1LAL 0x348 +#define PECFG_PIM1LAH 0x34c #define PECFG_PIM01SAL 0x350 #define PECFG_PIM01SAH 0x354 @@ -161,6 +161,21 @@ mtdcr(DCRN_SDR0_CFGADDR, offset); \ mtdcr(DCRN_SDR0_CFGDATA,data);}) +#define PCIE_IN(opcode, ret, addr) \ + __asm__ __volatile__( \ + "sync\n" \ + #opcode " %0,0,%1\n" \ + "1: twi 0,%0,0\n" \ + "isync\n" \ + "b 3f\n" \ + "2: li %0,-1\n" \ + "3:\n" \ + ".section __ex_table,\"a\"\n" \ + ".balign 4\n" \ + ".long 1b,2b\n" \ + ".previous\n" \ + : "=r" (ret) : "r" (addr), "m" (*addr)); + int ppc440spe_init_pcie(void); int ppc440spe_init_pcie_rootport(int port); void yucca_setup_pcie_fpga_rootpoint(int port); diff --git a/cpu/ppc4xx/traps.c b/cpu/ppc4xx/traps.c index 2fcce3de8..6b15a9ea2 100755 --- a/cpu/ppc4xx/traps.c +++ b/cpu/ppc4xx/traps.c @@ -151,12 +151,17 @@ MachineCheckException(struct pt_regs *regs) int uncorr_ecc = 0; #endif - /* Probing PCI using config cycles cause this exception - * when a device is not present. Catch it and return to - * the PCI exception handler. + /* Probing PCI(E) using config cycles may cause this exception + * when a device is not present. To gracefully recover in such + * scenarios config read/write routines need to be instrumented in + * order to return via fixup handler. For examples refer to + * pcie_in_8(), pcie_in_le16() and pcie_in_le32() */ if ((fixup = search_exception_table(regs->nip)) != 0) { regs->nip = fixup; + val = mfspr(MCSR); + /* Clear MCSR */ + mtspr(SPRN_MCSR, val); return; } diff --git a/lib_ppc/extable.c b/lib_ppc/extable.c index 8354411f0..2d995fa30 100644 --- a/lib_ppc/extable.c +++ b/lib_ppc/extable.c @@ -89,7 +89,7 @@ search_exception_table(unsigned long addr) /* if the serial port does not hang in exception, printf can be used */ #if !defined(CFG_SERIAL_HANG_IN_EXCEPTION) if (ex_tab_message) - printf("Bus Fault @ 0x%08lx, fixup 0x%08lx\n", addr, ret); + debug("Bus Fault @ 0x%08lx, fixup 0x%08lx\n", addr, ret); #endif if (ret) return ret; From 9ca8d79de096c65b9b9c867259b3ff4685f775ef Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Thu, 2 Aug 2007 08:33:56 +0200 Subject: [PATCH 056/259] ppc4xx: Code cleanup Signed-off-by: Stefan Roese --- cpu/ppc4xx/traps.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/cpu/ppc4xx/traps.c b/cpu/ppc4xx/traps.c index 6b15a9ea2..de5fde9e2 100755 --- a/cpu/ppc4xx/traps.c +++ b/cpu/ppc4xx/traps.c @@ -161,7 +161,7 @@ MachineCheckException(struct pt_regs *regs) regs->nip = fixup; val = mfspr(MCSR); /* Clear MCSR */ - mtspr(SPRN_MCSR, val); + mtspr(SPRN_MCSR, val); return; } From 537223afa61f64480df31ce440a9cb386df4a814 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Mon, 6 Aug 2007 21:10:17 +0200 Subject: [PATCH 057/259] ppc4xx: Update AMCC Bamboo README doc/README.bamboo As suggested by Eugene O'Brien , here an updated Bamboo README. Signed-off-by: Stefan Roese --- doc/README.bamboo | 62 +++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 62 insertions(+) diff --git a/doc/README.bamboo b/doc/README.bamboo index b50be01ab..e139c6d12 100644 --- a/doc/README.bamboo +++ b/doc/README.bamboo @@ -1,3 +1,65 @@ +The 2 important dipswitches are configured as shown below: + +SW1 (for 33MHz SysClk) +---------------------- +S1 S2 S3 S4 S5 S6 S7 S8 +OFF OFF OFF OFF OFF OFF OFF ON + +SW7 (for Op-Code Flash and Boot Option H) +----------------------------------------- +S1 S2 S3 S4 S5 S6 S7 S8 +OFF OFF OFF ON OFF OFF OFF OFF + +The EEPROM at location 0x52 is loaded with these 16 bytes: +C47042A6 05D7A190 40082350 0d050000 + +SDR0_SDSTP0[ENG]: 1 : PLL's VCO is the source for PLL forward divisors +SDR0_SDSTP0[SRC]: 1 : Feedback originates from PLLOUTB +SDR0_SDSTP0[SEL]: 0 : Feedback selection is PLL output +SDR0_SDSTP0[TUNE]: 1000111000 : 10 <= M <= 22, 600MHz < VCO <= 900MHz +SDR0_SDSTP0[FBDV]: 4 : PLL feedback divisor +SDR0_SDSTP0[FBDVA]: 2 : PLL forward divisor A +SDR0_SDSTP0[FBDVB]: 5 : PLL forward divisor B +SDR0_SDSTP0[PRBDV0]: 1 : PLL primary divisor B +SDR0_SDSTP0[OPBDV0]: 2 : OPB clock divisor +SDR0_SDSTP0[LFBDV]: 1 : PLL local feedback divisor +SDR0_SDSTP0[PERDV0]: 3 : Peripheral clock divisor 0 +SDR0_SDSTP0[MALDV0]: 2 : MAL clock divisor 0 +SDR0_SDSTP0[PCIDV0]: 2 : Sync PCI clock divisor 0 +SDR0_SDSTP0[PLLTIMER]: 7 : PLL locking timer +SDR0_SDSTP0[RW]: 1 : EBC ROM width: 16-bit +SDR0_SDSTP0[RL]: 0 : EBC ROM location: EBC +SDR0_SDSTP0[PAE]: 0 : PCI internal arbiter: disabled +SDR0_SDSTP0[PHCE]: 0 : PCI host configuration: disabled +SDR0_SDSTP0[ZM]: 3 : ZMII mode: RMII mode 100 +SDR0_SDSTP0[CTE]: 0 : CPU trace: disabled +SDR0_SDSTP0[Nto1]: 0 : CPU/PLB ratio N/P: not N to 1 +SDR0_SDSTP0[PAME]: 1 : PCI asynchronous mode: enabled +SDR0_SDSTP0[MEM]: 1 : Multiplex: EMAC +SDR0_SDSTP0[NE]: 0 : NDFC: disabled +SDR0_SDSTP0[NBW]: 0 : NDFC boot width: 8-bit +SDR0_SDSTP0[NBW]: 0 : NDFC boot page selection +SDR0_SDSTP0[NBAC]: 0 : NDFC boot address selection cycle: 3 Addr. Cycles, 1 Col. + 2 Row (512 page size) +SDR0_SDSTP0[NARE]: 0 : NDFC auto read : disabled +SDR0_SDSTP0[NRB]: 0 : NDFC Ready/Busy : Ready +SDR0_SDSTP0[NDRSC]: 33333 : NDFC device reset counter +SDR0_SDSTP0[NCG0]: 0 : NDFC/EBC chip select gating CS0 : EBC +SDR0_SDSTP0[NCG1]: 0 : NDFC/EBC chip select gating CS1 : EBC +SDR0_SDSTP0[NCG2]: 0 : NDFC/EBC chip select gating CS2 : EBC +SDR0_SDSTP0[NCG3]: 0 : NDFC/EBC chip select gating CS3 : EBC +SDR0_SDSTP0[NCRDC]: 3333 : NDFC device read count + +PPC440EP Clocking Configuration + +SysClk is 33.0MHz, M is 20, VCO is 660.0MHz, CPU is 330.0MHz, PLB is 132.0MHz +OPB is 66.0MHz, EBC is 44.0MHz, MAL is 66.0MHz, Sync PCI is 66.0MHz + +The above information is reported by Eugene O'Brien +. Thanks a lot. + +2007-08-06, Stefan Roese +--------------------------------------------------------------------- + The configuration for the AMCC 440EP eval board "Bamboo" was changed to only use 384 kbytes of FLASH for the U-Boot image. This way the redundant environment can be saved in the remaining 2 sectors of the From 9998bd37ead85e93953559720710d3b0685c81e6 Mon Sep 17 00:00:00 2001 From: TsiChungLiew Date: Sun, 5 Aug 2007 03:19:10 -0500 Subject: [PATCH 058/259] Renamed CONFIG_MCFSERIAL to CONFIG_MCFUART Signed-off-by: TsiChungLiew --- drivers/serial/mcfuart.c | 4 ++-- include/configs/M5329EVB.h | 6 ++---- 2 files changed, 4 insertions(+), 6 deletions(-) diff --git a/drivers/serial/mcfuart.c b/drivers/serial/mcfuart.c index f54aabec2..39d4e1816 100644 --- a/drivers/serial/mcfuart.c +++ b/drivers/serial/mcfuart.c @@ -33,7 +33,7 @@ DECLARE_GLOBAL_DATA_PTR; -#ifdef CONFIG_MCFSERIAL +#ifdef CONFIG_MCFUART int serial_init(void) { volatile uart_t *uart; @@ -124,4 +124,4 @@ void serial_setbrg(void) uart->ucr = UART_UCR_RX_ENABLED | UART_UCR_TX_ENABLED; } -#endif /* CONFIG_MCFSERIAL */ +#endif /* CONFIG_MCFUART */ diff --git a/include/configs/M5329EVB.h b/include/configs/M5329EVB.h index d1ac34004..50be03fe3 100644 --- a/include/configs/M5329EVB.h +++ b/include/configs/M5329EVB.h @@ -39,7 +39,8 @@ #undef DEBUG -#define CONFIG_MCFSERIAL +#define CONFIG_MCFUART +#define CFG_UART_PORT (0) #define CONFIG_BAUDRATE 115200 #define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 } @@ -84,9 +85,6 @@ # endif /* CFG_DISCOVER_PHY */ #endif -#define CONFIG_MCFUART -#define CFG_UART_PORT (0) - #define CONFIG_MCFRTC #undef RTC_DEBUG From 9e737d8476e7d6a596d16caaf6a3853a9a1190a2 Mon Sep 17 00:00:00 2001 From: TsiChungLiew Date: Sun, 5 Aug 2007 03:30:44 -0500 Subject: [PATCH 059/259] Declared attributes of void __mii_init(void) as an alias for int mii_init(void) Signed-off-by: TsiChungLiew --- board/freescale/m5329evb/mii.c | 4 +++- drivers/net/mcffec.c | 2 +- include/common.h | 2 +- 3 files changed, 5 insertions(+), 3 deletions(-) diff --git a/board/freescale/m5329evb/mii.c b/board/freescale/m5329evb/mii.c index 691b14459..68dc04fd9 100644 --- a/board/freescale/m5329evb/mii.c +++ b/board/freescale/m5329evb/mii.c @@ -203,7 +203,9 @@ int mii_discover_phy(struct eth_device *dev) } #endif /* CFG_DISCOVER_PHY */ -void mii_init(void) +int mii_init(void) __attribute__((weak,alias("__mii_init"))); + +void __mii_init(void) { volatile fec_t *fecp; struct fec_info_s *info; diff --git a/drivers/net/mcffec.c b/drivers/net/mcffec.c index 11f672189..fde1aaecb 100644 --- a/drivers/net/mcffec.c +++ b/drivers/net/mcffec.c @@ -101,7 +101,7 @@ void fec_reset(struct eth_device *dev); extern int fecpin_setclear(struct eth_device *dev, int setclear); #ifdef CFG_DISCOVER_PHY -extern void mii_init(void); +extern void __mii_init(void); extern uint mii_send(uint mii_cmd); extern int mii_discover_phy(struct eth_device *dev); extern int mcffec_miiphy_read(char *devname, unsigned char addr, diff --git a/include/common.h b/include/common.h index 23f93907e..a1a329071 100644 --- a/include/common.h +++ b/include/common.h @@ -539,7 +539,7 @@ ulong bootcount_load (void); #define BOOTCOUNT_MAGIC 0xB001C041 /* $(CPU)/.../ */ -void mii_init (void); +/*void mii_init (void);*/ /* $(CPU)/.../lcd.c */ ulong lcd_setmem (ulong); From 6fde84a44b7e575ea80fe0e2d5be3b6f73d1e630 Mon Sep 17 00:00:00 2001 From: TsiChungLiew Date: Sun, 5 Aug 2007 03:43:30 -0500 Subject: [PATCH 060/259] Moved sync() from board file to include/asm-m68k/io.h Signed-off-by: TsiChungLiew --- board/freescale/m5329evb/m5329evb.c | 7 ------- include/asm-m68k/io.h | 7 +++++++ 2 files changed, 7 insertions(+), 7 deletions(-) diff --git a/board/freescale/m5329evb/m5329evb.c b/board/freescale/m5329evb/m5329evb.c index d180b6f43..058cda5b2 100644 --- a/board/freescale/m5329evb/m5329evb.c +++ b/board/freescale/m5329evb/m5329evb.c @@ -87,10 +87,3 @@ int testdram(void) return (0); } -#ifdef CFG_FLASH_CFI -void sync(void) -{ - /* This sync function is PowerPC intruction, - coldfire does not have this instruction. Dummy function */ -} -#endif /* CFG_FLASH_CFI */ diff --git a/include/asm-m68k/io.h b/include/asm-m68k/io.h index 8dea02aba..114efb15d 100644 --- a/include/asm-m68k/io.h +++ b/include/asm-m68k/io.h @@ -211,4 +211,11 @@ extern inline void out_be32(volatile unsigned *addr, int val) *addr = val; } +static inline void sync(void) +{ + /* This sync function is for PowerPC or other architecture instruction + * ColdFire does not have this instruction. Dummy function, added for + * compatibility (CFI driver) + */ +} #endif /* __ASM_M68K_IO_H__ */ From 8d1d66af54d305de29d0bbf4aa8c9e6375f7f731 Mon Sep 17 00:00:00 2001 From: TsiChungLiew Date: Sun, 5 Aug 2007 03:55:21 -0500 Subject: [PATCH 061/259] Added uart_gpio_conf() in serial_init(), seperated uart port configuration from cpu_init() to uart_gpio_conf() Signed-off-by: TsiChungLiew --- cpu/mcf532x/cpu_init.c | 35 +++++++++++++++++++++-------------- drivers/serial/mcfuart.c | 4 ++++ 2 files changed, 25 insertions(+), 14 deletions(-) diff --git a/cpu/mcf532x/cpu_init.c b/cpu/mcf532x/cpu_init.c index 32711a174..5a26ae031 100644 --- a/cpu/mcf532x/cpu_init.c +++ b/cpu/mcf532x/cpu_init.c @@ -60,20 +60,6 @@ void cpu_init_f(void) scm2->pacrg = 0; scm1->pacrh = 0; - /* Setup Ports: */ - switch (CFG_UART_PORT) { - case 0: - gpio->par_uart = (GPIO_PAR_UART_TXD0 | GPIO_PAR_UART_RXD0); - break; - case 1: - gpio->par_uart = - (GPIO_PAR_UART_TXD1(3) | GPIO_PAR_UART_RXD1(3)); - break; - case 2: - gpio->par_uart = (GPIO_PAR_TIN3_URXD2 | GPIO_PAR_TIN2_UTXD2); - break; - } - /* Port configuration */ gpio->par_cs = 0x3E; @@ -124,3 +110,24 @@ int cpu_init_r(void) { return (0); } + +void uart_port_conf(void) +{ + volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; + + /* Setup Ports: */ + switch (CFG_UART_PORT) { + case 0: + gpio->par_uart = (GPIO_PAR_UART_TXD0 | GPIO_PAR_UART_RXD0); + break; + case 1: + gpio->par_uart = + (GPIO_PAR_UART_TXD1(3) | GPIO_PAR_UART_RXD1(3)); + break; + case 2: + gpio->par_timer &= 0x0F; + gpio->par_timer |= (GPIO_PAR_TIN3_URXD2 | GPIO_PAR_TIN2_UTXD2); + break; + } +} + diff --git a/drivers/serial/mcfuart.c b/drivers/serial/mcfuart.c index 39d4e1816..bc7077de7 100644 --- a/drivers/serial/mcfuart.c +++ b/drivers/serial/mcfuart.c @@ -34,6 +34,8 @@ DECLARE_GLOBAL_DATA_PTR; #ifdef CONFIG_MCFUART +extern void uart_port_conf(void); + int serial_init(void) { volatile uart_t *uart; @@ -41,6 +43,8 @@ int serial_init(void) uart = (volatile uart_t *)(CFG_UART_BASE); + uart_port_conf(); + /* write to SICR: SIM2 = uart mode,dcd does not affect rx */ uart->ucr = UART_UCR_RESET_RX; uart->ucr = UART_UCR_RESET_TX; From 99c03c175d2689093176facf17c58ce2cb320001 Mon Sep 17 00:00:00 2001 From: TsiChungLiew Date: Sun, 5 Aug 2007 03:58:52 -0500 Subject: [PATCH 062/259] Changed CFG_CLK to gd->bus_clk for CFG_TIMER_PRESCALER. Added DECLARE_GLOBAL_DATA_PTR for time.c Signed-off-by: TsiChungLiew --- include/asm-m68k/immap.h | 2 +- lib_m68k/time.c | 2 ++ 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/include/asm-m68k/immap.h b/include/asm-m68k/immap.h index 4e238c3f5..7c267af56 100644 --- a/include/asm-m68k/immap.h +++ b/include/asm-m68k/immap.h @@ -41,7 +41,7 @@ #define CFG_TMRINTR_NO (INT0_HI_DTMR1) #define CFG_TMRINTR_MASK (INTC_IPRH_INT33) #define CFG_TMRINTR_PRI (6) -#define CFG_TIMER_PRESCALER (((CFG_CLK / 1000000) - 1) << 8) +#define CFG_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8) #endif #ifdef CONFIG_MCFPIT diff --git a/lib_m68k/time.c b/lib_m68k/time.c index 267a3cdbc..3dbce0721 100644 --- a/lib_m68k/time.c +++ b/lib_m68k/time.c @@ -48,6 +48,8 @@ #include #endif +DECLARE_GLOBAL_DATA_PTR; + static ulong timestamp; #if defined(CONFIG_M5282) || defined(CONFIG_M5271) static unsigned short lastinc; From eaf9e447beb3e498818ef8ad0b8c1597cd506149 Mon Sep 17 00:00:00 2001 From: TsiChungLiew Date: Sun, 5 Aug 2007 04:11:20 -0500 Subject: [PATCH 063/259] Added I2C support Signed-off-by: TsiChungLiew --- include/asm-m68k/fsl_i2c.h | 86 ++++++++++++++++++++++++++++++++++++++ include/configs/M5329EVB.h | 52 +++++++++++++---------- 2 files changed, 117 insertions(+), 21 deletions(-) create mode 100644 include/asm-m68k/fsl_i2c.h diff --git a/include/asm-m68k/fsl_i2c.h b/include/asm-m68k/fsl_i2c.h new file mode 100644 index 000000000..4f7134132 --- /dev/null +++ b/include/asm-m68k/fsl_i2c.h @@ -0,0 +1,86 @@ +/* + * Freescale I2C Controller + * + * Copyright 2006 Freescale Semiconductor, Inc. + * + * Based on earlier versions by Gleb Natapov , + * Xianghua Xiao , Eran Liberty (liberty@freescale.com), + * and Jeff Brown. + * Some bits are taken from linux driver writen by adrian@humboldt.co.uk. + * + * This software may be used and distributed according to the + * terms of the GNU Public License, Version 2, incorporated + * herein by reference. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * Version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _ASM_FSL_I2C_H_ +#define _ASM_FSL_I2C_H_ + +#include + +typedef struct fsl_i2c { + + u8 adr; /* I2C slave address */ + u8 res0[3]; +#define I2C_ADR 0xFE +#define I2C_ADR_SHIFT 1 +#define I2C_ADR_RES ~(I2C_ADR) + + u8 fdr; /* I2C frequency divider register */ + u8 res1[3]; +#define IC2_FDR 0x3F +#define IC2_FDR_SHIFT 0 +#define IC2_FDR_RES ~(IC2_FDR) + + u8 cr; /* I2C control redister */ + u8 res2[3]; +#define I2C_CR_MEN 0x80 +#define I2C_CR_MIEN 0x40 +#define I2C_CR_MSTA 0x20 +#define I2C_CR_MTX 0x10 +#define I2C_CR_TXAK 0x08 +#define I2C_CR_RSTA 0x04 +#define I2C_CR_BCST 0x01 + + u8 sr; /* I2C status register */ + u8 res3[3]; +#define I2C_SR_MCF 0x80 +#define I2C_SR_MAAS 0x40 +#define I2C_SR_MBB 0x20 +#define I2C_SR_MAL 0x10 +#define I2C_SR_BCSTM 0x08 +#define I2C_SR_SRW 0x04 +#define I2C_SR_MIF 0x02 +#define I2C_SR_RXAK 0x01 + + u8 dr; /* I2C data register */ + u8 res4[3]; +#define I2C_DR 0xFF +#define I2C_DR_SHIFT 0 +#define I2C_DR_RES ~(I2C_DR) + + u8 dfsrr; /* I2C digital filter sampling rate register */ + u8 res5[3]; +#define I2C_DFSRR 0x3F +#define I2C_DFSRR_SHIFT 0 +#define I2C_DFSRR_RES ~(I2C_DR) + + /* Fill out the reserved block */ + u8 res6[0xE8]; +} fsl_i2c_t; + +#endif /* _ASM_I2C_H_ */ diff --git a/include/configs/M5329EVB.h b/include/configs/M5329EVB.h index 50be03fe3..605684bee 100644 --- a/include/configs/M5329EVB.h +++ b/include/configs/M5329EVB.h @@ -52,6 +52,7 @@ CFG_CMD_DATE | \ CFG_CMD_ELF | \ CFG_CMD_FLASH | \ + CFG_CMD_I2C | \ (CFG_CMD_LOADB | CFG_CMD_LOADS) | \ CFG_CMD_MEMORY | \ CFG_CMD_MISC | \ @@ -65,15 +66,15 @@ #define CONFIG_MCFFEC #ifdef CONFIG_MCFFEC -# define CONFIG_NET_MULTI 1 +# define CONFIG_NET_MULTI 1 # define CONFIG_MII 1 # define CFG_DISCOVER_PHY # define CFG_RX_ETH_BUFFER 8 # define CFG_FAULT_ECHO_LINK_DOWN -# define CFG_FEC0_PINMUX 0 -# define CFG_FEC0_MIIBASE CFG_FEC0_IOBASE -# define MCFFEC_TOUT_LOOP 50000 +# define CFG_FEC0_PINMUX 0 +# define CFG_FEC0_MIIBASE CFG_FEC0_IOBASE +# define MCFFEC_TOUT_LOOP 50000 /* If CFG_DISCOVER_PHY is not defined - hardcoded */ # ifndef CFG_DISCOVER_PHY # define FECDUPLEX FULL @@ -92,14 +93,23 @@ #define CONFIG_MCFTMR #undef CONFIG_MCFPIT +/* I2C */ +#define CONFIG_FSL_I2C +#define CONFIG_HARD_I2C /* I2C with hw support */ +#undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CFG_I2C_SPEED 80000 +#define CFG_I2C_SLAVE 0x7F +#define CFG_I2C_OFFSET 0x58000 +#define CFG_IMMR CFG_MBAR + /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ #include #define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */ #ifdef CONFIG_MCFFEC -# define CONFIG_ETHADDR 00:e0:0c:bc:e5:60 -# define CONFIG_IPADDR 192.162.1.2 -# define CONFIG_NETMASK 255.255.255.0 -# define CONFIG_SERVERIP 192.162.1.1 +# define CONFIG_ETHADDR 00:e0:0c:bc:e5:60 +# define CONFIG_IPADDR 192.162.1.2 +# define CONFIG_NETMASK 255.255.255.0 +# define CONFIG_SERVERIP 192.162.1.1 # define CONFIG_GATEWAYIP 192.162.1.1 # define CONFIG_OVERWRITE_ETHADDR_ONCE #endif /* FEC_ENET */ @@ -117,26 +127,26 @@ "save\0" \ "" -#define CONFIG_PRAM 512 /* 512 KB */ -#define CFG_PROMPT "-> " +#define CONFIG_PRAM 512 /* 512 KB */ +#define CFG_PROMPT "-> " #define CFG_LONGHELP /* undef to save memory */ #if (CONFIG_COMMANDS & CFG_CMD_KGDB) -# define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +# define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else -# define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +# define CFG_CBSIZE 256 /* Console I/O Buffer Size */ #endif #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_MAXARGS 16 /* max number of command args */ #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ #define CFG_LOAD_ADDR 0x40010000 -#define CFG_HZ 1000 -#define CFG_CLK 80000000 -#define CFG_CPU_CLK CFG_CLK * 3 +#define CFG_HZ 1000 +#define CFG_CLK 80000000 +#define CFG_CPU_CLK CFG_CLK * 3 -#define CFG_MBAR 0xFC000000 +#define CFG_MBAR 0xFC000000 /* * Low Level Configuration Settings @@ -190,13 +200,13 @@ # define CFG_FLASH_CFI_DRIVER 1 # define CFG_FLASH_SIZE 0x800000 /* Max size that the board might have */ # define CFG_FLASH_CFI_WIDTH FLASH_CFI_16BIT -# define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -# define CFG_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ +# define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +# define CFG_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ # define CFG_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ #endif -#define CFG_FLASH_BASE 0 -#define CFG_FLASH0_BASE (CFG_CS0_BASE << 16) +#define CFG_FLASH_BASE 0 +#define CFG_FLASH0_BASE (CFG_CS0_BASE << 16) /* Configuration for environment * Environment is embedded in u-boot in the second sector of the flash From 1a33ce65a4c51a69190dd8c408f9e1c62a66e94f Mon Sep 17 00:00:00 2001 From: TsiChungLiew Date: Sun, 5 Aug 2007 04:31:18 -0500 Subject: [PATCH 064/259] Added NAND support Signed-off-by: TsiChungLiew --- board/freescale/m5329evb/Makefile | 2 +- board/freescale/m5329evb/nand.c | 115 +++++++++++++++++++++++++ include/asm-m68k/bitops.h | 39 +++++++++ include/asm-m68k/errno.h | 138 ++++++++++++++++++++++++++++++ include/configs/M5329EVB.h | 27 +++++- 5 files changed, 317 insertions(+), 4 deletions(-) create mode 100644 board/freescale/m5329evb/nand.c create mode 100644 include/asm-m68k/errno.h diff --git a/board/freescale/m5329evb/Makefile b/board/freescale/m5329evb/Makefile index 74c252869..ab0f11e9d 100644 --- a/board/freescale/m5329evb/Makefile +++ b/board/freescale/m5329evb/Makefile @@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a -COBJS = $(BOARD).o mii.o +COBJS = $(BOARD).o mii.o nand.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/board/freescale/m5329evb/nand.c b/board/freescale/m5329evb/nand.c new file mode 100644 index 000000000..2a4ca7137 --- /dev/null +++ b/board/freescale/m5329evb/nand.c @@ -0,0 +1,115 @@ +/* + * (C) Copyright 2000-2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#if (CONFIG_COMMANDS & CFG_CMD_NAND) +#include +#include + +#define SET_CLE 0x10 +#define CLR_CLE ~SET_CLE +#define SET_ALE 0x08 +#define CLR_ALE ~SET_ALE + +static void nand_hwcontrol(struct mtd_info *mtdinfo, int cmd) +{ + struct nand_chip *this = mtdinfo->priv; + volatile fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS; + u32 nand_baseaddr = (u32) this->IO_ADDR_W; + + switch (cmd) { + case NAND_CTL_SETNCE: + case NAND_CTL_CLRNCE: + break; + case NAND_CTL_SETCLE: + nand_baseaddr |= SET_CLE; + break; + case NAND_CTL_CLRCLE: + nand_baseaddr &= CLR_CLE; + break; + case NAND_CTL_SETALE: + nand_baseaddr |= SET_ALE; + break; + case NAND_CTL_CLRALE: + nand_baseaddr |= CLR_ALE; + break; + case NAND_CTL_SETWP: + fbcs->csmr2 |= CSMR_WP; + break; + case NAND_CTL_CLRWP: + fbcs->csmr2 &= ~CSMR_WP; + break; + } + this->IO_ADDR_W = (void __iomem *)(nand_baseaddr); +} + +static void nand_write_byte(struct mtd_info *mtdinfo, u_char byte) +{ + struct nand_chip *this = mtdinfo->priv; + *((volatile u8 *)(this->IO_ADDR_W)) = byte; +} + +static u8 nand_read_byte(struct mtd_info *mtdinfo) +{ + struct nand_chip *this = mtdinfo->priv; + return (u8) (*((volatile u8 *)this->IO_ADDR_R)); +} + +static int nand_dev_ready(struct mtd_info *mtdinfo) +{ + return 1; +} + +int board_nand_init(struct nand_chip *nand) +{ + volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; + + *((volatile u16 *)CFG_LATCH_ADDR) |= 0x0004; + + /* set up pin configuration */ + gpio->par_timer &= ~GPIO_PAR_TIN3_TIN3; + gpio->pddr_timer |= 0x08; + gpio->ppd_timer |= 0x08; + gpio->pclrr_timer = 0; + gpio->podr_timer = 0; + + nand->chip_delay = 50; + nand->eccmode = NAND_ECC_SOFT; + nand->hwcontrol = nand_hwcontrol; + nand->read_byte = nand_read_byte; + nand->write_byte = nand_write_byte; + nand->dev_ready = nand_dev_ready; + + return 0; +} +#endif + diff --git a/include/asm-m68k/bitops.h b/include/asm-m68k/bitops.h index 32837142c..0f9e8abe9 100644 --- a/include/asm-m68k/bitops.h +++ b/include/asm-m68k/bitops.h @@ -15,4 +15,43 @@ extern int test_and_set_bit(int nr, volatile void *addr); extern int test_and_clear_bit(int nr, volatile void *addr); extern int test_and_change_bit(int nr, volatile void *addr); +#ifdef __KERNEL__ + +/* + * ffs: find first bit set. This is defined the same way as + * the libc and compiler builtin ffs routines, therefore + * differs in spirit from the above ffz (man ffs). + */ +extern __inline__ int ffs(int x) +{ + int r = 1; + + if (!x) + return 0; + if (!(x & 0xffff)) { + x >>= 16; + r += 16; + } + if (!(x & 0xff)) { + x >>= 8; + r += 8; + } + if (!(x & 0xf)) { + x >>= 4; + r += 4; + } + if (!(x & 3)) { + x >>= 2; + r += 2; + } + if (!(x & 1)) { + x >>= 1; + r += 1; + } + return r; +} +#define __ffs(x) (ffs(x) - 1) + +#endif /* __KERNEL__ */ + #endif /* _M68K_BITOPS_H */ diff --git a/include/asm-m68k/errno.h b/include/asm-m68k/errno.h new file mode 100644 index 000000000..ff364b820 --- /dev/null +++ b/include/asm-m68k/errno.h @@ -0,0 +1,138 @@ +#ifndef _PPC_ERRNO_H +#define _PPC_ERRNO_H + +#define EPERM 1 /* Operation not permitted */ +#define ENOENT 2 /* No such file or directory */ +#define ESRCH 3 /* No such process */ +#define EINTR 4 /* Interrupted system call */ +#define EIO 5 /* I/O error */ +#define ENXIO 6 /* No such device or address */ +#define E2BIG 7 /* Arg list too long */ +#define ENOEXEC 8 /* Exec format error */ +#define EBADF 9 /* Bad file number */ +#define ECHILD 10 /* No child processes */ +#define EAGAIN 11 /* Try again */ +#define ENOMEM 12 /* Out of memory */ +#define EACCES 13 /* Permission denied */ +#define EFAULT 14 /* Bad address */ +#define ENOTBLK 15 /* Block device required */ +#define EBUSY 16 /* Device or resource busy */ +#define EEXIST 17 /* File exists */ +#define EXDEV 18 /* Cross-device link */ +#define ENODEV 19 /* No such device */ +#define ENOTDIR 20 /* Not a directory */ +#define EISDIR 21 /* Is a directory */ +#define EINVAL 22 /* Invalid argument */ +#define ENFILE 23 /* File table overflow */ +#define EMFILE 24 /* Too many open files */ +#define ENOTTY 25 /* Not a typewriter */ +#define ETXTBSY 26 /* Text file busy */ +#define EFBIG 27 /* File too large */ +#define ENOSPC 28 /* No space left on device */ +#define ESPIPE 29 /* Illegal seek */ +#define EROFS 30 /* Read-only file system */ +#define EMLINK 31 /* Too many links */ +#define EPIPE 32 /* Broken pipe */ +#define EDOM 33 /* Math argument out of domain of func */ +#define ERANGE 34 /* Math result not representable */ +#define EDEADLK 35 /* Resource deadlock would occur */ +#define ENAMETOOLONG 36 /* File name too long */ +#define ENOLCK 37 /* No record locks available */ +#define ENOSYS 38 /* Function not implemented */ +#define ENOTEMPTY 39 /* Directory not empty */ +#define ELOOP 40 /* Too many symbolic links encountered */ +#define EWOULDBLOCK EAGAIN /* Operation would block */ +#define ENOMSG 42 /* No message of desired type */ +#define EIDRM 43 /* Identifier removed */ +#define ECHRNG 44 /* Channel number out of range */ +#define EL2NSYNC 45 /* Level 2 not synchronized */ +#define EL3HLT 46 /* Level 3 halted */ +#define EL3RST 47 /* Level 3 reset */ +#define ELNRNG 48 /* Link number out of range */ +#define EUNATCH 49 /* Protocol driver not attached */ +#define ENOCSI 50 /* No CSI structure available */ +#define EL2HLT 51 /* Level 2 halted */ +#define EBADE 52 /* Invalid exchange */ +#define EBADR 53 /* Invalid request descriptor */ +#define EXFULL 54 /* Exchange full */ +#define ENOANO 55 /* No anode */ +#define EBADRQC 56 /* Invalid request code */ +#define EBADSLT 57 /* Invalid slot */ +#define EDEADLOCK 58 /* File locking deadlock error */ +#define EBFONT 59 /* Bad font file format */ +#define ENOSTR 60 /* Device not a stream */ +#define ENODATA 61 /* No data available */ +#define ETIME 62 /* Timer expired */ +#define ENOSR 63 /* Out of streams resources */ +#define ENONET 64 /* Machine is not on the network */ +#define ENOPKG 65 /* Package not installed */ +#define EREMOTE 66 /* Object is remote */ +#define ENOLINK 67 /* Link has been severed */ +#define EADV 68 /* Advertise error */ +#define ESRMNT 69 /* Srmount error */ +#define ECOMM 70 /* Communication error on send */ +#define EPROTO 71 /* Protocol error */ +#define EMULTIHOP 72 /* Multihop attempted */ +#define EDOTDOT 73 /* RFS specific error */ +#define EBADMSG 74 /* Not a data message */ +#define EOVERFLOW 75 /* Value too large for defined data type */ +#define ENOTUNIQ 76 /* Name not unique on network */ +#define EBADFD 77 /* File descriptor in bad state */ +#define EREMCHG 78 /* Remote address changed */ +#define ELIBACC 79 /* Can not access a needed shared library */ +#define ELIBBAD 80 /* Accessing a corrupted shared library */ +#define ELIBSCN 81 /* .lib section in a.out corrupted */ +#define ELIBMAX 82 /* Attempting to link in too many shared libraries */ +#define ELIBEXEC 83 /* Cannot exec a shared library directly */ +#define EILSEQ 84 /* Illegal byte sequence */ +#define ERESTART 85 /* Interrupted system call should be restarted */ +#define ESTRPIPE 86 /* Streams pipe error */ +#define EUSERS 87 /* Too many users */ +#define ENOTSOCK 88 /* Socket operation on non-socket */ +#define EDESTADDRREQ 89 /* Destination address required */ +#define EMSGSIZE 90 /* Message too long */ +#define EPROTOTYPE 91 /* Protocol wrong type for socket */ +#define ENOPROTOOPT 92 /* Protocol not available */ +#define EPROTONOSUPPORT 93 /* Protocol not supported */ +#define ESOCKTNOSUPPORT 94 /* Socket type not supported */ +#define EOPNOTSUPP 95 /* Operation not supported on transport endpoint */ +#define EPFNOSUPPORT 96 /* Protocol family not supported */ +#define EAFNOSUPPORT 97 /* Address family not supported by protocol */ +#define EADDRINUSE 98 /* Address already in use */ +#define EADDRNOTAVAIL 99 /* Cannot assign requested address */ +#define ENETDOWN 100 /* Network is down */ +#define ENETUNREACH 101 /* Network is unreachable */ +#define ENETRESET 102 /* Network dropped connection because of reset */ +#define ECONNABORTED 103 /* Software caused connection abort */ +#define ECONNRESET 104 /* Connection reset by peer */ +#define ENOBUFS 105 /* No buffer space available */ +#define EISCONN 106 /* Transport endpoint is already connected */ +#define ENOTCONN 107 /* Transport endpoint is not connected */ +#define ESHUTDOWN 108 /* Cannot send after transport endpoint shutdown */ +#define ETOOMANYREFS 109 /* Too many references: cannot splice */ +#define ETIMEDOUT 110 /* Connection timed out */ +#define ECONNREFUSED 111 /* Connection refused */ +#define EHOSTDOWN 112 /* Host is down */ +#define EHOSTUNREACH 113 /* No route to host */ +#define EALREADY 114 /* Operation already in progress */ +#define EINPROGRESS 115 /* Operation now in progress */ +#define ESTALE 116 /* Stale NFS file handle */ +#define EUCLEAN 117 /* Structure needs cleaning */ +#define ENOTNAM 118 /* Not a XENIX named type file */ +#define ENAVAIL 119 /* No XENIX semaphores available */ +#define EISNAM 120 /* Is a named type file */ +#define EREMOTEIO 121 /* Remote I/O error */ +#define EDQUOT 122 /* Quota exceeded */ + +#define ENOMEDIUM 123 /* No medium found */ +#define EMEDIUMTYPE 124 /* Wrong medium type */ + +/* Should never be seen by user programs */ +#define ERESTARTSYS 512 +#define ERESTARTNOINTR 513 +#define ERESTARTNOHAND 514 /* restart if no handler.. */ +#define ENOIOCTLCMD 515 /* No ioctl command */ + +#define _LAST_ERRNO 515 + +#endif diff --git a/include/configs/M5329EVB.h b/include/configs/M5329EVB.h index 605684bee..6a7e052a0 100644 --- a/include/configs/M5329EVB.h +++ b/include/configs/M5329EVB.h @@ -47,7 +47,7 @@ #undef CONFIG_WATCHDOG #define CONFIG_WATCHDOG_TIMEOUT 5000 /* timeout in milliseconds, max timeout is 6.71sec */ -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ +#define DEFAULT_COMMANDS ( CONFIG_CMD_DFL | \ CFG_CMD_CACHE | \ CFG_CMD_DATE | \ CFG_CMD_ELF | \ @@ -62,6 +62,12 @@ CFG_CMD_REGINFO \ ) +#ifdef NANDFLASH_SIZE +# define CONFIG_COMMANDS (DEFAULT_COMMANDS | CFG_CMD_NAND) +#else +# define CONFIG_COMMANDS (DEFAULT_COMMANDS) +#endif + #define CFG_UNIFY_CACHE #define CONFIG_MCFFEC @@ -148,6 +154,8 @@ #define CFG_MBAR 0xFC000000 +#define CFG_LATCH_ADDR (CFG_CS1_BASE + 0x80000) + /* * Low Level Configuration Settings * (address mappings, register initial values, etc.) @@ -205,6 +213,19 @@ # define CFG_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ #endif +#ifdef NANDFLASH_SIZE +# define CFG_MAX_NAND_DEVICE 1 +# define CFG_NAND_BASE (CFG_CS2_BASE << 16) +# define CFG_NAND_SIZE 1 +# define CFG_NAND_BASE_LIST { CFG_NAND_BASE } +# define NAND_MAX_CHIPS 1 +# define NAND_ALLOW_ERASE_ALL 1 +# define CONFIG_JFFS2_NAND 1 +# define CONFIG_JFFS2_DEV "nand0" +# define CONFIG_JFFS2_PART_SIZE (CFG_CS2_MASK & ~1) +# define CONFIG_JFFS2_PART_OFFSET 0x00000000 +#endif + #define CFG_FLASH_BASE 0 #define CFG_FLASH0_BASE (CFG_CS0_BASE << 16) @@ -241,8 +262,8 @@ #define CFG_CS1_CTRL 0x002A3780 #ifdef NANDFLASH_SIZE -#define CFG_CS2_BASE 0x00800000 -#define CFG_CS2_MASK 0x00ff0001 +#define CFG_CS2_BASE 0x2000 +#define CFG_CS2_MASK ((NANDFLASH_SIZE << 20) | 1) #define CFG_CS2_CTRL 0x00001f60 #endif From a41de1f0d373e09c782dea558385a06247111ba5 Mon Sep 17 00:00:00 2001 From: TsiChungLiew Date: Sun, 5 Aug 2007 05:15:18 -0500 Subject: [PATCH 065/259] Port enabled for I2C signals and chipselects port configuration. Signed-off-by: TsiChungLiew --- cpu/mcf532x/cpu_init.c | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/cpu/mcf532x/cpu_init.c b/cpu/mcf532x/cpu_init.c index 5a26ae031..eb9b7a407 100644 --- a/cpu/mcf532x/cpu_init.c +++ b/cpu/mcf532x/cpu_init.c @@ -61,7 +61,7 @@ void cpu_init_f(void) scm1->pacrh = 0; /* Port configuration */ - gpio->par_cs = 0x3E; + gpio->par_cs = 0; #if (defined(CFG_CS0_BASE) && defined(CFG_CS0_MASK) && defined(CFG_CS0_CTRL)) fbcs->csar0 = CFG_CS0_BASE; @@ -71,35 +71,44 @@ void cpu_init_f(void) #if (defined(CFG_CS1_BASE) && defined(CFG_CS1_MASK) && defined(CFG_CS1_CTRL)) /* Latch chipselect */ + gpio->par_cs |= GPIO_PAR_CS1; fbcs->csar1 = CFG_CS1_BASE; fbcs->cscr1 = CFG_CS1_CTRL; fbcs->csmr1 = CFG_CS1_MASK; #endif #if (defined(CFG_CS2_BASE) && defined(CFG_CS2_MASK) && defined(CFG_CS2_CTRL)) + gpio->par_cs |= GPIO_PAR_CS2; fbcs->csar2 = CFG_CS2_BASE; fbcs->cscr2 = CFG_CS2_CTRL; fbcs->csmr2 = CFG_CS2_MASK; #endif #if (defined(CFG_CS3_BASE) && defined(CFG_CS3_MASK) && defined(CFG_CS3_CTRL)) + gpio->par_cs |= GPIO_PAR_CS3; fbcs->csar3 = CFG_CS3_BASE; fbcs->cscr3 = CFG_CS3_CTRL; fbcs->csmr3 = CFG_CS3_MASK; #endif #if (defined(CFG_CS4_BASE) && defined(CFG_CS4_MASK) && defined(CFG_CS4_CTRL)) + gpio->par_cs |= GPIO_PAR_CS4; fbcs->csar4 = CFG_CS4_BASE; fbcs->cscr4 = CFG_CS4_CTRL; fbcs->csmr4 = CFG_CS4_MASK; #endif #if (defined(CFG_CS5_BASE) && defined(CFG_CS5_MASK) && defined(CFG_CS5_CTRL)) + gpio->par_cs |= GPIO_PAR_CS5; fbcs->csar5 = CFG_CS5_BASE; fbcs->cscr5 = CFG_CS5_CTRL; fbcs->csmr5 = CFG_CS5_MASK; #endif +#ifdef CONFIG_FSL_I2C + gpio->par_feci2c = GPIO_PAR_FECI2C_SCL_SCL | GPIO_PAR_FECI2C_SDA_SDA; +#endif + icache_enable(); } From 3ba4c2d68f6541db4677b4aea12071f56e6ff6e6 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Wed, 8 Aug 2007 09:54:26 +0200 Subject: [PATCH 066/259] Coding style cleanup Signed-off-by: Stefan Roese --- board/freescale/m5329evb/m5329evb.c | 1 - board/freescale/m5329evb/nand.c | 103 ++++++++++++++-------------- cpu/mcf532x/cpu_init.c | 11 ++- 3 files changed, 56 insertions(+), 59 deletions(-) diff --git a/board/freescale/m5329evb/m5329evb.c b/board/freescale/m5329evb/m5329evb.c index 058cda5b2..242eb1a18 100644 --- a/board/freescale/m5329evb/m5329evb.c +++ b/board/freescale/m5329evb/m5329evb.c @@ -86,4 +86,3 @@ int testdram(void) return (0); } - diff --git a/board/freescale/m5329evb/nand.c b/board/freescale/m5329evb/nand.c index 2a4ca7137..2272a2446 100644 --- a/board/freescale/m5329evb/nand.c +++ b/board/freescale/m5329evb/nand.c @@ -35,81 +35,80 @@ DECLARE_GLOBAL_DATA_PTR; #include #include -#define SET_CLE 0x10 -#define CLR_CLE ~SET_CLE -#define SET_ALE 0x08 -#define CLR_ALE ~SET_ALE +#define SET_CLE 0x10 +#define CLR_CLE ~SET_CLE +#define SET_ALE 0x08 +#define CLR_ALE ~SET_ALE static void nand_hwcontrol(struct mtd_info *mtdinfo, int cmd) { - struct nand_chip *this = mtdinfo->priv; - volatile fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS; - u32 nand_baseaddr = (u32) this->IO_ADDR_W; + struct nand_chip *this = mtdinfo->priv; + volatile fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS; + u32 nand_baseaddr = (u32) this->IO_ADDR_W; - switch (cmd) { - case NAND_CTL_SETNCE: - case NAND_CTL_CLRNCE: - break; - case NAND_CTL_SETCLE: - nand_baseaddr |= SET_CLE; - break; - case NAND_CTL_CLRCLE: - nand_baseaddr &= CLR_CLE; - break; - case NAND_CTL_SETALE: - nand_baseaddr |= SET_ALE; - break; - case NAND_CTL_CLRALE: - nand_baseaddr |= CLR_ALE; - break; - case NAND_CTL_SETWP: - fbcs->csmr2 |= CSMR_WP; - break; - case NAND_CTL_CLRWP: - fbcs->csmr2 &= ~CSMR_WP; - break; - } - this->IO_ADDR_W = (void __iomem *)(nand_baseaddr); + switch (cmd) { + case NAND_CTL_SETNCE: + case NAND_CTL_CLRNCE: + break; + case NAND_CTL_SETCLE: + nand_baseaddr |= SET_CLE; + break; + case NAND_CTL_CLRCLE: + nand_baseaddr &= CLR_CLE; + break; + case NAND_CTL_SETALE: + nand_baseaddr |= SET_ALE; + break; + case NAND_CTL_CLRALE: + nand_baseaddr |= CLR_ALE; + break; + case NAND_CTL_SETWP: + fbcs->csmr2 |= CSMR_WP; + break; + case NAND_CTL_CLRWP: + fbcs->csmr2 &= ~CSMR_WP; + break; + } + this->IO_ADDR_W = (void __iomem *)(nand_baseaddr); } static void nand_write_byte(struct mtd_info *mtdinfo, u_char byte) { - struct nand_chip *this = mtdinfo->priv; - *((volatile u8 *)(this->IO_ADDR_W)) = byte; + struct nand_chip *this = mtdinfo->priv; + *((volatile u8 *)(this->IO_ADDR_W)) = byte; } static u8 nand_read_byte(struct mtd_info *mtdinfo) { - struct nand_chip *this = mtdinfo->priv; - return (u8) (*((volatile u8 *)this->IO_ADDR_R)); + struct nand_chip *this = mtdinfo->priv; + return (u8) (*((volatile u8 *)this->IO_ADDR_R)); } static int nand_dev_ready(struct mtd_info *mtdinfo) { - return 1; + return 1; } int board_nand_init(struct nand_chip *nand) { - volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; + volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; - *((volatile u16 *)CFG_LATCH_ADDR) |= 0x0004; + *((volatile u16 *)CFG_LATCH_ADDR) |= 0x0004; - /* set up pin configuration */ - gpio->par_timer &= ~GPIO_PAR_TIN3_TIN3; - gpio->pddr_timer |= 0x08; - gpio->ppd_timer |= 0x08; - gpio->pclrr_timer = 0; - gpio->podr_timer = 0; + /* set up pin configuration */ + gpio->par_timer &= ~GPIO_PAR_TIN3_TIN3; + gpio->pddr_timer |= 0x08; + gpio->ppd_timer |= 0x08; + gpio->pclrr_timer = 0; + gpio->podr_timer = 0; - nand->chip_delay = 50; - nand->eccmode = NAND_ECC_SOFT; - nand->hwcontrol = nand_hwcontrol; - nand->read_byte = nand_read_byte; - nand->write_byte = nand_write_byte; - nand->dev_ready = nand_dev_ready; + nand->chip_delay = 50; + nand->eccmode = NAND_ECC_SOFT; + nand->hwcontrol = nand_hwcontrol; + nand->read_byte = nand_read_byte; + nand->write_byte = nand_write_byte; + nand->dev_ready = nand_dev_ready; - return 0; + return 0; } #endif - diff --git a/cpu/mcf532x/cpu_init.c b/cpu/mcf532x/cpu_init.c index eb9b7a407..93086f74b 100644 --- a/cpu/mcf532x/cpu_init.c +++ b/cpu/mcf532x/cpu_init.c @@ -71,35 +71,35 @@ void cpu_init_f(void) #if (defined(CFG_CS1_BASE) && defined(CFG_CS1_MASK) && defined(CFG_CS1_CTRL)) /* Latch chipselect */ - gpio->par_cs |= GPIO_PAR_CS1; + gpio->par_cs |= GPIO_PAR_CS1; fbcs->csar1 = CFG_CS1_BASE; fbcs->cscr1 = CFG_CS1_CTRL; fbcs->csmr1 = CFG_CS1_MASK; #endif #if (defined(CFG_CS2_BASE) && defined(CFG_CS2_MASK) && defined(CFG_CS2_CTRL)) - gpio->par_cs |= GPIO_PAR_CS2; + gpio->par_cs |= GPIO_PAR_CS2; fbcs->csar2 = CFG_CS2_BASE; fbcs->cscr2 = CFG_CS2_CTRL; fbcs->csmr2 = CFG_CS2_MASK; #endif #if (defined(CFG_CS3_BASE) && defined(CFG_CS3_MASK) && defined(CFG_CS3_CTRL)) - gpio->par_cs |= GPIO_PAR_CS3; + gpio->par_cs |= GPIO_PAR_CS3; fbcs->csar3 = CFG_CS3_BASE; fbcs->cscr3 = CFG_CS3_CTRL; fbcs->csmr3 = CFG_CS3_MASK; #endif #if (defined(CFG_CS4_BASE) && defined(CFG_CS4_MASK) && defined(CFG_CS4_CTRL)) - gpio->par_cs |= GPIO_PAR_CS4; + gpio->par_cs |= GPIO_PAR_CS4; fbcs->csar4 = CFG_CS4_BASE; fbcs->cscr4 = CFG_CS4_CTRL; fbcs->csmr4 = CFG_CS4_MASK; #endif #if (defined(CFG_CS5_BASE) && defined(CFG_CS5_MASK) && defined(CFG_CS5_CTRL)) - gpio->par_cs |= GPIO_PAR_CS5; + gpio->par_cs |= GPIO_PAR_CS5; fbcs->csar5 = CFG_CS5_BASE; fbcs->cscr5 = CFG_CS5_CTRL; fbcs->csmr5 = CFG_CS5_MASK; @@ -139,4 +139,3 @@ void uart_port_conf(void) break; } } - From 29cb25da56afe18cf5e7072a92a9d98ea8af1fd4 Mon Sep 17 00:00:00 2001 From: Yuri Tikhonov Date: Fri, 10 Aug 2007 08:25:22 +0200 Subject: [PATCH 067/259] POST: Add ppc4xx UART POST support without external uart clock (lwmon5) The patch adds support for UART POST on ppc44x-based boards with no external serial clocks installed. Signed-off-by: Yuri Tikhonov Acked-by: Stefan Roese --- post/cpu/ppc4xx/uart.c | 43 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 43 insertions(+) diff --git a/post/cpu/ppc4xx/uart.c b/post/cpu/ppc4xx/uart.c index b047d42df..0aeed75ae 100644 --- a/post/cpu/ppc4xx/uart.c +++ b/post/cpu/ppc4xx/uart.c @@ -84,6 +84,49 @@ DECLARE_GLOBAL_DATA_PTR; +#if !defined(CFG_EXT_SERIAL_CLOCK) +static void serial_divs (int baudrate, unsigned long *pudiv, + unsigned short *pbdiv) +{ + sys_info_t sysinfo; + unsigned long div; /* total divisor udiv * bdiv */ + unsigned long umin; /* minimum udiv */ + unsigned short diff; /* smallest diff */ + unsigned long udiv; /* best udiv */ + unsigned short idiff; /* current diff */ + unsigned short ibdiv; /* current bdiv */ + unsigned long i; + unsigned long est; /* current estimate */ + + get_sys_info(&sysinfo); + + udiv = 32; /* Assume lowest possible serial clk */ + div = sysinfo.freqPLB / (16 * baudrate); /* total divisor */ + umin = sysinfo.pllOpbDiv << 1; /* 2 x OPB divisor */ + diff = 32; /* highest possible */ + + /* i is the test udiv value -- start with the largest + * possible (32) to minimize serial clock and constrain + * search to umin. + */ + for (i = 32; i > umin; i--) { + ibdiv = div / i; + est = i * ibdiv; + idiff = (est > div) ? (est-div) : (div-est); + if (idiff == 0) { + udiv = i; + break; /* can't do better */ + } else if (idiff < diff) { + udiv = i; /* best so far */ + diff = idiff; /* update lowest diff*/ + } + } + + *pudiv = udiv; + *pbdiv = div / udiv; +} +#endif + static int uart_post_init (unsigned long dev_base) { unsigned long reg; From 3e4c90c6233618fc1806e63fde68df5f3d6a0171 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Fri, 10 Aug 2007 08:42:55 +0200 Subject: [PATCH 068/259] ppc4xx: Update lwmon5 POST configuration Signed-off-by: Stefan Roese --- include/configs/lwmon5.h | 21 +++++++++++++++++++-- 1 file changed, 19 insertions(+), 2 deletions(-) diff --git a/include/configs/lwmon5.h b/include/configs/lwmon5.h index 5ebe4404d..52db71e89 100644 --- a/include/configs/lwmon5.h +++ b/include/configs/lwmon5.h @@ -137,10 +137,25 @@ #define CONFIG_DDR_DATA_EYE 1 /* use DDR2 optimization */ #if 0 /* test-only: disable ECC for now */ #define CONFIG_DDR_ECC 1 /* enable ECC */ +#define CFG_POST_ECC_ON CFG_POST_ECC +#else +#define CFG_POST_ECC_ON 0 +#endif /* POST support */ -#define CONFIG_POST (CFG_POST_ECC) -#endif +#define CONFIG_POST (CFG_POST_MEMORY | \ + CFG_POST_ECC_ON | \ + CFG_POST_CPU | \ + CFG_POST_UART | \ + CFG_POST_I2C | \ + CFG_POST_CACHE | \ + CFG_POST_FPU | \ + CFG_POST_ETHER | \ + CFG_POST_SPR) + +#define CFG_POST_CACHE_ADDR 0x10000000 /* free virtual address */ +#define CONFIG_LOGBUFFER +#define CFG_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */ /*----------------------------------------------------------------------- * I2C @@ -170,6 +185,7 @@ "hostname=lwmon5\0" \ "netdev=eth0\0" \ "unlock=yes\0" \ + "logversion=2\0" \ "nfsargs=setenv bootargs root=/dev/nfs rw " \ "nfsroot=${serverip}:${rootpath}\0" \ "ramargs=setenv bootargs root=/dev/ram rw\0" \ @@ -244,6 +260,7 @@ CFG_CMD_EEPROM | \ CFG_CMD_ELF | \ CFG_CMD_FAT | \ + CFG_CMD_LOG | \ CFG_CMD_I2C | \ CFG_CMD_IRQ | \ CFG_CMD_MII | \ From 641cca9569ce351ddb287fd3343d8b1dcb591db4 Mon Sep 17 00:00:00 2001 From: Niklaus Giger Date: Fri, 27 Jul 2007 11:37:40 +0200 Subject: [PATCH 069/259] Add PPC4xx-HCU4 and HCU5 boards: Infrastructure This series of patches adds support for 2 boards from Netstal Maschinen. The HCU4 has a PPC405Gpr and the HCU5 has a PPC440EPX. The HCU4 has a somehow complicated flash setup, as the booteprom is only 8 bits and the CFI 16 bits wide, which makes it impossible to use a more elegant solution. The HCU5 has only a booteprom as the whole code will be downloaded from a different board which has HD, CD-ROM, etc and where all code is stored. This is my third try. I incorporated all suggestions made by Wolfgang and Stefan. Thanks them a lot. Signed-off-by: Niklaus Giger --- CREDITS | 5 +++++ MAINTAINERS | 5 +++++ MAKEALL | 20 ++++++++++---------- 3 files changed, 20 insertions(+), 10 deletions(-) diff --git a/CREDITS b/CREDITS index 7af1b806a..1af9c7f34 100644 --- a/CREDITS +++ b/CREDITS @@ -160,6 +160,11 @@ N: Thomas Frieden E: ThomasF@hyperion-entertainment.com D: Support for AmigaOne +N: Niklaus Giger +E: niklaus.giger@netstal.com +D: Support for HCU(x) boards +W: www.netstal.com + N: Paul Gortmaker E: paul.gortmaker@windriver.com D: Support for WRS SBC8347/8349 boards diff --git a/MAINTAINERS b/MAINTAINERS index 693b11572..8dc46ad67 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -160,6 +160,11 @@ Matthias Fuchs WUH405 PPC405EP CMS700 PPC405EP +Niklaus Giger + + HCU4 PPC405GPr + HCU5 PPC440EPx + Frank Gottschling MHPC MPC8xx diff --git a/MAKEALL b/MAKEALL index 127faa83a..e7067972c 100755 --- a/MAKEALL +++ b/MAKEALL @@ -82,16 +82,16 @@ LIST_4xx=" \ CPCI405DT CPCI440 CPCIISER4 CRAYL1 \ csb272 csb472 DASA_SIM DP405 \ DU405 ebony ERIC EXBITGEN \ - G2000 HH405 HUB405 JSE \ - KAREF katmai luan lwmon5 \ - METROBOX MIP405 MIP405T ML2 \ - ml300 ocotea OCRTC ORSG \ - p3p440 PCI405 pcs440ep PIP405 \ - PLU405 PMC405 PPChameleonEVB sbc405 \ - sc3 sequoia sequoia_nand taishan \ - VOH405 VOM405 W7OLMC W7OLMG \ - walnut WUH405 XPEDITE1K yellowstone \ - yosemite yucca \ + G2000 HH405 hcu4 hcu5 \ + HUB405 JSE KAREF katmai \ + luan lwmon5 METROBOX MIP405 \ + MIP405T ML2 ml300 ocotea \ + OCRTC ORSG p3p440 PCI405 \ + pcs440ep PIP405 PLU405 PMC405 \ + PPChameleonEVB sbc405 sc3 sequoia \ + sequoia_nand taishan VOH405 VOM405 \ + W7OLMC W7OLMG walnut WUH405 \ + XPEDITE1K yellowstone yosemite yucca \ " ######################################################################### From 1894dd381124bdbfbdae7cf3a6ca52a8eb1f4421 Mon Sep 17 00:00:00 2001 From: Niklaus Giger Date: Fri, 27 Jul 2007 11:25:31 +0200 Subject: [PATCH 070/259] Add PPC4xx-HCU4 and HCU5 boards: READMEs Signed-off-by: Niklaus Giger --- board/netstal/hcu4/README.txt | 59 ++++++++++++ board/netstal/hcu5/README.txt | 174 ++++++++++++++++++++++++++++++++++ 2 files changed, 233 insertions(+) create mode 100644 board/netstal/hcu4/README.txt create mode 100644 board/netstal/hcu5/README.txt diff --git a/board/netstal/hcu4/README.txt b/board/netstal/hcu4/README.txt new file mode 100644 index 000000000..1e9c64ab3 --- /dev/null +++ b/board/netstal/hcu4/README.txt @@ -0,0 +1,59 @@ +HCU4 Configuration Details + +Memory Bank 0 -- Flash chip +--------------------------- + +0xfff00000 - 0xffffffff + +The flash chip is really only 512Kbytes, but the high address bit of +the 1Meg region is ignored, so the flash is replicated through the +region. Thus, this is consistent with a flash base address 0xfff80000. + +The placement at the end is to be consistent with reset behavior, +where the processor itself initially uses this bus to load the branch +vector and start running. + +On-Chip Memory +-------------- + +0xf4000000 - 0xf4000fff + +The 405GPr includes a 4K on-chip memory that can be placed however +software chooses. I choose to place the memory at this address, to +keep it out of the cachable areas. + + +Internal Peripherals +-------------------- + +0xef600300 - 0xef6008ff + +These are scattered various peripherals internal to the PPC405GPr +chip. + +Chip-Select 2: Flash Memory +--------------------------- + +0x70000000 + +Chip-Select 3: CAN Interface +---------------------------- +0x7800000 + + +Chip-Select 4: IMC-bus standard +------------------------------- + +Our IO-Bus (slow version) + + +Chip-Select 5: IMC-bus fast (inactive) +-------------------------------------- + +Our IO-Bus (fast, but not yet use) + + +Memory Bank 1 -- SDRAM +------------------------------------- + +0x00000000 - 0x1ffffff # Default 32 MB diff --git a/board/netstal/hcu5/README.txt b/board/netstal/hcu5/README.txt new file mode 100644 index 000000000..3118da9e0 --- /dev/null +++ b/board/netstal/hcu5/README.txt @@ -0,0 +1,174 @@ +HCU5 configuration details and startup sequence + +(C) Copyright 2007 Netstal Maschinen AG + Niklaus Giger (Niklaus.Giger@netstal.com) + +TODO: +----- +- Fix error: Waiting for PHY auto negotiation to complete..... TIMEOUT ! + - Does not occur if both EMAC are connected +- Fix RTS/CTS problem (HW?) + CONFIG_SERIAL_MULTI/CONFIG_SERIAL_SOFTWARE_FIFO hangs after + Switching to interrupt driven serial input mode +- Make vxWorks start from u-boot. Possible reasons + - Does vxWorks need an entry for the Machine Check interrupt like this + tlbentry( 0x40000000, SZ_256M, 0, 1, AC_R|AC_W|AC_X|SA_G|SA_I ) ? + +Caveats: +-------- +Errata CHIP_8: Incorrect Write to DDR SDRAM. (was not applied to sequoia.c) +see hcu5.c. + + +Memory Bank 0 -- Flash chip +--------------------------- + +0xfff00000 - 0xffffffff + +The flash chip is really only 512Kbytes, but the high address bit of +the 1Meg region is ignored, so the flash is replicated through the +region. Thus, this is consistent with a flash base address 0xfff80000. + +The placement at the end is to be consistent with reset behavior, +where the processor itself initially uses this bus to load the branch +vector and start running. + +On-Chip Memory +-------------- + +0xe0010000- 0xe0013fff CFG_OCM_BASE +The 440EPx includes a 16K on-chip memory that can be placed however +software chooses. + +Internal Peripherals +-------------------- + +0xef600300 - 0xef6008ff + +These are scattered various peripherals internal to the PPC440EPX +chip. + +Chip-Select 2: Flash Memory +--------------------------- + +Not used + +Chip-Select 3: CAN Interface +---------------------------- +0xc800000: 2 Intel 82527 CAN-Controller + + +Chip-Select 4: IMC-bus standard +------------------------------- + +0xcc00000: Netstal specific IO-Bus + + +Chip-Select 5: IMC-bus fast (inactive) +-------------------------------------- + +0xce00000: Netstal specific IO-Bus (fast, but not yet used) + + +Memory Bank 1 -- DDR2 +------------------------------------- + +0x00000000 - 0xfffffff # Default 256 MB + +PCI ?? + +USB ?? +Only USB_STORAGE is enabled to load vxWorks +from a memory stick. + +System-LEDs ??? (Analog zu HCU4 ???) + +Startup sequence +---------------- + +(cpu/ppc4xx/resetvec.S) +depending on configs option +call _start_440 _start_pci oder _start + +(cpu/ppc4xx/start.S) + +_start_440: + initialize register like + CCR0 + debug + setup interrupt vectors + configure cache regions + clear and setup TLB + enable internal RAM + jump start_ram + which in turn will jump to start +_start: + Clear and set up some registers. + Debug setup + Setup the internal SRAM + Setup the stack in internal SRAM + setup stack pointer (r1) + setup GOT + call cpu_init_f /* run low-level CPU init code (from Flash) */ + + call cpu_init_f + board_init_f: (lib_ppc\board.c) + init_sequence defines a list of function to be called + board_early_init_f: (board/netstal/hcu5/hcu5.c) + We are using Bootstrap-Option A + if CPR0_ICFG_RLI_MASK == 0 then set some registers and reboot + Setup the GPIO pins + Setup the interrupt controller polarities, triggers, etc. + Ethernet, PCI, USB enable + setup BOOT FLASH (Chip timing) + init_baudrate, + serial_init + checkcpu + misc_init_f #ifdef + init_func_i2c #ifdef + post_init_f #ifdef + init_func_ram -> calls init_dram board/netstal/hcu5/sdram.c + (EYE function removed!!) + test_dram call + + * Reserve memory at end of RAM for (top down in that order): + * - kernel log buffer + * - protected RAM + * - LCD framebuffer + * - monitor code + * - board info struct + Save local variables to board info struct + call relocate_code() does not return + relocate_code: (cpu/ppc4xx/start.S) +------------------------------------------------------- +From now on our copy is in RAM and we will run from there, + starting with board_init_r +------------------------------------------------------- + board_init_r: (lib_ppc\board.c) + setup bd function pointers + trap_init + flash_init: (board/netstal/hcu5/flash.c) + /* setup for u-boot erase, update */ + setup bd flash info + cpu_init_r: (cpu/ppc4xx/cpu_init.c) + peripheral chip select in using defines like + CFG_EBC_PB0A, CFG_EBC_PB0C from hcu5.h + mem_malloc_init + malloc_bin_reloc + spi_init (r or f)??? (CFG_ENV_IS_IN_EEPROM) + env_relocated + misc_init_r(bd): (board/netstal/hcu5.c) + ethaddr mit serial number ergänzen + Then we will somehow go into the command loop + +Most of the HW specific code for the HCU5 may be found in +include/configs/hcu5.h +board/netstal/hcu5/* +cpu/ppc4xx/* +lib_ppc/* +include/ppc440.h + +Drivers for serial etc are found under drivers/ + +Don't ask question if you did not look at the README !! +Most CFG_* and CONFIG_* switches are mentioned/explained there. From 714bc55b35b6f6a65cc8740a3842a543e88cdef2 Mon Sep 17 00:00:00 2001 From: Niklaus Giger Date: Fri, 27 Jul 2007 11:27:15 +0200 Subject: [PATCH 071/259] Add PPC4xx-HCU4 and HCU5 boards: HCU4 config Signed-off-by: Niklaus Giger --- include/configs/hcu4.h | 343 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 343 insertions(+) create mode 100644 include/configs/hcu4.h diff --git a/include/configs/hcu4.h b/include/configs/hcu4.h new file mode 100644 index 000000000..8779db9af --- /dev/null +++ b/include/configs/hcu4.h @@ -0,0 +1,343 @@ +/* + *(C) Copyright 2005-2007 Netstal Maschinen AG + * Niklaus Giger (Niklaus.Giger@netstal.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/************************************************************************ + * hcu4.h - configuration for HCU4 board (similar to hcu5.h) + ***********************************************************************/ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/*----------------------------------------------------------------------- + * High Level Configuration Options + *----------------------------------------------------------------------*/ +#define CONFIG_HCU4 1 /* Board is HCU4 */ +#define CONFIG_4xx 1 /* ... PPC4xx family */ +#define CONFIG_405GPr 1 /* HCU4 has a 405GPr */ +#define CONFIG_405GP 1 +#define CONFIG_4xx 1 + +#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */ + +#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ +#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */ + +/*----------------------------------------------------------------------- + * Base addresses -- Note these are effective addresses where the + * actual resources get mapped (not physical addresses) +*----------------------------------------------------------------------*/ +#define CFG_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Monitor */ +#define CFG_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */ + + +#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */ +#define CFG_FLASH_BASE 0xfff80000 /* start of FLASH */ +#define CFG_MONITOR_BASE TEXT_BASE + +/* ... with on-chip memory here (4KBytes) */ +#define CFG_OCM_DATA_ADDR 0xF4000000 +#define CFG_OCM_DATA_SIZE 0x00001000 +/* Do not set up locked dcache as init ram. */ +#undef CFG_INIT_DCACHE_CS + +/* Use the On-Chip-Memory (OCM) as a temporary stack for the startup code. */ +#define CFG_TEMP_STACK_OCM 1 + +#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* OCM */ +#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE +#define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +/*----------------------------------------------------------------------- + * Serial Port + *----------------------------------------------------------------------*/ +/* + * If CFG_EXT_SERIAL_CLOCK, then the UART divisor is 1. + * If CFG_405_UART_ERRATA_59, then UART divisor is 31. + * Otherwise, UART divisor is determined by CPU Clock and CFG_BASE_BAUD value. + * The Linux BASE_BAUD define should match this configuration. + * baseBaud = cpuClock/(uartDivisor*16) + * If CFG_405_UART_ERRATA_59 and 200MHz CPU clock, + * set Linux BASE_BAUD to 403200. + */ +#undef CFG_EXT_SERIAL_CLOCK /* external serial clock */ +#undef CONFIG_SERIAL_MULTI /* needed to be able to define + CONFIG_SERIAL_SOFTWARE_FIFO */ +#undef CFG_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */ +#define CFG_BASE_BAUD 691200 + +/* Size (bytes) of interrupt driven serial port buffer. + * Set to 0 to use polling instead of interrupts. + * Setting to 0 will also disable RTS/CTS handshaking. + */ +#undef CONFIG_SERIAL_SOFTWARE_FIFO + +/* Set console baudrate to 9600 */ +#define CONFIG_BAUDRATE 9600 + + +#define CFG_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} + +/*----------------------------------------------------------------------- + * Environment + *----------------------------------------------------------------------*/ + +#undef CFG_ENV_IS_IN_NVRAM +#undef CFG_ENV_IS_IN_FLASH +#define CFG_ENV_IS_IN_EEPROM +#undef CFG_ENV_IS_NOWHERE + +#ifdef CFG_ENV_IS_IN_EEPROM +/* Put the environment after the SDRAM configuration */ +#define PROM_SIZE 2048 +#define CFG_ENV_OFFSET 512 +#define CFG_ENV_SIZE (PROM_SIZE-CFG_ENV_OFFSET) +#endif + +#ifdef CFG_ENV_IS_IN_FLASH +/* Put the environment in Flash */ +#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */ +#define CFG_ENV_ADDR ((-CFG_MONITOR_LEN)-CFG_ENV_SECT_SIZE) +#define CFG_ENV_SIZE 0x10000 /* Total Size of Environment Sector */ + +/* Address and size of Redundant Environment Sector */ +#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE) +#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) +#endif + +/*----------------------------------------------------------------------- + * I2C stuff for a ATMEL AT24C16 (2kB holding ENV, we are using the + * the first internal I2C controller of the PPC440EPx + *----------------------------------------------------------------------*/ +#define CFG_SPD_BUS_NUM 0 + +#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ +#undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CFG_I2C_SLAVE 0x7F + +/* This is the 7bit address of the device, not including P. */ +#define CFG_I2C_EEPROM_ADDR 0x50 +#define CFG_I2C_EEPROM_ADDR_LEN 1 + +/* The EEPROM can do 16byte ( 1 << 4 ) page writes. */ +#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07 +#define CFG_EEPROM_PAGE_WRITE_BITS 4 +#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 +#define CFG_EEPROM_PAGE_WRITE_ENABLE +#undef CFG_I2C_MULTI_EEPROMS + + +#define CONFIG_PREBOOT "echo;" \ + "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ + "echo" + +#undef CONFIG_BOOTARGS + +/* Setup some board specific values for the default environment variables */ +#define CONFIG_HOSTNAME hcu4 +#define CONFIG_IPADDR 172.25.1.42 +#define CONFIG_ETHADDR 00:60:13:00:00:00 /* Netstal Machines AG MAC */ +#define CONFIG_OVERWRITE_ETHADDR_ONCE +#define CONFIG_SERVERIP 172.25.1.3 + +#define CFG_TFTP_LOADADDR 0x01000000 /* @16 MB */ + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "loadaddr=0x01000000\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=${serverip}:${rootpath}\0" \ + "ramargs=setenv bootargs root=/dev/ram rw\0" \ + "addip=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:${netdev}:off panic=1\0" \ + "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ + "nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ + "bootm\0" \ + "rootpath=/home/diagnose/eldk/ppc_4xx\0" \ + "bootfile=/tftpboot/hcu4/uImage\0" \ + "load=tftp 100000 hcu4/u-boot.bin\0" \ + "update=protect off FFFa0000 FFFFFFFF;era FFFa0000 FFFFFFFF;" \ + "cp.b 100000 FFFa0000 60000\0" \ + "upd=run load;run update\0" \ + "vx=tftp ${loadaddr} hcu4_vx_rom;" \ + "setenv bootargs emac(0,0)hcu4_vx_rom e=${ipaddr} " \ + " h=${serverip} u=dpu pw=netstal8752 tn=hcu4 f=0x3008;" \ + "bootvx ${loadaddr}\0" \ + "" +#define CONFIG_BOOTCOMMAND "run vx" + +#if 0 +#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ +#else +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ +#endif + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +#define CONFIG_MII 1 /* MII PHY management */ +#define CONFIG_PHY_ADDR 1 /* PHY address */ + +#define CONFIG_PHY_RESET 1 /* reset phy upon startup */ + +#define CONFIG_HAS_ETH0 +#define CFG_RX_ETH_BUFFER 16 /* Number of ethernet rx buffers & descriptors */ +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ + CFG_CMD_ASKENV | \ + CFG_CMD_BSP | \ + CFG_CMD_CACHE | \ + CFG_CMD_DHCP | \ + CFG_CMD_DIAG | \ + CFG_CMD_EEPROM | \ + CFG_CMD_ELF | \ + CFG_CMD_FLASH | \ + CFG_CMD_I2C | \ + CFG_CMD_IMMAP | \ + CFG_CMD_IRQ | \ + CFG_CMD_MII | \ + CFG_CMD_NET | \ + CFG_CMD_PING | \ + CFG_CMD_REGINFO | \ + CFG_CMD_SDRAM \ + ) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +/* SPD EEPROM (sdram speed config) disabled */ +#define CONFIG_SPD_EEPROM 1 +#define SPD_EEPROM_ADDRESS 0x50 + +/*----------------------------------------------------------------------- + * Miscellaneous configurable options + *----------------------------------------------------------------------*/ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) + #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else + #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ +#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ + + +#define CFG_LOAD_ADDR 0x100000 /* default load address */ +#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ +#define CONFIG_LOOPW 1 /* enable loopw command */ +#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ +#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ + +/*----------------------------------------------------------------------- + * External Bus Controller (EBC) Setup + */ + +/* Memory Bank 0 (Flash Bank 0) initialization */ +#define CFG_EBC_PB0AP 0x02005400 +#define CFG_EBC_PB0CR 0xFFF18000 /* BAS=0xFFF,BS=1MB,BU=R/W,BW=8bit */ + +#define CFG_EBC_PB1AP 0x03041200 +#define CFG_EBC_PB1CR 0x7009A000 /* BAS=,BS=MB,BU=R/W,BW=bit */ + +#define CFG_EBC_PB2AP 0x02054500 +#define CFG_EBC_PB2CR 0x78018000 /* BAS=,BS=MB,BU=R/W,BW=bit */ + +#define CFG_EBC_PB3AP 0x01840300 +#define CFG_EBC_PB3CR 0x7c0ba000 /* BAS=,BS=MB,BU=R/W,BW=bit */ + +#define CFG_EBC_PB4AP 0x01800300 +#define CFG_EBC_PB4CR 0x7e0ba000 /* BAS=,BS=MB,BU=R/W,BW=bit */ + +#define CFG_GPIO0_TCR 0x7ffe0000 /* GPIO value */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/*----------------------------------------------------------------------- + * FLASH organization + */ +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ + + +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ + +/* Init Memory Controller: + * + * BR0/1 and OR0/1 (FLASH) + */ + +#define FLASH_BASE0_PRELIM CFG_FLASH_BASE /* FLASH bank #0 */ +#define FLASH_BASE1_PRELIM 0 /* FLASH bank #1 */ + + +/* Configuration Port location */ +#define CONFIG_PORT_ADDR 0xF0000500 + + + + +/*----------------------------------------------------------------------- + * Cache Configuration + *----------------------------------------------------------------------*/ +#define CFG_DCACHE_SIZE 16384 /* For IBM 405GPr CPUs */ +#define CFG_CACHELINE_SIZE 32 /* ... */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#define CFG_HUSH_PARSER /* use "hush" command parser */ +#ifdef CFG_HUSH_PARSER + #define CFG_PROMPT_HUSH_PS2 "> " +#endif + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif +#endif /* __CONFIG_H */ From 137fdd9f474ecb853efdace5200576308c67f18d Mon Sep 17 00:00:00 2001 From: Niklaus Giger Date: Fri, 27 Jul 2007 11:28:03 +0200 Subject: [PATCH 072/259] Add PPC4xx-HCU4 and HCU5 boards: HCU5 config Signed-off-by: Niklaus Giger --- include/configs/hcu5.h | 392 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 392 insertions(+) create mode 100644 include/configs/hcu5.h diff --git a/include/configs/hcu5.h b/include/configs/hcu5.h new file mode 100644 index 000000000..87f6948df --- /dev/null +++ b/include/configs/hcu5.h @@ -0,0 +1,392 @@ +/* + * (C) Copyright 2007 Netstal Maschinen AG + * Niklaus Giger (Niklaus.Giger@netstal.com) + * + * (C) Copyright 2006-2007 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * (C) Copyright 2006 + * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com + * Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/************************************************************************ + * hcu5.h - configuration for HCU5 board (derived from sequoia.h) + ***********************************************************************/ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/*----------------------------------------------------------------------- + * High Level Configuration Options + *----------------------------------------------------------------------*/ +#define CONFIG_HCU5 1 /* Board is HCU5 */ +#define CONFIG_440EPX 1 /* Specific PPC440EPx */ +#define CONFIG_440 1 /* ... PPC440 family */ +#define CONFIG_4xx 1 /* ... PPC4xx family */ +#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */ + +#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ +#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */ +#define CONFIG_ADD_RAM_INFO 1 /* Print additional info */ + +/*----------------------------------------------------------------------- + * Base addresses -- Note these are effective addresses where the + * actual resources get mapped (not physical addresses) + *----------------------------------------------------------------------*/ +#define CFG_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Monitor */ +#define CFG_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */ + +#define CFG_BOOT_BASE_ADDR 0xfff00000 +#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */ +#define CFG_FLASH_BASE 0xfff80000 /* start of FLASH */ +#define CFG_MONITOR_BASE TEXT_BASE +#define CFG_OCM_BASE 0xe0010000 /* ocm */ +#define CFG_PCI_BASE 0xe0000000 /* Internal PCI regs */ +#define CFG_PCI_MEMBASE 0x80000000 /* mapped pci memory */ +#define CFG_PCI_MEMBASE1 CFG_PCI_MEMBASE + 0x10000000 +#define CFG_PCI_MEMBASE2 CFG_PCI_MEMBASE1 + 0x10000000 +#define CFG_PCI_MEMBASE3 CFG_PCI_MEMBASE2 + 0x10000000 + +/* Don't change either of these */ +#define CFG_PERIPHERAL_BASE 0xef600000 /* internal peripherals */ + +#define CFG_USB2D0_BASE 0xe0000100 +#define CFG_USB_DEVICE 0xe0000000 +#define CFG_USB_HOST 0xe0000400 + +/*----------------------------------------------------------------------- + * Initial RAM & stack pointer + *----------------------------------------------------------------------*/ +/* 440EPx/440GRx have 16KB of internal SRAM, so no need for D-Cache */ +#define CFG_INIT_RAM_OCM 1 /* OCM as init ram */ +#define CFG_INIT_RAM_ADDR CFG_OCM_BASE /* OCM */ + +#define CFG_INIT_RAM_END (4 << 10) +#define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +/*----------------------------------------------------------------------- + * Serial Port + *----------------------------------------------------------------------*/ +#undef CFG_EXT_SERIAL_CLOCK /* external serial clock */ +#define CONFIG_BAUDRATE 9600 +#undef CONFIG_SERIAL_MULTI /* needed to be able to define + CONFIG_SERIAL_SOFTWARE_FIFO, but + CONFIG_SERIAL_SOFTWARE_FIFO (16) does not work */ +/* Size (bytes) of interrupt driven serial port buffer. + * Set to 0 to use polling instead of interrupts. + * Setting to 0 will also disable RTS/CTS handshaking. + */ +#undef CONFIG_SERIAL_SOFTWARE_FIFO +#undef CONFIG_UART1_CONSOLE + +#define CFG_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} + +/*----------------------------------------------------------------------- + * Environment + *----------------------------------------------------------------------*/ + +#undef CFG_ENV_IS_IN_NVRAM +#undef CFG_ENV_IS_IN_FLASH +#define CFG_ENV_IS_IN_EEPROM +#undef CFG_ENV_IS_NOWHERE + +#ifdef CFG_ENV_IS_IN_EEPROM +/* Put the environment after the SDRAM and bootstrap configuration */ +#define PROM_SIZE 2048 +#define CFG_BOOSTRAP_OPTION_OFFSET 512 +#define CFG_ENV_OFFSET (CFG_BOOSTRAP_OPTION_OFFSET + 0x10) +#define CFG_ENV_SIZE (PROM_SIZE-CFG_ENV_OFFSET) +#endif + +#ifdef CFG_ENV_IS_IN_FLASH +/* Put the environment in Flash */ +#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */ +#define CFG_ENV_ADDR ((-CFG_MONITOR_LEN)-CFG_ENV_SECT_SIZE) +#define CFG_ENV_SIZE 0x10000 /* Total Size of Environment Sector */ + +/* Address and size of Redundant Environment Sector */ +#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE) +#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) +#endif + +/*----------------------------------------------------------------------- + * DDR SDRAM + *----------------------------------------------------------------------*/ +#define CFG_MBYTES_SDRAM (128) /* 128 MB or 256 MB */ +#define CFG_DDR_CACHED_ADDR 0x40000000 /* setup 2nd TLB cached here */ +#undef CONFIG_DDR_DATA_EYE /* Do not use DDR2 optimization */ +#define CONFIG_DDR_ECC 1 /* enable ECC */ + +/*----------------------------------------------------------------------- + * I2C stuff for a ATMEL AT24C16 (2kB holding ENV, we are using the + * the second internal I2C controller of the PPC440EPx + *----------------------------------------------------------------------*/ +#define CFG_SPD_BUS_NUM 1 + +#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ +#undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CFG_I2C_SLAVE 0x7F + +/* This is the 7bit address of the device, not including P. */ +#define CFG_I2C_EEPROM_ADDR 0x50 +#define CFG_I2C_EEPROM_ADDR_LEN 1 + +/* The EEPROM can do 16byte ( 1 << 4 ) page writes. */ +#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07 +#define CFG_EEPROM_PAGE_WRITE_BITS 4 +#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 +#define CFG_EEPROM_PAGE_WRITE_ENABLE +#undef CFG_I2C_MULTI_EEPROMS + + +#define CONFIG_PREBOOT "echo;" \ + "echo Type \"run nfs\" to mount Linux root filesystem over NFS;"\ + "echo" + +#undef CONFIG_BOOTARGS + +/* Setup some board specific values for the default environment variables */ +#define CONFIG_HOSTNAME hcu5 +#define CONFIG_IPADDR 172.25.1.42 +#define CONFIG_ETHADDR 00:60:13:00:00:00 /* Netstal Machines AG MAC */ +#define CONFIG_OVERWRITE_ETHADDR_ONCE +#define CONFIG_SERVERIP 172.25.1.3 + +#define CFG_TFTP_LOADADDR 0x01000000 /* @16 MB */ + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "loadaddr=0x01000000\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=${serverip}:${rootpath}\0" \ + "ramargs=setenv bootargs root=/dev/ram rw\0" \ + "addip=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:${netdev}:off panic=1\0" \ + "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ + "nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ + "bootm\0" \ + "bootfile=hcu5/uImage\0" \ + "rootpath=/home/hcu/eldk/ppc_4xxFP\0" \ + "load=tftp 100000 hcu5/u-boot.bin\0" \ + "update=protect off FFFa0000 FFFFFFFF;era FFFa0000 FFFFFFFF;" \ + "cp.b 100000 FFFa0000 60000\0" \ + "upd=run load;run update\0" \ + "vx=tftp ${loadaddr} hcu5/hcu5_vx_rom;" \ + "setenv bootargs emac(0,0)hcu5_vx_rom e=${ipaddr} " \ + " h=${serverip} u=dpu pw=netstal8752 tn=hcu5 f=0x3008;" \ + "bootvx ${loadaddr}\0" \ + "" +#define CONFIG_BOOTCOMMAND "run vx" + +#if 0 +#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ +#else +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ +#endif + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +#define CONFIG_M88E1111_PHY 1 +#define CONFIG_IBM_EMAC4_V4 1 +#define CONFIG_MII 1 /* MII PHY management */ +#define CONFIG_PHY_ADDR 0 /* PHY address, See schematics */ + +#define CONFIG_PHY_RESET 1 /* reset phy upon startup */ + +#define CONFIG_HAS_ETH0 +#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */ + +#define CONFIG_NET_MULTI 1 +#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */ +#define CONFIG_PHY1_ADDR 1 + +/* USB */ +#define CONFIG_USB_OHCI +#define CONFIG_USB_STORAGE + +/* Comment this out to enable USB 1.1 device */ +#define USB_2_0_DEVICE + +#define CMD_USB CFG_CMD_USB + +/* Partitions */ +#define CONFIG_MAC_PARTITION +#define CONFIG_DOS_PARTITION +#define CONFIG_ISO_PARTITION + +// CFG_CMD_FLASH | + +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ + CFG_CMD_ASKENV | \ + CFG_CMD_BSP | \ + CFG_CMD_DHCP | \ + CFG_CMD_DIAG | \ + CFG_CMD_EEPROM | \ + CFG_CMD_ELF | \ + CFG_CMD_FAT | \ + CFG_CMD_I2C | \ + CFG_CMD_IMMAP | \ + CFG_CMD_IRQ | \ + CFG_CMD_MII | \ + CFG_CMD_NET | \ + CFG_CMD_NFS | \ + CFG_CMD_PCI | \ + CFG_CMD_PING | \ + CFG_CMD_REGINFO | \ + CFG_CMD_SDRAM | \ + CMD_USB) + +#define CONFIG_SUPPORT_VFAT + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +/*----------------------------------------------------------------------- + * Miscellaneous configurable options + *----------------------------------------------------------------------*/ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ +#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ + +#define CFG_LOAD_ADDR 0x100000 /* default load address */ +#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ +#define CONFIG_LOOPW 1 /* enable loopw command */ +#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */ +#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ +#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ + +/*----------------------------------------------------------------------- + * PCI stuff + *----------------------------------------------------------------------*/ +/* General PCI */ +#define CONFIG_PCI /* include pci support */ +#undef CONFIG_PCI_PNP /* do (not) pci plug-and-play */ +#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ +#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE*/ + +/* Board-specific PCI */ +#define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */ +#define CFG_PCI_TARGET_INIT +#define CFG_PCI_MASTER_INIT + +#define CFG_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */ +#define CFG_PCI_SUBSYS_ID 0xcafe /* Whatever */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/*----------------------------------------------------------------------- + * External Bus Controller (EBC) Setup + *----------------------------------------------------------------------*/ +#define CFG_FLASH CFG_FLASH_BASE +#define CFG_CS_1 0xC8000000 /* CAN */ +#define CFG_CS_2 0xCC000000 /* CPLD and IMC-Bus Standard */ +#define CFG_CPLD CFG_CS_2 +#define CFG_CS_3 0xCD000000 /* CPLD and IMC-Bus Fast */ + +/*----------------------------------------------------------------------- + * FLASH organization + * Memory Bank 0 (BOOT-FLASH) initialization + */ +#define CFG_BOOTFLASH_CS 0 /* Boot Flash chip connected to CSx */ +#define CFG_EBC_PB0AP 0x02005400 +#define CFG_EBC_PB0CR 0xFFF18000 /* (CFG_FLASH | 0xda000) */ +#define FLASH_BASE0_PRELIM CFG_FLASH_BASE /* FLASH bank #0 */ +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 32 /* max number of sectors on one chip */ + + +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ + +/* Memory Bank 1 CAN-Chips initialization */ +#define CFG_EBC_PB1AP 0x02054500 +#define CFG_EBC_PB1CR 0xC8018000 + +/* Memory Bank 2 CPLD/IMC-Bus standard initialization */ +#define CFG_EBC_PB2AP 0x01840300 +#define CFG_EBC_PB2CR 0xCC0BA000 + +/* Memory Bank 3 IMC-Bus fast mode initialization */ +#define CFG_EBC_PB3AP 0x01800300 +#define CFG_EBC_PB3CR 0xCE0BA000 + +/* Memory Bank 4 (not used) initialization */ +#undef CFG_EBC_PB4AP +#undef CFG_EBC_PB4CR + +/* Memory Bank 5 (not used) initialization */ +#undef CFG_EBC_PB5AP +#undef CFG_EBC_PB5CR + +#define HCU_CPLD_VERSION_REGISTER ( CFG_CPLD + 0x0F00000 ) +#define HCU_HW_VERSION_REGISTER ( CFG_CPLD + 0x1400000 ) + +/*----------------------------------------------------------------------- + * Cache Configuration + *----------------------------------------------------------------------*/ +#define CFG_DCACHE_SIZE (32<<10) /* For AMCC 440 CPUs */ +#define CFG_CACHELINE_SIZE 32 /* ... */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#define CFG_HUSH_PARSER /* use "hush" command parser */ +#ifdef CFG_HUSH_PARSER + #define CFG_PROMPT_HUSH_PS2 "> " +#endif + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif +#endif /* __CONFIG_H */ + From ac982ea5a4f2f993efcf52dca122f5a59df047d8 Mon Sep 17 00:00:00 2001 From: Niklaus Giger Date: Fri, 27 Jul 2007 11:28:44 +0200 Subject: [PATCH 073/259] Add PPC4xx-HCU4 and HCU5 boards: make related Signed-off-by: Niklaus Giger --- Makefile | 6 ++ board/netstal/hcu4/Makefile | 49 ++++++++++++ board/netstal/hcu4/config.mk | 29 +++++++ board/netstal/hcu4/u-boot.lds | 140 +++++++++++++++++++++++++++++++++ board/netstal/hcu5/Makefile | 49 ++++++++++++ board/netstal/hcu5/config.mk | 31 ++++++++ board/netstal/hcu5/u-boot.lds | 144 ++++++++++++++++++++++++++++++++++ 7 files changed, 448 insertions(+) create mode 100644 board/netstal/hcu4/Makefile create mode 100644 board/netstal/hcu4/config.mk create mode 100644 board/netstal/hcu4/u-boot.lds create mode 100644 board/netstal/hcu5/Makefile create mode 100644 board/netstal/hcu5/config.mk create mode 100644 board/netstal/hcu5/u-boot.lds diff --git a/Makefile b/Makefile index 3af9962e6..04c2c02dc 100644 --- a/Makefile +++ b/Makefile @@ -1134,6 +1134,12 @@ EXBITGEN_config: unconfig G2000_config: unconfig @$(MKCONFIG) $(@:_config=) ppc ppc4xx g2000 +hcu4_config: unconfig + @./mkconfig $(@:_config=) ppc ppc4xx hcu4 netstal + +hcu5_config: unconfig + @./mkconfig $(@:_config=) ppc ppc4xx hcu5 netstal + HH405_config: unconfig @$(MKCONFIG) $(@:_config=) ppc ppc4xx hh405 esd diff --git a/board/netstal/hcu4/Makefile b/board/netstal/hcu4/Makefile new file mode 100644 index 000000000..d9825a5f2 --- /dev/null +++ b/board/netstal/hcu4/Makefile @@ -0,0 +1,49 @@ +# +# (C) Copyright 2007 Netstal Maschinen AG +# Niklaus Giger (ng@netstal.com) +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +vpath flash.c ../common +COBJS = $(BOARD).o flash.o +SOBJS = + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/netstal/hcu4/config.mk b/board/netstal/hcu4/config.mk new file mode 100644 index 000000000..f5a4ce474 --- /dev/null +++ b/board/netstal/hcu4/config.mk @@ -0,0 +1,29 @@ +# +# (C) Copyright 2005 Netstal Maschinen AG +# Niklaus Giger (ng@netstal.com) +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# Netstal Maschinen AG: HCU4 boards +# + +TEXT_BASE = 0xFFFa0000 + +ifeq ($(debug),1) +PLATFORM_CPPFLAGS += -DDEBUG -g +endif + diff --git a/board/netstal/hcu4/u-boot.lds b/board/netstal/hcu4/u-boot.lds new file mode 100644 index 000000000..b6e28f839 --- /dev/null +++ b/board/netstal/hcu4/u-boot.lds @@ -0,0 +1,140 @@ +/* + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + .resetvec 0xFFFFFFFC : + { + *(.resetvec) + } = 0xffff + + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : { + /* The start.o file includes the initial jump vector that + must be located in the beginning. It is the basic run- + time function that calls all other functions. */ + cpu/ppc4xx/start.o (.text) + +/* . = env_offset;*/ +/* common/environment.o(.text)*/ + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/netstal/hcu5/Makefile b/board/netstal/hcu5/Makefile new file mode 100644 index 000000000..eee310b1a --- /dev/null +++ b/board/netstal/hcu5/Makefile @@ -0,0 +1,49 @@ +# +# (C) Copyright 2007 Netstal Maschinen AG +# Niklaus Giger (ng@netstal.com) +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +vpath flash.c ../common +COBJS = $(BOARD).o sdram.o flash.o +SOBJS = init.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/netstal/hcu5/config.mk b/board/netstal/hcu5/config.mk new file mode 100644 index 000000000..58ec2af31 --- /dev/null +++ b/board/netstal/hcu5/config.mk @@ -0,0 +1,31 @@ +# +# (C) Copyright 2005 Netstal Maschinen AG +# Niklaus Giger (ng@netstal.com) +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# Netstal Maschinen AG: HCU5 boards +# + +TEXT_BASE = 0xFFFa0000 + +PLATFORM_CPPFLAGS += -DCONFIG_440=1 + +ifeq ($(debug),1) +PLATFORM_CPPFLAGS += -DDEBUG -g +endif + diff --git a/board/netstal/hcu5/u-boot.lds b/board/netstal/hcu5/u-boot.lds new file mode 100644 index 000000000..6d255a94e --- /dev/null +++ b/board/netstal/hcu5/u-boot.lds @@ -0,0 +1,144 @@ +/* + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); + +SECTIONS +{ + .resetvec 0xFFFFFFFC : + { + *(.resetvec) + } = 0xffff + + .bootpg 0xFFFFF000 : + { + cpu/ppc4xx/start.o (.bootpg) + } = 0xffff + + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/ppc4xx/start.o (.text) + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + + ppcenv_assert = ASSERT(. < 0xFFFF8000, ".bss section too big, overlaps .ppcenv section. Please update your confguration: CFG_MONITOR_BASE, CFG_MONITOR_LEN and TEXT_BASE may need to be modified."); + + _end = . ; + PROVIDE (end = .); +} From e8397fc78c9394d71de233a4d810fbc9047e4c76 Mon Sep 17 00:00:00 2001 From: Niklaus Giger Date: Fri, 27 Jul 2007 11:38:26 +0200 Subject: [PATCH 074/259] Add PPC4xx-HCU4 and HCU5 boards: common files Signed-off-by: Niklaus Giger --- board/netstal/common/flash.c | 528 ++++++++++++++++++++++++++++++++++ board/netstal/common/nm_bsp.c | 42 +++ 2 files changed, 570 insertions(+) create mode 100644 board/netstal/common/flash.c create mode 100644 board/netstal/common/nm_bsp.c diff --git a/board/netstal/common/flash.c b/board/netstal/common/flash.c new file mode 100644 index 000000000..be2cb3773 --- /dev/null +++ b/board/netstal/common/flash.c @@ -0,0 +1,528 @@ +/* + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * Modified 4/5/2001 + * Wait for completion of each sector erase command issued + * 4/5/2001 + * Chris Hallinan - DS4.COM, Inc. - clh@net1plus.com + * + * Modified 6/6/2007 + * Added isync + * Niklaus Giger, Netstal Maschinen, niklaus.giger@netstal.com + * + */ + +#include +#include +#include + +#if CFG_MAX_FLASH_BANKS != 1 +#error "CFG_MAX_FLASH_BANKS must be 1" +#endif +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ + +/*----------------------------------------------------------------------- + * Functions + */ +static ulong flash_get_size (vu_long * addr, flash_info_t * info); +static int write_word (flash_info_t * info, ulong dest, ulong data); +static void flash_get_offsets (ulong base, flash_info_t * info); + +#define ADDR0 0x5555 +#define ADDR1 0x2aaa +#define FLASH_WORD_SIZE unsigned char + +/*-----------------------------------------------------------------------*/ + +unsigned long flash_init (void) +{ + unsigned long size_b0; + + /* Init: no FLASHes known */ + flash_info[0].flash_id = FLASH_UNKNOWN; + + /* Static FLASH Bank configuration here - FIXME XXX */ + + size_b0 = flash_get_size ((vu_long *) FLASH_BASE0_PRELIM, + &flash_info[0]); + + if (flash_info[0].flash_id == FLASH_UNKNOWN) { + printf ("## Unknown FLASH on Bank 0- Size=0x%08lx=%ld MB\n", + size_b0, size_b0 << 20); + } + + /* Only one bank */ + /* Setup offsets */ + flash_get_offsets (FLASH_BASE0_PRELIM, &flash_info[0]); + + /* Monitor protection ON by default */ + (void) flash_protect (FLAG_PROTECT_SET, + FLASH_BASE0_PRELIM, + FLASH_BASE0_PRELIM + monitor_flash_len - 1, + &flash_info[0]); + flash_info[0].size = size_b0; + + return size_b0; +} + + +/*-----------------------------------------------------------------------*/ +/* + * This implementation assumes that the flash chips are uniform sector + * devices. This is true for all likely flash devices on a HCUx. + */ +static void flash_get_offsets (ulong base, flash_info_t * info) +{ + unsigned idx; + unsigned long sector_size = info->size / info->sector_count; + + for (idx = 0; idx < info->sector_count; idx += 1) { + info->start[idx] = base + (idx * sector_size); + } +} + +/*-----------------------------------------------------------------------*/ +void flash_print_info (flash_info_t * info) +{ + int i; + int k; + int size; + int erased; + volatile unsigned long *flash; + + if (info->flash_id == FLASH_UNKNOWN) { + printf ("missing or unknown FLASH type\n"); + return; + } + + switch (info->flash_id & FLASH_VENDMASK) { + case FLASH_MAN_AMD: + printf ("AMD "); + break; + case FLASH_MAN_FUJ: + printf ("FUJITSU "); + break; + case FLASH_MAN_SST: + printf ("SST "); + break; + case FLASH_MAN_STM: + printf ("ST Micro "); + break; + default: + printf ("Unknown Vendor "); + break; + } + + /* (Reduced table of only parts expected in HCUx boards.) */ + switch (info->flash_id) { + case FLASH_MAN_AMD | FLASH_AM040: + printf ("AM29F040 (512 Kbit, uniform sector size)\n"); + break; + case FLASH_MAN_STM | FLASH_AM040: + printf ("MM29W040W (512 Kbit, uniform sector size)\n"); + break; + default: + printf ("Unknown Chip Type\n"); + break; + } + + printf (" Size: %ld KB in %d Sectors\n", + info->size >> 10, info->sector_count); + + printf (" Sector Start Addresses:"); + for (i = 0; i < info->sector_count; ++i) { + /* + * Check if whole sector is erased + */ + if (i != (info->sector_count - 1)) + size = info->start[i + 1] - info->start[i]; + else + size = info->start[0] + info->size - info->start[i]; + erased = 1; + flash = (volatile unsigned long *) info->start[i]; + size = size >> 2; /* divide by 4 for longword access */ + for (k = 0; k < size; k++) { + if (*flash++ != 0xffffffff) { + erased = 0; + break; + } + } + + if ((i % 5) == 0) + printf ("\n "); + printf (" %08lX%s%s", + info->start[i], + erased ? " E" : " ", info->protect[i] ? "RO " : " " + ); + } + printf ("\n"); + return; +} + +/*-----------------------------------------------------------------------*/ + +/* + * The following code cannot be run from FLASH! + */ +static ulong flash_get_size (vu_long * addr, flash_info_t * info) +{ + short i; + FLASH_WORD_SIZE value; + ulong base = (ulong) addr; + volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *) addr; + + /* Write auto select command: read Manufacturer ID */ + asm("isync"); + addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA; + asm("isync"); + addr2[ADDR1] = (FLASH_WORD_SIZE) 0x00550055; + asm("isync"); + addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00900090; + asm("isync"); + + value = addr2[0]; + asm("isync"); + + switch (value) { + case (FLASH_WORD_SIZE) AMD_MANUFACT: + info->flash_id = FLASH_MAN_AMD; + break; + case (FLASH_WORD_SIZE) FUJ_MANUFACT: + info->flash_id = FLASH_MAN_FUJ; + break; + case (FLASH_WORD_SIZE) SST_MANUFACT: + info->flash_id = FLASH_MAN_SST; + break; + case (FLASH_WORD_SIZE)STM_MANUFACT: + info->flash_id = FLASH_MAN_STM; + break; + default: + info->flash_id = FLASH_UNKNOWN; + info->sector_count = 0; + info->size = 0; + printf("Unknown flash manufacturer code: 0x%x at %p\n", + value, addr); + addr2[ADDR0] = (FLASH_WORD_SIZE) 0; + return (0); /* no or unknown flash */ + } + + value = addr2[1]; /* device ID */ + + switch (value) { + case (FLASH_WORD_SIZE) AMD_ID_F040B: + info->flash_id += FLASH_AM040; + info->sector_count = 8; + info->size = 0x0080000; /* => 512 ko */ + break; + case (FLASH_WORD_SIZE) AMD_ID_LV040B: + info->flash_id += FLASH_AM040; + info->sector_count = 8; + info->size = 0x0080000; /* => 512 ko */ + break; + case (FLASH_WORD_SIZE)STM_ID_M29W040B: /* most likele HCU5 chip */ + info->flash_id += FLASH_AM040; + info->sector_count = 8; + info->size = 0x0080000; /* => 512 ko */ + break; + default: + info->flash_id = FLASH_UNKNOWN; + return (0); /* => no or unknown flash */ + + } + + /* Calculate the sector offsets (Use HCUx Optimized code). */ + flash_get_offsets(base, info); + + /* check for protected sectors */ + for (i = 0; i < info->sector_count; i++) { + /* read sector protection at sector address, + *(A7 .. A0) = 0x02 + * D0 = 1 if protected + */ + addr2 = (volatile FLASH_WORD_SIZE *) (info->start[i]); + if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) + info->protect[i] = 0; + else + info->protect[i] = addr2[2] & 1; + } + + /* + * Prevent writes to uninitialized FLASH. + */ + if (info->flash_id != FLASH_UNKNOWN) { + addr2 = (FLASH_WORD_SIZE *) info->start[0]; + *addr2 = (FLASH_WORD_SIZE) 0x00F000F0; /* reset bank */ + } + + return (info->size); +} + +int wait_for_DQ7 (flash_info_t * info, int sect) +{ + ulong start, now, last; + volatile FLASH_WORD_SIZE *addr = + (FLASH_WORD_SIZE *) (info->start[sect]); + + start = get_timer (0); + last = start; + while ((addr[0] & (FLASH_WORD_SIZE) 0x00800080) != + (FLASH_WORD_SIZE) 0x00800080) { + if ((now = get_timer (start)) > CFG_FLASH_ERASE_TOUT) { + printf ("Timeout\n"); + return -1; + } + /* show that we're waiting */ + if ((now - last) > 1000) { /* every second */ + putc ('.'); + last = now; + } + } + return 0; +} + +/*-----------------------------------------------------------------------*/ + +int flash_erase (flash_info_t * info, int s_first, int s_last) +{ + volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *) (info->start[0]); + volatile FLASH_WORD_SIZE *addr2; + int flag, prot, sect, l_sect; + int i; + + if ((s_first < 0) || (s_first > s_last)) { + if (info->flash_id == FLASH_UNKNOWN) { + printf ("- missing\n"); + } else { + printf ("- no sectors to erase\n"); + } + return 1; + } + + if (info->flash_id == FLASH_UNKNOWN) { + printf ("Can't erase unknown flash type - aborted\n"); + return 1; + } + + prot = 0; + for (sect = s_first; sect <= s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + + if (prot) { + printf ("- Warning: %d protected sectors not erased!\n", + prot); + } else { + printf ("\n"); + } + + l_sect = -1; + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts (); + + /* Start erase on unprotected sectors */ + for (sect = s_first; sect <= s_last; sect++) { + if (info->protect[sect] == 0) { /* not protected */ + addr2 = (FLASH_WORD_SIZE *) (info->start[sect]); + printf ("Erasing sector %p\n", addr2); /* CLH */ + + if ((info->flash_id & FLASH_VENDMASK) == + FLASH_MAN_SST) { + addr[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA; + addr[ADDR1] = (FLASH_WORD_SIZE) 0x00550055; + addr[ADDR0] = (FLASH_WORD_SIZE) 0x00800080; + addr[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA; + addr[ADDR1] = (FLASH_WORD_SIZE) 0x00550055; + /* block erase */ + addr2[0] = (FLASH_WORD_SIZE) 0x00500050; + for (i = 0; i < 50; i++) udelay (1000); + } else { + addr[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA; + addr[ADDR1] = (FLASH_WORD_SIZE) 0x00550055; + addr[ADDR0] = (FLASH_WORD_SIZE) 0x00800080; + addr[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA; + addr[ADDR1] = (FLASH_WORD_SIZE) 0x00550055; + /* sector erase */ + addr2[0] = (FLASH_WORD_SIZE) 0x00300030; + } + l_sect = sect; + /* + * Wait for each sector to complete, it's more + * reliable. According to AMD Spec, you must + * issue all erase commands within a specified + * timeout. This has been seen to fail, especially + * if printf()s are included (for debug)!! + */ + wait_for_DQ7 (info, sect); + } + } + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts (); + + /* wait at least 80us - let's wait 1 ms */ + udelay (1000); + +#if 0 + /* + * We wait for the last triggered sector + */ + if (l_sect < 0) + goto DONE; + wait_for_DQ7 (info, l_sect); + +DONE: +#endif + /* reset to read mode */ + addr = (FLASH_WORD_SIZE *) info->start[0]; + addr[0] = (FLASH_WORD_SIZE) 0x00F000F0; /* reset bank */ + + printf (" done\n"); + return 0; +} + +/*----------------------------------------------------------------------- + * Copy memory to flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ + +int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) +{ + ulong cp, wp, data; + int i, l, rc; + + wp = (addr & ~3); /* get lower word aligned address */ + + /* + * handle unaligned start bytes + */ + if ((l = addr - wp) != 0) { + data = 0; + for (i = 0, cp = wp; i < l; ++i, ++cp) { + data = (data << 8) | (*(uchar *) cp); + } + for (; i < 4 && cnt > 0; ++i) { + data = (data << 8) | *src++; + --cnt; + ++cp; + } + for (; cnt == 0 && i < 4; ++i, ++cp) { + data = (data << 8) | (*(uchar *) cp); + } + + if ((rc = write_word (info, wp, data)) != 0) { + return (rc); + } + wp += 4; + } + + /* + * handle word aligned part + */ + while (cnt >= 4) { + data = 0; + for (i = 0; i < 4; ++i) { + data = (data << 8) | *src++; + } + if ((rc = write_word (info, wp, data)) != 0) { + return (rc); + } + wp += 4; + cnt -= 4; + } + + if (cnt == 0) { + return (0); + } + + /* + * handle unaligned tail bytes + */ + data = 0; + for (i = 0, cp = wp; i < 4 && cnt > 0; ++i, ++cp) { + data = (data << 8) | *src++; + --cnt; + } + for (; i < 4; ++i, ++cp) { + data = (data << 8) | (*(uchar *) cp); + } + + return (write_word (info, wp, data)); +} + +/*----------------------------------------------------------------------- + * Write a word to Flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +static int write_word (flash_info_t * info, ulong dest, ulong data) +{ + volatile FLASH_WORD_SIZE *addr2 = + (FLASH_WORD_SIZE *) (info->start[0]); + volatile FLASH_WORD_SIZE *dest2 = (FLASH_WORD_SIZE *) dest; + volatile FLASH_WORD_SIZE *data2 = (FLASH_WORD_SIZE *) & data; + ulong start; + int i; + + /* Check if Flash is (sufficiently) erased */ + if ((*((volatile FLASH_WORD_SIZE *) dest) & + (FLASH_WORD_SIZE) data) != (FLASH_WORD_SIZE) data) { + return (2); + } + + for (i = 0; i < 4 / sizeof (FLASH_WORD_SIZE); i++) { + int flag; + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts (); + + addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA; + addr2[ADDR1] = (FLASH_WORD_SIZE) 0x00550055; + addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00A000A0; + + dest2[i] = data2[i]; + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts (); + + /* data polling for D7 */ + start = get_timer (0); + while ((dest2[i] & (FLASH_WORD_SIZE) 0x00800080) != + (data2[i] & (FLASH_WORD_SIZE) 0x00800080)) { + + if (get_timer (start) > CFG_FLASH_WRITE_TOUT) { + return (1); + } + } + } + + return (0); +} diff --git a/board/netstal/common/nm_bsp.c b/board/netstal/common/nm_bsp.c new file mode 100644 index 000000000..ee1b684ab --- /dev/null +++ b/board/netstal/common/nm_bsp.c @@ -0,0 +1,42 @@ +/* + *(C) Copyright 2005-2007 Netstal Maschinen AG + * Niklaus Giger (Niklaus.Giger@netstal.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +#include +#include + +#if (CONFIG_COMMANDS & CFG_CMD_BSP) +/* + * Command nm_bsp: Netstal Maschinen BSP specific command + */ +int nm_bsp(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + printf("%s: flag %d, argc %d, argv[0] %s\n", __FUNCTION__, + flag, argc, argv[0]); + printf("Netstal Maschinen BSP specific command. None at the moment.\n"); + return 0; +} + +U_BOOT_CMD( + nm_bsp, 1, 1, nm_bsp, + "nm_bsp - Netstal Maschinen BSP specific command. \n", + "Help for Netstal Maschinen BSP specific command.\n" + ); +#endif + From 6e5de26c6e7580faf16e87745cd488b92b492d0c Mon Sep 17 00:00:00 2001 From: Niklaus Giger Date: Fri, 27 Jul 2007 11:30:33 +0200 Subject: [PATCH 075/259] Add PPC4xx-HCU4 and HCU5 boards: HCU4 files Signed-off-by: Niklaus Giger --- board/netstal/hcu4/hcu4.c | 393 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 393 insertions(+) create mode 100644 board/netstal/hcu4/hcu4.c diff --git a/board/netstal/hcu4/hcu4.c b/board/netstal/hcu4/hcu4.c new file mode 100644 index 000000000..deb7d2da9 --- /dev/null +++ b/board/netstal/hcu4/hcu4.c @@ -0,0 +1,393 @@ +/* + *(C) Copyright 2005-2007 Netstal Maschinen AG + * Niklaus Giger (Niklaus.Giger@netstal.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +#include +#include +#include +#include +#include +#include "../common/nm_bsp.c" + +DECLARE_GLOBAL_DATA_PTR; + +void sysLedSet(u32 value); +long int spd_sdram(int(read_spd)(uint addr)) +#ifdef CONFIG_SPD_EEPROM + #define DEBUG +#endif + +#if defined(DEBUG) +void show_sdram_registers(void); +#endif + +/* + * This function is run very early, out of flash, and before devices are + * initialized. It is called by lib_ppc/board.c:board_init_f by virtue + * of being in the init_sequence array. + * + * The SDRAM has been initialized already -- start.S:start called + * init.S:init_sdram early on -- but it is not yet being used for + * anything, not even stack. So be careful. + */ + +#define CPC0_CR0 0xb1 /* Chip control register 0 */ +#define CPC0_CR1 0xb2 /* Chip control register 1 */ +/* Attention: If you want 1 microsecs times from the external oscillator + * use 0x00804051. But this causes problems with u-boot and linux! + */ +#define CPC0_CR1_VALUE 0x00004051 +#define CPC0_ECR 0xaa /* Edge condition register */ +#define EBC0_CFG 0x23 /* External Peripheral Control Register */ +#define CPC0_EIRR 0xb6 /* External Interrupt Register */ + + +int board_early_init_f (void) +{ + /*-------------------------------------------------------------------+ + | Interrupt controller setup for the HCU4 board. + | Note: IRQ 0-15 405GP internally generated; high; level sensitive + | IRQ 16 405GP internally generated; low; level sensitive + | IRQ 17-24 RESERVED/UNUSED + | IRQ 31 (EXT IRQ 6) (unused) + +-------------------------------------------------------------------*/ + mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */ + mtdcr (uicer, 0x00000000); /* disable all ints */ + mtdcr (uiccr, 0x00000000); /* set all to be non-critical */ + mtdcr (uicpr, 0xFFFFFF87); /* set int polarities */ + mtdcr (uictr, 0x10000000); /* set int trigger levels */ + mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */ + + mtdcr(CPC0_CR1, CPC0_CR1_VALUE); + mtdcr(CPC0_ECR, 0x60606000); + mtdcr(CPC0_EIRR, 0x7c000000); + + return 0; +} + +#ifdef CONFIG_BOARD_PRE_INIT +int board_pre_init (void) +{ + return board_early_init_f (); +} + +#endif + +enum { + /* HW_GENERATION_HCU wird nicht mehr unterstuetzt */ + HW_GENERATION_HCU2 = 0x10, + HW_GENERATION_HCU3 = 0x10, + HW_GENERATION_HCU4 = 0x20, + HW_GENERATION_MCU = 0x08, + HW_GENERATION_MCU20 = 0x0a, + HW_GENERATION_MCU25 = 0x09, +}; + +int checkboard (void) +{ +#define HCU_MACH_VERSIONS_REGISTER ( 0x7C000000 + 0xF00000 ) + unsigned j; + uint16_t *boardVersReg = (uint16_t *) HCU_MACH_VERSIONS_REGISTER; + uint16_t generation = *boardVersReg & 0xf0; + uint16_t index = *boardVersReg & 0x0f; + /* Force /RTS to active. The board it not wired quite + correctly to use cts/rtc flow control, so just force the + /RST active and forget about it. */ + writeb (readb (0xef600404) | 0x03, 0xef600404); + printf ("\nNetstal Maschinen AG "); + if (generation == HW_GENERATION_HCU3) + printf ("HCU3: index %d\n\n", index); + else if (generation == HW_GENERATION_HCU4) + printf ("HCU4: index %d\n\n", index); + /* GPIO here noch nicht richtig initialisert !!! */ + sysLedSet(0); + for (j=0; j < 7;j++) { + sysLedSet(1 << j); + udelay(50*1000); + } + return 0; +} + +u32 sysLedGet(void) +{ + return( ~( (*(u32 *)GPIO0_OR)) >> 23) & 0xff; +} + +void sysLedSet(u32 value /* value to place in LEDs */) +{ + u32 tmp = ~value; + u32 *ledReg; + tmp = (tmp << 23) | 0x7FFFFF; + ledReg = (u32 *)GPIO0_OR; + *ledReg = tmp; +} + +/* + * sdram_init - Dummy implementation for start.S, spd_sdram or initdram + * used for HCUx + */ +void sdram_init(void) +{ + return; +} + +#define mtsdram(reg, data) { mtdcr(memcfga,reg);mtdcr(memcfgd,data); } +#define mfsdram(value, reg) { mtdcr(memcfga,reg); value = mfdcr(memcfgd); } + +#if defined(DEBUG) +void show_sdram_registers(void) +{ + u32 value; + printf ("SDRAM Controller Registers --\n"); + mfsdram(value, mem_mcopt1); + printf (" SDRAM0_CFG : 0x%08x\n", value); + mfsdram(value, mem_status); + printf (" SDRAM0_STATUS: 0x%08x\n", value); + mfsdram(value, mem_mb0cf); + printf (" SDRAM0_B0CR : 0x%08x\n", value); + mfsdram(value, mem_mb1cf); + printf (" SDRAM0_B1CR : 0x%08x\n", value); + mfsdram(value, mem_sdtr1); + printf (" SDRAM0_TR : 0x%08x\n", value); + mfsdram(value, mem_rtr); + printf (" SDRAM0_RTR : 0x%08x\n", value); +} +#endif + +#define SDRAM_LEN 32*1024*1024 /* 32 MB -RAM */ + +/* + * this is even after checkboard. It returns the size of the SDRAM + * that we have installed. This function is called by board_init_f + * in lib_ppc/board.c to initialize the memory and return what I + * found. These are default value, which will be overridden later. + */ + +long int fixed_hcu4_sdram (int board_type) +{ +#ifdef DEBUG + printf (__FUNCTION__); +#endif + /* disable memory controller */ + mtdcr (memcfga, mem_mcopt1); + mtdcr (memcfgd, 0x00000000); + + udelay (500); + + /* Clear SDRAM0_BESR0 (Bus Error Syndrome Register) */ + mtdcr (memcfga, mem_besra); + mtdcr (memcfgd, 0xffffffff); + + /* Clear SDRAM0_BESR1 (Bus Error Syndrome Register) */ + mtdcr (memcfga, mem_besrb); + mtdcr (memcfgd, 0xffffffff); + + /* Clear SDRAM0_ECCCFG (disable ECC) */ + mtdcr (memcfga, mem_ecccf); + mtdcr (memcfgd, 0x00000000); + + /* Clear SDRAM0_ECCESR (ECC Error Syndrome Register) */ + mtdcr (memcfga, mem_eccerr); + mtdcr (memcfgd, 0xffffffff); + + /* Timing register: CASL=2, PTA=2, CTP=2, LDF=1, RFTA=5, RCD=2 + * TODO ngngng + */ + mtdcr (memcfga, mem_sdtr1); + mtdcr (memcfgd, 0x008a4015); + + /* Memory Bank 0 Config == BA=0x00000000, SZ=64M, AM=3, BE=1 + * TODO ngngng + */ + mtdcr (memcfga, mem_mb0cf); + mtdcr (memcfgd, 0x00062001); + + /* refresh timer = 0x400 */ + mtdcr (memcfga, mem_rtr); + mtdcr (memcfgd, 0x04000000); + + /* Power management idle timer set to the default. */ + mtdcr (memcfga, mem_pmit); + mtdcr (memcfgd, 0x07c00000); + + udelay (500); + + /* Enable banks (DCE=1, BPRF=1, ECCDD=1, EMDUL=1) TODO */ + mtdcr (memcfga, mem_mcopt1); + mtdcr (memcfgd, 0x90800000); + +#ifdef DEBUG + printf ("%s: done\n", __FUNCTION__); +#endif + return SDRAM_LEN; +} + +/*---------------------------------------------------------------------------+ + * getSerialNr + *---------------------------------------------------------------------------*/ +static u32 getSerialNr(void) +{ + u32 *serial = (u32 *)CFG_FLASH_BASE; + if (*serial == 0xffffffff) { + return get_ticks(); + } + return *serial; +} + + +/*---------------------------------------------------------------------------+ + * misc_init_r. + *---------------------------------------------------------------------------*/ + +int misc_init_r(void) +{ + char *s = getenv("ethaddr"); + char *e; + int i; + u32 serial = getSerialNr(); + for (i = 0; i < 6; ++i) { + gd->bd->bi_enetaddr[i] = s ? simple_strtoul (s, &e, 16) : 0; + if (s) + s = (*e) ? e + 1 : e; + } + if (gd->bd->bi_enetaddr[3] == 0 && + gd->bd->bi_enetaddr[4] == 0 && + gd->bd->bi_enetaddr[5] == 0) { + char ethaddr[22]; + /* [0..3] Must be in sync with CONFIG_ETHADDR */ + gd->bd->bi_enetaddr[0] = 0x00; + gd->bd->bi_enetaddr[1] = 0x60; + gd->bd->bi_enetaddr[2] = 0x13; + gd->bd->bi_enetaddr[3] = (serial >> 16) & 0xff; + gd->bd->bi_enetaddr[4] = (serial >> 8) & 0xff; + gd->bd->bi_enetaddr[5] = (serial >> 0) & 0xff; + sprintf (ethaddr, "%02X:%02X:%02X:%02X:%02X:%02X\0", + gd->bd->bi_enetaddr[0], gd->bd->bi_enetaddr[1], + gd->bd->bi_enetaddr[2], gd->bd->bi_enetaddr[3], + gd->bd->bi_enetaddr[4], gd->bd->bi_enetaddr[5]) ; + printf("%s: Setting eth %s serial 0x%x\n", __FUNCTION__, + ethaddr, serial); + setenv ("ethaddr", ethaddr); + } + return 0; +} + +#define DO_UGLY_SDRAM_WORKAROUND +#ifdef DO_UGLY_SDRAM_WORKAROUND + #include "i2c.h" +void set_spd_default_value(unsigned int spd_addr,uchar def_val) +{ + uchar value; + int res = i2c_read(SPD_EEPROM_ADDRESS, spd_addr, 1, &value, 1) ; + if (res == 0 && value == 0xff) { + res = i2c_write(SPD_EEPROM_ADDRESS, + spd_addr, 1, &def_val, 1) ; +#ifdef DEBUG + printf("%s: Setting spd offset %3d to %3d res %d\n", + __FUNCTION__, spd_addr, def_val, res); +#endif + } +} +#endif + +long int initdram(int board_type) +{ + long dram_size = 0; + +#if !defined(CONFIG_SPD_EEPROM) + dram_size = fixed_hcu4_sdram(); +#else +#ifdef DO_UGLY_SDRAM_WORKAROUND + /* Workaround if you have no working I2C-EEPROM-SPD-configuration */ + i2c_init(CFG_I2C_SPEED, CFG_I2C_SLAVE); + set_spd_default_value(2, 4); /* SDRAM Type */ + set_spd_default_value(7, 0); /* module width, high byte */ + set_spd_default_value(12, 1); /* Refresh or 0x81 */ + + /* Only correct for HCU3 with 32 MB RAM*/ + /* Number of bytes used by module manufacturer */ + set_spd_default_value( 0, 128); + set_spd_default_value( 1, 11 ); /* Total SPD memory size */ + set_spd_default_value( 2, 4 ); /* Memory type */ + set_spd_default_value( 3, 12 ); /* Number of row address bits */ + set_spd_default_value( 4, 9 ); /* Number of column address bits */ + set_spd_default_value( 5, 1 ); /* Number of module rows */ + set_spd_default_value( 6, 32 ); /* Module data width, LSB */ + set_spd_default_value( 7, 0 ); /* Module data width, MSB */ + set_spd_default_value( 8, 1 ); /* Module interface signal levels */ + /* SDRAM cycle time for highest CL (Tclk) */ + set_spd_default_value( 9, 112); + /* SDRAM access time from clock for highest CL (Tac) */ + set_spd_default_value(10, 84 ); + set_spd_default_value(11, 2 ); /* Module configuration type */ + set_spd_default_value(12, 128); /* Refresh rate/type */ + set_spd_default_value(13, 16 ); /* Primary SDRAM width */ + set_spd_default_value(14, 8 ); /* Error Checking SDRAM width */ + /* SDRAM device attributes, min clock delay for back to back */ + /*random column addresses (Tccd) */ + set_spd_default_value(15, 1 ); + /* SDRAM device attributes, burst lengths supported */ + set_spd_default_value(16, 143); + /* SDRAM device attributes, number of banks on SDRAM device */ + set_spd_default_value(17, 4 ); + /* SDRAM device attributes, CAS latency */ + set_spd_default_value(18, 6 ); + /* SDRAM device attributes, CS latency */ + set_spd_default_value(19, 1 ); + /* SDRAM device attributes, WE latency */ + set_spd_default_value(20, 1 ); + set_spd_default_value(21, 0 ); /* SDRAM module attributes */ + /* SDRAM device attributes, general */ + set_spd_default_value(22, 14 ); + /* SDRAM cycle time for 2nd highest CL (Tclk) */ + set_spd_default_value(23, 117); + /* SDRAM access time from clock for2nd highest CL (Tac) */ + set_spd_default_value(24, 84 ); + /* SDRAM cycle time for 3rd highest CL (Tclk) */ + set_spd_default_value(25, 0 ); + /* SDRAM access time from clock for3rd highest CL (Tac) */ + set_spd_default_value(26, 0 ); + set_spd_default_value(27, 15 ); /* Minimum row precharge time (Trp) */ + /* Minimum row active to row active delay (Trrd) */ + set_spd_default_value(28, 14 ); + set_spd_default_value(29, 15 ); /* Minimum CAS to RAS delay (Trcd) */ + set_spd_default_value(30, 37 ); /* Minimum RAS pulse width (Tras) */ + set_spd_default_value(31, 8 ); /* Module bank density */ + /* Command and Address signal input setup time */ + set_spd_default_value(32, 21 ); + /* Command and Address signal input hold time */ + set_spd_default_value(33, 8 ); + set_spd_default_value(34, 21 ); /* Data signal input setup time */ + set_spd_default_value(35, 8 ); /* Data signal input hold time */ +#endif /* DO_UGLY_SDRAM_WORKAROUND */ + dram_size = spd_sdram(0); +#endif + +#ifdef DEBUG + show_sdram_registers(); +#endif + +#if defined(CFG_DRAM_TEST) + bcu4_testdram(dram_size); + printf("%s %d MB of SDRAM\n", __FUNCTION__, dram_size/(1024*1024)); +#endif + return dram_size; +} + + From 157cda4d0c3d592ccbb19bbfc07d9251894f0894 Mon Sep 17 00:00:00 2001 From: Niklaus Giger Date: Fri, 27 Jul 2007 11:31:22 +0200 Subject: [PATCH 076/259] Add PPC4xx-HCU4 and HCU5 boards: HCU5 files Signed-off-by: Niklaus Giger --- board/netstal/hcu5/hcu5.c | 526 +++++++++++++++++++++++++++++++++++++ board/netstal/hcu5/init.S | 81 ++++++ board/netstal/hcu5/sdram.c | 299 +++++++++++++++++++++ 3 files changed, 906 insertions(+) create mode 100644 board/netstal/hcu5/hcu5.c create mode 100644 board/netstal/hcu5/init.S create mode 100644 board/netstal/hcu5/sdram.c diff --git a/board/netstal/hcu5/hcu5.c b/board/netstal/hcu5/hcu5.c new file mode 100644 index 000000000..59107b920 --- /dev/null +++ b/board/netstal/hcu5/hcu5.c @@ -0,0 +1,526 @@ +/* + *(C) Copyright 2005-2007 Netstal Maschinen AG + * Niklaus Giger (Niklaus.Giger@netstal.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +void sysLedSet(u32 value); + +extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; + +#define mtcpr0(reg, data) do { mtdcr(CPR0_CFGADDR,reg); \ + mtdcr(CPR0_CFGDATA,data); } while (0) +#define mfcpr0(reg, data) do { mtdcr(CPR0_CFGADDR,reg); \ + data = mfdcr(CPR0_CFGDATA); } while (0) + +#define SDR0_CP440 0x0180 + +/* + * This function is run very early, out of flash, and before devices are + * initialized. It is called by lib_ppc/board.c:board_init_f by virtue + * of being in the init_sequence array. + * + * The SDRAM has been initialized already -- start.S:start called + * init.S:init_sdram early on -- but it is not yet being used for + * anything, not even stack. So be careful. + */ + +int board_early_init_f(void) +{ + u32 reg; + +#undef BOOTSTRAP_OPTION_A_ACTIVE +#ifdef BOOTSTRAP_OPTION_A_ACTIVE + /* Booting with Bootstrap Option A + * First boot, with CPR0_ICFG_RLI_MASK == 0 + * no we setup varios boot strapping register, + * then we do reset the PPC440 using a chip reset + * Unfortunately, we cannot use this option, as Nto1 is not set + * with Bootstrap Option A and cannot be changed later on by SW + * There are no other possible boostrap options with a 8 bit ROM + * See Errata (Version 1.04) CHIP_9 + */ + + u32 cpr0icfg; + u32 dbcr; + mfcpr0(CPR0_ICFG, cpr0icfg); + if ( ! (cpr0icfg & CPR0_ICFG_RLI_MASK ) ) { + mtcpr0(CPR0_MALD, 0x02000000); + mtcpr0(CPR0_OPBD, 0x02000000); + mtcpr0(CPR0_PERD, 0x05000000); /* 1:5 */ + mtcpr0(CPR0_PLLC, 0x40000238); + mtcpr0(CPR0_PLLD, 0x01010414); + mtcpr0(CPR0_PRIMAD, 0x01000000); + mtcpr0(CPR0_PRIMBD, 0x01000000); + mtcpr0(CPR0_SPCID, 0x03000000); + mtsdr(SDR0_PFC0, 0x00003E00); /* [CTE] = 0 */ + mtsdr(SDR0_CP440, 0x0EAAEA02); /* [Nto1] = 1*/ + mtcpr0(CPR0_ICFG, cpr0icfg | CPR0_ICFG_RLI_MASK); + + /* + * Initiate system reset in debug control register DBCR + */ + dbcr = mfspr(dbcr0); + #define SYSTEM_RESET 0x30000000 + #define CHIP_RESET 0x20000000 + mtspr(dbcr0, dbcr | CHIP_RESET ); + } + mtsdr(SDR0_CP440, 0x0EAAEA02); /* [Nto1] = 1*/ +#endif + mtdcr(ebccfga, xbcfg); + mtdcr(ebccfgd, 0xb8400000); + + /*-------------------------------------------------------------------- + * Setup the GPIO pins + *-------------------------------------------------------------------*/ + /* test-only: take GPIO init from pcs440ep ???? in config file */ + out32(GPIO0_OR, 0x00000000); + out32(GPIO0_TCR, 0x7C2FF1CF); + out32(GPIO0_OSRL, 0x40055000); + out32(GPIO0_OSRH, 0x00000000); + out32(GPIO0_TSRL, 0x40055000); + out32(GPIO0_TSRH, 0x00000400); + out32(GPIO0_ISR1L, 0x40000000); + out32(GPIO0_ISR1H, 0x00000000); + out32(GPIO0_ISR2L, 0x00000000); + out32(GPIO0_ISR2H, 0x00000000); + out32(GPIO0_ISR3L, 0x00000000); + out32(GPIO0_ISR3H, 0x00000000); + + out32(GPIO1_OR, 0x00000000); + out32(GPIO1_TCR, 0xC6007FFF); + out32(GPIO1_OSRL, 0x00140000); + out32(GPIO1_OSRH, 0x00000000); + out32(GPIO1_TSRL, 0x00000000); + out32(GPIO1_TSRH, 0x00000000); + out32(GPIO1_ISR1L, 0x05415555); + out32(GPIO1_ISR1H, 0x40000000); + out32(GPIO1_ISR2L, 0x00000000); + out32(GPIO1_ISR2H, 0x00000000); + out32(GPIO1_ISR3L, 0x00000000); + out32(GPIO1_ISR3H, 0x00000000); + + /*-------------------------------------------------------------------- + * Setup the interrupt controller polarities, triggers, etc. + *-------------------------------------------------------------------*/ + mtdcr(uic0sr, 0xffffffff); /* clear all */ + mtdcr(uic0er, 0x00000000); /* disable all */ + mtdcr(uic0cr, 0x00000005); /* ATI & UIC1 crit are critical */ + mtdcr(uic0pr, 0xfffff7ff); /* per ref-board manual */ + mtdcr(uic0tr, 0x00000000); /* per ref-board manual */ + mtdcr(uic0vr, 0x00000000); /* int31 highest, base=0x000 */ + mtdcr(uic0sr, 0xffffffff); /* clear all */ + + mtdcr(uic1sr, 0xffffffff); /* clear all */ + mtdcr(uic1er, 0x00000000); /* disable all */ + mtdcr(uic1cr, 0x00000000); /* all non-critical */ + mtdcr(uic1pr, 0xffffffff); /* per ref-board manual */ + mtdcr(uic1tr, 0x00000000); /* per ref-board manual */ + mtdcr(uic1vr, 0x00000000); /* int31 highest, base=0x000 */ + mtdcr(uic1sr, 0xffffffff); /* clear all */ + + mtdcr(uic2sr, 0xffffffff); /* clear all */ + mtdcr(uic2er, 0x00000000); /* disable all */ + mtdcr(uic2cr, 0x00000000); /* all non-critical */ + mtdcr(uic2pr, 0xffffffff); /* per ref-board manual */ + mtdcr(uic2tr, 0x00000000); /* per ref-board manual */ + mtdcr(uic2vr, 0x00000000); /* int31 highest, base=0x000 */ + mtdcr(uic2sr, 0xffffffff); /* clear all */ + mtsdr(sdr_pfc0, 0x00003E00); /* Pin function: */ + mtsdr(sdr_pfc1, 0x00848000); /* Pin function: UART0 has 4 pins */ + + /* PCI arbiter enabled */ + mfsdr(sdr_pci0, reg); + mtsdr(sdr_pci0, 0x80000000 | reg); + + pci_pre_init(0); + + /* setup BOOT FLASH */ + mtsdr(SDR0_CUST0, 0xC0082350); + + return 0; +} + +#ifdef CONFIG_BOARD_PRE_INIT +int board_pre_init (void) +{ + return board_early_init_f (); +} + +#endif + +enum { + /* HW_GENERATION_HCU1 is no longer supported */ + HW_GENERATION_HCU2 = 0x10, + HW_GENERATION_HCU3 = 0x10, + HW_GENERATION_HCU4 = 0x20, + HW_GENERATION_HCU5 = 0x30, + HW_GENERATION_MCU = 0x08, + HW_GENERATION_MCU20 = 0x0a, + HW_GENERATION_MCU25 = 0x09, +}; + +int checkboard (void) +{ +#define SDR0_ECID0 0x0080 +#define SDR0_ECID1 0x0081 +#define SDR0_ECID2 0x0082 +#define SDR0_ECID3 0x0083 + unsigned j; + uint16_t *hwVersReg = (uint16_t *) HCU_HW_VERSION_REGISTER; + uint16_t *boardVersReg = (uint16_t *) HCU_CPLD_VERSION_REGISTER; + uint16_t generation = *boardVersReg & 0xf0; + uint16_t index = *boardVersReg & 0x0f; + ulong ecid0, ecid1, ecid2, ecid3; + printf ("Netstal Maschinen AG: "); + if (generation == HW_GENERATION_HCU3) + printf ("HCU3: index %d", index); + else if (generation == HW_GENERATION_HCU4) + printf ("HCU4: index %d", index); + else if (generation == HW_GENERATION_HCU5) + printf ("HCU5: index %d", index); + printf (" HW 0x%02x\n", *hwVersReg & 0xff); + mfsdr(SDR0_ECID0, ecid0); + mfsdr(SDR0_ECID1, ecid1); + mfsdr(SDR0_ECID2, ecid2); + mfsdr(SDR0_ECID3, ecid3); + + printf("Chip ID 0x%x 0x%x 0x%x 0x%x\n", ecid0, ecid1, ecid2, ecid3); + for (j=0; j < 6;j++) { + sysLedSet(1 << j); + udelay(200*1000); + } + return 0; +} + +#define SYS_IO_ADDRESS 0xcce00000 + +u32 sysLedGet(void) +{ + return in16(SYS_IO_ADDRESS) & 0x3f; +} + +void sysLedSet(u32 value /* value to place in LEDs */) +{ + out16(SYS_IO_ADDRESS, value); +} + +/*---------------------------------------------------------------------------+ + * getSerialNr + *---------------------------------------------------------------------------*/ +static u32 getSerialNr(void) +{ + u32 *serial = (u32 *)CFG_FLASH_BASE; + if (*serial == 0xffffffff) { + return get_ticks(); + } + return *serial; +} + + +/*---------------------------------------------------------------------------+ + * misc_init_r. + *---------------------------------------------------------------------------*/ + +#define DEFAULT_ETH_ADDR "ethaddr" +/* ethaddr for first or etha1ddr for second ethernet */ + +int misc_init_r(void) +{ + char *s = getenv(DEFAULT_ETH_ADDR); + char *e; + int i; + u32 serial = getSerialNr(); + unsigned long usb2d0cr = 0; + unsigned long usb2phy0cr, usb2h0cr = 0; + unsigned long sdr0_pfc1; + + for (i = 0; i < 6; ++i) { + gd->bd->bi_enetaddr[i] = s ? simple_strtoul (s, &e, 16) : 0; + if (s) + s = (*e) ? e + 1 : e; + } + if (gd->bd->bi_enetaddr[3] == 0 && + gd->bd->bi_enetaddr[4] == 0 && + gd->bd->bi_enetaddr[5] == 0) { + char ethaddr[22]; + /* Must be in sync with CONFIG_ETHADDR */ + gd->bd->bi_enetaddr[0] = 0x00; + gd->bd->bi_enetaddr[1] = 0x60; + gd->bd->bi_enetaddr[2] = 0x13; + gd->bd->bi_enetaddr[3] = (serial >> 16) & 0xff; + gd->bd->bi_enetaddr[4] = (serial >> 8) & 0xff; + /* byte[5].bit 0 must be zero */ + gd->bd->bi_enetaddr[5] = (serial >> 0) & 0xfe; + sprintf (ethaddr, "%02X:%02X:%02X:%02X:%02X:%02X\0", + gd->bd->bi_enetaddr[0], gd->bd->bi_enetaddr[1], + gd->bd->bi_enetaddr[2], gd->bd->bi_enetaddr[3], + gd->bd->bi_enetaddr[4], gd->bd->bi_enetaddr[5]) ; + printf("%s: Setting eth %s serial 0x%x\n", __FUNCTION__, + ethaddr, serial); + setenv (DEFAULT_ETH_ADDR, ethaddr); + } +#ifdef CFG_ENV_IS_IN_FLASH + /* Monitor protection ON by default */ + (void)flash_protect(FLAG_PROTECT_SET, + -CFG_MONITOR_LEN, + 0xffffffff, + &flash_info[0]); + + /* Env protection ON by default */ + (void)flash_protect(FLAG_PROTECT_SET, + CFG_ENV_ADDR_REDUND, + CFG_ENV_ADDR_REDUND + 2*CFG_ENV_SECT_SIZE - 1, + &flash_info[0]); +#endif + + /* + * USB stuff... + */ + + /* SDR Setting */ + mfsdr(SDR0_PFC1, sdr0_pfc1); + mfsdr(SDR0_USB2D0CR, usb2d0cr); + mfsdr(SDR0_USB2PHY0CR, usb2phy0cr); + mfsdr(SDR0_USB2H0CR, usb2h0cr); + + usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK; + usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL; /*0*/ + usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK; + usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ; /*1*/ + usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK; + usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS; /*0*/ + usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK; + usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST; /*1*/ + usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK; + usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST; /*1*/ + + /* An 8-bit/60MHz interface is the only possible alternative + when connecting the Device to the PHY */ + usb2h0cr = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK; + usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_16BIT_30MHZ; /*1*/ + + /* To enable the USB 2.0 Device function through the UTMI interface */ + usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK; + usb2d0cr = usb2d0cr | SDR0_USB2D0CR_USB2DEV_SELECTION; /*1*/ + + sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK; + sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_USB2D_SEL; /*0*/ + + mtsdr(SDR0_PFC1, sdr0_pfc1); + mtsdr(SDR0_USB2D0CR, usb2d0cr); + mtsdr(SDR0_USB2PHY0CR, usb2phy0cr); + mtsdr(SDR0_USB2H0CR, usb2h0cr); + + /*clear resets*/ + udelay (1000); + mtsdr(SDR0_SRST1, 0x00000000); + udelay (1000); + mtsdr(SDR0_SRST0, 0x00000000); + + printf("USB: Host(int phy) Device(ext phy)\n"); + + return 0; +} + +/************************************************************************* + * pci_pre_init + * + * This routine is called just prior to registering the hose and gives + * the board the opportunity to check things. Returning a value of zero + * indicates that things are bad & PCI initialization should be aborted. + * + * Different boards may wish to customize the pci controller structure + * (add regions, override default access routines, etc) or perform + * certain pre-initialization actions. + * + ************************************************************************/ +#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) +int pci_pre_init(struct pci_controller *hose) +{ + unsigned long addr; + + /*-------------------------------------------------------------------+ + * As of errata version 0.4, CHIP_8: Incorrect Write to DDR SDRAM. + * Workaround: Disable write pipelining to DDR SDRAM by setting + * PLB0_ACR[WRP] = 0. + *-------------------------------------------------------------------*/ + + /*-------------------------------------------------------------------+ + | Set priority for all PLB3 devices to 0. + | Set PLB3 arbiter to fair mode. + +-------------------------------------------------------------------*/ + mfsdr(sdr_amp1, addr); + mtsdr(sdr_amp1, (addr & 0x000000FF) | 0x0000FF00); + addr = mfdcr(plb3_acr); + // mtdcr(plb3_acr, addr & ~plb1_acr_wrp_mask); /* ngngng */ + mtdcr(plb3_acr, addr | 0x80000000); /* Sequoia */ + + /*-------------------------------------------------------------------+ + | Set priority for all PLB4 devices to 0. + +-------------------------------------------------------------------*/ + mfsdr(sdr_amp0, addr); + mtsdr(sdr_amp0, (addr & 0x000000FF) | 0x0000FF00); + addr = mfdcr(plb4_acr) | 0xa0000000; /* Was 0x8---- */ +// mtdcr(plb4_acr, addr & ~plb1_acr_wrp_mask); /* ngngng */ + mtdcr(plb4_acr, addr); /* Sequoia */ + + /*-------------------------------------------------------------------+ + | Set Nebula PLB4 arbiter to fair mode. + +-------------------------------------------------------------------*/ + /* Segment0 */ + addr = (mfdcr(plb0_acr) & ~plb0_acr_ppm_mask) | plb0_acr_ppm_fair; + addr = (addr & ~plb0_acr_hbu_mask) | plb0_acr_hbu_enabled; + addr = (addr & ~plb0_acr_rdp_mask) | plb0_acr_rdp_4deep; +// addr = (addr & ~plb0_acr_wrp_mask) ; /* ngngng */ + addr = (addr & ~plb0_acr_wrp_mask) | plb0_acr_wrp_2deep; /* Sequoia */ + + // mtdcr(plb0_acr, addr); /* Sequoia */ + mtdcr(plb0_acr, 0); // PATCH HAB: WRITE PIPELINING OFF + + + /* Segment1 */ + addr = (mfdcr(plb1_acr) & ~plb1_acr_ppm_mask) | plb1_acr_ppm_fair; + addr = (addr & ~plb1_acr_hbu_mask) | plb1_acr_hbu_enabled; + addr = (addr & ~plb1_acr_rdp_mask) | plb1_acr_rdp_4deep; + addr = (addr & ~plb1_acr_wrp_mask) ; + // mtdcr(plb1_acr, addr); /* Sequoia */ + mtdcr(plb1_acr, 0); // PATCH HAB: WRITE PIPELINING OFF + + return 1; +} +#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */ + +/************************************************************************* + * pci_target_init + * + * The bootstrap configuration provides default settings for the pci + * inbound map (PIM). But the bootstrap config choices are limited and + * may not be sufficient for a given board. + * + ************************************************************************/ +#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) +void pci_target_init(struct pci_controller *hose) +{ + /*-------------------------------------------------------------+ + * Set up Direct MMIO registers + *-------------------------------------------------------------*/ + /*-------------------------------------------------------------+ + | PowerPC440EPX PCI Master configuration. + | Map one 1Gig range of PLB/processor addresses to PCI memory space. + | PLB address 0xA0000000-0xDFFFFFFF ==> PCI address + | 0xA0000000-0xDFFFFFFF + | Use byte reversed out routines to handle endianess. + | Make this region non-prefetchable. + +-------------------------------------------------------------*/ + /* PMM0 Mask/Attribute - disabled b4 setting */ + out32r(PCIX0_PMM0MA, 0x00000000); + out32r(PCIX0_PMM0LA, CFG_PCI_MEMBASE); /* PMM0 Local Address */ + /* PMM0 PCI Low Address */ + out32r(PCIX0_PMM0PCILA, CFG_PCI_MEMBASE); + out32r(PCIX0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */ + /* 512M + No prefetching, and enable region */ + out32r(PCIX0_PMM0MA, 0xE0000001); + + /* PMM0 Mask/Attribute - disabled b4 setting */ + out32r(PCIX0_PMM1MA, 0x00000000); + out32r(PCIX0_PMM1LA, CFG_PCI_MEMBASE2); /* PMM0 Local Address */ + /* PMM0 PCI Low Address */ + out32r(PCIX0_PMM1PCILA, CFG_PCI_MEMBASE2); + out32r(PCIX0_PMM1PCIHA, 0x00000000); /* PMM0 PCI High Address */ + /* 512M + No prefetching, and enable region */ + out32r(PCIX0_PMM1MA, 0xE0000001); + + out32r(PCIX0_PTM1MS, 0x00000001); /* Memory Size/Attribute */ + out32r(PCIX0_PTM1LA, 0); /* Local Addr. Reg */ + out32r(PCIX0_PTM2MS, 0); /* Memory Size/Attribute */ + out32r(PCIX0_PTM2LA, 0); /* Local Addr. Reg */ + + /*------------------------------------------------------------------+ + * Set up Configuration registers + *------------------------------------------------------------------*/ + + /* Program the board's subsystem id/vendor id */ + pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID, + CFG_PCI_SUBSYS_VENDORID); + pci_write_config_word(0, PCI_SUBSYSTEM_ID, CFG_PCI_SUBSYS_ID); + + /* Configure command register as bus master */ + pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER); + + /* 240nS PCI clock */ + pci_write_config_word(0, PCI_LATENCY_TIMER, 1); + + /* No error reporting */ + pci_write_config_word(0, PCI_ERREN, 0); + + pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101); + +} +#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */ + +/************************************************************************* + * pci_master_init + * + ************************************************************************/ +#if defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) +void pci_master_init(struct pci_controller *hose) +{ + unsigned short temp_short; + + /*---------------------------------------------------------------+ + | Write the PowerPC440 EP PCI Configuration regs. + | Enable PowerPC440 EP to be a master on the PCI bus (PMM). + | Enable PowerPC440 EP to act as a PCI memory target (PTM). + +--------------------------------------------------------------*/ + pci_read_config_word(0, PCI_COMMAND, &temp_short); + pci_write_config_word(0, PCI_COMMAND, + temp_short | PCI_COMMAND_MASTER | + PCI_COMMAND_MEMORY); +} +#endif +/* defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) */ + +/************************************************************************* + * is_pci_host + * + * This routine is called to determine if a pci scan should be + * performed. With various hardware environments (especially cPCI and + * PPMC) it's insufficient to depend on the state of the arbiter enable + * bit in the strap register, or generic host/adapter assumptions. + * + * Rather than hard-code a bad assumption in the general 440 code, the + * 440 pci code requires the board to decide at runtime. + * + * Return 0 for adapter mode, non-zero for host (monarch) mode. + * + * + ************************************************************************/ +#if defined(CONFIG_PCI) +int is_pci_host(struct pci_controller *hose) +{ + return 1; +} +#endif /* defined(CONFIG_PCI) */ + diff --git a/board/netstal/hcu5/init.S b/board/netstal/hcu5/init.S new file mode 100644 index 000000000..6da5f22ce --- /dev/null +++ b/board/netstal/hcu5/init.S @@ -0,0 +1,81 @@ +/* + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +/************************************************************************** + * TLB TABLE + * + * This table is used by the cpu boot code to setup the initial tlb + * entries. Rather than make broad assumptions in the cpu source tree, + * this table lets each board set things up however they like. + * + * Pointer to the table is returned in r1 + * + *************************************************************************/ + .section .bootpg,"ax" + .globl tlbtab + +tlbtab: + tlbtab_start + + /* vxWorks needs this entry for the Machine Check interrupt, */ + /* tlbentry( 0x40000000, SZ_256M, 0, 1, AC_R|AC_W|AC_X|SA_G|SA_I ) */ + + /* + * BOOT_CS (FLASH) must be second. Before relocation SA_I can be off to use the + * speed up boot process. It is patched after relocation to enable SA_I + */ + tlbentry( CFG_BOOT_BASE_ADDR, SZ_1M, CFG_BOOT_BASE_ADDR, 1, AC_R|AC_W|AC_X|SA_G ) + + /* TLB-entry for PCI Memory */ + tlbentry( CFG_PCI_MEMBASE, SZ_256M, CFG_PCI_MEMBASE, 1, AC_R|AC_W|SA_G|SA_I ) + tlbentry( CFG_PCI_MEMBASE1, SZ_256M, CFG_PCI_MEMBASE1, 1, AC_R|AC_W|SA_G|SA_I ) + tlbentry( CFG_PCI_MEMBASE2, SZ_256M, CFG_PCI_MEMBASE2, 1, AC_R|AC_W|SA_G|SA_I ) + tlbentry( CFG_PCI_MEMBASE3, SZ_256M, CFG_PCI_MEMBASE3, 1, AC_R|AC_W|SA_G|SA_I ) + + /* TLB-entry for EBC (CFG_CPLD) */ + // tlbentry( CFG_CPLD, SZ_1K, CFG_CPLD, 1, AC_R|AC_W|AC_X|SA_G|SA_I ) + /* CAN */ + tlbentry( CFG_CS_1, SZ_16M, CFG_CS_1, 1, AC_R|AC_W|AC_X|SA_G|SA_I ) + /* IMC + CPLD */ + tlbentry( CFG_CS_2, SZ_16M, CFG_CS_2, 1, AC_R|AC_W|AC_X|SA_G|SA_I ) + tlbentry( CFG_CS_2 + 0x1000000, SZ_16M, CFG_CS_2 + 0x1000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I ) + /* IMC-Fast */ + tlbentry( CFG_CS_3, SZ_16M, CFG_CS_3, 1, AC_R|AC_W|AC_X|SA_G|SA_I ) + tlbentry( CFG_CS_3 + 0x1000000, SZ_16M, CFG_CS_3 + 0x1000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I ) + + /* TLB-entry for Internal Registers & OCM */ + tlbentry( CFG_PCI_BASE, SZ_16M, 0xe0000000, 0, AC_R|AC_W|AC_X|SA_I ) + + /*TLB-entry PCI registers*/ + tlbentry( 0xEEC00000, SZ_1K, 0xEEC00000, 1, AC_R|AC_W|AC_X|SA_G|SA_I ) + + /* TLB-entry for peripherals */ + tlbentry( 0xEF000000, SZ_16M, 0xEF000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I) + + /* TLB for SDRAM will be added by initdram (sdram.c) */ + + tlbtab_end + + diff --git a/board/netstal/hcu5/sdram.c b/board/netstal/hcu5/sdram.c new file mode 100644 index 000000000..f7d6865a3 --- /dev/null +++ b/board/netstal/hcu5/sdram.c @@ -0,0 +1,299 @@ +/* + * (C) Copyright 2007 + * Niklaus Giger (Niklaus.Giger@netstal.com) + * (C) Copyright 2006 + * Sylvie Gohl, AMCC/IBM, gohl.sylvie@fr.ibm.com + * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com + * Thierry Roman, AMCC/IBM, thierry_roman@fr.ibm.com + * Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com + * Robert Snyder, AMCC/IBM, rob.snyder@fr.ibm.com + * + * (C) Copyright 2006 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* define DEBUG for debug output */ +#undef DEBUG + +#include +#include +#include +#include +#include + +void sysLedSet(u32 value); +void dcbz_area(u32 start_address, u32 num_bytes); +void dflush(void); + +#define DDR_DCR_BASE 0x10 +#define ddrcfga (DDR_DCR_BASE+0x0) /* DDR configuration address reg */ +#define ddrcfgd (DDR_DCR_BASE+0x1) /* DDR configuration data reg */ + +#define DDR0_01_INT_MASK_MASK 0x000000FF +#define DDR0_00_INT_ACK_ALL 0x7F000000 +#define DDR0_01_INT_MASK_ALL_ON 0x000000FF +#define DDR0_01_INT_MASK_ALL_OFF 0x00000000 + +#define DDR0_17_DLLLOCKREG_MASK 0x00010000 /* Read only */ +#define DDR0_17_DLLLOCKREG_UNLOCKED 0x00000000 +#define DDR0_17_DLLLOCKREG_LOCKED 0x00010000 + +#define DDR0_22 0x16 +/* ECC */ +#define DDR0_22_CTRL_RAW_MASK 0x03000000 +#define DDR0_22_CTRL_RAW_ECC_DISABLE 0x00000000 /* ECC not enabled */ +#define DDR0_22_CTRL_RAW_ECC_CHECK_ONLY 0x01000000 /* ECC no correction */ +#define DDR0_22_CTRL_RAW_NO_ECC_RAM 0x02000000 /* Not a ECC RAM*/ +#define DDR0_22_CTRL_RAW_ECC_ENABLE 0x03000000 /* ECC correcting on */ +#define DDR0_03_CASLAT_DECODE(n) ((((unsigned long)(n))>>16)&0x7) + +#ifdef CFG_ENABLE_SDRAM_CACHE +#define MY_TLB_WORD2_I_ENABLE 0 /* enable caching on DDR2 */ +#else +#define MY_TLB_WORD2_I_ENABLE TLB_WORD2_I_ENABLE /* disable caching on DDR2 */ +#endif + +void program_tlb(u32 phys_addr, u32 virt_addr, u32 size, u32 tlb_word2_i_value); + +#ifdef CONFIG_ADD_RAM_INFO +void board_add_ram_info(int use_default) +{ + PPC440_SYS_INFO board_cfg; + u32 val; + mfsdram(DDR0_22, val); + val &= DDR0_22_CTRL_RAW_MASK; + switch (val) { + case DDR0_22_CTRL_RAW_ECC_DISABLE: + puts(" (ECC disabled"); + break; + case DDR0_22_CTRL_RAW_ECC_CHECK_ONLY: + puts(" (ECC check only"); + break; + case DDR0_22_CTRL_RAW_NO_ECC_RAM: + puts(" (no ECC ram"); + break; + case DDR0_22_CTRL_RAW_ECC_ENABLE: + puts(" (ECC enabled"); + break; + } + + get_sys_info(&board_cfg); + printf(", %d MHz", (board_cfg.freqPLB * 2) / 1000000); + + mfsdram(DDR0_03, val); + val = DDR0_03_CASLAT_DECODE(val); + printf(", CL%d)", val); +} +#endif + +/*-------------------------------------------------------------------- + * wait_for_dlllock. + *--------------------------------------------------------------------*/ +static int wait_for_dlllock(void) +{ + unsigned long val; + int wait = 0; + + /* -----------------------------------------------------------+ + * Wait for the DCC master delay line to finish calibration + * ----------------------------------------------------------*/ + mtdcr(ddrcfga, DDR0_17); + val = DDR0_17_DLLLOCKREG_UNLOCKED; + + while (wait != 0xffff) { + val = mfdcr(ddrcfgd); + if ((val & DDR0_17_DLLLOCKREG_MASK) == + DDR0_17_DLLLOCKREG_LOCKED) + /* dlllockreg bit on */ + return 0; + else + wait++; + } + debug("0x%04x: DDR0_17 Value (dlllockreg bit): 0x%08x\n", wait, val); + debug("Waiting for dlllockreg bit to raise\n"); + + return -1; +} + +/*********************************************************************** + * + * sdram_panic -- Panic if we cannot configure the sdram correctly + * + ************************************************************************/ +void sdram_panic(const char *reason) +{ + printf("\n%s: reason %s", __FUNCTION__, reason); + sysLedSet(0xff); + while (1) { + } + /* Never return */ +} + +#ifdef CONFIG_DDR_ECC +static void blank_string(int size) +{ + int i; + + for (i=0; i> ! */ + mtsdram(DDR0_00, 0x0000190A); + mtsdram(DDR0_01, 0x01000000); + mtsdram(DDR0_03, 0x02030602); + mtsdram(DDR0_04, 0x0A020200); + mtsdram(DDR0_05, 0x02020307); + switch (*hwVersReg & HCU_HW_SDRAM_CONFIG_MASK) { + case 0: + dram_size = 128 * 1024 * 1024 ; + mtsdram(DDR0_06, 0x0102C80D); // 128MB RAM + mtsdram(DDR0_11, 0x000FC800); // 128MB RAM + mtsdram(DDR0_43, 0x030A0300); // 128MB RAM + break; + case 1: + dram_size = 256 * 1024 * 1024 ; + mtsdram(DDR0_06, 0x0102C812); // 256MB RAM + mtsdram(DDR0_11, 0x0014C800); // 256MB RAM + mtsdram(DDR0_43, 0x030A0200); // 256MB RAM + break; + default: + sdram_panic(INVALID_HW_CONFIG); + break; + } + dram_size -= 16 * 1024 * 1024; + mtsdram(DDR0_07, 0x00090100); + // TCPD=200 cycles of clock input is required to lock the DLL. + // CKE must be HIGH the entire time.mtsdram(DDR0_08, 0x02C80001); + mtsdram(DDR0_08, 0x02C80001); + mtsdram(DDR0_09, 0x00011D5F); + mtsdram(DDR0_10, 0x00000100); + mtsdram(DDR0_12, 0x00000003); + mtsdram(DDR0_14, 0x00000000); + mtsdram(DDR0_17, 0x1D000000); + mtsdram(DDR0_18, 0x1D1D1D1D); + mtsdram(DDR0_19, 0x1D1D1D1D); + mtsdram(DDR0_20, 0x0B0B0B0B); + mtsdram(DDR0_21, 0x0B0B0B0B); + #define ECC_RAM 0x03267F0B + #define NO_ECC_RAM 0x00267F0B +#ifdef CONFIG_DDR_ECC + mtsdram(DDR0_22, ECC_RAM); +#else + mtsdram(DDR0_22, NO_ECC_RAM); +#endif + + mtsdram(DDR0_23, 0x00000000); + mtsdram(DDR0_24, 0x01020001); + mtsdram(DDR0_26, 0x2D930517); + mtsdram(DDR0_27, 0x00008236); + mtsdram(DDR0_28, 0x00000000); + mtsdram(DDR0_31, 0x00000000); + mtsdram(DDR0_42, 0x01000006); + mtsdram(DDR0_44, 0x00000003); + mtsdram(DDR0_02, 0x00000001); + wait_for_dlllock(); + mtsdram(DDR0_00, 0x40000000); /* Zero init bit */ + + /* + * Program tlb entries for this size (dynamic) + */ + program_tlb(0, 0, dram_size, MY_TLB_WORD2_I_ENABLE); + + /* + * Setup 2nd TLB with same physical address but different virtual + * address with cache enabled. This is done for fast ECC generation. + */ + program_tlb(0, CFG_DDR_CACHED_ADDR, dram_size, 0); + +#ifdef CONFIG_DDR_ECC + /* + * If ECC is enabled, initialize the parity bits. + */ + program_ecc(CFG_DDR_CACHED_ADDR, dram_size, 0); +#endif + + return (dram_size); +} From 35d22f957a85a22bb3cd1ad084fa5404620d1c42 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Fri, 10 Aug 2007 10:42:25 +0200 Subject: [PATCH 077/259] Coding style cleanup Signed-off-by: Stefan Roese --- MAKEALL | 2 +- Makefile | 8 +- board/netstal/common/nm_bsp.c | 1 - board/netstal/hcu4/config.mk | 1 - board/netstal/hcu4/hcu4.c | 80 ++++++++------- board/netstal/hcu5/config.mk | 1 - board/netstal/hcu5/hcu5.c | 177 +++++++++++++++++----------------- board/netstal/hcu5/init.S | 4 +- board/netstal/hcu5/sdram.c | 23 +++-- include/configs/hcu4.h | 4 +- include/configs/hcu5.h | 4 - 11 files changed, 153 insertions(+), 152 deletions(-) diff --git a/MAKEALL b/MAKEALL index e7067972c..61a4d4570 100755 --- a/MAKEALL +++ b/MAKEALL @@ -91,7 +91,7 @@ LIST_4xx=" \ PPChameleonEVB sbc405 sc3 sequoia \ sequoia_nand taishan VOH405 VOM405 \ W7OLMC W7OLMG walnut WUH405 \ - XPEDITE1K yellowstone yosemite yucca \ + XPEDITE1K yellowstone yosemite yucca \ " ######################################################################### diff --git a/Makefile b/Makefile index 04c2c02dc..8282c71d1 100644 --- a/Makefile +++ b/Makefile @@ -1040,7 +1040,7 @@ ADCIOP_config: unconfig @$(MKCONFIG) $(@:_config=) ppc ppc4xx adciop esd alpr_config: unconfig - @./mkconfig $(@:_config=) ppc ppc4xx alpr prodrive + @$(MKCONFIG) $(@:_config=) ppc ppc4xx alpr prodrive AP1000_config:unconfig @$(MKCONFIG) $(@:_config=) ppc ppc4xx ap1000 amirix @@ -1135,10 +1135,10 @@ G2000_config: unconfig @$(MKCONFIG) $(@:_config=) ppc ppc4xx g2000 hcu4_config: unconfig - @./mkconfig $(@:_config=) ppc ppc4xx hcu4 netstal + @$(MKCONFIG) $(@:_config=) ppc ppc4xx hcu4 netstal hcu5_config: unconfig - @./mkconfig $(@:_config=) ppc ppc4xx hcu5 netstal + @$(MKCONFIG) $(@:_config=) ppc ppc4xx hcu5 netstal HH405_config: unconfig @$(MKCONFIG) $(@:_config=) ppc ppc4xx hh405 esd @@ -1258,7 +1258,7 @@ rainier_nand_config: unconfig @echo "CONFIG_NAND_U_BOOT = y" >> $(obj)include/config.mk sc3_config:unconfig - @./mkconfig $(@:_config=) ppc ppc4xx sc3 + @$(MKCONFIG) $(@:_config=) ppc ppc4xx sc3 taishan_config: unconfig @$(MKCONFIG) $(@:_config=) ppc ppc4xx taishan amcc diff --git a/board/netstal/common/nm_bsp.c b/board/netstal/common/nm_bsp.c index ee1b684ab..1e06780c0 100644 --- a/board/netstal/common/nm_bsp.c +++ b/board/netstal/common/nm_bsp.c @@ -39,4 +39,3 @@ U_BOOT_CMD( "Help for Netstal Maschinen BSP specific command.\n" ); #endif - diff --git a/board/netstal/hcu4/config.mk b/board/netstal/hcu4/config.mk index f5a4ce474..376609ab0 100644 --- a/board/netstal/hcu4/config.mk +++ b/board/netstal/hcu4/config.mk @@ -26,4 +26,3 @@ TEXT_BASE = 0xFFFa0000 ifeq ($(debug),1) PLATFORM_CPPFLAGS += -DDEBUG -g endif - diff --git a/board/netstal/hcu4/hcu4.c b/board/netstal/hcu4/hcu4.c index deb7d2da9..252aaa76b 100644 --- a/board/netstal/hcu4/hcu4.c +++ b/board/netstal/hcu4/hcu4.c @@ -27,10 +27,30 @@ DECLARE_GLOBAL_DATA_PTR; +#define HCU_MACH_VERSIONS_REGISTER (0x7C000000 + 0xF00000) + +#define mtsdram(reg, data) { mtdcr(memcfga,reg);mtdcr(memcfgd,data); } +#define mfsdram(value, reg) { mtdcr(memcfga,reg); value = mfdcr(memcfgd); } + +#define SDRAM_LEN 32*1024*1024 /* 32 MB -RAM */ + +#define DO_UGLY_SDRAM_WORKAROUND + +enum { + /* HW_GENERATION_HCU wird nicht mehr unterstuetzt */ + HW_GENERATION_HCU2 = 0x10, + HW_GENERATION_HCU3 = 0x10, + HW_GENERATION_HCU4 = 0x20, + HW_GENERATION_MCU = 0x08, + HW_GENERATION_MCU20 = 0x0a, + HW_GENERATION_MCU25 = 0x09, +}; + void sysLedSet(u32 value); -long int spd_sdram(int(read_spd)(uint addr)) +long int spd_sdram(int(read_spd)(uint addr)); + #ifdef CONFIG_SPD_EEPROM - #define DEBUG +#define DEBUG #endif #if defined(DEBUG) @@ -86,26 +106,15 @@ int board_pre_init (void) { return board_early_init_f (); } - #endif -enum { - /* HW_GENERATION_HCU wird nicht mehr unterstuetzt */ - HW_GENERATION_HCU2 = 0x10, - HW_GENERATION_HCU3 = 0x10, - HW_GENERATION_HCU4 = 0x20, - HW_GENERATION_MCU = 0x08, - HW_GENERATION_MCU20 = 0x0a, - HW_GENERATION_MCU25 = 0x09, -}; - int checkboard (void) { -#define HCU_MACH_VERSIONS_REGISTER ( 0x7C000000 + 0xF00000 ) - unsigned j; - uint16_t *boardVersReg = (uint16_t *) HCU_MACH_VERSIONS_REGISTER; - uint16_t generation = *boardVersReg & 0xf0; - uint16_t index = *boardVersReg & 0x0f; + unsigned int j; + u16 *boardVersReg = (u16 *) HCU_MACH_VERSIONS_REGISTER; + u16 generation = *boardVersReg & 0xf0; + u16 index = *boardVersReg & 0x0f; + /* Force /RTS to active. The board it not wired quite correctly to use cts/rtc flow control, so just force the /RST active and forget about it. */ @@ -117,24 +126,26 @@ int checkboard (void) printf ("HCU4: index %d\n\n", index); /* GPIO here noch nicht richtig initialisert !!! */ sysLedSet(0); - for (j=0; j < 7;j++) { + for (j = 0; j < 7; j++) { sysLedSet(1 << j); - udelay(50*1000); + udelay(50 * 1000); } + return 0; } u32 sysLedGet(void) { - return( ~( (*(u32 *)GPIO0_OR)) >> 23) & 0xff; + return (~((*(u32 *)GPIO0_OR)) >> 23) & 0xff; } void sysLedSet(u32 value /* value to place in LEDs */) { u32 tmp = ~value; u32 *ledReg; - tmp = (tmp << 23) | 0x7FFFFF; - ledReg = (u32 *)GPIO0_OR; + + tmp = (tmp << 23) | 0x7FFFFF; + ledReg = (u32 *)GPIO0_OR; *ledReg = tmp; } @@ -147,13 +158,11 @@ void sdram_init(void) return; } -#define mtsdram(reg, data) { mtdcr(memcfga,reg);mtdcr(memcfgd,data); } -#define mfsdram(value, reg) { mtdcr(memcfga,reg); value = mfdcr(memcfgd); } - #if defined(DEBUG) void show_sdram_registers(void) { u32 value; + printf ("SDRAM Controller Registers --\n"); mfsdram(value, mem_mcopt1); printf (" SDRAM0_CFG : 0x%08x\n", value); @@ -170,8 +179,6 @@ void show_sdram_registers(void) } #endif -#define SDRAM_LEN 32*1024*1024 /* 32 MB -RAM */ - /* * this is even after checkboard. It returns the size of the SDRAM * that we have installed. This function is called by board_init_f @@ -244,9 +251,10 @@ long int fixed_hcu4_sdram (int board_type) static u32 getSerialNr(void) { u32 *serial = (u32 *)CFG_FLASH_BASE; - if (*serial == 0xffffffff) { + + if (*serial == 0xffffffff) return get_ticks(); - } + return *serial; } @@ -260,12 +268,14 @@ int misc_init_r(void) char *s = getenv("ethaddr"); char *e; int i; - u32 serial = getSerialNr(); + u32 serial = getSerialNr(); + for (i = 0; i < 6; ++i) { gd->bd->bi_enetaddr[i] = s ? simple_strtoul (s, &e, 16) : 0; if (s) s = (*e) ? e + 1 : e; } + if (gd->bd->bi_enetaddr[3] == 0 && gd->bd->bi_enetaddr[4] == 0 && gd->bd->bi_enetaddr[5] == 0) { @@ -288,13 +298,14 @@ int misc_init_r(void) return 0; } -#define DO_UGLY_SDRAM_WORKAROUND #ifdef DO_UGLY_SDRAM_WORKAROUND - #include "i2c.h" +#include "i2c.h" + void set_spd_default_value(unsigned int spd_addr,uchar def_val) { uchar value; int res = i2c_read(SPD_EEPROM_ADDRESS, spd_addr, 1, &value, 1) ; + if (res == 0 && value == 0xff) { res = i2c_write(SPD_EEPROM_ADDRESS, spd_addr, 1, &def_val, 1) ; @@ -387,7 +398,6 @@ long int initdram(int board_type) bcu4_testdram(dram_size); printf("%s %d MB of SDRAM\n", __FUNCTION__, dram_size/(1024*1024)); #endif + return dram_size; } - - diff --git a/board/netstal/hcu5/config.mk b/board/netstal/hcu5/config.mk index 58ec2af31..cfd574412 100644 --- a/board/netstal/hcu5/config.mk +++ b/board/netstal/hcu5/config.mk @@ -28,4 +28,3 @@ PLATFORM_CPPFLAGS += -DCONFIG_440=1 ifeq ($(debug),1) PLATFORM_CPPFLAGS += -DDEBUG -g endif - diff --git a/board/netstal/hcu5/hcu5.c b/board/netstal/hcu5/hcu5.c index 59107b920..23df0814f 100644 --- a/board/netstal/hcu5/hcu5.c +++ b/board/netstal/hcu5/hcu5.c @@ -29,12 +29,34 @@ void sysLedSet(u32 value); extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; -#define mtcpr0(reg, data) do { mtdcr(CPR0_CFGADDR,reg); \ - mtdcr(CPR0_CFGDATA,data); } while (0) -#define mfcpr0(reg, data) do { mtdcr(CPR0_CFGADDR,reg); \ - data = mfdcr(CPR0_CFGDATA); } while (0) +#undef BOOTSTRAP_OPTION_A_ACTIVE + +#define SDR0_CP440 0x0180 + +#define SYSTEM_RESET 0x30000000 +#define CHIP_RESET 0x20000000 + +#define SDR0_ECID0 0x0080 +#define SDR0_ECID1 0x0081 +#define SDR0_ECID2 0x0082 +#define SDR0_ECID3 0x0083 + +#define SYS_IO_ADDRESS 0xcce00000 + +#define DEFAULT_ETH_ADDR "ethaddr" +/* ethaddr for first or etha1ddr for second ethernet */ + +enum { + /* HW_GENERATION_HCU1 is no longer supported */ + HW_GENERATION_HCU2 = 0x10, + HW_GENERATION_HCU3 = 0x10, + HW_GENERATION_HCU4 = 0x20, + HW_GENERATION_HCU5 = 0x30, + HW_GENERATION_MCU = 0x08, + HW_GENERATION_MCU20 = 0x0a, + HW_GENERATION_MCU25 = 0x09, +}; -#define SDR0_CP440 0x0180 /* * This function is run very early, out of flash, and before devices are @@ -50,7 +72,6 @@ int board_early_init_f(void) { u32 reg; -#undef BOOTSTRAP_OPTION_A_ACTIVE #ifdef BOOTSTRAP_OPTION_A_ACTIVE /* Booting with Bootstrap Option A * First boot, with CPR0_ICFG_RLI_MASK == 0 @@ -64,27 +85,26 @@ int board_early_init_f(void) u32 cpr0icfg; u32 dbcr; - mfcpr0(CPR0_ICFG, cpr0icfg); - if ( ! (cpr0icfg & CPR0_ICFG_RLI_MASK ) ) { - mtcpr0(CPR0_MALD, 0x02000000); - mtcpr0(CPR0_OPBD, 0x02000000); - mtcpr0(CPR0_PERD, 0x05000000); /* 1:5 */ - mtcpr0(CPR0_PLLC, 0x40000238); - mtcpr0(CPR0_PLLD, 0x01010414); - mtcpr0(CPR0_PRIMAD, 0x01000000); - mtcpr0(CPR0_PRIMBD, 0x01000000); - mtcpr0(CPR0_SPCID, 0x03000000); - mtsdr(SDR0_PFC0, 0x00003E00); /* [CTE] = 0 */ - mtsdr(SDR0_CP440, 0x0EAAEA02); /* [Nto1] = 1*/ - mtcpr0(CPR0_ICFG, cpr0icfg | CPR0_ICFG_RLI_MASK); + + mfcpr(CPR0_ICFG, cpr0icfg); + if (!(cpr0icfg & CPR0_ICFG_RLI_MASK)) { + mtcpr(CPR0_MALD, 0x02000000); + mtcpr(CPR0_OPBD, 0x02000000); + mtcpr(CPR0_PERD, 0x05000000); /* 1:5 */ + mtcpr(CPR0_PLLC, 0x40000238); + mtcpr(CPR0_PLLD, 0x01010414); + mtcpr(CPR0_PRIMAD, 0x01000000); + mtcpr(CPR0_PRIMBD, 0x01000000); + mtcpr(CPR0_SPCID, 0x03000000); + mtsdr(SDR0_PFC0, 0x00003E00); /* [CTE] = 0 */ + mtsdr(SDR0_CP440, 0x0EAAEA02); /* [Nto1] = 1*/ + mtcpr(CPR0_ICFG, cpr0icfg | CPR0_ICFG_RLI_MASK); /* * Initiate system reset in debug control register DBCR */ dbcr = mfspr(dbcr0); - #define SYSTEM_RESET 0x30000000 - #define CHIP_RESET 0x20000000 - mtspr(dbcr0, dbcr | CHIP_RESET ); + mtspr(dbcr0, dbcr | CHIP_RESET); } mtsdr(SDR0_CP440, 0x0EAAEA02); /* [Nto1] = 1*/ #endif @@ -162,60 +182,42 @@ int board_early_init_f(void) return 0; } -#ifdef CONFIG_BOARD_PRE_INIT -int board_pre_init (void) +int board_pre_init(void) { - return board_early_init_f (); + return board_early_init_f(); } -#endif - -enum { - /* HW_GENERATION_HCU1 is no longer supported */ - HW_GENERATION_HCU2 = 0x10, - HW_GENERATION_HCU3 = 0x10, - HW_GENERATION_HCU4 = 0x20, - HW_GENERATION_HCU5 = 0x30, - HW_GENERATION_MCU = 0x08, - HW_GENERATION_MCU20 = 0x0a, - HW_GENERATION_MCU25 = 0x09, -}; - -int checkboard (void) +int checkboard(void) { -#define SDR0_ECID0 0x0080 -#define SDR0_ECID1 0x0081 -#define SDR0_ECID2 0x0082 -#define SDR0_ECID3 0x0083 - unsigned j; - uint16_t *hwVersReg = (uint16_t *) HCU_HW_VERSION_REGISTER; - uint16_t *boardVersReg = (uint16_t *) HCU_CPLD_VERSION_REGISTER; - uint16_t generation = *boardVersReg & 0xf0; - uint16_t index = *boardVersReg & 0x0f; - ulong ecid0, ecid1, ecid2, ecid3; - printf ("Netstal Maschinen AG: "); + unsigned int j; + u16 *hwVersReg = (u16 *) HCU_HW_VERSION_REGISTER; + u16 *boardVersReg = (u16 *) HCU_CPLD_VERSION_REGISTER; + u16 generation = *boardVersReg & 0xf0; + u16 index = *boardVersReg & 0x0f; + u32 ecid0, ecid1, ecid2, ecid3; + + printf("Netstal Maschinen AG: "); if (generation == HW_GENERATION_HCU3) - printf ("HCU3: index %d", index); + printf("HCU3: index %d", index); else if (generation == HW_GENERATION_HCU4) - printf ("HCU4: index %d", index); + printf("HCU4: index %d", index); else if (generation == HW_GENERATION_HCU5) - printf ("HCU5: index %d", index); - printf (" HW 0x%02x\n", *hwVersReg & 0xff); + printf("HCU5: index %d", index); + printf(" HW 0x%02x\n", *hwVersReg & 0xff); mfsdr(SDR0_ECID0, ecid0); mfsdr(SDR0_ECID1, ecid1); mfsdr(SDR0_ECID2, ecid2); mfsdr(SDR0_ECID3, ecid3); - printf("Chip ID 0x%x 0x%x 0x%x 0x%x\n", ecid0, ecid1, ecid2, ecid3); - for (j=0; j < 6;j++) { + printf("Chip ID 0x%x 0x%x 0x%x 0x%x\n", ecid0, ecid1, ecid2, ecid3); + for (j = 0;j < 6; j++) { sysLedSet(1 << j); - udelay(200*1000); + udelay(200 * 1000); } + return 0; } -#define SYS_IO_ADDRESS 0xcce00000 - u32 sysLedGet(void) { return in16(SYS_IO_ADDRESS) & 0x3f; @@ -232,9 +234,10 @@ void sysLedSet(u32 value /* value to place in LEDs */) static u32 getSerialNr(void) { u32 *serial = (u32 *)CFG_FLASH_BASE; - if (*serial == 0xffffffff) { + + if (*serial == 0xffffffff) return get_ticks(); - } + return *serial; } @@ -242,45 +245,44 @@ static u32 getSerialNr(void) /*---------------------------------------------------------------------------+ * misc_init_r. *---------------------------------------------------------------------------*/ - -#define DEFAULT_ETH_ADDR "ethaddr" -/* ethaddr for first or etha1ddr for second ethernet */ - int misc_init_r(void) { char *s = getenv(DEFAULT_ETH_ADDR); char *e; int i; - u32 serial = getSerialNr(); + u32 serial = getSerialNr(); unsigned long usb2d0cr = 0; unsigned long usb2phy0cr, usb2h0cr = 0; unsigned long sdr0_pfc1; for (i = 0; i < 6; ++i) { - gd->bd->bi_enetaddr[i] = s ? simple_strtoul (s, &e, 16) : 0; + gd->bd->bi_enetaddr[i] = s ? simple_strtoul(s, &e, 16) : 0; if (s) s = (*e) ? e + 1 : e; } + if (gd->bd->bi_enetaddr[3] == 0 && gd->bd->bi_enetaddr[4] == 0 && gd->bd->bi_enetaddr[5] == 0) { char ethaddr[22]; + /* Must be in sync with CONFIG_ETHADDR */ gd->bd->bi_enetaddr[0] = 0x00; gd->bd->bi_enetaddr[1] = 0x60; gd->bd->bi_enetaddr[2] = 0x13; - gd->bd->bi_enetaddr[3] = (serial >> 16) & 0xff; - gd->bd->bi_enetaddr[4] = (serial >> 8) & 0xff; + gd->bd->bi_enetaddr[3] = (serial >> 16) & 0xff; + gd->bd->bi_enetaddr[4] = (serial >> 8) & 0xff; /* byte[5].bit 0 must be zero */ - gd->bd->bi_enetaddr[5] = (serial >> 0) & 0xfe; - sprintf (ethaddr, "%02X:%02X:%02X:%02X:%02X:%02X\0", - gd->bd->bi_enetaddr[0], gd->bd->bi_enetaddr[1], - gd->bd->bi_enetaddr[2], gd->bd->bi_enetaddr[3], - gd->bd->bi_enetaddr[4], gd->bd->bi_enetaddr[5]) ; + gd->bd->bi_enetaddr[5] = (serial >> 0) & 0xfe; + sprintf(ethaddr, "%02X:%02X:%02X:%02X:%02X:%02X\0", + gd->bd->bi_enetaddr[0], gd->bd->bi_enetaddr[1], + gd->bd->bi_enetaddr[2], gd->bd->bi_enetaddr[3], + gd->bd->bi_enetaddr[4], gd->bd->bi_enetaddr[5]) ; printf("%s: Setting eth %s serial 0x%x\n", __FUNCTION__, ethaddr, serial); - setenv (DEFAULT_ETH_ADDR, ethaddr); + setenv(DEFAULT_ETH_ADDR, ethaddr); } + #ifdef CFG_ENV_IS_IN_FLASH /* Monitor protection ON by default */ (void)flash_protect(FLAG_PROTECT_SET, @@ -334,9 +336,9 @@ int misc_init_r(void) mtsdr(SDR0_USB2H0CR, usb2h0cr); /*clear resets*/ - udelay (1000); + udelay(1000); mtsdr(SDR0_SRST1, 0x00000000); - udelay (1000); + udelay(1000); mtsdr(SDR0_SRST0, 0x00000000); printf("USB: Host(int phy) Device(ext phy)\n"); @@ -356,7 +358,7 @@ int misc_init_r(void) * certain pre-initialization actions. * ************************************************************************/ -#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) +#if defined(CONFIG_PCI) int pci_pre_init(struct pci_controller *hose) { unsigned long addr; @@ -374,7 +376,7 @@ int pci_pre_init(struct pci_controller *hose) mfsdr(sdr_amp1, addr); mtsdr(sdr_amp1, (addr & 0x000000FF) | 0x0000FF00); addr = mfdcr(plb3_acr); - // mtdcr(plb3_acr, addr & ~plb1_acr_wrp_mask); /* ngngng */ + /* mtdcr(plb3_acr, addr & ~plb1_acr_wrp_mask); */ /* ngngng */ mtdcr(plb3_acr, addr | 0x80000000); /* Sequoia */ /*-------------------------------------------------------------------+ @@ -383,7 +385,7 @@ int pci_pre_init(struct pci_controller *hose) mfsdr(sdr_amp0, addr); mtsdr(sdr_amp0, (addr & 0x000000FF) | 0x0000FF00); addr = mfdcr(plb4_acr) | 0xa0000000; /* Was 0x8---- */ -// mtdcr(plb4_acr, addr & ~plb1_acr_wrp_mask); /* ngngng */ + /* mtdcr(plb4_acr, addr & ~plb1_acr_wrp_mask); */ /* ngngng */ mtdcr(plb4_acr, addr); /* Sequoia */ /*-------------------------------------------------------------------+ @@ -393,24 +395,23 @@ int pci_pre_init(struct pci_controller *hose) addr = (mfdcr(plb0_acr) & ~plb0_acr_ppm_mask) | plb0_acr_ppm_fair; addr = (addr & ~plb0_acr_hbu_mask) | plb0_acr_hbu_enabled; addr = (addr & ~plb0_acr_rdp_mask) | plb0_acr_rdp_4deep; -// addr = (addr & ~plb0_acr_wrp_mask) ; /* ngngng */ + /* addr = (addr & ~plb0_acr_wrp_mask); */ /* ngngng */ addr = (addr & ~plb0_acr_wrp_mask) | plb0_acr_wrp_2deep; /* Sequoia */ - // mtdcr(plb0_acr, addr); /* Sequoia */ - mtdcr(plb0_acr, 0); // PATCH HAB: WRITE PIPELINING OFF - + /* mtdcr(plb0_acr, addr); */ /* Sequoia */ + mtdcr(plb0_acr, 0); /* PATCH HAB: WRITE PIPELINING OFF */ /* Segment1 */ addr = (mfdcr(plb1_acr) & ~plb1_acr_ppm_mask) | plb1_acr_ppm_fair; addr = (addr & ~plb1_acr_hbu_mask) | plb1_acr_hbu_enabled; addr = (addr & ~plb1_acr_rdp_mask) | plb1_acr_rdp_4deep; addr = (addr & ~plb1_acr_wrp_mask) ; - // mtdcr(plb1_acr, addr); /* Sequoia */ - mtdcr(plb1_acr, 0); // PATCH HAB: WRITE PIPELINING OFF + /* mtdcr(plb1_acr, addr); */ /* Sequoia */ + mtdcr(plb1_acr, 0); /* PATCH HAB: WRITE PIPELINING OFF */ return 1; } -#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */ +#endif /* defined(CONFIG_PCI) */ /************************************************************************* * pci_target_init @@ -476,7 +477,6 @@ void pci_target_init(struct pci_controller *hose) pci_write_config_word(0, PCI_ERREN, 0); pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101); - } #endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */ @@ -523,4 +523,3 @@ int is_pci_host(struct pci_controller *hose) return 1; } #endif /* defined(CONFIG_PCI) */ - diff --git a/board/netstal/hcu5/init.S b/board/netstal/hcu5/init.S index 6da5f22ce..5ab6cd24d 100644 --- a/board/netstal/hcu5/init.S +++ b/board/netstal/hcu5/init.S @@ -55,7 +55,7 @@ tlbtab: tlbentry( CFG_PCI_MEMBASE3, SZ_256M, CFG_PCI_MEMBASE3, 1, AC_R|AC_W|SA_G|SA_I ) /* TLB-entry for EBC (CFG_CPLD) */ - // tlbentry( CFG_CPLD, SZ_1K, CFG_CPLD, 1, AC_R|AC_W|AC_X|SA_G|SA_I ) + /* tlbentry( CFG_CPLD, SZ_1K, CFG_CPLD, 1, AC_R|AC_W|AC_X|SA_G|SA_I ) */ /* CAN */ tlbentry( CFG_CS_1, SZ_16M, CFG_CS_1, 1, AC_R|AC_W|AC_X|SA_G|SA_I ) /* IMC + CPLD */ @@ -77,5 +77,3 @@ tlbtab: /* TLB for SDRAM will be added by initdram (sdram.c) */ tlbtab_end - - diff --git a/board/netstal/hcu5/sdram.c b/board/netstal/hcu5/sdram.c index f7d6865a3..40391958d 100644 --- a/board/netstal/hcu5/sdram.c +++ b/board/netstal/hcu5/sdram.c @@ -216,8 +216,9 @@ long int initdram (int board_type) { #define HCU_HW_SDRAM_CONFIG_MASK 0x7 #define INVALID_HW_CONFIG "Invalid HW-Config" - uint16_t *hwVersReg = (uint16_t *) HCU_HW_VERSION_REGISTER; - unsigned int dram_size=0; + u16 *hwVersReg = (u16 *) HCU_HW_VERSION_REGISTER; + unsigned int dram_size = 0; + mtsdram(DDR0_02, 0x00000000); /* Values must be kept in sync with Excel-table <> ! */ @@ -229,15 +230,15 @@ long int initdram (int board_type) switch (*hwVersReg & HCU_HW_SDRAM_CONFIG_MASK) { case 0: dram_size = 128 * 1024 * 1024 ; - mtsdram(DDR0_06, 0x0102C80D); // 128MB RAM - mtsdram(DDR0_11, 0x000FC800); // 128MB RAM - mtsdram(DDR0_43, 0x030A0300); // 128MB RAM + mtsdram(DDR0_06, 0x0102C80D); /* 128MB RAM */ + mtsdram(DDR0_11, 0x000FC800); /* 128MB RAM */ + mtsdram(DDR0_43, 0x030A0300); /* 128MB RAM */ break; case 1: dram_size = 256 * 1024 * 1024 ; - mtsdram(DDR0_06, 0x0102C812); // 256MB RAM - mtsdram(DDR0_11, 0x0014C800); // 256MB RAM - mtsdram(DDR0_43, 0x030A0200); // 256MB RAM + mtsdram(DDR0_06, 0x0102C812); /* 256MB RAM */ + mtsdram(DDR0_11, 0x0014C800); /* 256MB RAM */ + mtsdram(DDR0_43, 0x030A0200); /* 256MB RAM */ break; default: sdram_panic(INVALID_HW_CONFIG); @@ -245,8 +246,10 @@ long int initdram (int board_type) } dram_size -= 16 * 1024 * 1024; mtsdram(DDR0_07, 0x00090100); - // TCPD=200 cycles of clock input is required to lock the DLL. - // CKE must be HIGH the entire time.mtsdram(DDR0_08, 0x02C80001); + /* + * TCPD=200 cycles of clock input is required to lock the DLL. + * CKE must be HIGH the entire time.mtsdram(DDR0_08, 0x02C80001); + */ mtsdram(DDR0_08, 0x02C80001); mtsdram(DDR0_09, 0x00011D5F); mtsdram(DDR0_10, 0x00000100); diff --git a/include/configs/hcu4.h b/include/configs/hcu4.h index 8779db9af..9e45e903d 100644 --- a/include/configs/hcu4.h +++ b/include/configs/hcu4.h @@ -312,8 +312,6 @@ #define CONFIG_PORT_ADDR 0xF0000500 - - /*----------------------------------------------------------------------- * Cache Configuration *----------------------------------------------------------------------*/ @@ -333,7 +331,7 @@ #define CFG_HUSH_PARSER /* use "hush" command parser */ #ifdef CFG_HUSH_PARSER - #define CFG_PROMPT_HUSH_PS2 "> " +#define CFG_PROMPT_HUSH_PS2 "> " #endif #if (CONFIG_COMMANDS & CFG_CMD_KGDB) diff --git a/include/configs/hcu5.h b/include/configs/hcu5.h index 87f6948df..fa6ca3753 100644 --- a/include/configs/hcu5.h +++ b/include/configs/hcu5.h @@ -236,8 +236,6 @@ #define CONFIG_DOS_PARTITION #define CONFIG_ISO_PARTITION -// CFG_CMD_FLASH | - #define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ CFG_CMD_ASKENV | \ CFG_CMD_BSP | \ @@ -301,7 +299,6 @@ #define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE*/ /* Board-specific PCI */ -#define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */ #define CFG_PCI_TARGET_INIT #define CFG_PCI_MASTER_INIT @@ -389,4 +386,3 @@ #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif #endif /* __CONFIG_H */ - From cfc7a7f5bb3273c9951173c788001d45118f141f Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Thu, 2 Aug 2007 14:42:20 -0500 Subject: [PATCH 078/259] cpu/86xx fixes. Remove rev 1 fixes. Always set PICGCR_MODE. Enable machine check and provide board config option to set and handle SoC error interrupts. Include MSSSR0 in error message. Isolate a RAMBOOT bit of code with #ifdef CFG_RAMBOOT. Signed-off-by: Ed Swarthout Signed-off-by: Jon Loeliger --- cpu/mpc86xx/cpu_init.c | 4 +- cpu/mpc86xx/interrupts.c | 51 ++++++++++++---------- cpu/mpc86xx/start.S | 85 ++++++------------------------------ cpu/mpc86xx/traps.c | 8 +++- include/asm-ppc/immap_86xx.h | 16 +++++-- include/asm-ppc/processor.h | 3 +- 6 files changed, 65 insertions(+), 102 deletions(-) diff --git a/cpu/mpc86xx/cpu_init.c b/cpu/mpc86xx/cpu_init.c index 4673d05e7..c8e466669 100644 --- a/cpu/mpc86xx/cpu_init.c +++ b/cpu/mpc86xx/cpu_init.c @@ -104,8 +104,8 @@ void cpu_init_f(void) /* enable the timebase bit in HID0 */ set_hid0(get_hid0() | 0x4000000); - /* enable SYNCBE | ABE bits in HID1 */ - set_hid1(get_hid1() | 0x00000C00); + /* enable EMCP, SYNCBE | ABE bits in HID1 */ + set_hid1(get_hid1() | 0x80000C00); } /* diff --git a/cpu/mpc86xx/interrupts.c b/cpu/mpc86xx/interrupts.c index 08e0675fe..d9f634fda 100644 --- a/cpu/mpc86xx/interrupts.c +++ b/cpu/mpc86xx/interrupts.c @@ -8,7 +8,7 @@ * (C) Copyright 2003 Motorola Inc. (MPC85xx port) * Xianghua Xiao (X.Xiao@motorola.com) * - * (C) Copyright 2004 Freescale Semiconductor. (MPC86xx Port) + * (C) Copyright 2004, 2007 Freescale Semiconductor. (MPC86xx Port) * Jeff Brown * Srikanth Srinivasan (srikanth.srinivasan@freescale.com) * @@ -80,25 +80,10 @@ int interrupt_init(void) { int ret; - /* - * The IRQ0 on Rev 2 is pulled high (low in Rev 1.x) to - * implement PEX10 errata. As INT is active high, it - * will cause core to take 0x500 interrupt. - * - * Due to the PIC's default pass through mode, as soon - * as interrupts are enabled (MSR[EE] = 1), an interrupt - * will be taken and u-boot will hang. This is due to a - * hardware change (per an errata fix) on new revisions - * of the board with Rev 2.x parts. - * - * Setting the PIC to mixed mode prevents the hang. - */ - if ((get_svr() & 0xf0) == 0x20) { - volatile immap_t *immr = (immap_t *)CFG_IMMR; - immr->im_pic.gcr = MPC86xx_PICGCR_RST; - while (immr->im_pic.gcr & MPC86xx_PICGCR_RST); - immr->im_pic.gcr = MPC86xx_PICGCR_MODE; - } + volatile immap_t *immr = (immap_t *)CFG_IMMR; + immr->im_pic.gcr = MPC86xx_PICGCR_RST; + while (immr->im_pic.gcr & MPC86xx_PICGCR_RST); + immr->im_pic.gcr = MPC86xx_PICGCR_MODE; /* call cpu specific function from $(CPU)/interrupts.c */ ret = interrupt_init_cpu(&decrementer_count); @@ -119,6 +104,30 @@ int interrupt_init(void) get_msr(), get_dec()); +#ifdef CONFIG_INTERRUPTS + volatile ccsr_pic_t *pic = &immr->im_pic; + + pic->iivpr1 = 0x810001; /* 50220 enable mcm interrupts */ + debug("iivpr1@%x = %x\n", &pic->iivpr1, pic->iivpr1); + + pic->iivpr2 = 0x810002; /* 50240 enable ddr interrupts */ + debug("iivpr2@%x = %x\n", &pic->iivpr2, pic->iivpr2); + + pic->iivpr3 = 0x810003; /* 50260 enable lbc interrupts */ + debug("iivpr3@%x = %x\n", &pic->iivpr3, pic->iivpr3); + +#if defined(CONFIG_PCI1) || defined(CONFIG_PCIE1) + pic->iivpr8 = 0x810008; /* enable pcie1 interrupts */ + debug("iivpr8@%x = %x\n", &pic->iivpr8, pic->iivpr8); +#endif +#if defined(CONFIG_PCI2) || defined(CONFIG_PCIE2) + pic->iivpr9 = 0x810009; /* enable pcie2 interrupts */ + debug("iivpr9@%x = %x\n", &pic->iivpr9, pic->iivpr9); +#endif + + pic->ctpr = 0; /* 40080 clear current task priority register */ +#endif + return 0; } @@ -158,8 +167,6 @@ void timer_interrupt(struct pt_regs *regs) timestamp++; - ppcDcbf((unsigned long)×tamp); - /* Restore Decrementer Count */ set_dec(decrementer_count); diff --git a/cpu/mpc86xx/start.S b/cpu/mpc86xx/start.S index 412745bda..c83310a33 100644 --- a/cpu/mpc86xx/start.S +++ b/cpu/mpc86xx/start.S @@ -1,5 +1,5 @@ /* - * Copyright 2004 Freescale Semiconductor. + * Copyright 2004, 2007 Freescale Semiconductor. * Srikanth Srinivasan * * See file CREDITS for list of people who contributed to this @@ -44,11 +44,9 @@ #define CONFIG_IDENT_STRING "" #endif -/* We don't want the MMU yet. -*/ -#undef MSR_KERNEL -/* Machine Check and Recoverable Interr. */ -#define MSR_KERNEL ( MSR_ME | MSR_RI ) +/* + * Need MSR_DR | MSR_IR enabled to access I/O (printf) in exceptions + */ /* * Set up GOT: Global Offset Table @@ -195,17 +193,21 @@ boot_warm: bl secondary_cpu_setup #endif +1: +#ifdef CFG_RAMBOOT /* disable everything */ -1: li r0, 0 + li r0, 0 mtspr HID0, r0 sync mtmsr 0 +#endif + bl invalidate_bats sync #ifdef CFG_L2 /* init the L2 cache */ - addis r3, r0, L2_INIT@h + lis r3, L2_INIT@h ori r3, r3, L2_INIT@l mtspr l2cr, r3 /* invalidate the L2 cache */ @@ -241,69 +243,9 @@ in_flash: bl setup_ccsrbar #endif - - /* -- MPC8641 Rev 1.0 MCM Errata fixups -- */ - - /* skip fixups if not Rev 1.0 */ - mfspr r4, SVR - rlwinm r4,r4,0,24,31 - cmpwi r4,0x10 - bne 1f - - lis r3,MCM_ABCR@ha - lwz r4,MCM_ABCR@l(r3) /* ABCR -> r4 */ - - /* set ABCR[A_STRM_CNT] = 0 */ - rlwinm r4,r4,0,0,29 - - /* set ABCR[ARB_POLICY] to 0x1 (round-robin) */ - addi r0,r0,1 - rlwimi r4,r0,12,18,19 - - stw r4,MCM_ABCR@l(r3) /* r4 -> ABCR */ - sync - - /* Set DBCR[ERD_DIS] */ - lis r3,MCM_DBCR@ha - lwz r4,MCM_DBCR@l(r3) - oris r4, r4, 0x4000 - stw r4,MCM_DBCR@l(r3) - sync -1: /* setup the law entries */ bl law_entry sync - - -#if (EMULATOR_RUN == 1) - /* On the emulator we want to adjust these ASAP */ - /* otherwise things are sloooow */ - /* Setup OR0 (LALE FIX)*/ - lis r3, CFG_CCSRBAR@h - ori r3, r3, 0x5004 - li r4, 0x0FF3 - stw r4, 0(r3) - sync - - /* Setup LCRR */ - lis r3, CFG_CCSRBAR@h - ori r3, r3, 0x50D4 - lis r4, 0x8000 - ori r4, r4, 0x0002 - stw r4, 0(r3) - sync -#endif -#if 1 - /* make sure timer enabled in guts register too */ - lis r3, CFG_CCSRBAR@h - oris r3,r3, 0xE - ori r3,r3,0x0070 - lwz r4, 0(r3) - lis r5,0xFFFC - ori r5,r5,0x5FFF - and r4,r4,r5 - stw r4,0(r3) -#endif /* * Cache must be enabled here for stack-in-cache trick. * This means we need to enable the BATS. @@ -346,8 +288,6 @@ in_flash: #ifdef RUN_DIAG - /* Sri: Code to run the diagnostic automatically */ - /* Load PX_AUX register address in r4 */ lis r4, 0xf810 ori r4, r4, 0x6 @@ -392,6 +332,7 @@ diag_done: .globl invalidate_bats invalidate_bats: + li r0, 0 /* invalidate BATs */ mtspr IBAT0U, r0 mtspr IBAT1U, r0 @@ -1040,6 +981,7 @@ trap_init: mfmsr r7 li r8,MSR_IP andc r7,r7,r8 + ori r7,r7,MSR_ME /* Enable Machine Check */ mtmsr r7 mtlr r4 /* restore link register */ @@ -1224,8 +1166,9 @@ secondary_cpu_setup: sync isync - /*SYNCBE|ABE in HID1*/ + /* MCP|SYNCBE|ABE in HID1 */ mfspr r4, HID1 + oris r4, r4, 0x8000 ori r4, r4, 0x0C00 mtspr HID1, r4 sync diff --git a/cpu/mpc86xx/traps.c b/cpu/mpc86xx/traps.c index fab197583..c84bfbf6a 100644 --- a/cpu/mpc86xx/traps.c +++ b/cpu/mpc86xx/traps.c @@ -130,8 +130,11 @@ MachineCheckException(struct pt_regs *regs) printf("Machine check in kernel mode.\n"); printf("Caused by (from msr): "); printf("regs %p ", regs); - switch (regs->msr & 0x000F0000) { - case (0x80000000 >> 12): + switch ( regs->msr & 0x001F0000) { + case (0x80000000>>11): + printf("MSS error. MSSSR0: %08x\n", mfspr(SPRN_MSSSR0)); + break; + case (0x80000000>>12): printf("Machine check signal - probably due to mm fault\n" "with mmu off\n"); break; @@ -209,6 +212,7 @@ UnknownException(struct pt_regs *regs) if (debugger_exception_handler && (*debugger_exception_handler) (regs)) return; #endif + printf("UnknownException regs@%x\n", regs); printf("Bad trap at PC: %lx, SR: %lx, vector=%lx\n", regs->nip, regs->msr, regs->trap); _exception(0, regs); diff --git a/include/asm-ppc/immap_86xx.h b/include/asm-ppc/immap_86xx.h index 0e3fc3403..169725b92 100644 --- a/include/asm-ppc/immap_86xx.h +++ b/include/asm-ppc/immap_86xx.h @@ -1257,9 +1257,12 @@ typedef struct ccsr_gur { uint porpllsr; /* 0xe0000 - POR PLL ratio status register */ uint porbmsr; /* 0xe0004 - POR boot mode status register */ #define MPC86xx_PORBMSR_HA 0x00060000 +#define MPC85xx_PORBMSR_HA 0x00070000 uint porimpscr; /* 0xe0008 - POR I/O impedance status and control register */ uint pordevsr; /* 0xe000c - POR I/O device status regsiter */ -#define MPC86xx_PORDEVSR_IO_SEL 0x000F0000 +#define MPC86xx_PORDEVSR_IO_SEL 0x000F0000 +#define MPC85xx_PORDEVSR_IO_SEL 0x00380000 /* 85xx platform type */ +#define MPC86xx_PORDEVSR_CORE1TE 0x00000080 /* ASMP (Core1 addr trans) */ uint pordbgmsr; /* 0xe0010 - POR debug mode status register */ char res1[12]; uint gpporcr; /* 0xe0020 - General-purpose POR configuration register */ @@ -1273,8 +1276,11 @@ typedef struct ccsr_gur { uint pmuxcr; /* 0xe0060 - Alternate function signal multiplex control */ char res6[12]; uint devdisr; /* 0xe0070 - Device disable control */ -#define MPC86xx_DEVDISR_PCIEX1 0x80000000 -#define MPC86xx_DEVDISR_PCIEX2 0x40000000 +#define MPC86xx_DEVDISR_PCIEX1 0x80000000 +#define MPC86xx_DEVDISR_PCIEX2 0x40000000 +#define MPC86xx_DEVDISR_PCI1 0x80000000 +#define MPC86xx_DEVDISR_PCIE1 0x40000000 +#define MPC86xx_DEVDISR_PCIE2 0x20000000 char res7[12]; uint powmgtcsr; /* 0xe0080 - Power management status and control register */ char res8[12]; @@ -1282,7 +1288,9 @@ typedef struct ccsr_gur { char res9[12]; uint pvr; /* 0xe00a0 - Processor version register */ uint svr; /* 0xe00a4 - System version register */ - char res10[3416]; + char res10a[1880]; + uint clkdvdr; /* 0xe0800 - Clock Divide register */ + char res10b[1532]; uint clkocr; /* 0xe0e00 - Clock out select register */ char res11[12]; uint ddrdllcr; /* 0xe0e10 - DDR DLL control register */ diff --git a/include/asm-ppc/processor.h b/include/asm-ppc/processor.h index 71e2e847a..b806cc09f 100644 --- a/include/asm-ppc/processor.h +++ b/include/asm-ppc/processor.h @@ -464,7 +464,8 @@ #define ESR_ST 0x00800000 /* Store Operation */ #if defined(CONFIG_MPC86xx) -#define SPRN_MSSCRO 0x3f6 +#define SPRN_MSSCR0 0x3f6 +#define SPRN_MSSSR0 0x3f7 #endif From cf0b185e58ca0aec8ae2b2a8804ec0ef58ee21d4 Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Mon, 6 Aug 2007 17:39:44 -0500 Subject: [PATCH 079/259] 8641hpcn: Do correct sized pointer math. When I rebased Ed's patch and cleaned up a few compilation problems, I apparently rebased my brain on crack first. Fix that by doing (char *) sized pointer math as needed. Signed-off-by: Jon Loeliger --- board/mpc8641hpcn/mpc8641hpcn.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/board/mpc8641hpcn/mpc8641hpcn.c b/board/mpc8641hpcn/mpc8641hpcn.c index d2182aba5..1bfbe88b5 100644 --- a/board/mpc8641hpcn/mpc8641hpcn.c +++ b/board/mpc8641hpcn/mpc8641hpcn.c @@ -268,8 +268,8 @@ void pci_init_board(void) * Activate ULI1575 legacy chip by performing a fake * memory access. Needed to make ULI RTC work. */ - in_be32((unsigned *) CFG_PCI1_MEM_BASE - + CFG_PCI1_MEM_SIZE - 0x1000000); + in_be32((unsigned *) ((char *)(CFG_PCI1_MEM_BASE + + CFG_PCI1_MEM_SIZE - 0x1000000))); } else { puts("PCI-EXPRESS 1: Disabled\n"); From 936b3e69b667c3eb9a61ece4e78647d3fce9fc2a Mon Sep 17 00:00:00 2001 From: Ed Swarthout Date: Fri, 27 Jul 2007 01:50:44 -0500 Subject: [PATCH 080/259] pciauto_setup_device bars_num fix Passing bars_num=0 to pciauto_setup_device should assign no bars. Signed-off-by: Ed Swarthout Acked-by: Shinya Kuribayashi Acked-by: Andy Fleming --- drivers/pci_auto.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pci_auto.c b/drivers/pci_auto.c index a3c609ba4..2378553be 100644 --- a/drivers/pci_auto.c +++ b/drivers/pci_auto.c @@ -94,7 +94,7 @@ void pciauto_setup_device(struct pci_controller *hose, pci_hose_read_config_dword(hose, dev, PCI_COMMAND, &cmdstat); cmdstat = (cmdstat & ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) | PCI_COMMAND_MASTER; - for (bar = PCI_BASE_ADDRESS_0; bar <= PCI_BASE_ADDRESS_0 + (bars_num*4); bar += 4) { + for (bar = PCI_BASE_ADDRESS_0; bar < PCI_BASE_ADDRESS_0 + (bars_num*4); bar += 4) { /* Tickle the BAR and get the response */ pci_hose_write_config_dword(hose, dev, bar, 0xffffffff); pci_hose_read_config_dword(hose, dev, bar, &bar_response); From 2e4d94f1e3c2961428967a33b6ff2520568391b3 Mon Sep 17 00:00:00 2001 From: Ed Swarthout Date: Fri, 27 Jul 2007 01:50:45 -0500 Subject: [PATCH 081/259] fsl_pci_init cleanup. Do not enable normal errors created during probe (master abort, perr, and pcie Invalid Configuration access). Add CONFIG_PCI_NOSCAN board option to prevent bus scan. Signed-off-by: Ed Swarthout Acked-by: Andy Fleming --- drivers/fsl_pci_init.c | 46 ++++++++++++------------------------- include/asm-ppc/processor.h | 2 +- 2 files changed, 16 insertions(+), 32 deletions(-) diff --git a/drivers/fsl_pci_init.c b/drivers/fsl_pci_init.c index 1d1f6df99..1084dc6b7 100644 --- a/drivers/fsl_pci_init.c +++ b/drivers/fsl_pci_init.c @@ -15,7 +15,7 @@ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, * MA 02111-1307 USA */ -#define DEBUG + #include #ifdef CONFIG_FSL_PCI_INIT @@ -93,7 +93,11 @@ fsl_pci_init(struct pci_controller *hose) hose->current_busno = hose->first_busno; pci->pedr = 0xffffffff; /* Clear any errors */ - pci->peer = 0xffffffff; /* Enable Error Interupts */ + pci->peer = ~0x20140; /* Enable All Error Interupts except + * - Master abort (pci) + * - Master PERR (pci) + * - ICCA (PCIe) + */ pci_hose_read_config_dword (hose, dev, PCI_DCR, &temp32); temp32 |= 0xf000e; /* set URR, FER, NFER (but not CER) */ pci_hose_write_config_dword(hose, dev, PCI_DCR, temp32); @@ -108,7 +112,7 @@ fsl_pci_init(struct pci_controller *hose) if (!enabled) { debug("....PCIE link error. Skipping scan." - "LTSSM=0x%02x\n", temp16); + "LTSSM=0x%02x\n", ltssm); hose->last_busno = hose->first_busno; return; } @@ -118,61 +122,41 @@ fsl_pci_init(struct pci_controller *hose) #ifdef DEBUG pci_hose_read_config_word(hose, dev, PCI_LSR, &temp16); neg_link_w = (temp16 & 0x3f0 ) >> 4; - debug("...PCIE LTSSM=0x%x, Negotiated link width=%d\n", + printf("...PCIE LTSSM=0x%x, Negotiated link width=%d\n", ltssm, neg_link_w); #endif hose->current_busno++; /* Start scan with secondary */ pciauto_prescan_setup_bridge(hose, dev, hose->current_busno); - } else { -#if 0 -/* done in pci_hose_config_device() */ - pci_hose_read_config_word(hose, dev, PCI_COMMAND, &temp16); - temp16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | - PCI_COMMAND_MEMORY | PCI_COMMAND_IO; - pci_hose_write_config_word(hose, dev, PCI_COMMAND, temp16); - pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff); - pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80); -#endif } /* Call setup to allocate PCSRBAR window */ pciauto_setup_device(hose, dev, 1, hose->pci_mem, hose->pci_prefetch, hose->pci_io); - +#ifndef CONFIG_PCI_NOSCAN printf (" Scanning PCI bus %02x\n", hose->current_busno); hose->last_busno = pci_hose_scan_bus(hose,hose->current_busno); if ( bridge ) { /* update limit regs and subordinate busno */ pciauto_postscan_setup_bridge(hose, dev, hose->last_busno); } +#else + hose->last_busno = hose->current_busno; +#endif /* Clear all error indications */ - if (pci->pme_msg_det && pci->pme_msg_det != 0xffffffff) { - debug("pci_fsl_init: pme_msg_det@%x=%x. Clearing\n", - &pci->pme_msg_det, pci->pme_msg_det); - pci->pme_msg_det = 0xffffffff; - } - - if (pci->pedr) { - debug("pci_fsl_init: pedr@%x=%x. Clearing\n", - &pci->pedr, pci->pedr); - pci->pedr = 0xffffffff; - } + pci->pme_msg_det = 0xffffffff; + pci->pedr = 0xffffffff; pci_hose_read_config_word (hose, dev, PCI_DSR, &temp16); if (temp16) { - debug("pci_fsl_init: PCI_DSR@%x=%x. Clearing\n", - PCI_DSR, temp16); pci_hose_write_config_word(hose, dev, - PCI_DSR, 0xffff); + PCI_DSR, 0xffff); } pci_hose_read_config_word (hose, dev, PCI_SEC_STATUS, &temp16); if (temp16) { - debug("pci_fsl_init: PCI_SEC_STATUS@%x=%x. Clearing\n", - PCI_SEC_STATUS, temp16); pci_hose_write_config_word(hose, dev, PCI_SEC_STATUS, 0xffff); } } diff --git a/include/asm-ppc/processor.h b/include/asm-ppc/processor.h index b806cc09f..9be5a279e 100644 --- a/include/asm-ppc/processor.h +++ b/include/asm-ppc/processor.h @@ -532,7 +532,7 @@ #define LR SPRN_LR #define MBAR SPRN_MBAR /* System memory base address */ #if defined(CONFIG_MPC86xx) -#define MSSCR0 SPRN_MSSCRO +#define MSSCR0 SPRN_MSSCR0 #endif #if defined(CONFIG_E500) || defined(CONFIG_MPC86xx) #define PIR SPRN_PIR From 8ac273271d57321f90505c7a51cdb1ef2113b628 Mon Sep 17 00:00:00 2001 From: Joe Hamman Date: Thu, 9 Aug 2007 15:10:53 -0500 Subject: [PATCH 082/259] Add support for SBC8641D. Board files. Add support for Wind River's SBC8641D reference board. Signed-off by: Joe Hamman Acked-by: Wolfgang Denk Acked-by: Jon Loeliger --- board/sbc8641d/Makefile | 52 ++++++ board/sbc8641d/config.mk | 30 ++++ board/sbc8641d/init.S | 192 ++++++++++++++++++++++ board/sbc8641d/sbc8641d.c | 326 ++++++++++++++++++++++++++++++++++++++ board/sbc8641d/u-boot.lds | 135 ++++++++++++++++ 5 files changed, 735 insertions(+) create mode 100644 board/sbc8641d/Makefile create mode 100644 board/sbc8641d/config.mk create mode 100644 board/sbc8641d/init.S create mode 100644 board/sbc8641d/sbc8641d.c create mode 100644 board/sbc8641d/u-boot.lds diff --git a/board/sbc8641d/Makefile b/board/sbc8641d/Makefile new file mode 100644 index 000000000..a90b725db --- /dev/null +++ b/board/sbc8641d/Makefile @@ -0,0 +1,52 @@ +# +# (C) Copyright 2001 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS := $(BOARD).o +SOBJS := init.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +clean: + rm -f $(OBJS) $(SOBJS) + +.PHONY: distclean +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude ($obj).depend + +######################################################################### diff --git a/board/sbc8641d/config.mk b/board/sbc8641d/config.mk new file mode 100644 index 000000000..dd1754d2b --- /dev/null +++ b/board/sbc8641d/config.mk @@ -0,0 +1,30 @@ +# Copyright 2004 Freescale Semiconductor. +# Modified by Jeff Brown +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# sbc8641 board +# default CCSRBAR is at 0xff700000 +# +TEXT_BASE = 0xfff00000 + +PLATFORM_CPPFLAGS += -DCONFIG_MPC86xx=1 +PLATFORM_CPPFLAGS += -DCONFIG_MPC8641=1 -maltivec -mabi=altivec -msoft-float diff --git a/board/sbc8641d/init.S b/board/sbc8641d/init.S new file mode 100644 index 000000000..c151d7eff --- /dev/null +++ b/board/sbc8641d/init.S @@ -0,0 +1,192 @@ +/* + * Copyright 2007 Wind River Systemes, Inc. + * Copyright 2007 Embedded Specialties, Inc. + * Joe Hamman joe.hamman@embeddedspecialties.com + * + * Copyright 2004 Freescale Semiconductor. + * Jeff Brown + * Srikanth Srinivasan (srikanth.srinivasan@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include + +/* + * LAW(Local Access Window) configuration: + * + * 0x0000_0000 0x0fff_ffff DDR1 256M + * 0x1000_0000 0x1fff_ffff DDR2 256M + * 0xe000_0000 0xffff_ffff LBC 512M + * + * Notes: + * CCSRBAR doesn't need a configured Local Access Window. + * If flash is 8M at default position (last 8M), no LAW needed. + */ + +# DDR Bank 1 +# #define LAWBAR1 ((CFG_DDR_SDRAM_BASE>>12) & 0xffffff) +# #define LAWAR1 (LAWAR_EN | LAWAR_TRGT_IF_DDR1 | (LAWAR_SIZE & LAWAR_SIZE_256M)) + +# DDR Bank 2 +# #define LAWBAR2 ((CFG_DDR_SDRAM_BASE2>>12) & 0xffffff) +# #define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_DDR2 | (LAWAR_SIZE & LAWAR_SIZE_256M)) + +# LBC +# #define LAWBAR3 ((0xe0000000>>12) & 0xffffff) +# #define LAWAR3 (LAWAR_EN & (LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_512M))) + +/* + * LAW (Local Access Window) configuration: + * + * 0x0000_0000 DDR 256M + * 0x1000_0000 DDR2 256M + * 0x8000_0000 PCI1 MEM 512M + * 0xa000_0000 PCI2 MEM 512M + * 0xc000_0000 RapidIO 512M + * 0xe200_0000 PCI1 IO 16M + * 0xe300_0000 PCI2 IO 16M + * 0xf800_0000 CCSRBAR 2M + * 0xfe00_0000 FLASH (boot bank) 32M + * + */ + +#define LAWBAR1 ((CFG_DDR_SDRAM_BASE>>12) & 0xffffff) +#define LAWAR1 (LAWAR_EN | LAWAR_TRGT_IF_DDR1 | (LAWAR_SIZE & LAWAR_SIZE_256M)) + +#define LAWBAR2 ((CFG_PCI1_MEM_BASE>>12) & 0xffffff) +#define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_512M)) + +#define LAWBAR3 ((CFG_PCI2_MEM_BASE>>12) & 0xffffff) +#define LAWAR3 (~LAWAR_EN & (LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_512M))) + +#define LAWBAR4 ((0xf8000000>>12) & 0xffffff) +#define LAWAR4 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_2M)) + +#define LAWBAR5 ((CFG_PCI1_IO_BASE>>12) & 0xffffff) +#define LAWAR5 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_16M)) + +#define LAWBAR6 ((CFG_PCI2_IO_BASE>>12) & 0xffffff) +#define LAWAR6 (~LAWAR_EN &( LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_16M))) + +#define LAWBAR7 ((0xfe000000 >>12) & 0xffffff) +#define LAWAR7 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_32M)) + +#define LAWBAR8 ((CFG_DDR_SDRAM_BASE2>>12) & 0xffffff) +#define LAWAR8 (LAWAR_EN | LAWAR_TRGT_IF_DDR2 | (LAWAR_SIZE & LAWAR_SIZE_256M)) + +#define LAWBAR9 ((CFG_RIO_MEM_BASE>>12) & 0xfffff) +#define LAWAR9 (LAWAR_EN | LAWAR_TRGT_IF_RIO | (LAWAR_SIZE & LAWAR_SIZE_512M)) + + .section .bootpg, "ax" + .globl law_entry +law_entry: + lis r7,CFG_CCSRBAR@h + ori r7,r7,CFG_CCSRBAR@l + + addi r4,r7,0 + addi r5,r7,0 + + /* Skip LAWAR0, start at LAWAR1 */ + lis r6,LAWBAR1@h + ori r6,r6,LAWBAR1@l + stwu r6, 0xc28(r4) + + lis r6,LAWAR1@h + ori r6,r6,LAWAR1@l + stwu r6, 0xc30(r5) + + /* LAWBAR2, LAWAR2 */ + lis r6,LAWBAR2@h + ori r6,r6,LAWBAR2@l + stwu r6, 0x20(r4) + + lis r6,LAWAR2@h + ori r6,r6,LAWAR2@l + stwu r6, 0x20(r5) + + /* LAWBAR3, LAWAR3 */ + lis r6,LAWBAR3@h + ori r6,r6,LAWBAR3@l + stwu r6, 0x20(r4) + + lis r6,LAWAR3@h + ori r6,r6,LAWAR3@l + stwu r6, 0x20(r5) + + /* LAWBAR4, LAWAR4 */ + lis r6,LAWBAR4@h + ori r6,r6,LAWBAR4@l + stwu r6, 0x20(r4) + + lis r6,LAWAR4@h + ori r6,r6,LAWAR4@l + stwu r6, 0x20(r5) + + /* LAWBAR5, LAWAR5 */ + lis r6,LAWBAR5@h + ori r6,r6,LAWBAR5@l + stwu r6, 0x20(r4) + + lis r6,LAWAR5@h + ori r6,r6,LAWAR5@l + stwu r6, 0x20(r5) + + /* LAWBAR6, LAWAR6 */ + lis r6,LAWBAR6@h + ori r6,r6,LAWBAR6@l + stwu r6, 0x20(r4) + + lis r6,LAWAR6@h + ori r6,r6,LAWAR6@l + stwu r6, 0x20(r5) + + /* LAWBAR7, LAWAR7 */ + lis r6,LAWBAR7@h + ori r6,r6,LAWBAR7@l + stwu r6, 0x20(r4) + + lis r6,LAWAR7@h + ori r6,r6,LAWAR7@l + stwu r6, 0x20(r5) + + /* LAWBAR8, LAWAR8 */ + lis r6,LAWBAR8@h + ori r6,r6,LAWBAR8@l + stwu r6, 0x20(r4) + + lis r6,LAWAR8@h + ori r6,r6,LAWAR8@l + stwu r6, 0x20(r5) + + /* LAWBAR9, LAWAR9 */ + lis r6,LAWBAR9@h + ori r6,r6,LAWBAR9@l + stwu r6, 0x20(r4) + + lis r6,LAWAR9@h + ori r6,r6,LAWAR9@l + stwu r6, 0x20(r5) + + blr diff --git a/board/sbc8641d/sbc8641d.c b/board/sbc8641d/sbc8641d.c new file mode 100644 index 000000000..e5dd5509c --- /dev/null +++ b/board/sbc8641d/sbc8641d.c @@ -0,0 +1,326 @@ +/* + * Copyright 2007 Wind River Systemes, Inc. + * Copyright 2007 Embedded Specialties, Inc. + * Joe Hamman joe.hamman@embeddedspecialties.com + * + * Copyright 2004 Freescale Semiconductor. + * Jeff Brown + * Srikanth Srinivasan (srikanth.srinivasan@freescale.com) + * + * (C) Copyright 2002 Scott McNutt + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include + +#if defined(CONFIG_OF_FLAT_TREE) +#include +extern void ft_cpu_setup (void *blob, bd_t * bd); +#endif + +#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) +extern void ddr_enable_ecc (unsigned int dram_size); +#endif + +#if defined(CONFIG_SPD_EEPROM) +#include "spd_sdram.h" +#endif + +void sdram_init (void); +long int fixed_sdram (void); + +int board_early_init_f (void) +{ + return 0; +} + +int checkboard (void) +{ + puts ("Board: Wind River SBC8641D\n"); + +#ifdef CONFIG_PCI + + volatile immap_t *immap = (immap_t *) CFG_CCSRBAR; + volatile ccsr_gur_t *gur = &immap->im_gur; + volatile ccsr_pex_t *pex1 = &immap->im_pex1; + + uint devdisr = gur->devdisr; + uint io_sel = (gur->pordevsr & MPC86xx_PORDEVSR_IO_SEL) >> 16; + uint host1_agent = (gur->porbmsr & MPC86xx_PORBMSR_HA) >> 17; + uint pex1_agent = (host1_agent == 0) || (host1_agent == 1); + + if ((io_sel == 2 || io_sel == 3 || io_sel == 5 + || io_sel == 6 || io_sel == 7 || io_sel == 0xF) + && !(devdisr & MPC86xx_DEVDISR_PCIEX1)) { + debug ("PCI-EXPRESS 1: %s \n", pex1_agent ? "Agent" : "Host"); + debug ("0x%08x=0x%08x ", &pex1->pme_msg_det, pex1->pme_msg_det); + if (pex1->pme_msg_det) { + pex1->pme_msg_det = 0xffffffff; + debug (" with errors. Clearing. Now 0x%08x", + pex1->pme_msg_det); + } + debug ("\n"); + } else { + puts ("PCI-EXPRESS 1: Disabled in hardware\n"); + } + +#else + puts ("PCI-EXPRESS1: Disabled in configuration\n"); +#endif + + return 0; +} + +long int initdram (int board_type) +{ + long dram_size = 0; + +#if defined(CONFIG_SPD_EEPROM) + dram_size = spd_sdram (); +#else + dram_size = fixed_sdram (); +#endif + +#if defined(CFG_RAMBOOT) + puts (" DDR: "); + return dram_size; +#endif + +#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) + /* + * Initialize and enable DDR ECC. + */ + ddr_enable_ecc (dram_size); +#endif + + puts (" DDR: "); + return dram_size; +} + +#if defined(CFG_DRAM_TEST) +int testdram (void) +{ + uint *pstart = (uint *) CFG_MEMTEST_START; + uint *pend = (uint *) CFG_MEMTEST_END; + uint *p; + + puts ("SDRAM test phase 1:\n"); + for (p = pstart; p < pend; p++) + *p = 0xaaaaaaaa; + + for (p = pstart; p < pend; p++) { + if (*p != 0xaaaaaaaa) { + printf ("SDRAM test fails at: %08x\n", (uint) p); + return 1; + } + } + + puts ("SDRAM test phase 2:\n"); + for (p = pstart; p < pend; p++) + *p = 0x55555555; + + for (p = pstart; p < pend; p++) { + if (*p != 0x55555555) { + printf ("SDRAM test fails at: %08x\n", (uint) p); + return 1; + } + } + + puts ("SDRAM test passed.\n"); + return 0; +} +#endif + +#if !defined(CONFIG_SPD_EEPROM) +/* + * Fixed sdram init -- doesn't use serial presence detect. + */ +long int fixed_sdram (void) +{ +#if !defined(CFG_RAMBOOT) + volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile ccsr_ddr_t *ddr = &immap->im_ddr1; + + ddr->cs0_bnds = CFG_DDR_CS0_BNDS; + ddr->cs1_bnds = CFG_DDR_CS1_BNDS; + ddr->cs2_bnds = CFG_DDR_CS2_BNDS; + ddr->cs3_bnds = CFG_DDR_CS3_BNDS; + ddr->cs0_config = CFG_DDR_CS0_CONFIG; + ddr->cs1_config = CFG_DDR_CS1_CONFIG; + ddr->cs2_config = CFG_DDR_CS2_CONFIG; + ddr->cs3_config = CFG_DDR_CS3_CONFIG; + ddr->ext_refrec = CFG_DDR_EXT_REFRESH; + ddr->timing_cfg_0 = CFG_DDR_TIMING_0; + ddr->timing_cfg_1 = CFG_DDR_TIMING_1; + ddr->timing_cfg_2 = CFG_DDR_TIMING_2; + ddr->sdram_cfg_1 = CFG_DDR_CFG_1A; + ddr->sdram_cfg_2 = CFG_DDR_CFG_2; + ddr->sdram_mode_1 = CFG_DDR_MODE_1; + ddr->sdram_mode_2 = CFG_DDR_MODE_2; + ddr->sdram_mode_cntl = CFG_DDR_MODE_CTL; + ddr->sdram_interval = CFG_DDR_INTERVAL; + ddr->sdram_data_init = CFG_DDR_DATA_INIT; + ddr->sdram_clk_cntl = CFG_DDR_CLK_CTRL; + + asm ("sync;isync"); + + udelay (500); + + ddr->sdram_cfg_1 = CFG_DDR_CFG_1B; + asm ("sync; isync"); + + udelay (500); + ddr = &immap->im_ddr2; + + ddr->cs0_bnds = CFG_DDR2_CS0_BNDS; + ddr->cs1_bnds = CFG_DDR2_CS1_BNDS; + ddr->cs2_bnds = CFG_DDR2_CS2_BNDS; + ddr->cs3_bnds = CFG_DDR2_CS3_BNDS; + ddr->cs0_config = CFG_DDR2_CS0_CONFIG; + ddr->cs1_config = CFG_DDR2_CS1_CONFIG; + ddr->cs2_config = CFG_DDR2_CS2_CONFIG; + ddr->cs3_config = CFG_DDR2_CS3_CONFIG; + ddr->ext_refrec = CFG_DDR2_EXT_REFRESH; + ddr->timing_cfg_0 = CFG_DDR2_TIMING_0; + ddr->timing_cfg_1 = CFG_DDR2_TIMING_1; + ddr->timing_cfg_2 = CFG_DDR2_TIMING_2; + ddr->sdram_cfg_1 = CFG_DDR2_CFG_1A; + ddr->sdram_cfg_2 = CFG_DDR2_CFG_2; + ddr->sdram_mode_1 = CFG_DDR2_MODE_1; + ddr->sdram_mode_2 = CFG_DDR2_MODE_2; + ddr->sdram_mode_cntl = CFG_DDR2_MODE_CTL; + ddr->sdram_interval = CFG_DDR2_INTERVAL; + ddr->sdram_data_init = CFG_DDR2_DATA_INIT; + ddr->sdram_clk_cntl = CFG_DDR2_CLK_CTRL; + + asm ("sync;isync"); + + udelay (500); + + ddr->sdram_cfg_1 = CFG_DDR2_CFG_1B; + asm ("sync; isync"); + + udelay (500); +#endif + return CFG_SDRAM_SIZE * 1024 * 1024; +} +#endif /* !defined(CONFIG_SPD_EEPROM) */ + +#if defined(CONFIG_PCI) +/* + * Initialize PCI Devices, report devices found. + */ + +#ifndef CONFIG_PCI_PNP +static struct pci_config_table pci_fsl86xxads_config_table[] = { + {PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, + PCI_IDSEL_NUMBER, PCI_ANY_ID, + pci_cfgfunc_config_device, {PCI_ENET0_IOADDR, + PCI_ENET0_MEMADDR, + PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER}}, + {} +}; +#endif + +static struct pci_controller hose = { +#ifndef CONFIG_PCI_PNP + config_table:pci_mpc86xxcts_config_table, +#endif +}; + +#endif /* CONFIG_PCI */ + +void pci_init_board (void) +{ +#ifdef CONFIG_PCI + extern void pci_mpc86xx_init (struct pci_controller *hose); + + pci_mpc86xx_init (&hose); +#endif /* CONFIG_PCI */ +} + +#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP) +void ft_board_setup (void *blob, bd_t * bd) +{ + u32 *p; + int len; + + ft_cpu_setup (blob, bd); + + p = ft_get_prop (blob, "/memory/reg", &len); + if (p != NULL) { + *p++ = cpu_to_be32 (bd->bi_memstart); + *p = cpu_to_be32 (bd->bi_memsize); + } +} +#endif + +void sbc8641d_reset_board (void) +{ + puts ("Resetting board....\n"); +} + +/* + * get_board_sys_clk + * Clock is fixed at 1GHz on this board. Used for CONFIG_SYS_CLK_FREQ + */ + +unsigned long get_board_sys_clk (ulong dummy) +{ + int i; + ulong val = 0; + + i = 5; + i &= 0x07; + + switch (i) { + case 0: + val = 33000000; + break; + case 1: + val = 40000000; + break; + case 2: + val = 50000000; + break; + case 3: + val = 66000000; + break; + case 4: + val = 83000000; + break; + case 5: + val = 100000000; + break; + case 6: + val = 134000000; + break; + case 7: + val = 166000000; + break; + } + + return val; +} diff --git a/board/sbc8641d/u-boot.lds b/board/sbc8641d/u-boot.lds new file mode 100644 index 000000000..fd0f35039 --- /dev/null +++ b/board/sbc8641d/u-boot.lds @@ -0,0 +1,135 @@ +/* + * Copyright 2006, 2007 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) + +SECTIONS +{ + + /* Read-only sections, merged into text segment: */ + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/mpc86xx/start.o (.text) + board/sbc8641d/init.o (.bootpg) + cpu/mpc86xx/traps.o (.text) + cpu/mpc86xx/interrupts.o (.text) + cpu/mpc86xx/cpu_init.o (.text) + cpu/mpc86xx/cpu.o (.text) + cpu/mpc86xx/speed.o (.text) + common/dlmalloc.o (.text) + lib_generic/crc32.o (.text) + lib_ppc/extable.o (.text) + lib_generic/zlib.o (.text) + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} From c646bba6465a45c60746d4cc1602cd06c1960f2d Mon Sep 17 00:00:00 2001 From: Joe Hamman Date: Thu, 9 Aug 2007 15:11:03 -0500 Subject: [PATCH 083/259] Add support for SBC8641D. Config files. Add support for Wind River's SBC8641D reference board. Signed-off by: Joe Hamman Acked-by: Wolfgang Denk Acked-by: Jon Loeliger --- MAINTAINERS | 4 + MAKEALL | 1 + Makefile | 2 + doc/README.sbc8641d | 28 ++ include/configs/sbc8641d.h | 599 +++++++++++++++++++++++++++++++++++++ 5 files changed, 634 insertions(+) create mode 100644 doc/README.sbc8641d create mode 100644 include/configs/sbc8641d.h diff --git a/MAINTAINERS b/MAINTAINERS index 693b11572..703f2fe48 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -179,6 +179,10 @@ Howard Gray MVS1 MPC823 +Joe Hamman + + sbc8641d MPC8641D + Klaus Heydeck KUP4K MPC855 diff --git a/MAKEALL b/MAKEALL index 3e186ccd5..22b12061e 100755 --- a/MAKEALL +++ b/MAKEALL @@ -165,6 +165,7 @@ LIST_85xx=" \ LIST_86xx=" \ MPC8641HPCN \ + SBC8641D \ " ######################################################################### diff --git a/Makefile b/Makefile index 2a18a4d6a..4b607365f 100644 --- a/Makefile +++ b/Makefile @@ -1866,6 +1866,8 @@ TQM8560_config: unconfig MPC8641HPCN_config: unconfig @$(MKCONFIG) $(@:_config=) ppc mpc86xx mpc8641hpcn +sbc8641d_config: unconfig + @./mkconfig $(@:_config=) ppc mpc86xx sbc8641d ######################################################################### ## 74xx/7xx Systems diff --git a/doc/README.sbc8641d b/doc/README.sbc8641d new file mode 100644 index 000000000..a051466a1 --- /dev/null +++ b/doc/README.sbc8641d @@ -0,0 +1,28 @@ +Wind River SBC8641D reference board +=========================== + +Created 06/14/2007 Joe Hamman +Copyright 2007, Embedded Specialties, Inc. +Copyright 2007 Wind River Systemes, Inc. +----------------------------- + +1. Building U-Boot +------------------ +The SBC8641D code is known to build using ELDK 4.1. + + $ make sbc8641d_config + Configuring for sbc8641d board... + + $ make + + +2. Switch and Jumper Settings +----------------------------- +All Jumpers & Switches are in their default positions. Please refer to +the board documentation for details. Some settings control CPU voltages +and settings may change with board revisions. + +3. Known limitations +-------------------- +PCI: + The PCI command may hang if no boards are present in either slot. diff --git a/include/configs/sbc8641d.h b/include/configs/sbc8641d.h new file mode 100644 index 000000000..dba19441c --- /dev/null +++ b/include/configs/sbc8641d.h @@ -0,0 +1,599 @@ +/* + * Copyright 2007 Wind River Systems + * Copyright 2007 Embedded Specialties, Inc. + * Joe Hamman + * + * Copyright 2006 Freescale Semiconductor. + * + * Srikanth Srinivasan (srikanth.srinivasan@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * SBC8641D board configuration file + * + * Make sure you change the MAC address and other network params first, + * search for CONFIG_ETHADDR, CONFIG_SERVERIP, etc in this file. + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* High Level Configuration Options */ +#define CONFIG_MPC86xx 1 /* MPC86xx */ +#define CONFIG_MPC8641 1 /* MPC8641 specific */ +#define CONFIG_SBC8641D 1 /* SBC8641D board specific */ +#define CONFIG_NUM_CPUS 2 /* Number of CPUs in the system */ +#define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */ + +#ifdef RUN_DIAG +#define CFG_DIAG_ADDR 0xff800000 +#endif + +#define CFG_RESET_ADDRESS 0xfff00100 + +#undef CONFIG_PCI +#define CONFIG_FSL_PCI_INIT 1 + +#define CONFIG_TSEC_ENET /* tsec ethernet support */ +#define CONFIG_ENV_OVERWRITE + +#undef CONFIG_SPD_EEPROM /* Do not use SPD EEPROM for DDR setup*/ +#undef CONFIG_DDR_DLL /* possible DLL fix needed */ +#define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */ +#undef CONFIG_DDR_ECC /* only for ECC DDR module */ +#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ +#define CONFIG_MEM_INIT_VALUE 0xDeadBeef +#define CONFIG_NUM_DDR_CONTROLLERS 2 +#define CACHE_LINE_INTERLEAVING 0x20000000 +#define PAGE_INTERLEAVING 0x21000000 +#define BANK_INTERLEAVING 0x22000000 +#define SUPER_BANK_INTERLEAVING 0x23000000 + + +#define CONFIG_ALTIVEC 1 + +/* + * L2CR setup -- make sure this is right for your board! + */ +#define CFG_L2 +#define L2_INIT 0 +#define L2_ENABLE (L2CR_L2E) + +#ifndef CONFIG_SYS_CLK_FREQ +#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) +#endif + +#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ + +#undef CFG_DRAM_TEST /* memory test, takes time */ +#define CFG_MEMTEST_START 0x00200000 /* memtest region */ +#define CFG_MEMTEST_END 0x00400000 + +/* + * Base addresses -- Note these are effective addresses where the + * actual resources get mapped (not physical addresses) + */ +#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ +#define CFG_CCSRBAR 0xf8000000 /* relocated CCSRBAR */ +#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ + +/* + * DDR Setup + */ +#define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory */ +#define CFG_DDR_SDRAM_BASE2 0x10000000 /* DDR bank 2 */ +#define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE +#define CFG_SDRAM_BASE2 CFG_DDR_SDRAM_BASE2 +#define CONFIG_VERY_BIG_RAM + +#define MPC86xx_DDR_SDRAM_CLK_CNTL + +#if defined(CONFIG_SPD_EEPROM) + /* + * Determine DDR configuration from I2C interface. + */ + #define SPD_EEPROM_ADDRESS1 0x51 /* DDR DIMM */ + #define SPD_EEPROM_ADDRESS2 0x52 /* DDR DIMM */ + #define SPD_EEPROM_ADDRESS3 0x53 /* DDR DIMM */ + #define SPD_EEPROM_ADDRESS4 0x54 /* DDR DIMM */ + +#else + /* + * Manually set up DDR1 & DDR2 parameters + */ + + #define CFG_SDRAM_SIZE 512 /* DDR is 512MB */ + + #define CFG_DDR_CS0_BNDS 0x0000000F + #define CFG_DDR_CS1_BNDS 0x00000000 + #define CFG_DDR_CS2_BNDS 0x00000000 + #define CFG_DDR_CS3_BNDS 0x00000000 + #define CFG_DDR_CS0_CONFIG 0x80010102 + #define CFG_DDR_CS1_CONFIG 0x00000000 + #define CFG_DDR_CS2_CONFIG 0x00000000 + #define CFG_DDR_CS3_CONFIG 0x00000000 + #define CFG_DDR_EXT_REFRESH 0x00000000 + #define CFG_DDR_TIMING_0 0x00220802 + #define CFG_DDR_TIMING_1 0x38377322 + #define CFG_DDR_TIMING_2 0x002040c7 + #define CFG_DDR_CFG_1A 0x43008008 + #define CFG_DDR_CFG_2 0x24401000 + #define CFG_DDR_MODE_1 0x23c00542 + #define CFG_DDR_MODE_2 0x00000000 + #define CFG_DDR_MODE_CTL 0x00000000 + #define CFG_DDR_INTERVAL 0x05080100 + #define CFG_DDR_DATA_INIT 0x00000000 + #define CFG_DDR_CLK_CTRL 0x03800000 + #define CFG_DDR_CFG_1B 0xC3008008 + + #define CFG_DDR2_CS0_BNDS 0x0010001F + #define CFG_DDR2_CS1_BNDS 0x00000000 + #define CFG_DDR2_CS2_BNDS 0x00000000 + #define CFG_DDR2_CS3_BNDS 0x00000000 + #define CFG_DDR2_CS0_CONFIG 0x80010102 + #define CFG_DDR2_CS1_CONFIG 0x00000000 + #define CFG_DDR2_CS2_CONFIG 0x00000000 + #define CFG_DDR2_CS3_CONFIG 0x00000000 + #define CFG_DDR2_EXT_REFRESH 0x00000000 + #define CFG_DDR2_TIMING_0 0x00220802 + #define CFG_DDR2_TIMING_1 0x38377322 + #define CFG_DDR2_TIMING_2 0x002040c7 + #define CFG_DDR2_CFG_1A 0x43008008 + #define CFG_DDR2_CFG_2 0x24401000 + #define CFG_DDR2_MODE_1 0x23c00542 + #define CFG_DDR2_MODE_2 0x00000000 + #define CFG_DDR2_MODE_CTL 0x00000000 + #define CFG_DDR2_INTERVAL 0x05080100 + #define CFG_DDR2_DATA_INIT 0x00000000 + #define CFG_DDR2_CLK_CTRL 0x03800000 + #define CFG_DDR2_CFG_1B 0xC3008008 + + +#endif + +/* #define CFG_ID_EEPROM 1 +#define ID_EEPROM_ADDR 0x57 */ + +/* + * The SBC8641D contains 16MB flash space at ff000000. + */ +#define CFG_FLASH_BASE 0xff000000 /* start of FLASH 16M */ + +/* Flash */ +#define CFG_BR0_PRELIM 0xff001001 /* port size 16bit */ +#define CFG_OR0_PRELIM 0xff006e65 /* 16MB Boot Flash area */ + +/* 64KB EEPROM */ +#define CFG_BR1_PRELIM 0xf0000801 /* port size 16bit */ +#define CFG_OR1_PRELIM 0xffff6e65 /* 64K EEPROM area */ + +/* EPLD - User switches, board id, LEDs */ +#define CFG_BR2_PRELIM 0xf1000801 /* port size 16bit */ +#define CFG_OR2_PRELIM 0xfff06e65 /* EPLD (switches, board ID, LEDs) area */ + +/* Local bus SDRAM 128MB */ +#define CFG_BR3_PRELIM 0xe0001861 /* port size ?bit */ +#define CFG_OR3_PRELIM 0xfc006cc0 /* 128MB local bus SDRAM area (1st half) */ +#define CFG_BR4_PRELIM 0xe4001861 /* port size ?bit */ +#define CFG_OR4_PRELIM 0xfc006cc0 /* 128MB local bus SDRAM area (2nd half) */ + +/* Disk on Chip (DOC) 128MB */ +#define CFG_BR5_PRELIM 0xe8001001 /* port size ?bit */ +#define CFG_OR5_PRELIM 0xf8006e65 /* 128MB local bus SDRAM area (2nd half) */ + +/* LCD */ +#define CFG_BR6_PRELIM 0xf4000801 /* port size ?bit */ +#define CFG_OR6_PRELIM 0xfff06e65 /* 128MB local bus SDRAM area (2nd half) */ + +/* Control logic & misc peripherals */ +#define CFG_BR7_PRELIM 0xf2000801 /* port size ?bit */ +#define CFG_OR7_PRELIM 0xfff06e65 /* 128MB local bus SDRAM area (2nd half) */ + +#define CFG_MAX_FLASH_BANKS 1 /* number of banks */ +#define CFG_MAX_FLASH_SECT 131 /* sectors per device */ + +#undef CFG_FLASH_CHECKSUM +#define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ +#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ + +#define CFG_FLASH_CFI_DRIVER +#define CFG_FLASH_CFI +#define CFG_WRITE_SWAPPED_DATA +#define CFG_FLASH_EMPTY_INFO +#define CFG_FLASH_PROTECTION + +#undef CONFIG_CLOCKS_IN_MHZ + +#define CONFIG_L1_INIT_RAM +#define CFG_INIT_RAM_LOCK 1 +#ifndef CFG_INIT_RAM_LOCK +#define CFG_INIT_RAM_ADDR 0x0fd00000 /* Initial RAM address */ +#else +#define CFG_INIT_RAM_ADDR 0xf8400000 /* Initial RAM address */ +#endif +#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */ + +#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ +#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ + +/* Serial Port */ +#define CONFIG_CONS_INDEX 1 +#undef CONFIG_SERIAL_SOFTWARE_FIFO +#define CFG_NS16550 +#define CFG_NS16550_SERIAL +#define CFG_NS16550_REG_SIZE 1 +#define CFG_NS16550_CLK get_bus_freq(0) + +#define CFG_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} + +#define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500) +#define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600) + +/* Use the HUSH parser */ +#define CFG_HUSH_PARSER +#ifdef CFG_HUSH_PARSER +#define CFG_PROMPT_HUSH_PS2 "> " +#endif + +/* + * Pass open firmware flat tree to kernel + */ +#define CONFIG_OF_FLAT_TREE 1 +#define CONFIG_OF_BOARD_SETUP 1 + +/* maximum size of the flat tree (8K) */ +#define OF_FLAT_TREE_MAX_SIZE 8192 + +#define OF_CPU "PowerPC,8641@0" +#define OF_SOC "soc@f8000000" +#define OF_TBCLK (bd->bi_busfreq / 4) +#define OF_STDOUT_PATH "/soc@f8000000/serial@4500" + +#define CFG_64BIT_VSPRINTF 1 +#define CFG_64BIT_STRTOUL 1 + +/* + * I2C + */ +#define CONFIG_FSL_I2C /* Use FSL common I2C driver */ +#define CONFIG_HARD_I2C /* I2C with hardware support*/ +#undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CFG_I2C_SLAVE 0x7F +#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ +#define CFG_I2C_OFFSET 0x3100 + +/* + * RapidIO MMU + */ +#define CFG_RIO_MEM_BASE 0xc0000000 /* base address */ +#define CFG_RIO_MEM_PHYS CFG_RIO_MEM_BASE +#define CFG_RIO_MEM_SIZE 0x20000000 /* 128M */ + +/* + * General PCI + * Addresses are mapped 1-1. + */ +#define CFG_PCI1_MEM_BASE 0x80000000 +#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE +#define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */ +#define CFG_PCI1_IO_BASE 0xe2000000 +#define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE +#define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */ + +/* PCI view of System Memory */ +#define CFG_PCI_MEMORY_BUS 0x00000000 +#define CFG_PCI_MEMORY_PHYS 0x00000000 +#define CFG_PCI_MEMORY_SIZE 0x80000000 + +#define CFG_PCI2_MEM_BASE 0xa0000000 +#define CFG_PCI2_MEM_PHYS CFG_PCI2_MEM_BASE +#define CFG_PCI2_MEM_SIZE 0x10000000 /* 256M */ +#define CFG_PCI2_IO_BASE 0xe3000000 +#define CFG_PCI2_IO_PHYS CFG_PCI2_IO_BASE +#define CFG_PCI2_IO_SIZE 0x1000000 /* 16M */ + +#if defined(CONFIG_PCI) + +#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ + +#undef CFG_SCSI_SCAN_BUS_REVERSE + +#define CONFIG_NET_MULTI +#define CONFIG_PCI_PNP /* do pci plug-and-play */ + +#undef CONFIG_EEPRO100 +#undef CONFIG_TULIP + +#if !defined(CONFIG_PCI_PNP) + #define PCI_ENET0_IOADDR 0xe0000000 + #define PCI_ENET0_MEMADDR 0xe0000000 + #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ +#endif + +#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ + +#define CONFIG_DOS_PARTITION +#undef CONFIG_SCSI_AHCI + +#ifdef CONFIG_SCSI_AHCI +#define CONFIG_SATA_ULI5288 +#define CFG_SCSI_MAX_SCSI_ID 4 +#define CFG_SCSI_MAX_LUN 1 +#define CFG_SCSI_MAX_DEVICE (CFG_SCSI_MAX_SCSI_ID * CFG_SCSI_MAX_LUN) +#define CFG_SCSI_MAXDEVICE CFG_SCSI_MAX_DEVICE +#endif + +#endif /* CONFIG_PCI */ + +#if defined(CONFIG_TSEC_ENET) + +#ifndef CONFIG_NET_MULTI +#define CONFIG_NET_MULTI 1 +#endif + +/* #define CONFIG_MII 1 */ /* MII PHY management */ + +#define CONFIG_TSEC1 1 +#define CONFIG_TSEC1_NAME "eTSEC1" +#define CONFIG_TSEC2 1 +#define CONFIG_TSEC2_NAME "eTSEC2" +#define CONFIG_TSEC3 1 +#define CONFIG_TSEC3_NAME "eTSEC3" +#define CONFIG_TSEC4 1 +#define CONFIG_TSEC4_NAME "eTSEC4" + +#define TSEC1_PHY_ADDR 0x1F +#define TSEC2_PHY_ADDR 0x00 +#define TSEC3_PHY_ADDR 0x01 +#define TSEC4_PHY_ADDR 0x02 +#define TSEC1_PHYIDX 0 +#define TSEC2_PHYIDX 0 +#define TSEC3_PHYIDX 0 +#define TSEC4_PHYIDX 0 + +#define CFG_TBIPA_VALUE 0x1e /* Set TBI address not to conflict with TSEC1_PHY_ADDR */ + +#define CONFIG_ETHPRIME "eTSEC1" + +#endif /* CONFIG_TSEC_ENET */ + +/* + * BAT0 2G Cacheable, non-guarded + * 0x0000_0000 2G DDR + */ +#define CFG_DBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE) +#define CFG_DBAT0U (BATU_BL_2G | BATU_VS | BATU_VP) +#define CFG_IBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE ) +#define CFG_IBAT0U CFG_DBAT0U + +/* + * BAT1 1G Cache-inhibited, guarded + * 0x8000_0000 512M PCI-Express 1 Memory + * 0xa000_0000 512M PCI-Express 2 Memory + * Changed it for operating from 0xd0000000 + */ +#define CFG_DBAT1L ( CFG_PCI1_MEM_BASE | BATL_PP_RW \ + | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CFG_DBAT1U (CFG_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) +#define CFG_IBAT1L (CFG_PCI1_MEM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) +#define CFG_IBAT1U CFG_DBAT1U + +/* + * BAT2 512M Cache-inhibited, guarded + * 0xc000_0000 512M RapidIO Memory + */ +#define CFG_DBAT2L (CFG_RIO_MEM_BASE | BATL_PP_RW \ + | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CFG_DBAT2U (CFG_RIO_MEM_BASE | BATU_BL_512M | BATU_VS | BATU_VP) +#define CFG_IBAT2L (CFG_RIO_MEM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) +#define CFG_IBAT2U CFG_DBAT2U + +/* + * BAT3 4M Cache-inhibited, guarded + * 0xf800_0000 4M CCSR + */ +#define CFG_DBAT3L ( CFG_CCSRBAR | BATL_PP_RW \ + | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CFG_DBAT3U (CFG_CCSRBAR | BATU_BL_4M | BATU_VS | BATU_VP) +#define CFG_IBAT3L (CFG_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT) +#define CFG_IBAT3U CFG_DBAT3U + +/* + * BAT4 32M Cache-inhibited, guarded + * 0xe200_0000 16M PCI-Express 1 I/O + * 0xe300_0000 16M PCI-Express 2 I/0 + * Note that this is at 0xe0000000 + */ +#define CFG_DBAT4L ( CFG_PCI1_IO_BASE | BATL_PP_RW \ + | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CFG_DBAT4U (CFG_PCI1_IO_BASE | BATU_BL_32M | BATU_VS | BATU_VP) +#define CFG_IBAT4L (CFG_PCI1_IO_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) +#define CFG_IBAT4U CFG_DBAT4U + +/* + * BAT5 128K Cacheable, non-guarded + * 0xe401_0000 128K Init RAM for stack in the CPU DCache (no backing memory) + */ +#define CFG_DBAT5L (CFG_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE) +#define CFG_DBAT5U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) +#define CFG_IBAT5L CFG_DBAT5L +#define CFG_IBAT5U CFG_DBAT5U + +/* + * BAT6 32M Cache-inhibited, guarded + * 0xfe00_0000 32M FLASH + */ +#define CFG_DBAT6L ((CFG_FLASH_BASE & 0xfe000000) | BATL_PP_RW \ + | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CFG_DBAT6U ((CFG_FLASH_BASE & 0xfe000000) | BATU_BL_32M | BATU_VS | BATU_VP) +#define CFG_IBAT6L ((CFG_FLASH_BASE & 0xfe000000) | BATL_PP_RW | BATL_MEMCOHERENCE) +#define CFG_IBAT6U CFG_DBAT6U + +#define CFG_DBAT7L 0x00000000 +#define CFG_DBAT7U 0x00000000 +#define CFG_IBAT7L 0x00000000 +#define CFG_IBAT7U 0x00000000 + +/* + * Environment + */ +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000) +#define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ +#define CFG_ENV_SIZE 0x2000 + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +#include + #define CONFIG_CMD_PING + #define CONFIG_CMD_I2C + +#if defined(CONFIG_PCI) + #define CONFIG_CMD_PCI +#endif + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_LOAD_ADDR 0x2000000 /* default load address */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) + #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else + #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif + +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ +#define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ + +/* Cache Configuration */ +#define CFG_DCACHE_SIZE 32768 +#define CFG_CACHELINE_SIZE 32 +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/ +#endif + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif + +/* + * Environment Configuration + */ + +/* The mac addresses for all ethernet interface */ +#if defined(CONFIG_TSEC_ENET) +#define CONFIG_ETHADDR 02:E0:0C:00:00:01 +#define CONFIG_ETH1ADDR 02:E0:0C:00:01:FD +#define CONFIG_ETH2ADDR 02:E0:0C:00:02:FD +#define CONFIG_ETH3ADDR 02:E0:0C:00:03:FD +#endif + +#define CONFIG_HAS_ETH1 1 +#define CONFIG_HAS_ETH2 1 +#define CONFIG_HAS_ETH3 1 + +#define CONFIG_IPADDR 192.168.0.50 + +#define CONFIG_HOSTNAME sbc8641d +#define CONFIG_ROOTPATH /opt/eldk/ppc_74xx +#define CONFIG_BOOTFILE uImage + +#define CONFIG_SERVERIP 192.168.0.2 +#define CONFIG_GATEWAYIP 192.168.0.1 +#define CONFIG_NETMASK 255.255.255.0 + +/* default location for tftp and bootm */ +#define CONFIG_LOADADDR 1000000 + +#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ +#undef CONFIG_BOOTARGS /* the boot command will set bootargs */ + +#define CONFIG_BAUDRATE 115200 + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "consoledev=ttyS0\0" \ + "ramdiskaddr=2000000\0" \ + "ramdiskfile=uRamdisk\0" \ + "dtbaddr=400000\0" \ + "dtbfile=sbc8641d.dtb\0" \ + "en-wd=mw.b f8100010 0x08; echo -expect:- 08; md.b f8100010 1\0" \ + "dis-wd=mw.b f8100010 0x00; echo -expect:- 00; md.b f8100010 1\0" \ + "maxcpus=1" + +#define CONFIG_NFSBOOTCOMMAND \ + "setenv bootargs root=/dev/nfs rw " \ + "nfsroot=$serverip:$rootpath " \ + "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $dtbaddr $dtbfile;" \ + "bootm $loadaddr - $dtbaddr" + +#define CONFIG_RAMBOOTCOMMAND \ + "setenv bootargs root=/dev/ram rw " \ + "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $ramdiskaddr $ramdiskfile;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $dtbaddr $dtbfile;" \ + "bootm $loadaddr $ramdiskaddr $dtbaddr" + +#define CONFIG_FLASHBOOTCOMMAND \ + "setenv bootargs root=/dev/ram rw " \ + "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "bootm ffd00000 ffb00000 ffa00000" + +#define CONFIG_BOOTCOMMAND CONFIG_FLASHBOOTCOMMAND + +#endif /* __CONFIG_H */ From 273db7e1bdd1937e32f1d4507321bb721ebd3118 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Mon, 13 Aug 2007 09:05:33 +0200 Subject: [PATCH 084/259] ppc4xx: Fix problem in PLL clock calculation This patch was originall provided by David Mitchell and fixes a bug in the PLL clock calculation. Signed-off-by: Stefan Roese --- cpu/ppc4xx/serial.c | 9 +++++++-- cpu/ppc4xx/speed.c | 33 +++++++++++++++++---------------- include/ppc405.h | 2 ++ 3 files changed, 26 insertions(+), 18 deletions(-) diff --git a/cpu/ppc4xx/serial.c b/cpu/ppc4xx/serial.c index e62dd9dac..a75e5eebb 100644 --- a/cpu/ppc4xx/serial.c +++ b/cpu/ppc4xx/serial.c @@ -448,12 +448,17 @@ static void serial_divs (int baudrate, unsigned long *pudiv, unsigned long i; unsigned long est; /* current estimate */ unsigned long plloutb; + unsigned long cpr_pllc; u32 reg; + /* check the pll feedback source */ + mfcpr(cprpllc, cpr_pllc); + get_sys_info(&sysinfo); - plloutb = ((CONFIG_SYS_CLK_FREQ * sysinfo.pllFwdDiv * sysinfo.pllFbkDiv) - / sysinfo.pllFwdDivB); + plloutb = ((CONFIG_SYS_CLK_FREQ * ((cpr_pllc & PLLC_SRC_MASK) ? + sysinfo.pllFwdDivB : sysinfo.pllFwdDiv) * sysinfo.pllFbkDiv) / + sysinfo.pllFwdDivB); udiv = 256; /* Assume lowest possible serial clk */ div = plloutb / (16 * baudrate); /* total divisor */ umin = (plloutb / get_OPB_freq()) << 1; /* 2 x OPB divisor */ diff --git a/cpu/ppc4xx/speed.c b/cpu/ppc4xx/speed.c index 028b11af8..da5330a36 100644 --- a/cpu/ppc4xx/speed.c +++ b/cpu/ppc4xx/speed.c @@ -771,6 +771,7 @@ ulong get_PCI_freq (void) void get_sys_info (PPC405_SYS_INFO * sysInfo) { unsigned long cpr_plld; + unsigned long cpr_pllc; unsigned long cpr_primad; unsigned long sysClkPeriodPs = ONE_BILLION / (CONFIG_SYS_CLK_FREQ/1000); unsigned long primad_cpudv; @@ -780,6 +781,7 @@ void get_sys_info (PPC405_SYS_INFO * sysInfo) * Read PLL Mode registers */ mfcpr(cprplld, cpr_plld); + mfcpr(cprpllc, cpr_pllc); /* * Determine forward divider A @@ -787,20 +789,18 @@ void get_sys_info (PPC405_SYS_INFO * sysInfo) sysInfo->pllFwdDiv = ((cpr_plld & PLLD_FWDVA_MASK) >> 16); /* - * Determine forward divider B (should be equal to A) + * Determine forward divider B */ sysInfo->pllFwdDivB = ((cpr_plld & PLLD_FWDVB_MASK) >> 8); - if (sysInfo->pllFwdDivB == 0) { + if (sysInfo->pllFwdDivB == 0) sysInfo->pllFwdDivB = 8; - } /* * Determine FBK_DIV. */ sysInfo->pllFbkDiv = ((cpr_plld & PLLD_FBDV_MASK) >> 24); - if (sysInfo->pllFbkDiv == 0) { + if (sysInfo->pllFbkDiv == 0) sysInfo->pllFbkDiv = 256; - } /* * Read CPR_PRIMAD register @@ -810,30 +810,30 @@ void get_sys_info (PPC405_SYS_INFO * sysInfo) * Determine PLB_DIV. */ sysInfo->pllPlbDiv = ((cpr_primad & PRIMAD_PLBDV_MASK) >> 16); - if (sysInfo->pllPlbDiv == 0) { + if (sysInfo->pllPlbDiv == 0) sysInfo->pllPlbDiv = 16; - } /* * Determine EXTBUS_DIV. */ sysInfo->pllExtBusDiv = (cpr_primad & PRIMAD_EBCDV_MASK); - if (sysInfo->pllExtBusDiv == 0) { + if (sysInfo->pllExtBusDiv == 0) sysInfo->pllExtBusDiv = 16; - } /* * Determine OPB_DIV. */ sysInfo->pllOpbDiv = ((cpr_primad & PRIMAD_OPBDV_MASK) >> 8); - if (sysInfo->pllOpbDiv == 0) { + if (sysInfo->pllOpbDiv == 0) sysInfo->pllOpbDiv = 16; - } /* * Determine the M factor */ - m = sysInfo->pllFbkDiv * sysInfo->pllFwdDivB; + if (cpr_pllc & PLLC_SRC_MASK) + m = sysInfo->pllFbkDiv * sysInfo->pllFwdDivB; + else + m = sysInfo->pllFbkDiv * sysInfo->pllFwdDiv; /* * Determine VCO clock frequency @@ -845,16 +845,17 @@ void get_sys_info (PPC405_SYS_INFO * sysInfo) * Determine CPU clock frequency */ primad_cpudv = ((cpr_primad & PRIMAD_CPUDV_MASK) >> 24); - if (primad_cpudv == 0) { + if (primad_cpudv == 0) primad_cpudv = 16; - } - sysInfo->freqProcessor = (CONFIG_SYS_CLK_FREQ * sysInfo->pllFbkDiv) / primad_cpudv; + sysInfo->freqProcessor = (CONFIG_SYS_CLK_FREQ * m) / + sysInfo->pllFwdDiv / primad_cpudv; /* * Determine PLB clock frequency */ - sysInfo->freqPLB = (CONFIG_SYS_CLK_FREQ * sysInfo->pllFbkDiv) / sysInfo->pllPlbDiv; + sysInfo->freqPLB = (CONFIG_SYS_CLK_FREQ * m) / + sysInfo->pllFwdDiv / sysInfo->pllPlbDiv; } /******************************************** diff --git a/include/ppc405.h b/include/ppc405.h index 8e6473192..e4522e7cc 100644 --- a/include/ppc405.h +++ b/include/ppc405.h @@ -617,6 +617,8 @@ #define CPR_CLKUPD_ENDVCH_EN 0x20000000 /* Enable CPR Sys. Div. Changes */ #define CPR_PERD0_SPIDV_MASK 0x000F0000 /* SPI Clock Divider */ +#define PLLC_SRC_MASK 0x20000000 /* PLL feedback source */ + #define PLLD_FBDV_MASK 0x1F000000 /* PLL feedback divider value */ #define PLLD_FWDVA_MASK 0x000F0000 /* PLL forward divider A value */ #define PLLD_FWDVB_MASK 0x00000700 /* PLL forward divider B value */ From cca34967cbd13ff6bd352be29e3f1cc88ab24c05 Mon Sep 17 00:00:00 2001 From: Joe Hamman Date: Sat, 11 Aug 2007 06:54:58 -0500 Subject: [PATCH 085/259] Modify SBC8641D to use new Freescale PCI routines PCI-Express sockets 1 and 2 verified working with Intel Pro/1000 PT adapter. Signed-off-by: Joe Hamman Signde-off-by: Jon Loeliger --- board/sbc8641d/sbc8641d.c | 156 ++++++++++++++++++++++++++++--------- include/configs/sbc8641d.h | 9 ++- 2 files changed, 125 insertions(+), 40 deletions(-) diff --git a/board/sbc8641d/sbc8641d.c b/board/sbc8641d/sbc8641d.c index e5dd5509c..7adc42fae 100644 --- a/board/sbc8641d/sbc8641d.c +++ b/board/sbc8641d/sbc8641d.c @@ -33,6 +33,7 @@ #include #include #include +#include #include #if defined(CONFIG_OF_FLAT_TREE) @@ -60,36 +61,6 @@ int checkboard (void) { puts ("Board: Wind River SBC8641D\n"); -#ifdef CONFIG_PCI - - volatile immap_t *immap = (immap_t *) CFG_CCSRBAR; - volatile ccsr_gur_t *gur = &immap->im_gur; - volatile ccsr_pex_t *pex1 = &immap->im_pex1; - - uint devdisr = gur->devdisr; - uint io_sel = (gur->pordevsr & MPC86xx_PORDEVSR_IO_SEL) >> 16; - uint host1_agent = (gur->porbmsr & MPC86xx_PORBMSR_HA) >> 17; - uint pex1_agent = (host1_agent == 0) || (host1_agent == 1); - - if ((io_sel == 2 || io_sel == 3 || io_sel == 5 - || io_sel == 6 || io_sel == 7 || io_sel == 0xF) - && !(devdisr & MPC86xx_DEVDISR_PCIEX1)) { - debug ("PCI-EXPRESS 1: %s \n", pex1_agent ? "Agent" : "Host"); - debug ("0x%08x=0x%08x ", &pex1->pme_msg_det, pex1->pme_msg_det); - if (pex1->pme_msg_det) { - pex1->pme_msg_det = 0xffffffff; - debug (" with errors. Clearing. Now 0x%08x", - pex1->pme_msg_det); - } - debug ("\n"); - } else { - puts ("PCI-EXPRESS 1: Disabled in hardware\n"); - } - -#else - puts ("PCI-EXPRESS1: Disabled in configuration\n"); -#endif - return 0; } @@ -244,21 +215,130 @@ static struct pci_config_table pci_fsl86xxads_config_table[] = { }; #endif -static struct pci_controller hose = { +static struct pci_controller pci1_hose = { #ifndef CONFIG_PCI_PNP - config_table:pci_mpc86xxcts_config_table, + config_table:pci_mpc86xxcts_config_table #endif }; +#endif /* CONFIG_PCI */ -#endif /* CONFIG_PCI */ +#ifdef CONFIG_PCI2 +static struct pci_controller pci2_hose; +#endif /* CONFIG_PCI2 */ -void pci_init_board (void) +int first_free_busno = 0; + +void pci_init_board(void) { -#ifdef CONFIG_PCI - extern void pci_mpc86xx_init (struct pci_controller *hose); + volatile immap_t *immap = (immap_t *) CFG_CCSRBAR; + volatile ccsr_gur_t *gur = &immap->im_gur; + uint devdisr = gur->devdisr; + uint io_sel = (gur->pordevsr & MPC86xx_PORDEVSR_IO_SEL) >> 16; + +#ifdef CONFIG_PCI1 +{ + volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCI1_ADDR; + extern void fsl_pci_init(struct pci_controller *hose); + struct pci_controller *hose = &pci1_hose; +#ifdef DEBUG + uint host1_agent = (gur->porbmsr & MPC86xx_PORBMSR_HA) >> 17; + uint pex1_agent = (host1_agent == 0) || (host1_agent == 1); +#endif + if ((io_sel == 2 || io_sel == 3 || io_sel == 5 + || io_sel == 6 || io_sel == 7 || io_sel == 0xF) + && !(devdisr & MPC86xx_DEVDISR_PCIEX1)) { + debug("PCI-EXPRESS 1: %s \n", pex1_agent ? "Agent" : "Host"); + debug("0x%08x=0x%08x ", &pci->pme_msg_det, pci->pme_msg_det); + if (pci->pme_msg_det) { + pci->pme_msg_det = 0xffffffff; + debug(" with errors. Clearing. Now 0x%08x", + pci->pme_msg_det); + } + debug("\n"); + + /* inbound */ + pci_set_region(hose->regions + 0, + CFG_PCI_MEMORY_BUS, + CFG_PCI_MEMORY_PHYS, + CFG_PCI_MEMORY_SIZE, + PCI_REGION_MEM | PCI_REGION_MEMORY); + + /* outbound memory */ + pci_set_region(hose->regions + 1, + CFG_PCI1_MEM_BASE, + CFG_PCI1_MEM_PHYS, + CFG_PCI1_MEM_SIZE, + PCI_REGION_MEM); + + /* outbound io */ + pci_set_region(hose->regions + 2, + CFG_PCI1_IO_BASE, + CFG_PCI1_IO_PHYS, + CFG_PCI1_IO_SIZE, + PCI_REGION_IO); + + hose->region_count = 3; + + hose->first_busno=first_free_busno; + pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); + + fsl_pci_init(hose); + + first_free_busno=hose->last_busno+1; + printf (" PCI-EXPRESS 1 on bus %02x - %02x\n", + hose->first_busno,hose->last_busno); + + } else { + puts("PCI-EXPRESS 1: Disabled\n"); + } +} +#else + puts("PCI-EXPRESS1: Disabled\n"); +#endif /* CONFIG_PCI1 */ + +#ifdef CONFIG_PCI2 +{ + volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCI2_ADDR; + extern void fsl_pci_init(struct pci_controller *hose); + struct pci_controller *hose = &pci2_hose; + + + /* inbound */ + pci_set_region(hose->regions + 0, + CFG_PCI_MEMORY_BUS, + CFG_PCI_MEMORY_PHYS, + CFG_PCI_MEMORY_SIZE, + PCI_REGION_MEM | PCI_REGION_MEMORY); + + /* outbound memory */ + pci_set_region(hose->regions + 1, + CFG_PCI2_MEM_BASE, + CFG_PCI2_MEM_PHYS, + CFG_PCI2_MEM_SIZE, + PCI_REGION_MEM); + + /* outbound io */ + pci_set_region(hose->regions + 2, + CFG_PCI2_IO_BASE, + CFG_PCI2_IO_PHYS, + CFG_PCI2_IO_SIZE, + PCI_REGION_IO); + + hose->region_count = 3; + + hose->first_busno=first_free_busno; + pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); + + fsl_pci_init(hose); + + first_free_busno=hose->last_busno+1; + printf (" PCI-EXPRESS 2 on bus %02x - %02x\n", + hose->first_busno,hose->last_busno); +} +#else + puts("PCI-EXPRESS 2: Disabled\n"); +#endif /* CONFIG_PCI2 */ - pci_mpc86xx_init (&hose); -#endif /* CONFIG_PCI */ } #if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP) diff --git a/include/configs/sbc8641d.h b/include/configs/sbc8641d.h index dba19441c..68d31ca1d 100644 --- a/include/configs/sbc8641d.h +++ b/include/configs/sbc8641d.h @@ -49,8 +49,10 @@ #define CFG_RESET_ADDRESS 0xfff00100 -#undef CONFIG_PCI -#define CONFIG_FSL_PCI_INIT 1 +#define CONFIG_PCI 1 /* Enable PCIE */ +#define CONFIG_PCI1 1 /* PCIE controler 1 (slot 1) */ +#define CONFIG_PCI2 1 /* PCIE controler 2 (slot 2) */ +#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ #define CONFIG_TSEC_ENET /* tsec ethernet support */ #define CONFIG_ENV_OVERWRITE @@ -95,6 +97,9 @@ #define CFG_CCSRBAR 0xf8000000 /* relocated CCSRBAR */ #define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ +#define CFG_PCI1_ADDR (CFG_CCSRBAR+0x8000) +#define CFG_PCI2_ADDR (CFG_CCSRBAR+0x9000) + /* * DDR Setup */ From be5d72d10d47609326226225181e301fb9a33b58 Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Mon, 13 Aug 2007 21:57:53 +0200 Subject: [PATCH 086/259] Minor coding style cleanup. Update CHANGELOG. Signed-off-by: Wolfgang Denk --- CHANGELOG | 74 +++++++++++++++++++++++++++++++++++++ board/cm5200/cm5200.c | 6 +-- board/cm5200/cm5200.h | 2 +- board/cm5200/cmd_cm5200.c | 2 +- doc/README.generic_usb_ohci | 5 +-- drivers/nand/nand_util.c | 10 ++--- drivers/usb_ohci.c | 11 ------ include/configs/cm5200.h | 21 +---------- libfdt/fdt_ro.c | 1 - 9 files changed, 86 insertions(+), 46 deletions(-) diff --git a/CHANGELOG b/CHANGELOG index 1228908a5..57299b65f 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -1,3 +1,53 @@ +commit a08458303e7f9db67f296980036d3292c35cb45c +Author: Haavard Skinnemoen +Date: Fri Jun 29 18:38:51 2007 +0200 + + atmel_mci: Fix data timeout value + + Calculate the data timeout based on values from the CSD instead of + just using a hardcoded DTOR value. This is a backport of a similar fix + in BSP 2.0, with one additional fix: the DTOCYC value is rounded up + instead of down. + + Signed-off-by: Haavard Skinnemoen + +commit 0ba8eed28b575626b17e0a7882f923b83e0d7584 +Author: Haavard Skinnemoen +Date: Mon Aug 13 17:22:31 2007 +0200 + + AVR32: Include instead of + + include/asm-avr32/div64.h was recently moved to include/div64.h, but + cpu/at32ap/interrupts.c wasn't properly updated (an earlier version of + the patch was merged perhaps?) + + This patch updates cpu/at32ap/interrupts.c so that the avr32 port + compiles again. + + Signed-off-by: Haavard Skinnemoen + +commit f0d1246ed7cb5a88522244c596d7ae7e6f161283 +Author: Haavard Skinnemoen +Date: Wed Jun 27 13:34:26 2007 +0200 + + atmel_mci: Use 512 byte blocksize if possible + + Instead of always using the largest blocksize the card supports, check + if it can support smaller block sizes and use 512 bytes if possible. + Most cards do support this, and other parts of u-boot seem to have + trouble with block sizes different from 512 bytes. + + Also enable underrun/overrun protection. + + Signed-off-by: Haavard Skinnemoen + Acked-by: Hans-Christian Egtvedt + +commit 9986bc3e40e899bea372a99a2bca4071bdf2e24b +Author: Wolfgang Denk +Date: Sun Aug 12 21:34:50 2007 +0200 + + Update CHANGELOG + commit 77d19a8bf3b0b1e401cb9f23c81e2ef419705c1a Author: Wolfgang Denk Date: Sun Aug 12 21:34:34 2007 +0200 @@ -3928,6 +3978,30 @@ Date: Fri Jan 5 09:15:34 2007 +0100 Signed-off-by Dan Malek, +commit f2134f8e9eb006bdcd729e89f309c07b2fa45180 +Author: Haavard Skinnemoen +Date: Wed May 2 13:31:53 2007 +0200 + + macb: Don't restart autonegotiation if we already have link + + Rework macb_phy_init so that it doesn't attempt to re-negotiate if the + link is already up. + + Signed-off-by: Haavard Skinnemoen + +commit 04fcb5d38bc90779cd9a710d60702075986f0e29 +Author: Haavard Skinnemoen +Date: Wed May 2 13:22:38 2007 +0200 + + macb: Introduce a few barriers when dealing with DMA descriptors + + There were a few theoretical possibilities that the compiler might + optimize away DMA descriptor reads and/or writes and thus cause + synchronization problems with the hardware. Insert barriers where + we depend on reads/writes actually hitting memory. + + Signed-off-by: Haavard Skinnemoen + commit ffa621a0d12a1ccd81c936c567f8917a213787a8 Author: Andy Fleming Date: Sat Feb 24 01:08:13 2007 -0600 diff --git a/board/cm5200/cm5200.c b/board/cm5200/cm5200.c index 6804e33c2..b74ac08bc 100644 --- a/board/cm5200/cm5200.c +++ b/board/cm5200/cm5200.c @@ -122,7 +122,7 @@ long int initdram(int board_type) mem_conf_t *mem_conf; mem_conf = get_mem_config(board_type); - + /* configure SDRAM start/end for detection */ *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001e; /* 2G at 0x0 */ @@ -303,7 +303,7 @@ int checkboard(void) hw_id_t hw_id_tmp; char module_name_tmp[MODULE_NAME_MAXLEN] = ""; - /* + /* * We need I2C to access HW ID data from EEPROM, so we call i2c_init() * here despite the fact that it will be called again later on. We * also use a little trick to silence I2C-related output. @@ -321,7 +321,7 @@ int checkboard(void) else printf("Board: unrecognized cm5200 module (%s)\n", module_name_tmp); - + return 0; } diff --git a/board/cm5200/cm5200.h b/board/cm5200/cm5200.h index a6cbc88f4..b2ea5ce0d 100644 --- a/board/cm5200/cm5200.h +++ b/board/cm5200/cm5200.h @@ -138,7 +138,7 @@ static char **hw_id_list[] = { cmu1_qa_hw_id, }; -/* indices to the above list - keep in sync */ +/* indices to the above list - keep in sync */ enum { CM1_QA, CM11_QA, diff --git a/board/cm5200/cmd_cm5200.c b/board/cm5200/cmd_cm5200.c index fd9b914ae..513c36553 100644 --- a/board/cm5200/cmd_cm5200.c +++ b/board/cm5200/cmd_cm5200.c @@ -1,7 +1,7 @@ /* * (C) Copyright 2007 Markus Kappeler * - * Adapted for U-Boot 1.2 by Piotr Kruszynski + * Adapted for U-Boot 1.2 by Piotr Kruszynski * * See file CREDITS for list of people who contributed to this * project. diff --git a/doc/README.generic_usb_ohci b/doc/README.generic_usb_ohci index c343dfdf9..494dd1f5d 100644 --- a/doc/README.generic_usb_ohci +++ b/doc/README.generic_usb_ohci @@ -41,7 +41,7 @@ mpc5xxx. For these the config option CFG_OHCI_BE_CONTROLLER -needs to be defined. +needs to be defined. PCI Controllers @@ -55,6 +55,3 @@ PCI Controllers need to do byte swapping on register accesses, so they should to define: CFG_OHCI_SWAP_REG_ACCESS - - - diff --git a/drivers/nand/nand_util.c b/drivers/nand/nand_util.c index aee872703..cf05043c0 100644 --- a/drivers/nand/nand_util.c +++ b/drivers/nand/nand_util.c @@ -209,7 +209,7 @@ int nand_erase_opts(nand_info_t *meminfo, const nand_erase_options_t *opts) } if (!opts->quiet) { - unsigned long long n =(unsigned long long) + unsigned long long n =(unsigned long long) (erase.addr+meminfo->erasesize-opts->offset) * 100; int percent = (int)do_div(n, erase_length); @@ -476,8 +476,8 @@ int nand_write_opts(nand_info_t *meminfo, const nand_write_options_t *opts) imglen -= readlen; if (!opts->quiet) { - unsigned long long n = (unsigned long long) - (opts->length-imglen) * 100; + unsigned long long n = (unsigned long long) + (opts->length-imglen) * 100; int percent = (int)do_div(n, opts->length); /* output progress message only at whole percent * steps to reduce the number of messages printed @@ -651,8 +651,8 @@ int nand_read_opts(nand_info_t *meminfo, const nand_read_options_t *opts) } if (!opts->quiet) { - unsigned long long n = (unsigned long long) - (opts->length-imglen) * 100; + unsigned long long n = (unsigned long long) + (opts->length-imglen) * 100; int percent = (int)do_div(n ,opts->length); /* output progress message only at whole percent * steps to reduce the number of messages printed diff --git a/drivers/usb_ohci.c b/drivers/usb_ohci.c index d6b745fad..f0a37b20a 100644 --- a/drivers/usb_ohci.c +++ b/drivers/usb_ohci.c @@ -132,8 +132,6 @@ int got_rhsc; /* device which was disconnected */ struct usb_device *devgone; - - /*-------------------------------------------------------------------------*/ /* AMD-756 (D2 rev) reports corrupt register contents in some cases. @@ -157,7 +155,6 @@ static inline u32 roothub_status (struct ohci *hc) static u32 roothub_portstatus (struct ohci *hc, int i) { return read_roothub (hc, portstatus [i], 0xffe0fce0); } - /* forward declaration */ static int hc_interrupt (void); static void @@ -412,8 +409,6 @@ static void ohci_dump (ohci_t *controller, int verbose) ep_print_int_eds (controller, "hcca"); dbg ("hcca frame #%04x", controller->hcca->frame_no); ohci_dump_roothub (controller, 1); -} - #endif /* DEBUG */ @@ -701,7 +696,6 @@ static void periodic_unlink ( struct ohci *ohci, volatile struct ed *ed, } } - /* unlink an ed from one of the HC chains. * just the link to the ed is unlinked. * the link from the ed still points to another operational ed or 0 @@ -759,7 +753,6 @@ static int ep_unlink (ohci_t *ohci, ed_t *edi) return 0; } - /*-------------------------------------------------------------------------*/ /* add/reinit an endpoint; this should be done once at the @@ -939,7 +932,6 @@ static void td_submit_job (struct usb_device *dev, unsigned long pipe, void *buf * Done List handling functions *-------------------------------------------------------------------------*/ - /* calculate the transfer length and update the urb */ static void dl_transfer_length(td_t * td) @@ -951,7 +943,6 @@ static void dl_transfer_length(td_t * td) tdBE = m32_swap (td->hwBE); tdCBP = m32_swap (td->hwCBP); - if (!(usb_pipetype (lurb_priv->pipe) == PIPE_CONTROL && ((td->index == 0) || (td->index == lurb_priv->length - 1)))) { if (tdBE != 0) { @@ -1094,7 +1085,6 @@ static __u8 root_hub_dev_des[] = 0x01 /* __u8 bNumConfigurations; */ }; - /* Configuration descriptor */ static __u8 root_hub_config_des[] = { @@ -1172,7 +1162,6 @@ static unsigned char root_hub_str_index1[] = /* Hub class-specific descriptor is constructed dynamically */ - /*-------------------------------------------------------------------------*/ #define OK(x) len = (x); break diff --git a/include/configs/cm5200.h b/include/configs/cm5200.h index 56c0ecb4d..d55434802 100644 --- a/include/configs/cm5200.h +++ b/include/configs/cm5200.h @@ -31,7 +31,6 @@ #define CONFIG_MPC5200 1 /* (more precisely an MPC5200 CPU) */ #define CONFIG_CM5200 1 /* ... on CM5200 platform */ - /* * Supported commands */ @@ -60,7 +59,6 @@ #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } #define CONFIG_SILENT_CONSOLE 1 /* needed to silence i2c_init() */ - /* * Ethernet configuration */ @@ -71,7 +69,6 @@ #define CONFIG_MISC_INIT_R 1 #define CONFIG_MAC_OFFSET 0x35 /* MAC address offset in I2C EEPROM */ - /* * POST support */ @@ -80,11 +77,9 @@ /* List of I2C addresses to be verified by POST */ #define I2C_ADDR_LIST { CFG_I2C_SLAVE, CFG_I2C_IO, CFG_I2C_EEPROM } - /* display image timestamps */ #define CONFIG_TIMESTAMP 1 - /* * Autobooting */ @@ -137,19 +132,16 @@ "" #define CONFIG_BOOTCOMMAND "run flash_flash" - /* * Low level configuration */ - /* * Clock configuration */ #define CFG_MPC5XXX_CLKIN 33000000 /* SYS_XTAL_IN = 33MHz */ #define CFG_IPBCLK_EQUALS_XLBCLK 1 /* IPB = 133MHz */ - /* * Memory map */ @@ -184,7 +176,7 @@ */ #define CFG_FLASH_CFI 1 #define CFG_FLASH_CFI_DRIVER 1 -#define CFG_FLASH_BASE 0xfc000000 +#define CFG_FLASH_BASE 0xfc000000 /* we need these despite using CFI */ #define CFG_MAX_FLASH_BANKS 1 /* max num of flash banks */ #define CFG_MAX_FLASH_SECT 256 /* max num of sectors on one chip */ @@ -215,7 +207,6 @@ #define CFG_CS_BURST 0x00000000 #define CFG_CS_DEADCYCLE 0x00000001 - /* * SDRAM configuration * settings for k4s561632E-xx75, assuming XLB = 132 MHz @@ -225,8 +216,6 @@ #define SDRAM_CONFIG1 0xE2333900 #define SDRAM_CONFIG2 0x8EE70000 - - /* * MTD configuration */ @@ -238,7 +227,6 @@ "2m(kernel),27904k(rootfs)," \ "-(config)" - /* * I2C configuration */ @@ -249,13 +237,11 @@ #define CFG_I2C_IO 0x38 /* PCA9554AD I2C I/O port address */ #define CFG_I2C_EEPROM 0x53 /* I2C EEPROM device address */ - /* * RTC configuration */ #define CONFIG_RTC_MPC5200 1 /* use internal MPC5200 RTC */ - /* * USB configuration */ @@ -284,7 +270,6 @@ #define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR + CFG_ENV_SECT_SIZE) #define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) - /* * Pin multiplexing configuration */ @@ -302,7 +287,6 @@ */ #define CFG_GPS_PORT_CONFIG 0x10559C44 - /* * Miscellaneous configurable options */ @@ -322,7 +306,6 @@ #define CFG_LOAD_ADDR 0x100000 /* default load address */ #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - /* * Various low-level settings */ @@ -334,7 +317,6 @@ #define CFG_XLB_PIPELINING 1 /* enable transaction pipeling */ - /* * Cache Configuration */ @@ -343,7 +325,6 @@ #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ #endif - /* * Flat Device Tree support */ diff --git a/libfdt/fdt_ro.c b/libfdt/fdt_ro.c index ffd9209b1..46d525db1 100644 --- a/libfdt/fdt_ro.c +++ b/libfdt/fdt_ro.c @@ -534,4 +534,3 @@ int fdt_get_reservemap(void *fdt, int n, struct fdt_reserve_entry *re) } #endif /* CONFIG_OF_LIBFDT */ - From 50cca8b976ec74069860208c36e64ce8f4d5e4c1 Mon Sep 17 00:00:00 2001 From: Mike Rapoport Date: Sun, 12 Aug 2007 08:48:27 +0300 Subject: [PATCH 087/259] Add ability to take MAC address from the environment to DM9000 driver Signed-off-by: Mike Rapoport Signed-off-by: Ben Warren --- drivers/dm9000x.c | 15 +++++++++++++++ include/net.h | 23 +++++++++++++++++++++++ 2 files changed, 38 insertions(+) diff --git a/drivers/dm9000x.c b/drivers/dm9000x.c index 687707627..78acb097e 100644 --- a/drivers/dm9000x.c +++ b/drivers/dm9000x.c @@ -302,6 +302,21 @@ eth_init(bd_t * bd) /* Set Node address */ for (i = 0; i < 6; i++) ((u16 *) bd->bi_enetaddr)[i] = read_srom_word(i); + + if (!is_zero_ether_addr(bd->bi_enetaddr) && + !is_mutlicast_ether_addr(bd->bi_enetaddr)) { + /* try reading from environment */ + u8 i; + char *s, *e; + s = getenv ("ethaddr"); + for (i = 0; i < 6; ++i) { + bd->bi_enetaddr[i] = s ? + simple_strtoul (s, &e, 16) : 0; + if (s) + s = (*e) ? e + 1 : e; + } + } + printf("MAC: %02x:%02x:%02x:%02x:%02x:%02x\n", bd->bi_enetaddr[0], bd->bi_enetaddr[1], bd->bi_enetaddr[2], bd->bi_enetaddr[3], bd->bi_enetaddr[4], bd->bi_enetaddr[5]); diff --git a/include/net.h b/include/net.h index 967194800..aa58e333a 100644 --- a/include/net.h +++ b/include/net.h @@ -435,6 +435,29 @@ static inline void NetCopyLong(ulong *to, ulong *from) memcpy((void*)to, (void*)from, sizeof(ulong)); } +/** + * is_zero_ether_addr - Determine if give Ethernet address is all zeros. + * @addr: Pointer to a six-byte array containing the Ethernet address + * + * Return true if the address is all zeroes. + */ +static inline int is_zero_ether_addr(const u8 *addr) +{ + return !(addr[0] | addr[1] | addr[2] | addr[3] | addr[4] | addr[5]); +} + +/** + * is_multicast_ether_addr - Determine if the Ethernet address is a multicast. + * @addr: Pointer to a six-byte array containing the Ethernet address + * + * Return true if the address is a multicast address. + * By definition the broadcast address is also a multicast address. + */ +static inline int is_multicast_ether_addr(const u8 *addr) +{ + return (0x01 & addr[0]); +} + /* Convert an IP address to a string */ extern void ip_to_string (IPaddr_t x, char *s); From 5d110f0aa69f065ee386ec1840dfee1e8cc46bc1 Mon Sep 17 00:00:00 2001 From: Wilson Callan Date: Sat, 28 Jul 2007 10:56:13 -0400 Subject: [PATCH 088/259] New CONFIG_BOOTP_SERVERIP option Added CONFIG_BOOTP_SERVERIP to allow the tftp server to be different from the bootp server Signed-off-by: Wilson Callan Signed-off-by: Ben Warren --- README | 5 ++++- net/bootp.c | 2 ++ 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/README b/README index 398ea7e79..6af6aaa02 100644 --- a/README +++ b/README @@ -1102,6 +1102,9 @@ The following options need to be configured: CONFIG_BOOTP_TIMEOFFSET CONFIG_BOOTP_VENDOREX + CONFIG_BOOTP_SERVERIP - TFTP server will be the serverip + environment variable, not the BOOTP server. + CONFIG_BOOTP_DNS2 - If a DHCP client requests the DNS serverip from a DHCP server, it is possible that more than one DNS serverip is offered to the client. @@ -1114,7 +1117,7 @@ The following options need to be configured: CONFIG_BOOTP_SEND_HOSTNAME - Some DHCP servers are capable to do a dynamic update of a DNS server. To do this, they need the hostname of the DHCP requester. - If CONFIG_BOOP_SEND_HOSTNAME is defined, the content + If CONFIG_BOOTP_SEND_HOSTNAME is defined, the content of the "hostname" environment variable is passed as option 12 to the DHCP server. diff --git a/net/bootp.c b/net/bootp.c index 80f53bc88..be1ee332a 100644 --- a/net/bootp.c +++ b/net/bootp.c @@ -120,10 +120,12 @@ static void BootpCopyNetParams(Bootp_t *bp) IPaddr_t tmp_ip; NetCopyIP(&NetOurIP, &bp->bp_yiaddr); +#if !defined(CONFIG_BOOTP_SERVERIP) NetCopyIP(&tmp_ip, &bp->bp_siaddr); if (tmp_ip != 0) NetCopyIP(&NetServerIP, &bp->bp_siaddr); memcpy (NetServerEther, ((Ethernet_t *)NetRxPkt)->et_src, 6); +#endif if (strlen(bp->bp_file) > 0) copy_filename (BootFile, bp->bp_file, sizeof(BootFile)); From 53a5c424bf8655b7b4e2c305a441963259a26a81 Mon Sep 17 00:00:00 2001 From: David Updegraff Date: Mon, 11 Jun 2007 10:41:07 -0500 Subject: [PATCH 089/259] multicast tftp: RFC2090 Implemented IETF RFC2090, Multicast TFTP. Initial implementation on Realtek RTL8139 and Freescale TSEC. Signed-off-by: David Updegraff Signed-off-by: Ben Warren --- README | 10 ++ drivers/rtl8139.c | 7 ++ drivers/tsec.c | 48 ++++++++++ include/net.h | 11 ++- net/eth.c | 45 +++++++++ net/net.c | 8 ++ net/tftp.c | 238 +++++++++++++++++++++++++++++++++++++++++++++- 7 files changed, 360 insertions(+), 7 deletions(-) diff --git a/README b/README index 6af6aaa02..291b30468 100644 --- a/README +++ b/README @@ -1066,6 +1066,16 @@ The following options need to be configured: Defines a default value for theIP address of a TFTP server to contact when using the "tftboot" command. +- Multicast TFTP Mode: + CONFIG_MCAST_TFTP + + Defines whether you want to support multicast TFTP as per + rfc-2090; for example to work with atftp. Lets lots of targets + tftp down the same boot image concurrently. Note: the ethernet + driver in use must provide a function: mcast() to join/leave a + multicast group. + + CONFIG_BOOTP_RANDOM_DELAY - BOOTP Recovery Mode: CONFIG_BOOTP_RANDOM_DELAY diff --git a/drivers/rtl8139.c b/drivers/rtl8139.c index 9045523a3..3e259b6b1 100644 --- a/drivers/rtl8139.c +++ b/drivers/rtl8139.c @@ -193,6 +193,10 @@ static void rtl_reset(struct eth_device *dev); static int rtl_transmit(struct eth_device *dev, volatile void *packet, int length); static int rtl_poll(struct eth_device *dev); static void rtl_disable(struct eth_device *dev); +#ifdef CONFIG_MCAST_TFTP/* This driver already accepts all b/mcast */ +static int rtl_bcast_addr (struct eth_device *dev, u8 bcast_mac, u8 set) + { return (0); } +#endif static struct pci_device_id supported[] = { {PCI_VENDOR_ID_REALTEK, PCI_DEVICE_ID_REALTEK_8139}, @@ -228,6 +232,9 @@ int rtl8139_initialize(bd_t *bis) dev->halt = rtl_disable; dev->send = rtl_transmit; dev->recv = rtl_poll; +#ifdef CONFIG_MCAST_TFTP + dev->mcast = rtl_bcast_addr; +#endif eth_register (dev); diff --git a/drivers/tsec.c b/drivers/tsec.c index c01112349..fd21ed4ed 100644 --- a/drivers/tsec.c +++ b/drivers/tsec.c @@ -129,6 +129,9 @@ static int tsec_miiphy_write(char *devname, unsigned char addr, unsigned char reg, unsigned short value); static int tsec_miiphy_read(char *devname, unsigned char addr, unsigned char reg, unsigned short *value); +#ifdef CONFIG_MCAST_TFTP +static int tsec_mcast_addr (struct eth_device *dev, u8 mcast_mac, u8 set); +#endif /* Initialize device structure. Returns success if PHY * initialization succeeded (i.e. if it recognizes the PHY) @@ -167,6 +170,9 @@ int tsec_initialize(bd_t * bis, int index, char *devname) dev->halt = tsec_halt; dev->send = tsec_send; dev->recv = tsec_recv; +#ifdef CONFIG_MCAST_TFTP + dev->mcast = tsec_mcast_addr; +#endif /* Tell u-boot to get the addr from the env */ for (i = 0; i < 6; i++) @@ -1539,4 +1545,46 @@ static int tsec_miiphy_write(char *devname, unsigned char addr, #endif +#ifdef CONFIG_MCAST_TFTP + +/* CREDITS: linux gianfar driver, slightly adjusted... thanx. */ + +/* Set the appropriate hash bit for the given addr */ + +/* The algorithm works like so: + * 1) Take the Destination Address (ie the multicast address), and + * do a CRC on it (little endian), and reverse the bits of the + * result. + * 2) Use the 8 most significant bits as a hash into a 256-entry + * table. The table is controlled through 8 32-bit registers: + * gaddr0-7. gaddr0's MSB is entry 0, and gaddr7's LSB is + * gaddr7. This means that the 3 most significant bits in the + * hash index which gaddr register to use, and the 5 other bits + * indicate which bit (assuming an IBM numbering scheme, which + * for PowerPC (tm) is usually the case) in the tregister holds + * the entry. */ +static int +tsec_mcast_addr (struct eth_device *dev, u8 mcast_mac, u8 set) +{ + struct tsec_private *priv = privlist[1]; + volatile tsec_t *regs = priv->regs; + volatile u32 *reg_array, value; + u8 result, whichbit, whichreg; + + result = (u8)((ether_crc(MAC_ADDR_LEN,mcast_mac) >> 24) & 0xff); + whichbit = result & 0x1f; /* the 5 LSB = which bit to set */ + whichreg = result >> 5; /* the 3 MSB = which reg to set it in */ + value = (1 << (31-whichbit)); + + reg_array = &(regs->hash.gaddr0); + + if (set) { + reg_array[whichreg] |= value; + } else { + reg_array[whichreg] &= ~value; + } + return 0; +} +#endif /* Multicast TFTP ? */ + #endif /* CONFIG_TSEC_ENET */ diff --git a/include/net.h b/include/net.h index aa58e333a..603452ab3 100644 --- a/include/net.h +++ b/include/net.h @@ -99,10 +99,12 @@ struct eth_device { int state; int (*init) (struct eth_device*, bd_t*); - int (*send) (struct eth_device*, volatile void* pachet, int length); + int (*send) (struct eth_device*, volatile void* packet, int length); int (*recv) (struct eth_device*); void (*halt) (struct eth_device*); - +#ifdef CONFIG_MCAST_TFTP + int (*mcast) (struct eth_device*, u32 ip, u8 set); +#endif struct eth_device *next; void *priv; }; @@ -124,6 +126,11 @@ extern int eth_rx(void); /* Check for received packets */ extern void eth_halt(void); /* stop SCC */ extern char *eth_get_name(void); /* get name of current device */ +#ifdef CONFIG_MCAST_TFTP +int eth_mcast_join( IPaddr_t mcast_addr, u8 join); +u32 ether_crc (size_t len, unsigned char const *p); +#endif + /**********************************************************************/ /* diff --git a/net/eth.c b/net/eth.c index c8f92a526..9ccbccac0 100644 --- a/net/eth.c +++ b/net/eth.c @@ -353,6 +353,51 @@ void eth_set_enetaddr(int num, char *addr) { memcpy(dev->enetaddr, enetaddr, 6); } +#ifdef CONFIG_MCAST_TFTP +/* Multicast. + * mcast_addr: multicast ipaddr from which multicast Mac is made + * join: 1=join, 0=leave. + */ +int eth_mcast_join( IPaddr_t mcast_ip, u8 join) +{ + u8 mcast_mac[6]; + if (!eth_current || !eth_current->mcast) + return -1; + mcast_mac[5] = htonl(mcast_ip) & 0xff; + mcast_mac[4] = (htonl(mcast_ip)>>8) & 0xff; + mcast_mac[3] = (htonl(mcast_ip)>>16) & 0x7f; + mcast_mac[2] = 0x5e; + mcast_mac[1] = 0x0; + mcast_mac[0] = 0x1; + return eth_current->mcast(eth_current, mcast_mac, join); +} + +/* the 'way' for ethernet-CRC-32. Spliced in from Linux lib/crc32.c + * and this is the ethernet-crc method needed for TSEC -- and perhaps + * some other adapter -- hash tables + */ +#define CRCPOLY_LE 0xedb88320 +u32 ether_crc (size_t len, unsigned char const *p) +{ + int i; + u32 crc; + crc = ~0; + while (len--) { + crc ^= *p++; + for (i = 0; i < 8; i++) + crc = (crc >> 1) ^ ((crc & 1) ? CRCPOLY_LE : 0); + } + /* an reverse the bits, cuz of way they arrive -- last-first */ + crc = (crc >> 16) | (crc << 16); + crc = (crc >> 8 & 0x00ff00ff) | (crc << 8 & 0xff00ff00); + crc = (crc >> 4 & 0x0f0f0f0f) | (crc << 4 & 0xf0f0f0f0); + crc = (crc >> 2 & 0x33333333) | (crc << 2 & 0xcccccccc); + crc = (crc >> 1 & 0x55555555) | (crc << 1 & 0xaaaaaaaa); + return crc; +} + +#endif + int eth_init(bd_t *bis) { diff --git a/net/net.c b/net/net.c index e9d775764..2b11a1365 100644 --- a/net/net.c +++ b/net/net.c @@ -118,6 +118,10 @@ char NetOurHostName[32]={0,}; /* Our hostname */ char NetOurRootPath[64]={0,}; /* Our bootpath */ ushort NetBootFileSize=0; /* Our bootfile size in blocks */ +#ifdef CONFIG_MCAST_TFTP /* Multicast TFTP */ +IPaddr_t Mcast_addr; +#endif + /** END OF BOOTP EXTENTIONS **/ ulong NetBootFileXferSize; /* The actual transferred size of the bootfile (in bytes) */ @@ -1386,6 +1390,9 @@ NetReceive(volatile uchar * inpkt, int len) } tmp = NetReadIP(&ip->ip_dst); if (NetOurIP && tmp != NetOurIP && tmp != 0xFFFFFFFF) { +#ifdef CONFIG_MCAST_TFTP + if (Mcast_addr != tmp) +#endif return; } /* @@ -1492,6 +1499,7 @@ NetReceive(volatile uchar * inpkt, int len) } #endif + #ifdef CONFIG_NETCONSOLE nc_input_packet((uchar *)ip +IP_HDR_SIZE, ntohs(ip->udp_dst), diff --git a/net/tftp.c b/net/tftp.c index d56e30b5b..95fee775e 100644 --- a/net/tftp.c +++ b/net/tftp.c @@ -61,10 +61,43 @@ static char *tftp_filename; extern flash_info_t flash_info[]; #endif +/* 512 is poor choice for ethernet, MTU is typically 1500. + * Minus eth.hdrs thats 1468. Can get 2x better throughput with + * almost-MTU block sizes. At least try... fall back to 512 if need be. + */ +#define TFTP_MTU_BLOCKSIZE 1468 +static unsigned short TftpBlkSize=TFTP_BLOCK_SIZE; +static unsigned short TftpBlkSizeOption=TFTP_MTU_BLOCKSIZE; + +#ifdef CONFIG_MCAST_TFTP +#include +#define MTFTP_BITMAPSIZE 0x1000 +static unsigned *Bitmap; +static int PrevBitmapHole,Mapsize=MTFTP_BITMAPSIZE; +static uchar ProhibitMcast=0, MasterClient=0; +static uchar Multicast=0; +extern IPaddr_t Mcast_addr; +static int Mcast_port; +static ulong TftpEndingBlock; /* can get 'last' block before done..*/ + +static void parse_multicast_oack(char *pkt,int len); + +static void +mcast_cleanup(void) +{ + if (Mcast_addr) eth_mcast_join(Mcast_addr, 0); + if (Bitmap) free(Bitmap); + Bitmap=NULL; + Mcast_addr = Multicast = Mcast_port = 0; + TftpEndingBlock = -1; +} + +#endif /* CONFIG_MCAST_TFTP */ + static __inline__ void store_block (unsigned block, uchar * src, unsigned len) { - ulong offset = block * TFTP_BLOCK_SIZE + TftpBlockWrapOffset; + ulong offset = block * TftpBlkSize + TftpBlockWrapOffset; ulong newsize = offset + len; #ifdef CFG_DIRECT_FLASH_TFTP int i, rc = 0; @@ -90,6 +123,10 @@ store_block (unsigned block, uchar * src, unsigned len) { (void)memcpy((void *)(load_addr + offset), src, len); } +#ifdef CONFIG_MCAST_TFTP + if (Multicast) + ext2_set_bit(block, Bitmap); +#endif if (NetBootFileXferSize < newsize) NetBootFileXferSize = newsize; @@ -108,6 +145,13 @@ TftpSend (void) int len = 0; volatile ushort *s; +#ifdef CONFIG_MCAST_TFTP + /* Multicast TFTP.. non-MasterClients do not ACK data. */ + if (Multicast + && (TftpState == STATE_DATA) + && (MasterClient == 0)) + return; +#endif /* * We will always be sending some sort of packet, so * cobble together the packet headers now. @@ -132,11 +176,30 @@ TftpSend (void) printf("send option \"timeout %s\"\n", (char *)pkt); #endif pkt += strlen((char *)pkt) + 1; + /* try for more effic. blk size */ + pkt += sprintf((char *)pkt,"blksize%c%d%c", + 0,htons(TftpBlkSizeOption),0); +#ifdef CONFIG_MCAST_TFTP + /* Check all preconditions before even trying the option */ + if (!ProhibitMcast + && (Bitmap=malloc(Mapsize)) + && eth_get_dev()->mcast) { + free(Bitmap); + Bitmap=NULL; + pkt += sprintf((char *)pkt,"multicast%c%c",0,0); + } +#endif /* CONFIG_MCAST_TFTP */ len = pkt - xp; break; - case STATE_DATA: case STATE_OACK: +#ifdef CONFIG_MCAST_TFTP + /* My turn! Start at where I need blocks I missed.*/ + if (Multicast) + TftpBlock=ext2_find_next_zero_bit(Bitmap,(Mapsize*8),0); + /*..falling..*/ +#endif + case STATE_DATA: xp = pkt; s = (ushort *)pkt; *s++ = htons(TFTP_ACK); @@ -177,8 +240,13 @@ TftpHandler (uchar * pkt, unsigned dest, unsigned src, unsigned len) { ushort proto; ushort *s; + int i; if (dest != TftpOurPort) { +#ifdef CONFIG_MCAST_TFTP + if (Multicast + && (!Mcast_port || (dest != Mcast_port))) +#endif return; } if (TftpState != STATE_RRQ && src != TftpServerPort) { @@ -208,6 +276,24 @@ TftpHandler (uchar * pkt, unsigned dest, unsigned src, unsigned len) #endif TftpState = STATE_OACK; TftpServerPort = src; + /* Check for 'blksize' option */ + for (i=0;i>20); } else { if (((TftpBlock - 1) % 10) == 0) { @@ -248,6 +334,11 @@ TftpHandler (uchar * pkt, unsigned dest, unsigned src, unsigned len) TftpBlockWrap = 0; TftpBlockWrapOffset = 0; +#ifdef CONFIG_MCAST_TFTP + if (Multicast) { /* start!=1 common if mcast */ + TftpLastBlock = TftpBlock - 1; + } else +#endif if (TftpBlock != 1) { /* Assertion */ printf ("\nTFTP error: " "First block is not block 1 (%ld)\n" @@ -274,9 +365,44 @@ TftpHandler (uchar * pkt, unsigned dest, unsigned src, unsigned len) * Acknoledge the block just received, which will prompt * the server for the next one. */ +#ifdef CONFIG_MCAST_TFTP + /* if I am the MasterClient, actively calculate what my next + * needed block is; else I'm passive; not ACKING + */ + if (Multicast) { + if (len < TftpBlkSize) { + TftpEndingBlock = TftpBlock; + } else if (MasterClient) { + TftpBlock = PrevBitmapHole = + ext2_find_next_zero_bit( + Bitmap, + (Mapsize*8), + PrevBitmapHole); + if (TftpBlock > ((Mapsize*8) - 1)) { + printf ("tftpfile too big\n"); + /* try to double it and retry */ + Mapsize<<=1; + mcast_cleanup(); + NetStartAgain (); + return; + } + TftpLastBlock = TftpBlock; + } + } +#endif TftpSend (); - if (len < TFTP_BLOCK_SIZE) { +#ifdef CONFIG_MCAST_TFTP + if (Multicast) { + if (MasterClient && (TftpBlock >= TftpEndingBlock)) { + puts ("\nMulticast tftp done\n"); + mcast_cleanup(); + NetState = NETLOOP_SUCCESS; + } + } + else +#endif + if (len < TftpBlkSize) { /* * We received the whole thing. Try to * run it. @@ -290,6 +416,9 @@ TftpHandler (uchar * pkt, unsigned dest, unsigned src, unsigned len) printf ("\nTFTP error: '%s' (%d)\n", pkt + 2, ntohs(*(ushort *)pkt)); puts ("Starting again\n\n"); +#ifdef CONFIG_MCAST_TFTP + mcast_cleanup(); +#endif NetStartAgain (); break; } @@ -301,6 +430,9 @@ TftpTimeout (void) { if (++TftpTimeoutCount > TIMEOUT_COUNT) { puts ("\nRetry count exceeded; starting again\n"); +#ifdef CONFIG_MCAST_TFTP + mcast_cleanup(); +#endif NetStartAgain (); } else { puts ("T "); @@ -370,6 +502,7 @@ TftpStart (void) TftpState = STATE_RRQ; /* Use a pseudo-random port unless a specific port is set */ TftpOurPort = 1024 + (get_timer(0) % 3072); + #ifdef CONFIG_TFTP_PORT if ((ep = getenv("tftpdstp")) != NULL) { TftpServerPort = simple_strtol(ep, NULL, 10); @@ -382,8 +515,103 @@ TftpStart (void) /* zero out server ether in case the server ip has changed */ memset(NetServerEther, 0, 6); + /* Revert TftpBlkSize to dflt */ + TftpBlkSize = TFTP_BLOCK_SIZE; +#ifdef CONFIG_MCAST_TFTP + mcast_cleanup(); +#endif TftpSend (); } -#endif +#ifdef CONFIG_MCAST_TFTP +/* Credits: atftp project. + */ + +/* pick up BcastAddr, Port, and whether I am [now] the master-client. * + * Frame: + * +-------+-----------+---+-------~~-------+---+ + * | opc | multicast | 0 | addr, port, mc | 0 | + * +-------+-----------+---+-------~~-------+---+ + * The multicast addr/port becomes what I listen to, and if 'mc' is '1' then + * I am the new master-client so must send ACKs to DataBlocks. If I am not + * master-client, I'm a passive client, gathering what DataBlocks I may and + * making note of which ones I got in my bitmask. + * In theory, I never go from master->passive.. + * .. this comes in with pkt already pointing just past opc + */ +static void parse_multicast_oack(char *pkt, int len) +{ + int i; + IPaddr_t addr; + char *mc_adr, *port, *mc; + + mc_adr=port=mc=NULL; + /* march along looking for 'multicast\0', which has to start at least + * 14 bytes back from the end. + */ + for (i=0;i= (len-14)) /* non-Multicast OACK, ign. */ + return; + + i+=10; /* strlen multicast */ + mc_adr = pkt+i; + for (;i Date: Fri, 27 Jul 2007 01:50:46 -0500 Subject: [PATCH 090/259] e500 needs ppc_asm.tmp MCK_EXCEPTION Always define MCK_EXCEPTION macro - so e500 can use it too. Signed-off-by: Ed Swarthout Acked-by: Andy Fleming --- include/ppc_asm.tmpl | 2 -- 1 file changed, 2 deletions(-) diff --git a/include/ppc_asm.tmpl b/include/ppc_asm.tmpl index ac8f31768..0019d4609 100644 --- a/include/ppc_asm.tmpl +++ b/include/ppc_asm.tmpl @@ -285,7 +285,6 @@ label: \ .long hdlr - _start + _START_OFFSET; \ .long crit_return - _start + _START_OFFSET -#ifdef CONFIG_440 #define MCK_EXCEPTION(n, label, hdlr) \ . = n; \ label: \ @@ -299,6 +298,5 @@ label: \ .L_ ## label : \ .long hdlr - _start + _START_OFFSET; \ .long mck_return - _start + _START_OFFSET -#endif /* CONFIG_440 */ #endif /* __PPC_ASM_TMPL__ */ From 29372ff38c5baab7d0e3a8c14fe11fa194a38704 Mon Sep 17 00:00:00 2001 From: Ed Swarthout Date: Fri, 27 Jul 2007 01:50:47 -0500 Subject: [PATCH 091/259] mpc85xx L2 cache reporting and SRAM relocation option. Allow debugger to override flash cs0/cs1 settings to enable alternate boot regions Signed-off-by: Ed Swarthout Acked-by: Andy Fleming --- cpu/mpc85xx/cpu_init.c | 65 ++++++++++++++++++++++++++++++------------ 1 file changed, 47 insertions(+), 18 deletions(-) diff --git a/cpu/mpc85xx/cpu_init.c b/cpu/mpc85xx/cpu_init.c index 9517146ed..888417f86 100644 --- a/cpu/mpc85xx/cpu_init.c +++ b/cpu/mpc85xx/cpu_init.c @@ -1,4 +1,6 @@ /* + * Copyright 2007 Freescale Semiconductor. + * * (C) Copyright 2003 Motorola Inc. * Modified by Xianghua Xiao, X.Xiao@motorola.com * @@ -133,15 +135,18 @@ void cpu_init_f (void) #endif /* now restrict to preliminary range */ + /* if cs1 is already set via debugger, leave cs0/cs1 alone */ + if (! memctl->br1 & 1) { #if defined(CFG_BR0_PRELIM) && defined(CFG_OR0_PRELIM) - memctl->br0 = CFG_BR0_PRELIM; - memctl->or0 = CFG_OR0_PRELIM; + memctl->br0 = CFG_BR0_PRELIM; + memctl->or0 = CFG_OR0_PRELIM; #endif #if defined(CFG_BR1_PRELIM) && defined(CFG_OR1_PRELIM) - memctl->or1 = CFG_OR1_PRELIM; - memctl->br1 = CFG_BR1_PRELIM; + memctl->or1 = CFG_OR1_PRELIM; + memctl->br1 = CFG_BR1_PRELIM; #endif + } #if defined(CFG_BR2_PRELIM) && defined(CFG_OR2_PRELIM) memctl->or2 = CFG_OR2_PRELIM; @@ -185,16 +190,23 @@ void cpu_init_f (void) * The newer 8548, etc, parts have twice as much cache, but * use the same bit-encoding as the older 8555, etc, parts. * - * FIXME: Use PVR_VER(pvr) == 1 test here instead of SVR_VER()? */ int cpu_init_r(void) { + volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile ccsr_local_ecm_t *ecm = &immap->im_local_ecm; + +#ifdef CONFIG_CLEAR_LAW0 + /* clear alternate boot location LAW (used for sdram, or ddr bank) */ + ecm->lawar0 = 0; +#endif + #if defined(CONFIG_L2_CACHE) - volatile immap_t *immap = (immap_t *)CFG_IMMR; volatile ccsr_l2cache_t *l2cache = &immap->im_l2cache; volatile uint cache_ctl; uint svr, ver; + uint l2srbar; svr = get_svr(); ver = SVR_VER(svr); @@ -204,30 +216,47 @@ int cpu_init_r(void) switch (cache_ctl & 0x30000000) { case 0x20000000: - if (ver == SVR_8548 || ver == SVR_8548_E) { + if (ver == SVR_8548 || ver == SVR_8548_E || + ver == SVR_8544) { printf ("L2 cache 512KB:"); + /* set L2E=1, L2I=1, & L2SRAM=0 */ + cache_ctl = 0xc0000000; } else { printf ("L2 cache 256KB:"); + /* set L2E=1, L2I=1, & L2BLKSZ=2 (256 Kbyte) */ + cache_ctl = 0xc8000000; } break; - case 0x00000000: case 0x10000000: + printf ("L2 cache 256KB:"); + if (ver == SVR_8544 || ver == SVR_8544_E) { + cache_ctl = 0xc0000000; /* set L2E=1, L2I=1, & L2SRAM=0 */ + } + break; case 0x30000000: + case 0x00000000: default: printf ("L2 cache unknown size (0x%08x)\n", cache_ctl); return -1; } - asm("msync;isync"); - l2cache->l2ctl = 0x68000000; /* invalidate */ - cache_ctl = l2cache->l2ctl; - asm("msync;isync"); - - l2cache->l2ctl = 0xa8000000; /* enable 256KB L2 cache */ - cache_ctl = l2cache->l2ctl; - asm("msync;isync"); - - printf(" enabled\n"); + if (l2cache->l2ctl & 0x80000000) { + printf(" already enabled."); + l2srbar = l2cache->l2srbar0; +#ifdef CFG_INIT_L2_ADDR + if (l2cache->l2ctl & 0x00010000 && l2srbar >= CFG_FLASH_BASE) { + l2srbar = CFG_INIT_L2_ADDR; + l2cache->l2srbar0 = l2srbar; + printf(" Moving to 0x%08x", CFG_INIT_L2_ADDR); + } +#endif /* CFG_INIT_L2_ADDR */ + puts("\n"); + } else { + asm("msync;isync"); + l2cache->l2ctl = cache_ctl; /* invalidate & enable */ + asm("msync;isync"); + printf(" enabled\n"); + } #else printf("L2 cache: disabled\n"); #endif From 40c7f9b0de4e300370adfc704128fa0f79a143b6 Mon Sep 17 00:00:00 2001 From: Ed Swarthout Date: Fri, 27 Jul 2007 01:50:48 -0500 Subject: [PATCH 092/259] 85xx allow debugger to configure ddr. Only check for mpc8548 rev 1 when compiled for 8548. Signed-off-by: Ed Swarthout Acked-by: Andy Fleming --- cpu/mpc85xx/spd_sdram.c | 48 ++++++++++++++++++++++++++++++++++++++--- 1 file changed, 45 insertions(+), 3 deletions(-) diff --git a/cpu/mpc85xx/spd_sdram.c b/cpu/mpc85xx/spd_sdram.c index 3777f49ad..d98455401 100644 --- a/cpu/mpc85xx/spd_sdram.c +++ b/cpu/mpc85xx/spd_sdram.c @@ -1,5 +1,5 @@ /* - * Copyright 2004 Freescale Semiconductor. + * Copyright 2004, 2007 Freescale Semiconductor. * (C) Copyright 2003 Motorola Inc. * Xianghua Xiao (X.Xiao@motorola.com) * @@ -173,7 +173,6 @@ spd_sdram(void) { volatile immap_t *immap = (immap_t *)CFG_IMMR; volatile ccsr_ddr_t *ddr = &immap->im_ddr; - volatile ccsr_gur_t *gur = &immap->im_gur; spd_eeprom_t spd; unsigned int n_ranks; unsigned int rank_density; @@ -189,7 +188,7 @@ spd_sdram(void) unsigned int max_data_rate, effective_data_rate; unsigned int busfreq; unsigned sdram_cfg; - unsigned int memsize; + unsigned int memsize = 0; unsigned char caslat, caslat_ctrl; unsigned int trfc, trfc_clk, trfc_low, trfc_high; unsigned int trcd_clk; @@ -204,6 +203,46 @@ spd_sdram(void) unsigned int mode_caslat; unsigned char sdram_type; unsigned char d_init; + unsigned int bnds; + + /* + * Skip configuration if already configured. + * memsize is determined from last configured chip select. + */ + if (ddr->cs0_config & 0x80000000) { + debug(" cs0 already configured, bnds=%x\n",ddr->cs0_bnds); + bnds = 0xfff & ddr->cs0_bnds; + if (bnds < 0xff) { /* do not add if at top of 4G */ + memsize = (bnds + 1) << 4; + } + } + if (ddr->cs1_config & 0x80000000) { + debug(" cs1 already configured, bnds=%x\n",ddr->cs1_bnds); + bnds = 0xfff & ddr->cs1_bnds; + if (bnds < 0xff) { /* do not add if at top of 4G */ + memsize = (bnds + 1) << 4; /* assume ordered bnds */ + } + } + if (ddr->cs2_config & 0x80000000) { + debug(" cs2 already configured, bnds=%x\n",ddr->cs2_bnds); + bnds = 0xfff & ddr->cs2_bnds; + if (bnds < 0xff) { /* do not add if at top of 4G */ + memsize = (bnds + 1) << 4; + } + } + if (ddr->cs3_config & 0x80000000) { + debug(" cs3 already configured, bnds=%x\n",ddr->cs3_bnds); + bnds = 0xfff & ddr->cs3_bnds; + if (bnds < 0xff) { /* do not add if at top of 4G */ + memsize = (bnds + 1) << 4; + } + } + + if (memsize) { + printf(" Reusing current %dMB configuration\n",memsize); + memsize = setup_laws_and_tlbs(memsize); + return memsize << 20; + } /* * Read SPD information. @@ -262,6 +301,7 @@ spd_sdram(void) return 0; } +#ifdef CONFIG_MPC8548 /* * Adjust DDR II IO voltage biasing. * Only 8548 rev 1 needs the fix @@ -269,9 +309,11 @@ spd_sdram(void) if ((SVR_VER(get_svr()) == SVR_8548_E) && (SVR_MJREV(get_svr()) == 1) && (spd.mem_type == SPD_MEMTYPE_DDR2)) { + volatile ccsr_gur_t *gur = &immap->im_gur; gur->ddrioovcr = (0x80000000 /* Enable */ | 0x10000000);/* VSEL to 1.8V */ } +#endif /* * Determine the size of each Rank in bytes. From 7bd30fc4a6475b41d6679ae3aafc9fa505260c47 Mon Sep 17 00:00:00 2001 From: Andy Fleming Date: Tue, 14 Aug 2007 01:33:18 -0500 Subject: [PATCH 093/259] Add MPC8544DS README Signed-off-by: Andy Fleming --- doc/README.mpc8544ds | 122 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 122 insertions(+) create mode 100644 doc/README.mpc8544ds diff --git a/doc/README.mpc8544ds b/doc/README.mpc8544ds new file mode 100644 index 000000000..14c7f765e --- /dev/null +++ b/doc/README.mpc8544ds @@ -0,0 +1,122 @@ +Overview +-------- +The MPC8544DS system is similar to the 85xx CDS systems such +as the MPC8548CDS due to the similar E500 core. However, it +is placed on the same board as the 8641 HPCN system. + + +Flash Banks +----------- +Like the 85xx CDS systems, the 8544 DS board has two flash banks. +They are both present on boot, but there locations can be swapped +using the dip-switch SW10, bit 2. + +However, unlike the CDS systems, but similar to the 8641 HPCN +board, a runtime reset through the FPGA can also affect a swap +on the flash bank mappings for the next reset cycle. + +Irrespective of the switch SW10[2], booting is always from the +boot bank at 0xfff8_0000. + + +Memory Map +---------- + +0xff80_0000 - 0xffbf_ffff Alernate bank 4MB +0xffc0_0000 - 0xffff_ffff Boot bank 4MB + +0xffb8_0000 Alternate image start 512KB +0xfff8_0000 Boot image start 512KB + + +Flashing Images +--------------- + +For example, to place a new image in the alternate flash bank +and then reset with that new image temporarily, use this: + + tftp 1000000 u-boot.bin.8544ds + erase ffb80000 ffbfffff + cp.b 1000000 ffb80000 80000 + pixis_reset altbank + + +To overwrite the image in the boot flash bank: + + tftp 1000000 u-boot.bin.8544ds + protect off all + erase fff80000 ffffffff + cp.b 1000000 fff80000 80000 + +Other example U-Boot image and flash manipulations examples +can be found in the README.mpc85xxcds file as well. + + +The pixis_reset command +----------------------- +A new command, "pixis_reset", is introduced to reset mpc8641hpcn board +using the FPGA sequencer. When the board restarts, it has the option +of using either the current or alternate flash bank as the boot +image, with or without the watchdog timer enabled, and finally with +or without frequency changes. + +Usage is; + + pixis_reset + pixis_reset altbank + pixis_reset altbank wd + pixis_reset altbank cf + pixis_reset cf + +Examples; + + /* reset to current bank, like "reset" command */ + pixis_reset + + /* reset board but use the to alternate flash bank */ + pixis_reset altbank + + /* reset board, use alternate flash bank with watchdog timer enabled*/ + pixis_reset altbank wd + + /* reset board to alternate bank with frequency changed. + * 40 is SYSCLK, 2.5 is COREPLL ratio, 10 is MPXPLL ratio + */ + pixis-reset altbank cf 40 2.5 10 + +Valid clock choices are in the 8641 Reference Manuals. + + +Using the Device Tree Source File +--------------------------------- +To create the DTB (Device Tree Binary) image file, +use a command similar to this: + + dtc -b 0 -f -I dts -O dtb mpc8544ds.dts > mpc8544ds.dtb + +Likely, that .dts file will come from here; + + linux-2.6/arch/powerpc/boot/dts/mpc8544ds.dts + +After placing the DTB file in your TFTP disk area, +you can download that dtb file using a command like: + + tftp 900000 mpc8544ds.dtb + +Burn it to flash if you want. + + +Booting Linux +------------- + +Place a linux uImage in the TFTP disk area too. + + tftp 1000000 uImage.8544 + tftp 900000 mpc8544ds.dtb + bootm 1000000 - 900000 + +Watch your ethact, netdev and bootargs U-Boot environment variables. +You may want to do something like this too: + + setenv ethact eTSEC3 + setenv netdev eth1 From 61a21e980a7b9188424d04f1c265fdc5c21c7e85 Mon Sep 17 00:00:00 2001 From: Andy Fleming Date: Tue, 14 Aug 2007 01:34:21 -0500 Subject: [PATCH 094/259] 85xx start.S cleanup and exception support From: Ed Swarthout Support external interrupts from platform to eliminate system hangs. Define CONFIG_INTERRUPTS board configure option to enable. Enable ecm, ddr, lbc, and pci/pcie error interrupts in PIC. Remove extra cpu initialization redundant with hardware initialization. Whitespace cleanup. Define and use _START_OFFSET consistent with other processors using ppc_asm.tmpl Move additional code from .text to boot page to make room for exception vectors at start of image. Handle Machine Check, External and Critical exceptions. Fix e500 machine check error determination in traps.c TEXT_BASE can now be 0xfffc_0000 - which cuts binary image in half. Signed-off-by: Ed Swarthout Acked-by: Andy Fleming --- cpu/mpc85xx/interrupts.c | 33 +++ cpu/mpc85xx/start.S | 485 +++++++++++++++--------------------- cpu/mpc85xx/traps.c | 99 ++++++-- include/asm-ppc/processor.h | 3 + include/mpc85xx.h | 8 +- 5 files changed, 326 insertions(+), 302 deletions(-) diff --git a/cpu/mpc85xx/interrupts.c b/cpu/mpc85xx/interrupts.c index dc246dca0..bf737d622 100644 --- a/cpu/mpc85xx/interrupts.c +++ b/cpu/mpc85xx/interrupts.c @@ -89,6 +89,39 @@ int interrupt_init (void) mtspr(SPRN_TCR, TCR_PIE); set_dec (decrementer_count); set_msr (get_msr () | MSR_EE); + +#ifdef CONFIG_INTERRUPTS + volatile ccsr_pic_t *pic = &immr->im_pic; + + pic->iivpr1 = 0x810002; /* 50220 enable ecm interrupts */ + debug("iivpr1@%x = %x\n",&pic->iivpr1, pic->iivpr1); + + pic->iivpr2 = 0x810002; /* 50240 enable ddr interrupts */ + debug("iivpr2@%x = %x\n",&pic->iivpr2, pic->iivpr2); + + pic->iivpr3 = 0x810003; /* 50260 enable lbc interrupts */ + debug("iivpr3@%x = %x\n",&pic->iivpr3, pic->iivpr3); + +#ifdef CONFIG_PCI1 + pic->iivpr8 = 0x810008; /* enable pci1 interrupts */ + debug("iivpr8@%x = %x\n",&pic->iivpr8, pic->iivpr8); +#endif +#if defined(CONFIG_PCI2) || defined(CONFIG_PCIE2) + pic->iivpr9 = 0x810009; /* enable pci1 interrupts */ + debug("iivpr9@%x = %x\n",&pic->iivpr9, pic->iivpr9); +#endif +#ifdef CONFIG_PCIE1 + pic->iivpr10 = 0x81000a; /* enable pcie1 interrupts */ + debug("iivpr10@%x = %x\n",&pic->iivpr10, pic->iivpr10); +#endif +#ifdef CONFIG_PCIE3 + pic->iivpr11 = 0x81000b; /* enable pcie3 interrupts */ + debug("iivpr11@%x = %x\n",&pic->iivpr11, pic->iivpr11); +#endif + + pic->ctpr=0; /* 40080 clear current task priority register */ +#endif + return (0); } diff --git a/cpu/mpc85xx/start.S b/cpu/mpc85xx/start.S index 77c155c5b..9dfd38d6a 100644 --- a/cpu/mpc85xx/start.S +++ b/cpu/mpc85xx/start.S @@ -1,7 +1,6 @@ /* - * Copyright 2004 Freescale Semiconductor. + * Copyright 2004, 2007 Freescale Semiconductor. * Copyright (C) 2003 Motorola,Inc. - * Xianghua Xiao * * See file CREDITS for list of people who contributed to this * project. @@ -46,7 +45,7 @@ #endif #undef MSR_KERNEL -#define MSR_KERNEL ( MSR_ME ) /* Machine Check */ +#define MSR_KERNEL ( MSR_ME ) /* Machine Check */ /* * Set up GOT: Global Offset Table @@ -80,110 +79,37 @@ * */ - .section .bootpg,"ax" - .globl _start_e500 + .section .bootpg,"ax" + .globl _start_e500 _start_e500: - mfspr r0, PVR - lis r1, PVR_85xx_REV1@h - ori r1, r1, PVR_85xx_REV1@l - cmpw r0, r1 - bne 1f - /* Semi-bogus errata fixup for Rev 1 */ - li r0,0x2000 - mtspr 977,r0 +/* clear registers/arrays not reset by hardware */ - /* - * Before invalidating MMU L1/L2, read TLB1 Entry 0 and then - * write it back immediately to fixup a Rev 1 bug (Errata CPU4) - * for this initial TLB1 entry 0, otherwise the TLB1 entry 0 - * will be invalidated (incorrectly). - */ - lis r2,0x1000 - mtspr MAS0,r2 - tlbre - tlbwe - isync - -1: - /* - * Clear and set up some registers. - * Note: Some registers need strict synchronization by - * sync/mbar/msync/isync when being "mtspr". - * BookE: isync before PID,tlbivax,tlbwe - * BookE: isync after MSR,PID; msync_isync after tlbivax & tlbwe - * E500: msync,isync before L1CSR0 - * E500: isync after BBEAR,BBTAR,BUCSR,DBCR0,DBCR1,HID0,HID1, - * L1CSR0, L1CSR1, MAS[0,1,2,3,4,6],MMUCSR0, PID[0,1,2], - * SPEFCSR - */ - - /* invalidate d-cache */ - mfspr r0,L1CSR0 - ori r0,r0,0x0002 - msync - isync - mtspr L1CSR0,r0 - isync - - /* disable d-cache */ - li r0,0x0 - mtspr L1CSR0,r0 - - /* invalidate i-cache */ - mfspr r0,L1CSR1 - ori r0,r0,0x0002 - mtspr L1CSR1,r0 - isync - - /* disable i-cache */ - li r0,0x0 - mtspr L1CSR1,r0 - isync - - /* clear registers */ - li r0,0 - mtspr SRR0,r0 - mtspr SRR1,r0 - mtspr CSRR0,r0 - mtspr CSRR1,r0 - mtspr MCSRR0,r0 - mtspr MCSRR1,r0 - - mtspr ESR,r0 - mtspr MCSR,r0 - mtspr DEAR,r0 - - /* not needed and conflicts with some debuggers */ - /* mtspr DBCR0,r0 */ - mtspr DBCR1,r0 - mtspr DBCR2,r0 - /* not needed and conflicts with some debuggers */ - /* mtspr IAC1,r0 */ - /* mtspr IAC2,r0 */ - mtspr DAC1,r0 - mtspr DAC2,r0 + /* L1 */ + li r0,2 + mtspr L1CSR0,r0 /* invalidate d-cache */ + mtspr L1CSR1,r0 /* invalidate i-cache */ mfspr r1,DBSR mtspr DBSR,r1 /* Clear all valid bits */ - mtspr PID0,r0 - mtspr PID1,r0 - mtspr PID2,r0 - mtspr TCR,r0 + /* + * Enable L1 Caches early + * + */ - mtspr BUCSR,r0 /* disable branch prediction */ - mtspr MAS4,r0 - mtspr MAS6,r0 -#if defined(CONFIG_ENABLE_36BIT_PHYS) - mtspr MAS7,r0 -#endif + lis r2,L1CSR0_CPE@H /* enable parity */ + ori r2,r2,L1CSR0_DCE + mtspr L1CSR0,r2 /* enable L1 Dcache */ isync + mtspr L1CSR1,r2 /* enable L1 Icache */ + isync + msync /* Setup interrupt vectors */ lis r1,TEXT_BASE@h - mtspr IVPR, r1 + mtspr IVPR,r1 li r1,0x0100 mtspr IVOR0,r1 /* 0: Critical input */ @@ -217,26 +143,6 @@ _start_e500: li r1,0x0f00 mtspr IVOR15,r1 /* 15: Debug */ - /* - * Invalidate MMU L1/L2 - * - * Note: There is a fixup earlier for Errata CPU4 on - * Rev 1 parts that must precede this MMU invalidation. - */ - li r2, 0x001e - mtspr MMUCSR0, r2 - isync - - /* - * Invalidate all TLB0 entries. - */ - li r3,4 - li r4,0 - tlbivax r4,r3 - /* - * To avoid REV1 Errata CPU6 issues, make sure - * the instruction following tlbivax is not a store. - */ /* * After reset, CCSRBAR is located at CFG_CCSRBAR_DEFAULT, i.e. @@ -254,14 +160,14 @@ _start_e500: lwzu r4,0(r5) /* how many TLB1 entries we actually use */ mtctr r4 -0: lwzu r0,4(r5) - lwzu r1,4(r5) - lwzu r2,4(r5) - lwzu r3,4(r5) - mtspr MAS0,r0 - mtspr MAS1,r1 - mtspr MAS2,r2 - mtspr MAS3,r3 +0: lwzu r6,4(r5) + lwzu r7,4(r5) + lwzu r8,4(r5) + lwzu r9,4(r5) + mtspr MAS0,r6 + mtspr MAS1,r7 + mtspr MAS2,r8 + mtspr MAS3,r9 isync msync tlbwe @@ -271,22 +177,22 @@ _start_e500: 1: #if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR) /* Special sequence needed to update CCSRBAR itself */ - lis r4, CFG_CCSRBAR_DEFAULT@h - ori r4, r4, CFG_CCSRBAR_DEFAULT@l + lis r4,CFG_CCSRBAR_DEFAULT@h + ori r4,r4,CFG_CCSRBAR_DEFAULT@l - lis r5, CFG_CCSRBAR@h - ori r5, r5, CFG_CCSRBAR@l + lis r5,CFG_CCSRBAR@h + ori r5,r5,CFG_CCSRBAR@l srwi r6,r5,12 - stw r6, 0(r4) + stw r6,0(r4) isync - lis r5, 0xffff + lis r5,0xffff ori r5,r5,0xf000 - lwz r5, 0(r5) + lwz r5,0(r5) isync - lis r3, CFG_CCSRBAR@h - lwz r5, CFG_CCSRBAR@l(r3) + lis r3,CFG_CCSRBAR@h + lwz r5,CFG_CCSRBAR@l(r3) isync #endif @@ -300,8 +206,8 @@ _start_e500: lwzu r5,0(r6) /* how many windows we actually use */ mtctr r5 - li r2,0x0c28 /* the first pair is reserved for boot-over-rio-or-pci */ - li r1,0x0c30 + li r2,0x0c28 /* the first pair is reserved for */ + li r1,0x0c30 /* boot-over-rio-or-pci */ 0: lwzu r4,4(r6) lwzu r3,4(r6) @@ -311,31 +217,6 @@ _start_e500: addi r1,r1,0x0020 bdnz 0b - /* Jump out the last 4K page and continue to 'normal' start */ -1: bl 3f - b _start - -3: li r0,0 - mtspr SRR1,r0 /* Keep things disabled for now */ - mflr r1 - mtspr SRR0,r1 - rfi - -/* - * r3 - 1st arg to board_init(): IMMP pointer - * r4 - 2nd arg to board_init(): boot flag - */ - .text - .long 0x27051956 /* U-BOOT Magic Number */ - .globl version_string -version_string: - .ascii U_BOOT_VERSION - .ascii " (", __DATE__, " - ", __TIME__, ")" - .ascii CONFIG_IDENT_STRING, "\0" - - . = EXC_OFF_SYS_RESET - .globl _start -_start: /* Clear and set up some registers. */ li r0,0x0000 lis r1,0xffff @@ -354,17 +235,14 @@ _start: /* Enable Time Base and Select Time Base Clock */ lis r0,HID0_EMCP@h /* Enable machine check */ - ori r0,r0,0x4000 /* time base is processor clock */ #if defined(CONFIG_ENABLE_36BIT_PHYS) - ori r0,r0,0x0080 /* enable MAS7 updates */ + ori r0,r0,(HID0_TBEN|HID0_ENMAS7)@l /* Enable Timebase & MAS7 */ +#else + ori r0,r0,HID0_TBEN@l /* enable Timebase */ #endif mtspr HID0,r0 -#if defined(CONFIG_ADDR_STREAMING) - li r0,0x3000 -#else - li r0,0x1000 -#endif + li r0,(HID1_ASTME|HID1_ABE)@l /* Addr streaming & broadcast */ mtspr HID1,r0 /* Enable Branch Prediction */ @@ -382,35 +260,56 @@ _start: mtspr DBCR0,r0 #endif -/* L1 DCache is used for initial RAM */ - mfspr r2, L1CSR0 - ori r2, r2, 0x0003 - oris r2, r2, 0x0001 - mtspr L1CSR0, r2 /* enable/invalidate L1 Dcache */ + /* Jump out the last 4K page and continue to 'normal' start */ + bl 3f + b _start_cont + +3: li r0,0 + mtspr SRR1,r0 /* Keep things disabled for now */ + mflr r1 + mtspr SRR0,r1 + rfi isync + + .text + .globl _start +_start: + .long 0x27051956 /* U-BOOT Magic Number */ + .globl version_string +version_string: + .ascii U_BOOT_VERSION + .ascii " (", __DATE__, " - ", __TIME__, ")" + .ascii CONFIG_IDENT_STRING, "\0" + + .align 4 + .globl _start_cont +_start_cont: + +/* L1 DCache is used for initial RAM */ + /* Allocate Initial RAM in data cache. */ - lis r3, CFG_INIT_RAM_ADDR@h - ori r3, r3, CFG_INIT_RAM_ADDR@l - li r2, 512 /* 512*32=16K */ + lis r3,CFG_INIT_RAM_ADDR@h + ori r3,r3,CFG_INIT_RAM_ADDR@l + li r2,512 /* 512*32=16K */ mtctr r2 - li r0, 0 + li r0,0 1: - dcbz r0, r3 - dcbtls 0,r0, r3 - addi r3, r3, 32 + dcbz r0,r3 + dcbtls 0,r0,r3 + addi r3,r3,32 bdnz 1b #ifndef CFG_RAMBOOT /* Calculate absolute address in FLASH and jump there */ /*--------------------------------------------------------------*/ - lis r3, CFG_MONITOR_BASE@h - ori r3, r3, CFG_MONITOR_BASE@l - addi r3, r3, in_flash - _start + EXC_OFF_SYS_RESET + lis r3,CFG_MONITOR_BASE@h + ori r3,r3,CFG_MONITOR_BASE@l + addi r3,r3,in_flash - _start + _START_OFFSET mtlr r3 blr - + .global in_flash in_flash: #endif /* CFG_RAMBOOT */ @@ -424,26 +323,24 @@ in_flash: stwu r1,-8(r1) /* Save back chain and move SP */ lis r0,RESET_VECTOR@h /* Address of reset vector */ - ori r0,r0, RESET_VECTOR@l + ori r0,r0,RESET_VECTOR@l stwu r1,-8(r1) /* Save back chain and move SP */ stw r0,+12(r1) /* Save return addr (underflow vect) */ GET_GOT bl cpu_init_f - bl icache_enable bl board_init_f isync -/* --FIXME-- machine check with MCSRRn and rfmci */ - + . = EXC_OFF_SYS_RESET .globl _start_of_vectors _start_of_vectors: -#if 0 + /* Critical input. */ - CRIT_EXCEPTION(0x0100, CritcalInput, CritcalInputException) -#endif -/* Machine check --FIXME-- Should be MACH_EXCEPTION */ - CRIT_EXCEPTION(0x0200, MachineCheck, MachineCheckException) + CRIT_EXCEPTION(0x0100, CriticalInput, CritcalInputException) + +/* Machine check */ + MCK_EXCEPTION(0x200, MachineCheck, MachineCheckException) /* Data Storage exception. */ STD_EXCEPTION(0x0300, DataStorage, UnknownException) @@ -452,7 +349,7 @@ _start_of_vectors: STD_EXCEPTION(0x0400, InstStorage, UnknownException) /* External Interrupt exception. */ - STD_EXCEPTION(0x0500, ExtInterrupt, UnknownException) + STD_EXCEPTION(0x0500, ExtInterrupt, ExtIntException) /* Alignment exception. */ . = 0x0600 @@ -469,8 +366,8 @@ Alignment: mtlr r6 blrl .L_Alignment: - .long AlignmentException - _start + EXC_OFF_SYS_RESET - .long int_return - _start + EXC_OFF_SYS_RESET + .long AlignmentException - _start + _START_OFFSET + .long int_return - _start + _START_OFFSET /* Program check exception */ . = 0x0700 @@ -483,8 +380,8 @@ ProgramCheck: mtlr r6 blrl .L_ProgramCheck: - .long ProgramCheckException - _start + EXC_OFF_SYS_RESET - .long int_return - _start + EXC_OFF_SYS_RESET + .long ProgramCheckException - _start + _START_OFFSET + .long int_return - _start + _START_OFFSET /* No FPU on MPC85xx. This exception is not supposed to happen. */ @@ -496,23 +393,23 @@ ProgramCheck: * r3-... arguments */ SystemCall: - addis r11,r0,0 /* get functions table addr */ - ori r11,r11,0 /* Note: this code is patched in trap_init */ - addis r12,r0,0 /* get number of functions */ + addis r11,r0,0 /* get functions table addr */ + ori r11,r11,0 /* Note: this code is patched in trap_init */ + addis r12,r0,0 /* get number of functions */ ori r12,r12,0 - cmplw 0, r0, r12 + cmplw 0,r0,r12 bge 1f - rlwinm r0,r0,2,0,31 /* fn_addr = fn_tbl[r0] */ + rlwinm r0,r0,2,0,31 /* fn_addr = fn_tbl[r0] */ add r11,r11,r0 lwz r11,0(r11) - li r20,0xd00-4 /* Get stack pointer */ + li r20,0xd00-4 /* Get stack pointer */ lwz r12,0(r20) - subi r12,r12,12 /* Adjust stack pointer */ + subi r12,r12,12 /* Adjust stack pointer */ li r0,0xc00+_end_back-SystemCall - cmplw 0, r0, r12 /* Check stack overflow */ + cmplw 0,r0,r12 /* Check stack overflow */ bgt 1f stw r12,0(r20) @@ -570,7 +467,7 @@ _end_back: _end_of_vectors: - . = 0x2100 + . = . + (0x100 - ( . & 0xff )) /* align for debug */ /* * This code finishes saving the registers to the exception frame @@ -655,26 +552,58 @@ crit_return: REST_GPR(31, r1) lwz r2,_NIP(r1) /* Restore environment */ lwz r0,_MSR(r1) - mtspr 990,r2 /* SRR2 */ - mtspr 991,r0 /* SRR3 */ + mtspr SPRN_CSRR0,r2 + mtspr SPRN_CSRR1,r0 lwz r0,GPR0(r1) lwz r2,GPR2(r1) lwz r1,GPR1(r1) SYNC rfci +mck_return: + mfmsr r28 /* Disable interrupts */ + li r4,0 + ori r4,r4,MSR_EE + andc r28,r28,r4 + SYNC /* Some chip revs need this... */ + mtmsr r28 + SYNC + lwz r2,_CTR(r1) + lwz r0,_LINK(r1) + mtctr r2 + mtlr r0 + lwz r2,_XER(r1) + lwz r0,_CCR(r1) + mtspr XER,r2 + mtcrf 0xFF,r0 + REST_10GPRS(3, r1) + REST_10GPRS(13, r1) + REST_8GPRS(23, r1) + REST_GPR(31, r1) + lwz r2,_NIP(r1) /* Restore environment */ + lwz r0,_MSR(r1) + mtspr SPRN_MCSRR0,r2 + mtspr SPRN_MCSRR1,r0 + lwz r0,GPR0(r1) + lwz r2,GPR2(r1) + lwz r1,GPR1(r1) + SYNC + rfmci + /* Cache functions. */ invalidate_icache: mfspr r0,L1CSR1 - ori r0,r0,0x0002 + ori r0,r0,L1CSR1_ICFI + msync + isync mtspr L1CSR1,r0 isync - blr /* entire I cache */ + blr /* entire I cache */ invalidate_dcache: mfspr r0,L1CSR0 - ori r0,r0,0x0002 + ori r0,r0,L1CSR0_DCFI msync isync mtspr L1CSR0,r0 @@ -697,9 +626,9 @@ icache_enable: .globl icache_disable icache_disable: mfspr r0,L1CSR1 - lis r1,0xfffffffe@h - ori r1,r1,0xfffffffe@l - and r0,r0,r1 + lis r3,0 + ori r3,r3,L1CSR1_ICE + andc r0,r0,r3 mtspr L1CSR1,r0 isync blr @@ -707,7 +636,7 @@ icache_disable: .globl icache_status icache_status: mfspr r3,L1CSR1 - andi. r3,r3,1 + andi. r3,r3,L1CSR1_ICE blr .globl dcache_enable @@ -727,12 +656,10 @@ dcache_enable: .globl dcache_disable dcache_disable: - mfspr r0,L1CSR0 - lis r1,0xfffffffe@h - ori r1,r1,0xfffffffe@l - and r0,r0,r1 - msync - isync + mfspr r3,L1CSR0 + lis r4,0 + ori r4,r4,L1CSR0_DCE + andc r3,r3,r4 mtspr L1CSR0,r0 isync blr @@ -740,27 +667,27 @@ dcache_disable: .globl dcache_status dcache_status: mfspr r3,L1CSR0 - andi. r3,r3,1 + andi. r3,r3,L1CSR0_DCE blr .globl get_pir get_pir: - mfspr r3, PIR + mfspr r3,PIR blr .globl get_pvr get_pvr: - mfspr r3, PVR + mfspr r3,PVR blr .globl get_svr get_svr: - mfspr r3, SVR + mfspr r3,SVR blr .globl wr_tcr wr_tcr: - mtspr TCR, r3 + mtspr TCR,r3 blr /*------------------------------------------------------------------------------- */ @@ -913,16 +840,16 @@ ppcSync: */ .globl relocate_code relocate_code: - mr r1, r3 /* Set new stack pointer */ - mr r9, r4 /* Save copy of Init Data pointer */ - mr r10, r5 /* Save copy of Destination Address */ + mr r1,r3 /* Set new stack pointer */ + mr r9,r4 /* Save copy of Init Data pointer */ + mr r10,r5 /* Save copy of Destination Address */ - mr r3, r5 /* Destination Address */ - lis r4, CFG_MONITOR_BASE@h /* Source Address */ - ori r4, r4, CFG_MONITOR_BASE@l + mr r3,r5 /* Destination Address */ + lis r4,CFG_MONITOR_BASE@h /* Source Address */ + ori r4,r4,CFG_MONITOR_BASE@l lwz r5,GOT(__init_end) sub r5,r5,r4 - li r6, CFG_CACHELINE_SIZE /* Cache Line Size */ + li r6,CFG_CACHELINE_SIZE /* Cache Line Size */ /* * Fix GOT pointer: @@ -931,12 +858,12 @@ relocate_code: * * Offset: */ - sub r15, r10, r4 + sub r15,r10,r4 /* First our own GOT */ - add r14, r14, r15 + add r14,r14,r15 /* the the one used by the C code */ - add r30, r30, r15 + add r30,r30,r15 /* * Now relocate code @@ -997,10 +924,10 @@ relocate_code: * initialization, now running from RAM. */ - addi r0, r10, in_ram - _start + EXC_OFF_SYS_RESET + addi r0,r10,in_ram - _start + _START_OFFSET mtlr r0 blr /* NEVER RETURNS! */ - + .globl in_ram in_ram: /* @@ -1044,19 +971,19 @@ clear_bss: lwz r3,GOT(__bss_start) lwz r4,GOT(_end) - cmplw 0, r3, r4 + cmplw 0,r3,r4 beq 6f - li r0, 0 + li r0,0 5: - stw r0, 0(r3) - addi r3, r3, 4 - cmplw 0, r3, r4 + stw r0,0(r3) + addi r3,r3,4 + cmplw 0,r3,r4 bne 5b 6: - mr r3, r9 /* Init Data pointer */ - mr r4, r10 /* Destination Address */ + mr r3,r9 /* Init Data pointer */ + mr r4,r10 /* Destination Address */ bl board_init_r /* @@ -1067,52 +994,54 @@ clear_bss: */ .globl trap_init trap_init: - lwz r7, GOT(_start) - lwz r8, GOT(_end_of_vectors) + lwz r7,GOT(_start_of_vectors) + lwz r8,GOT(_end_of_vectors) - li r9, 0x100 /* reset vector always at 0x100 */ + li r9,0x100 /* reset vector always at 0x100 */ - cmplw 0, r7, r8 + cmplw 0,r7,r8 bgelr /* return if r7>=r8 - just in case */ mflr r4 /* save link register */ 1: - lwz r0, 0(r7) - stw r0, 0(r9) - addi r7, r7, 4 - addi r9, r9, 4 - cmplw 0, r7, r8 + lwz r0,0(r7) + stw r0,0(r9) + addi r7,r7,4 + addi r9,r9,4 + cmplw 0,r7,r8 bne 1b /* * relocate `hdlr' and `int_return' entries */ - li r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET + li r7,.L_CriticalInput - _start + _START_OFFSET bl trap_reloc - li r7, .L_DataStorage - _start + EXC_OFF_SYS_RESET + li r7,.L_MachineCheck - _start + _START_OFFSET bl trap_reloc - li r7, .L_InstStorage - _start + EXC_OFF_SYS_RESET + li r7,.L_DataStorage - _start + _START_OFFSET bl trap_reloc - li r7, .L_ExtInterrupt - _start + EXC_OFF_SYS_RESET + li r7,.L_InstStorage - _start + _START_OFFSET bl trap_reloc - li r7, .L_Alignment - _start + EXC_OFF_SYS_RESET + li r7,.L_ExtInterrupt - _start + _START_OFFSET bl trap_reloc - li r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET + li r7,.L_Alignment - _start + _START_OFFSET bl trap_reloc - li r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET + li r7,.L_ProgramCheck - _start + _START_OFFSET bl trap_reloc - li r7, .L_Decrementer - _start + EXC_OFF_SYS_RESET + li r7,.L_FPUnavailable - _start + _START_OFFSET bl trap_reloc - li r7, .L_IntervalTimer - _start + EXC_OFF_SYS_RESET - li r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET + li r7,.L_Decrementer - _start + _START_OFFSET + bl trap_reloc + li r7,.L_IntervalTimer - _start + _START_OFFSET + li r8,_end_of_vectors - _start + _START_OFFSET 2: bl trap_reloc - addi r7, r7, 0x100 /* next exception vector */ - cmplw 0, r7, r8 + addi r7,r7,0x100 /* next exception vector */ + cmplw 0,r7,r8 blt 2b lis r7,0x0 - mtspr IVPR, r7 + mtspr IVPR,r7 mtlr r4 /* restore link register */ blr @@ -1121,13 +1050,13 @@ trap_init: * Function: relocate entries for one exception vector */ trap_reloc: - lwz r0, 0(r7) /* hdlr ... */ - add r0, r0, r3 /* ... += dest_addr */ - stw r0, 0(r7) + lwz r0,0(r7) /* hdlr ... */ + add r0,r0,r3 /* ... += dest_addr */ + stw r0,0(r7) - lwz r0, 4(r7) /* int_return ... */ - add r0, r0, r3 /* ... += dest_addr */ - stw r0, 4(r7) + lwz r0,4(r7) /* int_return ... */ + add r0,r0,r3 /* ... += dest_addr */ + stw r0,4(r7) blr @@ -1135,13 +1064,13 @@ trap_reloc: .globl unlock_ram_in_cache unlock_ram_in_cache: /* invalidate the INIT_RAM section */ - lis r3, (CFG_INIT_RAM_ADDR & ~31)@h - ori r3, r3, (CFG_INIT_RAM_ADDR & ~31)@l - li r2,512 - mtctr r2 -1: icbi r0, r3 - dcbi r0, r3 - addi r3, r3, 32 + lis r3,(CFG_INIT_RAM_ADDR & ~31)@h + ori r3,r3,(CFG_INIT_RAM_ADDR & ~31)@l + li r4,512 + mtctr r4 +1: icbi r0,r3 + dcbi r0,r3 + addi r3,r3,32 bdnz 1b sync /* Wait for all icbi to complete on bus */ isync diff --git a/cpu/mpc85xx/traps.c b/cpu/mpc85xx/traps.c index 9cd621c3a..efc80c7ae 100644 --- a/cpu/mpc85xx/traps.c +++ b/cpu/mpc85xx/traps.c @@ -1,6 +1,7 @@ /* * linux/arch/ppc/kernel/traps.c * + * Copyright 2007 Freescale Semiconductor. * Copyright (C) 2003 Motorola * Modified by Xianghua Xiao(x.xiao@motorola.com) * @@ -145,10 +146,13 @@ CritcalInputException(struct pt_regs *regs) panic("Critical Input Exception"); } +int machinecheck_count = 0; +int machinecheck_error = 0; void MachineCheckException(struct pt_regs *regs) { unsigned long fixup; + unsigned int mcsr, mcsrr0, mcsrr1, mcar; /* Probing PCI using config cycles cause this exception * when a device is not present. Catch it and return to @@ -159,34 +163,62 @@ MachineCheckException(struct pt_regs *regs) return; } + mcsrr0 = mfspr(SPRN_MCSRR0); + mcsrr1 = mfspr(SPRN_MCSRR1); + mcsr = mfspr(SPRN_MCSR); + mcar = mfspr(SPRN_MCAR); + + machinecheck_count++; + machinecheck_error=1; + #if defined(CONFIG_CMD_KGDB) if (debugger_exception_handler && (*debugger_exception_handler)(regs)) return; #endif printf("Machine check in kernel mode.\n"); - printf("Caused by (from msr): "); - printf("regs %p ",regs); - switch( regs->msr & 0x000F0000) { - case (0x80000000>>12): - printf("Machine check signal - probably due to mm fault\n" - "with mmu off\n"); - break; - case (0x80000000>>13): - printf("Transfer error ack signal\n"); - break; - case (0x80000000>>14): - printf("Data parity signal\n"); - break; - case (0x80000000>>15): - printf("Address parity signal\n"); - break; - default: - printf("Unknown values in msr\n"); - } + printf("Caused by (from mcsr): "); + printf("mcsr = 0x%08x\n", mcsr); + if (mcsr & 0x80000000) + printf("Machine check input pin\n"); + if (mcsr & 0x40000000) + printf("Instruction cache parity error\n"); + if (mcsr & 0x20000000) + printf("Data cache push parity error\n"); + if (mcsr & 0x10000000) + printf("Data cache parity error\n"); + if (mcsr & 0x00000080) + printf("Bus instruction address error\n"); + if (mcsr & 0x00000040) + printf("Bus Read address error\n"); + if (mcsr & 0x00000020) + printf("Bus Write address error\n"); + if (mcsr & 0x00000010) + printf("Bus Instruction data bus error\n"); + if (mcsr & 0x00000008) + printf("Bus Read data bus error\n"); + if (mcsr & 0x00000004) + printf("Bus Write bus error\n"); + if (mcsr & 0x00000002) + printf("Bus Instruction parity error\n"); + if (mcsr & 0x00000001) + printf("Bus Read parity error\n"); + show_regs(regs); + printf("MCSR=0x%08x \tMCSRR0=0x%08x \nMCSRR1=0x%08x \tMCAR=0x%08x\n", + mcsr, mcsrr0, mcsrr1, mcar); print_backtrace((unsigned long *)regs->gpr[1]); - panic("machine check"); + if (machinecheck_count > 10) { + panic("machine check count too high\n"); + } + + if (machinecheck_count > 1) { + regs->nip += 4; /* skip offending instruction */ + printf("Skipping current instr, Returning to 0x%08x\n", + regs->nip); + } else { + printf("Returning back to 0x%08x\n",regs->nip); + } } void @@ -253,6 +285,33 @@ UnknownException(struct pt_regs *regs) regs->nip, regs->msr, regs->trap); _exception(0, regs); } +void +ExtIntException(struct pt_regs *regs) +{ + volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile ccsr_pic_t *pic = &immap->im_pic; + uint vect; + +#if defined(CONFIG_CMD_KGDB) + if (debugger_exception_handler && (*debugger_exception_handler)(regs)) + return; +#endif + + printf("External Interrupt Exception at PC: %lx, SR: %lx, vector=%lx", + regs->nip, regs->msr, regs->trap); + vect = pic->iack0; + printf(" irq IACK0@%05x=%d\n",&pic->iack0,vect); + show_regs(regs); + print_backtrace((unsigned long *)regs->gpr[1]); + machinecheck_count++; +#ifdef EXTINT_NOSKIP + printf("Returning back to 0x%08x\n",regs->nip); +#else + regs->nip += 4; /* skip offending instruction */ + printf("Skipping current instr, Returning to 0x%08x\n",regs->nip); +#endif + +} void DebugException(struct pt_regs *regs) diff --git a/include/asm-ppc/processor.h b/include/asm-ppc/processor.h index 9be5a279e..0a160e251 100644 --- a/include/asm-ppc/processor.h +++ b/include/asm-ppc/processor.h @@ -217,12 +217,14 @@ #define HID0_DPM (1<<20) #define HID0_ICE (1< From 837f1ba05cfb248aba5ab8e1fb1bfeefa07d5962 Mon Sep 17 00:00:00 2001 From: Ed Swarthout Date: Fri, 27 Jul 2007 01:50:51 -0500 Subject: [PATCH 095/259] 8544ds PCIE support PCI1 LAW mapping should use CFG_PCI1_MEM_PHY and not _BASE address. Enable LBC and ECM errors and clear error registers. Add tftpflash env var to get uboot from tftp server and flash it. Add pci/pcie convenience env vars to display register space: "run pcie3regs" to see all pcie3 ccsr registers "run pcie3cfg" to see all cfg registers Whitespace cleanup and MPC8544DS.h Enable CONFIG_INTERRUPTS. Signed-off-by: Ed Swarthout Acked-by: Andy Fleming --- board/freescale/mpc8544ds/init.S | 6 +- board/freescale/mpc8544ds/mpc8544ds.c | 350 ++++++++++++++++++++++++++ include/asm-ppc/immap_85xx.h | 37 ++- include/configs/MPC8544DS.h | 133 ++++++---- 4 files changed, 467 insertions(+), 59 deletions(-) diff --git a/board/freescale/mpc8544ds/init.S b/board/freescale/mpc8544ds/init.S index 296fee5e6..ea7d54dc3 100644 --- a/board/freescale/mpc8544ds/init.S +++ b/board/freescale/mpc8544ds/init.S @@ -52,8 +52,8 @@ */ #define entry_start \ - mflr r1 ; \ - bl 0f ; + mflr r1 ; \ + bl 0f ; #define entry_end \ 0: mflr r0 ; \ @@ -214,7 +214,7 @@ law_entry: .long 0 .long (LAWAR_TRGT_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN - .long (CFG_PCI1_MEM_BASE>>12) & 0xfffff + .long (CFG_PCI1_MEM_PHYS>>12) & 0xfffff .long LAWAR_EN | LAWAR_TRGT_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_512M) .long (CFG_PCI1_IO_PHYS>>12) & 0xfffff diff --git a/board/freescale/mpc8544ds/mpc8544ds.c b/board/freescale/mpc8544ds/mpc8544ds.c index 4ff1da930..8ddbb0101 100644 --- a/board/freescale/mpc8544ds/mpc8544ds.c +++ b/board/freescale/mpc8544ds/mpc8544ds.c @@ -22,8 +22,10 @@ #include #include +#include #include #include +#include #include #include @@ -51,12 +53,19 @@ int checkboard (void) { volatile immap_t *immap = (immap_t *) CFG_CCSRBAR; volatile ccsr_gur_t *gur = &immap->im_gur; + volatile ccsr_lbc_t *lbc = &immap->im_lbc; + volatile ccsr_local_ecm_t *ecm = &immap->im_local_ecm; if ((uint)&gur->porpllsr != 0xe00e0000) { printf("immap size error %x\n",&gur->porpllsr); } printf ("Board: MPC8544DS\n"); + lbc->ltesr = 0xffffffff; /* Clear LBC error interrupts */ + lbc->lteir = 0xffffffff; /* Enable LBC error interrupts */ + ecm->eedr = 0xffffffff; /* Clear ecm errors */ + ecm->eeer = 0xffffffff; /* Enable ecm errors */ + return 0; } @@ -118,6 +127,316 @@ testdram(void) } #endif +#ifdef CONFIG_PCI1 +static struct pci_controller pci1_hose; +#endif + +#ifdef CONFIG_PCIE1 +static struct pci_controller pcie1_hose; +#endif + +#ifdef CONFIG_PCIE2 +static struct pci_controller pcie2_hose; +#endif + +#ifdef CONFIG_PCIE3 +static struct pci_controller pcie3_hose; +#endif + +int first_free_busno=0; + +void +pci_init_board(void) +{ + volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile ccsr_gur_t *gur = &immap->im_gur; + uint devdisr = gur->devdisr; + uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19; + uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16; + + debug (" pci_init_board: devdisr=%x, io_sel=%x, host_agent=%x\n", + devdisr, io_sel, host_agent); + + if (io_sel & 1) { + if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII1_DIS)) + printf (" eTSEC1 is in sgmii mode.\n"); + if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS)) + printf (" eTSEC3 is in sgmii mode.\n"); + } + +#ifdef CONFIG_PCIE3 +{ + volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE3_ADDR; + extern void fsl_pci_init(struct pci_controller *hose); + struct pci_controller *hose = &pcie3_hose; + int pcie_ep = (host_agent == 3); + int pcie_configured = io_sel >= 1; + + if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ + printf ("\n PCIE3 connected to ULI as %s (base address %x)", + pcie_ep ? "End Point" : "Root Complex", + (uint)pci); + if (pci->pme_msg_det) { + pci->pme_msg_det = 0xffffffff; + debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det); + } + printf ("\n"); + + /* inbound */ + pci_set_region(hose->regions + 0, + CFG_PCI_MEMORY_BUS, + CFG_PCI_MEMORY_PHYS, + CFG_PCI_MEMORY_SIZE, + PCI_REGION_MEM | PCI_REGION_MEMORY); + + /* outbound memory */ + pci_set_region(hose->regions + 1, + CFG_PCIE3_MEM_BASE, + CFG_PCIE3_MEM_PHYS, + CFG_PCIE3_MEM_SIZE, + PCI_REGION_MEM); + + /* outbound io */ + pci_set_region(hose->regions + 2, + CFG_PCIE3_IO_BASE, + CFG_PCIE3_IO_PHYS, + CFG_PCIE3_IO_SIZE, + PCI_REGION_IO); + + hose->region_count = 3; +#ifdef CFG_PCIE3_MEM_BASE2 + /* outbound memory */ + pci_set_region(hose->regions + 3, + CFG_PCIE3_MEM_BASE2, + CFG_PCIE3_MEM_PHYS2, + CFG_PCIE3_MEM_SIZE2, + PCI_REGION_MEM); + hose->region_count++; +#endif + hose->first_busno=first_free_busno; + pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); + + fsl_pci_init(hose); + + first_free_busno=hose->last_busno+1; + printf (" PCIE3 on bus %02x - %02x\n", + hose->first_busno,hose->last_busno); + + } else { + printf (" PCIE3: disabled\n"); + } + + } +#else + gur->devdisr |= MPC85xx_DEVDISR_PCIE3; /* disable */ +#endif + +#ifdef CONFIG_PCIE1 + { + volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE1_ADDR; + extern void fsl_pci_init(struct pci_controller *hose); + struct pci_controller *hose = &pcie1_hose; + int pcie_ep = (host_agent == 5); + int pcie_configured = io_sel & 6; + + if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ + printf ("\n PCIE1 connected to Slot2 as %s (base address %x)", + pcie_ep ? "End Point" : "Root Complex", + (uint)pci); + if (pci->pme_msg_det) { + pci->pme_msg_det = 0xffffffff; + debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det); + } + printf ("\n"); + + /* inbound */ + pci_set_region(hose->regions + 0, + CFG_PCI_MEMORY_BUS, + CFG_PCI_MEMORY_PHYS, + CFG_PCI_MEMORY_SIZE, + PCI_REGION_MEM | PCI_REGION_MEMORY); + + /* outbound memory */ + pci_set_region(hose->regions + 1, + CFG_PCIE1_MEM_BASE, + CFG_PCIE1_MEM_PHYS, + CFG_PCIE1_MEM_SIZE, + PCI_REGION_MEM); + + /* outbound io */ + pci_set_region(hose->regions + 2, + CFG_PCIE1_IO_BASE, + CFG_PCIE1_IO_PHYS, + CFG_PCIE1_IO_SIZE, + PCI_REGION_IO); + + hose->region_count = 3; +#ifdef CFG_PCIE1_MEM_BASE2 + /* outbound memory */ + pci_set_region(hose->regions + 3, + CFG_PCIE1_MEM_BASE2, + CFG_PCIE1_MEM_PHYS2, + CFG_PCIE1_MEM_SIZE2, + PCI_REGION_MEM); + hose->region_count++; +#endif + hose->first_busno=first_free_busno; + + pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); + + fsl_pci_init(hose); + + first_free_busno=hose->last_busno+1; + printf(" PCIE1 on bus %02x - %02x\n", + hose->first_busno,hose->last_busno); + + } else { + printf (" PCIE1: disabled\n"); + } + + } +#else + gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */ +#endif + +#ifdef CONFIG_PCIE2 + { + volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE2_ADDR; + extern void fsl_pci_init(struct pci_controller *hose); + struct pci_controller *hose = &pcie2_hose; + int pcie_ep = (host_agent == 3); + int pcie_configured = io_sel & 4; + + if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ + printf ("\n PCIE2 connected to Slot 1 as %s (base address %x)", + pcie_ep ? "End Point" : "Root Complex", + (uint)pci); + if (pci->pme_msg_det) { + pci->pme_msg_det = 0xffffffff; + debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det); + } + printf ("\n"); + + /* inbound */ + pci_set_region(hose->regions + 0, + CFG_PCI_MEMORY_BUS, + CFG_PCI_MEMORY_PHYS, + CFG_PCI_MEMORY_SIZE, + PCI_REGION_MEM | PCI_REGION_MEMORY); + + /* outbound memory */ + pci_set_region(hose->regions + 1, + CFG_PCIE2_MEM_BASE, + CFG_PCIE2_MEM_PHYS, + CFG_PCIE2_MEM_SIZE, + PCI_REGION_MEM); + + /* outbound io */ + pci_set_region(hose->regions + 2, + CFG_PCIE2_IO_BASE, + CFG_PCIE2_IO_PHYS, + CFG_PCIE2_IO_SIZE, + PCI_REGION_IO); + + hose->region_count = 3; +#ifdef CFG_PCIE2_MEM_BASE2 + /* outbound memory */ + pci_set_region(hose->regions + 3, + CFG_PCIE2_MEM_BASE2, + CFG_PCIE2_MEM_PHYS2, + CFG_PCIE2_MEM_SIZE2, + PCI_REGION_MEM); + hose->region_count++; +#endif + hose->first_busno=first_free_busno; + pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); + + fsl_pci_init(hose); + first_free_busno=hose->last_busno+1; + printf (" PCIE2 on bus %02x - %02x\n", + hose->first_busno,hose->last_busno); + + } else { + printf (" PCIE2: disabled\n"); + } + + } +#else + gur->devdisr |= MPC85xx_DEVDISR_PCIE2; /* disable */ +#endif + + +#ifdef CONFIG_PCI1 +{ + volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCI1_ADDR; + extern void fsl_pci_init(struct pci_controller *hose); + struct pci_controller *hose = &pci1_hose; + + uint pci_agent = (host_agent == 6); + uint pci_speed = 66666000; /*get_clock_freq (); PCI PSPEED in [4:5] */ + uint pci_32 = 1; + uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; /* PORDEVSR[14] */ + uint pci_clk_sel = gur->porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; /* PORPLLSR[16] */ + + + if (!(devdisr & MPC85xx_DEVDISR_PCI1)) { + printf ("\n PCI: %d bit, %s MHz, %s, %s, %s (base address %x)\n", + (pci_32) ? 32 : 64, + (pci_speed == 33333000) ? "33" : + (pci_speed == 66666000) ? "66" : "unknown", + pci_clk_sel ? "sync" : "async", + pci_agent ? "agent" : "host", + pci_arb ? "arbiter" : "external-arbiter", + (uint)pci + ); + + /* inbound */ + pci_set_region(hose->regions + 0, + CFG_PCI_MEMORY_BUS, + CFG_PCI_MEMORY_PHYS, + CFG_PCI_MEMORY_SIZE, + PCI_REGION_MEM | PCI_REGION_MEMORY); + + /* outbound memory */ + pci_set_region(hose->regions + 1, + CFG_PCI1_MEM_BASE, + CFG_PCI1_MEM_PHYS, + CFG_PCI1_MEM_SIZE, + PCI_REGION_MEM); + + /* outbound io */ + pci_set_region(hose->regions + 2, + CFG_PCI1_IO_BASE, + CFG_PCI1_IO_PHYS, + CFG_PCI1_IO_SIZE, + PCI_REGION_IO); + hose->region_count = 3; +#ifdef CFG_PCIE3_MEM_BASE2 + /* outbound memory */ + pci_set_region(hose->regions + 3, + CFG_PCIE3_MEM_BASE2, + CFG_PCIE3_MEM_PHYS2, + CFG_PCIE3_MEM_SIZE2, + PCI_REGION_MEM); + hose->region_count++; +#endif + hose->first_busno=first_free_busno; + pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); + + fsl_pci_init(hose); + first_free_busno=hose->last_busno+1; + printf ("PCI on bus %02x - %02x\n", + hose->first_busno,hose->last_busno); + } else { + printf (" PCI: disabled\n"); + } +} +#else + gur->devdisr |= MPC85xx_DEVDISR_PCI1; /* disable */ +#endif +} + + int last_stage_init(void) { return 0; @@ -192,6 +511,37 @@ ft_board_setup(void *blob, bd_t *bd) ft_cpu_setup(blob, bd); + p = ft_get_prop(blob, "/memory/reg", &len); + if (p != NULL) { + *p++ = cpu_to_be32(bd->bi_memstart); + *p = cpu_to_be32(bd->bi_memsize); + } +#ifdef CONFIG_PCIE1 + p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@a000/bus-range", &len); + if (p != NULL) { + p[0] = 0; + p[1] = pcie1_hose.last_busno - pcie1_hose.first_busno; + debug("PCI@a000 first_busno=%d last_busno=%d\n",p[0],p[1]); + } +#endif +#ifdef CONFIG_PCIE2 + p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@9000/bus-range", &len); + if (p != NULL) { + p[0] = 0; + p[1] = pcie2_hose.last_busno - pcie2_hose.first_busno; + debug("PCI@9000 first_busno=%d last_busno=%d\n",p[0],p[1]); + } +#endif +#ifdef CONFIG_PCIE3 + p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@b000/bus-range", &len); + if (p != NULL) { + p[0] = 0; + p[1] = pcie3_hose.last_busno - pcie3_hose.first_busno;; + debug("PCI@b000 first_busno=%d last_busno=%d\n",p[0],p[1]); + } +#endif + ft_cpu_setup(blob, bd); + p = ft_get_prop(blob, "/memory/reg", &len); if (p != NULL) { *p++ = cpu_to_be32(bd->bi_memstart); diff --git a/include/asm-ppc/immap_85xx.h b/include/asm-ppc/immap_85xx.h index e002d2838..77f885daa 100644 --- a/include/asm-ppc/immap_85xx.h +++ b/include/asm-ppc/immap_85xx.h @@ -1,6 +1,8 @@ /* * MPC85xx Internal Memory Map * + * Copyright 2007 Freescale Semiconductor. + * * Copyright(c) 2002,2003 Motorola Inc. * Xianghua Xiao (x.xiao@motorola.com) * @@ -1526,8 +1528,22 @@ typedef struct ccsr_rio { typedef struct ccsr_gur { uint porpllsr; /* 0xe0000 - POR PLL ratio status register */ uint porbmsr; /* 0xe0004 - POR boot mode status register */ +#define MPC85xx_PORBMSR_HA 0x00070000 uint porimpscr; /* 0xe0008 - POR I/O impedance status and control register */ uint pordevsr; /* 0xe000c - POR I/O device status regsiter */ +#define MPC85xx_PORDEVSR_SGMII1_DIS 0x20000000 +#define MPC85xx_PORDEVSR_SGMII2_DIS 0x10000000 +#define MPC85xx_PORDEVSR_SGMII3_DIS 0x08000000 +#define MPC85xx_PORDEVSR_SGMII4_DIS 0x04000000 +#define MPC85xx_PORDEVSR_IO_SEL 0x00380000 +#define MPC85xx_PORDEVSR_PCI2_ARB 0x00040000 +#define MPC85xx_PORDEVSR_PCI1_ARB 0x00020000 +#define MPC85xx_PORDEVSR_PCI1_PCI32 0x00010000 +#define MPC85xx_PORDEVSR_PCI1_SPD 0x00008000 +#define MPC85xx_PORDEVSR_PCI2_SPD 0x00004000 +#define MPC85xx_PORDEVSR_DRAM_RTYPE 0x00000060 +#define MPC85xx_PORDEVSR_RIO_CTLS 0x00000008 +#define MPC85xx_PORDEVSR_RIO_DEV_ID 0x00000007 uint pordbgmsr; /* 0xe0010 - POR debug mode status register */ char res1[12]; uint gpporcr; /* 0xe0020 - General-purpose POR configuration register */ @@ -1541,6 +1557,25 @@ typedef struct ccsr_gur { uint pmuxcr; /* 0xe0060 - Alternate function signal multiplex control */ char res6[12]; uint devdisr; /* 0xe0070 - Device disable control */ +#define MPC85xx_DEVDISR_PCI1 0x80000000 +#define MPC85xx_DEVDISR_PCI2 0x40000000 +#define MPC85xx_DEVDISR_PCIE 0x20000000 +#define MPC85xx_DEVDISR_LBC 0x08000000 +#define MPC85xx_DEVDISR_PCIE2 0x04000000 +#define MPC85xx_DEVDISR_PCIE3 0x02000000 +#define MPC85xx_DEVDISR_SEC 0x01000000 +#define MPC85xx_DEVDISR_SRIO 0x00080000 +#define MPC85xx_DEVDISR_RMSG 0x00040000 +#define MPC85xx_DEVDISR_DDR 0x00010000 +#define MPC85xx_DEVDISR_CPU 0x00008000 +#define MPC85xx_DEVDISR_TB 0x00004000 +#define MPC85xx_DEVDISR_DMA 0x00000400 +#define MPC85xx_DEVDISR_TSEC1 0x00000080 +#define MPC85xx_DEVDISR_TSEC2 0x00000040 +#define MPC85xx_DEVDISR_TSEC3 0x00000020 +#define MPC85xx_DEVDISR_TSEC4 0x00000010 +#define MPC85xx_DEVDISR_I2C 0x00000004 +#define MPC85xx_DEVDISR_DUART 0x00000002 char res7[12]; uint powmgtcsr; /* 0xe0080 - Power management status and control register */ char res8[12]; @@ -1562,7 +1597,7 @@ typedef struct ccsr_gur { uint ddrioovcr; /* 0xe0f24 - DDR IO Override Control */ uint res14; /* 0xe0f28 */ uint tsec34ioovcr; /* 0xe0f2c - eTSEC 3/4 IO override control */ - char res15[61651]; + char res15[61648]; /* 0xe0f30 to 0xefffff */ } ccsr_gur_t; #define PORDEVSR_PCI (0x00800000) /* PCI Mode */ diff --git a/include/configs/MPC8544DS.h b/include/configs/MPC8544DS.h index d0f94a3e2..32934e155 100644 --- a/include/configs/MPC8544DS.h +++ b/include/configs/MPC8544DS.h @@ -34,14 +34,14 @@ #define CONFIG_MPC8544 1 #define CONFIG_MPC8544DS 1 -#undef CONFIG_PCI /* Enable PCI/PCIE */ -#undef CONFIG_PCI1 /* PCI controller 1 */ -#undef CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */ -#undef CONFIG_PCIE2 /* PCIE controler 2 (slot 2) */ -#undef CONFIG_PCIE3 /* PCIE controler 3 (ULI bridge) */ -#undef CONFIG_FSL_PCI_INIT /* Use common FSL init code */ +#define CONFIG_PCI 1 /* Enable PCI/PCIE */ +#define CONFIG_PCI1 1 /* PCI controller 1 */ +#define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */ +#define CONFIG_PCIE2 1 /* PCIE controler 2 (slot 2) */ +#define CONFIG_PCIE3 1 /* PCIE controler 3 (ULI bridge) */ +#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ -#define CONFIG_TSEC_ENET /* tsec ethernet support */ +#define CONFIG_TSEC_ENET /* tsec ethernet support */ #define CONFIG_ENV_OVERWRITE #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ #undef CONFIG_DDR_DLL @@ -52,6 +52,7 @@ #define CONFIG_MEM_INIT_VALUE 0xDeadBeef #define CONFIG_DDR_ECC_CMD +#define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */ /* * When initializing flash, if we cannot find the manufacturer ID, @@ -70,7 +71,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); /* * These can be toggled for performance analysis, otherwise use default. */ -#define CONFIG_L2_CACHE /* toggle L2 cache */ +#define CONFIG_L2_CACHE /* toggle L2 cache */ #define CONFIG_BTB /* toggle branch predition */ #define CONFIG_ADDR_STREAMING /* toggle addr streaming */ #define CONFIG_CLEAR_LAW0 /* Clear LAW0 in cpu_init_r */ @@ -86,13 +87,13 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CFG_MEMTEST_START 0x00200000 /* memtest works on */ #define CFG_MEMTEST_END 0x00400000 #define CFG_ALT_MEMTEST -#define CONFIG_PANIC_HANG /* do not reset board on panic */ +#define CONFIG_PANIC_HANG /* do not reset board on panic */ /* * Base addresses -- Note these are effective addresses where the * actual resources get mapped (not physical addresses) */ -#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ +#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ #define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ #define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ @@ -344,7 +345,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_SATA_ULI5288 #define CFG_SCSI_MAX_SCSI_ID 4 #define CFG_SCSI_MAX_LUN 1 -#define CFG_SCSI_MAX_DEVICE (CFG_SCSI_MAX_SCSI_ID * CFG_SCSI_MAX_LUN) +#define CFG_SCSI_MAX_DEVICE (CFG_SCSI_MAX_SCSI_ID * CFG_SCSI_MAX_LUN) #define CFG_SCSI_MAXDEVICE CFG_SCSI_MAX_DEVICE #endif /* SCSCI */ @@ -354,7 +355,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #if defined(CONFIG_TSEC_ENET) #ifndef CONFIG_NET_MULTI -#define CONFIG_NET_MULTI 1 +#define CONFIG_NET_MULTI 1 #endif #define CONFIG_MII 1 /* MII PHY management */ @@ -365,6 +366,10 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_TSEC3_NAME "eTSEC3" #undef CONFIG_MPC85XX_FEC +#define CONFIG_TSEC_TBI 1 /* enable internal TBI phy */ +#define CONFIG_SGMII_RISER +#define TSEC1_SGMII_PHY_ADDR_OFFSET 0x1c /* sgmii phy base */ + #define TSEC1_PHY_ADDR 0 #define TSEC3_PHY_ADDR 1 @@ -374,7 +379,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_ETHPRIME "eTSEC1" #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ - #endif /* CONFIG_TSEC_ENET */ /* @@ -392,7 +396,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - /* * BOOTP options */ @@ -415,6 +418,8 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_CMD_PCI #define CONFIG_CMD_BEDBUG #define CONFIG_CMD_NET + #define CONFIG_CMD_SCSI + #define CONFIG_CMD_EXT2 #endif @@ -441,10 +446,10 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); * have to be in the first 8 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ /* Cache Configuration */ -#define CFG_DCACHE_SIZE 32768 +#define CFG_DCACHE_SIZE 32768 #define CFG_CACHELINE_SIZE 32 #if defined(CONFIG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/ @@ -482,7 +487,8 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_HOSTNAME 8544ds_unknown #define CONFIG_ROOTPATH /nfs/mpc85xx -#define CONFIG_BOOTFILE 8544ds_tmt/uImage.uboot +#define CONFIG_BOOTFILE 8544ds/uImage.uboot +#define CONFIG_UBOOTPATH 8544ds/u-boot.bin /* TFTP server */ #define CONFIG_SERVERIP 192.168.0.1 #define CONFIG_GATEWAYIP 192.168.0.1 @@ -491,7 +497,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_LOADADDR 1000000 /*default location for tftp and bootm*/ #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ -#undef CONFIG_BOOTARGS /* the boot command will set bootargs*/ +#undef CONFIG_BOOTARGS /* the boot command will set bootargs*/ #define CONFIG_BAUDRATE 115200 @@ -499,10 +505,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define PCIE_ENV \ "pciereg=md ${a}000 6; md ${a}020 4; md ${a}bf8 2; echo o;md ${a}c00 25;" \ "echo i; md ${a}da0 15; echo e;md ${a}e00 e; echo d; md ${a}f00 c\0" \ - "pcie1regs=setenv a e000a; run pciereg\0" \ - "pcie2regs=setenv a e0009; run pciereg\0" \ - "pcie3regs=setenv a e000b; run pciereg\0" \ - "pcieerr=md ${a}020 1; md ${a}e00;" \ + "pcieerr=md ${a}020 1; md ${a}e00 e;" \ "pci d.b $b.0 7 1; pci d.w $b.0 1e 1;" \ "pci d.w $b.0 56 1;" \ "pci d $b.0 104 1;pci d $b.0 110 1;pci d $b.0 130 1\0" \ @@ -511,12 +514,18 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); "pci w $b.0 104 ffffffff; pci w $b.0 110 ffffffff;" \ "pci w $b.0 130 ffffffff\0" \ "pciecfg=pci d $b.0 0 20; pci d $b.0 100 e; pci d $b.0 400 69\0" \ - "pcie1err=setenv a e000a; run pcieerr\0" \ - "pcie2err=setenv a e0009; run pcieerr\0" \ - "pcie3err=setenv a e000b; run pcieerr\0" \ - "pcie1errc=setenv a e000a; run pcieerrc\0" \ - "pcie2errc=setenv a e0009; run pcieerrc\0" \ - "pcie3errc=setenv a e000b; run pcieerrc\0" + "pcie1regs=setenv a e000a; run pciereg\0" \ + "pcie2regs=setenv a e0009; run pciereg\0" \ + "pcie3regs=setenv a e000b; run pciereg\0" \ + "pcie1cfg=setenv b 3; run pciecfg\0" \ + "pcie2cfg=setenv b 5; run pciecfg\0" \ + "pcie3cfg=setenv b 0; run pciecfg\0" \ + "pcie1err=setenv a e000a; setenv b 3; run pcieerr\0" \ + "pcie2err=setenv a e0009; setenv b 5; run pcieerr\0" \ + "pcie3err=setenv a e000b; setenv b 0; run pcieerr\0" \ + "pcie1errc=setenv a e000a; setenv b 3; run pcieerrc\0" \ + "pcie2errc=setenv a e0009; setenv b 5; run pcieerrc\0" \ + "pcie3errc=setenv a e000b; setenv b 0; run pcieerrc\0" #else #define PCIE_ENV "" #endif @@ -524,14 +533,14 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #if defined(CONFIG_PCI1) #define PCI_ENV \ "pcireg=md ${a}000 3; echo o;md ${a}c00 25; echo i; md ${a}da0 15;" \ - "echo e;md ${a}e00 9\0" \ + "echo e;md ${a}e00 9\0" \ "pci1regs=setenv a e0008; run pcireg\0" \ "pcierr=md ${a}e00 8; pci d.b $b.0 7 1; pci d.w $b.0 1e 1;" \ "pci d.w $b.0 56 1\0" \ - "pcierrc=mw ${a}e00 ffffffff; pci w.b $b.0 7 ff; pci w.w $b.0 1e ffff;" \ - "pci w.w $b.0 56 ffff\0" \ - "pci1err=setenv a e0008; run pcierr\0" \ - "pci1errc=setenv a e0008; run pcierrc\0" + "pcierrc=mw ${a}e00 ffffffff; mw ${a}e0c 0; pci w.b $b.0 7 ff;" \ + "pci w.w $b.0 1e ffff; pci w.w $b.0 56 ffff\0" \ + "pci1err=setenv a e0008; setenv b 7; run pcierr\0" \ + "pci1errc=setenv a e0008; setenv b 7; run pcierrc\0" #else #define PCI_ENV "" #endif @@ -551,25 +560,39 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define ENET_ENV "" #endif -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ + "tftpflash=tftpboot $loadaddr $uboot; " \ + "protect off " MK_STR(TEXT_BASE) " +$filesize; " \ + "erase " MK_STR(TEXT_BASE) " +$filesize; " \ + "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \ + "protect on " MK_STR(TEXT_BASE) " +$filesize; " \ + "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \ "consoledev=ttyS0\0" \ "ramdiskaddr=2000000\0" \ - "ramdiskfile=8544ds_tmt/ramdisk.uboot\0" \ - "fdtaddr=400000\0" \ - "fdtfile=8544ds_tmt/mpc8544ds.dtb\0" \ - "eoi=mw e00400b0 0\0" \ - "iack=md e00400a0 1\0" \ + "ramdiskfile=8544ds/ramdisk.uboot\0" \ + "dtbaddr=c00000\0" \ + "dtbfile=8544ds/mpc8544ds.dtb\0" \ + "bdev=sda3\0" \ + "eoi=mw e00400b0 0\0" \ + "iack=md e00400a0 1\0" \ "ddrreg=md ${a}000 8; md ${a}080 8;md ${a}100 d; md ${a}140 4; md ${a}bf0 4;" \ "md ${a}e00 3; md ${a}e20 3; md ${a}e40 7; md ${a}f00 5\0" \ - "ddrregs=setenv a e0002; run ddrreg\0" \ + "ddrregs=setenv a e0002; run ddrreg\0" \ "gureg=md ${a}000 2c; md ${a}0b0 1; md ${a}0c0 1; md ${a}b20 3;" \ - "md ${a}e00 1; md ${a}e60 1; md ${a}ef0 15\0" \ - "guregs=setenv a e00e0; run gureg\0" \ + "md ${a}e00 1; md ${a}e60 1; md ${a}ef0 15\0" \ + "guregs=setenv a e00e0; run gureg\0" \ "ecmreg=md ${a}000 1; md ${a}010 1; md ${a}bf8 2; md ${a}e00 6\0" \ - "ecmregs=setenv a e0001; run ecmreg\0" \ - PCIE_ENV \ - PCI_ENV \ + "ecmregs=setenv a e0001; run ecmreg\0" \ + "lawregs=md e0000c08 4b\0" \ + "lbcregs=md e0005000 36\0" \ + "dma0regs=md e0021100 12\0" \ + "dma1regs=md e0021180 12\0" \ + "dma2regs=md e0021200 12\0" \ + "dma3regs=md e0021280 12\0" \ + PCIE_ENV \ + PCI_ENV \ ENET_ENV @@ -579,23 +602,23 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ "console=$consoledev,$baudrate $othbootargs;" \ "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr - $fdtaddr" + "tftp $dtbaddr $dtbfile;" \ + "bootm $loadaddr - $dtbaddr" -#define CONFIG_RAMBOOTCOMMAND \ +#define CONFIG_RAMBOOTCOMMAND \ "setenv bootargs root=/dev/ram rw " \ "console=$consoledev,$baudrate $othbootargs;" \ "tftp $ramdiskaddr $ramdiskfile;" \ "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr $ramdiskaddr $fdtaddr" + "tftp $dtbaddr $dtbfile;" \ + "bootm $loadaddr $ramdiskaddr $dtbaddr" -#define CONFIG_BOOTCOMMAND \ - "setenv bootargs root=/dev/sda3 rw " \ +#define CONFIG_BOOTCOMMAND \ + "setenv bootargs root=/dev/$bdev rw " \ "console=$consoledev,$baudrate $othbootargs;" \ "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr - $fdtaddr" + "tftp $dtbaddr $dtbfile;" \ + "bootm $loadaddr - $dtbaddr" #endif /* __CONFIG_H */ From f2cff6b104f82b993bef6086ce0c97159bbe1add Mon Sep 17 00:00:00 2001 From: Ed Swarthout Date: Fri, 27 Jul 2007 01:50:52 -0500 Subject: [PATCH 096/259] 8548cds PCIE support. Make the early L1 cache stack region guarded to prevent speculative fetches outside the locked range. Use _PHYS defines, not _MEM for cpu-side PCI memory mapped regions. init.S whitespace cleanup. Allow TEXT_BASE value to be specified on command line. This allows it to be set to 0xfffc0000 which cuts the uboot binary in half. Clear and enable lbc and ecm errors. Update last_busno in device-tree for pci and pcie. Remove load of obsolete cpu/mpc85xx/pci.0 Signed-off-by: Ed Swarthout Acked-by: Andy Fleming --- board/cds/mpc8548cds/config.mk | 4 +- board/cds/mpc8548cds/init.S | 168 +++++++-------- board/cds/mpc8548cds/mpc8548cds.c | 237 ++++++++++++++++++--- board/cds/mpc8548cds/u-boot.lds | 3 +- include/configs/MPC8548CDS.h | 335 ++++++++++++++++++++---------- 5 files changed, 524 insertions(+), 223 deletions(-) diff --git a/board/cds/mpc8548cds/config.mk b/board/cds/mpc8548cds/config.mk index 242a67620..b23bc8737 100644 --- a/board/cds/mpc8548cds/config.mk +++ b/board/cds/mpc8548cds/config.mk @@ -1,5 +1,5 @@ # -# Copyright 2004 Freescale Semiconductor. +# Copyright 2004, 2007 Freescale Semiconductor. # # See file CREDITS for list of people who contributed to this # project. @@ -23,7 +23,9 @@ # # mpc8548cds board # +ifndef TEXT_BASE TEXT_BASE = 0xfff80000 +endif PLATFORM_CPPFLAGS += -DCONFIG_E500=1 PLATFORM_CPPFLAGS += -DCONFIG_MPC85xx=1 diff --git a/board/cds/mpc8548cds/init.S b/board/cds/mpc8548cds/init.S index d468f5b61..72940b035 100644 --- a/board/cds/mpc8548cds/init.S +++ b/board/cds/mpc8548cds/init.S @@ -1,5 +1,5 @@ /* - * Copyright 2004 Freescale Semiconductor. + * Copyright 2004, 2007 Freescale Semiconductor. * Copyright 2002,2003, Motorola Inc. * * See file CREDITS for list of people who contributed to this @@ -28,6 +28,12 @@ #include #include +#define LAWAR_TRGT_PCI1 0x00000000 +#define LAWAR_TRGT_PCI2 0x00100000 +#define LAWAR_TRGT_PCIE 0x00200000 +#define LAWAR_TRGT_RIO 0x00c00000 +#define LAWAR_TRGT_LBC 0x00400000 +#define LAWAR_TRGT_DDR 0x00f00000 /* * TLB0 and TLB1 Entries @@ -47,8 +53,8 @@ */ #define entry_start \ - mflr r1 ; \ - bl 0f ; + mflr r1 ; \ + bl 0f ; #define entry_end \ 0: mflr r0 ; \ @@ -84,8 +90,8 @@ tlb1_entry: #endif /* - * TLB0 16K Cacheable, non-guarded - * 0xd001_0000 16K Temporary Global data for initialization + * TLB0 16K Cacheable, guarded + * Temporary Global data for initialization * * Use four 4K TLB0 entries. These entries must be cacheable * as they provide the bootstrap memory before the memory @@ -97,28 +103,28 @@ tlb1_entry: .long TLB1_MAS0(0, 0, 0) .long TLB1_MAS1(1, 0, 0, 0, 0) .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR), - 0,0,0,0,0,0,0,0) + 0,0,0,0,0,0,1,0) .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR), 0,0,0,0,0,1,0,1,0,1) .long TLB1_MAS0(0, 0, 0) .long TLB1_MAS1(1, 0, 0, 0, 0) .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 4 * 1024), - 0,0,0,0,0,0,0,0) + 0,0,0,0,0,0,1,0) .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 4 * 1024), 0,0,0,0,0,1,0,1,0,1) .long TLB1_MAS0(0, 0, 0) .long TLB1_MAS1(1, 0, 0, 0, 0) .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 8 * 1024), - 0,0,0,0,0,0,0,0) + 0,0,0,0,0,0,1,0) .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 8 * 1024), 0,0,0,0,0,1,0,1,0,1) .long TLB1_MAS0(0, 0, 0) .long TLB1_MAS1(1, 0, 0, 0, 0) .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 12 * 1024), - 0,0,0,0,0,0,0,0) + 0,0,0,0,0,0,1,0) .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 12 * 1024), 0,0,0,0,0,1,0,1,0,1) @@ -130,51 +136,44 @@ tlb1_entry: */ .long TLB1_MAS0(1, 0, 0) .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M) - .long TLB1_MAS2(E500_TLB_EPN(CFG_FLASH_BASE), 0,0,0,0,1,0,1,0) - .long TLB1_MAS3(E500_TLB_RPN(CFG_FLASH_BASE), 0,0,0,0,0,1,0,1,0,1) + .long TLB1_MAS2(E500_TLB_EPN(CFG_BOOT_BLOCK), 0,0,0,0,1,0,1,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_BOOT_BLOCK), 0,0,0,0,0,1,0,1,0,1) /* - * TLB 1: 256M Non-cacheable, guarded - * 0x80000000 256M PCI1 MEM + * TLB 1: 1G Non-cacheable, guarded + * 0x80000000 1G PCI1/PCIE 8,9,a,b */ .long TLB1_MAS0(1, 1, 0) - .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) - .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE), 0,0,0,0,1,0,1,0) - .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE), 0,0,0,0,0,1,0,1,0,1) + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1G) + .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI_PHYS), 0,0,0,0,1,0,1,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI_PHYS), 0,0,0,0,0,1,0,1,0,1) +#ifdef CFG_RIO_MEM_PHYS /* * TLB 2: 256M Non-cacheable, guarded - * 0x90000000 256M PCI2 MEM */ .long TLB1_MAS0(1, 2, 0) .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) - .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI2_MEM_BASE), + .long TLB1_MAS2(E500_TLB_EPN(CFG_RIO_MEM_PHYS), 0,0,0,0,1,0,1,0) - .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI2_MEM_BASE), - 0,0,0,0,0,1,0,1,0,1) + .long TLB1_MAS3(E500_TLB_RPN(CFG_RIO_MEM_PHYS), 0,0,0,0,0,1,0,1,0,1) /* - * TLB 3: 1GB Non-cacheable, guarded - * 0xa0000000 256M PEX MEM First half - * 0xb0000000 256M PEX MEM Second half - * 0xc0000000 256M Rapid IO MEM First half - * 0xd0000000 256M Rapid IO MEM Second half + * TLB 3: 256M Non-cacheable, guarded */ .long TLB1_MAS0(1, 3, 0) - .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1G) - .long TLB1_MAS2(E500_TLB_EPN(CFG_PEX_MEM_BASE), 0,0,0,0,1,0,1,0) - .long TLB1_MAS3(E500_TLB_RPN(CFG_PEX_MEM_BASE), 0,0,0,0,0,1,0,1,0,1) - - /* - * TLB 4: Reserved for future usage - */ - + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) + .long TLB1_MAS2(E500_TLB_EPN(CFG_RIO_MEM_PHYS + 0x10000000), + 0,0,0,0,1,0,1,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_RIO_MEM_PHYS + 0x10000000), + 0,0,0,0,0,1,0,1,0,1) +#endif /* * TLB 5: 64M Non-cacheable, guarded * 0xe000_0000 1M CCSRBAR - * 0xe200_0000 8M PCI1 IO - * 0xe280_0000 8M PCI2 IO - * 0xe300_0000 16M PEX IO + * 0xe200_0000 1M PCI1 IO + * 0xe210_0000 1M PCI2 IO + * 0xe300_0000 1M PCIe IO */ .long TLB1_MAS0(1, 5, 0) .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) @@ -187,17 +186,18 @@ tlb1_entry: */ .long TLB1_MAS0(1, 6, 0) .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) - .long TLB1_MAS2(E500_TLB_EPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,0,0,0) - .long TLB1_MAS3(E500_TLB_RPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,1,0,1,0,1) + .long TLB1_MAS2(E500_TLB_EPN(CFG_LBC_CACHE_BASE), 0,0,0,0,0,0,0,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_LBC_CACHE_BASE), 0,0,0,0,0,1,0,1,0,1) /* - * TLB 7: 1M Non-cacheable, guarded - * 0xf8000000 1M CADMUS registers + * TLB 7: 64M Non-cacheable, guarded + * 0xf8000000 64M CADMUS registers, relocated L2SRAM */ .long TLB1_MAS0(1, 7, 0) - .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1M) - .long TLB1_MAS2(E500_TLB_EPN(CADMUS_BASE_ADDR), 0,0,0,0,1,0,1,0) - .long TLB1_MAS3(E500_TLB_RPN(CADMUS_BASE_ADDR), 0,0,0,0,0,1,0,1,0,1) + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) + .long TLB1_MAS2(E500_TLB_EPN(CFG_LBC_NONCACHE_BASE), 0,0,0,0,1,0,1,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_LBC_NONCACHE_BASE), 0,0,0,0,0,1,0,1,0,1) + 2: entry_end @@ -205,14 +205,13 @@ tlb1_entry: * LAW(Local Access Window) configuration: * * 0x0000_0000 0x7fff_ffff DDR 2G - * 0x8000_0000 0x8fff_ffff PCI1 MEM 256M - * 0x9000_0000 0x9fff_ffff PCI2 MEM 256M - * 0xa000_0000 0xbfff_ffff PEX MEM 512M + * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M + * 0xa000_0000 0xbfff_ffff PCIe MEM 512M * 0xc000_0000 0xdfff_ffff RapidIO 512M * 0xe000_0000 0xe000_ffff CCSR 1M - * 0xe200_0000 0xe27f_ffff PCI1 IO 8M - * 0xe280_0000 0xe2ff_ffff PCI2 IO 8M - * 0xe300_0000 0xe3ff_ffff PEX IO 16M + * 0xe200_0000 0xe10f_ffff PCI1 IO 1M + * 0xe280_0000 0xe20f_ffff PCI2 IO 1M + * 0xe300_0000 0xe30f_ffff PCIe IO 1M * 0xf000_0000 0xf3ff_ffff SDRAM 64M * 0xf800_0000 0xf80f_ffff NVRAM/CADMUS (*) 1M * 0xff00_0000 0xff7f_ffff FLASH (2nd bank) 8M @@ -222,47 +221,50 @@ tlb1_entry: * CCSRBAR and L2-as-SRAM don't need a configured Local Access Window. * If flash is 8M at default position (last 8M), no LAW needed. * - * The defines below are 1-off of the actual LAWAR0 usage. - * So LAWAR3 define uses the LAWAR4 register in the ECM. + * LAW 0 is reserved for boot mapping */ -#define LAWBAR0 0 -#define LAWAR0 ((LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN) - -#define LAWBAR1 ((CFG_PCI1_MEM_BASE>>12) & 0xfffff) -#define LAWAR1 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_256M)) - -#define LAWBAR2 ((CFG_PCI2_MEM_BASE>>12) & 0xfffff) -#define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_256M)) - -#define LAWBAR3 ((CFG_PCI1_IO_PHYS>>12) & 0xfffff) -#define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_8M)) - -#define LAWBAR4 ((CFG_PCI2_IO_PHYS>>12) & 0xfffff) -#define LAWAR4 (LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_8M)) - -/* LBC window - maps 256M 0xf0000000 -> 0xffffffff */ -#define LAWBAR5 ((CFG_LBC_SDRAM_BASE>>12) & 0xfffff) -#define LAWAR5 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M)) - -#define LAWBAR6 ((CFG_PEX_MEM_BASE>>12) & 0xfffff) -#define LAWAR6 (LAWAR_EN | LAWAR_TRGT_IF_PEX | (LAWAR_SIZE & LAWAR_SIZE_512M)) - -#define LAWBAR7 ((CFG_PEX_IO_PHYS>>12) & 0xfffff) -#define LAWAR7 (LAWAR_EN | LAWAR_TRGT_IF_PEX | (LAWAR_SIZE & LAWAR_SIZE_16M)) - -#define LAWBAR8 ((CFG_RIO_MEM_BASE>>12) & 0xfffff) -#define LAWAR8 (LAWAR_EN | LAWAR_TRGT_IF_RIO | (LAWAR_SIZE & LAWAR_SIZE_512M)) - .section .bootpg, "ax" .globl law_entry - law_entry: entry_start + .long (4f-3f)/8 3: - .long LAWBAR0,LAWAR0,LAWBAR1,LAWAR1,LAWBAR2,LAWAR2,LAWBAR3,LAWAR3 - .long LAWBAR4,LAWAR4,LAWBAR5,LAWAR5,LAWBAR6,LAWAR6,LAWBAR7,LAWAR7 - .long LAWBAR8,LAWAR8 + .long 0 + .long (LAWAR_TRGT_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN + +#ifdef CFG_PCI1_MEM_PHYS + .long (CFG_PCI1_MEM_PHYS>>12) & 0xfffff + .long LAWAR_EN | LAWAR_TRGT_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_512M) + + .long (CFG_PCI1_IO_PHYS>>12) & 0xfffff + .long LAWAR_EN | LAWAR_TRGT_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_1M) +#endif + +#ifdef CFG_PCI2_MEM_PHYS + .long (CFG_PCI2_MEM_PHYS>>12) & 0xfffff + .long LAWAR_EN | LAWAR_TRGT_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_512M) + + .long (CFG_PCI2_IO_PHYS>>12) & 0xfffff + .long LAWAR_EN | LAWAR_TRGT_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_1M) +#endif + +#ifdef CFG_PCIE1_MEM_PHYS + .long (CFG_PCIE1_MEM_PHYS>>12) & 0xfffff + .long LAWAR_EN | LAWAR_TRGT_PCIE | (LAWAR_SIZE & LAWAR_SIZE_512M) + + .long (CFG_PCIE1_IO_PHYS>>12) & 0xfffff + .long LAWAR_EN | LAWAR_TRGT_PCIE | (LAWAR_SIZE & LAWAR_SIZE_1M) +#endif + + /* LBC window - maps 256M 0xf0000000 -> 0xffffffff */ + .long (CFG_LBC_CACHE_BASE>>12) & 0xfffff + .long LAWAR_EN | LAWAR_TRGT_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M) + +#ifdef CFG_RIO_MEM_PHYS + .long (CFG_RIO_MEM_PHYS>>12) & 0xfffff + .long LAWAR_EN | LAWAR_TRGT_RIO | (LAWAR_SIZE & LAWAR_SIZE_512M) +#endif 4: entry_end diff --git a/board/cds/mpc8548cds/mpc8548cds.c b/board/cds/mpc8548cds/mpc8548cds.c index b7236417e..242a68c39 100644 --- a/board/cds/mpc8548cds/mpc8548cds.c +++ b/board/cds/mpc8548cds/mpc8548cds.c @@ -1,5 +1,5 @@ /* - * Copyright 2004 Freescale Semiconductor. + * Copyright 2004, 2007 Freescale Semiconductor. * * (C) Copyright 2002 Scott McNutt * @@ -26,6 +26,7 @@ #include #include #include +#include #include #include @@ -33,10 +34,15 @@ #include "../common/eeprom.h" #include "../common/via.h" +#if defined(CONFIG_OF_FLAT_TREE) +#include +#endif #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) extern void ddr_enable_ecc(unsigned int dram_size); #endif +DECLARE_GLOBAL_DATA_PTR; + extern long int spd_sdram(void); void local_bus_init(void); @@ -56,13 +62,6 @@ int checkboard (void) /* PCI slot in USER bits CSR[6:7] by convention. */ uint pci_slot = get_pci_slot (); - uint pci_dual = get_pci_dual (); /* PCI DUAL in CM_PCI[3] */ - uint pci1_32 = gur->pordevsr & 0x10000; /* PORDEVSR[15] */ - uint pci1_clk_sel = gur->porpllsr & 0x8000; /* PORPLLSR[16] */ - uint pci2_clk_sel = gur->porpllsr & 0x4000; /* PORPLLSR[17] */ - - uint pci1_speed = get_clock_freq (); /* PCI PSPEED in [4:5] */ - uint cpu_board_rev = get_cpu_board_revision (); printf ("Board: CDS Version 0x%02x, PCI Slot %d\n", @@ -71,20 +70,6 @@ int checkboard (void) printf ("CPU Board Revision %d.%d (0x%04x)\n", MPC85XX_CPU_BOARD_MAJOR (cpu_board_rev), MPC85XX_CPU_BOARD_MINOR (cpu_board_rev), cpu_board_rev); - - printf (" PCI1: %d bit, %s MHz, %s\n", - (pci1_32) ? 32 : 64, - (pci1_speed == 33000000) ? "33" : - (pci1_speed == 66000000) ? "66" : "unknown", - pci1_clk_sel ? "sync" : "async"); - - if (pci_dual) { - printf (" PCI2: 32 bit, 66 MHz, %s\n", - pci2_clk_sel ? "sync" : "async"); - } else { - printf (" PCI2: disabled\n"); - } - /* * Initialize local bus. */ @@ -102,6 +87,8 @@ int checkboard (void) */ gur->tsec34ioovcr = 0xe7e0; /* 1110 0111 1110 0xxx */ + ecm->eedr = 0xffffffff; /* clear ecm errors */ + ecm->eeer = 0xffffffff; /* enable ecm errors */ return 0; } @@ -176,6 +163,9 @@ local_bus_init(void) lbc->lcrr |= 0x00030000; asm("sync;isync;msync"); + + lbc->ltesr = 0xffffffff; /* Clear LBC error interrupts */ + lbc->lteir = 0xffffffff; /* Enable LBC error interrupts */ } /* @@ -301,7 +291,7 @@ testdram(void) } #endif -#if defined(CONFIG_PCI) +#if defined(CONFIG_PCI) || defined(CONFIG_PCI1) /* For some reason the Tundra PCI bridge shows up on itself as a * different device. Work around that by refusing to configure it. */ @@ -320,21 +310,175 @@ static struct pci_config_table pci_mpc85xxcds_config_table[] = { {}, }; -static struct pci_controller hose[] = { - { config_table: pci_mpc85xxcds_config_table,}, -#ifdef CONFIG_MPC85XX_PCI2 - {}, -#endif -}; - +static struct pci_controller pci1_hose = { + config_table: pci_mpc85xxcds_config_table}; #endif /* CONFIG_PCI */ +#ifdef CONFIG_PCI2 +static struct pci_controller pci2_hose; +#endif /* CONFIG_PCI2 */ + +#ifdef CONFIG_PCIE1 +static struct pci_controller pcie1_hose; +#endif /* CONFIG_PCIE1 */ + +int first_free_busno=0; + void pci_init_board(void) { -#ifdef CONFIG_PCI - pci_mpc85xx_init(&hose); + volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile ccsr_gur_t *gur = &immap->im_gur; + uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19; + uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16; + + +#ifdef CONFIG_PCI1 +{ + volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCI1_ADDR; + extern void fsl_pci_init(struct pci_controller *hose); + struct pci_controller *hose = &pci1_hose; + struct pci_config_table *table; + + uint pci_32 = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_PCI32; /* PORDEVSR[15] */ + uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; /* PORDEVSR[14] */ + uint pci_clk_sel = gur->porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; /* PORPLLSR[16] */ + + uint pci_agent = (host_agent == 3) || (host_agent == 4 ) || (host_agent == 6); + + uint pci_speed = get_clock_freq (); /* PCI PSPEED in [4:5] */ + + if (!(gur->devdisr & MPC85xx_DEVDISR_PCI1)) { + printf (" PCI: %d bit, %s MHz, %s, %s, %s\n", + (pci_32) ? 32 : 64, + (pci_speed == 33333000) ? "33" : + (pci_speed == 66666000) ? "66" : "unknown", + pci_clk_sel ? "sync" : "async", + pci_agent ? "agent" : "host", + pci_arb ? "arbiter" : "external-arbiter" + ); + + + /* outbound memory */ + pci_set_region(hose->regions + 0, + CFG_PCI1_MEM_BASE, + CFG_PCI1_MEM_PHYS, + CFG_PCI1_MEM_SIZE, + PCI_REGION_MEM); + + /* outbound io */ + pci_set_region(hose->regions + 1, + CFG_PCI1_IO_BASE, + CFG_PCI1_IO_PHYS, + CFG_PCI1_IO_SIZE, + PCI_REGION_IO); + hose->region_count = 2; + + /* relocate config table pointers */ + hose->config_table = \ + (struct pci_config_table *)((uint)hose->config_table + gd->reloc_off); + for (table = hose->config_table; table && table->vendor; table++) + table->config_device += gd->reloc_off; + + hose->first_busno=first_free_busno; + pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); + + fsl_pci_init(hose); + first_free_busno=hose->last_busno+1; + printf ("PCI on bus %02x - %02x\n",hose->first_busno,hose->last_busno); +#ifdef CONFIG_PCIX_CHECK + if (!(gur->pordevsr & PORDEVSR_PCI)) { + /* PCI-X init */ + if (CONFIG_SYS_CLK_FREQ < 66000000) + printf("PCI-X will only work at 66 MHz\n"); + + reg16 = PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ + | PCI_X_CMD_ERO | PCI_X_CMD_DPERR_E; + pci_hose_write_config_word(hose, bus, PCIX_COMMAND, reg16); + } #endif + } else { + printf (" PCI: disabled\n"); + } +} +#else + gur->devdisr |= MPC85xx_DEVDISR_PCI1; /* disable */ +#endif + +#ifdef CONFIG_PCI2 +{ + uint pci2_clk_sel = gur->porpllsr & 0x4000; /* PORPLLSR[17] */ + uint pci_dual = get_pci_dual (); /* PCI DUAL in CM_PCI[3] */ + if (pci_dual) { + printf (" PCI2: 32 bit, 66 MHz, %s\n", + pci2_clk_sel ? "sync" : "async"); + } else { + printf (" PCI2: disabled\n"); + } +} +#else + gur->devdisr |= MPC85xx_DEVDISR_PCI2; /* disable */ +#endif /* CONFIG_PCI2 */ + +#ifdef CONFIG_PCIE1 +{ + volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE1_ADDR; + extern void fsl_pci_init(struct pci_controller *hose); + struct pci_controller *hose = &pcie1_hose; + int pcie_ep = (host_agent == 0) || (host_agent == 2 ) || (host_agent == 3); + + int pcie_configured = io_sel >= 1; + + if (pcie_configured && !(gur->devdisr & MPC85xx_DEVDISR_PCIE)){ + printf ("\n PCIE connected to slot as %s (base address %x)", + pcie_ep ? "End Point" : "Root Complex", + (uint)pci); + + if (pci->pme_msg_det) { + pci->pme_msg_det = 0xffffffff; + debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det); + } + printf ("\n"); + + /* inbound */ + pci_set_region(hose->regions + 0, + CFG_PCI_MEMORY_BUS, + CFG_PCI_MEMORY_PHYS, + CFG_PCI_MEMORY_SIZE, + PCI_REGION_MEM | PCI_REGION_MEMORY); + + /* outbound memory */ + pci_set_region(hose->regions + 1, + CFG_PCIE1_MEM_BASE, + CFG_PCIE1_MEM_PHYS, + CFG_PCIE1_MEM_SIZE, + PCI_REGION_MEM); + + /* outbound io */ + pci_set_region(hose->regions + 2, + CFG_PCIE1_IO_BASE, + CFG_PCIE1_IO_PHYS, + CFG_PCIE1_IO_SIZE, + PCI_REGION_IO); + + hose->region_count = 3; + + hose->first_busno=first_free_busno; + pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); + + fsl_pci_init(hose); + printf ("PCIE on bus %d - %d\n",hose->first_busno,hose->last_busno); + + first_free_busno=hose->last_busno+1; + + } else { + printf (" PCIE: disabled\n"); + } + } +#else + gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */ +#endif + } int last_stage_init(void) @@ -367,3 +511,32 @@ int last_stage_init(void) return 0; } + + +#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP) +void +ft_pci_setup(void *blob, bd_t *bd) +{ + u32 *p; + int len; + + +#ifdef CONFIG_PCI1 + p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@8000/bus-range", &len); + if (p != NULL) { + p[0] = 0; + p[1] = pci1_hose.last_busno - pci1_hose.first_busno; + debug("PCI@8000 first_busno=%d last_busno=%d\n",p[0],p[1]); + } +#endif + +#ifdef CONFIG_PCIE1 + p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@a000/bus-range", &len); + if (p != NULL) { + p[0] = 0; + p[1] = pcie1_hose.last_busno - pcie1_hose.first_busno; + debug("PCI@a000 first_busno=%d last_busno=%d\n",p[0],p[1]); + } +#endif +} +#endif diff --git a/board/cds/mpc8548cds/u-boot.lds b/board/cds/mpc8548cds/u-boot.lds index c1f3495d7..530ba5a72 100644 --- a/board/cds/mpc8548cds/u-boot.lds +++ b/board/cds/mpc8548cds/u-boot.lds @@ -1,5 +1,5 @@ /* - * Copyright 2004 Freescale Semiconductor. + * Copyright 2004, 2007 Freescale Semiconductor. * * See file CREDITS for list of people who contributed to this * project. @@ -71,7 +71,6 @@ SECTIONS cpu/mpc85xx/cpu.o (.text) drivers/tsec.o (.text) cpu/mpc85xx/speed.o (.text) - cpu/mpc85xx/pci.o (.text) common/dlmalloc.o (.text) lib_generic/crc32.o (.text) lib_ppc/extable.o (.text) diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h index 2e84fc874..d7afdbd60 100644 --- a/include/configs/MPC8548CDS.h +++ b/include/configs/MPC8548CDS.h @@ -1,5 +1,5 @@ /* - * Copyright 2004 Freescale Semiconductor. + * Copyright 2004, 2007 Freescale Semiconductor. * * See file CREDITS for list of people who contributed to this * project. @@ -11,7 +11,7 @@ * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License @@ -36,8 +36,14 @@ #define CONFIG_MPC8548 1 /* MPC8548 specific */ #define CONFIG_MPC8548CDS 1 /* MPC8548CDS board specific */ -#define CONFIG_PCI -#define CONFIG_TSEC_ENET /* tsec ethernet support */ +#define CONFIG_PCI /* enable any pci type devices */ +#define CONFIG_PCI1 /* PCI controller 1 */ +#define CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */ +#undef CONFIG_RIO +#undef CONFIG_PCI2 +#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ + +#define CONFIG_TSEC_ENET /* tsec ethernet support */ #define CONFIG_ENV_OVERWRITE #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ #define CONFIG_DDR_DLL /* possible DLL fix needed */ @@ -46,6 +52,7 @@ #define CONFIG_DDR_ECC /* only for ECC DDR module */ #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ #define CONFIG_MEM_INIT_VALUE 0xDeadBeef +#define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */ /* @@ -65,16 +72,16 @@ extern unsigned long get_clock_freq(void); /* * These can be toggled for performance analysis, otherwise use default. */ -#define CONFIG_L2_CACHE /* toggle L2 cache */ -#define CONFIG_BTB /* toggle branch predition */ -#define CONFIG_ADDR_STREAMING /* toggle addr streaming */ +#define CONFIG_L2_CACHE /* toggle L2 cache */ +#define CONFIG_BTB /* toggle branch predition */ +#define CONFIG_ADDR_STREAMING /* toggle addr streaming */ +#define CONFIG_CLEAR_LAW0 /* Clear LAW0 in cpu_init_r */ /* * Only possible on E500 Version 2 or newer cores. */ #define CONFIG_ENABLE_36BIT_PHYS 1 - #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ #undef CFG_DRAM_TEST /* memory test, takes time */ @@ -85,10 +92,14 @@ extern unsigned long get_clock_freq(void); * Base addresses -- Note these are effective addresses where the * actual resources get mapped (not physical addresses) */ -#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ +#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ #define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ #define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ +#define CFG_PCI1_ADDR (CFG_CCSRBAR+0x8000) +#define CFG_PCI2_ADDR (CFG_CCSRBAR+0x9000) +#define CFG_PCIE1_ADDR (CFG_CCSRBAR+0xa000) + /* * DDR Setup */ @@ -106,7 +117,6 @@ extern unsigned long get_clock_freq(void); #undef CONFIG_CLOCKS_IN_MHZ - /* * Local Bus Definitions */ @@ -124,9 +134,9 @@ extern unsigned long get_clock_freq(void); * Use GPCM = BRx[24:26] = 000 * Valid = BRx[31] = 1 * - * 0 4 8 12 16 20 24 28 - * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001 BR0 - * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001 BR1 + * 0 4 8 12 16 20 24 28 + * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001 BR0 + * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001 BR1 * * OR0, OR1: * Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0 @@ -137,11 +147,12 @@ extern unsigned long get_clock_freq(void); * TRLX = use relaxed timing = ORx[29] = 1 * EAD = use external address latch delay = OR[31] = 1 * - * 0 4 8 12 16 20 24 28 - * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 ORx + * 0 4 8 12 16 20 24 28 + * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 ORx */ -#define CFG_FLASH_BASE 0xff000000 /* start of FLASH 8M */ +#define CFG_BOOT_BLOCK 0xff000000 /* boot TLB block */ +#define CFG_FLASH_BASE CFG_BOOT_BLOCK /* start of FLASH 16M */ #define CFG_BR0_PRELIM 0xff801001 #define CFG_BR1_PRELIM 0xff001001 @@ -156,7 +167,7 @@ extern unsigned long get_clock_freq(void); #define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ -#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ +#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ #define CFG_FLASH_CFI_DRIVER #define CFG_FLASH_CFI @@ -166,7 +177,12 @@ extern unsigned long get_clock_freq(void); /* * SDRAM on the Local Bus */ -#define CFG_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ +#define CFG_LBC_CACHE_BASE 0xf0000000 /* Localbus cacheable */ +#define CFG_LBC_CACHE_SIZE 64 +#define CFG_LBC_NONCACHE_BASE 0xf8000000 /* Localbus non-cacheable */ +#define CFG_LBC_NONCACHE_SIZE 64 + +#define CFG_LBC_SDRAM_BASE CFG_LBC_CACHE_BASE /* Localbus SDRAM */ #define CFG_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ /* @@ -180,14 +196,14 @@ extern unsigned long get_clock_freq(void); * SDRAM for MSEL = BR2[24:26] = 011 * Valid = BR[31] = 1 * - * 0 4 8 12 16 20 24 28 + * 0 4 8 12 16 20 24 28 * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861 * * FIXME: CFG_LBC_SDRAM_BASE should be masked and OR'ed into * FIXME: the top 17 bits of BR2. */ -#define CFG_BR2_PRELIM 0xf0001861 +#define CFG_BR2_PRELIM 0xf0001861 /* * The SDRAM size in MB, CFG_LBC_SDRAM_SIZE, is 64. @@ -196,19 +212,19 @@ extern unsigned long get_clock_freq(void); * 64MB mask for AM, OR2[0:7] = 1111 1100 * XAM, OR2[17:18] = 11 * 9 columns OR2[19-21] = 010 - * 13 rows OR2[23-25] = 100 + * 13 rows OR2[23-25] = 100 * EAD set for extra time OR[31] = 1 * - * 0 4 8 12 16 20 24 28 + * 0 4 8 12 16 20 24 28 * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901 */ #define CFG_OR2_PRELIM 0xfc006901 -#define CFG_LBC_LCRR 0x00030004 /* LB clock ratio reg */ -#define CFG_LBC_LBCR 0x00000000 /* LB config reg */ -#define CFG_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ -#define CFG_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/ +#define CFG_LBC_LCRR 0x00030004 /* LB clock ratio reg */ +#define CFG_LBC_LBCR 0x00000000 /* LB config reg */ +#define CFG_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ +#define CFG_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/ /* * LSDMR masks @@ -236,7 +252,7 @@ extern unsigned long get_clock_freq(void); /* * Common settings for all Local Bus SDRAM commands. * At run time, either BSMA1516 (for CPU 1.1) - * or BSMA1617 (for CPU 1.0) (old) + * or BSMA1617 (for CPU 1.0) (old) * is OR'ed in too. */ #define CFG_LBC_LSDMR_COMMON ( CFG_LBC_LSDMR_RFCR16 \ @@ -256,61 +272,63 @@ extern unsigned long get_clock_freq(void); * Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0 * port-size = 8-bits = BR[19:20] = 01 * no parity checking = BR[21:22] = 00 - * GPMC for MSEL = BR[24:26] = 000 - * Valid = BR[31] = 1 + * GPMC for MSEL = BR[24:26] = 000 + * Valid = BR[31] = 1 * - * 0 4 8 12 16 20 24 28 + * 0 4 8 12 16 20 24 28 * 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801 * * For OR3, need: - * 1 MB mask for AM, OR[0:16] = 1111 1111 1111 0000 0 + * 1 MB mask for AM, OR[0:16] = 1111 1111 1111 0000 0 * disable buffer ctrl OR[19] = 0 - * CSNT OR[20] = 1 - * ACS OR[21:22] = 11 - * XACS OR[23] = 1 + * CSNT OR[20] = 1 + * ACS OR[21:22] = 11 + * XACS OR[23] = 1 * SCY 15 wait states OR[24:27] = 1111 max is suboptimal but safe - * SETA OR[28] = 0 - * TRLX OR[29] = 1 - * EHTR OR[30] = 1 - * EAD extra time OR[31] = 1 + * SETA OR[28] = 0 + * TRLX OR[29] = 1 + * EHTR OR[30] = 1 + * EAD extra time OR[31] = 1 * - * 0 4 8 12 16 20 24 28 + * 0 4 8 12 16 20 24 28 * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7 */ #define CADMUS_BASE_ADDR 0xf8000000 -#define CFG_BR3_PRELIM 0xf8000801 -#define CFG_OR3_PRELIM 0xfff00ff7 +#define CFG_BR3_PRELIM 0xf8000801 +#define CFG_OR3_PRELIM 0xfff00ff7 #define CONFIG_L1_INIT_RAM -#define CFG_INIT_RAM_LOCK 1 +#define CFG_INIT_RAM_LOCK 1 #define CFG_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ -#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */ +#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */ -#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ +#define CFG_INIT_L2_ADDR 0xf8f80000 /* relocate boot L2SRAM */ + +#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET -#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ -#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ +#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ +#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ /* Serial Port */ -#define CONFIG_CONS_INDEX 2 +#define CONFIG_CONS_INDEX 2 #undef CONFIG_SERIAL_SOFTWARE_FIFO #define CFG_NS16550 #define CFG_NS16550_SERIAL -#define CFG_NS16550_REG_SIZE 1 +#define CFG_NS16550_REG_SIZE 1 #define CFG_NS16550_CLK get_bus_freq(0) -#define CFG_BAUDRATE_TABLE \ +#define CFG_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} -#define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500) -#define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600) +#define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500) +#define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600) /* Use the HUSH parser */ #define CFG_HUSH_PARSER -#ifdef CFG_HUSH_PARSER +#ifdef CFG_HUSH_PARSER #define CFG_PROMPT_HUSH_PS2 "> " #endif @@ -331,55 +349,66 @@ extern unsigned long get_clock_freq(void); */ #define CONFIG_FSL_I2C /* Use FSL common I2C driver */ #define CONFIG_HARD_I2C /* I2C with hardware support*/ -#undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#undef CONFIG_SOFT_I2C /* I2C bit-banged */ #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ #define CFG_I2C_EEPROM_ADDR 0x57 #define CFG_I2C_SLAVE 0x7F -#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ +#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ #define CFG_I2C_OFFSET 0x3000 /* * General PCI * Memory space is mapped 1-1, but I/O space must start from 0. */ +#define CFG_PCI_PHYS 0x80000000 /* 1G PCI TLB */ + #define CFG_PCI1_MEM_BASE 0x80000000 #define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE -#define CFG_PCI1_MEM_SIZE 0x10000000 /* 256M */ +#define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */ #define CFG_PCI1_IO_BASE 0x00000000 #define CFG_PCI1_IO_PHYS 0xe2000000 -#define CFG_PCI1_IO_SIZE 0x00800000 /* 8M */ +#define CFG_PCI1_IO_SIZE 0x00100000 /* 1M */ -#define CFG_PCI2_MEM_BASE 0x90000000 +#ifdef CONFIG_PCI2 +#define CFG_PCI2_MEM_BASE 0xa0000000 #define CFG_PCI2_MEM_PHYS CFG_PCI2_MEM_BASE -#define CFG_PCI2_MEM_SIZE 0x10000000 /* 256M */ +#define CFG_PCI2_MEM_SIZE 0x20000000 /* 512M */ #define CFG_PCI2_IO_BASE 0x00000000 #define CFG_PCI2_IO_PHYS 0xe2800000 -#define CFG_PCI2_IO_SIZE 0x00800000 /* 8M */ +#define CFG_PCI2_IO_SIZE 0x00100000 /* 1M */ +#endif -#define CFG_PEX_MEM_BASE 0xa0000000 -#define CFG_PEX_MEM_PHYS CFG_PEX_MEM_BASE -#define CFG_PEX_MEM_SIZE 0x20000000 /* 512M */ -#define CFG_PEX_IO_BASE 0x00000000 -#define CFG_PEX_IO_PHYS 0xe3000000 -#define CFG_PEX_IO_SIZE 0x01000000 /* 16M */ +#ifdef CONFIG_PCIE1 +#define CFG_PCIE1_MEM_BASE 0xa0000000 +#define CFG_PCIE1_MEM_PHYS CFG_PCIE1_MEM_BASE +#define CFG_PCIE1_MEM_SIZE 0x20000000 /* 512M */ +#define CFG_PCIE1_IO_BASE 0x00000000 +#define CFG_PCIE1_IO_PHYS 0xe3000000 +#define CFG_PCIE1_IO_SIZE 0x00100000 /* 1M */ +#endif +#ifdef CONFIG_RIO /* * RapidIO MMU */ #define CFG_RIO_MEM_BASE 0xC0000000 #define CFG_RIO_MEM_SIZE 0x20000000 /* 512M */ +#endif #if defined(CONFIG_PCI) #define CONFIG_NET_MULTI -#define CONFIG_PCI_PNP /* do pci plug-and-play */ -#define CONFIG_85XX_PCI2 +#define CONFIG_PCI_PNP /* do pci plug-and-play */ #undef CONFIG_EEPRO100 #undef CONFIG_TULIP #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ -#define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ + +/* PCI view of System Memory */ +#define CFG_PCI_MEMORY_BUS 0x00000000 +#define CFG_PCI_MEMORY_PHYS 0x00000000 +#define CFG_PCI_MEMORY_SIZE 0x80000000 #endif /* CONFIG_PCI */ @@ -387,7 +416,7 @@ extern unsigned long get_clock_freq(void); #if defined(CONFIG_TSEC_ENET) #ifndef CONFIG_NET_MULTI -#define CONFIG_NET_MULTI 1 +#define CONFIG_NET_MULTI 1 #endif #define CONFIG_MII 1 /* MII PHY management */ @@ -397,7 +426,7 @@ extern unsigned long get_clock_freq(void); #define CONFIG_TSEC2_NAME "eTSEC1" #define CONFIG_TSEC3 1 #define CONFIG_TSEC3_NAME "eTSEC2" -#undef CONFIG_TSEC4 +#define CONFIG_TSEC4 #define CONFIG_TSEC4_NAME "eTSEC3" #undef CONFIG_MPC85XX_FEC @@ -413,7 +442,7 @@ extern unsigned long get_clock_freq(void); /* Options are: eTSEC[0-3] */ #define CONFIG_ETHPRIME "eTSEC0" - +#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ #endif /* CONFIG_TSEC_ENET */ /* @@ -473,7 +502,7 @@ extern unsigned long get_clock_freq(void); * have to be in the first 8 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ /* Cache Configuration */ #define CFG_DCACHE_SIZE 32768 @@ -501,58 +530,154 @@ extern unsigned long get_clock_freq(void); /* The mac addresses for all ethernet interface */ #if defined(CONFIG_TSEC_ENET) -#define CONFIG_ETHADDR 00:E0:0C:00:00:FD +#define CONFIG_ETHADDR 00:E0:0C:00:00:FD #define CONFIG_HAS_ETH1 -#define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD +#define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD #define CONFIG_HAS_ETH2 -#define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD +#define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD #define CONFIG_HAS_ETH3 -#define CONFIG_ETH3ADDR 00:E0:0C:00:03:FD +#define CONFIG_ETH3ADDR 00:E0:0C:00:03:FD #endif -#define CONFIG_IPADDR 192.168.1.253 +#define CONFIG_IPADDR 192.168.1.253 -#define CONFIG_HOSTNAME unknown -#define CONFIG_ROOTPATH /nfsroot -#define CONFIG_BOOTFILE your.uImage +#define CONFIG_HOSTNAME unknown +#define CONFIG_ROOTPATH /nfsroot +#define CONFIG_BOOTFILE 8548cds/uImage.uboot +#define CONFIG_UBOOTPATH 8548cds/u-boot.bin /* TFTP server */ -#define CONFIG_SERVERIP 192.168.1.1 +#define CONFIG_SERVERIP 192.168.1.1 #define CONFIG_GATEWAYIP 192.168.1.1 -#define CONFIG_NETMASK 255.255.255.0 +#define CONFIG_NETMASK 255.255.255.0 -#define CONFIG_LOADADDR 200000 /*default location for tftp and bootm*/ +#define CONFIG_LOADADDR 1000000 /*default location for tftp and bootm*/ -#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ -#undef CONFIG_BOOTARGS /* the boot command will set bootargs*/ +#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ +#undef CONFIG_BOOTARGS /* the boot command will set bootargs*/ #define CONFIG_BAUDRATE 115200 -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "consoledev=ttyS1\0" \ - "ramdiskaddr=600000\0" \ - "ramdiskfile=your.ramdisk.u-boot\0" \ - "fdtaddr=400000\0" \ - "fdtfile=your.fdt.dtb\0" +#if defined(CONFIG_PCIE1) +#define PCIE_ENV \ + "pciereg=md ${a}000 6; md ${a}020 4; md ${a}bf8 2; echo o;md ${a}c00 25;" \ + "echo i; md ${a}da0 15; echo e;md ${a}e00 e; echo d; md ${a}f00 c\0" \ + "pcieerr=md ${a}020 1; md ${a}e00 e; pci d.b $b.0 7 1; pci d.w $b.0 1e 1;" \ + "pci d.w $b.0 56 1; pci d $b.0 104 1; pci d $b.0 110 1;" \ + "pci d $b.0 130 1\0" \ + "pcieerrc=mw ${a}020 ffffffff; mw ${a}e00 ffffffff; pci w.b $b.0 7 ff;" \ + "pci w.w $b.0 1e ffff; pci w.w $b.0 56 ffff; pci w $b.0 104 ffffffff;"\ + "pci w $b.0 110 ffffffff; pci w $b.0 130 ffffffff\0" \ + "pciecfg=pci d $b.0 0 20; pci d $b.0 100 e; pci d $b.0 400 69\0" \ + "pcie1regs=setenv a e000a; run pciereg\0" \ + "pcie1cfg=setenv b 3; run pciecfg\0" \ + "pcie1err=setenv a e000a; setenv b 3; run pcieerr\0" \ + "pcie1errc=setenv a e000a; setenv b 3; run pcieerrc\0" +#else +#define PCIE_ENV "" +#endif + +#if defined(CONFIG_PCI1) || defined(CONFIG_PCI2) +#define PCI_ENV \ + "pcireg=md ${a}000 3; echo o;md ${a}c00 25; echo i; md ${a}da0 15;" \ + "echo e;md ${a}e00 9\0" \ + "pcierr=md ${a}e00 8; pci d.b $b.0 7 1;pci d.w $b.0 1e 1;" \ + "pci d.w $b.0 56 1\0" \ + "pcierrc=mw ${a}e00 ffffffff; mw ${a}e0c 0; pci w.b $b.0 7 ff;" \ + "pci w.w $b.0 1e ffff; pci w.w $b.0 56 ffff\0" +#else +#define PCI_ENV "" +#endif + +#if defined(CONFIG_PCI1) +#define PCI_ENV1 \ + "pci1regs=setenv a e0008; run pcireg\0" \ + "pci1err=setenv a e0008; setenv b 0; run pcierr\0" \ + "pci1errc=setenv a e0008; setenv b 0; run pcierrc\0" +#else +#define PCI_ENV1 "" +#endif + +#if defined(CONFIG_PCI2) +#define PCI_ENV2 \ + "pci2regs=setenv a e0009; run pcireg\0" \ + "pci2err=setenv a e0009; setenv b 123; run pcierr\0" \ + "pci2errc=setenv a e0009; setenv b 123; run pcierrc\0" +#else +#define PCI_ENV2 "" +#endif + +#if defined(CONFIG_TSEC_ENET) +#define ENET_ENV \ + "enetreg1=md ${a}000 2; md ${a}010 9; md ${a}050 4; md ${a}08c 1;" \ + "md ${a}098 2\0" \ + "enetregt=echo t;md ${a}100 6; md ${a}140 2; md ${a}180 10; md ${a}200 10\0" \ + "enetregr=echo r;md ${a}300 6; md ${a}330 5; md ${a}380 10; md ${a}400 10\0" \ + "enetregm=echo mac;md ${a}500 5; md ${a}520 28;echo fifo;md ${a}a00 1;" \ + "echo mib;md ${a}680 31\0" \ + "enetreg=run enetreg1; run enetregm; run enetregt; run enetregr\0" \ + "enet1regs=setenv a e0024; run enetreg\0" \ + "enet2regs=setenv a e0025; run enetreg\0" \ + "enet3regs=setenv a e0026; run enetreg\0" \ + "enet4regs=setenv a e0027; run enetreg\0" +#else +#define ENET_ENV "" +#endif + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ + "tftpflash=tftpboot $loadaddr $uboot; " \ + "protect off " MK_STR(TEXT_BASE) " +$filesize; " \ + "erase " MK_STR(TEXT_BASE) " +$filesize; " \ + "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \ + "protect on " MK_STR(TEXT_BASE) " +$filesize; " \ + "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \ + "consoledev=ttyS1\0" \ + "ramdiskaddr=2000000\0" \ + "ramdiskfile=mpc8548cds\ramdisk.uboot\0" \ + "dtbaddr=c00000\0" \ + "dtbfile=mpc8548cds\mpc8548cds.dtb\0" \ + "eoi=mw e00400b0 0\0" \ + "iack=md e00400a0 1\0" \ + "ddrreg=md ${a}000 8; md ${a}080 8;md ${a}100 d; md ${a}140 4; md ${a}bf0 4;" \ + "md ${a}e00 3; md ${a}e20 3; md ${a}e40 7; md ${a}f00 5\0" \ + "ddrregs=setenv a e0002; run ddrreg\0" \ + "gureg=md ${a}000 2c; md ${a}0b0 1; md ${a}0c0 1; md ${a}b20 3;" \ + "md ${a}e00 1; md ${a}e60 1; md ${a}ef0 15\0" \ + "guregs=setenv a e00e0; run gureg\0" \ + "ecmreg=md ${a}000 1; md ${a}010 1; md ${a}bf8 2; md ${a}e00 6\0" \ + "ecmregs=setenv a e0001; run ecmreg\0" \ + "lawregs=md e0000c08 4b\0" \ + "lbcregs=md e0005000 36\0" \ + "dma0regs=md e0021100 12\0" \ + "dma1regs=md e0021180 12\0" \ + "dma2regs=md e0021200 12\0" \ + "dma3regs=md e0021280 12\0" \ + PCIE_ENV \ + PCI_ENV \ + PCI_ENV1 \ + PCI_ENV2 \ + ENET_ENV -#define CONFIG_NFSBOOTCOMMAND \ - "setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$serverip:$rootpath " \ +#define CONFIG_NFSBOOTCOMMAND \ + "setenv bootargs root=/dev/nfs rw " \ + "nfsroot=$serverip:$rootpath " \ "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr - $fdtaddr" + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $dtbaddr $dtbfile;" \ + "bootm $loadaddr - $dtbaddr" #define CONFIG_RAMBOOTCOMMAND \ - "setenv bootargs root=/dev/ram rw " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $ramdiskaddr $ramdiskfile;" \ - "tftp $loadaddr $bootfile;" \ - "bootm $loadaddr $ramdiskaddr" + "setenv bootargs root=/dev/ram rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $ramdiskaddr $ramdiskfile;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $dtbaddr $dtbfile;" \ + "bootm $loadaddr $ramdiskaddr $dtbaddr" -#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND +#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND #endif /* __CONFIG_H */ From 6c543597bb4b1ecf5d8589f7abb0f39929fb7fd1 Mon Sep 17 00:00:00 2001 From: Andy Fleming Date: Mon, 13 Aug 2007 14:38:06 -0500 Subject: [PATCH 097/259] Fix minor 85xx warnings Some patches had inserted warnings into the build: * mpc8560ads declared data without using it * cpu_init declared ecm and immap without using it in all CONFIGs * MPC8548CDS.h had its default filenames changed so that they contained "\m" in the paths. Made the defaults not Windows-specific (or anything-specific) Signed-off-by: Andy Fleming --- board/mpc8560ads/mpc8560ads.c | 1 - cpu/mpc85xx/cpu_init.c | 4 +++- include/configs/MPC8548CDS.h | 6 ++++-- 3 files changed, 7 insertions(+), 4 deletions(-) diff --git a/board/mpc8560ads/mpc8560ads.c b/board/mpc8560ads/mpc8560ads.c index 41acb97af..eef524b45 100644 --- a/board/mpc8560ads/mpc8560ads.c +++ b/board/mpc8560ads/mpc8560ads.c @@ -554,7 +554,6 @@ ft_soc_setup(void *blob, bd_t *bd) { u32 *p; int len; - ulong data; p = ft_get_prop(blob, "/" OF_SOC "/cpm@e0000000/brg-frequency", &len); diff --git a/cpu/mpc85xx/cpu_init.c b/cpu/mpc85xx/cpu_init.c index 888417f86..c7fe130ee 100644 --- a/cpu/mpc85xx/cpu_init.c +++ b/cpu/mpc85xx/cpu_init.c @@ -194,10 +194,12 @@ void cpu_init_f (void) int cpu_init_r(void) { +#if defined(CONFIG_CLEAR_LAW0) || defined(CONFIG_L2_CACHE) volatile immap_t *immap = (immap_t *)CFG_IMMR; +#endif +#ifdef CONFIG_CLEAR_LAW0 volatile ccsr_local_ecm_t *ecm = &immap->im_local_ecm; -#ifdef CONFIG_CLEAR_LAW0 /* clear alternate boot location LAW (used for sdram, or ddr bank) */ ecm->lawar0 = 0; #endif diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h index d7afdbd60..dfe4f5b7a 100644 --- a/include/configs/MPC8548CDS.h +++ b/include/configs/MPC8548CDS.h @@ -623,6 +623,7 @@ extern unsigned long get_clock_freq(void); #define ENET_ENV "" #endif +#if 0 #define CONFIG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0" \ "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ @@ -634,9 +635,9 @@ extern unsigned long get_clock_freq(void); "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \ "consoledev=ttyS1\0" \ "ramdiskaddr=2000000\0" \ - "ramdiskfile=mpc8548cds\ramdisk.uboot\0" \ + "ramdiskfile=ramdisk.uboot\0" \ "dtbaddr=c00000\0" \ - "dtbfile=mpc8548cds\mpc8548cds.dtb\0" \ + "dtbfile=mpc8548cds.dtb\0" \ "eoi=mw e00400b0 0\0" \ "iack=md e00400a0 1\0" \ "ddrreg=md ${a}000 8; md ${a}080 8;md ${a}100 d; md ${a}140 4; md ${a}bf0 4;" \ @@ -658,6 +659,7 @@ extern unsigned long get_clock_freq(void); PCI_ENV1 \ PCI_ENV2 \ ENET_ENV +#endif #define CONFIG_NFSBOOTCOMMAND \ From 39980c610c9a4c381907c9e1d1b9c0e1c0dca57a Mon Sep 17 00:00:00 2001 From: Andy Fleming Date: Mon, 13 Aug 2007 14:49:59 -0500 Subject: [PATCH 098/259] MPC85xx BA bits not set for 3-bit bank address DIMM The current implementation does not set the number of bank address bits (BA) in the processor. The default assumes 2 logical bank bits. This works fine for a DIMM that uses devices with 4 internal banks (SPD byte17 = 0x4) but needs to be set appropriately for a DIMM that uses devices with 8 internal banks (SPD byte17 = 0x8). Signed-off-by: Greg Davis --- cpu/mpc85xx/spd_sdram.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/cpu/mpc85xx/spd_sdram.c b/cpu/mpc85xx/spd_sdram.c index d98455401..679f3608f 100644 --- a/cpu/mpc85xx/spd_sdram.c +++ b/cpu/mpc85xx/spd_sdram.c @@ -176,7 +176,7 @@ spd_sdram(void) spd_eeprom_t spd; unsigned int n_ranks; unsigned int rank_density; - unsigned int odt_rd_cfg, odt_wr_cfg; + unsigned int odt_rd_cfg, odt_wr_cfg, ba_bits; unsigned int odt_cfg, mode_odt_enable; unsigned int refresh_clk; #ifdef MPC85xx_DDR_SDRAM_CLK_CNTL @@ -341,9 +341,14 @@ spd_sdram(void) #endif } + ba_bits = 0; + if (spd.nbanks == 0x8) + ba_bits = 1; + ddr->cs0_config = ( 1 << 31 | (odt_rd_cfg << 20) | (odt_wr_cfg << 16) + | (ba_bits << 14) | (spd.nrow_addr - 12) << 8 | (spd.ncol_addr - 8) ); debug("\n"); From 3db0bef59eab1155801618cef5c481e97553b597 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Tue, 7 Aug 2007 18:07:27 -0500 Subject: [PATCH 099/259] Use an absolute address when jumping out of 4k boot page On e500 when we leave the 4k boot page we should use an absolute address since we don't know where the board code may want us to be really running at. Signed-off-by: Kumar Gala --- cpu/mpc85xx/start.S | 59 +++++++++++++++++++++------------------------ 1 file changed, 27 insertions(+), 32 deletions(-) diff --git a/cpu/mpc85xx/start.S b/cpu/mpc85xx/start.S index 9dfd38d6a..2c98c2ad8 100644 --- a/cpu/mpc85xx/start.S +++ b/cpu/mpc85xx/start.S @@ -260,32 +260,6 @@ _start_e500: mtspr DBCR0,r0 #endif - /* Jump out the last 4K page and continue to 'normal' start */ - bl 3f - b _start_cont - -3: li r0,0 - mtspr SRR1,r0 /* Keep things disabled for now */ - mflr r1 - mtspr SRR0,r1 - rfi - isync - - - .text - .globl _start -_start: - .long 0x27051956 /* U-BOOT Magic Number */ - .globl version_string -version_string: - .ascii U_BOOT_VERSION - .ascii " (", __DATE__, " - ", __TIME__, ")" - .ascii CONFIG_IDENT_STRING, "\0" - - .align 4 - .globl _start_cont -_start_cont: - /* L1 DCache is used for initial RAM */ /* Allocate Initial RAM in data cache. @@ -301,18 +275,39 @@ _start_cont: addi r3,r3,32 bdnz 1b -#ifndef CFG_RAMBOOT + /* Jump out the last 4K page and continue to 'normal' start */ +#ifdef CFG_RAMBOOT + bl 3f + b _start_cont +#else /* Calculate absolute address in FLASH and jump there */ /*--------------------------------------------------------------*/ lis r3,CFG_MONITOR_BASE@h ori r3,r3,CFG_MONITOR_BASE@l - addi r3,r3,in_flash - _start + _START_OFFSET + addi r3,r3,_start_cont - _start + _START_OFFSET mtlr r3 - blr - .global in_flash -in_flash: -#endif /* CFG_RAMBOOT */ +#endif +3: li r0,0 + mtspr SRR1,r0 /* Keep things disabled for now */ + mflr r1 + mtspr SRR0,r1 + rfi + isync + + .text + .globl _start +_start: + .long 0x27051956 /* U-BOOT Magic Number */ + .globl version_string +version_string: + .ascii U_BOOT_VERSION + .ascii " (", __DATE__, " - ", __TIME__, ")" + .ascii CONFIG_IDENT_STRING, "\0" + + .align 4 + .globl _start_cont +_start_cont: /* Setup the stack in initial RAM,could be L2-as-SRAM or L1 dcache*/ lis r1,CFG_INIT_RAM_ADDR@h ori r1,r1,CFG_INIT_SP_OFFSET@l From d111d6382c99fdea08c2312eeeae8786945e189a Mon Sep 17 00:00:00 2001 From: Haiying Wang Date: Tue, 19 Jun 2007 14:18:32 -0400 Subject: [PATCH 100/259] Empirically set cpo and clk_adjust for mpc85xx DDR2 support This patch is against u-boot-mpc85xx.git of www.denx.com Setting cpo to 0x9 for frequencies higher than 333MHz is verified on both MPC8548CDS board and MPC8568MDS board, especially for supporting 533MHz DDR2. Setting clk_adjust to 0x6(3/4 late cycle) for MPC8568MDS board is for DDR2 on all current board versions especially ver 1.92 or later to bring up. Signed-off-by: Haiying Wang --- cpu/mpc85xx/spd_sdram.c | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/cpu/mpc85xx/spd_sdram.c b/cpu/mpc85xx/spd_sdram.c index 679f3608f..5dc223a53 100644 --- a/cpu/mpc85xx/spd_sdram.c +++ b/cpu/mpc85xx/spd_sdram.c @@ -692,13 +692,10 @@ spd_sdram(void) */ cpo = 0; if (spd.mem_type == SPD_MEMTYPE_DDR2) { - if (effective_data_rate == 266 || effective_data_rate == 333) { + if (effective_data_rate <= 333) { cpo = 0x7; /* READ_LAT + 5/4 */ - } else if (effective_data_rate == 400) { - cpo = 0x9; /* READ_LAT + 7/4 */ } else { - /* Pure speculation */ - cpo = 0xb; + cpo = 0x9; /* READ_LAT + 7/4 */ } } @@ -905,7 +902,12 @@ spd_sdram(void) if (spd.mem_type == SPD_MEMTYPE_DDR) clk_adjust = 0x6; else +#ifdef CONFIG_MPC8568 + /* Empirally setting clk_adjust */ + clk_adjust = 0x6; +#else clk_adjust = 0x7; +#endif ddr->sdram_clk_cntl = (0 | 0x80000000 From c59e4091ffe0148398b9e9ff14a019ea038b7432 Mon Sep 17 00:00:00 2001 From: Haiying Wang Date: Tue, 19 Jun 2007 14:18:34 -0400 Subject: [PATCH 101/259] Add PCI support for MPC8568MDS board This patch is against u-boot-mpc85xx.git of www.denx.com Signed-off-by: Haiying Wang Signed-off-by: Ebony Zhu --- board/mpc8568mds/init.S | 48 +++++++++++----------------- board/mpc8568mds/mpc8568mds.c | 60 ++++++++++++++++++++++++++++++++--- include/asm-ppc/immap_85xx.h | 17 ++++++++++ include/configs/MPC8568MDS.h | 11 ++++--- 4 files changed, 98 insertions(+), 38 deletions(-) diff --git a/board/mpc8568mds/init.S b/board/mpc8568mds/init.S index 0d879821e..972a7d429 100644 --- a/board/mpc8568mds/init.S +++ b/board/mpc8568mds/init.S @@ -143,54 +143,42 @@ tlb1_entry: .long TLB1_MAS3(E500_TLB_RPN(CFG_FLASH_BASE), 0,0,0,0,0,1,0,1,0,1) /* - * TLBe 2: 256M Non-cacheable, guarded - * 0x80000000 256M PCI1 MEM + * TLBe 2: 1G Non-cacheable, guarded + * 0x80000000 512M PCI1 MEM + * 0xa0000000 512M PCIe MEM */ .long TLB1_MAS0(1, 2, 0) - .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1G) .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE), 0,0,0,0,1,0,1,0) .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE), 0,0,0,0,0,1,0,1,0,1) /* - * TLBe 3: 256M Non-cacheable, guarded - * 0xa0000000 256M PCIe Mem - */ - .long TLB1_MAS0(1, 3, 0) - .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) - .long TLB1_MAS2(E500_TLB_EPN(CFG_PEX_MEM_BASE), 0,0,0,0,1,0,1,0) - .long TLB1_MAS3(E500_TLB_RPN(CFG_PEX_MEM_BASE), 0,0,0,0,0,1,0,1,0,1) - - /* - * TLBe 4: Reserved for future usage - */ - - /* - * TLBe 5: 64M Non-cacheable, guarded + * TLBe 3: 64M Non-cacheable, guarded * 0xe000_0000 1M CCSRBAR * 0xe200_0000 8M PCI1 IO * 0xe280_0000 8M PCIe IO */ - .long TLB1_MAS0(1, 5, 0) + .long TLB1_MAS0(1, 3, 0) .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) .long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR), 0,0,0,0,1,0,1,0) .long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR), 0,0,0,0,0,1,0,1,0,1) /* - * TLBe 6: 64M Cacheable, non-guarded + * TLBe 4: 64M Cacheable, non-guarded * 0xf000_0000 64M LBC SDRAM */ - .long TLB1_MAS0(1, 6, 0) + .long TLB1_MAS0(1, 4, 0) .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) .long TLB1_MAS2(E500_TLB_EPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,0,0,0) .long TLB1_MAS3(E500_TLB_RPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,1,0,1,0,1) /* - * TLBe 7: 256K Non-cacheable, guarded + * TLBe 5: 256K Non-cacheable, guarded * 0xf8000000 32K BCSR * 0xf8008000 32K PIB (CS4) * 0xf8010000 32K PIB (CS5) */ - .long TLB1_MAS0(1, 7, 0) + .long TLB1_MAS0(1, 5, 0) .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256K) .long TLB1_MAS2(E500_TLB_EPN(CFG_BCSR_BASE), 0,0,0,0,1,0,1,0) .long TLB1_MAS3(E500_TLB_RPN(CFG_BCSR_BASE), 0,0,0,0,0,1,0,1,0,1) @@ -202,12 +190,12 @@ tlb1_entry: * LAW(Local Access Window) configuration: * *0) 0x0000_0000 0x7fff_ffff DDR 2G - *1) 0x8000_0000 0x9fff_ffff PCI1 MEM 256MB - *2) 0xa000_0000 0xbfff_ffff PCIe MEM 256MB - *5) 0xc000_0000 0xdfff_ffff SRIO 256MB + *1) 0x8000_0000 0x9fff_ffff PCI1 MEM 512MB + *2) 0xa000_0000 0xbfff_ffff PCIe MEM 512MB *-) 0xe000_0000 0xe00f_ffff CCSR 1M *3) 0xe200_0000 0xe27f_ffff PCI1 I/O 8M - *4) 0xe280_0000 0xe2ff_ffff PCIe I/0 8M + *4) 0xe280_0000 0xe2ff_ffff PCIe I/O 8M + *5) 0xc000_0000 0xdfff_ffff SRIO 512MB *6.a) 0xf000_0000 0xf3ff_ffff SDRAM 64MB *6.b) 0xf800_0000 0xf800_7fff BCSR 32KB *6.c) 0xf800_8000 0xf800_ffff PIB (CS4) 32KB @@ -226,20 +214,20 @@ tlb1_entry: #define LAWAR0 ((LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN) #define LAWBAR1 ((CFG_PCI1_MEM_BASE>>12) & 0xfffff) -#define LAWAR1 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_256M)) +#define LAWAR1 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_512M)) #define LAWBAR2 ((CFG_PEX_MEM_BASE>>12) & 0xfffff) -#define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_PEX | (LAWAR_SIZE & LAWAR_SIZE_256M)) +#define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_PEX | (LAWAR_SIZE & LAWAR_SIZE_512M)) #define LAWBAR3 ((CFG_PCI1_IO_PHYS>>12) & 0xfffff) #define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_8M)) #define LAWBAR4 ((CFG_PEX_IO_PHYS>>12) & 0xfffff) -#define LAWAR4 (LAWAR_EN | LAWAR_TRGT_IF_PEX | (LAWAR_SIZE & LAWAR_SIZE_16M)) +#define LAWAR4 (LAWAR_EN | LAWAR_TRGT_IF_PEX | (LAWAR_SIZE & LAWAR_SIZE_8M)) #define LAWBAR5 ((CFG_SRIO_MEM_BASE>>12) & 0xfffff) -#define LAWAR5 (LAWAR_EN | LAWAR_TRGT_IF_RIO | (LAWAR_SIZE & LAWAR_SIZE_256M)) +#define LAWAR5 (LAWAR_EN | LAWAR_TRGT_IF_RIO | (LAWAR_SIZE & LAWAR_SIZE_512M)) /* LBC window - maps 256M. That's SDRAM, BCSR, PIBs, and Flash */ #define LAWBAR6 ((CFG_LBC_SDRAM_BASE>>12) & 0xfffff) diff --git a/board/mpc8568mds/mpc8568mds.c b/board/mpc8568mds/mpc8568mds.c index 9c7960d47..23caaec72 100644 --- a/board/mpc8568mds/mpc8568mds.c +++ b/board/mpc8568mds/mpc8568mds.c @@ -27,6 +27,7 @@ #include #include #include +#include #include "bcsr.h" @@ -50,6 +51,15 @@ int board_early_init_f (void) enable_8568mds_duart(); enable_8568mds_flash_write(); +#ifdef CFG_I2C2_OFFSET + /* Enable I2C2_SCL and I2C2_SDA */ + volatile struct par_io *port_c; + port_c = (struct par_io*)(CFG_IMMR + 0xe0140); + port_c->cpdir2 |= 0x0f000000; + port_c->cppar2 &= ~0x0f000000; + port_c->cppar2 |= 0x0a000000; +#endif + return 0; } @@ -269,20 +279,62 @@ static struct pci_config_table pci_mpc8568mds_config_table[] = { #endif static struct pci_controller hose[] = { + { #ifndef CONFIG_PCI_PNP - { config_table: pci_mpc8568mds_config_table,}, -#endif -#ifdef CONFIG_MPC85XX_PCI2 - {}, + config_table: pci_mpc8568mds_config_table, #endif + } }; #endif /* CONFIG_PCI */ +/* + * pib_init() -- Initialize the PCA9555 IO expander on the PIB board + */ +void +pib_init(void) +{ + u8 val8, orig_i2c_bus; + /* + * Assign PIB PMC2/3 to PCI bus + */ + + /*switch temporarily to I2C bus #2 */ + orig_i2c_bus = i2c_get_bus_num(); + i2c_set_bus_num(1); + + val8 = 0x00; + i2c_write(0x23, 0x6, 1, &val8, 1); + i2c_write(0x23, 0x7, 1, &val8, 1); + val8 = 0xff; + i2c_write(0x23, 0x2, 1, &val8, 1); + i2c_write(0x23, 0x3, 1, &val8, 1); + + val8 = 0x00; + i2c_write(0x26, 0x6, 1, &val8, 1); + val8 = 0x34; + i2c_write(0x26, 0x7, 1, &val8, 1); + val8 = 0xf9; + i2c_write(0x26, 0x2, 1, &val8, 1); + val8 = 0xff; + i2c_write(0x26, 0x3, 1, &val8, 1); + + val8 = 0x00; + i2c_write(0x27, 0x6, 1, &val8, 1); + i2c_write(0x27, 0x7, 1, &val8, 1); + val8 = 0xff; + i2c_write(0x27, 0x2, 1, &val8, 1); + val8 = 0xef; + i2c_write(0x27, 0x3, 1, &val8, 1); + + asm("eieio"); +} + void pci_init_board(void) { #ifdef CONFIG_PCI + pib_init(); pci_mpc85xx_init(&hose); #endif } diff --git a/include/asm-ppc/immap_85xx.h b/include/asm-ppc/immap_85xx.h index 77f885daa..3d4816f3a 100644 --- a/include/asm-ppc/immap_85xx.h +++ b/include/asm-ppc/immap_85xx.h @@ -1522,6 +1522,17 @@ typedef struct ccsr_rio { char res58[60176]; } ccsr_rio_t; +/* Quick Engine Block Pin Muxing Registers (0xe_0100 - 0xe_01bf) */ +typedef struct par_io { + uint cpodr; /* 0x100 */ + uint cpdat; /* 0x104 */ + uint cpdir1; /* 0x108 */ + uint cpdir2; /* 0x10c */ + uint cppar1; /* 0x110 */ + uint cppar2; /* 0x114 */ + char res[8]; +}par_io_t; + /* * Global Utilities Register Block(0xe_0000-0xf_ffff) */ @@ -1585,7 +1596,13 @@ typedef struct ccsr_gur { uint svr; /* 0xe00a4 - System version register */ char res10a[8]; uint rstcr; /* 0xe00b0 - Reset control register */ +#ifdef MPC8568 + char res10b[76]; + par_io_t qe_par_io[7]; /* 0xe0100 - 0xe01bf */ + char res10c[3136]; +#else char res10b[3404]; +#endif uint clkocr; /* 0xe0e00 - Clock out select register */ char res11[12]; uint ddrdllcr; /* 0xe0e10 - DDR DLL control register */ diff --git a/include/configs/MPC8568MDS.h b/include/configs/MPC8568MDS.h index eef168c25..5bc953adc 100644 --- a/include/configs/MPC8568MDS.h +++ b/include/configs/MPC8568MDS.h @@ -33,7 +33,7 @@ #define CONFIG_MPC8568 1 /* MPC8568 specific */ #define CONFIG_MPC8568MDS 1 /* MPC8568MDS board specific */ -#undef CONFIG_PCI +#define CONFIG_PCI #define CONFIG_TSEC_ENET /* tsec ethernet support */ #define CONFIG_ENV_OVERWRITE #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ @@ -306,11 +306,14 @@ extern unsigned long get_clock_freq(void); #define CONFIG_FSL_I2C /* Use FSL common I2C driver */ #define CONFIG_HARD_I2C /* I2C with hardware support*/ #undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CONFIG_I2C_MULTI_BUS +#define CONFIG_I2C_CMD_TREE #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CFG_I2C_EEPROM_ADDR 0x57 +#define CFG_I2C_EEPROM_ADDR 0x52 #define CFG_I2C_SLAVE 0x7F -#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ +#define CFG_I2C_NOPROBES {0,0x69} /* Don't probe these addrs */ #define CFG_I2C_OFFSET 0x3000 +#define CFG_I2C2_OFFSET 0x3100 /* * General PCI @@ -318,7 +321,7 @@ extern unsigned long get_clock_freq(void); */ #define CFG_PCI1_MEM_BASE 0x80000000 #define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE -#define CFG_PCI1_MEM_SIZE 0x10000000 /* 256M */ +#define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */ #define CFG_PCI1_IO_BASE 0x00000000 #define CFG_PCI1_IO_PHYS 0xe2000000 #define CFG_PCI1_IO_SIZE 0x00800000 /* 8M */ From da9d4610d76e52c4d20a8f3d8433439a7fcf5b71 Mon Sep 17 00:00:00 2001 From: Andy Fleming Date: Tue, 14 Aug 2007 00:14:25 -0500 Subject: [PATCH 102/259] Add support for UEC to 8568 Signed-off-by: Haiying Wang Signed-off-by: Andy Fleming --- Makefile | 3 ++ board/mpc8568mds/bcsr.c | 7 +++ board/mpc8568mds/bcsr.h | 1 + board/mpc8568mds/mpc8568mds.c | 61 ++++++++++++++++++++++++- cpu/mpc85xx/Makefile | 2 +- cpu/mpc85xx/cpu.c | 24 +++++++++- cpu/mpc85xx/cpu_init.c | 33 ++++++++++++++ cpu/mpc85xx/qe_io.c | 85 +++++++++++++++++++++++++++++++++++ drivers/qe/uec.c | 27 ++++++----- drivers/qe/uec.h | 1 + drivers/qe/uec_phy.c | 14 +++--- drivers/qe/uec_phy.h | 6 +-- include/asm-ppc/global_data.h | 8 ++-- include/asm-ppc/immap_qe.h | 20 ++++++++- include/configs/MPC8568MDS.h | 56 ++++++++++++++++++++--- 15 files changed, 313 insertions(+), 35 deletions(-) create mode 100644 cpu/mpc85xx/qe_io.c diff --git a/Makefile b/Makefile index f51688961..a5698cf7c 100644 --- a/Makefile +++ b/Makefile @@ -212,6 +212,9 @@ LIBS += drivers/nand_legacy/libnand_legacy.a ifeq ($(CPU),mpc83xx) LIBS += drivers/qe/qe.a endif +ifeq ($(CPU),mpc85xx) +LIBS += drivers/qe/qe.a +endif LIBS += drivers/sk98lin/libsk98lin.a LIBS += post/libpost.a post/drivers/libpostdrivers.a LIBS += $(shell if [ -d post/lib_$(ARCH) ]; then echo \ diff --git a/board/mpc8568mds/bcsr.c b/board/mpc8568mds/bcsr.c index 2e2e8cd18..aae0f98e0 100644 --- a/board/mpc8568mds/bcsr.c +++ b/board/mpc8568mds/bcsr.c @@ -47,3 +47,10 @@ void disable_8568mds_flash_write() bcsr[9] &= ~(0x01); } + +void enable_8568mds_qe_mdio() +{ + u8 *bcsr = (u8 *)(CFG_BCSR); + + bcsr[7] |= 0x01; +} diff --git a/board/mpc8568mds/bcsr.h b/board/mpc8568mds/bcsr.h index 8d4cb2f14..aefd9bf54 100644 --- a/board/mpc8568mds/bcsr.h +++ b/board/mpc8568mds/bcsr.h @@ -95,5 +95,6 @@ void enable_8568mds_duart(void); void enable_8568mds_flash_write(void); void disable_8568mds_flash_write(void); +void enable_8568mds_qe_mdio(void); #endif /* __BCSR_H_ */ diff --git a/board/mpc8568mds/mpc8568mds.c b/board/mpc8568mds/mpc8568mds.c index 23caaec72..818ff138a 100644 --- a/board/mpc8568mds/mpc8568mds.c +++ b/board/mpc8568mds/mpc8568mds.c @@ -28,9 +28,65 @@ #include #include #include +#include #include "bcsr.h" +const qe_iop_conf_t qe_iop_conf_tab[] = { + /* GETH1 */ + {4, 10, 1, 0, 2}, /* TxD0 */ + {4, 9, 1, 0, 2}, /* TxD1 */ + {4, 8, 1, 0, 2}, /* TxD2 */ + {4, 7, 1, 0, 2}, /* TxD3 */ + {4, 23, 1, 0, 2}, /* TxD4 */ + {4, 22, 1, 0, 2}, /* TxD5 */ + {4, 21, 1, 0, 2}, /* TxD6 */ + {4, 20, 1, 0, 2}, /* TxD7 */ + {4, 15, 2, 0, 2}, /* RxD0 */ + {4, 14, 2, 0, 2}, /* RxD1 */ + {4, 13, 2, 0, 2}, /* RxD2 */ + {4, 12, 2, 0, 2}, /* RxD3 */ + {4, 29, 2, 0, 2}, /* RxD4 */ + {4, 28, 2, 0, 2}, /* RxD5 */ + {4, 27, 2, 0, 2}, /* RxD6 */ + {4, 26, 2, 0, 2}, /* RxD7 */ + {4, 11, 1, 0, 2}, /* TX_EN */ + {4, 24, 1, 0, 2}, /* TX_ER */ + {4, 16, 2, 0, 2}, /* RX_DV */ + {4, 30, 2, 0, 2}, /* RX_ER */ + {4, 17, 2, 0, 2}, /* RX_CLK */ + {4, 19, 1, 0, 2}, /* GTX_CLK */ + {1, 31, 2, 0, 3}, /* GTX125 */ + + /* GETH2 */ + {5, 10, 1, 0, 2}, /* TxD0 */ + {5, 9, 1, 0, 2}, /* TxD1 */ + {5, 8, 1, 0, 2}, /* TxD2 */ + {5, 7, 1, 0, 2}, /* TxD3 */ + {5, 23, 1, 0, 2}, /* TxD4 */ + {5, 22, 1, 0, 2}, /* TxD5 */ + {5, 21, 1, 0, 2}, /* TxD6 */ + {5, 20, 1, 0, 2}, /* TxD7 */ + {5, 15, 2, 0, 2}, /* RxD0 */ + {5, 14, 2, 0, 2}, /* RxD1 */ + {5, 13, 2, 0, 2}, /* RxD2 */ + {5, 12, 2, 0, 2}, /* RxD3 */ + {5, 29, 2, 0, 2}, /* RxD4 */ + {5, 28, 2, 0, 2}, /* RxD5 */ + {5, 27, 2, 0, 3}, /* RxD6 */ + {5, 26, 2, 0, 2}, /* RxD7 */ + {5, 11, 1, 0, 2}, /* TX_EN */ + {5, 24, 1, 0, 2}, /* TX_ER */ + {5, 16, 2, 0, 2}, /* RX_DV */ + {5, 30, 2, 0, 2}, /* RX_ER */ + {5, 17, 2, 0, 2}, /* RX_CLK */ + {5, 19, 1, 0, 2}, /* GTX_CLK */ + {1, 31, 2, 0, 3}, /* GTX125 */ + {4, 6, 3, 0, 2}, /* MDIO */ + {4, 5, 1, 0, 2}, /* MDC */ + {0, 0, 0, 0, QE_IOP_TAB_END}, /* END of table */ +}; + #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) extern void ddr_enable_ecc(unsigned int dram_size); @@ -50,6 +106,9 @@ int board_early_init_f (void) enable_8568mds_duart(); enable_8568mds_flash_write(); +#if defined(CONFIG_QE) && !defined(CONFIG_eTSEC_MDIO_BUS) + enable_8568mds_qe_mdio(); +#endif #ifdef CFG_I2C2_OFFSET /* Enable I2C2_SCL and I2C2_SDA */ @@ -335,6 +394,6 @@ pci_init_board(void) { #ifdef CONFIG_PCI pib_init(); - pci_mpc85xx_init(&hose); + pci_mpc85xx_init(hose); #endif } diff --git a/cpu/mpc85xx/Makefile b/cpu/mpc85xx/Makefile index ff67dcdd3..32091fa4e 100644 --- a/cpu/mpc85xx/Makefile +++ b/cpu/mpc85xx/Makefile @@ -30,7 +30,7 @@ LIB = $(obj)lib$(CPU).a START = start.o resetvec.o COBJS = traps.o cpu.o cpu_init.o speed.o interrupts.o \ - pci.o serial_scc.o commproc.o ether_fcc.o spd_sdram.o + pci.o serial_scc.o commproc.o ether_fcc.o spd_sdram.o qe_io.o SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) diff --git a/cpu/mpc85xx/cpu.c b/cpu/mpc85xx/cpu.c index 1d791c9b9..08e04685f 100644 --- a/cpu/mpc85xx/cpu.c +++ b/cpu/mpc85xx/cpu.c @@ -280,7 +280,7 @@ ft_cpu_setup(void *blob, bd_t *bd) if (p != NULL) *p = cpu_to_be32(clock); -#if defined(CONFIG_TSEC1) +#if defined(CONFIG_HAS_ETH0) p = ft_get_prop(blob, "/" OF_SOC "/ethernet@24000/mac-address", &len); if (p) memcpy(p, bd->bi_enetaddr, 6); @@ -308,6 +308,17 @@ ft_cpu_setup(void *blob, bd_t *bd) p = ft_get_prop(blob, "/" OF_SOC "/ethernet@26000/local-mac-address", &len); if (p) memcpy(p, bd->bi_enet2addr, 6); + +#ifdef CONFIG_UEC_ETH + p = ft_get_prop(blob, "/" OF_QE "/ucc@2000/mac-address", &len); + if (p) + memcpy(p, bd->bi_enet2addr, 6); + + p = ft_get_prop(blob, "/" OF_QE "/ucc@2000/local-mac-address", &len); + if (p) + memcpy(p, bd->bi_enet2addr, 6); + +#endif #endif #if defined(CONFIG_HAS_ETH3) @@ -318,6 +329,17 @@ ft_cpu_setup(void *blob, bd_t *bd) p = ft_get_prop(blob, "/" OF_SOC "/ethernet@27000/local-mac-address", &len); if (p) memcpy(p, bd->bi_enet3addr, 6); + +#ifdef CONFIG_UEC_ETH + p = ft_get_prop(blob, "/" OF_QE "/ucc@3000/mac-address", &len); + if (p) + memcpy(p, bd->bi_enet3addr, 6); + + p = ft_get_prop(blob, "/" OF_QE "/ucc@3000/local-mac-address", &len); + if (p) + memcpy(p, bd->bi_enet3addr, 6); + +#endif #endif } diff --git a/cpu/mpc85xx/cpu_init.c b/cpu/mpc85xx/cpu_init.c index c7fe130ee..7b9961013 100644 --- a/cpu/mpc85xx/cpu_init.c +++ b/cpu/mpc85xx/cpu_init.c @@ -34,6 +34,29 @@ DECLARE_GLOBAL_DATA_PTR; +#ifdef CONFIG_QE +extern qe_iop_conf_t qe_iop_conf_tab[]; +extern void qe_config_iopin(u8 port, u8 pin, int dir, + int open_drain, int assign); +extern void qe_init(uint qe_base); +extern void qe_reset(void); + +static void config_qe_ioports(void) +{ + u8 port, pin; + int dir, open_drain, assign; + int i; + + for (i = 0; qe_iop_conf_tab[i].assign != QE_IOP_TAB_END; i++) { + port = qe_iop_conf_tab[i].port; + pin = qe_iop_conf_tab[i].pin; + dir = qe_iop_conf_tab[i].dir; + open_drain = qe_iop_conf_tab[i].open_drain; + assign = qe_iop_conf_tab[i].assign; + qe_config_iopin(port, pin, dir, open_drain, assign); + } +} +#endif #ifdef CONFIG_CPM2 static void config_8560_ioports (volatile immap_t * immr) @@ -181,6 +204,11 @@ void cpu_init_f (void) #if defined(CONFIG_CPM2) m8560_cpm_reset(); #endif +#ifdef CONFIG_QE + /* Config QE ioports */ + config_qe_ioports(); +#endif + } @@ -262,6 +290,11 @@ int cpu_init_r(void) #else printf("L2 cache: disabled\n"); #endif +#ifdef CONFIG_QE + uint qe_base = CFG_IMMR + 0x00080000; /* QE immr base */ + qe_init(qe_base); + qe_reset(); +#endif return 0; } diff --git a/cpu/mpc85xx/qe_io.c b/cpu/mpc85xx/qe_io.c new file mode 100644 index 000000000..8878bc531 --- /dev/null +++ b/cpu/mpc85xx/qe_io.c @@ -0,0 +1,85 @@ +/* + * Copyright (C) 2006 Freescale Semiconductor, Inc. + * + * Dave Liu + * based on source code of Shlomi Gridish + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include "common.h" +#include "asm/errno.h" +#include "asm/io.h" +#include "asm/immap_85xx.h" + +#if defined(CONFIG_QE) +#define NUM_OF_PINS 32 +void qe_config_iopin(u8 port, u8 pin, int dir, int open_drain, int assign) +{ + u32 pin_2bit_mask; + u32 pin_2bit_dir; + u32 pin_2bit_assign; + u32 pin_1bit_mask; + u32 tmp_val; + volatile immap_t *im = (volatile immap_t *)CFG_IMMR; + volatile par_io_t *par_io = (volatile par_io_t *) + &(im->im_gur.qe_par_io); + + /* Caculate pin location and 2bit mask and dir */ + pin_2bit_mask = (u32)(0x3 << (NUM_OF_PINS-(pin%(NUM_OF_PINS/2)+1)*2)); + pin_2bit_dir = (u32)(dir << (NUM_OF_PINS-(pin%(NUM_OF_PINS/2)+1)*2)); + + /* Setup the direction */ + tmp_val = (pin > (NUM_OF_PINS/2) - 1) ? \ + in_be32(&par_io[port].cpdir2) : + in_be32(&par_io[port].cpdir1); + + if (pin > (NUM_OF_PINS/2) -1) { + out_be32(&par_io[port].cpdir2, ~pin_2bit_mask & tmp_val); + out_be32(&par_io[port].cpdir2, pin_2bit_dir | tmp_val); + } else { + out_be32(&par_io[port].cpdir1, ~pin_2bit_mask & tmp_val); + out_be32(&par_io[port].cpdir1, pin_2bit_dir | tmp_val); + } + + /* Calculate pin location for 1bit mask */ + pin_1bit_mask = (u32)(1 << (NUM_OF_PINS - (pin+1))); + + /* Setup the open drain */ + tmp_val = in_be32(&par_io[port].cpodr); + if (open_drain) + out_be32(&par_io[port].cpodr, pin_1bit_mask | tmp_val); + else + out_be32(&par_io[port].cpodr, ~pin_1bit_mask & tmp_val); + + /* Setup the assignment */ + tmp_val = (pin > (NUM_OF_PINS/2) - 1) ? + in_be32(&par_io[port].cppar2): + in_be32(&par_io[port].cppar1); + pin_2bit_assign = (u32)(assign + << (NUM_OF_PINS - (pin%(NUM_OF_PINS/2)+1)*2)); + + /* Clear and set 2 bits mask */ + if (pin > (NUM_OF_PINS/2) - 1) { + out_be32(&par_io[port].cppar2, ~pin_2bit_mask & tmp_val); + out_be32(&par_io[port].cppar2, pin_2bit_assign | tmp_val); + } else { + out_be32(&par_io[port].cppar1, ~pin_2bit_mask & tmp_val); + out_be32(&par_io[port].cppar1, pin_2bit_assign | tmp_val); + } +} + +#endif /* CONFIG_QE */ diff --git a/drivers/qe/uec.c b/drivers/qe/uec.c index c416a67c8..89a727982 100644 --- a/drivers/qe/uec.c +++ b/drivers/qe/uec.c @@ -391,17 +391,17 @@ static int uec_set_mac_if_mode(uec_private_t *uec, enet_interface_e if_mode) return 0; } -static int init_mii_management_configuration(uec_t *uec_regs) +static int init_mii_management_configuration(uec_mii_t *uec_mii_regs) { uint timeout = 0x1000; u32 miimcfg = 0; - miimcfg = in_be32(&uec_regs->miimcfg); + miimcfg = in_be32(&uec_mii_regs->miimcfg); miimcfg |= MIIMCFG_MNGMNT_CLC_DIV_INIT_VALUE; - out_be32(&uec_regs->miimcfg, miimcfg); + out_be32(&uec_mii_regs->miimcfg, miimcfg); /* Wait until the bus is free */ - while ((in_be32(&uec_regs->miimcfg) & MIIMIND_BUSY) && timeout--); + while ((in_be32(&uec_mii_regs->miimcfg) & MIIMIND_BUSY) && timeout--); if (timeout <= 0) { printf("%s: The MII Bus is stuck!", __FUNCTION__); return -ETIMEDOUT; @@ -413,13 +413,13 @@ static int init_mii_management_configuration(uec_t *uec_regs) static int init_phy(struct eth_device *dev) { uec_private_t *uec; - uec_t *uec_regs; + uec_mii_t *umii_regs; struct uec_mii_info *mii_info; struct phy_info *curphy; int err; uec = (uec_private_t *)dev->priv; - uec_regs = uec->uec_regs; + umii_regs = uec->uec_mii_regs; uec->oldlink = 0; uec->oldspeed = 0; @@ -451,19 +451,19 @@ static int init_phy(struct eth_device *dev) mii_info->mii_id = uec->uec_info->phy_address; mii_info->dev = dev; - mii_info->mdio_read = &read_phy_reg; - mii_info->mdio_write = &write_phy_reg; + mii_info->mdio_read = &uec_read_phy_reg; + mii_info->mdio_write = &uec_write_phy_reg; uec->mii_info = mii_info; - if (init_mii_management_configuration(uec_regs)) { + if (init_mii_management_configuration(umii_regs)) { printf("%s: The MII Bus is stuck!", dev->name); err = -1; goto bus_fail; } /* get info for this PHY */ - curphy = get_phy_info(uec->mii_info); + curphy = uec_get_phy_info(uec->mii_info); if (!curphy) { printf("%s: No PHY found", dev->name); err = -1; @@ -989,6 +989,13 @@ static int uec_startup(uec_private_t *uec) /* Setup MAC interface mode */ uec_set_mac_if_mode(uec, uec_info->enet_interface); + /* Setup MII management base */ +#ifndef CONFIG_eTSEC_MDIO_BUS + uec->uec_mii_regs = (uec_mii_t *)(&uec_regs->miimcfg); +#else + uec->uec_mii_regs = (uec_mii_t *) CONFIG_MIIM_ADDRESS; +#endif + /* Setup MII master clock source */ qe_set_mii_clk_src(uec_info->uf_info.ucc_num); diff --git a/drivers/qe/uec.h b/drivers/qe/uec.h index 04950264b..c384055ce 100644 --- a/drivers/qe/uec.h +++ b/drivers/qe/uec.h @@ -675,6 +675,7 @@ typedef struct uec_private { ucc_fast_private_t *uccf; struct eth_device *dev; uec_t *uec_regs; + uec_mii_t *uec_mii_regs; /* enet init command parameter */ uec_init_cmd_pram_t *p_init_enet_param; u32 init_enet_param_offset; diff --git a/drivers/qe/uec_phy.c b/drivers/qe/uec_phy.c index 76fd38896..ca6faa6ef 100644 --- a/drivers/qe/uec_phy.c +++ b/drivers/qe/uec_phy.c @@ -60,14 +60,14 @@ void phy_write (struct uec_mii_info *mii_info, u16 regnum, u16 val); /* Write value to the PHY for this device to the register at regnum, */ /* waiting until the write is done before it returns. All PHY */ /* configuration has to be done through the TSEC1 MIIM regs */ -void write_phy_reg (struct eth_device *dev, int mii_id, int regnum, int value) +void uec_write_phy_reg (struct eth_device *dev, int mii_id, int regnum, int value) { uec_private_t *ugeth = (uec_private_t *) dev->priv; - uec_t *ug_regs; + uec_mii_t *ug_regs; enet_tbi_mii_reg_e mii_reg = (enet_tbi_mii_reg_e) regnum; u32 tmp_reg; - ug_regs = ugeth->uec_regs; + ug_regs = ugeth->uec_mii_regs; /* Stop the MII management read cycle */ out_be32 (&ug_regs->miimcom, 0); @@ -87,15 +87,15 @@ void write_phy_reg (struct eth_device *dev, int mii_id, int regnum, int value) /* Reads from register regnum in the PHY for device dev, */ /* returning the value. Clears miimcom first. All PHY */ /* configuration has to be done through the TSEC1 MIIM regs */ -int read_phy_reg (struct eth_device *dev, int mii_id, int regnum) +int uec_read_phy_reg (struct eth_device *dev, int mii_id, int regnum) { uec_private_t *ugeth = (uec_private_t *) dev->priv; - uec_t *ug_regs; + uec_mii_t *ug_regs; enet_tbi_mii_reg_e mii_reg = (enet_tbi_mii_reg_e) regnum; u32 tmp_reg; u16 value; - ug_regs = ugeth->uec_regs; + ug_regs = ugeth->uec_mii_regs; /* Setting up the MII Mangement Address Register */ tmp_reg = ((u32) mii_id << MIIMADD_PHY_ADDRESS_SHIFT) | mii_reg; @@ -521,7 +521,7 @@ void phy_write (struct uec_mii_info *mii_info, u16 regnum, u16 val) /* Use the PHY ID registers to determine what type of PHY is attached * to device dev. return a struct phy_info structure describing that PHY */ -struct phy_info *get_phy_info (struct uec_mii_info *mii_info) +struct phy_info *uec_get_phy_info (struct uec_mii_info *mii_info) { u16 phy_reg; u32 phy_ID; diff --git a/drivers/qe/uec_phy.h b/drivers/qe/uec_phy.h index 9bd926ddd..e59a940e0 100644 --- a/drivers/qe/uec_phy.h +++ b/drivers/qe/uec_phy.h @@ -249,10 +249,10 @@ struct phy_info { void (*close) (struct uec_mii_info * mii_info); }; -struct phy_info *get_phy_info (struct uec_mii_info *mii_info); -void write_phy_reg (struct eth_device *dev, int mii_id, int regnum, +struct phy_info *uec_get_phy_info (struct uec_mii_info *mii_info); +void uec_write_phy_reg (struct eth_device *dev, int mii_id, int regnum, int value); -int read_phy_reg (struct eth_device *dev, int mii_id, int regnum); +int uec_read_phy_reg (struct eth_device *dev, int mii_id, int regnum); void mii_clear_phy_interrupt (struct uec_mii_info *mii_info); void mii_configure_phy_interrupt (struct uec_mii_info *mii_info, u32 interrupts); diff --git a/include/asm-ppc/global_data.h b/include/asm-ppc/global_data.h index bbaeb3f57..1f1583a92 100644 --- a/include/asm-ppc/global_data.h +++ b/include/asm-ppc/global_data.h @@ -71,16 +71,16 @@ typedef struct global_data { u32 lclk_clk; u32 ddr_clk; u32 pci_clk; +#if defined(CONFIG_MPC8360) + u32 ddr_sec_clk; +#endif /* CONFIG_MPC8360 */ +#endif #if defined(CONFIG_QE) u32 qe_clk; u32 brg_clk; uint mp_alloc_base; uint mp_alloc_top; #endif /* CONFIG_QE */ -#if defined (CONFIG_MPC8360) - u32 ddr_sec_clk; -#endif /* CONFIG_MPC8360 */ -#endif #if defined(CONFIG_MPC5xxx) unsigned long ipb_clk; unsigned long pci_clk; diff --git a/include/asm-ppc/immap_qe.h b/include/asm-ppc/immap_qe.h index 950b9497f..a16a6d3fc 100644 --- a/include/asm-ppc/immap_qe.h +++ b/include/asm-ppc/immap_qe.h @@ -281,6 +281,17 @@ typedef struct ucc_slow { u8 res4[0x200 - 0x091]; } __attribute__ ((packed)) ucc_slow_t; +typedef struct ucc_mii_mng { + u32 miimcfg; /* MII management configuration reg */ + u32 miimcom; /* MII management command reg */ + u32 miimadd; /* MII management address reg */ + u32 miimcon; /* MII management control reg */ + u32 miimstat; /* MII management status reg */ + u32 miimind; /* MII management indication reg */ + u32 ifctl; /* interface control reg */ + u32 ifstat; /* interface statux reg */ +} __attribute__ ((packed))uec_mii_t; + typedef struct ucc_ethernet { u32 maccfg1; /* mac configuration reg. 1 */ u32 maccfg2; /* mac configuration reg. 2 */ @@ -540,14 +551,21 @@ typedef struct qe_immap { u8 res14[0x300]; u8 res15[0x3A00]; u8 res16[0x8000]; /* 0x108000 - 0x110000 */ +#if defined(CONFIG_MPC8568) + u8 muram[0x10000]; /* 0x1_0000 - 0x2_0000 Multi-user RAM */ + u8 res17[0x20000]; /* 0x2_0000 - 0x4_0000 */ +#else u8 muram[0xC000]; /* 0x110000 - 0x11C000 Multi-user RAM */ u8 res17[0x24000]; /* 0x11C000 - 0x140000 */ u8 res18[0xC0000]; /* 0x140000 - 0x200000 */ +#endif } __attribute__ ((packed)) qe_map_t; extern qe_map_t *qe_immr; -#if defined(CONFIG_MPC8360) +#if defined(CONFIG_MPC8568) +#define QE_MURAM_SIZE 0x10000UL +#elif defined(CONFIG_MPC8360) #define QE_MURAM_SIZE 0xc000UL #elif defined(CONFIG_MPC832X) #define QE_MURAM_SIZE 0x4000UL diff --git a/include/configs/MPC8568MDS.h b/include/configs/MPC8568MDS.h index 5bc953adc..dc9cb1ff5 100644 --- a/include/configs/MPC8568MDS.h +++ b/include/configs/MPC8568MDS.h @@ -28,20 +28,21 @@ /* High Level Configuration Options */ #define CONFIG_BOOKE 1 /* BOOKE */ -#define CONFIG_E500 1 /* BOOKE e500 family */ +#define CONFIG_E500 1 /* BOOKE e500 family */ #define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48/68 */ #define CONFIG_MPC8568 1 /* MPC8568 specific */ #define CONFIG_MPC8568MDS 1 /* MPC8568MDS board specific */ #define CONFIG_PCI #define CONFIG_TSEC_ENET /* tsec ethernet support */ +#undef CONFIG_QE /* Enable QE */ #define CONFIG_ENV_OVERWRITE #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ #define CONFIG_DDR_DLL /* possible DLL fix needed */ /*#define CONFIG_DDR_2T_TIMING Sets the 2T timing bit */ /*#define CONFIG_DDR_ECC*/ /* only for ECC DDR module */ -/*#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER*/ /* DDR controller or DMA? */ +/*#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER*/ /* DDR controller or DMA? */ #define CONFIG_MEM_INIT_VALUE 0xDeadBeef @@ -297,6 +298,7 @@ extern unsigned long get_clock_freq(void); #define OF_CPU "PowerPC,8568@0" #define OF_SOC "soc8568@e0000000" +#define OF_QE "qe@e0080000" #define OF_TBCLK (bd->bi_busfreq / 8) #define OF_STDOUT_PATH "/soc8568@e0000000/serial@4600" @@ -311,7 +313,7 @@ extern unsigned long get_clock_freq(void); #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ #define CFG_I2C_EEPROM_ADDR 0x52 #define CFG_I2C_SLAVE 0x7F -#define CFG_I2C_NOPROBES {0,0x69} /* Don't probe these addrs */ +#define CFG_I2C_NOPROBES {{0,0x69}} /* Don't probe these addrs */ #define CFG_I2C_OFFSET 0x3000 #define CFG_I2C2_OFFSET 0x3100 @@ -340,6 +342,44 @@ extern unsigned long get_clock_freq(void); #define CONFIG_NET_MULTI #define CONFIG_PCI_PNP /* do pci plug-and-play */ +#ifdef CONFIG_QE +/* + * QE UEC ethernet configuration + */ +#define CONFIG_UEC_ETH +#ifndef CONFIG_TSEC_ENET +#define CONFIG_ETHPRIME "Freescale GETH" +#endif +#define CONFIG_PHY_MODE_NEED_CHANGE +#define CONFIG_eTSEC_MDIO_BUS + +#ifdef CONFIG_eTSEC_MDIO_BUS +#define CONFIG_MIIM_ADDRESS 0xE0024520 +#endif + +#define CONFIG_UEC_ETH1 /* GETH1 */ + +#ifdef CONFIG_UEC_ETH1 +#define CFG_UEC1_UCC_NUM 0 /* UCC1 */ +#define CFG_UEC1_RX_CLK QE_CLK_NONE +#define CFG_UEC1_TX_CLK QE_CLK16 +#define CFG_UEC1_ETH_TYPE GIGA_ETH +#define CFG_UEC1_PHY_ADDR 7 +#define CFG_UEC1_INTERFACE_MODE ENET_1000_GMII +#endif + +#define CONFIG_UEC_ETH2 /* GETH2 */ + +#ifdef CONFIG_UEC_ETH2 +#define CFG_UEC2_UCC_NUM 1 /* UCC2 */ +#define CFG_UEC2_RX_CLK QE_CLK_NONE +#define CFG_UEC2_TX_CLK QE_CLK16 +#define CFG_UEC2_ETH_TYPE GIGA_ETH +#define CFG_UEC2_PHY_ADDR 1 +#define CFG_UEC2_INTERFACE_MODE ENET_1000_GMII +#endif +#endif /* CONFIG_QE */ + #undef CONFIG_EEPRO100 #undef CONFIG_TULIP @@ -348,13 +388,12 @@ extern unsigned long get_clock_freq(void); #endif /* CONFIG_PCI */ - -#if defined(CONFIG_TSEC_ENET) - #ifndef CONFIG_NET_MULTI #define CONFIG_NET_MULTI 1 #endif +#if defined(CONFIG_TSEC_ENET) + #define CONFIG_MII 1 /* MII PHY management */ #define CONFIG_TSEC1 1 #define CONFIG_TSEC1_NAME "eTSEC0" @@ -460,12 +499,15 @@ extern unsigned long get_clock_freq(void); */ /* The mac addresses for all ethernet interface */ -#if defined(CONFIG_TSEC_ENET) +#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_UEC_ETH) +#define CONFIG_HAS_ETH0 #define CONFIG_ETHADDR 00:E0:0C:00:00:FD #define CONFIG_HAS_ETH1 #define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD #define CONFIG_HAS_ETH2 #define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD +#define CONFIG_HAS_ETH3 +#define CONFIG_ETH3ADDR 00:E0:0C:00:03:FD #endif #define CONFIG_IPADDR 192.168.1.253 From e41094c7e38177c755fbd9b182018069614f080d Mon Sep 17 00:00:00 2001 From: Andy Fleming Date: Tue, 14 Aug 2007 01:50:09 -0500 Subject: [PATCH 103/259] 85xxCDS: Enable the VIA PCI-to-ISA bridge. Author: Randy Vinson Enable the PCI-to-ISA bridge in the VIA Southbridge located on the Arcadia main board. Signed-off-by: Randy Vinson Signed-off-by: York Sun --- board/cds/common/via.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/board/cds/common/via.c b/board/cds/common/via.c index e79bd02a1..ded214f06 100644 --- a/board/cds/common/via.c +++ b/board/cds/common/via.c @@ -28,11 +28,16 @@ void mpc85xx_config_via(struct pci_controller *hose, pci_dev_t dev, struct pci_config_table *tab) { pci_dev_t bridge; + unsigned int cmdstat; /* Enable USB and IDE functions */ pci_hose_write_config_byte(hose, dev, 0x48, 0x08); - pciauto_config_device(hose, dev); + pci_hose_read_config_dword(hose, dev, PCI_COMMAND, &cmdstat); + cmdstat |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY| PCI_COMMAND_MASTER; + pci_hose_write_config_dword(hose, dev, PCI_COMMAND, cmdstat); + pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08); + pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80); /* * Force the backplane P2P bridge to have a window From 7f3f2bd2dc08e0b05e185662ca2e2d283757104a Mon Sep 17 00:00:00 2001 From: Randy Vinson Date: Tue, 27 Feb 2007 19:42:22 -0700 Subject: [PATCH 104/259] 85xxCDS: Add make targets for legacy systems. The PCI ID select values on the Arcadia main board differ depending on the version of the hardware. The standard configuration supports Rev 3.1. The legacy target supports Rev 2.x. Signed-off-by Randy Vinson --- Makefile | 27 ++++++++++++++++++++++++--- board/cds/common/via.c | 2 +- board/cds/mpc8541cds/mpc8541cds.c | 15 +++++++++------ board/cds/mpc8548cds/mpc8548cds.c | 15 +++++++++------ board/cds/mpc8555cds/mpc8555cds.c | 15 +++++++++------ cpu/mpc85xx/pci.c | 2 +- include/configs/MPC8541CDS.h | 7 +++++++ include/configs/MPC8548CDS.h | 8 ++++++++ include/configs/MPC8555CDS.h | 7 +++++++ 9 files changed, 75 insertions(+), 23 deletions(-) diff --git a/Makefile b/Makefile index a5698cf7c..95e9e369a 100644 --- a/Makefile +++ b/Makefile @@ -1786,17 +1786,38 @@ MPC8540EVAL_66_slave_config: unconfig MPC8560ADS_config: unconfig @$(MKCONFIG) $(@:_config=) ppc mpc85xx mpc8560ads +MPC8541CDS_legacy_config \ MPC8541CDS_config: unconfig - @$(MKCONFIG) $(@:_config=) ppc mpc85xx mpc8541cds cds + @mkdir -p $(obj)include + @echo "" >$(obj)include/config.h ; \ + if [ "$(findstring _legacy_,$@)" ] ; then \ + echo "#define CONFIG_LEGACY" >>$(obj)include/config.h ; \ + echo "... legacy" ; \ + fi + @$(MKCONFIG) -a MPC8541CDS ppc mpc85xx mpc8541cds cds MPC8544DS_config: unconfig @$(MKCONFIG) $(@:_config=) ppc mpc85xx mpc8544ds freescale +MPC8548CDS_legacy_config \ MPC8548CDS_config: unconfig - @$(MKCONFIG) $(@:_config=) ppc mpc85xx mpc8548cds cds + @mkdir -p $(obj)include + @echo "" >$(obj)include/config.h ; \ + if [ "$(findstring _legacy_,$@)" ] ; then \ + echo "#define CONFIG_LEGACY" >>$(obj)include/config.h ; \ + echo "... legacy" ; \ + fi + @$(MKCONFIG) -a MPC8548CDS ppc mpc85xx mpc8548cds cds +MPC8555CDS_legacy_config \ MPC8555CDS_config: unconfig - @$(MKCONFIG) $(@:_config=) ppc mpc85xx mpc8555cds cds + @mkdir -p $(obj)include + @echo "" >$(obj)include/config.h ; \ + if [ "$(findstring _legacy_,$@)" ] ; then \ + echo "#define CONFIG_LEGACY" >>$(obj)include/config.h ; \ + echo "... legacy" ; \ + fi + @$(MKCONFIG) -a MPC8555CDS ppc mpc85xx mpc8555cds cds MPC8568MDS_config: unconfig @$(MKCONFIG) $(@:_config=) ppc mpc85xx mpc8568mds diff --git a/board/cds/common/via.c b/board/cds/common/via.c index ded214f06..4a63d7794 100644 --- a/board/cds/common/via.c +++ b/board/cds/common/via.c @@ -45,7 +45,7 @@ void mpc85xx_config_via(struct pci_controller *hose, * This allows legacy I/O (i8259, etc) on the VIA * southbridge to be accessed. */ - bridge = PCI_BDF(0,17,0); + bridge = PCI_BDF(0,BRIDGE_ID,0); pci_hose_write_config_byte(hose, bridge, PCI_IO_BASE, 0); pci_hose_write_config_word(hose, bridge, PCI_IO_BASE_UPPER16, 0); pci_hose_write_config_byte(hose, bridge, PCI_IO_LIMIT, 0x10); diff --git a/board/cds/mpc8541cds/mpc8541cds.c b/board/cds/mpc8541cds/mpc8541cds.c index 419232483..558ba9903 100644 --- a/board/cds/mpc8541cds/mpc8541cds.c +++ b/board/cds/mpc8541cds/mpc8541cds.c @@ -476,14 +476,17 @@ void dummy_func(struct pci_controller* hose, pci_dev_t dev, struct pci_config_ta static struct pci_config_table pci_mpc85xxcds_config_table[] = { {0x10e3, 0x0513, PCI_ANY_ID, 1, 3, PCI_ANY_ID, dummy_func, {0,0,0}}, - {0x1106, 0x0686, PCI_ANY_ID, 1, 2, 0, mpc85xx_config_via, {0,0,0}}, - {0x1106, 0x0571, PCI_ANY_ID, 1, 2, 1, + {0x1106, 0x0686, PCI_ANY_ID, 1, VIA_ID, 0, mpc85xx_config_via, {0,0,0}}, + {0x1106, 0x0571, PCI_ANY_ID, 1, VIA_ID, 1, mpc85xx_config_via_usbide, {0,0,0}}, - {0x1105, 0x3038, PCI_ANY_ID, 1, 2, 2, mpc85xx_config_via_usb, {0,0,0}}, - {0x1106, 0x3038, PCI_ANY_ID, 1, 2, 3, mpc85xx_config_via_usb2, {0,0,0}}, - {0x1106, 0x3058, PCI_ANY_ID, 1, 2, 5, + {0x1105, 0x3038, PCI_ANY_ID, 1, VIA_ID, 2, + mpc85xx_config_via_usb, {0,0,0}}, + {0x1106, 0x3038, PCI_ANY_ID, 1, VIA_ID, 3, + mpc85xx_config_via_usb2, {0,0,0}}, + {0x1106, 0x3058, PCI_ANY_ID, 1, VIA_ID, 5, mpc85xx_config_via_power, {0,0,0}}, - {0x1106, 0x3068, PCI_ANY_ID, 1, 2, 6, mpc85xx_config_via_ac97, {0,0,0}}, + {0x1106, 0x3068, PCI_ANY_ID, 1, VIA_ID, 6, + mpc85xx_config_via_ac97, {0,0,0}}, {}, }; diff --git a/board/cds/mpc8548cds/mpc8548cds.c b/board/cds/mpc8548cds/mpc8548cds.c index 242a68c39..48753d7e2 100644 --- a/board/cds/mpc8548cds/mpc8548cds.c +++ b/board/cds/mpc8548cds/mpc8548cds.c @@ -299,14 +299,17 @@ void dummy_func(struct pci_controller* hose, pci_dev_t dev, struct pci_config_ta static struct pci_config_table pci_mpc85xxcds_config_table[] = { {0x10e3, 0x0513, PCI_ANY_ID, 1, 3, PCI_ANY_ID, dummy_func, {0,0,0}}, - {0x1106, 0x0686, PCI_ANY_ID, 1, 2, 0, mpc85xx_config_via, {0,0,0}}, - {0x1106, 0x0571, PCI_ANY_ID, 1, 2, 1, + {0x1106, 0x0686, PCI_ANY_ID, 1, VIA_ID, 0, mpc85xx_config_via, {0,0,0}}, + {0x1106, 0x0571, PCI_ANY_ID, 1, VIA_ID, 1, mpc85xx_config_via_usbide, {0,0,0}}, - {0x1105, 0x3038, PCI_ANY_ID, 1, 2, 2, mpc85xx_config_via_usb, {0,0,0}}, - {0x1106, 0x3038, PCI_ANY_ID, 1, 2, 3, mpc85xx_config_via_usb2, {0,0,0}}, - {0x1106, 0x3058, PCI_ANY_ID, 1, 2, 5, + {0x1105, 0x3038, PCI_ANY_ID, 1, VIA_ID, 2, + mpc85xx_config_via_usb, {0,0,0}}, + {0x1106, 0x3038, PCI_ANY_ID, 1, VIA_ID, 3, + mpc85xx_config_via_usb2, {0,0,0}}, + {0x1106, 0x3058, PCI_ANY_ID, 1, VIA_ID, 5, mpc85xx_config_via_power, {0,0,0}}, - {0x1106, 0x3068, PCI_ANY_ID, 1, 2, 6, mpc85xx_config_via_ac97, {0,0,0}}, + {0x1106, 0x3068, PCI_ANY_ID, 1, VIA_ID, 6, + mpc85xx_config_via_ac97, {0,0,0}}, {}, }; diff --git a/board/cds/mpc8555cds/mpc8555cds.c b/board/cds/mpc8555cds/mpc8555cds.c index 704bf0316..8f1642187 100644 --- a/board/cds/mpc8555cds/mpc8555cds.c +++ b/board/cds/mpc8555cds/mpc8555cds.c @@ -473,14 +473,17 @@ void dummy_func(struct pci_controller* hose, pci_dev_t dev, struct pci_config_ta static struct pci_config_table pci_mpc85xxcds_config_table[] = { {0x10e3, 0x0513, PCI_ANY_ID, 1, 3, PCI_ANY_ID, dummy_func, {0,0,0}}, - {0x1106, 0x0686, PCI_ANY_ID, 1, 2, 0, mpc85xx_config_via, {0,0,0}}, - {0x1106, 0x0571, PCI_ANY_ID, 1, 2, 1, + {0x1106, 0x0686, PCI_ANY_ID, 1, VIA_ID, 0, mpc85xx_config_via, {0,0,0}}, + {0x1106, 0x0571, PCI_ANY_ID, 1, VIA_ID, 1, mpc85xx_config_via_usbide, {0,0,0}}, - {0x1105, 0x3038, PCI_ANY_ID, 1, 2, 2, mpc85xx_config_via_usb, {0,0,0}}, - {0x1106, 0x3038, PCI_ANY_ID, 1, 2, 3, mpc85xx_config_via_usb2, {0,0,0}}, - {0x1106, 0x3058, PCI_ANY_ID, 1, 2, 5, + {0x1105, 0x3038, PCI_ANY_ID, 1, VIA_ID, 2, + mpc85xx_config_via_usb, {0,0,0}}, + {0x1106, 0x3038, PCI_ANY_ID, 1, VIA_ID, 3, + mpc85xx_config_via_usb2, {0,0,0}}, + {0x1106, 0x3058, PCI_ANY_ID, 1, VIA_ID, 5, mpc85xx_config_via_power, {0,0,0}}, - {0x1106, 0x3068, PCI_ANY_ID, 1, 2, 6, mpc85xx_config_via_ac97, {0,0,0}}, + {0x1106, 0x3068, PCI_ANY_ID, 1, VIA_ID, 6, + mpc85xx_config_via_ac97, {0,0,0}}, {}, }; diff --git a/cpu/mpc85xx/pci.c b/cpu/mpc85xx/pci.c index 3c1a323aa..db09e45fb 100644 --- a/cpu/mpc85xx/pci.c +++ b/cpu/mpc85xx/pci.c @@ -142,7 +142,7 @@ pci_mpc85xx_init(struct pci_controller *board_hose) u8 header_type; pci_hose_read_config_byte(hose, - PCI_BDF(0,17,0), + PCI_BDF(0,BRIDGE_ID,0), PCI_HEADER_TYPE, &header_type); } diff --git a/include/configs/MPC8541CDS.h b/include/configs/MPC8541CDS.h index 50d3b6b87..232f1716b 100644 --- a/include/configs/MPC8541CDS.h +++ b/include/configs/MPC8541CDS.h @@ -350,6 +350,13 @@ extern unsigned long get_clock_freq(void); #define CFG_PCI2_IO_PHYS 0xe2100000 #define CFG_PCI2_IO_SIZE 0x100000 /* 1M */ +#ifdef CONFIG_LEGACY +#define BRIDGE_ID 17 +#define VIA_ID 2 +#else +#define BRIDGE_ID 28 +#define VIA_ID 4 +#endif #if defined(CONFIG_PCI) diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h index dfe4f5b7a..cda9fd5c1 100644 --- a/include/configs/MPC8548CDS.h +++ b/include/configs/MPC8548CDS.h @@ -395,6 +395,14 @@ extern unsigned long get_clock_freq(void); #define CFG_RIO_MEM_SIZE 0x20000000 /* 512M */ #endif +#ifdef CONFIG_LEGACY +#define BRIDGE_ID 17 +#define VIA_ID 2 +#else +#define BRIDGE_ID 28 +#define VIA_ID 4 +#endif + #if defined(CONFIG_PCI) #define CONFIG_NET_MULTI diff --git a/include/configs/MPC8555CDS.h b/include/configs/MPC8555CDS.h index a3025bd71..e8fe99aaf 100644 --- a/include/configs/MPC8555CDS.h +++ b/include/configs/MPC8555CDS.h @@ -350,6 +350,13 @@ extern unsigned long get_clock_freq(void); #define CFG_PCI2_IO_PHYS 0xe2100000 #define CFG_PCI2_IO_SIZE 0x00100000 /* 1M */ +#ifdef CONFIG_LEGACY +#define BRIDGE_ID 17 +#define VIA_ID 2 +#else +#define BRIDGE_ID 28 +#define VIA_ID 4 +#endif #if defined(CONFIG_PCI) From 85eb5caf6b906f7ec5b54814e8c7c74f55986bb7 Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Tue, 14 Aug 2007 09:47:27 +0200 Subject: [PATCH 105/259] Coding style cleanup; rebuild CHANGELOG --- CHANGELOG | 153 ++++++++++++++++++++++++++++++++++++++++++++++ drivers/rtl8139.c | 6 +- net/eth.c | 8 +-- net/net.c | 2 +- net/tftp.c | 36 +++++------ 5 files changed, 180 insertions(+), 25 deletions(-) diff --git a/CHANGELOG b/CHANGELOG index 57299b65f..6ebf48725 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -1,3 +1,56 @@ +commit 53a5c424bf8655b7b4e2c305a441963259a26a81 +Author: David Updegraff +Date: Mon Jun 11 10:41:07 2007 -0500 + + multicast tftp: RFC2090 + + Implemented IETF RFC2090, Multicast TFTP. Initial implementation + on Realtek RTL8139 and Freescale TSEC. + + Signed-off-by: David Updegraff + Signed-off-by: Ben Warren + +commit 5d110f0aa69f065ee386ec1840dfee1e8cc46bc1 +Author: Wilson Callan +Date: Sat Jul 28 10:56:13 2007 -0400 + + New CONFIG_BOOTP_SERVERIP option + + Added CONFIG_BOOTP_SERVERIP to allow the tftp server to be different + from the bootp server + + Signed-off-by: Wilson Callan + Signed-off-by: Ben Warren + +commit 50cca8b976ec74069860208c36e64ce8f4d5e4c1 +Author: Mike Rapoport +Date: Sun Aug 12 08:48:27 2007 +0300 + + Add ability to take MAC address from the environment to DM9000 driver + + Signed-off-by: Mike Rapoport + Signed-off-by: Ben Warren + +commit be5d72d10d47609326226225181e301fb9a33b58 +Author: Wolfgang Denk +Date: Mon Aug 13 21:57:53 2007 +0200 + + Minor coding style cleanup. Update CHANGELOG. + + Signed-off-by: Wolfgang Denk + +commit cca34967cbd13ff6bd352be29e3f1cc88ab24c05 +Author: Joe Hamman +Date: Sat Aug 11 06:54:58 2007 -0500 + + Modify SBC8641D to use new Freescale PCI routines + + PCI-Express sockets 1 and 2 verified working with Intel Pro/1000 PT + adapter. + + Signed-off-by: Joe Hamman + Signde-off-by: Jon Loeliger + commit a08458303e7f9db67f296980036d3292c35cb45c Author: Haavard Skinnemoen Date: Fri Jun 29 18:38:51 2007 +0200 @@ -365,6 +418,30 @@ Date: Fri Aug 10 15:48:59 2007 +0800 Signed-off-by: Dave Liu +commit c646bba6465a45c60746d4cc1602cd06c1960f2d +Author: Joe Hamman +Date: Thu Aug 9 15:11:03 2007 -0500 + + Add support for SBC8641D. Config files. + + Add support for Wind River's SBC8641D reference board. + + Signed-off by: Joe Hamman + Acked-by: Wolfgang Denk + Acked-by: Jon Loeliger + +commit 8ac273271d57321f90505c7a51cdb1ef2113b628 +Author: Joe Hamman +Date: Thu Aug 9 15:10:53 2007 -0500 + + Add support for SBC8641D. Board files. + + Add support for Wind River's SBC8641D reference board. + + Signed-off by: Joe Hamman + Acked-by: Wolfgang Denk + Acked-by: Jon Loeliger + commit c2c0ab4aff86622b837a48a0e560351f9afafb95 Author: Stefan Roese Date: Fri Aug 10 20:34:58 2007 +0200 @@ -420,6 +497,62 @@ Date: Fri Aug 10 20:26:18 2007 +0200 Acked-by: Zach Sadecki Acked-by: Stefan Roese +commit 2e4d94f1e3c2961428967a33b6ff2520568391b3 +Author: Ed Swarthout +Date: Fri Jul 27 01:50:45 2007 -0500 + + fsl_pci_init cleanup. + + Do not enable normal errors created during probe (master abort, perr, + and pcie Invalid Configuration access). + + Add CONFIG_PCI_NOSCAN board option to prevent bus scan. + + Signed-off-by: Ed Swarthout + Acked-by: Andy Fleming + +commit 936b3e69b667c3eb9a61ece4e78647d3fce9fc2a +Author: Ed Swarthout +Date: Fri Jul 27 01:50:44 2007 -0500 + + pciauto_setup_device bars_num fix + + Passing bars_num=0 to pciauto_setup_device should assign no bars. + + Signed-off-by: Ed Swarthout + Acked-by: Shinya Kuribayashi + Acked-by: Andy Fleming + +commit cf0b185e58ca0aec8ae2b2a8804ec0ef58ee21d4 +Author: Jon Loeliger +Date: Mon Aug 6 17:39:44 2007 -0500 + + 8641hpcn: Do correct sized pointer math. + + When I rebased Ed's patch and cleaned up a few compilation + problems, I apparently rebased my brain on crack first. + Fix that by doing (char *) sized pointer math as needed. + + Signed-off-by: Jon Loeliger + +commit cfc7a7f5bb3273c9951173c788001d45118f141f +Author: Jon Loeliger +Date: Thu Aug 2 14:42:20 2007 -0500 + + cpu/86xx fixes. + + Remove rev 1 fixes. + Always set PICGCR_MODE. + Enable machine check and provide board config option + to set and handle SoC error interrupts. + + Include MSSSR0 in error message. + + Isolate a RAMBOOT bit of code with #ifdef CFG_RAMBOOT. + + Signed-off-by: Ed Swarthout + Signed-off-by: Jon Loeliger + commit 3a6d56c20989fe27360afe743bd2a7ad4d76e48f Author: Dirk Behme Date: Thu Aug 2 17:42:08 2007 +0200 @@ -2887,6 +3020,26 @@ Date: Fri Jun 8 09:55:24 2007 +0200 Signed-off-by: Benoit Monin Signed-off-by: Stefan Roese +commit f539edc076cfe52bff919dd512ba8d7af0e22092 +Author: Vadim Bendebury +Date: Thu May 24 15:52:25 2007 -0700 + + cosmetic changes to bcm570x driver + + This is a cosmetic only changes submission. + It affects files relevant to bcm570x driver. + the commands used to generate this change was + + cd drivers + Lindent -pcs -l80 bcm570x.c bcm570x_lm.h bcm570x_mm.h tigon3.c tigon3.h + + The BMW target (the only one using this chip so far) builds cleanly, the + `before and after' generated object files for drivers/bcm570x.c and + drivers/tigon3.o are identical as reported by objdump -d + + Signed-off-by: Vadim Bendebury + Signed-off-by: Ben Warren + commit 725671ccd2cd04c9ebc50c9e5a94dd8cbade66b7 Author: Wolfgang Denk Date: Wed Jun 6 16:26:56 2007 +0200 diff --git a/drivers/rtl8139.c b/drivers/rtl8139.c index 3e259b6b1..236718005 100644 --- a/drivers/rtl8139.c +++ b/drivers/rtl8139.c @@ -194,8 +194,10 @@ static int rtl_transmit(struct eth_device *dev, volatile void *packet, int lengt static int rtl_poll(struct eth_device *dev); static void rtl_disable(struct eth_device *dev); #ifdef CONFIG_MCAST_TFTP/* This driver already accepts all b/mcast */ -static int rtl_bcast_addr (struct eth_device *dev, u8 bcast_mac, u8 set) - { return (0); } +static int rtl_bcast_addr (struct eth_device *dev, u8 bcast_mac, u8 set) +{ + return (0); +} #endif static struct pci_device_id supported[] = { diff --git a/net/eth.c b/net/eth.c index 9ccbccac0..c2c23f6f1 100644 --- a/net/eth.c +++ b/net/eth.c @@ -356,12 +356,12 @@ void eth_set_enetaddr(int num, char *addr) { #ifdef CONFIG_MCAST_TFTP /* Multicast. * mcast_addr: multicast ipaddr from which multicast Mac is made - * join: 1=join, 0=leave. + * join: 1=join, 0=leave. */ int eth_mcast_join( IPaddr_t mcast_ip, u8 join) { u8 mcast_mac[6]; - if (!eth_current || !eth_current->mcast) + if (!eth_current || !eth_current->mcast) return -1; mcast_mac[5] = htonl(mcast_ip) & 0xff; mcast_mac[4] = (htonl(mcast_ip)>>8) & 0xff; @@ -372,8 +372,8 @@ int eth_mcast_join( IPaddr_t mcast_ip, u8 join) return eth_current->mcast(eth_current, mcast_mac, join); } -/* the 'way' for ethernet-CRC-32. Spliced in from Linux lib/crc32.c - * and this is the ethernet-crc method needed for TSEC -- and perhaps +/* the 'way' for ethernet-CRC-32. Spliced in from Linux lib/crc32.c + * and this is the ethernet-crc method needed for TSEC -- and perhaps * some other adapter -- hash tables */ #define CRCPOLY_LE 0xedb88320 diff --git a/net/net.c b/net/net.c index 2b11a1365..c47610e74 100644 --- a/net/net.c +++ b/net/net.c @@ -1391,7 +1391,7 @@ NetReceive(volatile uchar * inpkt, int len) tmp = NetReadIP(&ip->ip_dst); if (NetOurIP && tmp != NetOurIP && tmp != 0xFFFFFFFF) { #ifdef CONFIG_MCAST_TFTP - if (Mcast_addr != tmp) + if (Mcast_addr != tmp) #endif return; } diff --git a/net/tftp.c b/net/tftp.c index 95fee775e..888ec987c 100644 --- a/net/tftp.c +++ b/net/tftp.c @@ -61,8 +61,8 @@ static char *tftp_filename; extern flash_info_t flash_info[]; #endif -/* 512 is poor choice for ethernet, MTU is typically 1500. - * Minus eth.hdrs thats 1468. Can get 2x better throughput with +/* 512 is poor choice for ethernet, MTU is typically 1500. + * Minus eth.hdrs thats 1468. Can get 2x better throughput with * almost-MTU block sizes. At least try... fall back to 512 if need be. */ #define TFTP_MTU_BLOCKSIZE 1468 @@ -145,11 +145,11 @@ TftpSend (void) int len = 0; volatile ushort *s; -#ifdef CONFIG_MCAST_TFTP +#ifdef CONFIG_MCAST_TFTP /* Multicast TFTP.. non-MasterClients do not ACK data. */ - if (Multicast - && (TftpState == STATE_DATA) - && (MasterClient == 0)) + if (Multicast + && (TftpState == STATE_DATA) + && (MasterClient == 0)) return; #endif /* @@ -179,10 +179,10 @@ TftpSend (void) /* try for more effic. blk size */ pkt += sprintf((char *)pkt,"blksize%c%d%c", 0,htons(TftpBlkSizeOption),0); -#ifdef CONFIG_MCAST_TFTP +#ifdef CONFIG_MCAST_TFTP /* Check all preconditions before even trying the option */ - if (!ProhibitMcast - && (Bitmap=malloc(Mapsize)) + if (!ProhibitMcast + && (Bitmap=malloc(Mapsize)) && eth_get_dev()->mcast) { free(Bitmap); Bitmap=NULL; @@ -244,7 +244,7 @@ TftpHandler (uchar * pkt, unsigned dest, unsigned src, unsigned len) if (dest != TftpOurPort) { #ifdef CONFIG_MCAST_TFTP - if (Multicast + if (Multicast && (!Mcast_port || (dest != Mcast_port))) #endif return; @@ -290,7 +290,7 @@ TftpHandler (uchar * pkt, unsigned dest, unsigned src, unsigned len) } #ifdef CONFIG_MCAST_TFTP parse_multicast_oack((char *)pkt,len-1); - if ((Multicast) && (!MasterClient)) + if ((Multicast) && (!MasterClient)) TftpState = STATE_DATA; /* passive.. */ else #endif @@ -366,14 +366,14 @@ TftpHandler (uchar * pkt, unsigned dest, unsigned src, unsigned len) * the server for the next one. */ #ifdef CONFIG_MCAST_TFTP - /* if I am the MasterClient, actively calculate what my next - * needed block is; else I'm passive; not ACKING + /* if I am the MasterClient, actively calculate what my next + * needed block is; else I'm passive; not ACKING */ if (Multicast) { if (len < TftpBlkSize) { TftpEndingBlock = TftpBlock; } else if (MasterClient) { - TftpBlock = PrevBitmapHole = + TftpBlock = PrevBitmapHole = ext2_find_next_zero_bit( Bitmap, (Mapsize*8), @@ -398,7 +398,7 @@ TftpHandler (uchar * pkt, unsigned dest, unsigned src, unsigned len) puts ("\nMulticast tftp done\n"); mcast_cleanup(); NetState = NETLOOP_SUCCESS; - } + } } else #endif @@ -555,7 +555,7 @@ static void parse_multicast_oack(char *pkt, int len) break; if (i >= (len-14)) /* non-Multicast OACK, ign. */ return; - + i+=10; /* strlen multicast */ mc_adr = pkt+i; for (;i Date: Tue, 14 Aug 2007 09:54:46 +0200 Subject: [PATCH 106/259] Coding style cleanup, update CHANGELOG Signed-off-by: Wolfgang Denk --- CHANGELOG | 228 +++++++++++++++++++++++++++++++++++++++++++ doc/README.mpc8544ds | 2 +- 2 files changed, 229 insertions(+), 1 deletion(-) diff --git a/CHANGELOG b/CHANGELOG index 6ebf48725..5472c8fe5 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -1,3 +1,231 @@ +commit 85eb5caf6b906f7ec5b54814e8c7c74f55986bb7 +Author: Wolfgang Denk +Date: Tue Aug 14 09:47:27 2007 +0200 + + Coding style cleanup; rebuild CHANGELOG + +commit 7f3f2bd2dc08e0b05e185662ca2e2d283757104a +Author: Randy Vinson +Date: Tue Feb 27 19:42:22 2007 -0700 + + 85xxCDS: Add make targets for legacy systems. + + The PCI ID select values on the Arcadia main board differ depending + on the version of the hardware. The standard configuration supports + Rev 3.1. The legacy target supports Rev 2.x. + + Signed-off-by Randy Vinson + +commit e41094c7e38177c755fbd9b182018069614f080d +Author: Andy Fleming +Date: Tue Aug 14 01:50:09 2007 -0500 + + 85xxCDS: Enable the VIA PCI-to-ISA bridge. + + Author: Randy Vinson + + Enable the PCI-to-ISA bridge in the VIA Southbridge located on the + Arcadia main board. + + Signed-off-by: Randy Vinson + Signed-off-by: York Sun + +commit da9d4610d76e52c4d20a8f3d8433439a7fcf5b71 +Author: Andy Fleming +Date: Tue Aug 14 00:14:25 2007 -0500 + + Add support for UEC to 8568 + + Signed-off-by: Haiying Wang + Signed-off-by: Andy Fleming + +commit c59e4091ffe0148398b9e9ff14a019ea038b7432 +Author: Haiying Wang +Date: Tue Jun 19 14:18:34 2007 -0400 + + Add PCI support for MPC8568MDS board + + This patch is against u-boot-mpc85xx.git of www.denx.com + + Signed-off-by: Haiying Wang + Signed-off-by: Ebony Zhu + +commit d111d6382c99fdea08c2312eeeae8786945e189a +Author: Haiying Wang +Date: Tue Jun 19 14:18:32 2007 -0400 + + Empirically set cpo and clk_adjust for mpc85xx DDR2 support + + This patch is against u-boot-mpc85xx.git of www.denx.com + + Setting cpo to 0x9 for frequencies higher than 333MHz is verified on + both MPC8548CDS board and MPC8568MDS board, especially for supporting + 533MHz DDR2. + + Setting clk_adjust to 0x6(3/4 late cycle) for MPC8568MDS board is for + DDR2 on all current board versions especially ver 1.92 or later to bring + up. + + Signed-off-by: Haiying Wang + +commit 3db0bef59eab1155801618cef5c481e97553b597 +Author: Kumar Gala +Date: Tue Aug 7 18:07:27 2007 -0500 + + Use an absolute address when jumping out of 4k boot page + + On e500 when we leave the 4k boot page we should use an absolute address since + we don't know where the board code may want us to be really running at. + + Signed-off-by: Kumar Gala + +commit 39980c610c9a4c381907c9e1d1b9c0e1c0dca57a +Author: Andy Fleming +Date: Mon Aug 13 14:49:59 2007 -0500 + + MPC85xx BA bits not set for 3-bit bank address DIMM + + The current implementation does not set the number of bank address bits + (BA) in the processor. The default assumes 2 logical bank bits. This + works fine for a DIMM that uses devices with 4 internal banks (SPD + byte17 = 0x4) but needs to be set appropriately for a DIMM that uses + devices with 8 internal banks (SPD byte17 = 0x8). + + Signed-off-by: Greg Davis + +commit 6c543597bb4b1ecf5d8589f7abb0f39929fb7fd1 +Author: Andy Fleming +Date: Mon Aug 13 14:38:06 2007 -0500 + + Fix minor 85xx warnings + + Some patches had inserted warnings into the build: + * mpc8560ads declared data without using it + * cpu_init declared ecm and immap without using it in all CONFIGs + * MPC8548CDS.h had its default filenames changed so that they contained + "\m" in the paths. Made the defaults not Windows-specific (or + anything-specific) + + Signed-off-by: Andy Fleming + +commit f2cff6b104f82b993bef6086ce0c97159bbe1add +Author: Ed Swarthout +Date: Fri Jul 27 01:50:52 2007 -0500 + + 8548cds PCIE support. + + Make the early L1 cache stack region guarded to prevent speculative + fetches outside the locked range. + + Use _PHYS defines, not _MEM for cpu-side PCI memory mapped regions. + init.S whitespace cleanup. + + Allow TEXT_BASE value to be specified on command line. This allows it + to be set to 0xfffc0000 which cuts the uboot binary in half. + + Clear and enable lbc and ecm errors. + + Update last_busno in device-tree for pci and pcie. + + Remove load of obsolete cpu/mpc85xx/pci.0 + + Signed-off-by: Ed Swarthout + Acked-by: Andy Fleming + +commit 837f1ba05cfb248aba5ab8e1fb1bfeefa07d5962 +Author: Ed Swarthout +Date: Fri Jul 27 01:50:51 2007 -0500 + + 8544ds PCIE support + + PCI1 LAW mapping should use CFG_PCI1_MEM_PHY and not _BASE address. + + Enable LBC and ECM errors and clear error registers. + + Add tftpflash env var to get uboot from tftp server and flash it. + + Add pci/pcie convenience env vars to display register space: + "run pcie3regs" to see all pcie3 ccsr registers + "run pcie3cfg" to see all cfg registers + Whitespace cleanup and MPC8544DS.h + + Enable CONFIG_INTERRUPTS. + + Signed-off-by: Ed Swarthout + Acked-by: Andy Fleming + +commit 61a21e980a7b9188424d04f1c265fdc5c21c7e85 +Author: Andy Fleming +Date: Tue Aug 14 01:34:21 2007 -0500 + + 85xx start.S cleanup and exception support + + From: Ed Swarthout + + Support external interrupts from platform to eliminate system hangs. + Define CONFIG_INTERRUPTS board configure option to enable. + Enable ecm, ddr, lbc, and pci/pcie error interrupts in PIC. + + Remove extra cpu initialization redundant with hardware initialization. + Whitespace cleanup. + + Define and use _START_OFFSET consistent with other processors using + ppc_asm.tmpl + + Move additional code from .text to boot page to make room for + exception vectors at start of image. + + Handle Machine Check, External and Critical exceptions. + + Fix e500 machine check error determination in traps.c + + TEXT_BASE can now be 0xfffc_0000 - which cuts binary image in half. + + Signed-off-by: Ed Swarthout + Acked-by: Andy Fleming + +commit 7bd30fc4a6475b41d6679ae3aafc9fa505260c47 +Author: Andy Fleming +Date: Tue Aug 14 01:33:18 2007 -0500 + + Add MPC8544DS README + + Signed-off-by: Andy Fleming + +commit 40c7f9b0de4e300370adfc704128fa0f79a143b6 +Author: Ed Swarthout +Date: Fri Jul 27 01:50:48 2007 -0500 + + 85xx allow debugger to configure ddr. + + Only check for mpc8548 rev 1 when compiled for 8548. + + Signed-off-by: Ed Swarthout + Acked-by: Andy Fleming + +commit 29372ff38c5baab7d0e3a8c14fe11fa194a38704 +Author: Ed Swarthout +Date: Fri Jul 27 01:50:47 2007 -0500 + + mpc85xx L2 cache reporting and SRAM relocation option. + + Allow debugger to override flash cs0/cs1 settings to enable alternate + boot regions + + Signed-off-by: Ed Swarthout + Acked-by: Andy Fleming + +commit 41f0f8fb1ab92f0cba7d329de90070f822f8299f +Author: Ed Swarthout +Date: Fri Jul 27 01:50:46 2007 -0500 + + e500 needs ppc_asm.tmp MCK_EXCEPTION + + Always define MCK_EXCEPTION macro - so e500 can use it too. + + Signed-off-by: Ed Swarthout + Acked-by: Andy Fleming + commit 53a5c424bf8655b7b4e2c305a441963259a26a81 Author: David Updegraff Date: Mon Jun 11 10:41:07 2007 -0500 diff --git a/doc/README.mpc8544ds b/doc/README.mpc8544ds index 14c7f765e..bf257a005 100644 --- a/doc/README.mpc8544ds +++ b/doc/README.mpc8544ds @@ -98,7 +98,7 @@ Likely, that .dts file will come from here; linux-2.6/arch/powerpc/boot/dts/mpc8544ds.dts -After placing the DTB file in your TFTP disk area, +After placing the DTB file in your TFTP disk area, you can download that dtb file using a command like: tftp 900000 mpc8544ds.dtb From d4fc6012fd0a5c211b825691f44b06f8032c0551 Mon Sep 17 00:00:00 2001 From: Peter Pearse Date: Tue, 14 Aug 2007 10:10:52 +0100 Subject: [PATCH 107/259] Add MACH_TYPE records for several AT91 boards. Merge to two at45.c files into a common file, split to at45.c and spi.c Fix spelling error in DM9161 PHY Support. Initialize at91rm9200 board (and set LED). Add PIO control for at91rm9200dk LEDs and Mux. Change dataflash partition boundaries to be compatible with Linux 2.6. Signed-off-by: Peter Pearse Signed-off-by: Ulf Samuelsson --- board/at91rm9200dk/Makefile | 2 +- common/soft_i2c.c | 2 +- cpu/arm920t/at91rm9200/Makefile | 2 +- cpu/arm920t/at91rm9200/dm9161.c | 11 +- cpu/arm920t/start.S | 93 ++++++- drivers/dataflash.c | 279 ++++++++++++++----- include/asm-arm/arch-at91rm9200/AT91RM9200.h | 139 +++++---- include/asm-arm/mach-types.h | 69 +++++ include/config_cmd_all.h | 1 + include/configs/at91rm9200dk.h | 5 + include/dataflash.h | 43 ++- include/dm9161.h | 4 +- include/flash.h | 5 + 13 files changed, 516 insertions(+), 139 deletions(-) diff --git a/board/at91rm9200dk/Makefile b/board/at91rm9200dk/Makefile index 0fcafd9b0..7dfc27f0a 100644 --- a/board/at91rm9200dk/Makefile +++ b/board/at91rm9200dk/Makefile @@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a -COBJS := at91rm9200dk.o at45.o flash.o +COBJS := at91rm9200dk.o at45.o flash.o led.o mux.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/common/soft_i2c.c b/common/soft_i2c.c index 0f6e3a938..c5d7e205e 100644 --- a/common/soft_i2c.c +++ b/common/soft_i2c.c @@ -29,7 +29,7 @@ #ifdef CONFIG_MPC8260 /* only valid for MPC8260 */ #include #endif -#ifdef CONFIG_AT91RM9200DK /* need this for the at91rm9200dk */ +#ifdef CONFIG_AT91RM9200 /* need this for the at91rm9200 */ #include #include #endif diff --git a/cpu/arm920t/at91rm9200/Makefile b/cpu/arm920t/at91rm9200/Makefile index eaabad26a..ab4c52c8f 100644 --- a/cpu/arm920t/at91rm9200/Makefile +++ b/cpu/arm920t/at91rm9200/Makefile @@ -26,7 +26,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(SOC).a COBJS = bcm5221.o dm9161.o ether.o i2c.o interrupts.o \ - lxt972.o serial.o usb.o + lxt972.o serial.o usb.o spi.o SOBJS = lowlevel_init.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) diff --git a/cpu/arm920t/at91rm9200/dm9161.c b/cpu/arm920t/at91rm9200/dm9161.c index 968f65308..1beb6e8ba 100644 --- a/cpu/arm920t/at91rm9200/dm9161.c +++ b/cpu/arm920t/at91rm9200/dm9161.c @@ -95,7 +95,7 @@ UCHAR dm9161_GetLinkSpeed (AT91PS_EMAC p_mac) return TRUE; } - if ((stat1 & DM9161_100BASE_T4_HD) && (stat2 & DM9161_100HDX)) { + if ((stat1 & DM9161_100BASE_TX_HD) && (stat2 & DM9161_100HDX)) { /*set MII for 100BaseTX and Half Duplex */ p_mac->EMAC_CFG = (p_mac->EMAC_CFG & ~(AT91C_EMAC_SPD | AT91C_EMAC_FD)) @@ -140,7 +140,7 @@ UCHAR dm9161_InitPhy (AT91PS_EMAC p_mac) at91rm9200_EmacReadPhy (p_mac, DM9161_MDINTR, &IntValue); /* set FDX, SPD, Link, INTR masks */ IntValue |= (DM9161_FDX_MASK | DM9161_SPD_MASK | - DM9161_LINK_MASK | DM9161_INTR_MASK); + DM9161_LINK_MASK | DM9161_INTR_MASK); at91rm9200_EmacWritePhy (p_mac, DM9161_MDINTR, &IntValue); at91rm9200_EmacDisableMDIO (p_mac); @@ -174,10 +174,11 @@ UCHAR dm9161_AutoNegotiate (AT91PS_EMAC p_mac, int *status) if (!at91rm9200_EmacWritePhy (p_mac, DM9161_BMCR, &value)) return FALSE; - /* Set the Auto_negotiation Advertisement Register */ - /* MII advertising for Next page, 100BaseTxFD and HD, 10BaseTFD and HD, IEEE 802.3 */ + /* Set the Auto_negotiation Advertisement Register */ + /* MII advertising for Next page, 100BaseTxFD and HD, */ + /* 10BaseTFD and HD, IEEE 802.3 */ PhyAnar = DM9161_NP | DM9161_TX_FDX | DM9161_TX_HDX | - DM9161_10_FDX | DM9161_10_HDX | DM9161_AN_IEEE_802_3; + DM9161_10_FDX | DM9161_10_HDX | DM9161_AN_IEEE_802_3; if (!at91rm9200_EmacWritePhy (p_mac, DM9161_ANAR, &PhyAnar)) return FALSE; diff --git a/cpu/arm920t/start.S b/cpu/arm920t/start.S index 346f0d09e..b9c364bc6 100644 --- a/cpu/arm920t/start.S +++ b/cpu/arm920t/start.S @@ -27,7 +27,9 @@ #include #include - +#if defined(CONFIG_AT91RM9200DK) || defined(CONFIG_AT91RM9200EK) || defined(CONFIG_AT91RM9200DF) +#include +#endif /* ************************************************************************* @@ -116,6 +118,69 @@ reset: orr r0,r0,#0xd3 msr cpsr,r0 +#if CONFIG_AT91RM9200 +#if defined(CONFIG_AT91RM9200DK) || defined(CONFIG_AT91RM9200EK) || defined(CONFIG_AT91RM9200DF) + bl LED_init + bl red_LED_on +#endif + +#ifdef CONFIG_BOOTBINFUNC +/* code based on entry.S from ATMEL */ +#define AT91C_BASE_CKGR 0xFFFFFC20 +#define CKGR_MOR 0 + /* Get the CKGR Base Address */ + ldr r1, =AT91C_BASE_CKGR + +/* Main oscillator Enable register APMC_MOR : Enable main oscillator , OSCOUNT = 0xFF */ +/* ldr r0, = AT91C_CKGR_MOSCEN:OR:AT91C_CKGR_OSCOUNT */ + ldr r0, =0x0000FF01 + str r0, [r1, #CKGR_MOR] + /* Add loop to compensate Main Oscillator startup time */ + ldr r0, =0x00000010 +LoopOsc: + subs r0, r0, #1 + bhi LoopOsc + /* scratch stack */ + ldr r1, =0x00204000 + /* Insure word alignment */ + bic r1, r1, #3 + /* Init stack SYS */ + mov sp, r1 + /* + * This does a lot more than just set up the memory, which + * is why it's called lowlevelinit + */ + bl lowlevelinit /* in memsetup.S */ + bl icache_enable; + /* ------------------------------------ + * Read/modify/write CP15 control register + * ------------------------------------- + * read cp15 control register (cp15 r1) in r0 + * ------------------------------------ + */ + mrc p15, 0, r0, c1, c0, 0 + /* Reset bit :Little Endian end fast bus mode */ + ldr r3, =0xC0000080 + /* Set bit :Asynchronous clock mode, Not Fast Bus */ + ldr r4, =0xC0000000 + bic r0, r0, r3 + orr r0, r0, r4 + /* write r0 in cp15 control register (cp15 r1) */ + mcr p15, 0, r0, c1, c0, 0 +#endif /* CONFIG_BOOTBINFUNC */ + /* + * relocate exeception table + */ + ldr r0, =_start + ldr r1, =0x0 + mov r2, #16 +copyex: + subs r2, r2, #1 + ldr r3, [r0], #4 + str r3, [r1], #4 + bne copyex +#endif + /* turn off the watchdog */ #if defined(CONFIG_S3C2400) # define pWTCON 0x15300000 @@ -160,6 +225,26 @@ reset: bl cpu_init_crit #endif +#ifdef CONFIG_AT91RM9200 +#ifdef CONFIG_BOOTBINFUNC +relocate: /* relocate U-Boot to RAM */ + adr r0, _start /* r0 <- current position of code */ + ldr r1, _TEXT_BASE /* test if we run from flash or RAM */ + cmp r0, r1 /* don't reloc during debug */ + beq stack_setup + + ldr r2, _armboot_start + ldr r3, _bss_start + sub r2, r3, r2 /* r2 <- size of armboot */ + add r2, r0, r2 /* r2 <- source end address */ + +copy_loop: + ldmia r0!, {r3-r10} /* copy from source address [r0] */ + stmia r1!, {r3-r10} /* copy to target address [r1] */ + cmp r0, r2 /* until source end addreee [r2] */ + ble copy_loop +#endif /* CONFIG_BOOTBINFUNC */ +#else #ifndef CONFIG_SKIP_RELOCATE_UBOOT relocate: /* relocate U-Boot to RAM */ adr r0, _start /* r0 <- current position of code */ @@ -178,7 +263,7 @@ copy_loop: cmp r0, r2 /* until source end addreee [r2] */ ble copy_loop #endif /* CONFIG_SKIP_RELOCATE_UBOOT */ - +#endif /* Set up the stack */ stack_setup: ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */ @@ -262,7 +347,11 @@ cpu_init_crit: * find a lowlevel_init.S in your board directory. */ mov ip, lr +#if defined(CONFIG_AT91RM9200DK) || defined(CONFIG_AT91RM9200EK) || defined(CONFIG_AT91RM9200DF) + +#else bl lowlevel_init +#endif mov lr, ip mov pc, lr #endif /* CONFIG_SKIP_LOWLEVEL_INIT */ diff --git a/drivers/dataflash.c b/drivers/dataflash.c index 17eb8597f..3b068d712 100644 --- a/drivers/dataflash.c +++ b/drivers/dataflash.c @@ -26,18 +26,67 @@ AT91S_DATAFLASH_INFO dataflash_info[CFG_MAX_DATAFLASH_BANKS]; static AT91S_DataFlash DataFlashInst; +#ifdef CONFIG_AT91SAM9260EK +int cs[][CFG_MAX_DATAFLASH_BANKS] = { + {CFG_DATAFLASH_LOGIC_ADDR_CS0, 0}, /* Logical adress, CS */ + {CFG_DATAFLASH_LOGIC_ADDR_CS1, 1} +}; +#elif defined(CONFIG_AT91SAM9263EK) +int cs[][CFG_MAX_DATAFLASH_BANKS] = { + {CFG_DATAFLASH_LOGIC_ADDR_CS0, 0} /* Logical adress, CS */ +}; +#else int cs[][CFG_MAX_DATAFLASH_BANKS] = { {CFG_DATAFLASH_LOGIC_ADDR_CS0, 0}, /* Logical adress, CS */ {CFG_DATAFLASH_LOGIC_ADDR_CS3, 3} }; +#endif /*define the area offsets*/ +#if defined(CONFIG_AT91SAM9261EK) || defined(CONFIG_AT91SAM9260EK) || defined(CONFIG_AT91SAM9263EK) +#if defined(CONFIG_NEW_PARTITION) +dataflash_protect_t area_list[NB_DATAFLASH_AREA] = { + {0x00000000, 0x00003FFF, FLAG_PROTECT_SET, 0, "Bootstrap"}, /* ROM code */ + {0x00004200, 0x000083FF, FLAG_PROTECT_CLEAR, 0, "Environment"}, /* u-boot environment */ + {0x00008400, 0x0003DDFF, FLAG_PROTECT_SET, 0, "U-Boot"}, /* u-boot code */ + {0x0003DE00, 0x00041FFF, FLAG_PROTECT_CLEAR, FLAG_SETENV, "MON"}, /* Room for alternative boot monitor */ + {0x00042000, 0x0018BFFF, FLAG_PROTECT_CLEAR, FLAG_SETENV, "OS"}, /* data area size to tune */ + {0x0018C000, 0xFFFFFFFF, FLAG_PROTECT_CLEAR, FLAG_SETENV, "FS"}, /* data area size to tune */ +}; +#else +dataflash_protect_t area_list[NB_DATAFLASH_AREA] = { + {0, 0x3fff, FLAG_PROTECT_SET}, /* ROM code */ + {0x4000, 0x7fff, FLAG_PROTECT_CLEAR}, /* u-boot environment */ + {0x8000, 0x37fff, FLAG_PROTECT_SET}, /* u-boot code */ + {0x38000, 0x1fffff, FLAG_PROTECT_CLEAR}, /* data area size to tune */ +}; +#endif +#elif defined(CONFIG_NEW_PARTITION) +/*define the area offsets*/ +/* Invalid partitions should be defined with start > end */ +dataflash_protect_t area_list[NB_DATAFLASH_AREA*CFG_MAX_DATAFLASH_BANKS] = { + {0x00000000, 0x000083ff, FLAG_PROTECT_SET, 0, "Bootstrap"}, /* ROM code */ + {0x00008400, 0x00020fff, FLAG_PROTECT_SET, 0, "U-Boot"}, /* u-boot code */ + {0x00021000, 0x000293ff, FLAG_PROTECT_CLEAR, 0, "Environment"}, /* u-boot environment 8Kb */ + {0x00029400, 0x00041fff, FLAG_PROTECT_INVALID, 0, ""}, /* Rest of Sector 1 */ + {0x00042000, 0x0018Bfff, FLAG_PROTECT_CLEAR, FLAG_SETENV, "OS"}, /* data area size to tune */ + {0x0018C000, 0xffffffff, FLAG_PROTECT_CLEAR, FLAG_SETENV, "FS"}, /* data area size to tune */ + + {0x00000000, 0xffffffff, FLAG_PROTECT_CLEAR, FLAG_SETENV, "Data"}, /* data area */ + {0xffffffff, 0x00000000, FLAG_PROTECT_INVALID, 0, ""}, /* Invalid */ + {0xffffffff, 0x00000000, FLAG_PROTECT_INVALID, 0, ""}, /* Invalid */ + {0xffffffff, 0x00000000, FLAG_PROTECT_INVALID, 0, ""}, /* Invalid */ + {0xffffffff, 0x00000000, FLAG_PROTECT_INVALID, 0, ""}, /* Invalid */ + {0xffffffff, 0x00000000, FLAG_PROTECT_INVALID, 0, ""}, /* Invalid */ +}; +#else dataflash_protect_t area_list[NB_DATAFLASH_AREA] = { {0, 0x7fff, FLAG_PROTECT_SET}, /* ROM code */ {0x8000, 0x1ffff, FLAG_PROTECT_SET}, /* u-boot code */ {0x20000, 0x27fff, FLAG_PROTECT_CLEAR}, /* u-boot environment */ {0x28000, 0x1fffff, FLAG_PROTECT_CLEAR}, /* data area size to tune */ }; +#endif extern void AT91F_SpiInit (void); extern int AT91F_DataflashProbe (int i, AT91PS_DataflashDesc pDesc); @@ -45,22 +94,28 @@ extern int AT91F_DataFlashRead (AT91PS_DataFlash pDataFlash, unsigned long addr, unsigned long size, char *buffer); extern int AT91F_DataFlashWrite( AT91PS_DataFlash pDataFlash, - unsigned char *src, - int dest, - int size ); + unsigned char *src, + int dest, + int size ); int AT91F_DataflashInit (void) { int i, j; int dfcode; + int part = 0; + int last_part; + int found[CFG_MAX_DATAFLASH_BANKS]; + unsigned char protected; AT91F_SpiInit (); for (i = 0; i < CFG_MAX_DATAFLASH_BANKS; i++) { + found[i] = 0; dataflash_info[i].Desc.state = IDLE; dataflash_info[i].id = 0; dataflash_info[i].Device.pages_number = 0; - dfcode = AT91F_DataflashProbe (cs[i][1], &dataflash_info[i].Desc); + dfcode = AT91F_DataflashProbe (cs[i][1], + &dataflash_info[i].Desc); switch (dfcode) { case AT45DB161: @@ -72,6 +127,7 @@ int AT91F_DataflashInit (void) dataflash_info[i].Desc.DataFlash_state = IDLE; dataflash_info[i].logical_address = cs[i][0]; dataflash_info[i].id = dfcode; + found[i] += dfcode;; break; case AT45DB321: @@ -83,6 +139,7 @@ int AT91F_DataflashInit (void) dataflash_info[i].Desc.DataFlash_state = IDLE; dataflash_info[i].logical_address = cs[i][0]; dataflash_info[i].id = dfcode; + found[i] += dfcode;; break; case AT45DB642: @@ -94,7 +151,9 @@ int AT91F_DataflashInit (void) dataflash_info[i].Desc.DataFlash_state = IDLE; dataflash_info[i].logical_address = cs[i][0]; dataflash_info[i].id = dfcode; + found[i] += dfcode;; break; + case AT45DB128: dataflash_info[i].Device.pages_number = 16384; dataflash_info[i].Device.pages_size = 1056; @@ -104,9 +163,11 @@ int AT91F_DataflashInit (void) dataflash_info[i].Desc.DataFlash_state = IDLE; dataflash_info[i].logical_address = cs[i][0]; dataflash_info[i].id = dfcode; + found[i] += dfcode;; break; default: + dfcode = 0; break; } /* set the last area end to the dataflash size*/ @@ -114,16 +175,64 @@ int AT91F_DataflashInit (void) (dataflash_info[i].Device.pages_number * dataflash_info[i].Device.pages_size)-1; + last_part=0; /* set the area addresses */ for(j = 0; j (pdataFlash->pDevice->pages_size * pdataFlash->pDevice->pages_number)) return 0; /* is too large for the dataflash */ if (size > ((pdataFlash->pDevice->pages_size * - pdataFlash->pDevice->pages_number) - ((int)addr & 0x0FFFFFFF))) return 0; + pdataFlash->pDevice->pages_number) - + ((int)addr & 0x0FFFFFFF))) return 0; return 1; } -/*-----------------------------------------------------------------------------*/ -/* Function Name : prot_dataflash */ -/* Object : Test if destination area is protected */ -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ +/* Function Name : prot_dataflash */ +/* Object : Test if destination area is protected */ +/*---------------------------------------------------------------------------*/ int prot_dataflash (AT91PS_DataFlash pdataFlash, unsigned long addr) { int area; @@ -241,17 +368,23 @@ int area; (addr < pdataFlash->pDevice->area_list[area].end)) break; } - if (area == NB_DATAFLASH_AREA) return -1; + if (area == NB_DATAFLASH_AREA) + return -1; + /*test protection value*/ - if (pdataFlash->pDevice->area_list[area].protected == FLAG_PROTECT_SET) return 0; + if (pdataFlash->pDevice->area_list[area].protected == FLAG_PROTECT_SET) + return 0; + if (pdataFlash->pDevice->area_list[area].protected == FLAG_PROTECT_INVALID) + return 0; return 1; } -/*-----------------------------------------------------------------------------*/ -/* Function Name : dataflash_real_protect */ -/* Object : protect/unprotect area */ -/*-----------------------------------------------------------------------------*/ -int dataflash_real_protect (int flag, unsigned long start_addr, unsigned long end_addr) +/*--------------------------------------------------------------------------*/ +/* Function Name : dataflash_real_protect */ +/* Object : protect/unprotect area */ +/*--------------------------------------------------------------------------*/ +int dataflash_real_protect (int flag, unsigned long start_addr, + unsigned long end_addr) { int i,j, area1, area2, addr_valid = 0; /* find dataflash */ @@ -267,27 +400,38 @@ int i,j, area1, area2, addr_valid = 0; } /* find start area */ for (area1=0; area1 < NB_DATAFLASH_AREA; area1++) { - if (start_addr == dataflash_info[i].Device.area_list[area1].start) break; + if (start_addr == dataflash_info[i].Device.area_list[area1].start) + break; } if (area1 == NB_DATAFLASH_AREA) return -1; /* find end area */ for (area2=0; area2 < NB_DATAFLASH_AREA; area2++) { - if (end_addr == dataflash_info[i].Device.area_list[area2].end) break; + if (end_addr == dataflash_info[i].Device.area_list[area2].end) + break; } - if (area2 == NB_DATAFLASH_AREA) return -1; + if (area2 == NB_DATAFLASH_AREA) + return -1; /*set protection value*/ for(j = area1; j < area2+1 ; j++) - if (flag == 0) dataflash_info[i].Device.area_list[j].protected = FLAG_PROTECT_CLEAR; - else dataflash_info[i].Device.area_list[j].protected = FLAG_PROTECT_SET; + if(dataflash_info[i].Device.area_list[j].protected + != FLAG_PROTECT_INVALID) { + if (flag == 0) { + dataflash_info[i].Device.area_list[j].protected + = FLAG_PROTECT_CLEAR; + } else { + dataflash_info[i].Device.area_list[j].protected + = FLAG_PROTECT_SET; + } + } return (area2-area1+1); } -/*------------------------------------------------------------------------------*/ -/* Function Name : read_dataflash */ -/* Object : dataflash memory read */ -/*------------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ +/* Function Name : read_dataflash */ +/* Object : dataflash memory read */ +/*---------------------------------------------------------------------------*/ int read_dataflash (unsigned long addr, unsigned long size, char *result) { unsigned long AddrToRead = addr; @@ -305,12 +449,12 @@ int read_dataflash (unsigned long addr, unsigned long size, char *result) } -/*-----------------------------------------------------------------------------*/ -/* Function Name : write_dataflash */ -/* Object : write a block in dataflash */ -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ +/* Function Name : write_dataflash */ +/* Object : write a block in dataflash */ +/*---------------------------------------------------------------------------*/ int write_dataflash (unsigned long addr_dest, unsigned long addr_src, - unsigned long size) + unsigned long size) { unsigned long AddrToWrite = addr_dest; AT91PS_DataFlash pFlash = &DataFlashInst; @@ -329,7 +473,8 @@ int write_dataflash (unsigned long addr_dest, unsigned long addr_src, if (AddrToWrite == -1) return -1; - return AT91F_DataFlashWrite (pFlash, (uchar *)addr_src, AddrToWrite, size); + return AT91F_DataFlashWrite (pFlash, (uchar *)addr_src, + AddrToWrite, size); } @@ -339,22 +484,22 @@ void dataflash_perror (int err) case ERR_OK: break; case ERR_TIMOUT: - printf ("Timeout writing to DataFlash\n"); + printf("Timeout writing to DataFlash\n"); break; case ERR_PROTECTED: - printf ("Can't write to protected DataFlash sectors\n"); + printf("Can't write to protected/invalid DataFlash sectors\n"); break; case ERR_INVAL: - printf ("Outside available DataFlash\n"); + printf("Outside available DataFlash\n"); break; case ERR_UNKNOWN_FLASH_TYPE: - printf ("Unknown Type of DataFlash\n"); + printf("Unknown Type of DataFlash\n"); break; case ERR_PROG_ERROR: - printf ("General DataFlash Programming Error\n"); + printf("General DataFlash Programming Error\n"); break; default: - printf ("%s[%d] FIXME: rc=%d\n", __FILE__, __LINE__, err); + printf("%s[%d] FIXME: rc=%d\n", __FILE__, __LINE__, err); break; } } diff --git a/include/asm-arm/arch-at91rm9200/AT91RM9200.h b/include/asm-arm/arch-at91rm9200/AT91RM9200.h index 97d470484..0e01005a9 100644 --- a/include/asm-arm/arch-at91rm9200/AT91RM9200.h +++ b/include/asm-arm/arch-at91rm9200/AT91RM9200.h @@ -27,9 +27,9 @@ typedef volatile unsigned int AT91_REG; /* Hardware register definition */ -/******************************************************************************/ -/* SOFTWARE API DEFINITION FOR Timer Counter Channel Interface */ -/******************************************************************************/ +/*****************************************************************************/ +/* SOFTWARE API DEFINITION FOR Timer Counter Channel Interface */ +/*****************************************************************************/ typedef struct _AT91S_TC { AT91_REG TC_CCR; /* Channel Control Register */ @@ -45,24 +45,24 @@ typedef struct _AT91S_TC AT91_REG TC_IMR; /* Interrupt Mask Register */ } AT91S_TC, *AT91PS_TC; -#define AT91C_TC_TIMER_DIV1_CLOCK ((unsigned int) 0x0 << 0) /* (TC) MCK/2 */ -#define AT91C_TC_TIMER_DIV2_CLOCK ((unsigned int) 0x1 << 0) /* (TC) MCK/8 */ -#define AT91C_TC_TIMER_DIV3_CLOCK ((unsigned int) 0x2 << 0) /* (TC) MCK/32 */ -#define AT91C_TC_TIMER_DIV4_CLOCK ((unsigned int) 0x3 << 0) /* (TC) MCK/128 */ -#define AT91C_TC_SLOW_CLOCK ((unsigned int) 0x4 << 0) /* (TC) SLOW CLK */ -#define AT91C_TC_XC0_CLOCK ((unsigned int) 0x5 << 0) /* (TC) XC0 */ -#define AT91C_TC_XC1_CLOCK ((unsigned int) 0x6 << 0) /* (TC) XC1 */ -#define AT91C_TC_XC2_CLOCK ((unsigned int) 0x7 << 0) /* (TC) XC2 */ -#define AT91C_TCB_TC0XC0S_NONE ((unsigned int) 0x1) /* (TCB) None signal connected to XC0 */ -#define AT91C_TCB_TC1XC1S_NONE ((unsigned int) 0x1 << 2) /* (TCB) None signal connected to XC1 */ -#define AT91C_TCB_TC2XC2S_NONE ((unsigned int) 0x1 << 4) /* (TCB) None signal connected to XC2 */ -#define AT91C_TC_CLKDIS ((unsigned int) 0x1 << 1) /* (TC) Counter Clock Disable Command */ -#define AT91C_TC_SWTRG ((unsigned int) 0x1 << 2) /* (TC) Software Trigger Command */ -#define AT91C_TC_CLKEN ((unsigned int) 0x1 << 0) /* (TC) Counter Clock Enable Command */ +#define AT91C_TC_TIMER_DIV1_CLOCK ((unsigned int) 0x0 << 0) /* (TC) MCK/2 */ +#define AT91C_TC_TIMER_DIV2_CLOCK ((unsigned int) 0x1 << 0) /* (TC) MCK/8 */ +#define AT91C_TC_TIMER_DIV3_CLOCK ((unsigned int) 0x2 << 0) /* (TC) MCK/32 */ +#define AT91C_TC_TIMER_DIV4_CLOCK ((unsigned int) 0x3 << 0) /* (TC) MCK/128 */ +#define AT91C_TC_SLOW_CLOCK ((unsigned int) 0x4 << 0) /* (TC) SLOW CLK*/ +#define AT91C_TC_XC0_CLOCK ((unsigned int) 0x5 << 0) /* (TC) XC0 */ +#define AT91C_TC_XC1_CLOCK ((unsigned int) 0x6 << 0) /* (TC) XC1 */ +#define AT91C_TC_XC2_CLOCK ((unsigned int) 0x7 << 0) /* (TC) XC2 */ +#define AT91C_TCB_TC0XC0S_NONE ((unsigned int) 0x1) /* (TCB) None signal connected to XC0 */ +#define AT91C_TCB_TC1XC1S_NONE ((unsigned int) 0x1 << 2) /* (TCB) None signal connected to XC1 */ +#define AT91C_TCB_TC2XC2S_NONE ((unsigned int) 0x1 << 4) /* (TCB) None signal connected to XC2 */ +#define AT91C_TC_CLKDIS ((unsigned int) 0x1 << 1) /* (TC) Counter Clock Disable Command */ +#define AT91C_TC_SWTRG ((unsigned int) 0x1 << 2) /* (TC) Software Trigger Command */ +#define AT91C_TC_CLKEN ((unsigned int) 0x1 << 0) /* (TC) Counter Clock Enable Command */ -/******************************************************************************/ -/* SOFTWARE API DEFINITION FOR Usart */ -/******************************************************************************/ +/*****************************************************************************/ +/* SOFTWARE API DEFINITION FOR Usart */ +/*****************************************************************************/ typedef struct _AT91S_USART { AT91_REG US_CR; /* Control Register */ @@ -94,9 +94,9 @@ typedef struct _AT91S_USART AT91_REG US_PTSR; /* PDC Transfer Status Register */ } AT91S_USART, *AT91PS_USART; -/******************************************************************************/ -/* SOFTWARE API DEFINITION FOR Clock Generator Controler */ -/******************************************************************************/ +/*****************************************************************************/ +/* SOFTWARE API DEFINITION FOR Clock Generator Controler */ +/*****************************************************************************/ typedef struct _AT91S_CKGR { AT91_REG CKGR_MOR; /* Main Oscillator Register */ @@ -141,9 +141,9 @@ typedef struct _AT91S_CKGR #define AT91C_CKGR_USB_96M ((unsigned int) 0x1 << 28) /* (CKGR) Divider for USB Ports */ #define AT91C_CKGR_USB_PLL ((unsigned int) 0x1 << 29) /* (CKGR) PLL Use */ -/******************************************************************************/ -/* SOFTWARE API DEFINITION FOR Parallel Input Output Controler */ -/******************************************************************************/ +/*****************************************************************************/ +/* SOFTWARE API DEFINITION FOR Parallel Input Output Controler */ +/*****************************************************************************/ typedef struct _AT91S_PIO { AT91_REG PIO_PER; /* PIO Enable Register */ @@ -184,9 +184,9 @@ typedef struct _AT91S_PIO } AT91S_PIO, *AT91PS_PIO; -/******************************************************************************/ -/* SOFTWARE API DEFINITION FOR Debug Unit */ -/******************************************************************************/ +/*****************************************************************************/ +/* SOFTWARE API DEFINITION FOR Debug Unit */ +/*****************************************************************************/ typedef struct _AT91S_DBGU { AT91_REG DBGU_CR; /* Control Register */ @@ -242,9 +242,9 @@ typedef struct _AT91S_DBGU #define AT91C_US_PAR_NONE ((unsigned int) 0x4 << 9) /* (DBGU) No Parity */ #define AT91C_US_NBSTOP_1_BIT ((unsigned int) 0x0 << 12) /* (USART) 1 stop bit */ -/******************************************************************************/ -/* SOFTWARE API DEFINITION FOR Static Memory Controller 2 Interface */ -/******************************************************************************/ +/*****************************************************************************/ +/* SOFTWARE API DEFINITION FOR Static Memory Controller 2 Interface */ +/*****************************************************************************/ typedef struct _AT91S_SMC2 { AT91_REG SMC2_CSR[8]; /* SMC2 Chip Select Register */ @@ -267,9 +267,9 @@ typedef struct _AT91S_SMC2 #define AT91C_SMC2_RWSETUP ((unsigned int) 0x7 << 24) /* (SMC2) Read and Write Signal Setup Time */ #define AT91C_SMC2_RWHOLD ((unsigned int) 0x7 << 29) /* (SMC2) Read and Write Signal Hold Time */ -/******************************************************************************/ -/* SOFTWARE API DEFINITION FOR Power Management Controler */ -/******************************************************************************/ +/*****************************************************************************/ +/* SOFTWARE API DEFINITION FOR Power Management Controler */ +/*****************************************************************************/ typedef struct _AT91S_PMC { AT91_REG PMC_SCER; /* System Clock Enable Register */ @@ -341,9 +341,9 @@ typedef struct _AT91S_PMC /*-------- PMC_SR : (PMC Offset: 0x68) PMC Status Register --------*/ /*-------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register --------*/ -/******************************************************************************/ -/* SOFTWARE API DEFINITION FOR Ethernet MAC */ -/******************************************************************************/ +/*****************************************************************************/ +/* SOFTWARE API DEFINITION FOR Ethernet MAC */ +/*****************************************************************************/ typedef struct _AT91S_EMAC { AT91_REG EMAC_CTL; /* Network Control Register */ @@ -424,11 +424,11 @@ typedef struct _AT91S_EMAC #define AT91C_EMAC_MDIO ((unsigned int) 0x1 << 1) /* (EMAC) */ #define AT91C_EMAC_IDLE ((unsigned int) 0x1 << 2) /* (EMAC) */ -/* -------- EMAC_TCR : (EMAC Offset: 0x10) Transmit Control Register -------- */ +/* -------- EMAC_TCR : (EMAC Offset: 0x10) Transmit Control Register ------- */ #define AT91C_EMAC_LEN ((unsigned int) 0x7FF << 0) /* (EMAC) */ #define AT91C_EMAC_NCRC ((unsigned int) 0x1 << 15) /* (EMAC) */ -/* -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Control Register -------- */ +/* -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Control Register ------- */ #define AT91C_EMAC_OVR ((unsigned int) 0x1 << 0) /* (EMAC) */ #define AT91C_EMAC_COL ((unsigned int) 0x1 << 1) /* (EMAC) */ #define AT91C_EMAC_RLE ((unsigned int) 0x1 << 2) /* (EMAC) */ @@ -442,7 +442,7 @@ typedef struct _AT91S_EMAC #define AT91C_EMAC_REC ((unsigned int) 0x1 << 1) /* (EMAC) */ #define AT91C_EMAC_RSR_OVR ((unsigned int) 0x1 << 2) /* (EMAC) */ -/* -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register -------- */ +/* -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register ------- */ #define AT91C_EMAC_DONE ((unsigned int) 0x1 << 0) /* (EMAC) */ #define AT91C_EMAC_RCOM ((unsigned int) 0x1 << 1) /* (EMAC) */ #define AT91C_EMAC_RBNA ((unsigned int) 0x1 << 2) /* (EMAC) */ @@ -456,8 +456,8 @@ typedef struct _AT91S_EMAC #define AT91C_EMAC_ROVR ((unsigned int) 0x1 << 10) /* (EMAC) */ #define AT91C_EMAC_HRESP ((unsigned int) 0x1 << 11) /* (EMAC) */ -/* -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register -------- */ -/* -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register -------- */ +/* -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register ------- */ +/* -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register ------ */ /* -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register -------- */ /* -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register -------- */ #define AT91C_EMAC_DATA ((unsigned int) 0xFFFF << 0) /* (EMAC) */ @@ -471,9 +471,9 @@ typedef struct _AT91S_EMAC #define AT91C_EMAC_HIGH ((unsigned int) 0x1 << 30) /* (EMAC) */ #define AT91C_EMAC_LOW ((unsigned int) 0x1 << 31) /* (EMAC) */ -/******************************************************************************/ -/* SOFTWARE API DEFINITION FOR Serial Parallel Interface */ -/******************************************************************************/ +/*****************************************************************************/ +/* SOFTWARE API DEFINITION FOR Serial Parallel Interface */ +/*****************************************************************************/ typedef struct _AT91S_SPI { AT91_REG SPI_CR; /* Control Register */ @@ -536,7 +536,7 @@ typedef struct _AT91S_SPI #define AT91C_SPI_SPIENS ((unsigned int) 0x1 << 16) /* (SPI) Enable Status */ /* -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- */ -/* -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- */ +/* -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register ------- */ /* -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- */ /* -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- */ #define AT91C_SPI_CPOL ((unsigned int) 0x1 << 0) /* (SPI) Clock Polarity */ @@ -555,9 +555,9 @@ typedef struct _AT91S_SPI #define AT91C_SPI_DLYBS ((unsigned int) 0xFF << 16) /* (SPI) Serial Clock Baud Rate */ #define AT91C_SPI_DLYBCT ((unsigned int) 0xFF << 24) /* (SPI) Delay Between Consecutive Transfers */ -/******************************************************************************/ -/* SOFTWARE API DEFINITION FOR Peripheral Data Controller */ -/******************************************************************************/ +/*****************************************************************************/ +/* SOFTWARE API DEFINITION FOR Peripheral Data Controller */ +/*****************************************************************************/ typedef struct _AT91S_PDC { AT91_REG PDC_RPR; /* Receive Pointer Register */ @@ -692,11 +692,15 @@ typedef struct _AT91S_PDC #define AT91C_PIO_PA7 ((unsigned int) 1 << 7) /* Pin Controlled by PA7 */ #define AT91C_PA7_ETXCK_EREFCK ((unsigned int) AT91C_PIO_PA7) /* Ethernet MAC Transmit Clock/Reference Clock */ +#define AT91C_PIO_PB0 ((unsigned int) 1 << 0) /* Pin Controlled by PB3 */ +#define AT91C_PIO_PB1 ((unsigned int) 1 << 1) /* Pin Controlled by PB3 */ +#define AT91C_PIO_PB2 ((unsigned int) 1 << 2) /* Pin Controlled by PB3 */ #define AT91C_PIO_PB3 ((unsigned int) 1 << 3) /* Pin Controlled by PB3 */ #define AT91C_PIO_PB4 ((unsigned int) 1 << 4) /* Pin Controlled by PB4 */ #define AT91C_PIO_PB5 ((unsigned int) 1 << 5) /* Pin Controlled by PB5 */ #define AT91C_PIO_PB6 ((unsigned int) 1 << 6) /* Pin Controlled by PB6 */ #define AT91C_PIO_PB7 ((unsigned int) 1 << 7) /* Pin Controlled by PB7 */ +#define AT91C_PIO_PB22 ((unsigned int) 1 << 22) /* Pin Controlled by PB22 */ #define AT91C_PIO_PB25 ((unsigned int) 1 << 25) /* Pin Controlled by PB25 */ #define AT91C_PB25_DSR1 ((unsigned int) AT91C_PIO_PB25) /* USART 1 Data Set ready */ #define AT91C_PB25_EF100 ((unsigned int) AT91C_PIO_PB25) /* Ethernet MAC Force 100 Mbits */ @@ -737,19 +741,36 @@ typedef struct _AT91S_PDC #define AT91C_PIOC_CODR ((AT91_REG *) 0xFFFFF834) /* (PIOC) Clear Output Data Register */ #define AT91C_PIOC_PDSR ((AT91_REG *) 0xFFFFF83C) /* (PIOC) Pin Data Status Register */ -#define AT91C_BASE_SPI ((AT91PS_SPI) 0xFFFE0000) /* (SPI) Base Address */ -#define AT91C_BASE_EMAC ((AT91PS_EMAC) 0xFFFBC000) /* (EMAC) Base Address */ -#define AT91C_BASE_PMC ((AT91PS_PMC) 0xFFFFFC00) /* (PMC) Base Address */ -#define AT91C_BASE_TC0 ((AT91PS_TC) 0xFFFA0000) /* (TC0) Base Address */ +#define AT91C_BASE_AIC ((AT91PS_AIC) 0xFFFFF000) /* (AIC) Base Address */ #define AT91C_BASE_DBGU ((AT91PS_DBGU) 0xFFFFF200) /* (DBGU) Base Address */ -#define AT91C_BASE_CKGR ((AT91PS_CKGR) 0xFFFFFC20) /* (CKGR) Base Address */ -#define AT91C_BASE_PIOC ((AT91PS_PIO) 0xFFFFF800) /* (PIOC) Base Address */ -#define AT91C_BASE_PIOB ((AT91PS_PIO) 0xFFFFF600) /* (PIOB) Base Address */ #define AT91C_BASE_PIOA ((AT91PS_PIO) 0xFFFFF400) /* (PIOA) Base Address */ -#define AT91C_EBI_CSA ((AT91_REG *) 0xFFFFFF60) /* (EBI) Chip Select Assignment Register */ -#define AT91C_BASE_SMC2 ((AT91PS_SMC2) 0xFFFFFF70) /* (SMC2) Base Address */ +#define AT91C_BASE_PIOB ((AT91PS_PIO) 0xFFFFF600) /* (PIOB) Base Address */ +#define AT91C_BASE_PIOC ((AT91PS_PIO) 0xFFFFF800) /* (PIOC) Base Address */ +#define AT91C_BASE_PIOD ((AT91PS_PIO) 0xFFFFFA00) /* (PIOC) Base Address */ +#define AT91C_BASE_PMC ((AT91PS_PMC) 0xFFFFFC00) /* (PMC) Base Address */ +#if 0 +#define AT91C_BASE_ST ((AT91PS_ST) 0xFFFFFD00) /* (PMC) Base Address */ +#define AT91C_BASE_RTC ((AT91PS_RTC) 0xFFFFFE00) /* (PMC) Base Address */ +#define AT91C_BASE_MC ((AT91PS_MC) 0xFFFFFF00) /* (PMC) Base Address */ +#endif + +#define AT91C_BASE_TC0 ((AT91PS_TC) 0xFFFA0000) /* (TC0) Base Address */ +#define AT91C_BASE_TC1 ((AT91PS_TC) 0xFFFA4000) /* (TC0) Base Address */ +#if 0 +#define AT91C_BASE_UDP ((AT91PS_UDP) 0xFFFB0000) /* (TC0) Base Address */ +#define AT91C_BASE_MCI ((AT91PS_MCI) 0xFFFB4000) /* (TC0) Base Address */ +#define AT91C_BASE_TWI ((AT91PS_TWI) 0xFFFB8000) /* (TC0) Base Address */ +#endif +#define AT91C_BASE_EMAC ((AT91PS_EMAC) 0xFFFBC000) /* (EMAC) Base Address */ #define AT91C_BASE_US0 ((AT91PS_USART) 0xFFFC0000) /* (US0) Base Address */ #define AT91C_BASE_US1 ((AT91PS_USART) 0xFFFC4000) /* (US1) Base Address */ +#define AT91C_BASE_US2 ((AT91PS_USART) 0xFFFC8000) /* (US1) Base Address */ +#define AT91C_BASE_US3 ((AT91PS_USART) 0xFFFCC000) /* (US1) Base Address */ +#define AT91C_BASE_SPI ((AT91PS_SPI) 0xFFFE0000) /* (SPI) Base Address */ + +#define AT91C_BASE_CKGR ((AT91PS_CKGR) 0xFFFFFC20) /* (CKGR) Base Address */ +#define AT91C_EBI_CSA ((AT91_REG *) 0xFFFFFF60) /* (EBI) Chip Select Assignment Register */ +#define AT91C_BASE_SMC2 ((AT91PS_SMC2) 0xFFFFFF70) /* (SMC2) Base Address */ #define AT91C_TCB0_BMR ((AT91_REG *) 0xFFFA00C4) /* (TCB0) TC Block Mode Register */ #define AT91C_TCB0_BCR ((AT91_REG *) 0xFFFA00C0) /* (TCB0) TC Block Control Register */ #define AT91C_PIOC_PDR ((AT91_REG *) 0xFFFFF804) /* (PIOC) PIO Disable Register */ diff --git a/include/asm-arm/mach-types.h b/include/asm-arm/mach-types.h index 7d7888ed8..f6a5b4f16 100644 --- a/include/asm-arm/mach-types.h +++ b/include/asm-arm/mach-types.h @@ -736,7 +736,11 @@ extern unsigned int __machine_arch_type; #define MACH_TYPE_LN2410SBC 725 #define MACH_TYPE_CB3RUFC 726 #define MACH_TYPE_MP2USB 727 +#define MACH_TYPE_AT91SAM9261EK 848 #define MACH_TYPE_PDNB3 1002 +#define MACH_TYPE_AT91SAM9260EK 1099 +#define MACH_TYPE_AT91RM9200DF 1119 +#define MACH_TYPE_AT91SAM9263EK 1202 #ifdef CONFIG_ARCH_EBSA110 # ifdef machine_arch_type @@ -9402,6 +9406,71 @@ extern unsigned int __machine_arch_type; # define machine_is_mp2usb() (0) #endif +#ifdef CONFIG_MACH_AT91SAM9261EK +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AT91SAM9261EK +# endif +# define machine_is_at91sam9261ek() \ + (machine_arch_type == MACH_TYPE_AT91SAM9261EK) +#else +# define machine_is_at91sam9261ek() (0) +#endif + +#ifdef CONFIG_MACH_AT91SAM9260EK +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AT91SAM9260EK +# endif +# define machine_is_at91sam9260ek() \ + (machine_arch_type == MACH_TYPE_AT91SAM9260EK) +#else +# define machine_is_at91sam9260ek() (0) +#endif + +#ifdef CONFIG_MACH_AT91SAM9263EK +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AT91SAM9263EK +# endif +# define machine_is_at91sam9263ek() \ + (machine_arch_type == MACH_TYPE_AT91SAM9263EK) +#else +# define machine_is_at91sam9263ek() (0) +#endif + +#ifdef CONFIG_MACH_AT91RM9200DF +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AT91RM9200DF +# endif +# define machine_is_at91rm9200df() \ + (machine_arch_type == MACH_TYPE_AT91RM9200DF) +#else +# define machine_is_at91rm9200df() (0) +#endif + +#ifdef CONFIG_MACH_AT91SAM9263EK +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AT91SAM9263EK +# endif +# define machine_is_at91sam9263ek() \ + (machine_arch_type == MACH_TYPE_AT91SAM9263EK) +#else +# define machine_is_at91sam9263ek() (0) +#endif + /* * These have not yet been registered */ diff --git a/include/config_cmd_all.h b/include/config_cmd_all.h index 14801b565..3d91e99b9 100644 --- a/include/config_cmd_all.h +++ b/include/config_cmd_all.h @@ -76,5 +76,6 @@ #define CONFIG_CMD_USB /* USB Support */ #define CONFIG_CMD_VFD /* VFD support (TRAB) */ #define CONFIG_CMD_XIMG /* Load part of Multi Image */ +#define CONFIG_CMD_MUX /* AT91 MMC/SPI Mux Support */ #endif /* _CONFIG_CMD_ALL_H */ diff --git a/include/configs/at91rm9200dk.h b/include/configs/at91rm9200dk.h index ecfa21d82..a65c5f342 100644 --- a/include/configs/at91rm9200dk.h +++ b/include/configs/at91rm9200dk.h @@ -163,6 +163,11 @@ #define CONFIG_NET_RETRY_COUNT 20 #define CONFIG_AT91C_USE_RMII +/* AC Characteristics */ +/* DLYBS = tCSS = 250ns min and DLYBCT = tCSH = 250ns */ +#define DATAFLASH_TCSS (0xC << 16) +#define DATAFLASH_TCHS (0x1 << 24) + #define CONFIG_HAS_DATAFLASH 1 #define CFG_SPI_WRITE_TOUT (5*CFG_HZ) #define CFG_MAX_DATAFLASH_BANKS 2 diff --git a/include/dataflash.h b/include/dataflash.h index 650454e7e..c597e69f1 100644 --- a/include/dataflash.h +++ b/include/dataflash.h @@ -38,13 +38,47 @@ #include "config.h" /*number of protected area*/ -#define NB_DATAFLASH_AREA 4 +#ifdef CONFIG_NEW_PARTITION +# define NB_DATAFLASH_AREA 6 +#else +# define NB_DATAFLASH_AREA 4 +#endif + +#ifdef CFG_NO_FLASH + +/*----------------------------------------------------------------------- + * return codes from flash_write(): + */ +# define ERR_OK 0 +# define ERR_TIMOUT 1 +# define ERR_NOT_ERASED 2 +# define ERR_PROTECTED 4 +# define ERR_INVAL 8 +# define ERR_ALIGN 16 +# define ERR_UNKNOWN_FLASH_VENDOR 32 +# define ERR_UNKNOWN_FLASH_TYPE 64 +# define ERR_PROG_ERROR 128 + +/*----------------------------------------------------------------------- + * Protection Flags for flash_protect(): + */ +# define FLAG_PROTECT_SET 0x01 +# define FLAG_PROTECT_CLEAR 0x02 +# define FLAG_PROTECT_INVALID 0x03 + +/*----------------------------------------------------------------------- + * Set Environment according to label: + */ +# define FLAG_SETENV 0x80 +#endif /* CFG_NO_FLASH */ /*define the area structure*/ typedef struct { unsigned long start; unsigned long end; unsigned char protected; + unsigned char setenv; + unsigned char label[20]; } dataflash_protect_t; typedef unsigned int AT91S_DataFlashStatus; @@ -96,6 +130,7 @@ typedef struct _AT91S_DATAFLASH_INFO { AT91S_DataflashDesc Desc; AT91S_DataflashFeatures Device; /* Pointer on a dataflash features array */ unsigned long logical_address; + unsigned long end_address; unsigned int id; /* device id */ } AT91S_DATAFLASH_INFO, *AT91PS_DATAFLASH_INFO; @@ -106,6 +141,7 @@ typedef struct _AT91S_DATAFLASH_INFO { #define AT45DB321 0x34 #define AT45DB642 0x3c #define AT45DB128 0x10 +#define PAGES_PER_BLOCK 8 #define AT91C_DATAFLASH_TIMEOUT 10000 /* For AT91F_DataFlashWaitReady */ @@ -168,6 +204,7 @@ typedef struct _AT91S_DATAFLASH_INFO { extern int size_dataflash (AT91PS_DataFlash pdataFlash, unsigned long addr, unsigned long size); extern int prot_dataflash (AT91PS_DataFlash pdataFlash, unsigned long addr); +extern int addr2ram(ulong addr); extern int dataflash_real_protect (int flag, unsigned long start_addr, unsigned long end_addr); extern int addr_dataflash (unsigned long addr); extern int read_dataflash (unsigned long addr, unsigned long size, char *result); @@ -175,4 +212,8 @@ extern int write_dataflash (unsigned long addr, unsigned long dest, unsigned lon extern void dataflash_print_info (void); extern void dataflash_perror (int err); +#ifdef CONFIG_NEW_DF_PARTITION +extern int AT91F_DataflashSetEnv (void); #endif +#endif + #endif diff --git a/include/dm9161.h b/include/dm9161.h index f5bfb1960..d5d0e8d3a 100644 --- a/include/dm9161.h +++ b/include/dm9161.h @@ -43,9 +43,9 @@ #define DM9161_COLLISION_TEST (1 << 7) /*--Bit definitions: DM9161_BMSR */ -#define DM9161_100BASE_T4 (1 << 15) +#define DM9161_100BASE_TX (1 << 15) #define DM9161_100BASE_TX_FD (1 << 14) -#define DM9161_100BASE_T4_HD (1 << 13) +#define DM9161_100BASE_TX_HD (1 << 13) #define DM9161_10BASE_T_FD (1 << 12) #define DM9161_10BASE_T_HD (1 << 11) #define DM9161_MF_PREAMB_SUPPR (1 << 6) diff --git a/include/flash.h b/include/flash.h index 43b9c6bdc..b0bf733f1 100644 --- a/include/flash.h +++ b/include/flash.h @@ -119,6 +119,11 @@ extern void flash_read_factory_serial(flash_info_t * info, void * buffer, int of */ #define FLAG_PROTECT_SET 0x01 #define FLAG_PROTECT_CLEAR 0x02 +#define FLAG_PROTECT_INVALID 0x03 +/*----------------------------------------------------------------------- + * Set Environment according to label: + */ +#define FLAG_SETENV 0x80 /*----------------------------------------------------------------------- * Device IDs From dcbfd2e5649f97aa04fbbc6ea2b008aa4486e225 Mon Sep 17 00:00:00 2001 From: Peter Pearse Date: Tue, 14 Aug 2007 10:14:05 +0100 Subject: [PATCH 108/259] Add the files. --- board/at91rm9200dk/led.c | 80 +++++ board/at91rm9200dk/mux.c | 39 +++ cpu/arm920t/at91rm9200/spi.c | 153 ++++++++++ drivers/at45.c | 550 +++++++++++++++++++++++++++++++++++ include/at45.h | 69 +++++ include/led.h | 46 +++ 6 files changed, 937 insertions(+) create mode 100644 board/at91rm9200dk/led.c create mode 100644 board/at91rm9200dk/mux.c create mode 100644 cpu/arm920t/at91rm9200/spi.c create mode 100644 drivers/at45.c create mode 100644 include/at45.h create mode 100644 include/led.h diff --git a/board/at91rm9200dk/led.c b/board/at91rm9200dk/led.c new file mode 100644 index 000000000..051891883 --- /dev/null +++ b/board/at91rm9200dk/led.c @@ -0,0 +1,80 @@ +/* + * (C) Copyright 2006 + * Atmel Nordic AB + * Ulf Samuelsson + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +#define GREEN_LED AT91C_PIO_PB0 +#define YELLOW_LED AT91C_PIO_PB1 +#define RED_LED AT91C_PIO_PB2 + +void green_LED_on(void) +{ + AT91PS_PIO PIOB = AT91C_BASE_PIOB; + PIOB->PIO_CODR = GREEN_LED; +} + +void yellow_LED_on(void) +{ + AT91PS_PIO PIOB = AT91C_BASE_PIOB; + PIOB->PIO_CODR = YELLOW_LED; +} + +void red_LED_on(void) +{ + AT91PS_PIO PIOB = AT91C_BASE_PIOB; + PIOB->PIO_CODR = RED_LED; +} + +void green_LED_off(void) +{ + AT91PS_PIO PIOB = AT91C_BASE_PIOB; + PIOB->PIO_SODR = GREEN_LED; +} + +void yellow_LED_off(void) +{ + AT91PS_PIO PIOB = AT91C_BASE_PIOB; + PIOB->PIO_SODR = YELLOW_LED; +} + +void red_LED_off(void) +{ + AT91PS_PIO PIOB = AT91C_BASE_PIOB; + PIOB->PIO_SODR = RED_LED; +} + + +void LED_init (void) +{ + AT91PS_PIO PIOB = AT91C_BASE_PIOB; + AT91PS_PMC PMC = AT91C_BASE_PMC; + PMC->PMC_PCER = (1 << AT91C_ID_PIOB); /* Enable PIOB clock */ + /* Disable peripherals on LEDs */ + PIOB->PIO_PER = AT91C_PIO_PB2 | AT91C_PIO_PB1 | AT91C_PIO_PB0; + /* Enable pins as outputs */ + PIOB->PIO_OER = AT91C_PIO_PB2 | AT91C_PIO_PB1 | AT91C_PIO_PB0; + /* Turn all LEDs OFF */ + PIOB->PIO_SODR = AT91C_PIO_PB2 | AT91C_PIO_PB1 | AT91C_PIO_PB0; +} diff --git a/board/at91rm9200dk/mux.c b/board/at91rm9200dk/mux.c new file mode 100644 index 000000000..d573923c1 --- /dev/null +++ b/board/at91rm9200dk/mux.c @@ -0,0 +1,39 @@ +#include +#include +#include +#include + +int AT91F_GetMuxStatus(void) { +#ifdef DATAFLASH_MMC_SELECT + AT91C_BASE_PIOB->PIO_PER = DATAFLASH_MMC_SELECT; /* Set in PIO mode */ + AT91C_BASE_PIOB->PIO_OER = DATAFLASH_MMC_SELECT; /* Configure in output */ + + + if(AT91C_BASE_PIOB->PIO_ODSR & DATAFLASH_MMC_SELECT) { + return 1; + } else { + return 0; + } +#endif + return 0; +} + +void AT91F_SelectMMC(void) { +#ifdef DATAFLASH_MMC_SELECT + AT91C_BASE_PIOB->PIO_PER = DATAFLASH_MMC_SELECT; /* Set in PIO mode */ + AT91C_BASE_PIOB->PIO_OER = DATAFLASH_MMC_SELECT; /* Configure in output */ + /* Set Output */ + AT91C_BASE_PIOB->PIO_SODR = DATAFLASH_MMC_SELECT; +#endif +} + +void AT91F_SelectSPI(void) { +#ifdef DATAFLASH_MMC_SELECT + AT91C_BASE_PIOB->PIO_PER = DATAFLASH_MMC_SELECT; /* Set in PIO mode */ + AT91C_BASE_PIOB->PIO_OER = DATAFLASH_MMC_SELECT; /* Configure in output */ + /* Clear Output */ + AT91C_BASE_PIOB->PIO_CODR = DATAFLASH_MMC_SELECT; +#endif +} + + diff --git a/cpu/arm920t/at91rm9200/spi.c b/cpu/arm920t/at91rm9200/spi.c new file mode 100644 index 000000000..7469e5382 --- /dev/null +++ b/cpu/arm920t/at91rm9200/spi.c @@ -0,0 +1,153 @@ +/* Driver for ATMEL DataFlash support + * Author : Hamid Ikdoumi (Atmel) + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#include +#include +#include + +#ifdef CONFIG_HAS_DATAFLASH +#include + +#define AT91C_SPI_CLK 10000000 /* Max Value = 10MHz to be compliant to + the Continuous Array Read function */ + +/* AC Characteristics */ +/* DLYBS = tCSS = 250ns min and DLYBCT = tCSH = 250ns */ +#define DATAFLASH_TCSS (0xC << 16) +#define DATAFLASH_TCHS (0x1 << 24) + +#define AT91C_TIMEOUT_WRDY 200000 +#define AT91C_SPI_PCS0_SERIAL_DATAFLASH 0xE /* Chip Select 0: NPCS0%1110 */ +#define AT91C_SPI_PCS3_DATAFLASH_CARD 0x7 /* Chip Select 3: NPCS3%0111 */ + +/*-------------------------------------------------------------------*/ +/* SPI DataFlash Init */ +/*-------------------------------------------------------------------*/ +void AT91F_SpiInit(void) +{ + /* Configure PIOs */ + AT91C_BASE_PIOA->PIO_ASR = + AT91C_PA3_NPCS0 | AT91C_PA4_NPCS1 | AT91C_PA1_MOSI | + AT91C_PA5_NPCS2 | AT91C_PA6_NPCS3 | AT91C_PA0_MISO | + AT91C_PA2_SPCK; + AT91C_BASE_PIOA->PIO_PDR = + AT91C_PA3_NPCS0 | AT91C_PA4_NPCS1 | AT91C_PA1_MOSI | + AT91C_PA5_NPCS2 | AT91C_PA6_NPCS3 | AT91C_PA0_MISO | + AT91C_PA2_SPCK; + /* Enable CLock */ + AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_SPI; + + /* Reset the SPI */ + AT91C_BASE_SPI->SPI_CR = AT91C_SPI_SWRST; + + /* Configure SPI in Master Mode with No CS selected !!! */ + AT91C_BASE_SPI->SPI_MR = + AT91C_SPI_MSTR | AT91C_SPI_MODFDIS | AT91C_SPI_PCS; + + /* Configure CS0 and CS3 */ + *(AT91C_SPI_CSR + 0) = + AT91C_SPI_CPOL | (AT91C_SPI_DLYBS & DATAFLASH_TCSS) | + (AT91C_SPI_DLYBCT & DATAFLASH_TCHS) | + ((AT91C_MASTER_CLOCK / (2*AT91C_SPI_CLK)) << 8); + + *(AT91C_SPI_CSR + 3) = + AT91C_SPI_CPOL | (AT91C_SPI_DLYBS & DATAFLASH_TCSS) | + (AT91C_SPI_DLYBCT & DATAFLASH_TCHS) | + ((AT91C_MASTER_CLOCK / (2*AT91C_SPI_CLK)) << 8); +} + +void AT91F_SpiEnable(int cs) +{ + switch(cs) { + case 0: /* Configure SPI CS0 for Serial DataFlash AT45DBxx */ + AT91C_BASE_SPI->SPI_MR &= 0xFFF0FFFF; + AT91C_BASE_SPI->SPI_MR |= + ((AT91C_SPI_PCS0_SERIAL_DATAFLASH<<16) & + AT91C_SPI_PCS); + break; + case 3: /* Configure SPI CS3 for Serial DataFlash Card */ + /* Set up PIO SDC_TYPE to switch on DataFlash Card */ + /* and not MMC/SDCard */ + AT91C_BASE_PIOB->PIO_PER = + AT91C_PIO_PB7; /* Set in PIO mode */ + AT91C_BASE_PIOB->PIO_OER = + AT91C_PIO_PB7; /* Configure in output */ + /* Clear Output */ + AT91C_BASE_PIOB->PIO_CODR = AT91C_PIO_PB7; + /* Configure PCS */ + AT91C_BASE_SPI->SPI_MR &= 0xFFF0FFFF; + AT91C_BASE_SPI->SPI_MR |= + ((AT91C_SPI_PCS3_DATAFLASH_CARD<<16) & AT91C_SPI_PCS); + break; + } + + /* SPI_Enable */ + AT91C_BASE_SPI->SPI_CR = AT91C_SPI_SPIEN; } + +/*---------------------------------------------------------------------------*/ +/* \fn AT91F_SpiWrite */ +/* \brief Set the PDC registers for a transfert */ +/*---------------------------------------------------------------------------*/ +unsigned int AT91F_SpiWrite ( AT91PS_DataflashDesc pDesc ) +{ + unsigned int timeout; + + pDesc->state = BUSY; + + AT91C_BASE_SPI->SPI_PTCR = AT91C_PDC_TXTDIS + AT91C_PDC_RXTDIS; + + /* Initialize the Transmit and Receive Pointer */ + AT91C_BASE_SPI->SPI_RPR = (unsigned int)pDesc->rx_cmd_pt ; + AT91C_BASE_SPI->SPI_TPR = (unsigned int)pDesc->tx_cmd_pt ; + + /* Intialize the Transmit and Receive Counters */ + AT91C_BASE_SPI->SPI_RCR = pDesc->rx_cmd_size; + AT91C_BASE_SPI->SPI_TCR = pDesc->tx_cmd_size; + + if ( pDesc->tx_data_size != 0 ) { + /* Initialize the Next Transmit and Next Receive Pointer */ + AT91C_BASE_SPI->SPI_RNPR = (unsigned int)pDesc->rx_data_pt ; + AT91C_BASE_SPI->SPI_TNPR = (unsigned int)pDesc->tx_data_pt ; + + /* Intialize the Next Transmit and Next Receive Counters */ + AT91C_BASE_SPI->SPI_RNCR = pDesc->rx_data_size ; + AT91C_BASE_SPI->SPI_TNCR = pDesc->tx_data_size ; + } + + /* arm simple, non interrupt dependent timer */ + reset_timer_masked(); + timeout = 0; + + AT91C_BASE_SPI->SPI_PTCR = AT91C_PDC_TXTEN + AT91C_PDC_RXTEN; + while(!(AT91C_BASE_SPI->SPI_SR & AT91C_SPI_RXBUFF) && + ((timeout = get_timer_masked() ) < CFG_SPI_WRITE_TOUT)); + AT91C_BASE_SPI->SPI_PTCR = AT91C_PDC_TXTDIS + AT91C_PDC_RXTDIS; + pDesc->state = IDLE; + + if (timeout >= CFG_SPI_WRITE_TOUT){ + printf("Error Timeout\n\r"); + return DATAFLASH_ERROR; + } + + return DATAFLASH_OK; +} + +#endif + diff --git a/drivers/at45.c b/drivers/at45.c new file mode 100644 index 000000000..35c9ecce4 --- /dev/null +++ b/drivers/at45.c @@ -0,0 +1,550 @@ +/* Driver for ATMEL DataFlash support + * Author : Hamid Ikdoumi (Atmel) + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#include +#include + +#ifdef CONFIG_HAS_DATAFLASH +#include + + +#define AT91C_TIMEOUT_WRDY 200000 + + +/*----------------------------------------------------------------------*/ +/* \fn AT91F_DataFlashSendCommand */ +/* \brief Generic function to send a command to the dataflash */ +/*----------------------------------------------------------------------*/ +AT91S_DataFlashStatus AT91F_DataFlashSendCommand( + AT91PS_DataFlash pDataFlash, + unsigned char OpCode, + unsigned int CmdSize, + unsigned int DataflashAddress) +{ + unsigned int adr; + + if ( (pDataFlash->pDataFlashDesc->state) != IDLE) + return DATAFLASH_BUSY; + + /* process the address to obtain page address and byte address */ + adr = ((DataflashAddress / (pDataFlash->pDevice->pages_size)) << + pDataFlash->pDevice->page_offset) + (DataflashAddress % + (pDataFlash->pDevice->pages_size)); + + /* fill the command buffer */ + pDataFlash->pDataFlashDesc->command[0] = OpCode; + if (pDataFlash->pDevice->pages_number >= 16384) { + pDataFlash->pDataFlashDesc->command[1] = + (unsigned char)((adr & 0x0F000000) >> 24); + pDataFlash->pDataFlashDesc->command[2] = + (unsigned char)((adr & 0x00FF0000) >> 16); + pDataFlash->pDataFlashDesc->command[3] = + (unsigned char)((adr & 0x0000FF00) >> 8); + pDataFlash->pDataFlashDesc->command[4] = + (unsigned char)(adr & 0x000000FF); + } else { + pDataFlash->pDataFlashDesc->command[1] = + (unsigned char)((adr & 0x00FF0000) >> 16); + pDataFlash->pDataFlashDesc->command[2] = + (unsigned char)((adr & 0x0000FF00) >> 8); + pDataFlash->pDataFlashDesc->command[3] = + (unsigned char)(adr & 0x000000FF); + pDataFlash->pDataFlashDesc->command[4] = 0; + } + pDataFlash->pDataFlashDesc->command[5] = 0; + pDataFlash->pDataFlashDesc->command[6] = 0; + pDataFlash->pDataFlashDesc->command[7] = 0; + + /* Initialize the SpiData structure for the spi write fuction */ + pDataFlash->pDataFlashDesc->tx_cmd_pt = + pDataFlash->pDataFlashDesc->command; + pDataFlash->pDataFlashDesc->tx_cmd_size = CmdSize; + pDataFlash->pDataFlashDesc->rx_cmd_pt = + pDataFlash->pDataFlashDesc->command; + pDataFlash->pDataFlashDesc->rx_cmd_size = CmdSize; + + /* send the command and read the data */ + return AT91F_SpiWrite (pDataFlash->pDataFlashDesc); } + + +/*----------------------------------------------------------------------*/ +/* \fn AT91F_DataFlashGetStatus */ +/* \brief Read the status register of the dataflash */ +/*----------------------------------------------------------------------*/ +AT91S_DataFlashStatus AT91F_DataFlashGetStatus(AT91PS_DataflashDesc pDesc) +{ + AT91S_DataFlashStatus status; + + /* if a transfert is in progress ==> return 0 */ + if( (pDesc->state) != IDLE) + return DATAFLASH_BUSY; + + /* first send the read status command (D7H) */ + pDesc->command[0] = DB_STATUS; + pDesc->command[1] = 0; + + pDesc->DataFlash_state = GET_STATUS; + pDesc->tx_data_size = 0; /* Transmit the command */ + /* and receive response */ + pDesc->tx_cmd_pt = pDesc->command; + pDesc->rx_cmd_pt = pDesc->command; + pDesc->rx_cmd_size = 2; + pDesc->tx_cmd_size = 2; + status = AT91F_SpiWrite (pDesc); + + pDesc->DataFlash_state = *( (unsigned char *) (pDesc->rx_cmd_pt) +1); + + return status; +} + + +/*----------------------------------------------------------------------*/ +/* \fn AT91F_DataFlashWaitReady */ +/* \brief wait for dataflash ready (bit7 of the status register == 1) */ +/*----------------------------------------------------------------------*/ +AT91S_DataFlashStatus AT91F_DataFlashWaitReady(AT91PS_DataflashDesc +pDataFlashDesc, unsigned int timeout) +{ + pDataFlashDesc->DataFlash_state = IDLE; + + do { + AT91F_DataFlashGetStatus(pDataFlashDesc); + timeout--; + } while( ((pDataFlashDesc->DataFlash_state & 0x80) != 0x80) && + (timeout > 0) ); + + if((pDataFlashDesc->DataFlash_state & 0x80) != 0x80) + return DATAFLASH_ERROR; + + return DATAFLASH_OK; +} + + +/*--------------------------------------------------------------------------*/ +/* Function Name : AT91F_DataFlashContinuousRead */ +/* Object : Continuous stream Read */ +/* Input Parameters : DataFlash Service */ +/* : = dataflash address */ +/* : <*dataBuffer> = data buffer pointer */ +/* : = data buffer size */ +/* Return value : State of the dataflash */ +/*--------------------------------------------------------------------------*/ +AT91S_DataFlashStatus AT91F_DataFlashContinuousRead ( + AT91PS_DataFlash pDataFlash, + int src, + unsigned char *dataBuffer, + int sizeToRead ) +{ + AT91S_DataFlashStatus status; + /* Test the size to read in the device */ + if ( (src + sizeToRead) > + (pDataFlash->pDevice->pages_size * + (pDataFlash->pDevice->pages_number))) + return DATAFLASH_MEMORY_OVERFLOW; + + pDataFlash->pDataFlashDesc->rx_data_pt = dataBuffer; + pDataFlash->pDataFlashDesc->rx_data_size = sizeToRead; + pDataFlash->pDataFlashDesc->tx_data_pt = dataBuffer; + pDataFlash->pDataFlashDesc->tx_data_size = sizeToRead; + + status = AT91F_DataFlashSendCommand + (pDataFlash, DB_CONTINUOUS_ARRAY_READ, 8, src); + /* Send the command to the dataflash */ + return(status); +} + + +/*---------------------------------------------------------------------------*/ +/* Function Name : AT91F_DataFlashPagePgmBuf */ +/* Object : Main memory page program thru buffer 1 or buffer 2 */ +/* Input Parameters : DataFlash Service */ +/* : <*src> = Source buffer */ +/* : = dataflash destination address */ +/* : = data buffer size */ +/* Return value : State of the dataflash */ +/*---------------------------------------------------------------------------*/ +AT91S_DataFlashStatus AT91F_DataFlashPagePgmBuf( + AT91PS_DataFlash pDataFlash, + unsigned char *src, + unsigned int dest, + unsigned int SizeToWrite) +{ + int cmdsize; + pDataFlash->pDataFlashDesc->tx_data_pt = src; + pDataFlash->pDataFlashDesc->tx_data_size = SizeToWrite; + pDataFlash->pDataFlashDesc->rx_data_pt = src; + pDataFlash->pDataFlashDesc->rx_data_size = SizeToWrite; + + cmdsize = 4; + /* Send the command to the dataflash */ + if (pDataFlash->pDevice->pages_number >= 16384) + cmdsize = 5; + return(AT91F_DataFlashSendCommand (pDataFlash, DB_PAGE_PGM_BUF1, +cmdsize, dest)); } + + +/*---------------------------------------------------------------------------*/ +/* Function Name : AT91F_MainMemoryToBufferTransfert */ +/* Object : Read a page in the SRAM Buffer 1 or 2 */ +/* Input Parameters : DataFlash Service */ +/* : Page concerned */ +/* : */ +/* Return value : State of the dataflash */ +/*---------------------------------------------------------------------------*/ +AT91S_DataFlashStatus AT91F_MainMemoryToBufferTransfert( + AT91PS_DataFlash pDataFlash, + unsigned char BufferCommand, + unsigned int page) +{ + int cmdsize; + /* Test if the buffer command is legal */ + if ((BufferCommand != DB_PAGE_2_BUF1_TRF) + && (BufferCommand != DB_PAGE_2_BUF2_TRF)) + return DATAFLASH_BAD_COMMAND; + + /* no data to transmit or receive */ + pDataFlash->pDataFlashDesc->tx_data_size = 0; + cmdsize = 4; + if (pDataFlash->pDevice->pages_number >= 16384) + cmdsize = 5; + return(AT91F_DataFlashSendCommand (pDataFlash, BufferCommand, cmdsize, +page*pDataFlash->pDevice->pages_size)); +} + + +/*-------------------------------------------------------------------------- */ +/* Function Name : AT91F_DataFlashWriteBuffer */ +/* Object : Write data to the internal sram buffer 1 or 2 */ +/* Input Parameters : DataFlash Service */ +/* : = command to write buffer1 or 2 */ +/* : <*dataBuffer> = data buffer to write */ +/* : = address in the internal buffer */ +/* : = data buffer size */ +/* Return value : State of the dataflash */ +/*---------------------------------------------------------------------------*/ +AT91S_DataFlashStatus AT91F_DataFlashWriteBuffer ( + AT91PS_DataFlash pDataFlash, + unsigned char BufferCommand, + unsigned char *dataBuffer, + unsigned int bufferAddress, + int SizeToWrite ) +{ + int cmdsize; + /* Test if the buffer command is legal */ + if ((BufferCommand != DB_BUF1_WRITE) + && (BufferCommand != DB_BUF2_WRITE)) + return DATAFLASH_BAD_COMMAND; + + /* buffer address must be lower than page size */ + if (bufferAddress > pDataFlash->pDevice->pages_size) + return DATAFLASH_BAD_ADDRESS; + + if ( (pDataFlash->pDataFlashDesc->state) != IDLE) + return DATAFLASH_BUSY; + + /* Send first Write Command */ + pDataFlash->pDataFlashDesc->command[0] = BufferCommand; + pDataFlash->pDataFlashDesc->command[1] = 0; + if (pDataFlash->pDevice->pages_number >= 16384) { + pDataFlash->pDataFlashDesc->command[2] = 0; + pDataFlash->pDataFlashDesc->command[3] = + (unsigned char)(((unsigned int)(bufferAddress & + pDataFlash->pDevice->byte_mask)) >> 8); + pDataFlash->pDataFlashDesc->command[4] = + (unsigned char)((unsigned int)bufferAddress & 0x00FF); + cmdsize = 5; + } else { + pDataFlash->pDataFlashDesc->command[2] = + (unsigned char)(((unsigned int)(bufferAddress & + pDataFlash->pDevice->byte_mask)) >> 8); + pDataFlash->pDataFlashDesc->command[3] = + (unsigned char)((unsigned int)bufferAddress & 0x00FF); + pDataFlash->pDataFlashDesc->command[4] = 0; + cmdsize = 4; + } + + pDataFlash->pDataFlashDesc->tx_cmd_pt = + pDataFlash->pDataFlashDesc->command; + pDataFlash->pDataFlashDesc->tx_cmd_size = cmdsize; + pDataFlash->pDataFlashDesc->rx_cmd_pt = + pDataFlash->pDataFlashDesc->command; + pDataFlash->pDataFlashDesc->rx_cmd_size = cmdsize; + + pDataFlash->pDataFlashDesc->rx_data_pt = dataBuffer; + pDataFlash->pDataFlashDesc->tx_data_pt = dataBuffer; + pDataFlash->pDataFlashDesc->rx_data_size = SizeToWrite; + pDataFlash->pDataFlashDesc->tx_data_size = SizeToWrite; + + return AT91F_SpiWrite(pDataFlash->pDataFlashDesc); +} + +/*---------------------------------------------------------------------------*/ +/* Function Name : AT91F_PageErase */ +/* Object : Erase a page */ +/* Input Parameters : DataFlash Service */ +/* : Page concerned */ +/* : */ +/* Return value : State of the dataflash */ +/*---------------------------------------------------------------------------*/ +AT91S_DataFlashStatus AT91F_PageErase( + AT91PS_DataFlash pDataFlash, + unsigned int page) +{ + int cmdsize; + /* Test if the buffer command is legal */ + /* no data to transmit or receive */ + pDataFlash->pDataFlashDesc->tx_data_size = 0; + + cmdsize = 4; + if (pDataFlash->pDevice->pages_number >= 16384) + cmdsize = 5; + return(AT91F_DataFlashSendCommand (pDataFlash, DB_PAGE_ERASE, cmdsize, +page*pDataFlash->pDevice->pages_size)); +} + + +/*---------------------------------------------------------------------------*/ +/* Function Name : AT91F_BlockErase */ +/* Object : Erase a Block */ +/* Input Parameters : DataFlash Service */ +/* : Page concerned */ +/* : */ +/* Return value : State of the dataflash */ +/*---------------------------------------------------------------------------*/ +AT91S_DataFlashStatus AT91F_BlockErase( + AT91PS_DataFlash pDataFlash, + unsigned int block) +{ + int cmdsize; + /* Test if the buffer command is legal */ + /* no data to transmit or receive */ + pDataFlash->pDataFlashDesc->tx_data_size = 0; + cmdsize = 4; + if (pDataFlash->pDevice->pages_number >= 16384) + cmdsize = 5; + return(AT91F_DataFlashSendCommand (pDataFlash, DB_BLOCK_ERASE,cmdsize, +block*8*pDataFlash->pDevice->pages_size)); +} + +/*---------------------------------------------------------------------------*/ +/* Function Name : AT91F_WriteBufferToMain */ +/* Object : Write buffer to the main memory */ +/* Input Parameters : DataFlash Service */ +/* : = command to send to buffer1 or buffer2 */ +/* : = main memory address */ +/* Return value : State of the dataflash */ +/*---------------------------------------------------------------------------*/ +AT91S_DataFlashStatus AT91F_WriteBufferToMain ( + AT91PS_DataFlash pDataFlash, + unsigned char BufferCommand, + unsigned int dest ) +{ + int cmdsize; + /* Test if the buffer command is correct */ + if ((BufferCommand != DB_BUF1_PAGE_PGM) && + (BufferCommand != DB_BUF1_PAGE_ERASE_PGM) && + (BufferCommand != DB_BUF2_PAGE_PGM) && + (BufferCommand != DB_BUF2_PAGE_ERASE_PGM) ) + return DATAFLASH_BAD_COMMAND; + + /* no data to transmit or receive */ + pDataFlash->pDataFlashDesc->tx_data_size = 0; + + cmdsize = 4; + if (pDataFlash->pDevice->pages_number >= 16384) + cmdsize = 5; + /* Send the command to the dataflash */ + return(AT91F_DataFlashSendCommand (pDataFlash, BufferCommand, cmdsize, + dest)); } + + +/*---------------------------------------------------------------------------*/ +/* Function Name : AT91F_PartialPageWrite */ +/* Object : Erase partielly a page */ +/* Input Parameters : = page number */ +/* : = adr to begin the fading */ +/* : = Number of bytes to erase */ +/*---------------------------------------------------------------------------*/ +AT91S_DataFlashStatus AT91F_PartialPageWrite ( + AT91PS_DataFlash pDataFlash, + unsigned char *src, + unsigned int dest, + unsigned int size) +{ + unsigned int page; + unsigned int AdrInPage; + + page = dest / (pDataFlash->pDevice->pages_size); + AdrInPage = dest % (pDataFlash->pDevice->pages_size); + + /* Read the contents of the page in the Sram Buffer */ + AT91F_MainMemoryToBufferTransfert(pDataFlash, + DB_PAGE_2_BUF1_TRF, page); + AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, + AT91C_TIMEOUT_WRDY); + /*Update the SRAM buffer */ + AT91F_DataFlashWriteBuffer(pDataFlash, DB_BUF1_WRITE, src, + AdrInPage, size); + + AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, + AT91C_TIMEOUT_WRDY); + + /* Erase page if a 128 Mbits device */ + if (pDataFlash->pDevice->pages_number >= 16384) { + AT91F_PageErase(pDataFlash, page); + /* Rewrite the modified Sram Buffer in the main memory */ + AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, + AT91C_TIMEOUT_WRDY); + } + + /* Rewrite the modified Sram Buffer in the main memory */ + return(AT91F_WriteBufferToMain(pDataFlash, DB_BUF1_PAGE_ERASE_PGM, + (page*pDataFlash->pDevice->pages_size))); +} + +/*---------------------------------------------------------------------------*/ +/* Function Name : AT91F_DataFlashWrite */ +/* Object : */ +/* Input Parameters : <*src> = Source buffer */ +/* : = dataflash adress */ +/* : = data buffer size */ +/*---------------------------------------------------------------------------*/ +AT91S_DataFlashStatus AT91F_DataFlashWrite( + AT91PS_DataFlash pDataFlash, + unsigned char *src, + int dest, + int size ) +{ + unsigned int length; + unsigned int page; + unsigned int status; + + AT91F_SpiEnable(pDataFlash->pDevice->cs); + + if ( (dest + size) > (pDataFlash->pDevice->pages_size * + (pDataFlash->pDevice->pages_number))) + return DATAFLASH_MEMORY_OVERFLOW; + + /* If destination does not fit a page start address */ + if ((dest % ((unsigned int)(pDataFlash->pDevice->pages_size))) != 0 ) + { + length = pDataFlash->pDevice->pages_size - + (dest % + ((unsigned int) + (pDataFlash->pDevice->pages_size))); + + if (size < length) + length = size; + + if(!AT91F_PartialPageWrite(pDataFlash,src, dest, length)) + return DATAFLASH_ERROR; + + AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, + AT91C_TIMEOUT_WRDY); + + /* Update size, source and destination pointers */ + size -= length; + dest += length; + src += length; + } + + while (( size - pDataFlash->pDevice->pages_size ) >= 0 ) { + /* program dataflash page */ + page = (unsigned int)dest / (pDataFlash->pDevice->pages_size); + + status = AT91F_DataFlashWriteBuffer(pDataFlash, + DB_BUF1_WRITE, src, 0, + pDataFlash->pDevice->pages_size); + AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, + AT91C_TIMEOUT_WRDY); + + status = AT91F_PageErase(pDataFlash, page); + AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, + AT91C_TIMEOUT_WRDY); + if (!status) + return DATAFLASH_ERROR; + + status = AT91F_WriteBufferToMain (pDataFlash, + DB_BUF1_PAGE_PGM, dest); + if(!status) + return DATAFLASH_ERROR; + + AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, + AT91C_TIMEOUT_WRDY); + + /* Update size, source and destination pointers */ + size -= pDataFlash->pDevice->pages_size; + dest += pDataFlash->pDevice->pages_size; + src += pDataFlash->pDevice->pages_size; + } + + /* If still some bytes to read */ + if ( size > 0 ) { + /* program dataflash page */ + if(!AT91F_PartialPageWrite(pDataFlash, src, dest, size) ) + return DATAFLASH_ERROR; + + AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, + AT91C_TIMEOUT_WRDY); + } + return DATAFLASH_OK; +} + + +/*---------------------------------------------------------------------------*/ +/* Function Name : AT91F_DataFlashRead */ +/* Object : Read a block in dataflash */ +/* Input Parameters : */ +/* Return value : */ +/*---------------------------------------------------------------------------*/ +int AT91F_DataFlashRead( + AT91PS_DataFlash pDataFlash, + unsigned long addr, + unsigned long size, + char *buffer) +{ + unsigned long SizeToRead; + + AT91F_SpiEnable(pDataFlash->pDevice->cs); + + if(AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, + AT91C_TIMEOUT_WRDY) != DATAFLASH_OK) + return -1; + + while (size) { + SizeToRead = (size < 0x8000)? size:0x8000; + + if (AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, + AT91C_TIMEOUT_WRDY) != DATAFLASH_OK) + return -1; + + if (AT91F_DataFlashContinuousRead (pDataFlash, addr, + (uchar *) buffer, SizeToRead) != DATAFLASH_OK) + return -1; + + size -= SizeToRead; + addr += SizeToRead; + buffer += SizeToRead; + } + + return DATAFLASH_OK; +} + + diff --git a/include/at45.h b/include/at45.h new file mode 100644 index 000000000..1f71a3b4e --- /dev/null +++ b/include/at45.h @@ -0,0 +1,69 @@ + +#ifndef _AT45_H_ +#define _AT45_H_ +#ifdef DATAFLASH_MMC_SELECT +extern void AT91F_SelectMMC(void); +extern void AT91F_SelectSPI(void); +extern int AT91F_GetMuxStatus(void); +#endif +extern void AT91F_SpiInit(void); +extern void AT91F_SpiEnable(int cs); +extern unsigned int AT91F_SpiWrite ( AT91PS_DataflashDesc pDesc ); +extern AT91S_DataFlashStatus AT91F_DataFlashSendCommand( + AT91PS_DataFlash pDataFlash, + unsigned char OpCode, + unsigned int CmdSize, + unsigned int DataflashAddress); +extern AT91S_DataFlashStatus AT91F_DataFlashGetStatus ( + AT91PS_DataflashDesc pDesc); +extern AT91S_DataFlashStatus AT91F_DataFlashWaitReady ( + AT91PS_DataflashDesc pDataFlashDesc, + unsigned int timeout); +extern AT91S_DataFlashStatus AT91F_DataFlashContinuousRead ( + AT91PS_DataFlash pDataFlash, + int src, + unsigned char *dataBuffer, + int sizeToRead ); +extern AT91S_DataFlashStatus AT91F_DataFlashPagePgmBuf( + AT91PS_DataFlash pDataFlash, + unsigned char *src, + unsigned int dest, + unsigned int SizeToWrite); +extern AT91S_DataFlashStatus AT91F_MainMemoryToBufferTransfert( + AT91PS_DataFlash pDataFlash, + unsigned char BufferCommand, + unsigned int page); +extern AT91S_DataFlashStatus AT91F_DataFlashWriteBuffer ( + AT91PS_DataFlash pDataFlash, + unsigned char BufferCommand, + unsigned char *dataBuffer, + unsigned int bufferAddress, + int SizeToWrite ); +extern AT91S_DataFlashStatus AT91F_PageErase( + AT91PS_DataFlash pDataFlash, + unsigned int page); +extern AT91S_DataFlashStatus AT91F_BlockErase( + AT91PS_DataFlash pDataFlash, + unsigned int block); +extern AT91S_DataFlashStatus AT91F_WriteBufferToMain ( + AT91PS_DataFlash pDataFlash, + unsigned char BufferCommand, + unsigned int dest ); +extern AT91S_DataFlashStatus AT91F_PartialPageWrite ( + AT91PS_DataFlash pDataFlash, + unsigned char *src, + unsigned int dest, + unsigned int size); +extern AT91S_DataFlashStatus AT91F_DataFlashWrite( + AT91PS_DataFlash pDataFlash, + unsigned char *src, + int dest, + int size ); +extern int AT91F_DataFlashRead( + AT91PS_DataFlash pDataFlash, + unsigned long addr, + unsigned long size, + char *buffer); +extern int AT91F_DataflashProbe(int cs, AT91PS_DataflashDesc pDesc); + +#endif diff --git a/include/led.h b/include/led.h new file mode 100644 index 000000000..a261f1bf2 --- /dev/null +++ b/include/led.h @@ -0,0 +1,46 @@ +/* + * (C) Copyright 2006 + * Atmel Nordic AB + * Ulf Samuelsson + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + + #ifndef __LED_H +#define __LED_H + +#ifndef __ASSEMBLY__ +extern void LED_init (void); +extern void red_LED_on(void); +extern void red_LED_off(void); +extern void green_LED_on(void); +extern void green_LED_off(void); +extern void yellow_LED_on(void); +extern void yellow_LED_off(void); +#else + .extern LED_init + .extern red_LED_on + .extern red_LED_off + .extern yellow_LED_on + .extern yellow_LED_off + .extern green_LED_on + .extern green_LED_off +#endif +#endif + From 3454cece2db57cb9eb7087995f7e73066a163f71 Mon Sep 17 00:00:00 2001 From: Peter Pearse Date: Tue, 14 Aug 2007 10:21:06 +0100 Subject: [PATCH 109/259] Delete the merged files. --- board/at91rm9200dk/at45.c | 621 -------------------------------------- board/cmc_pu2/at45.c | 621 -------------------------------------- 2 files changed, 1242 deletions(-) delete mode 100644 board/at91rm9200dk/at45.c delete mode 100644 board/cmc_pu2/at45.c diff --git a/board/at91rm9200dk/at45.c b/board/at91rm9200dk/at45.c deleted file mode 100644 index f886fe482..000000000 --- a/board/at91rm9200dk/at45.c +++ /dev/null @@ -1,621 +0,0 @@ -/* Driver for ATMEL DataFlash support - * Author : Hamid Ikdoumi (Atmel) - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - */ - -#include -#include -#include - -#ifdef CONFIG_HAS_DATAFLASH -#include - -#define AT91C_SPI_CLK 10000000 /* Max Value = 10MHz to be compliant to -the Continuous Array Read function */ - -/* AC Characteristics */ -/* DLYBS = tCSS = 250ns min and DLYBCT = tCSH = 250ns */ -#define DATAFLASH_TCSS (0xC << 16) -#define DATAFLASH_TCHS (0x1 << 24) - -#define AT91C_TIMEOUT_WRDY 200000 -#define AT91C_SPI_PCS0_SERIAL_DATAFLASH 0xE /* Chip Select 0 : NPCS0 %1110 */ -#define AT91C_SPI_PCS3_DATAFLASH_CARD 0x7 /* Chip Select 3 : NPCS3 %0111 */ - -void AT91F_SpiInit(void) { - -/*-------------------------------------------------------------------*/ -/* SPI DataFlash Init */ -/*-------------------------------------------------------------------*/ - /* Configure PIOs */ - AT91C_BASE_PIOA->PIO_ASR = AT91C_PA3_NPCS0 | AT91C_PA4_NPCS1 | AT91C_PA1_MOSI | AT91C_PA5_NPCS2 | - AT91C_PA6_NPCS3 | AT91C_PA0_MISO | AT91C_PA2_SPCK; - AT91C_BASE_PIOA->PIO_PDR = AT91C_PA3_NPCS0 | AT91C_PA4_NPCS1 | AT91C_PA1_MOSI | AT91C_PA5_NPCS2 | - AT91C_PA6_NPCS3 | AT91C_PA0_MISO | AT91C_PA2_SPCK; - /* Enable CLock */ - AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_SPI; - - /* Reset the SPI */ - AT91C_BASE_SPI->SPI_CR = AT91C_SPI_SWRST; - - /* Configure SPI in Master Mode with No CS selected !!! */ - AT91C_BASE_SPI->SPI_MR = AT91C_SPI_MSTR | AT91C_SPI_MODFDIS | AT91C_SPI_PCS; - - /* Configure CS0 and CS3 */ - *(AT91C_SPI_CSR + 0) = AT91C_SPI_CPOL | (AT91C_SPI_DLYBS & DATAFLASH_TCSS) | (AT91C_SPI_DLYBCT & - DATAFLASH_TCHS) | ((AT91C_MASTER_CLOCK / (2*AT91C_SPI_CLK)) << 8); - - *(AT91C_SPI_CSR + 3) = AT91C_SPI_CPOL | (AT91C_SPI_DLYBS & DATAFLASH_TCSS) | (AT91C_SPI_DLYBCT & - DATAFLASH_TCHS) | ((AT91C_MASTER_CLOCK / (2*AT91C_SPI_CLK)) << 8); - -} - -void AT91F_SpiEnable(int cs) { - switch(cs) { - case 0: /* Configure SPI CS0 for Serial DataFlash AT45DBxx */ - AT91C_BASE_SPI->SPI_MR &= 0xFFF0FFFF; - AT91C_BASE_SPI->SPI_MR |= ((AT91C_SPI_PCS0_SERIAL_DATAFLASH<<16) & AT91C_SPI_PCS); - break; - case 3: /* Configure SPI CS3 for Serial DataFlash Card */ - /* Set up PIO SDC_TYPE to switch on DataFlash Card and not MMC/SDCard */ - AT91C_BASE_PIOB->PIO_PER = AT91C_PIO_PB7; /* Set in PIO mode */ - AT91C_BASE_PIOB->PIO_OER = AT91C_PIO_PB7; /* Configure in output */ - /* Clear Output */ - AT91C_BASE_PIOB->PIO_CODR = AT91C_PIO_PB7; - /* Configure PCS */ - AT91C_BASE_SPI->SPI_MR &= 0xFFF0FFFF; - AT91C_BASE_SPI->SPI_MR |= ((AT91C_SPI_PCS3_DATAFLASH_CARD<<16) & AT91C_SPI_PCS); - break; - } - - /* SPI_Enable */ - AT91C_BASE_SPI->SPI_CR = AT91C_SPI_SPIEN; -} - -/*----------------------------------------------------------------------------*/ -/* \fn AT91F_SpiWrite */ -/* \brief Set the PDC registers for a transfert */ -/*----------------------------------------------------------------------------*/ -unsigned int AT91F_SpiWrite ( AT91PS_DataflashDesc pDesc ) -{ - unsigned int timeout; - - pDesc->state = BUSY; - - AT91C_BASE_SPI->SPI_PTCR = AT91C_PDC_TXTDIS + AT91C_PDC_RXTDIS; - - /* Initialize the Transmit and Receive Pointer */ - AT91C_BASE_SPI->SPI_RPR = (unsigned int)pDesc->rx_cmd_pt ; - AT91C_BASE_SPI->SPI_TPR = (unsigned int)pDesc->tx_cmd_pt ; - - /* Intialize the Transmit and Receive Counters */ - AT91C_BASE_SPI->SPI_RCR = pDesc->rx_cmd_size; - AT91C_BASE_SPI->SPI_TCR = pDesc->tx_cmd_size; - - if ( pDesc->tx_data_size != 0 ) { - /* Initialize the Next Transmit and Next Receive Pointer */ - AT91C_BASE_SPI->SPI_RNPR = (unsigned int)pDesc->rx_data_pt ; - AT91C_BASE_SPI->SPI_TNPR = (unsigned int)pDesc->tx_data_pt ; - - /* Intialize the Next Transmit and Next Receive Counters */ - AT91C_BASE_SPI->SPI_RNCR = pDesc->rx_data_size ; - AT91C_BASE_SPI->SPI_TNCR = pDesc->tx_data_size ; - } - - /* arm simple, non interrupt dependent timer */ - reset_timer_masked(); - timeout = 0; - - AT91C_BASE_SPI->SPI_PTCR = AT91C_PDC_TXTEN + AT91C_PDC_RXTEN; - while(!(AT91C_BASE_SPI->SPI_SR & AT91C_SPI_RXBUFF) && ((timeout = get_timer_masked() ) < CFG_SPI_WRITE_TOUT)); - AT91C_BASE_SPI->SPI_PTCR = AT91C_PDC_TXTDIS + AT91C_PDC_RXTDIS; - pDesc->state = IDLE; - - if (timeout >= CFG_SPI_WRITE_TOUT){ - printf("Error Timeout\n\r"); - return DATAFLASH_ERROR; - } - - return DATAFLASH_OK; -} - - -/*----------------------------------------------------------------------*/ -/* \fn AT91F_DataFlashSendCommand */ -/* \brief Generic function to send a command to the dataflash */ -/*----------------------------------------------------------------------*/ -AT91S_DataFlashStatus AT91F_DataFlashSendCommand( - AT91PS_DataFlash pDataFlash, - unsigned char OpCode, - unsigned int CmdSize, - unsigned int DataflashAddress) -{ - unsigned int adr; - - if ( (pDataFlash->pDataFlashDesc->state) != IDLE) - return DATAFLASH_BUSY; - - /* process the address to obtain page address and byte address */ - adr = ((DataflashAddress / (pDataFlash->pDevice->pages_size)) << pDataFlash->pDevice->page_offset) + (DataflashAddress % (pDataFlash->pDevice->pages_size)); - - /* fill the command buffer */ - pDataFlash->pDataFlashDesc->command[0] = OpCode; - if (pDataFlash->pDevice->pages_number >= 16384) { - pDataFlash->pDataFlashDesc->command[1] = (unsigned char)((adr & 0x0F000000) >> 24); - pDataFlash->pDataFlashDesc->command[2] = (unsigned char)((adr & 0x00FF0000) >> 16); - pDataFlash->pDataFlashDesc->command[3] = (unsigned char)((adr & 0x0000FF00) >> 8); - pDataFlash->pDataFlashDesc->command[4] = (unsigned char)(adr & 0x000000FF); - } else { - pDataFlash->pDataFlashDesc->command[1] = (unsigned char)((adr & 0x00FF0000) >> 16); - pDataFlash->pDataFlashDesc->command[2] = (unsigned char)((adr & 0x0000FF00) >> 8); - pDataFlash->pDataFlashDesc->command[3] = (unsigned char)(adr & 0x000000FF) ; - pDataFlash->pDataFlashDesc->command[4] = 0; - } - pDataFlash->pDataFlashDesc->command[5] = 0; - pDataFlash->pDataFlashDesc->command[6] = 0; - pDataFlash->pDataFlashDesc->command[7] = 0; - - /* Initialize the SpiData structure for the spi write fuction */ - pDataFlash->pDataFlashDesc->tx_cmd_pt = pDataFlash->pDataFlashDesc->command ; - pDataFlash->pDataFlashDesc->tx_cmd_size = CmdSize ; - pDataFlash->pDataFlashDesc->rx_cmd_pt = pDataFlash->pDataFlashDesc->command ; - pDataFlash->pDataFlashDesc->rx_cmd_size = CmdSize ; - - /* send the command and read the data */ - return AT91F_SpiWrite (pDataFlash->pDataFlashDesc); -} - - -/*----------------------------------------------------------------------*/ -/* \fn AT91F_DataFlashGetStatus */ -/* \brief Read the status register of the dataflash */ -/*----------------------------------------------------------------------*/ -AT91S_DataFlashStatus AT91F_DataFlashGetStatus(AT91PS_DataflashDesc pDesc) -{ - AT91S_DataFlashStatus status; - - /* if a transfert is in progress ==> return 0 */ - if( (pDesc->state) != IDLE) - return DATAFLASH_BUSY; - - /* first send the read status command (D7H) */ - pDesc->command[0] = DB_STATUS; - pDesc->command[1] = 0; - - pDesc->DataFlash_state = GET_STATUS; - pDesc->tx_data_size = 0 ; /* Transmit the command and receive response */ - pDesc->tx_cmd_pt = pDesc->command ; - pDesc->rx_cmd_pt = pDesc->command ; - pDesc->rx_cmd_size = 2 ; - pDesc->tx_cmd_size = 2 ; - status = AT91F_SpiWrite (pDesc); - - pDesc->DataFlash_state = *( (unsigned char *) (pDesc->rx_cmd_pt) +1); - - return status; -} - - -/*----------------------------------------------------------------------*/ -/* \fn AT91F_DataFlashWaitReady */ -/* \brief wait for dataflash ready (bit7 of the status register == 1) */ -/*----------------------------------------------------------------------*/ -AT91S_DataFlashStatus AT91F_DataFlashWaitReady(AT91PS_DataflashDesc pDataFlashDesc, unsigned int timeout) -{ - pDataFlashDesc->DataFlash_state = IDLE; - - do { - AT91F_DataFlashGetStatus(pDataFlashDesc); - timeout--; - } while( ((pDataFlashDesc->DataFlash_state & 0x80) != 0x80) && (timeout > 0) ); - - if((pDataFlashDesc->DataFlash_state & 0x80) != 0x80) - return DATAFLASH_ERROR; - - return DATAFLASH_OK; -} - - -/*------------------------------------------------------------------------------*/ -/* Function Name : AT91F_DataFlashContinuousRead */ -/* Object : Continuous stream Read */ -/* Input Parameters : DataFlash Service */ -/* : = dataflash address */ -/* : <*dataBuffer> = data buffer pointer */ -/* : = data buffer size */ -/* Return value : State of the dataflash */ -/*------------------------------------------------------------------------------*/ -AT91S_DataFlashStatus AT91F_DataFlashContinuousRead ( - AT91PS_DataFlash pDataFlash, - int src, - unsigned char *dataBuffer, - int sizeToRead ) -{ - AT91S_DataFlashStatus status; - /* Test the size to read in the device */ - if ( (src + sizeToRead) > (pDataFlash->pDevice->pages_size * (pDataFlash->pDevice->pages_number))) - return DATAFLASH_MEMORY_OVERFLOW; - - pDataFlash->pDataFlashDesc->rx_data_pt = dataBuffer; - pDataFlash->pDataFlashDesc->rx_data_size = sizeToRead; - pDataFlash->pDataFlashDesc->tx_data_pt = dataBuffer; - pDataFlash->pDataFlashDesc->tx_data_size = sizeToRead; - - status = AT91F_DataFlashSendCommand (pDataFlash, DB_CONTINUOUS_ARRAY_READ, 8, src); - /* Send the command to the dataflash */ - return(status); -} - - -/*------------------------------------------------------------------------------*/ -/* Function Name : AT91F_DataFlashPagePgmBuf */ -/* Object : Main memory page program through buffer 1 or buffer 2 */ -/* Input Parameters : DataFlash Service */ -/* : <*src> = Source buffer */ -/* : = dataflash destination address */ -/* : = data buffer size */ -/* Return value : State of the dataflash */ -/*------------------------------------------------------------------------------*/ -AT91S_DataFlashStatus AT91F_DataFlashPagePgmBuf( - AT91PS_DataFlash pDataFlash, - unsigned char *src, - unsigned int dest, - unsigned int SizeToWrite) -{ - int cmdsize; - pDataFlash->pDataFlashDesc->tx_data_pt = src ; - pDataFlash->pDataFlashDesc->tx_data_size = SizeToWrite ; - pDataFlash->pDataFlashDesc->rx_data_pt = src; - pDataFlash->pDataFlashDesc->rx_data_size = SizeToWrite; - - cmdsize = 4; - /* Send the command to the dataflash */ - if (pDataFlash->pDevice->pages_number >= 16384) - cmdsize = 5; - return(AT91F_DataFlashSendCommand (pDataFlash, DB_PAGE_PGM_BUF1, cmdsize, dest)); -} - - -/*------------------------------------------------------------------------------*/ -/* Function Name : AT91F_MainMemoryToBufferTransfert */ -/* Object : Read a page in the SRAM Buffer 1 or 2 */ -/* Input Parameters : DataFlash Service */ -/* : Page concerned */ -/* : */ -/* Return value : State of the dataflash */ -/*------------------------------------------------------------------------------*/ -AT91S_DataFlashStatus AT91F_MainMemoryToBufferTransfert( - AT91PS_DataFlash pDataFlash, - unsigned char BufferCommand, - unsigned int page) -{ - int cmdsize; - /* Test if the buffer command is legal */ - if ((BufferCommand != DB_PAGE_2_BUF1_TRF) && (BufferCommand != DB_PAGE_2_BUF2_TRF)) - return DATAFLASH_BAD_COMMAND; - - /* no data to transmit or receive */ - pDataFlash->pDataFlashDesc->tx_data_size = 0; - cmdsize = 4; - if (pDataFlash->pDevice->pages_number >= 16384) - cmdsize = 5; - return(AT91F_DataFlashSendCommand (pDataFlash, BufferCommand, cmdsize, page*pDataFlash->pDevice->pages_size)); -} - - -/*----------------------------------------------------------------------------- */ -/* Function Name : AT91F_DataFlashWriteBuffer */ -/* Object : Write data to the internal sram buffer 1 or 2 */ -/* Input Parameters : DataFlash Service */ -/* : = command to write buffer1 or buffer2 */ -/* : <*dataBuffer> = data buffer to write */ -/* : = address in the internal buffer */ -/* : = data buffer size */ -/* Return value : State of the dataflash */ -/*------------------------------------------------------------------------------*/ -AT91S_DataFlashStatus AT91F_DataFlashWriteBuffer ( - AT91PS_DataFlash pDataFlash, - unsigned char BufferCommand, - unsigned char *dataBuffer, - unsigned int bufferAddress, - int SizeToWrite ) -{ - int cmdsize; - /* Test if the buffer command is legal */ - if ((BufferCommand != DB_BUF1_WRITE) && (BufferCommand != DB_BUF2_WRITE)) - return DATAFLASH_BAD_COMMAND; - - /* buffer address must be lower than page size */ - if (bufferAddress > pDataFlash->pDevice->pages_size) - return DATAFLASH_BAD_ADDRESS; - - if ( (pDataFlash->pDataFlashDesc->state) != IDLE) - return DATAFLASH_BUSY; - - /* Send first Write Command */ - pDataFlash->pDataFlashDesc->command[0] = BufferCommand; - pDataFlash->pDataFlashDesc->command[1] = 0; - if (pDataFlash->pDevice->pages_number >= 16384) { - pDataFlash->pDataFlashDesc->command[2] = 0; - pDataFlash->pDataFlashDesc->command[3] = (unsigned char)(((unsigned int)(bufferAddress & pDataFlash->pDevice->byte_mask)) >> 8) ; - pDataFlash->pDataFlashDesc->command[4] = (unsigned char)((unsigned int)bufferAddress & 0x00FF) ; - cmdsize = 5; - } else { - pDataFlash->pDataFlashDesc->command[2] = (unsigned char)(((unsigned int)(bufferAddress & pDataFlash->pDevice->byte_mask)) >> 8) ; - pDataFlash->pDataFlashDesc->command[3] = (unsigned char)((unsigned int)bufferAddress & 0x00FF) ; - pDataFlash->pDataFlashDesc->command[4] = 0; - cmdsize = 4; - } - - pDataFlash->pDataFlashDesc->tx_cmd_pt = pDataFlash->pDataFlashDesc->command ; - pDataFlash->pDataFlashDesc->tx_cmd_size = cmdsize ; - pDataFlash->pDataFlashDesc->rx_cmd_pt = pDataFlash->pDataFlashDesc->command ; - pDataFlash->pDataFlashDesc->rx_cmd_size = cmdsize ; - - pDataFlash->pDataFlashDesc->rx_data_pt = dataBuffer ; - pDataFlash->pDataFlashDesc->tx_data_pt = dataBuffer ; - pDataFlash->pDataFlashDesc->rx_data_size = SizeToWrite ; - pDataFlash->pDataFlashDesc->tx_data_size = SizeToWrite ; - - return AT91F_SpiWrite(pDataFlash->pDataFlashDesc); -} - -/*------------------------------------------------------------------------------*/ -/* Function Name : AT91F_PageErase */ -/* Object : Erase a page */ -/* Input Parameters : DataFlash Service */ -/* : Page concerned */ -/* : */ -/* Return value : State of the dataflash */ -/*------------------------------------------------------------------------------*/ -AT91S_DataFlashStatus AT91F_PageErase( - AT91PS_DataFlash pDataFlash, - unsigned int page) -{ - int cmdsize; - /* Test if the buffer command is legal */ - /* no data to transmit or receive */ - pDataFlash->pDataFlashDesc->tx_data_size = 0; - - cmdsize = 4; - if (pDataFlash->pDevice->pages_number >= 16384) - cmdsize = 5; - return(AT91F_DataFlashSendCommand (pDataFlash, DB_PAGE_ERASE, cmdsize, page*pDataFlash->pDevice->pages_size)); -} - - -/*------------------------------------------------------------------------------*/ -/* Function Name : AT91F_BlockErase */ -/* Object : Erase a Block */ -/* Input Parameters : DataFlash Service */ -/* : Page concerned */ -/* : */ -/* Return value : State of the dataflash */ -/*------------------------------------------------------------------------------*/ -AT91S_DataFlashStatus AT91F_BlockErase( - AT91PS_DataFlash pDataFlash, - unsigned int block) -{ - int cmdsize; - /* Test if the buffer command is legal */ - /* no data to transmit or receive */ - pDataFlash->pDataFlashDesc->tx_data_size = 0; - cmdsize = 4; - if (pDataFlash->pDevice->pages_number >= 16384) - cmdsize = 5; - return(AT91F_DataFlashSendCommand (pDataFlash, DB_BLOCK_ERASE,cmdsize, block*8*pDataFlash->pDevice->pages_size)); -} - -/*------------------------------------------------------------------------------*/ -/* Function Name : AT91F_WriteBufferToMain */ -/* Object : Write buffer to the main memory */ -/* Input Parameters : DataFlash Service */ -/* : = command to send to buffer1 or buffer2 */ -/* : = main memory address */ -/* Return value : State of the dataflash */ -/*------------------------------------------------------------------------------*/ -AT91S_DataFlashStatus AT91F_WriteBufferToMain ( - AT91PS_DataFlash pDataFlash, - unsigned char BufferCommand, - unsigned int dest ) -{ - int cmdsize; - /* Test if the buffer command is correct */ - if ((BufferCommand != DB_BUF1_PAGE_PGM) && - (BufferCommand != DB_BUF1_PAGE_ERASE_PGM) && - (BufferCommand != DB_BUF2_PAGE_PGM) && - (BufferCommand != DB_BUF2_PAGE_ERASE_PGM) ) - return DATAFLASH_BAD_COMMAND; - - /* no data to transmit or receive */ - pDataFlash->pDataFlashDesc->tx_data_size = 0; - - cmdsize = 4; - if (pDataFlash->pDevice->pages_number >= 16384) - cmdsize = 5; - /* Send the command to the dataflash */ - return(AT91F_DataFlashSendCommand (pDataFlash, BufferCommand, cmdsize, dest)); -} - - -/*------------------------------------------------------------------------------*/ -/* Function Name : AT91F_PartialPageWrite */ -/* Object : Erase partielly a page */ -/* Input Parameters : = page number */ -/* : = adr to begin the fading */ -/* : = Number of bytes to erase */ -/*------------------------------------------------------------------------------*/ -AT91S_DataFlashStatus AT91F_PartialPageWrite ( - AT91PS_DataFlash pDataFlash, - unsigned char *src, - unsigned int dest, - unsigned int size) -{ - unsigned int page; - unsigned int AdrInPage; - - page = dest / (pDataFlash->pDevice->pages_size); - AdrInPage = dest % (pDataFlash->pDevice->pages_size); - - /* Read the contents of the page in the Sram Buffer */ - AT91F_MainMemoryToBufferTransfert(pDataFlash, DB_PAGE_2_BUF1_TRF, page); - AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY); - /*Update the SRAM buffer */ - AT91F_DataFlashWriteBuffer(pDataFlash, DB_BUF1_WRITE, src, AdrInPage, size); - - AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY); - - /* Erase page if a 128 Mbits device */ - if (pDataFlash->pDevice->pages_number >= 16384) { - AT91F_PageErase(pDataFlash, page); - /* Rewrite the modified Sram Buffer in the main memory */ - AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY); - } - - /* Rewrite the modified Sram Buffer in the main memory */ - return(AT91F_WriteBufferToMain(pDataFlash, DB_BUF1_PAGE_ERASE_PGM, (page*pDataFlash->pDevice->pages_size))); -} - - -/*------------------------------------------------------------------------------*/ -/* Function Name : AT91F_DataFlashWrite */ -/* Object : */ -/* Input Parameters : <*src> = Source buffer */ -/* : = dataflash adress */ -/* : = data buffer size */ -/*------------------------------------------------------------------------------*/ -AT91S_DataFlashStatus AT91F_DataFlashWrite( - AT91PS_DataFlash pDataFlash, - unsigned char *src, - int dest, - int size ) -{ - unsigned int length; - unsigned int page; - unsigned int status; - - AT91F_SpiEnable(pDataFlash->pDevice->cs); - - if ( (dest + size) > (pDataFlash->pDevice->pages_size * (pDataFlash->pDevice->pages_number))) - return DATAFLASH_MEMORY_OVERFLOW; - - /* If destination does not fit a page start address */ - if ((dest % ((unsigned int)(pDataFlash->pDevice->pages_size))) != 0 ) { - length = pDataFlash->pDevice->pages_size - (dest % ((unsigned int)(pDataFlash->pDevice->pages_size))); - - if (size < length) - length = size; - - if(!AT91F_PartialPageWrite(pDataFlash,src, dest, length)) - return DATAFLASH_ERROR; - - AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY); - - /* Update size, source and destination pointers */ - size -= length; - dest += length; - src += length; - } - - while (( size - pDataFlash->pDevice->pages_size ) >= 0 ) { - /* program dataflash page */ - page = (unsigned int)dest / (pDataFlash->pDevice->pages_size); - - status = AT91F_DataFlashWriteBuffer(pDataFlash, DB_BUF1_WRITE, src, 0, pDataFlash->pDevice->pages_size); - AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY); - - status = AT91F_PageErase(pDataFlash, page); - AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY); - if (!status) - return DATAFLASH_ERROR; - - status = AT91F_WriteBufferToMain (pDataFlash, DB_BUF1_PAGE_PGM, dest); - if(!status) - return DATAFLASH_ERROR; - - AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY); - - /* Update size, source and destination pointers */ - size -= pDataFlash->pDevice->pages_size ; - dest += pDataFlash->pDevice->pages_size ; - src += pDataFlash->pDevice->pages_size ; - } - - /* If still some bytes to read */ - if ( size > 0 ) { - /* program dataflash page */ - if(!AT91F_PartialPageWrite(pDataFlash, src, dest, size) ) - return DATAFLASH_ERROR; - - AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY); - } - return DATAFLASH_OK; -} - - -/*------------------------------------------------------------------------------*/ -/* Function Name : AT91F_DataFlashRead */ -/* Object : Read a block in dataflash */ -/* Input Parameters : */ -/* Return value : */ -/*------------------------------------------------------------------------------*/ -int AT91F_DataFlashRead( - AT91PS_DataFlash pDataFlash, - unsigned long addr, - unsigned long size, - char *buffer) -{ - unsigned long SizeToRead; - - AT91F_SpiEnable(pDataFlash->pDevice->cs); - - if(AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY) != DATAFLASH_OK) - return -1; - - while (size) { - SizeToRead = (size < 0x8000)? size:0x8000; - - if (AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY) != DATAFLASH_OK) - return -1; - - if (AT91F_DataFlashContinuousRead (pDataFlash, addr, (uchar *)buffer, SizeToRead) != DATAFLASH_OK) - return -1; - - size -= SizeToRead; - addr += SizeToRead; - buffer += SizeToRead; - } - - return DATAFLASH_OK; -} - - -/*------------------------------------------------------------------------------*/ -/* Function Name : AT91F_DataflashProbe */ -/* Object : */ -/* Input Parameters : */ -/* Return value : Dataflash status register */ -/*------------------------------------------------------------------------------*/ -int AT91F_DataflashProbe(int cs, AT91PS_DataflashDesc pDesc) -{ - AT91F_SpiEnable(cs); - AT91F_DataFlashGetStatus(pDesc); - return((pDesc->command[1] == 0xFF)? 0: pDesc->command[1] & 0x3C); -} - -#endif diff --git a/board/cmc_pu2/at45.c b/board/cmc_pu2/at45.c deleted file mode 100644 index 3c0013216..000000000 --- a/board/cmc_pu2/at45.c +++ /dev/null @@ -1,621 +0,0 @@ -/* Driver for ATMEL DataFlash support - * Author : Hamid Ikdoumi (Atmel) - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - */ - -#include -#include -#include - -#ifdef CONFIG_HAS_DATAFLASH -#include - -#define AT91C_SPI_CLK 10000000 /* Max Value = 10MHz to be compliant to -the Continuous Array Read function */ - -/* AC Characteristics */ -/* DLYBS = tCSS = 250ns min and DLYBCT = tCSH = 250ns */ -#define DATAFLASH_TCSS (0xC << 16) -#define DATAFLASH_TCHS (0x1 << 24) - -#define AT91C_TIMEOUT_WRDY 200000 -#define AT91C_SPI_PCS0_SERIAL_DATAFLASH 0xE /* Chip Select 0 : NPCS0 %1110 */ -#define AT91C_SPI_PCS3_DATAFLASH_CARD 0x7 /* Chip Select 3 : NPCS3 %0111 */ - -void AT91F_SpiInit(void) { - -/*-------------------------------------------------------------------*/ -/* SPI DataFlash Init */ -/*-------------------------------------------------------------------*/ - /* Configure PIOs */ - AT91C_BASE_PIOA->PIO_ASR = AT91C_PA3_NPCS0 | AT91C_PA4_NPCS1 | AT91C_PA1_MOSI | AT91C_PA5_NPCS2 | - AT91C_PA6_NPCS3 | AT91C_PA0_MISO | AT91C_PA2_SPCK; - AT91C_BASE_PIOA->PIO_PDR = AT91C_PA3_NPCS0 | AT91C_PA4_NPCS1 | AT91C_PA1_MOSI | AT91C_PA5_NPCS2 | - AT91C_PA6_NPCS3 | AT91C_PA0_MISO | AT91C_PA2_SPCK; - /* Enable CLock */ - AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_SPI; - - /* Reset the SPI */ - AT91C_BASE_SPI->SPI_CR = AT91C_SPI_SWRST; - - /* Configure SPI in Master Mode with No CS selected !!! */ - AT91C_BASE_SPI->SPI_MR = AT91C_SPI_MSTR | AT91C_SPI_MODFDIS | AT91C_SPI_PCS; - - /* Configure CS0 and CS3 */ - *(AT91C_SPI_CSR + 0) = AT91C_SPI_CPOL | (AT91C_SPI_DLYBS & DATAFLASH_TCSS) | (AT91C_SPI_DLYBCT & - DATAFLASH_TCHS) | ((AT91C_MASTER_CLOCK / (2*AT91C_SPI_CLK)) << 8); - - *(AT91C_SPI_CSR + 3) = AT91C_SPI_CPOL | (AT91C_SPI_DLYBS & DATAFLASH_TCSS) | (AT91C_SPI_DLYBCT & - DATAFLASH_TCHS) | ((AT91C_MASTER_CLOCK / (2*AT91C_SPI_CLK)) << 8); - -} - -void AT91F_SpiEnable(int cs) { - switch(cs) { - case 0: /* Configure SPI CS0 for Serial DataFlash AT45DBxx */ - AT91C_BASE_SPI->SPI_MR &= 0xFFF0FFFF; - AT91C_BASE_SPI->SPI_MR |= ((AT91C_SPI_PCS0_SERIAL_DATAFLASH<<16) & AT91C_SPI_PCS); - break; - case 3: /* Configure SPI CS3 for Serial DataFlash Card */ - /* Set up PIO SDC_TYPE to switch on DataFlash Card and not MMC/SDCard */ - AT91C_BASE_PIOB->PIO_PER = AT91C_PIO_PB7; /* Set in PIO mode */ - AT91C_BASE_PIOB->PIO_OER = AT91C_PIO_PB7; /* Configure in output */ - /* Clear Output */ - AT91C_BASE_PIOB->PIO_CODR = AT91C_PIO_PB7; - /* Configure PCS */ - AT91C_BASE_SPI->SPI_MR &= 0xFFF0FFFF; - AT91C_BASE_SPI->SPI_MR |= ((AT91C_SPI_PCS3_DATAFLASH_CARD<<16) & AT91C_SPI_PCS); - break; - } - - /* SPI_Enable */ - AT91C_BASE_SPI->SPI_CR = AT91C_SPI_SPIEN; -} - -/*----------------------------------------------------------------------------*/ -/* \fn AT91F_SpiWrite */ -/* \brief Set the PDC registers for a transfert */ -/*----------------------------------------------------------------------------*/ -unsigned int AT91F_SpiWrite ( AT91PS_DataflashDesc pDesc ) -{ - unsigned int timeout; - - pDesc->state = BUSY; - - AT91C_BASE_SPI->SPI_PTCR = AT91C_PDC_TXTDIS + AT91C_PDC_RXTDIS; - - /* Initialize the Transmit and Receive Pointer */ - AT91C_BASE_SPI->SPI_RPR = (unsigned int)pDesc->rx_cmd_pt ; - AT91C_BASE_SPI->SPI_TPR = (unsigned int)pDesc->tx_cmd_pt ; - - /* Intialize the Transmit and Receive Counters */ - AT91C_BASE_SPI->SPI_RCR = pDesc->rx_cmd_size; - AT91C_BASE_SPI->SPI_TCR = pDesc->tx_cmd_size; - - if ( pDesc->tx_data_size != 0 ) { - /* Initialize the Next Transmit and Next Receive Pointer */ - AT91C_BASE_SPI->SPI_RNPR = (unsigned int)pDesc->rx_data_pt ; - AT91C_BASE_SPI->SPI_TNPR = (unsigned int)pDesc->tx_data_pt ; - - /* Intialize the Next Transmit and Next Receive Counters */ - AT91C_BASE_SPI->SPI_RNCR = pDesc->rx_data_size ; - AT91C_BASE_SPI->SPI_TNCR = pDesc->tx_data_size ; - } - - /* arm simple, non interrupt dependent timer */ - reset_timer_masked(); - timeout = 0; - - AT91C_BASE_SPI->SPI_PTCR = AT91C_PDC_TXTEN + AT91C_PDC_RXTEN; - while(!(AT91C_BASE_SPI->SPI_SR & AT91C_SPI_RXBUFF) && ((timeout = get_timer_masked() ) < CFG_SPI_WRITE_TOUT)); - AT91C_BASE_SPI->SPI_PTCR = AT91C_PDC_TXTDIS + AT91C_PDC_RXTDIS; - pDesc->state = IDLE; - - if (timeout >= CFG_SPI_WRITE_TOUT){ - printf("Error Timeout\n\r"); - return DATAFLASH_ERROR; - } - - return DATAFLASH_OK; -} - - -/*----------------------------------------------------------------------*/ -/* \fn AT91F_DataFlashSendCommand */ -/* \brief Generic function to send a command to the dataflash */ -/*----------------------------------------------------------------------*/ -AT91S_DataFlashStatus AT91F_DataFlashSendCommand( - AT91PS_DataFlash pDataFlash, - unsigned char OpCode, - unsigned int CmdSize, - unsigned int DataflashAddress) -{ - unsigned int adr; - - if ( (pDataFlash->pDataFlashDesc->state) != IDLE) - return DATAFLASH_BUSY; - - /* process the address to obtain page address and byte address */ - adr = ((DataflashAddress / (pDataFlash->pDevice->pages_size)) << pDataFlash->pDevice->page_offset) + (DataflashAddress % (pDataFlash->pDevice->pages_size)); - - /* fill the command buffer */ - pDataFlash->pDataFlashDesc->command[0] = OpCode; - if (pDataFlash->pDevice->pages_number >= 16384) { - pDataFlash->pDataFlashDesc->command[1] = (unsigned char)((adr & 0x0F000000) >> 24); - pDataFlash->pDataFlashDesc->command[2] = (unsigned char)((adr & 0x00FF0000) >> 16); - pDataFlash->pDataFlashDesc->command[3] = (unsigned char)((adr & 0x0000FF00) >> 8); - pDataFlash->pDataFlashDesc->command[4] = (unsigned char)(adr & 0x000000FF); - } else { - pDataFlash->pDataFlashDesc->command[1] = (unsigned char)((adr & 0x00FF0000) >> 16); - pDataFlash->pDataFlashDesc->command[2] = (unsigned char)((adr & 0x0000FF00) >> 8); - pDataFlash->pDataFlashDesc->command[3] = (unsigned char)(adr & 0x000000FF) ; - pDataFlash->pDataFlashDesc->command[4] = 0; - } - pDataFlash->pDataFlashDesc->command[5] = 0; - pDataFlash->pDataFlashDesc->command[6] = 0; - pDataFlash->pDataFlashDesc->command[7] = 0; - - /* Initialize the SpiData structure for the spi write fuction */ - pDataFlash->pDataFlashDesc->tx_cmd_pt = pDataFlash->pDataFlashDesc->command ; - pDataFlash->pDataFlashDesc->tx_cmd_size = CmdSize ; - pDataFlash->pDataFlashDesc->rx_cmd_pt = pDataFlash->pDataFlashDesc->command ; - pDataFlash->pDataFlashDesc->rx_cmd_size = CmdSize ; - - /* send the command and read the data */ - return AT91F_SpiWrite (pDataFlash->pDataFlashDesc); -} - - -/*----------------------------------------------------------------------*/ -/* \fn AT91F_DataFlashGetStatus */ -/* \brief Read the status register of the dataflash */ -/*----------------------------------------------------------------------*/ -AT91S_DataFlashStatus AT91F_DataFlashGetStatus(AT91PS_DataflashDesc pDesc) -{ - AT91S_DataFlashStatus status; - - /* if a transfert is in progress ==> return 0 */ - if( (pDesc->state) != IDLE) - return DATAFLASH_BUSY; - - /* first send the read status command (D7H) */ - pDesc->command[0] = DB_STATUS; - pDesc->command[1] = 0; - - pDesc->DataFlash_state = GET_STATUS; - pDesc->tx_data_size = 0 ; /* Transmit the command and receive response */ - pDesc->tx_cmd_pt = pDesc->command ; - pDesc->rx_cmd_pt = pDesc->command ; - pDesc->rx_cmd_size = 2 ; - pDesc->tx_cmd_size = 2 ; - status = AT91F_SpiWrite (pDesc); - - pDesc->DataFlash_state = *( (unsigned char *) (pDesc->rx_cmd_pt) +1); - - return status; -} - - -/*----------------------------------------------------------------------*/ -/* \fn AT91F_DataFlashWaitReady */ -/* \brief wait for dataflash ready (bit7 of the status register == 1) */ -/*----------------------------------------------------------------------*/ -AT91S_DataFlashStatus AT91F_DataFlashWaitReady(AT91PS_DataflashDesc pDataFlashDesc, unsigned int timeout) -{ - pDataFlashDesc->DataFlash_state = IDLE; - - do { - AT91F_DataFlashGetStatus(pDataFlashDesc); - timeout--; - } while( ((pDataFlashDesc->DataFlash_state & 0x80) != 0x80) && (timeout > 0) ); - - if((pDataFlashDesc->DataFlash_state & 0x80) != 0x80) - return DATAFLASH_ERROR; - - return DATAFLASH_OK; -} - - -/*------------------------------------------------------------------------------*/ -/* Function Name : AT91F_DataFlashContinuousRead */ -/* Object : Continuous stream Read */ -/* Input Parameters : DataFlash Service */ -/* : = dataflash address */ -/* : <*dataBuffer> = data buffer pointer */ -/* : = data buffer size */ -/* Return value : State of the dataflash */ -/*------------------------------------------------------------------------------*/ -AT91S_DataFlashStatus AT91F_DataFlashContinuousRead ( - AT91PS_DataFlash pDataFlash, - int src, - unsigned char *dataBuffer, - int sizeToRead ) -{ - AT91S_DataFlashStatus status; - /* Test the size to read in the device */ - if ( (src + sizeToRead) > (pDataFlash->pDevice->pages_size * (pDataFlash->pDevice->pages_number))) - return DATAFLASH_MEMORY_OVERFLOW; - - pDataFlash->pDataFlashDesc->rx_data_pt = dataBuffer; - pDataFlash->pDataFlashDesc->rx_data_size = sizeToRead; - pDataFlash->pDataFlashDesc->tx_data_pt = dataBuffer; - pDataFlash->pDataFlashDesc->tx_data_size = sizeToRead; - - status = AT91F_DataFlashSendCommand (pDataFlash, DB_CONTINUOUS_ARRAY_READ, 8, src); - /* Send the command to the dataflash */ - return(status); -} - - -/*------------------------------------------------------------------------------*/ -/* Function Name : AT91F_DataFlashPagePgmBuf */ -/* Object : Main memory page program through buffer 1 or buffer 2 */ -/* Input Parameters : DataFlash Service */ -/* : <*src> = Source buffer */ -/* : = dataflash destination address */ -/* : = data buffer size */ -/* Return value : State of the dataflash */ -/*------------------------------------------------------------------------------*/ -AT91S_DataFlashStatus AT91F_DataFlashPagePgmBuf( - AT91PS_DataFlash pDataFlash, - unsigned char *src, - unsigned int dest, - unsigned int SizeToWrite) -{ - int cmdsize; - pDataFlash->pDataFlashDesc->tx_data_pt = src ; - pDataFlash->pDataFlashDesc->tx_data_size = SizeToWrite ; - pDataFlash->pDataFlashDesc->rx_data_pt = src; - pDataFlash->pDataFlashDesc->rx_data_size = SizeToWrite; - - cmdsize = 4; - /* Send the command to the dataflash */ - if (pDataFlash->pDevice->pages_number >= 16384) - cmdsize = 5; - return(AT91F_DataFlashSendCommand (pDataFlash, DB_PAGE_PGM_BUF1, cmdsize, dest)); -} - - -/*------------------------------------------------------------------------------*/ -/* Function Name : AT91F_MainMemoryToBufferTransfert */ -/* Object : Read a page in the SRAM Buffer 1 or 2 */ -/* Input Parameters : DataFlash Service */ -/* : Page concerned */ -/* : */ -/* Return value : State of the dataflash */ -/*------------------------------------------------------------------------------*/ -AT91S_DataFlashStatus AT91F_MainMemoryToBufferTransfert( - AT91PS_DataFlash pDataFlash, - unsigned char BufferCommand, - unsigned int page) -{ - int cmdsize; - /* Test if the buffer command is legal */ - if ((BufferCommand != DB_PAGE_2_BUF1_TRF) && (BufferCommand != DB_PAGE_2_BUF2_TRF)) - return DATAFLASH_BAD_COMMAND; - - /* no data to transmit or receive */ - pDataFlash->pDataFlashDesc->tx_data_size = 0; - cmdsize = 4; - if (pDataFlash->pDevice->pages_number >= 16384) - cmdsize = 5; - return(AT91F_DataFlashSendCommand (pDataFlash, BufferCommand, cmdsize, page*pDataFlash->pDevice->pages_size)); -} - - -/*----------------------------------------------------------------------------- */ -/* Function Name : AT91F_DataFlashWriteBuffer */ -/* Object : Write data to the internal sram buffer 1 or 2 */ -/* Input Parameters : DataFlash Service */ -/* : = command to write buffer1 or buffer2 */ -/* : <*dataBuffer> = data buffer to write */ -/* : = address in the internal buffer */ -/* : = data buffer size */ -/* Return value : State of the dataflash */ -/*------------------------------------------------------------------------------*/ -AT91S_DataFlashStatus AT91F_DataFlashWriteBuffer ( - AT91PS_DataFlash pDataFlash, - unsigned char BufferCommand, - unsigned char *dataBuffer, - unsigned int bufferAddress, - int SizeToWrite ) -{ - int cmdsize; - /* Test if the buffer command is legal */ - if ((BufferCommand != DB_BUF1_WRITE) && (BufferCommand != DB_BUF2_WRITE)) - return DATAFLASH_BAD_COMMAND; - - /* buffer address must be lower than page size */ - if (bufferAddress > pDataFlash->pDevice->pages_size) - return DATAFLASH_BAD_ADDRESS; - - if ( (pDataFlash->pDataFlashDesc->state) != IDLE) - return DATAFLASH_BUSY; - - /* Send first Write Command */ - pDataFlash->pDataFlashDesc->command[0] = BufferCommand; - pDataFlash->pDataFlashDesc->command[1] = 0; - if (pDataFlash->pDevice->pages_number >= 16384) { - pDataFlash->pDataFlashDesc->command[2] = 0; - pDataFlash->pDataFlashDesc->command[3] = (unsigned char)(((unsigned int)(bufferAddress & pDataFlash->pDevice->byte_mask)) >> 8) ; - pDataFlash->pDataFlashDesc->command[4] = (unsigned char)((unsigned int)bufferAddress & 0x00FF) ; - cmdsize = 5; - } else { - pDataFlash->pDataFlashDesc->command[2] = (unsigned char)(((unsigned int)(bufferAddress & pDataFlash->pDevice->byte_mask)) >> 8) ; - pDataFlash->pDataFlashDesc->command[3] = (unsigned char)((unsigned int)bufferAddress & 0x00FF) ; - pDataFlash->pDataFlashDesc->command[4] = 0; - cmdsize = 4; - } - - pDataFlash->pDataFlashDesc->tx_cmd_pt = pDataFlash->pDataFlashDesc->command ; - pDataFlash->pDataFlashDesc->tx_cmd_size = cmdsize ; - pDataFlash->pDataFlashDesc->rx_cmd_pt = pDataFlash->pDataFlashDesc->command ; - pDataFlash->pDataFlashDesc->rx_cmd_size = cmdsize ; - - pDataFlash->pDataFlashDesc->rx_data_pt = dataBuffer ; - pDataFlash->pDataFlashDesc->tx_data_pt = dataBuffer ; - pDataFlash->pDataFlashDesc->rx_data_size = SizeToWrite ; - pDataFlash->pDataFlashDesc->tx_data_size = SizeToWrite ; - - return AT91F_SpiWrite(pDataFlash->pDataFlashDesc); -} - -/*------------------------------------------------------------------------------*/ -/* Function Name : AT91F_PageErase */ -/* Object : Erase a page */ -/* Input Parameters : DataFlash Service */ -/* : Page concerned */ -/* : */ -/* Return value : State of the dataflash */ -/*------------------------------------------------------------------------------*/ -AT91S_DataFlashStatus AT91F_PageErase( - AT91PS_DataFlash pDataFlash, - unsigned int page) -{ - int cmdsize; - /* Test if the buffer command is legal */ - /* no data to transmit or receive */ - pDataFlash->pDataFlashDesc->tx_data_size = 0; - - cmdsize = 4; - if (pDataFlash->pDevice->pages_number >= 16384) - cmdsize = 5; - return(AT91F_DataFlashSendCommand (pDataFlash, DB_PAGE_ERASE, cmdsize, page*pDataFlash->pDevice->pages_size)); -} - - -/*------------------------------------------------------------------------------*/ -/* Function Name : AT91F_BlockErase */ -/* Object : Erase a Block */ -/* Input Parameters : DataFlash Service */ -/* : Page concerned */ -/* : */ -/* Return value : State of the dataflash */ -/*------------------------------------------------------------------------------*/ -AT91S_DataFlashStatus AT91F_BlockErase( - AT91PS_DataFlash pDataFlash, - unsigned int block) -{ - int cmdsize; - /* Test if the buffer command is legal */ - /* no data to transmit or receive */ - pDataFlash->pDataFlashDesc->tx_data_size = 0; - cmdsize = 4; - if (pDataFlash->pDevice->pages_number >= 16384) - cmdsize = 5; - return(AT91F_DataFlashSendCommand (pDataFlash, DB_BLOCK_ERASE,cmdsize, block*8*pDataFlash->pDevice->pages_size)); -} - -/*------------------------------------------------------------------------------*/ -/* Function Name : AT91F_WriteBufferToMain */ -/* Object : Write buffer to the main memory */ -/* Input Parameters : DataFlash Service */ -/* : = command to send to buffer1 or buffer2 */ -/* : = main memory address */ -/* Return value : State of the dataflash */ -/*------------------------------------------------------------------------------*/ -AT91S_DataFlashStatus AT91F_WriteBufferToMain ( - AT91PS_DataFlash pDataFlash, - unsigned char BufferCommand, - unsigned int dest ) -{ - int cmdsize; - /* Test if the buffer command is correct */ - if ((BufferCommand != DB_BUF1_PAGE_PGM) && - (BufferCommand != DB_BUF1_PAGE_ERASE_PGM) && - (BufferCommand != DB_BUF2_PAGE_PGM) && - (BufferCommand != DB_BUF2_PAGE_ERASE_PGM) ) - return DATAFLASH_BAD_COMMAND; - - /* no data to transmit or receive */ - pDataFlash->pDataFlashDesc->tx_data_size = 0; - - cmdsize = 4; - if (pDataFlash->pDevice->pages_number >= 16384) - cmdsize = 5; - /* Send the command to the dataflash */ - return(AT91F_DataFlashSendCommand (pDataFlash, BufferCommand, cmdsize, dest)); -} - - -/*------------------------------------------------------------------------------*/ -/* Function Name : AT91F_PartialPageWrite */ -/* Object : Erase partielly a page */ -/* Input Parameters : = page number */ -/* : = adr to begin the fading */ -/* : = Number of bytes to erase */ -/*------------------------------------------------------------------------------*/ -AT91S_DataFlashStatus AT91F_PartialPageWrite ( - AT91PS_DataFlash pDataFlash, - unsigned char *src, - unsigned int dest, - unsigned int size) -{ - unsigned int page; - unsigned int AdrInPage; - - page = dest / (pDataFlash->pDevice->pages_size); - AdrInPage = dest % (pDataFlash->pDevice->pages_size); - - /* Read the contents of the page in the Sram Buffer */ - AT91F_MainMemoryToBufferTransfert(pDataFlash, DB_PAGE_2_BUF1_TRF, page); - AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY); - /*Update the SRAM buffer */ - AT91F_DataFlashWriteBuffer(pDataFlash, DB_BUF1_WRITE, src, AdrInPage, size); - - AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY); - - /* Erase page if a 128 Mbits device */ - if (pDataFlash->pDevice->pages_number >= 16384) { - AT91F_PageErase(pDataFlash, page); - /* Rewrite the modified Sram Buffer in the main memory */ - AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY); - } - - /* Rewrite the modified Sram Buffer in the main memory */ - return(AT91F_WriteBufferToMain(pDataFlash, DB_BUF1_PAGE_ERASE_PGM, (page*pDataFlash->pDevice->pages_size))); -} - - -/*------------------------------------------------------------------------------*/ -/* Function Name : AT91F_DataFlashWrite */ -/* Object : */ -/* Input Parameters : <*src> = Source buffer */ -/* : = dataflash adress */ -/* : = data buffer size */ -/*------------------------------------------------------------------------------*/ -AT91S_DataFlashStatus AT91F_DataFlashWrite( - AT91PS_DataFlash pDataFlash, - unsigned char *src, - int dest, - int size ) -{ - unsigned int length; - unsigned int page; - unsigned int status; - - AT91F_SpiEnable(pDataFlash->pDevice->cs); - - if ( (dest + size) > (pDataFlash->pDevice->pages_size * (pDataFlash->pDevice->pages_number))) - return DATAFLASH_MEMORY_OVERFLOW; - - /* If destination does not fit a page start address */ - if ((dest % ((unsigned int)(pDataFlash->pDevice->pages_size))) != 0 ) { - length = pDataFlash->pDevice->pages_size - (dest % ((unsigned int)(pDataFlash->pDevice->pages_size))); - - if (size < length) - length = size; - - if(!AT91F_PartialPageWrite(pDataFlash,src, dest, length)) - return DATAFLASH_ERROR; - - AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY); - - /* Update size, source and destination pointers */ - size -= length; - dest += length; - src += length; - } - - while (( size - pDataFlash->pDevice->pages_size ) >= 0 ) { - /* program dataflash page */ - page = (unsigned int)dest / (pDataFlash->pDevice->pages_size); - - status = AT91F_DataFlashWriteBuffer(pDataFlash, DB_BUF1_WRITE, src, 0, pDataFlash->pDevice->pages_size); - AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY); - - status = AT91F_PageErase(pDataFlash, page); - AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY); - if (!status) - return DATAFLASH_ERROR; - - status = AT91F_WriteBufferToMain (pDataFlash, DB_BUF1_PAGE_PGM, dest); - if(!status) - return DATAFLASH_ERROR; - - AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY); - - /* Update size, source and destination pointers */ - size -= pDataFlash->pDevice->pages_size ; - dest += pDataFlash->pDevice->pages_size ; - src += pDataFlash->pDevice->pages_size ; - } - - /* If still some bytes to read */ - if ( size > 0 ) { - /* program dataflash page */ - if(!AT91F_PartialPageWrite(pDataFlash, src, dest, size) ) - return DATAFLASH_ERROR; - - AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY); - } - return DATAFLASH_OK; -} - - -/*------------------------------------------------------------------------------*/ -/* Function Name : AT91F_DataFlashRead */ -/* Object : Read a block in dataflash */ -/* Input Parameters : */ -/* Return value : */ -/*------------------------------------------------------------------------------*/ -int AT91F_DataFlashRead( - AT91PS_DataFlash pDataFlash, - unsigned long addr, - unsigned long size, - char *buffer) -{ - unsigned long SizeToRead; - - AT91F_SpiEnable(pDataFlash->pDevice->cs); - - if(AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY) != DATAFLASH_OK) - return -1; - - while (size) { - SizeToRead = (size < 0x8000)? size:0x8000; - - if (AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY) != DATAFLASH_OK) - return -1; - - if (AT91F_DataFlashContinuousRead (pDataFlash, addr, buffer, SizeToRead) != DATAFLASH_OK) - return -1; - - size -= SizeToRead; - addr += SizeToRead; - buffer += SizeToRead; - } - - return DATAFLASH_OK; -} - - -/*------------------------------------------------------------------------------*/ -/* Function Name : AT91F_DataflashProbe */ -/* Object : */ -/* Input Parameters : */ -/* Return value : Dataflash status register */ -/*------------------------------------------------------------------------------*/ -int AT91F_DataflashProbe(int cs, AT91PS_DataflashDesc pDesc) -{ - AT91F_SpiEnable(cs); - AT91F_DataFlashGetStatus(pDesc); - return((pDesc->command[1] == 0xFF)? 0: pDesc->command[1] & 0x3C); -} - -#endif From 65d7ada64557e76094b4fd3bad30a0f18f5fb2b2 Mon Sep 17 00:00:00 2001 From: Peter Pearse Date: Tue, 14 Aug 2007 10:30:06 +0100 Subject: [PATCH 110/259] Update Makefiles for merged and split at45.c. --- board/at91rm9200dk/Makefile | 2 +- board/cmc_pu2/Makefile | 2 +- drivers/Makefile | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) mode change 100644 => 100755 board/at91rm9200dk/Makefile mode change 100644 => 100755 board/cmc_pu2/Makefile mode change 100644 => 100755 drivers/Makefile diff --git a/board/at91rm9200dk/Makefile b/board/at91rm9200dk/Makefile old mode 100644 new mode 100755 index 7dfc27f0a..01f3bc30a --- a/board/at91rm9200dk/Makefile +++ b/board/at91rm9200dk/Makefile @@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a -COBJS := at91rm9200dk.o at45.o flash.o led.o mux.o +COBJS := at91rm9200dk.o flash.o led.o mux.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/board/cmc_pu2/Makefile b/board/cmc_pu2/Makefile old mode 100644 new mode 100755 index d445f287c..f7a136034 --- a/board/cmc_pu2/Makefile +++ b/board/cmc_pu2/Makefile @@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a -COBJS := cmc_pu2.o at45.o flash.o load_sernum_ethaddr.o +COBJS := cmc_pu2.o flash.o load_sernum_ethaddr.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/drivers/Makefile b/drivers/Makefile old mode 100644 new mode 100755 index fc9804076..3ee6312e9 --- a/drivers/Makefile +++ b/drivers/Makefile @@ -27,7 +27,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)libdrivers.a -COBJS = 3c589.o 5701rls.o ali512x.o ata_piix.o atmel_usart.o \ +COBJS = 3c589.o 5701rls.o ali512x.o at45.o ata_piix.o atmel_usart.o \ bcm570x.o bcm570x_autoneg.o cfb_console.o cfi_flash.o \ cs8900.o ct69000.o dataflash.o dc2114x.o dm9000x.o \ e1000.o eepro100.o enc28j60.o \ From 0c42f36f15074bd9808a7dbd7ef611fad9bf537c Mon Sep 17 00:00:00 2001 From: Peter Pearse Date: Tue, 14 Aug 2007 10:46:32 +0100 Subject: [PATCH 111/259] Replace lost end of at45.c. --- drivers/at45.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) mode change 100644 => 100755 drivers/at45.c diff --git a/drivers/at45.c b/drivers/at45.c old mode 100644 new mode 100755 index 35c9ecce4..4c12ca7a3 --- a/drivers/at45.c +++ b/drivers/at45.c @@ -547,4 +547,18 @@ int AT91F_DataFlashRead( return DATAFLASH_OK; } +/*---------------------------------------------------------------------------*/ +/* Function Name : AT91F_DataflashProbe */ +/* Object : */ +/* Input Parameters : */ +/* Return value : Dataflash status register */ +/*---------------------------------------------------------------------------*/ +int AT91F_DataflashProbe(int cs, AT91PS_DataflashDesc pDesc) { + AT91F_SpiEnable(cs); + AT91F_DataFlashGetStatus(pDesc); + return((pDesc->command[1] == 0xFF)? 0: pDesc->command[1] & 0x3C); +} + +#endif + From eb2b4010ae426245172988804ee8d9193fb41038 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Tue, 14 Aug 2007 14:39:44 +0200 Subject: [PATCH 112/259] POST: Add ppc405 support to cache and UART POST Signed-off-by: Stefan Roese --- post/cpu/ppc4xx/cache.c | 16 ++++- post/cpu/ppc4xx/cache_4xx.S | 44 ++++++++++++ post/cpu/ppc4xx/uart.c | 133 ++++++++++++++++++++++++++++++++++-- 3 files changed, 186 insertions(+), 7 deletions(-) diff --git a/post/cpu/ppc4xx/cache.c b/post/cpu/ppc4xx/cache.c index e1f989ed9..109ca1fbd 100644 --- a/post/cpu/ppc4xx/cache.c +++ b/post/cpu/ppc4xx/cache.c @@ -53,14 +53,25 @@ int cache_post_test6 (int tlb, void *p, int size); static int tlb = -1; /* index to the victim TLB entry */ +#ifdef CONFIG_440 static unsigned char testarea[CACHE_POST_SIZE] __attribute__((__aligned__(CACHE_POST_SIZE))); +#endif int cache_post_test (int flags) { void* virt = (void*)CFG_POST_CACHE_ADDR; - int ints, i, res = 0; - u32 word0; + int ints; + int res = 0; + + /* + * All 44x variants deal with cache management differently + * because they have the address translation always enabled. + * The 40x ppc's don't use address translation in U-Boot at all, + * so we have to distinguish here between 40x and 44x. + */ +#ifdef CONFIG_440 + int word0, i; if (tlb < 0) { /* @@ -83,6 +94,7 @@ int cache_post_test (int flags) } } } +#endif ints = disable_interrupts (); WATCHDOG_RESET (); diff --git a/post/cpu/ppc4xx/cache_4xx.S b/post/cpu/ppc4xx/cache_4xx.S index dddd76b23..d5cb075d6 100644 --- a/post/cpu/ppc4xx/cache_4xx.S +++ b/post/cpu/ppc4xx/cache_4xx.S @@ -37,6 +37,13 @@ .text + /* + * All 44x variants deal with cache management differently + * because they have the address translation always enabled. + * The 40x ppc's don't use address translation in U-Boot at all, + * so we have to distinguish here between 40x and 44x. + */ +#ifdef CONFIG_440 /* void cache_post_disable (int tlb) */ cache_post_disable: @@ -68,6 +75,43 @@ cache_post_wb: sync isync blr +#else +/* void cache_post_disable (int tlb) + */ +cache_post_disable: + lis r0, 0x0000 + ori r0, r0, 0x0000 + mtdccr r0 + sync + isync + blr + +/* void cache_post_wt (int tlb) + */ +cache_post_wt: + lis r0, 0x8000 + ori r0, r0, 0x0000 + mtdccr r0 + lis r0, 0x8000 + ori r0, r0, 0x0000 + mtdcwr r0 + sync + isync + blr + +/* void cache_post_wb (int tlb) + */ +cache_post_wb: + lis r0, 0x8000 + ori r0, r0, 0x0000 + mtdccr r0 + lis r0, 0x0000 + ori r0, r0, 0x0000 + mtdcwr r0 + sync + isync + blr +#endif /* void cache_post_dinvalidate (void *p, int size) */ diff --git a/post/cpu/ppc4xx/uart.c b/post/cpu/ppc4xx/uart.c index b047d42df..0cffda5fc 100644 --- a/post/cpu/ppc4xx/uart.c +++ b/post/cpu/ppc4xx/uart.c @@ -38,24 +38,77 @@ #if CONFIG_POST & CFG_POST_UART +/* + * This table defines the UART's that should be tested and can + * be overridden in the board config file + */ +#ifndef CFG_POST_UART_TABLE +#define CFG_POST_UART_TABLE {UART0_BASE, UART1_BASE, UART2_BASE, UART3_BASE} +#endif + #include #include +#if defined(CONFIG_440) +#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ + defined(CONFIG_440EPX) || defined(CONFIG_440GRX) #define UART0_BASE CFG_PERIPHERAL_BASE + 0x00000300 #define UART1_BASE CFG_PERIPHERAL_BASE + 0x00000400 #define UART2_BASE CFG_PERIPHERAL_BASE + 0x00000500 #define UART3_BASE CFG_PERIPHERAL_BASE + 0x00000600 +#else +#define UART0_BASE CFG_PERIPHERAL_BASE + 0x00000200 +#define UART1_BASE CFG_PERIPHERAL_BASE + 0x00000300 +#endif +#if defined(CONFIG_440SP) || defined(CONFIG_440SPE) +#define UART2_BASE CFG_PERIPHERAL_BASE + 0x00000600 +#endif + +#if defined(CONFIG_440GP) +#define CR0_MASK 0x3fff0000 +#define CR0_EXTCLK_ENA 0x00600000 +#define CR0_UDIV_POS 16 +#define UDIV_SUBTRACT 1 +#define UART0_SDR cntrl0 +#define MFREG(a, d) d = mfdcr(a) +#define MTREG(a, d) mtdcr(a, d) +#else /* #if defined(CONFIG_440GP) */ +/* all other 440 PPC's access clock divider via sdr register */ #define CR0_MASK 0xdfffffff #define CR0_EXTCLK_ENA 0x00800000 #define CR0_UDIV_POS 0 #define UDIV_SUBTRACT 0 #define UART0_SDR sdr_uart0 #define UART1_SDR sdr_uart1 +#if defined(CONFIG_440EP) || defined(CONFIG_440EPx) || \ + defined(CONFIG_440GR) || defined(CONFIG_440GRx) || \ + defined(CONFIG_440SP) || defined(CONFIG_440SPe) #define UART2_SDR sdr_uart2 +#endif +#if defined(CONFIG_440EP) || defined(CONFIG_440EPx) || \ + defined(CONFIG_440GR) || defined(CONFIG_440GRx) #define UART3_SDR sdr_uart3 +#endif #define MFREG(a, d) mfsdr(a, d) #define MTREG(a, d) mtsdr(a, d) +#endif /* #if defined(CONFIG_440GP) */ +#elif defined(CONFIG_405EP) || defined(CONFIG_405EZ) +#define UART0_BASE 0xef600300 +#define UART1_BASE 0xef600400 +#define UCR0_MASK 0x0000007f +#define UCR1_MASK 0x00007f00 +#define UCR0_UDIV_POS 0 +#define UCR1_UDIV_POS 8 +#define UDIV_MAX 127 +#else /* CONFIG_405GP || CONFIG_405CR */ +#define UART0_BASE 0xef600300 +#define UART1_BASE 0xef600400 +#define CR0_MASK 0x00001fff +#define CR0_EXTCLK_ENA 0x000000c0 +#define CR0_UDIV_POS 1 +#define UDIV_MAX 32 +#endif #define UART_RBR 0x00 #define UART_THR 0x00 @@ -71,8 +124,8 @@ #define UART_DLM 0x01 /* - Line Status Register. -*/ + * Line Status Register. + */ #define asyncLSRDataReady1 0x01 #define asyncLSROverrunError1 0x02 #define asyncLSRParityError1 0x04 @@ -84,6 +137,7 @@ DECLARE_GLOBAL_DATA_PTR; +#if defined(CONFIG_440) static int uart_post_init (unsigned long dev_base) { unsigned long reg; @@ -147,6 +201,77 @@ static int uart_post_init (unsigned long dev_base) return 0; } +#else /* CONFIG_440 */ + +static int uart_post_init (unsigned long dev_base) +{ + unsigned long reg; + unsigned long tmp; + unsigned long clk; + unsigned long udiv; + unsigned short bdiv; + volatile char val; + int i; + + for (i = 0; i < 3500; i++) { + if (in8 (dev_base + UART_LSR) & asyncLSRTxHoldEmpty1) + break; + udelay (100); + } + +#if defined(CONFIG_405EZ) + serial_divs(gd->baudrate, &udiv, &bdiv); + clk = tmp = reg = 0; +#else +#ifdef CONFIG_405EP + reg = mfdcr(cpc0_ucr) & ~(UCR0_MASK | UCR1_MASK); + clk = gd->cpu_clk; + tmp = CFG_BASE_BAUD * 16; + udiv = (clk + tmp / 2) / tmp; + if (udiv > UDIV_MAX) /* max. n bits for udiv */ + udiv = UDIV_MAX; + reg |= (udiv) << UCR0_UDIV_POS; /* set the UART divisor */ + reg |= (udiv) << UCR1_UDIV_POS; /* set the UART divisor */ + mtdcr (cpc0_ucr, reg); +#else /* CONFIG_405EP */ + reg = mfdcr(cntrl0) & ~CR0_MASK; +#ifdef CFG_EXT_SERIAL_CLOCK + clk = CFG_EXT_SERIAL_CLOCK; + udiv = 1; + reg |= CR0_EXTCLK_ENA; +#else + clk = gd->cpu_clk; +#ifdef CFG_405_UART_ERRATA_59 + udiv = 31; /* Errata 59: stuck at 31 */ +#else + tmp = CFG_BASE_BAUD * 16; + udiv = (clk + tmp / 2) / tmp; + if (udiv > UDIV_MAX) /* max. n bits for udiv */ + udiv = UDIV_MAX; +#endif +#endif + reg |= (udiv - 1) << CR0_UDIV_POS; /* set the UART divisor */ + mtdcr (cntrl0, reg); +#endif /* CONFIG_405EP */ + tmp = gd->baudrate * udiv * 16; + bdiv = (clk + tmp / 2) / tmp; +#endif /* CONFIG_405EZ */ + + out8(dev_base + UART_LCR, 0x80); /* set DLAB bit */ + out8(dev_base + UART_DLL, bdiv); /* set baudrate divisor */ + out8(dev_base + UART_DLM, bdiv >> 8); /* set baudrate divisor */ + out8(dev_base + UART_LCR, 0x03); /* clear DLAB; set 8 bits, no parity */ + out8(dev_base + UART_FCR, 0x00); /* disable FIFO */ + out8(dev_base + UART_MCR, 0x10); /* enable loopback mode */ + val = in8(dev_base + UART_LSR); /* clear line status */ + val = in8(dev_base + UART_RBR); /* read receive buffer */ + out8(dev_base + UART_SCR, 0x00); /* set scratchpad */ + out8(dev_base + UART_IER, 0x00); /* set interrupt enable reg */ + + return (0); +} +#endif /* CONFIG_440 */ + static void uart_post_putc (unsigned long dev_base, char c) { int i; @@ -198,9 +323,7 @@ done: int uart_post_test (int flags) { int i, res = 0; - static unsigned long base[] = { - UART0_BASE, UART1_BASE, UART2_BASE, UART3_BASE - }; + static unsigned long base[] = CFG_POST_UART_TABLE; for (i = 0; i < sizeof (base) / sizeof (base[0]); i++) { if (test_ctlr (base[i], i)) From c5a172a5fd636c12467429e3f7910e53773979c6 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Tue, 14 Aug 2007 14:41:55 +0200 Subject: [PATCH 113/259] POST: Add option for external ethernet loopback test When CFG_POST_ETHER_EXT_LOOPBACK is defined, the ethernet POST is not done using an internal loopback connection, but by assuming that an external loopback connector is plugged into the board. Signed-off-by: Stefan Roese --- post/cpu/ppc4xx/ether.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/post/cpu/ppc4xx/ether.c b/post/cpu/ppc4xx/ether.c index 391c815d7..ab23ca5a3 100644 --- a/post/cpu/ppc4xx/ether.c +++ b/post/cpu/ppc4xx/ether.c @@ -68,10 +68,10 @@ static char *rx_buf; static void ether_post_init (int devnum, int hw_addr) { int i; - unsigned mode_reg; #if defined(CONFIG_440GX) || \ defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ defined(CONFIG_440SP) || defined(CONFIG_440SPE) + unsigned mode_reg; sys_info_t sysinfo; #endif #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || defined(CONFIG_440SPE) @@ -185,10 +185,17 @@ static void ether_post_init (int devnum, int hw_addr) mtdcr (malrxcasr, (MAL_TXRX_CASR >> devnum)); /* set internal loopback mode */ +#ifdef CFG_POST_ETHER_EXT_LOOPBACK + out32 (EMAC_M1 + hw_addr, EMAC_M1_FDE | 0 | + EMAC_M1_RFS_4K | EMAC_M1_TX_FIFO_2K | + EMAC_M1_MF_100MBPS | EMAC_M1_IST | + in32 (EMAC_M1)); +#else out32 (EMAC_M1 + hw_addr, EMAC_M1_FDE | EMAC_M1_ILE | EMAC_M1_RFS_4K | EMAC_M1_TX_FIFO_2K | EMAC_M1_MF_100MBPS | EMAC_M1_IST | in32 (EMAC_M1)); +#endif /* set transmit enable & receive enable */ out32 (EMAC_M0 + hw_addr, EMAC_M0_TXE | EMAC_M0_RXE); From 779e975117a75e91fcebe226a63104dbfb924ab1 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Tue, 14 Aug 2007 14:44:41 +0200 Subject: [PATCH 114/259] ppc4xx: Add initial Zeus (PPC405EP) board support Signed-off-by: Stefan Roese --- MAINTAINERS | 1 + MAKEALL | 2 +- Makefile | 3 + board/amcc/bubinga/bubinga.c | 13 +- board/amcc/taihu/taihu.c | 6 + board/zeus/Makefile | 51 ++++ board/zeus/config.mk | 24 ++ board/zeus/u-boot.lds | 133 +++++++++ board/zeus/update.c | 105 +++++++ board/zeus/zeus.c | 511 +++++++++++++++++++++++++++++++++++ cpu/ppc4xx/sdram.c | 27 +- cpu/ppc4xx/sdram.h | 2 - cpu/ppc4xx/start.S | 48 ++-- doc/README.zeus | 73 +++++ include/configs/zeus.h | 375 +++++++++++++++++++++++++ include/ppc405.h | 14 + 16 files changed, 1344 insertions(+), 44 deletions(-) create mode 100644 board/zeus/Makefile create mode 100644 board/zeus/config.mk create mode 100644 board/zeus/u-boot.lds create mode 100644 board/zeus/update.c create mode 100644 board/zeus/zeus.c create mode 100644 doc/README.zeus create mode 100644 include/configs/zeus.h diff --git a/MAINTAINERS b/MAINTAINERS index 6dd43f861..853afeb4d 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -293,6 +293,7 @@ Stefan Roese walnut PPC405GP yellowstone PPC440GR yosemite PPC440EP + zeus PPC405EP P3M750 PPC750FX/GX/GL diff --git a/MAKEALL b/MAKEALL index f69134a63..00cb6b535 100755 --- a/MAKEALL +++ b/MAKEALL @@ -91,7 +91,7 @@ LIST_4xx=" \ sc3 sequoia sequoia_nand taihu \ taishan VOH405 VOM405 W7OLMC \ W7OLMG walnut WUH405 XPEDITE1K \ - yellowstone yosemite yucca \ + yellowstone yosemite yucca zeus \ " ######################################################################### diff --git a/Makefile b/Makefile index d4fd34e43..d75f8fddd 100644 --- a/Makefile +++ b/Makefile @@ -1294,6 +1294,9 @@ yellowstone_config: unconfig yucca_config: unconfig @$(MKCONFIG) $(@:_config=) ppc ppc4xx yucca amcc +zeus_config: unconfig + @$(MKCONFIG) $(@:_config=) ppc ppc4xx zeus + ######################################################################### ## MPC8220 Systems ######################################################################### diff --git a/board/amcc/bubinga/bubinga.c b/board/amcc/bubinga/bubinga.c index fe6ce8a6d..66e7509da 100644 --- a/board/amcc/bubinga/bubinga.c +++ b/board/amcc/bubinga/bubinga.c @@ -20,10 +20,12 @@ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, * MA 02111-1307 USA */ -long int spd_sdram(void); #include #include +#include + +long int spd_sdram(void); int board_early_init_f(void) { @@ -34,6 +36,15 @@ int board_early_init_f(void) mtdcr(uictr, 0x00000010); /* set int trigger levels */ mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ + /* + * Configure CPC0_PCI to enable PerWE as output + * and enable the internal PCI arbiter if selected + */ + if (in_8((void *)FPGA_REG1) & FPGA_REG1_PCI_INT_ARB) + mtdcr(cpc0_pci, CPC0_PCI_HOST_CFG_EN | CPC0_PCI_ARBIT_EN); + else + mtdcr(cpc0_pci, CPC0_PCI_HOST_CFG_EN); + return 0; } diff --git a/board/amcc/taihu/taihu.c b/board/amcc/taihu/taihu.c index ee9d3b544..ea8367198 100644 --- a/board/amcc/taihu/taihu.c +++ b/board/amcc/taihu/taihu.c @@ -50,6 +50,12 @@ int board_early_init_f(void) mtebc(pb3ap, CFG_EBC_PB3AP); /* memory bank 3 (CPLD_LCM) initialization */ mtebc(pb3cr, CFG_EBC_PB3CR); + /* + * Configure CPC0_PCI to enable PerWE as output + * and enable the internal PCI arbiter + */ + mtdcr(cpc0_pci, CPC0_PCI_SPE | CPC0_PCI_HOST_CFG_EN | CPC0_PCI_ARBIT_EN); + return 0; } diff --git a/board/zeus/Makefile b/board/zeus/Makefile new file mode 100644 index 000000000..f0d4e9f3f --- /dev/null +++ b/board/zeus/Makefile @@ -0,0 +1,51 @@ +# +# (C) Copyright 2007 +# Stefan Roese, DENX Software Engineering, sr@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS = $(BOARD).o update.o +SOBJS = + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/zeus/config.mk b/board/zeus/config.mk new file mode 100644 index 000000000..1bdf5e4fc --- /dev/null +++ b/board/zeus/config.mk @@ -0,0 +1,24 @@ +# +# (C) Copyright 2000 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +TEXT_BASE = 0xFFFC0000 diff --git a/board/zeus/u-boot.lds b/board/zeus/u-boot.lds new file mode 100644 index 000000000..73b83eba4 --- /dev/null +++ b/board/zeus/u-boot.lds @@ -0,0 +1,133 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + .resetvec 0xFFFFFFFC : + { + *(.resetvec) + } = 0xffff + + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/ppc4xx/start.o (.text) + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/zeus/update.c b/board/zeus/update.c new file mode 100644 index 000000000..c76519f09 --- /dev/null +++ b/board/zeus/update.c @@ -0,0 +1,105 @@ +/* + * (C) Copyright 2007 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include +#include + +#if defined(CONFIG_ZEUS) + +u8 buf_zeus_ce[] = { +/*00 01 02 03 04 05 06 07 */ + 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +/*08 09 0a 0b 0c 0d 0e 0f */ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +/*10 11 12 13 14 15 16 17 */ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +/*18 19 1a 1b 1c 1d 1e 1f */ + 0x00, 0xc0, 0x50, 0x12, 0x72, 0x3e, 0x00, 0x00 }; + +u8 buf_zeus_pe[] = { + +/* CPU_CLOCK_DIV 1 = 00 + CPU_PLB_FREQ_DIV 3 = 10 + OPB_PLB_FREQ_DIV 2 = 01 + EBC_PLB_FREQ_DIV 2 = 00 + MAL_PLB_FREQ_DIV 1 = 00 + PCI_PLB_FRQ_DIV 3 = 10 + PLL_PLLOUTA = IS SET + PLL_OPERATING = IS NOT SET + PLL_FDB_MUL 10 = 1010 + PLL_FWD_DIV_A 3 = 101 + PLL_FWD_DIV_B 3 = 101 + TUNE = 0x2be */ +/*00 01 02 03 04 05 06 07 */ + 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +/*08 09 0a 0b 0c 0d 0e 0f */ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +/*10 11 12 13 14 15 16 17 */ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +/*18 19 1a 1b 1c 1d 1e 1f */ + 0x00, 0x60, 0x68, 0x2d, 0x42, 0xbe, 0x00, 0x00 }; + +static int update_boot_eeprom(void) +{ + u32 len = 0x20; + u8 chip = CFG_I2C_EEPROM_ADDR; + u8 *pbuf; + u8 base; + int i; + + if (in_be32((void *)GPIO0_IR) & GPIO_VAL(CFG_GPIO_ZEUS_PE)) { + pbuf = buf_zeus_pe; + base = 0x40; + } else { + pbuf = buf_zeus_ce; + base = 0x00; + } + + for (i = 0; i < len; i++, base++) { + if (i2c_write(chip, base, 1, &pbuf[i], 1) != 0) { + printf("i2c_write fail\n"); + return 1; + } + udelay(11000); + } + + return 0; +} + +int do_update_boot_eeprom(cmd_tbl_t* cmdtp, int flag, int argc, char* argv[]) +{ + return update_boot_eeprom(); +} + +U_BOOT_CMD ( + update_boot_eeprom, 1, 1, do_update_boot_eeprom, + "update_boot_eeprom - update boot eeprom content\n", + NULL +); + +#endif diff --git a/board/zeus/zeus.c b/board/zeus/zeus.c new file mode 100644 index 000000000..4ab853f8f --- /dev/null +++ b/board/zeus/zeus.c @@ -0,0 +1,511 @@ +/* + * (C) Copyright 2007 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#define REBOOT_MAGIC 0x07081967 +#define REBOOT_NOP 0x00000000 +#define REBOOT_DO_POST 0x00000001 + +extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ +extern env_t *env_ptr; +extern uchar default_environment[]; + +ulong flash_get_size(ulong base, int banknum); +void env_crc_update(void); +int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); + +static u32 start_time; + +int board_early_init_f(void) +{ + mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ + mtdcr(uicer, 0x00000000); /* disable all ints */ + mtdcr(uiccr, 0x00000000); + mtdcr(uicpr, 0xFFFF7F00); /* set int polarities */ + mtdcr(uictr, 0x00000000); /* set int trigger levels */ + mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ + mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority */ + + /* + * Configure CPC0_PCI to enable PerWE as output + */ + mtdcr(cpc0_pci, CPC0_PCI_SPE); + + return 0; +} + +int misc_init_r(void) +{ + u32 pbcr; + int size_val = 0; + u32 post_magic; + u32 post_val; + + post_magic = in_be32((void *)CFG_POST_MAGIC); + post_val = in_be32((void *)CFG_POST_VAL); + if ((post_magic == REBOOT_MAGIC) && (post_val == REBOOT_DO_POST)) { + /* + * Set special bootline bootparameter to pass this POST boot + * mode to Linux to reset the username/password + */ + setenv("addmisc", "setenv bootargs \\${bootargs} factory_reset=yes"); + + /* + * Normally don't run POST tests, only when enabled + * via the sw-reset button. So disable further tests + * upon next bootup here. + */ + out_be32((void *)CFG_POST_VAL, REBOOT_NOP); + } else { + /* + * Only run POST when initiated via the sw-reset button mechanism + */ + post_word_store(0); + } + + /* + * Get current time + */ + start_time = get_timer(0); + + /* + * FLASH stuff... + */ + + /* Re-do sizing to get full correct info */ + + /* adjust flash start and offset */ + mfebc(pb0cr, pbcr); + switch (gd->bd->bi_flashsize) { + case 1 << 20: + size_val = 0; + break; + case 2 << 20: + size_val = 1; + break; + case 4 << 20: + size_val = 2; + break; + case 8 << 20: + size_val = 3; + break; + case 16 << 20: + size_val = 4; + break; + case 32 << 20: + size_val = 5; + break; + case 64 << 20: + size_val = 6; + break; + case 128 << 20: + size_val = 7; + break; + } + pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17); + mtebc(pb0cr, pbcr); + + /* + * Re-check to get correct base address + */ + flash_get_size(gd->bd->bi_flashstart, 0); + + /* Monitor protection ON by default */ + (void)flash_protect(FLAG_PROTECT_SET, + -CFG_MONITOR_LEN, + 0xffffffff, + &flash_info[0]); + + /* Env protection ON by default */ + (void)flash_protect(FLAG_PROTECT_SET, + CFG_ENV_ADDR_REDUND, + CFG_ENV_ADDR_REDUND + 2*CFG_ENV_SECT_SIZE - 1, + &flash_info[0]); + + return 0; +} + +/* + * Check Board Identity: + */ +int checkboard(void) +{ + char *s = getenv("serial#"); + + puts("Board: Zeus-"); + + if (in_be32((void *)GPIO0_IR) & GPIO_VAL(CFG_GPIO_ZEUS_PE)) + puts("PE"); + else + puts("CE"); + + puts(" of BulletEndPoint"); + + if (s != NULL) { + puts(", serial# "); + puts(s); + } + putc('\n'); + + /* both LED's off */ + gpio_write_bit(CFG_GPIO_LED_RED, 0); + gpio_write_bit(CFG_GPIO_LED_GREEN, 0); + udelay(10000); + /* and on again */ + gpio_write_bit(CFG_GPIO_LED_RED, 1); + gpio_write_bit(CFG_GPIO_LED_GREEN, 1); + + return (0); +} + +static u32 detect_sdram_size(void) +{ + u32 val; + u32 size; + + mfsdram(mem_mb0cf, val); + size = (4 << 20) << ((val & 0x000e0000) >> 17); + + /* + * Check if 2nd bank is enabled too + */ + mfsdram(mem_mb1cf, val); + if (val & 1) + size += (4 << 20) << ((val & 0x000e0000) >> 17); + + return size; +} + +long int initdram (int board_type) +{ + return detect_sdram_size(); +} + +#if defined(CFG_DRAM_TEST) +int testdram(void) +{ + unsigned long *mem = (unsigned long *)0; + const unsigned long kend = (1024 / sizeof(unsigned long)); + unsigned long k, n; + unsigned long msr; + unsigned long total_kbytes; + + total_kbytes = detect_sdram_size(); + + msr = mfmsr(); + mtmsr(msr & ~(MSR_EE)); + + for (k = 0; k < total_kbytes ; + ++k, mem += (1024 / sizeof(unsigned long))) { + if ((k & 1023) == 0) { + printf("%3d MB\r", k / 1024); + } + + memset(mem, 0xaaaaaaaa, 1024); + for (n = 0; n < kend; ++n) { + if (mem[n] != 0xaaaaaaaa) { + printf("SDRAM test fails at: %08x\n", + (uint) & mem[n]); + return 1; + } + } + + memset(mem, 0x55555555, 1024); + for (n = 0; n < kend; ++n) { + if (mem[n] != 0x55555555) { + printf("SDRAM test fails at: %08x\n", + (uint) & mem[n]); + return 1; + } + } + } + printf("SDRAM test passes\n"); + mtmsr(msr); + + return 0; +} +#endif + +static int default_env_var(char *buf, char *var) +{ + char *ptr; + char *val; + + /* + * Find env variable + */ + ptr = strstr(buf + 4, var); + if (ptr == NULL) { + printf("ERROR: %s not found!\n", var); + return -1; + } + ptr += strlen(var) + 1; + + /* + * Now the ethaddr needs to be updated in the "normal" + * environment storage -> redundant flash. + */ + val = ptr; + setenv(var, val); + printf("Updated %s from eeprom to %s!\n", var, val); + + return 0; +} + +static int restore_default(void) +{ + char *buf; + char *buf_save; + u32 crc; + + /* + * Unprotect and erase environment area + */ + flash_protect(FLAG_PROTECT_CLEAR, + CFG_ENV_ADDR_REDUND, + CFG_ENV_ADDR_REDUND + 2*CFG_ENV_SECT_SIZE - 1, + &flash_info[0]); + + flash_sect_erase(CFG_ENV_ADDR_REDUND, + CFG_ENV_ADDR_REDUND + 2*CFG_ENV_SECT_SIZE - 1); + + /* + * Now restore default environment from U-Boot image + * -> ipaddr, serverip... + */ + memset(env_ptr, 0, sizeof(env_t)); + memcpy(env_ptr->data, default_environment, ENV_SIZE); +#ifdef CFG_REDUNDAND_ENVIRONMENT + env_ptr->flags = 0xFF; +#endif + env_crc_update(); + gd->env_valid = 1; + + /* + * Read board specific values from I2C EEPROM + * and set env variables accordingly + * -> ethaddr, eth1addr, serial# + */ + buf = buf_save = malloc(FACTORY_RESET_ENV_SIZE); + if (eeprom_read(FACTORY_RESET_I2C_EEPROM, FACTORY_RESET_ENV_OFFS, + (u8 *)buf, FACTORY_RESET_ENV_SIZE)) { + puts("\nError reading EEPROM!\n"); + } else { + crc = crc32(0, (u8 *)(buf + 4), FACTORY_RESET_ENV_SIZE - 4); + if (crc != *(u32 *)buf) { + printf("ERROR: crc mismatch %08lx %08lx\n", crc, *(u32 *)buf); + return -1; + } + + default_env_var(buf, "ethaddr"); + buf += 8 + 18; + default_env_var(buf, "eth1addr"); + buf += 9 + 18; + default_env_var(buf, "serial#"); + } + + /* + * Finally save updated env variables back to flash + */ + saveenv(); + + free(buf_save); + + return 0; +} + +int do_set_default(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + char *buf; + char *buf_save; + char str[32]; + u32 crc; + char var[32]; + + if (argc < 4) { + puts("ERROR!\n"); + return -1; + } + + buf = buf_save = malloc(FACTORY_RESET_ENV_SIZE); + memset(buf, 0, FACTORY_RESET_ENV_SIZE); + + strcpy(var, "ethaddr"); + printf("Setting %s to %s\n", var, argv[1]); + sprintf(str, "%s=%s", var, argv[1]); + strcpy(buf + 4, str); + buf += strlen(str) + 1; + + strcpy(var, "eth1addr"); + printf("Setting %s to %s\n", var, argv[2]); + sprintf(str, "%s=%s", var, argv[2]); + strcpy(buf + 4, str); + buf += strlen(str) + 1; + + strcpy(var, "serial#"); + printf("Setting %s to %s\n", var, argv[3]); + sprintf(str, "%s=%s", var, argv[3]); + strcpy(buf + 4, str); + + crc = crc32(0, (u8 *)(buf_save + 4), FACTORY_RESET_ENV_SIZE - 4); + *(u32 *)buf_save = crc; + + if (eeprom_write(FACTORY_RESET_I2C_EEPROM, FACTORY_RESET_ENV_OFFS, + (u8 *)buf_save, FACTORY_RESET_ENV_SIZE)) { + puts("\nError writing EEPROM!\n"); + return -1; + } + + free(buf_save); + + return 0; +} + +U_BOOT_CMD( + setdef, 4, 1, do_set_default, + "setdef - write board-specific values to EEPROM (ethaddr...)\n", + "ethaddr eth1addr serial#\n - write board-specific values to EEPROM\n" + ); + +static inline int sw_reset_pressed(void) +{ + return !(in_be32((void *)GPIO0_IR) & GPIO_VAL(CFG_GPIO_SW_RESET)); +} + +int do_chkreset(cmd_tbl_t* cmdtp, int flag, int argc, char* argv[]) +{ + int delta; + int count = 0; + int post = 0; + int factory_reset = 0; + + if (!sw_reset_pressed()) { + printf("SW-Reset already high (Button released)\n"); + printf("-> No action taken!\n"); + return 0; + } + + printf("Waiting for SW-Reset button to be released."); + + while (1) { + delta = get_timer(start_time); + if (!sw_reset_pressed()) + break; + + if ((delta > CFG_TIME_POST) && !post) { + printf("\nWhen released now, POST tests will be started."); + gpio_write_bit(CFG_GPIO_LED_GREEN, 0); + post = 1; + } + + if ((delta > CFG_TIME_FACTORY_RESET) && !factory_reset) { + printf("\nWhen released now, factory default values" + " will be restored."); + gpio_write_bit(CFG_GPIO_LED_RED, 0); + factory_reset = 1; + } + + udelay(1000); + if (!(count++ % 1000)) + printf("."); + } + + + printf("\nSW-Reset Button released after %d milli-seconds!\n", delta); + + if (delta > CFG_TIME_FACTORY_RESET) { + printf("Starting factory reset value restoration...\n"); + + /* + * Restore default setting + */ + restore_default(); + + /* + * Reset the board for default to become valid + */ + do_reset(NULL, 0, 0, NULL); + + return 0; + } + + if (delta > CFG_TIME_POST) { + printf("Starting POST configuration...\n"); + + /* + * Enable POST upon next bootup + */ + out_be32((void *)CFG_POST_MAGIC, REBOOT_MAGIC); + out_be32((void *)CFG_POST_VAL, REBOOT_DO_POST); + post_bootmode_init(); + + /* + * Reset the logbuffer for a clean start + */ + logbuff_reset(); + + do_reset(NULL, 0, 0, NULL); + + return 0; + } + + return 0; +} + +U_BOOT_CMD ( + chkreset, 1, 1, do_chkreset, + "chkreset- Check for status of SW-reset button and act accordingly\n", + NULL +); + +#if defined(CONFIG_POST) +/* + * Returns 1 if keys pressed to start the power-on long-running tests + * Called from board_init_f(). + */ +int post_hotkeys_pressed(void) +{ + u32 post_magic; + u32 post_val; + + post_magic = in_be32((void *)CFG_POST_MAGIC); + post_val = in_be32((void *)CFG_POST_VAL); + + if ((post_magic == REBOOT_MAGIC) && (post_val == REBOOT_DO_POST)) + return 1; + else + return 0; +} +#endif /* CONFIG_POST */ diff --git a/cpu/ppc4xx/sdram.c b/cpu/ppc4xx/sdram.c index 3a0ca17d9..2724d91f0 100644 --- a/cpu/ppc4xx/sdram.c +++ b/cpu/ppc4xx/sdram.c @@ -187,14 +187,14 @@ void sdram_init(void) /* * Disable memory controller. */ - mtsdram0(mem_mcopt1, 0x00000000); + mtsdram(mem_mcopt1, 0x00000000); /* * Set MB0CF for bank 0. */ - mtsdram0(mem_mb0cf, mb0cf[i].reg); - mtsdram0(mem_sdtr1, sdtr1); - mtsdram0(mem_rtr, compute_rtr(speed, mb0cf[i].rows, 64)); + mtsdram(mem_mb0cf, mb0cf[i].reg); + mtsdram(mem_sdtr1, sdtr1); + mtsdram(mem_rtr, compute_rtr(speed, mb0cf[i].rows, 64)); udelay(200); @@ -203,7 +203,7 @@ void sdram_init(void) * Set DC_EN to '1' and BRD_PRF to '01' for 16 byte PLB Burst * read/prefetch. */ - mtsdram0(mem_mcopt1, 0x80800000); + mtsdram(mem_mcopt1, 0x80800000); udelay(10000); @@ -215,10 +215,21 @@ void sdram_init(void) #ifdef CONFIG_SDRAM_BANK1 u32 b1cr = mb0cf[i].size | mb0cf[i].reg; - mtsdram0(mem_mcopt1, 0x00000000); - mtsdram0(mem_mb1cf, b1cr); /* SDRAM0_B1CR */ - mtsdram0(mem_mcopt1, 0x80800000); + mtsdram(mem_mcopt1, 0x00000000); + mtsdram(mem_mb1cf, b1cr); /* SDRAM0_B1CR */ + mtsdram(mem_mcopt1, 0x80800000); udelay(10000); + + /* + * Check if 2nd bank is really available. + * If the size not equal to the size of the first + * bank, then disable the 2nd bank completely. + */ + if (get_ram_size((long *)mb0cf[i].size, mb0cf[i].size) != + mb0cf[i].size) { + mtsdram(mem_mb1cf, 0); + mtsdram(mem_mcopt1, 0); + } #endif return; } diff --git a/cpu/ppc4xx/sdram.h b/cpu/ppc4xx/sdram.h index 62b5442f3..4fb9b1ae1 100644 --- a/cpu/ppc4xx/sdram.h +++ b/cpu/ppc4xx/sdram.h @@ -29,8 +29,6 @@ #include -#define mtsdram0(reg, data) mtdcr(memcfga,reg);mtdcr(memcfgd,data) - #define ONE_BILLION 1000000000 struct sdram_conf_s { diff --git a/cpu/ppc4xx/start.S b/cpu/ppc4xx/start.S index 18d344560..9626b65c8 100644 --- a/cpu/ppc4xx/start.S +++ b/cpu/ppc4xx/start.S @@ -1869,38 +1869,7 @@ ppc405ep_init: ori r3,r3,CFG_EBC_PB4CR@l mtdcr ebccfgd,r3 #endif -#ifdef CONFIG_TAIHU - mfdcr r4, CPC0_BOOT - andi. r5, r4, CPC0_BOOT_SEP@l - bne strap_0 /* serial eeprom present */ -#endif -#ifndef CFG_CPC0_PCI - li r3,CPC0_PCI_HOST_CFG_EN -#ifdef CONFIG_BUBINGA - /* - !----------------------------------------------------------------------- - ! Check FPGA for PCI internal/external arbitration - ! If board is set to internal arbitration, update cpc0_pci - !----------------------------------------------------------------------- - */ - addis r5,r0,FPGA_REG1@h /* set offset for FPGA_REG1 */ - ori r5,r5,FPGA_REG1@l - lbz r5,0x0(r5) /* read to get PCI arb selection */ - andi. r6,r5,FPGA_REG1_PCI_INT_ARB /* using internal arbiter ?*/ - beq ..pci_cfg_set /* if not set, then bypass reg write*/ -#endif - ori r3,r3,CPC0_PCI_ARBIT_EN -#ifdef CONFIG_TAIHU - ori r3,r3,CPC0_PCI_SPE -#endif -#else /* CFG_CPC0_PCI */ - li r3,CFG_CPC0_PCI -#endif /* CFG_CPC0_PCI */ -..pci_cfg_set: - mtdcr CPC0_PCI, r3 /* Enable internal arbiter*/ - -strap_0: /* !----------------------------------------------------------------------- ! Check to see if chip is in bypass mode. @@ -1966,6 +1935,21 @@ strap_0: bne _pci_66mhz #endif /* CONFIG_TAIHU */ +#if defined(CONFIG_ZEUS) + mfdcr r4, CPC0_BOOT + andi. r5, r4, CPC0_BOOT_SEP@l + bne strap_1 /* serial eeprom present */ + lis r3,0x0000 + addi r3,r3,0x3030 + lis r4,0x8042 + addi r4,r4,0x223e + b 1f +strap_1: + mfdcr r3, CPC0_PLLMR0 + mfdcr r4, CPC0_PLLMR1 + b 1f +#endif + addis r3,0,PLLMR0_DEFAULT@h /* PLLMR0 default value */ ori r3,r3,PLLMR0_DEFAULT@l /* */ addis r4,0,PLLMR1_DEFAULT@h /* PLLMR1 default value */ @@ -1982,9 +1966,9 @@ _pci_66mhz: strap_1: mfdcr r3, CPC0_PLLMR0 mfdcr r4, CPC0_PLLMR1 -1: #endif /* CONFIG_TAIHU */ +1: b pll_write /* Write the CPC0_PLLMR with new value */ pll_done: diff --git a/doc/README.zeus b/doc/README.zeus new file mode 100644 index 000000000..1848d8cd3 --- /dev/null +++ b/doc/README.zeus @@ -0,0 +1,73 @@ + +Storage of the board specific values (ethaddr...) +------------------------------------------------- + +The board specific environment variables that should be unique +for each individual board, can be stored in the I2C EEPROM. This +will be done from offset 0x80 with the length of 0x80 bytes. The +following command can be used to store the values here: + +=> setdef de:20:6a:ed:e2:72 de:20:6a:ed:e2:73 AB0001 + + ethaddr eth1addr serial# + +Now those 3 values are stored into the I2C EEPROM. A CRC is added +to make sure that the values get not corrupted. + + +SW-Reset Pushbutton handling: +----------------------------- + +The SW-reset push button is connected to a GPIO input too. This +way U-Boot can "see" how long the SW-reset was pressed, and a +specific action can be taken. Two different actions are supported: + +a) Release after more than 5 seconds and less then 10 seconds: + -> Run POST + + Please note, that the POST test will take a while (approx. 1 min + on the 128MByte board). This is mainly due to the system memory + test. + +b) Release after more than 10 seconds: + -> Restore factory default settings + + The factory default values are restored. The default environment + variables are restored (ipaddr, serverip...) and the board + specific values (ethaddr, eth1addr and serial#) are restored + to the environment from the I2C EEPROM. Also a bootline parameter + is added to the Linux bootline to signal the Linux kernel upon + the next startup, that the factory defaults should be restored. + +The command to check this sw-reset status and act accordingly is + +=> chkreset + +This command is added to the default "bootcmd", so that it is called +automatically upon startup. + +Also, the 2 LED's are used to indicate the current status of this +command (time passed since pushing the button). When the POST test +will be run, the green LED will be switched off, and when the +factory restore will be initiated, the reg LED will be switched off. + + +Loggin of POST results: +----------------------- + +The results of the POST tests are logged in a logbuffer located at the end +of the onboard memory. It can be accessed with the U-Boot command "log": + +=> log show +<4>POST memory PASSED +<4>POST cache PASSED +<4>POST cpu PASSED +<4>POST uart PASSED +<4>POST ethernet PASSED + +The DENX Linux kernel tree has support for this log buffer included. Exactly +this buffer is used for logging of all kernel messages too. By enabling the +compile time option "CONFIG_LOGBUFFER" this support is enabled. This way you +can access the U-Boot log messages from Linux too. + +2007-08-10, Stefan Roese diff --git a/include/configs/zeus.h b/include/configs/zeus.h new file mode 100644 index 000000000..86a16e77a --- /dev/null +++ b/include/configs/zeus.h @@ -0,0 +1,375 @@ +/* + * (C) Copyright 2007 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/************************************************************************ + * zeus.h - configuration for Zeus board + ***********************************************************************/ +#ifndef __CONFIG_H +#define __CONFIG_H + +/*----------------------------------------------------------------------- + * High Level Configuration Options + *----------------------------------------------------------------------*/ +#define CONFIG_ZEUS 1 /* Board is Zeus */ +#define CONFIG_4xx 1 /* ... PPC4xx family */ +#define CONFIG_405EP 1 /* Specifc 405EP support*/ + +#define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */ + +#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ +#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */ + +#define PLLMR0_DEFAULT PLLMR0_333_111_55_111 +#define PLLMR1_DEFAULT PLLMR1_333_111_55_111 + +#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ + +#define CONFIG_OVERWRITE_ETHADDR_ONCE 1 + +#define CONFIG_MII 1 /* MII PHY management */ +#define CONFIG_PHY_ADDR 0x01 /* PHY address */ +#define CONFIG_HAS_ETH1 1 +#define CONFIG_PHY1_ADDR 0x11 /* EMAC1 PHY address */ +#define CONFIG_NET_MULTI 1 +#define CFG_RX_ETH_BUFFER 16 /* Number of ethernet rx buffers & descriptors */ +#define CONFIG_PHY_RESET 1 +#define CONFIG_PHY_RESET_DELAY 300 /* PHY RESET recovery delay */ + +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ + CFG_CMD_ASKENV | \ + CFG_CMD_CACHE | \ + CFG_CMD_DHCP | \ + CFG_CMD_DIAG | \ + CFG_CMD_EEPROM | \ + CFG_CMD_ELF | \ + CFG_CMD_I2C | \ + CFG_CMD_IRQ | \ + CFG_CMD_LOG | \ + CFG_CMD_MII | \ + CFG_CMD_NET | \ + CFG_CMD_NFS | \ + CFG_CMD_PING | \ + CFG_CMD_REGINFO) + +/* POST support */ +#define CONFIG_POST (CFG_POST_MEMORY | \ + CFG_POST_CPU | \ + CFG_POST_CACHE | \ + CFG_POST_UART | \ + CFG_POST_ETHER) + +#define CFG_POST_ETHER_EXT_LOOPBACK /* eth POST using ext loopack connector */ + +/* Define here the base-addresses of the UARTs to test in POST */ +#define CFG_POST_UART_TABLE {UART0_BASE} + +#define CONFIG_LOGBUFFER +#define CFG_POST_CACHE_ADDR 0x00800000 /* free virtual address */ + +#define CFG_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */ + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +/*----------------------------------------------------------------------- + * SDRAM + *----------------------------------------------------------------------*/ +/* + * SDRAM configuration (please see cpu/ppc/sdram.[ch]) + */ +#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ +#define CONFIG_SDRAM_BANK1 1 /* init onboard SDRAM bank 1 */ + +/* SDRAM timings used in datasheet */ +#define CFG_SDRAM_CL 3 /* CAS latency */ +#define CFG_SDRAM_tRP 20 /* PRECHARGE command period */ +#define CFG_SDRAM_tRC 66 /* ACTIVE-to-ACTIVE command period */ +#define CFG_SDRAM_tRCD 20 /* ACTIVE-to-READ delay */ +#define CFG_SDRAM_tRFC 66 /* Auto refresh period */ + +/*----------------------------------------------------------------------- + * Serial Port + *----------------------------------------------------------------------*/ +#undef CFG_EXT_SERIAL_CLOCK /* external serial clock */ +#define CFG_BASE_BAUD 691200 +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SERIAL_MULTI + +/* The following table includes the supported baudrates */ +#define CFG_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400} + +/*----------------------------------------------------------------------- + * Miscellaneous configurable options + *----------------------------------------------------------------------*/ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ +#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ + +#define CFG_LOAD_ADDR 0x100000 /* default load address */ +#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ +#define CONFIG_LOOPW 1 /* enable loopw command */ +#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */ +#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ +#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ + +/*----------------------------------------------------------------------- + * I2C + *----------------------------------------------------------------------*/ +#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ +#undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CFG_I2C_SLAVE 0x7F + +/* these are for the ST M24C02 2kbit serial i2c eeprom */ +#define CFG_I2C_EEPROM_ADDR 0x50 /* base address */ +#define CFG_I2C_EEPROM_ADDR_LEN 1 /* bytes of address */ +/* mask of address bits that overflow into the "EEPROM chip address" */ +#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07 + +#define CFG_EEPROM_PAGE_WRITE_ENABLE 1 /* write eeprom in pages */ +#define CFG_EEPROM_PAGE_WRITE_BITS 3 /* 8 byte write page size */ +#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ + +/* + * The layout of the I2C EEPROM, used for bootstrap setup and for board- + * specific values, like ethaddr... that can be restored via the sw-reset + * button + */ +#define FACTORY_RESET_I2C_EEPROM 0x50 +#define FACTORY_RESET_ENV_OFFS 0x80 +#define FACTORY_RESET_ENV_SIZE 0x80 + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + */ +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_FLASH_BASE 0xFF000000 +#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */ +#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */ +#define CFG_MONITOR_BASE (-CFG_MONITOR_LEN) + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/*----------------------------------------------------------------------- + * FLASH organization + */ +#define CFG_FLASH_CFI /* The flash is CFI compatible */ +#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */ + +#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE } + +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 512 /* max number of sectors on one chip */ + +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ + +#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ +#define CFG_FLASH_PROTECTION 1 /* use hardware flash protection */ + +#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ +#define CFG_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */ + +#ifdef CFG_ENV_IS_IN_FLASH +#define CFG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */ +#define CFG_ENV_ADDR ((-CFG_MONITOR_LEN)-CFG_ENV_SECT_SIZE) +#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */ + +/* Address and size of Redundant Environment Sector */ +#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE) +#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) +#endif + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_DCACHE_SIZE 16384 /* For IBM 405EP CPU */ +#define CFG_CACHELINE_SIZE 32 /* ... */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area (in data cache) + */ +/* use on chip memory (OCM) for temperary stack until sdram is tested */ +#define CFG_TEMP_STACK_OCM 1 + +/* On Chip Memory location */ +#define CFG_OCM_DATA_ADDR 0xF8000000 +#define CFG_OCM_DATA_SIZE 0x1000 +#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of OCM */ +#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM */ + +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +/* reserve some memory for POST and BOOT limit info */ +#define CFG_INIT_SP_OFFSET (CFG_GBL_DATA_OFFSET - 16) + +/* extra data in OCM */ +#define CFG_POST_WORD_ADDR (CFG_GBL_DATA_OFFSET - 4) +#define CFG_POST_MAGIC (CFG_OCM_DATA_ADDR + CFG_GBL_DATA_OFFSET - 8) +#define CFG_POST_VAL (CFG_OCM_DATA_ADDR + CFG_GBL_DATA_OFFSET - 12) + +/*----------------------------------------------------------------------- + * External Bus Controller (EBC) Setup + */ + +/* Memory Bank 0 (Flash 16M) initialization */ +#define CFG_EBC_PB0AP 0x05815600 +#define CFG_EBC_PB0CR 0xFF09A000 /* BAS=0xFF0,BS=16MB,BU=R/W,BW=16bit */ + +/*----------------------------------------------------------------------- + * Definitions for GPIO setup (PPC405EP specific) + * + * GPIO0[0] - External Bus Controller BLAST output + * GPIO0[1-9] - Instruction trace outputs + * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs + * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs + * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs + * GPIO0[24-27] - UART0 control signal inputs/outputs + * GPIO0[28-29] - UART1 data signal input/output + * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs + */ +#define CFG_GPIO0_OSRH 0x15555550 /* Chip selects */ +#define CFG_GPIO0_OSRL 0x00000110 /* UART_DTR-pin 27 alt out */ +#define CFG_GPIO0_ISR1H 0x10000041 /* Pin 2, 12 is input */ +#define CFG_GPIO0_ISR1L 0x15505440 /* OUT: LEDs 22/23; IN: pin12,2, NVALID# */ +#define CFG_GPIO0_TSRH 0x00000000 +#define CFG_GPIO0_TSRL 0x00000000 +#define CFG_GPIO0_TCR 0xBFF68317 /* 3-state OUT: 22/23/29; 12,2 is not 3-state */ +#define CFG_GPIO0_ODR 0x00000000 + +#define CFG_GPIO_SW_RESET 1 +#define CFG_GPIO_ZEUS_PE 12 +#define CFG_GPIO_LED_RED 22 +#define CFG_GPIO_LED_GREEN 23 + +/* Time in milli-seconds */ +#define CFG_TIME_POST 5000 +#define CFG_TIME_FACTORY_RESET 10000 + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif + +/* ENVIRONMENT VARS */ + +#define CONFIG_PREBOOT "echo;echo Welcome to Bulletendpoints board v1.1;echo" +#define CONFIG_IPADDR 192.168.1.10 +#define CONFIG_SERVERIP 192.168.1.100 +#define CONFIG_GATEWAYIP 192.168.1.100 +#define CONFIG_ETHADDR 50:00:00:00:06:00 +#define CONFIG_ETH1ADDR 50:00:00:00:06:01 +#if 0 +#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ +#else +#define CONFIG_BOOTDELAY 3 /* autoboot after 5 seconds */ +#endif + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "logversion=2\0" \ + "hostname=zeus\0" \ + "netdev=eth0\0" \ + "ethact=ppc_4xx_eth0\0" \ + "netmask=255.255.255.0\0" \ + "ramdisk_size=50000\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw" \ + " nfsroot=${serverip}:${rootpath}\0" \ + "ramargs=setenv bootargs root=/dev/ram rw" \ + " ramdisk=${ramdisk_size}\0" \ + "addip=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:${netdev}:off panic=1\0" \ + "addtty=setenv bootargs ${bootargs} console=ttyS0," \ + "${baudrate}\0" \ + "net_nfs=tftp ${kernel_mem_addr} ${file_kernel};" \ + "run nfsargs addip addtty;bootm\0" \ + "net_ram=tftp ${kernel_mem_addr} ${file_kernel};" \ + "tftp ${ramdisk_mem_addr} ${file_fs};" \ + "run ramargs addip addtty;" \ + "bootm ${kernel_mem_addr} ${ramdisk_mem_addr}\0" \ + "rootpath=/target_fs/zeus\0" \ + "kernel_fl_addr=ff000000\0" \ + "kernel_mem_addr=200000\0" \ + "ramdisk_fl_addr=ff300000\0" \ + "ramdisk_mem_addr=4000000\0" \ + "uboot_fl_addr=fffc0000\0" \ + "uboot_mem_addr=100000\0" \ + "file_uboot=/zeus/u-boot.bin\0" \ + "tftp_uboot=tftp 100000 ${file_uboot}\0" \ + "update_uboot=protect off fffc0000 ffffffff;" \ + "era fffc0000 ffffffff;cp.b 100000 fffc0000 40000;" \ + "protect on fffc0000 ffffffff\0" \ + "upd_uboot=run tftp_uboot;run update_uboot\0" \ + "file_kernel=/zeus/uImage_ba\0" \ + "tftp_kernel=tftp 100000 ${file_kernel}\0" \ + "update_kernel=protect off ff000000 ff17ffff;" \ + "era ff000000 ff17ffff;cp.b 100000 ff000000 180000\0" \ + "upd_kernel=run tftp_kernel;run update_kernel\0" \ + "file_fs=/zeus/rootfs_ba.img\0" \ + "tftp_fs=tftp 100000 ${file_fs}\0" \ + "update_fs=protect off ff300000 ff87ffff;era ff300000 ff87ffff;"\ + "cp.b 100000 ff300000 580000\0" \ + "upd_fs=run tftp_fs;run update_fs\0" \ + "bootcmd=chkreset;run ramargs addip addtty addmisc;" \ + "bootm ${kernel_fl_addr} ${ramdisk_fl_addr}\0" \ + "" + +#endif /* __CONFIG_H */ diff --git a/include/ppc405.h b/include/ppc405.h index 8e6473192..4fc52833d 100644 --- a/include/ppc405.h +++ b/include/ppc405.h @@ -541,6 +541,18 @@ #define PLLMR1_266_66_33_33 (PLL_FBKDIV_8 | \ PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \ PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW) +#define PLLMR0_333_111_55_37 (PLL_CPUDIV_1 | PLL_PLBDIV_3 | \ + PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 | \ + PLL_MALDIV_1 | PLL_PCIDIV_3) +#define PLLMR1_333_111_55_37 (PLL_FBKDIV_10 | \ + PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \ + PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI) +#define PLLMR0_333_111_55_111 (PLL_CPUDIV_1 | PLL_PLBDIV_3 | \ + PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 | \ + PLL_MALDIV_1 | PLL_PCIDIV_1) +#define PLLMR1_333_111_55_111 (PLL_FBKDIV_10 | \ + PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \ + PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI) /* * PLL Voltage Controlled Oscillator (VCO) definitions @@ -1226,6 +1238,8 @@ #define mtebc(reg, data) mtdcr(ebccfga,reg);mtdcr(ebccfgd,data) #define mfebc(reg, data) mtdcr(ebccfga,reg);data = mfdcr(ebccfgd) +#define mtsdram(reg, data) do { mtdcr(memcfga,reg);mtdcr(memcfgd,data); } while (0) +#define mfsdram(reg, data) do { mtdcr(memcfga,reg);data = mfdcr(memcfgd); } while (0) #ifndef __ASSEMBLY__ From 429d9571f60631ae8a2fe12b11be4c75b0c2b37c Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Tue, 14 Aug 2007 15:03:17 +0200 Subject: [PATCH 115/259] Coding style cleanup Signed-off-by: Stefan Roese --- cpu/ppc4xx/serial.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/cpu/ppc4xx/serial.c b/cpu/ppc4xx/serial.c index a75e5eebb..376ca1e5b 100644 --- a/cpu/ppc4xx/serial.c +++ b/cpu/ppc4xx/serial.c @@ -456,8 +456,8 @@ static void serial_divs (int baudrate, unsigned long *pudiv, get_sys_info(&sysinfo); - plloutb = ((CONFIG_SYS_CLK_FREQ * ((cpr_pllc & PLLC_SRC_MASK) ? - sysinfo.pllFwdDivB : sysinfo.pllFwdDiv) * sysinfo.pllFbkDiv) / + plloutb = ((CONFIG_SYS_CLK_FREQ * ((cpr_pllc & PLLC_SRC_MASK) ? + sysinfo.pllFwdDivB : sysinfo.pllFwdDiv) * sysinfo.pllFbkDiv) / sysinfo.pllFwdDivB); udiv = 256; /* Assume lowest possible serial clk */ div = plloutb / (16 * baudrate); /* total divisor */ From 4ce846ec59f36b85d6644a769690ad3feb667575 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Tue, 14 Aug 2007 15:12:01 +0200 Subject: [PATCH 116/259] POST: Fix merge problem Signed-off-by: Stefan Roese --- post/cpu/ppc4xx/uart.c | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/post/cpu/ppc4xx/uart.c b/post/cpu/ppc4xx/uart.c index 5f14967fe..7c3ed402c 100644 --- a/post/cpu/ppc4xx/uart.c +++ b/post/cpu/ppc4xx/uart.c @@ -137,7 +137,7 @@ DECLARE_GLOBAL_DATA_PTR; -<<<<<<< master +#if defined(CONFIG_440) #if !defined(CFG_EXT_SERIAL_CLOCK) static void serial_divs (int baudrate, unsigned long *pudiv, unsigned short *pbdiv) @@ -181,9 +181,6 @@ static void serial_divs (int baudrate, unsigned long *pudiv, } #endif -======= -#if defined(CONFIG_440) ->>>>>>> zeus static int uart_post_init (unsigned long dev_base) { unsigned long reg; From e54b970173769307a116bd34028b6d0c2eea2a4e Mon Sep 17 00:00:00 2001 From: Peter Pearse Date: Tue, 14 Aug 2007 15:40:00 +0100 Subject: [PATCH 117/259] Supply spi interface in at45.c --- drivers/at45.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/at45.c b/drivers/at45.c index 4c12ca7a3..7d35695b1 100755 --- a/drivers/at45.c +++ b/drivers/at45.c @@ -24,6 +24,11 @@ #ifdef CONFIG_HAS_DATAFLASH #include +/* + * spi.c API + */ +extern unsigned int AT91F_SpiWrite (AT91PS_DataflashDesc pDesc); +extern void AT91F_SpiEnable(int cs); #define AT91C_TIMEOUT_WRDY 200000 From 073e1b509980cefe6f53c2d7fbbcd135df1e3924 Mon Sep 17 00:00:00 2001 From: Andy Fleming Date: Tue, 14 Aug 2007 10:32:59 -0500 Subject: [PATCH 118/259] Fix initrd/dtb interaction The original code would wrongly relocate the blob to be right before the initrd if it existed. The blob *must* be within CFG_BOOTMAPSZ, if it is defined. So we make two changes: 1) flag the blob for relocation whenever its address is above BOOTMAPSZ 2) If the blob is being relocated, relocate it before kbd, not initrd Signed-off-by: Andy Fleming --- common/cmd_bootm.c | 23 ++++++++++++++--------- 1 file changed, 14 insertions(+), 9 deletions(-) diff --git a/common/cmd_bootm.c b/common/cmd_bootm.c index e19f83e48..8249dceb4 100644 --- a/common/cmd_bootm.c +++ b/common/cmd_bootm.c @@ -924,6 +924,15 @@ do_bootm_linux (cmd_tbl_t *cmdtp, int flag, initrd_end = 0; } +#ifdef CFG_BOOTMAPSZ + /* + * The blob must be within CFG_BOOTMAPSZ, + * so we flag it to be copied if it is + */ + if (of_flat_tree >= (char *)CFG_BOOTMAPSZ) + of_data = of_flat_tree; +#endif + #if defined(CONFIG_OF_LIBFDT) /* move of_flat_tree if needed */ if (of_data) { @@ -931,11 +940,9 @@ do_bootm_linux (cmd_tbl_t *cmdtp, int flag, ulong of_start, of_len; of_len = be32_to_cpu(fdt_totalsize(of_data)); - /* position on a 4K boundary before the initrd/kbd */ - if (initrd_start) - of_start = initrd_start - of_len; - else - of_start = (ulong)kbd - of_len; + + /* position on a 4K boundary before the kbd */ + of_start = (ulong)kbd - of_len; of_start &= ~(4096 - 1); /* align on page */ debug ("## device tree at 0x%08lX ... 0x%08lX (len=%ld=0x%lX)\n", of_data, of_data + of_len - 1, of_len, of_len); @@ -983,11 +990,9 @@ do_bootm_linux (cmd_tbl_t *cmdtp, int flag, if (of_data) { ulong of_start, of_len; of_len = ((struct boot_param_header *)of_data)->totalsize; + /* provide extra 8k pad */ - if (initrd_start) - of_start = initrd_start - of_len - 8192; - else - of_start = (ulong)kbd - of_len - 8192; + of_start = (ulong)kbd - of_len - 8192; of_start &= ~(4096 - 1); /* align on page */ debug ("## device tree at 0x%08lX ... 0x%08lX (len=%ld=0x%lX)\n", of_data, of_data + of_len - 1, of_len, of_len); From f01dbb5424a81453c81190dd30e945891466f621 Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Tue, 14 Aug 2007 18:42:36 +0200 Subject: [PATCH 119/259] Coding style cleanup. Update CHANGELOG. Signed-off-by: Wolfgang Denk --- CHANGELOG | 68 ++++++++++++++++++ board/at91rm9200dk/mux.c | 10 ++- cpu/arm920t/at91rm9200/spi.c | 2 - drivers/at45.c | 133 +++++++++++++++++------------------ drivers/dataflash.c | 50 ++++++------- include/at45.h | 2 +- include/dataflash.h | 2 +- include/led.h | 3 +- 8 files changed, 165 insertions(+), 105 deletions(-) diff --git a/CHANGELOG b/CHANGELOG index 5472c8fe5..a83456814 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -1,3 +1,71 @@ +commit 073e1b509980cefe6f53c2d7fbbcd135df1e3924 +Author: Andy Fleming +Date: Tue Aug 14 10:32:59 2007 -0500 + + Fix initrd/dtb interaction + + The original code would wrongly relocate the blob to be right before + the initrd if it existed. The blob *must* be within CFG_BOOTMAPSZ, + if it is defined. So we make two changes: + + 1) flag the blob for relocation whenever its address is above BOOTMAPSZ + + 2) If the blob is being relocated, relocate it before kbd, not initrd + + Signed-off-by: Andy Fleming + +commit e54b970173769307a116bd34028b6d0c2eea2a4e +Author: Peter Pearse +Date: Tue Aug 14 15:40:00 2007 +0100 + + Supply spi interface in at45.c + +commit 0c42f36f15074bd9808a7dbd7ef611fad9bf537c +Author: Peter Pearse +Date: Tue Aug 14 10:46:32 2007 +0100 + + Replace lost end of at45.c. + +commit 65d7ada64557e76094b4fd3bad30a0f18f5fb2b2 +Author: Peter Pearse +Date: Tue Aug 14 10:30:06 2007 +0100 + + Update Makefiles for merged and split at45.c. + +commit 3454cece2db57cb9eb7087995f7e73066a163f71 +Author: Peter Pearse +Date: Tue Aug 14 10:21:06 2007 +0100 + + Delete the merged files. + +commit dcbfd2e5649f97aa04fbbc6ea2b008aa4486e225 +Author: Peter Pearse +Date: Tue Aug 14 10:14:05 2007 +0100 + + Add the files. + +commit d4fc6012fd0a5c211b825691f44b06f8032c0551 +Author: Peter Pearse +Date: Tue Aug 14 10:10:52 2007 +0100 + + Add MACH_TYPE records for several AT91 boards. + Merge to two at45.c files into a common file, split to at45.c and spi.c + Fix spelling error in DM9161 PHY Support. + Initialize at91rm9200 board (and set LED). + Add PIO control for at91rm9200dk LEDs and Mux. + Change dataflash partition boundaries to be compatible with Linux 2.6. + + Signed-off-by: Peter Pearse + Signed-off-by: Ulf Samuelsson + +commit 4ef35e53c693556c54b0c22d6f873de87bade253 +Author: Wolfgang Denk +Date: Tue Aug 14 09:54:46 2007 +0200 + + Coding style cleanup, update CHANGELOG + + Signed-off-by: Wolfgang Denk + commit 85eb5caf6b906f7ec5b54814e8c7c74f55986bb7 Author: Wolfgang Denk Date: Tue Aug 14 09:47:27 2007 +0200 diff --git a/board/at91rm9200dk/mux.c b/board/at91rm9200dk/mux.c index d573923c1..767d28090 100644 --- a/board/at91rm9200dk/mux.c +++ b/board/at91rm9200dk/mux.c @@ -23,8 +23,8 @@ void AT91F_SelectMMC(void) { AT91C_BASE_PIOB->PIO_PER = DATAFLASH_MMC_SELECT; /* Set in PIO mode */ AT91C_BASE_PIOB->PIO_OER = DATAFLASH_MMC_SELECT; /* Configure in output */ /* Set Output */ - AT91C_BASE_PIOB->PIO_SODR = DATAFLASH_MMC_SELECT; -#endif + AT91C_BASE_PIOB->PIO_SODR = DATAFLASH_MMC_SELECT; +#endif } void AT91F_SelectSPI(void) { @@ -32,8 +32,6 @@ void AT91F_SelectSPI(void) { AT91C_BASE_PIOB->PIO_PER = DATAFLASH_MMC_SELECT; /* Set in PIO mode */ AT91C_BASE_PIOB->PIO_OER = DATAFLASH_MMC_SELECT; /* Configure in output */ /* Clear Output */ - AT91C_BASE_PIOB->PIO_CODR = DATAFLASH_MMC_SELECT; -#endif + AT91C_BASE_PIOB->PIO_CODR = DATAFLASH_MMC_SELECT; +#endif } - - diff --git a/cpu/arm920t/at91rm9200/spi.c b/cpu/arm920t/at91rm9200/spi.c index 7469e5382..265d18525 100644 --- a/cpu/arm920t/at91rm9200/spi.c +++ b/cpu/arm920t/at91rm9200/spi.c @@ -148,6 +148,4 @@ unsigned int AT91F_SpiWrite ( AT91PS_DataflashDesc pDesc ) return DATAFLASH_OK; } - #endif - diff --git a/drivers/at45.c b/drivers/at45.c index 7d35695b1..507ff36d4 100755 --- a/drivers/at45.c +++ b/drivers/at45.c @@ -36,7 +36,7 @@ extern void AT91F_SpiEnable(int cs); /*----------------------------------------------------------------------*/ /* \fn AT91F_DataFlashSendCommand */ /* \brief Generic function to send a command to the dataflash */ -/*----------------------------------------------------------------------*/ +/*----------------------------------------------------------------------*/ AT91S_DataFlashStatus AT91F_DataFlashSendCommand( AT91PS_DataFlash pDataFlash, unsigned char OpCode, @@ -49,27 +49,27 @@ AT91S_DataFlashStatus AT91F_DataFlashSendCommand( return DATAFLASH_BUSY; /* process the address to obtain page address and byte address */ - adr = ((DataflashAddress / (pDataFlash->pDevice->pages_size)) << - pDataFlash->pDevice->page_offset) + (DataflashAddress % + adr = ((DataflashAddress / (pDataFlash->pDevice->pages_size)) << + pDataFlash->pDevice->page_offset) + (DataflashAddress % (pDataFlash->pDevice->pages_size)); /* fill the command buffer */ pDataFlash->pDataFlashDesc->command[0] = OpCode; if (pDataFlash->pDevice->pages_number >= 16384) { - pDataFlash->pDataFlashDesc->command[1] = + pDataFlash->pDataFlashDesc->command[1] = (unsigned char)((adr & 0x0F000000) >> 24); - pDataFlash->pDataFlashDesc->command[2] = + pDataFlash->pDataFlashDesc->command[2] = (unsigned char)((adr & 0x00FF0000) >> 16); - pDataFlash->pDataFlashDesc->command[3] = + pDataFlash->pDataFlashDesc->command[3] = (unsigned char)((adr & 0x0000FF00) >> 8); - pDataFlash->pDataFlashDesc->command[4] = + pDataFlash->pDataFlashDesc->command[4] = (unsigned char)(adr & 0x000000FF); } else { - pDataFlash->pDataFlashDesc->command[1] = + pDataFlash->pDataFlashDesc->command[1] = (unsigned char)((adr & 0x00FF0000) >> 16); - pDataFlash->pDataFlashDesc->command[2] = + pDataFlash->pDataFlashDesc->command[2] = (unsigned char)((adr & 0x0000FF00) >> 8); - pDataFlash->pDataFlashDesc->command[3] = + pDataFlash->pDataFlashDesc->command[3] = (unsigned char)(adr & 0x000000FF); pDataFlash->pDataFlashDesc->command[4] = 0; } @@ -78,10 +78,10 @@ AT91S_DataFlashStatus AT91F_DataFlashSendCommand( pDataFlash->pDataFlashDesc->command[7] = 0; /* Initialize the SpiData structure for the spi write fuction */ - pDataFlash->pDataFlashDesc->tx_cmd_pt = + pDataFlash->pDataFlashDesc->tx_cmd_pt = pDataFlash->pDataFlashDesc->command; pDataFlash->pDataFlashDesc->tx_cmd_size = CmdSize; - pDataFlash->pDataFlashDesc->rx_cmd_pt = + pDataFlash->pDataFlashDesc->rx_cmd_pt = pDataFlash->pDataFlashDesc->command; pDataFlash->pDataFlashDesc->rx_cmd_size = CmdSize; @@ -92,8 +92,8 @@ AT91S_DataFlashStatus AT91F_DataFlashSendCommand( /*----------------------------------------------------------------------*/ /* \fn AT91F_DataFlashGetStatus */ /* \brief Read the status register of the dataflash */ -/*----------------------------------------------------------------------*/ -AT91S_DataFlashStatus AT91F_DataFlashGetStatus(AT91PS_DataflashDesc pDesc) +/*----------------------------------------------------------------------*/ +AT91S_DataFlashStatus AT91F_DataFlashGetStatus(AT91PS_DataflashDesc pDesc) { AT91S_DataFlashStatus status; @@ -123,16 +123,16 @@ AT91S_DataFlashStatus AT91F_DataFlashGetStatus(AT91PS_DataflashDesc pDesc) /*----------------------------------------------------------------------*/ /* \fn AT91F_DataFlashWaitReady */ /* \brief wait for dataflash ready (bit7 of the status register == 1) */ -/*----------------------------------------------------------------------*/ -AT91S_DataFlashStatus AT91F_DataFlashWaitReady(AT91PS_DataflashDesc -pDataFlashDesc, unsigned int timeout) +/*----------------------------------------------------------------------*/ +AT91S_DataFlashStatus AT91F_DataFlashWaitReady(AT91PS_DataflashDesc +pDataFlashDesc, unsigned int timeout) { pDataFlashDesc->DataFlash_state = IDLE; do { AT91F_DataFlashGetStatus(pDataFlashDesc); timeout--; - } while( ((pDataFlashDesc->DataFlash_state & 0x80) != 0x80) && + } while( ((pDataFlashDesc->DataFlash_state & 0x80) != 0x80) && (timeout > 0) ); if((pDataFlashDesc->DataFlash_state & 0x80) != 0x80) @@ -150,7 +150,7 @@ pDataFlashDesc, unsigned int timeout) /* : <*dataBuffer> = data buffer pointer */ /* : = data buffer size */ /* Return value : State of the dataflash */ -/*--------------------------------------------------------------------------*/ +/*--------------------------------------------------------------------------*/ AT91S_DataFlashStatus AT91F_DataFlashContinuousRead ( AT91PS_DataFlash pDataFlash, int src, @@ -159,8 +159,8 @@ AT91S_DataFlashStatus AT91F_DataFlashContinuousRead ( { AT91S_DataFlashStatus status; /* Test the size to read in the device */ - if ( (src + sizeToRead) > - (pDataFlash->pDevice->pages_size * + if ( (src + sizeToRead) > + (pDataFlash->pDevice->pages_size * (pDataFlash->pDevice->pages_number))) return DATAFLASH_MEMORY_OVERFLOW; @@ -169,7 +169,7 @@ AT91S_DataFlashStatus AT91F_DataFlashContinuousRead ( pDataFlash->pDataFlashDesc->tx_data_pt = dataBuffer; pDataFlash->pDataFlashDesc->tx_data_size = sizeToRead; - status = AT91F_DataFlashSendCommand + status = AT91F_DataFlashSendCommand (pDataFlash, DB_CONTINUOUS_ARRAY_READ, 8, src); /* Send the command to the dataflash */ return(status); @@ -184,7 +184,7 @@ AT91S_DataFlashStatus AT91F_DataFlashContinuousRead ( /* : = dataflash destination address */ /* : = data buffer size */ /* Return value : State of the dataflash */ -/*---------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ AT91S_DataFlashStatus AT91F_DataFlashPagePgmBuf( AT91PS_DataFlash pDataFlash, unsigned char *src, @@ -201,7 +201,7 @@ AT91S_DataFlashStatus AT91F_DataFlashPagePgmBuf( /* Send the command to the dataflash */ if (pDataFlash->pDevice->pages_number >= 16384) cmdsize = 5; - return(AT91F_DataFlashSendCommand (pDataFlash, DB_PAGE_PGM_BUF1, + return(AT91F_DataFlashSendCommand (pDataFlash, DB_PAGE_PGM_BUF1, cmdsize, dest)); } @@ -212,7 +212,7 @@ cmdsize, dest)); } /* : Page concerned */ /* : */ /* Return value : State of the dataflash */ -/*---------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ AT91S_DataFlashStatus AT91F_MainMemoryToBufferTransfert( AT91PS_DataFlash pDataFlash, unsigned char BufferCommand, @@ -220,7 +220,7 @@ AT91S_DataFlashStatus AT91F_MainMemoryToBufferTransfert( { int cmdsize; /* Test if the buffer command is legal */ - if ((BufferCommand != DB_PAGE_2_BUF1_TRF) + if ((BufferCommand != DB_PAGE_2_BUF1_TRF) && (BufferCommand != DB_PAGE_2_BUF2_TRF)) return DATAFLASH_BAD_COMMAND; @@ -229,7 +229,7 @@ AT91S_DataFlashStatus AT91F_MainMemoryToBufferTransfert( cmdsize = 4; if (pDataFlash->pDevice->pages_number >= 16384) cmdsize = 5; - return(AT91F_DataFlashSendCommand (pDataFlash, BufferCommand, cmdsize, + return(AT91F_DataFlashSendCommand (pDataFlash, BufferCommand, cmdsize, page*pDataFlash->pDevice->pages_size)); } @@ -253,7 +253,7 @@ AT91S_DataFlashStatus AT91F_DataFlashWriteBuffer ( { int cmdsize; /* Test if the buffer command is legal */ - if ((BufferCommand != DB_BUF1_WRITE) + if ((BufferCommand != DB_BUF1_WRITE) && (BufferCommand != DB_BUF2_WRITE)) return DATAFLASH_BAD_COMMAND; @@ -269,26 +269,26 @@ AT91S_DataFlashStatus AT91F_DataFlashWriteBuffer ( pDataFlash->pDataFlashDesc->command[1] = 0; if (pDataFlash->pDevice->pages_number >= 16384) { pDataFlash->pDataFlashDesc->command[2] = 0; - pDataFlash->pDataFlashDesc->command[3] = - (unsigned char)(((unsigned int)(bufferAddress & + pDataFlash->pDataFlashDesc->command[3] = + (unsigned char)(((unsigned int)(bufferAddress & pDataFlash->pDevice->byte_mask)) >> 8); - pDataFlash->pDataFlashDesc->command[4] = + pDataFlash->pDataFlashDesc->command[4] = (unsigned char)((unsigned int)bufferAddress & 0x00FF); cmdsize = 5; } else { - pDataFlash->pDataFlashDesc->command[2] = - (unsigned char)(((unsigned int)(bufferAddress & + pDataFlash->pDataFlashDesc->command[2] = + (unsigned char)(((unsigned int)(bufferAddress & pDataFlash->pDevice->byte_mask)) >> 8); - pDataFlash->pDataFlashDesc->command[3] = + pDataFlash->pDataFlashDesc->command[3] = (unsigned char)((unsigned int)bufferAddress & 0x00FF); pDataFlash->pDataFlashDesc->command[4] = 0; cmdsize = 4; } - pDataFlash->pDataFlashDesc->tx_cmd_pt = + pDataFlash->pDataFlashDesc->tx_cmd_pt = pDataFlash->pDataFlashDesc->command; pDataFlash->pDataFlashDesc->tx_cmd_size = cmdsize; - pDataFlash->pDataFlashDesc->rx_cmd_pt = + pDataFlash->pDataFlashDesc->rx_cmd_pt = pDataFlash->pDataFlashDesc->command; pDataFlash->pDataFlashDesc->rx_cmd_size = cmdsize; @@ -320,7 +320,7 @@ AT91S_DataFlashStatus AT91F_PageErase( cmdsize = 4; if (pDataFlash->pDevice->pages_number >= 16384) cmdsize = 5; - return(AT91F_DataFlashSendCommand (pDataFlash, DB_PAGE_ERASE, cmdsize, + return(AT91F_DataFlashSendCommand (pDataFlash, DB_PAGE_ERASE, cmdsize, page*pDataFlash->pDevice->pages_size)); } @@ -332,7 +332,7 @@ page*pDataFlash->pDevice->pages_size)); /* : Page concerned */ /* : */ /* Return value : State of the dataflash */ -/*---------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ AT91S_DataFlashStatus AT91F_BlockErase( AT91PS_DataFlash pDataFlash, unsigned int block) @@ -344,7 +344,7 @@ AT91S_DataFlashStatus AT91F_BlockErase( cmdsize = 4; if (pDataFlash->pDevice->pages_number >= 16384) cmdsize = 5; - return(AT91F_DataFlashSendCommand (pDataFlash, DB_BLOCK_ERASE,cmdsize, + return(AT91F_DataFlashSendCommand (pDataFlash, DB_BLOCK_ERASE,cmdsize, block*8*pDataFlash->pDevice->pages_size)); } @@ -355,7 +355,7 @@ block*8*pDataFlash->pDevice->pages_size)); /* : = command to send to buffer1 or buffer2 */ /* : = main memory address */ /* Return value : State of the dataflash */ -/*---------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ AT91S_DataFlashStatus AT91F_WriteBufferToMain ( AT91PS_DataFlash pDataFlash, unsigned char BufferCommand, @@ -386,7 +386,7 @@ AT91S_DataFlashStatus AT91F_WriteBufferToMain ( /* Input Parameters : = page number */ /* : = adr to begin the fading */ /* : = Number of bytes to erase */ -/*---------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ AT91S_DataFlashStatus AT91F_PartialPageWrite ( AT91PS_DataFlash pDataFlash, unsigned char *src, @@ -400,27 +400,27 @@ AT91S_DataFlashStatus AT91F_PartialPageWrite ( AdrInPage = dest % (pDataFlash->pDevice->pages_size); /* Read the contents of the page in the Sram Buffer */ - AT91F_MainMemoryToBufferTransfert(pDataFlash, + AT91F_MainMemoryToBufferTransfert(pDataFlash, DB_PAGE_2_BUF1_TRF, page); - AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, + AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY); /*Update the SRAM buffer */ - AT91F_DataFlashWriteBuffer(pDataFlash, DB_BUF1_WRITE, src, + AT91F_DataFlashWriteBuffer(pDataFlash, DB_BUF1_WRITE, src, AdrInPage, size); - AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, + AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY); /* Erase page if a 128 Mbits device */ if (pDataFlash->pDevice->pages_number >= 16384) { AT91F_PageErase(pDataFlash, page); /* Rewrite the modified Sram Buffer in the main memory */ - AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, + AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY); } /* Rewrite the modified Sram Buffer in the main memory */ - return(AT91F_WriteBufferToMain(pDataFlash, DB_BUF1_PAGE_ERASE_PGM, + return(AT91F_WriteBufferToMain(pDataFlash, DB_BUF1_PAGE_ERASE_PGM, (page*pDataFlash->pDevice->pages_size))); } @@ -430,7 +430,7 @@ AT91S_DataFlashStatus AT91F_PartialPageWrite ( /* Input Parameters : <*src> = Source buffer */ /* : = dataflash adress */ /* : = data buffer size */ -/*---------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ AT91S_DataFlashStatus AT91F_DataFlashWrite( AT91PS_DataFlash pDataFlash, unsigned char *src, @@ -443,15 +443,15 @@ AT91S_DataFlashStatus AT91F_DataFlashWrite( AT91F_SpiEnable(pDataFlash->pDevice->cs); - if ( (dest + size) > (pDataFlash->pDevice->pages_size * + if ( (dest + size) > (pDataFlash->pDevice->pages_size * (pDataFlash->pDevice->pages_number))) return DATAFLASH_MEMORY_OVERFLOW; /* If destination does not fit a page start address */ - if ((dest % ((unsigned int)(pDataFlash->pDevice->pages_size))) != 0 ) + if ((dest % ((unsigned int)(pDataFlash->pDevice->pages_size))) != 0 ) { - length = pDataFlash->pDevice->pages_size - - (dest % + length = pDataFlash->pDevice->pages_size - + (dest % ((unsigned int) (pDataFlash->pDevice->pages_size))); @@ -461,7 +461,7 @@ AT91S_DataFlashStatus AT91F_DataFlashWrite( if(!AT91F_PartialPageWrite(pDataFlash,src, dest, length)) return DATAFLASH_ERROR; - AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, + AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY); /* Update size, source and destination pointers */ @@ -474,24 +474,24 @@ AT91S_DataFlashStatus AT91F_DataFlashWrite( /* program dataflash page */ page = (unsigned int)dest / (pDataFlash->pDevice->pages_size); - status = AT91F_DataFlashWriteBuffer(pDataFlash, - DB_BUF1_WRITE, src, 0, + status = AT91F_DataFlashWriteBuffer(pDataFlash, + DB_BUF1_WRITE, src, 0, pDataFlash->pDevice->pages_size); - AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, + AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY); status = AT91F_PageErase(pDataFlash, page); - AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, + AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY); if (!status) return DATAFLASH_ERROR; - status = AT91F_WriteBufferToMain (pDataFlash, + status = AT91F_WriteBufferToMain (pDataFlash, DB_BUF1_PAGE_PGM, dest); if(!status) return DATAFLASH_ERROR; - AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, + AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY); /* Update size, source and destination pointers */ @@ -506,7 +506,7 @@ AT91S_DataFlashStatus AT91F_DataFlashWrite( if(!AT91F_PartialPageWrite(pDataFlash, src, dest, size) ) return DATAFLASH_ERROR; - AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, + AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY); } return DATAFLASH_OK; @@ -529,18 +529,18 @@ int AT91F_DataFlashRead( AT91F_SpiEnable(pDataFlash->pDevice->cs); - if(AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, + if(AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY) != DATAFLASH_OK) return -1; while (size) { SizeToRead = (size < 0x8000)? size:0x8000; - if (AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, + if (AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY) != DATAFLASH_OK) return -1; - if (AT91F_DataFlashContinuousRead (pDataFlash, addr, + if (AT91F_DataFlashContinuousRead (pDataFlash, addr, (uchar *) buffer, SizeToRead) != DATAFLASH_OK) return -1; @@ -557,13 +557,10 @@ int AT91F_DataFlashRead( /* Object : */ /* Input Parameters : */ /* Return value : Dataflash status register */ -/*---------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ int AT91F_DataflashProbe(int cs, AT91PS_DataflashDesc pDesc) { AT91F_SpiEnable(cs); AT91F_DataFlashGetStatus(pDesc); - return((pDesc->command[1] == 0xFF)? 0: pDesc->command[1] & 0x3C); + return((pDesc->command[1] == 0xFF)? 0: pDesc->command[1] & 0x3C); } - #endif - - diff --git a/drivers/dataflash.c b/drivers/dataflash.c index 3b068d712..91903c8c8 100644 --- a/drivers/dataflash.c +++ b/drivers/dataflash.c @@ -63,7 +63,7 @@ dataflash_protect_t area_list[NB_DATAFLASH_AREA] = { #endif #elif defined(CONFIG_NEW_PARTITION) /*define the area offsets*/ -/* Invalid partitions should be defined with start > end */ +/* Invalid partitions should be defined with start > end */ dataflash_protect_t area_list[NB_DATAFLASH_AREA*CFG_MAX_DATAFLASH_BANKS] = { {0x00000000, 0x000083ff, FLAG_PROTECT_SET, 0, "Bootstrap"}, /* ROM code */ {0x00008400, 0x00020fff, FLAG_PROTECT_SET, 0, "U-Boot"}, /* u-boot code */ @@ -114,7 +114,7 @@ int AT91F_DataflashInit (void) dataflash_info[i].Desc.state = IDLE; dataflash_info[i].id = 0; dataflash_info[i].Device.pages_number = 0; - dfcode = AT91F_DataflashProbe (cs[i][1], + dfcode = AT91F_DataflashProbe (cs[i][1], &dataflash_info[i].Desc); switch (dfcode) { @@ -179,26 +179,26 @@ int AT91F_DataflashInit (void) /* set the area addresses */ for(j = 0; jpDevice->pages_number)) return 0; /* is too large for the dataflash */ if (size > ((pdataFlash->pDevice->pages_size * - pdataFlash->pDevice->pages_number) - + pdataFlash->pDevice->pages_number) - ((int)addr & 0x0FFFFFFF))) return 0; return 1; @@ -368,13 +368,13 @@ int area; (addr < pdataFlash->pDevice->area_list[area].end)) break; } - if (area == NB_DATAFLASH_AREA) + if (area == NB_DATAFLASH_AREA) return -1; /*test protection value*/ - if (pdataFlash->pDevice->area_list[area].protected == FLAG_PROTECT_SET) + if (pdataFlash->pDevice->area_list[area].protected == FLAG_PROTECT_SET) return 0; - if (pdataFlash->pDevice->area_list[area].protected == FLAG_PROTECT_INVALID) + if (pdataFlash->pDevice->area_list[area].protected == FLAG_PROTECT_INVALID) return 0; return 1; @@ -383,7 +383,7 @@ int area; /* Function Name : dataflash_real_protect */ /* Object : protect/unprotect area */ /*--------------------------------------------------------------------------*/ -int dataflash_real_protect (int flag, unsigned long start_addr, +int dataflash_real_protect (int flag, unsigned long start_addr, unsigned long end_addr) { int i,j, area1, area2, addr_valid = 0; @@ -400,27 +400,27 @@ int i,j, area1, area2, addr_valid = 0; } /* find start area */ for (area1=0; area1 < NB_DATAFLASH_AREA; area1++) { - if (start_addr == dataflash_info[i].Device.area_list[area1].start) + if (start_addr == dataflash_info[i].Device.area_list[area1].start) break; } if (area1 == NB_DATAFLASH_AREA) return -1; /* find end area */ for (area2=0; area2 < NB_DATAFLASH_AREA; area2++) { - if (end_addr == dataflash_info[i].Device.area_list[area2].end) + if (end_addr == dataflash_info[i].Device.area_list[area2].end) break; } - if (area2 == NB_DATAFLASH_AREA) + if (area2 == NB_DATAFLASH_AREA) return -1; /*set protection value*/ for(j = area1; j < area2+1 ; j++) - if(dataflash_info[i].Device.area_list[j].protected + if(dataflash_info[i].Device.area_list[j].protected != FLAG_PROTECT_INVALID) { if (flag == 0) { - dataflash_info[i].Device.area_list[j].protected + dataflash_info[i].Device.area_list[j].protected = FLAG_PROTECT_CLEAR; } else { - dataflash_info[i].Device.area_list[j].protected + dataflash_info[i].Device.area_list[j].protected = FLAG_PROTECT_SET; } } @@ -473,7 +473,7 @@ int write_dataflash (unsigned long addr_dest, unsigned long addr_src, if (AddrToWrite == -1) return -1; - return AT91F_DataFlashWrite (pFlash, (uchar *)addr_src, + return AT91F_DataFlashWrite (pFlash, (uchar *)addr_src, AddrToWrite, size); } diff --git a/include/at45.h b/include/at45.h index 1f71a3b4e..40bb4a08b 100644 --- a/include/at45.h +++ b/include/at45.h @@ -17,7 +17,7 @@ extern AT91S_DataFlashStatus AT91F_DataFlashSendCommand( extern AT91S_DataFlashStatus AT91F_DataFlashGetStatus ( AT91PS_DataflashDesc pDesc); extern AT91S_DataFlashStatus AT91F_DataFlashWaitReady ( - AT91PS_DataflashDesc pDataFlashDesc, + AT91PS_DataflashDesc pDataFlashDesc, unsigned int timeout); extern AT91S_DataFlashStatus AT91F_DataFlashContinuousRead ( AT91PS_DataFlash pDataFlash, diff --git a/include/dataflash.h b/include/dataflash.h index c597e69f1..fbd5e17f4 100644 --- a/include/dataflash.h +++ b/include/dataflash.h @@ -78,7 +78,7 @@ typedef struct { unsigned long end; unsigned char protected; unsigned char setenv; - unsigned char label[20]; + unsigned char label[20]; } dataflash_protect_t; typedef unsigned int AT91S_DataFlashStatus; diff --git a/include/led.h b/include/led.h index a261f1bf2..57c2b4a37 100644 --- a/include/led.h +++ b/include/led.h @@ -22,7 +22,7 @@ * MA 02111-1307 USA */ - #ifndef __LED_H +#ifndef __LED_H #define __LED_H #ifndef __ASSEMBLY__ @@ -43,4 +43,3 @@ extern void yellow_LED_off(void); .extern green_LED_off #endif #endif - From b361acd64fd2525c081b9b288b0804efe209c0e9 Mon Sep 17 00:00:00 2001 From: "ksi@koi8.net" Date: Tue, 14 Aug 2007 10:02:16 -0700 Subject: [PATCH 120/259] TI DaVinci - fix unsupported %hhx format Signed-off-by: Sergey Kubushyn --- board/davinci/dv-evm/dv_board.c | 2 +- board/davinci/schmoogie/dv_board.c | 2 +- board/davinci/sonata/dv_board.c | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/board/davinci/dv-evm/dv_board.c b/board/davinci/dv-evm/dv_board.c index 94925ecfb..604edb56c 100644 --- a/board/davinci/dv-evm/dv_board.c +++ b/board/davinci/dv-evm/dv_board.c @@ -181,7 +181,7 @@ int misc_init_r (void) tmp[0] &= buf[i]; if ((tmp[0] != 0xff) && (getenv("ethaddr") == NULL)) { - sprintf((char *)&tmp[0], "%02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx", + sprintf((char *)&tmp[0], "%02x:%02x:%02x:%02x:%02x:%02x", buf[0], buf[1], buf[2], buf[3], buf[4], buf[5]); setenv("ethaddr", (char *)&tmp[0]); } diff --git a/board/davinci/schmoogie/dv_board.c b/board/davinci/schmoogie/dv_board.c index b15c5f718..9f271a166 100644 --- a/board/davinci/schmoogie/dv_board.c +++ b/board/davinci/schmoogie/dv_board.c @@ -228,7 +228,7 @@ int misc_init_r (void) forceenv("serial#", "FAILED"); } else { /* CRC OK, set "serial" env variable */ - sprintf((char *)&tmp[0], "%02hhx%02hhx%02hhx%02hhx%02hhx%02hhx", + sprintf((char *)&tmp[0], "%02x%02x%02x%02x%02x%02x", buf[6], buf[5], buf[4], buf[3], buf[2], buf[1]); forceenv("serial#", (char *)&tmp[0]); } diff --git a/board/davinci/sonata/dv_board.c b/board/davinci/sonata/dv_board.c index 7b0a459fa..99857c427 100644 --- a/board/davinci/sonata/dv_board.c +++ b/board/davinci/sonata/dv_board.c @@ -182,7 +182,7 @@ int misc_init_r (void) tmp[0] &= buf[i]; if ((tmp[0] != 0xff) && (getenv("ethaddr") == NULL)) { - sprintf((char *)&tmp[0], "%02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx", + sprintf((char *)&tmp[0], "%02x:%02x:%02x:%02x:%02x:%02x", buf[0], buf[1], buf[2], buf[3], buf[4], buf[5]); setenv("ethaddr", (char *)&tmp[0]); } From 594e79838ce5078a90d0c27abb2b2d61d5f8e8a7 Mon Sep 17 00:00:00 2001 From: Ed Swarthout Date: Tue, 14 Aug 2007 14:06:45 -0500 Subject: [PATCH 121/259] Fix malloc size error in ahci_init_one. Typically this causes scsi init to corrupt the devlist and break the coninfo command. Fix a compiler size warning. Signed-off-by: Jason Jin Signed-off-by: Ed Swarthout Acked-by: Andy Fleming --- drivers/ahci.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/ahci.c b/drivers/ahci.c index ccd4d71e8..3d82c625a 100644 --- a/drivers/ahci.c +++ b/drivers/ahci.c @@ -259,8 +259,8 @@ static int ahci_init_one(pci_dev_t pdev) memset((void *)ataid, 0, sizeof(hd_driveid_t *) * AHCI_MAX_PORTS); - probe_ent = malloc(sizeof(probe_ent)); - memset(probe_ent, 0, sizeof(probe_ent)); + probe_ent = malloc(sizeof(struct ahci_probe_ent)); + memset(probe_ent, 0, sizeof(struct ahci_probe_ent)); probe_ent->dev = pdev; pci_read_config_dword(pdev, AHCI_PCI_BAR, &iobase); From 0e19209767194a97cec6d93dba9e64d1da8d548e Mon Sep 17 00:00:00 2001 From: Niklaus Giger Date: Wed, 15 Aug 2007 12:14:23 +0200 Subject: [PATCH 122/259] PPC4xx:HCU4/5-Board fix compile warning Signed-off-by: Niklaus Giger --- board/netstal/common/{flash.c => hcu_flash.c} | 0 board/netstal/hcu4/Makefile | 14 +++++++++----- board/netstal/hcu5/Makefile | 14 +++++++++----- 3 files changed, 18 insertions(+), 10 deletions(-) rename board/netstal/common/{flash.c => hcu_flash.c} (100%) diff --git a/board/netstal/common/flash.c b/board/netstal/common/hcu_flash.c similarity index 100% rename from board/netstal/common/flash.c rename to board/netstal/common/hcu_flash.c diff --git a/board/netstal/hcu4/Makefile b/board/netstal/hcu4/Makefile index d9825a5f2..af90821fa 100644 --- a/board/netstal/hcu4/Makefile +++ b/board/netstal/hcu4/Makefile @@ -22,16 +22,20 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a -vpath flash.c ../common -COBJS = $(BOARD).o flash.o +vpath hcu_flash.c ../common + +# NOBJS : Netstal common objects +NOBJS = hcu_flash.o +COBJS = $(BOARD).o SOBJS = -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) ../common/$(NOBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) +NOBJS := $(addprefix $(obj),$(NOBJS)) SOBJS := $(addprefix $(obj),$(SOBJS)) -$(LIB): $(OBJS) $(SOBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) +$(LIB): $(OBJS) $(SOBJS) $(NOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) $(NOBJS) clean: rm -f $(SOBJS) $(OBJS) diff --git a/board/netstal/hcu5/Makefile b/board/netstal/hcu5/Makefile index eee310b1a..27398b905 100644 --- a/board/netstal/hcu5/Makefile +++ b/board/netstal/hcu5/Makefile @@ -22,16 +22,20 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a -vpath flash.c ../common -COBJS = $(BOARD).o sdram.o flash.o +vpath hcu_flash.c ../common + +# NOBJS : Netstal common objects +NOBJS = hcu_flash.o +COBJS = $(BOARD).o sdram.o SOBJS = init.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) ../common/$(NOBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) +NOBJS := $(addprefix $(obj),$(NOBJS)) SOBJS := $(addprefix $(obj),$(SOBJS)) -$(LIB): $(OBJS) $(SOBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) +$(LIB): $(OBJS) $(SOBJS) $(NOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) $(NOBJS) clean: rm -f $(SOBJS) $(OBJS) From 210f463c71917b7a4495c2103c228b9c179ae64d Mon Sep 17 00:00:00 2001 From: Jerry Van Baren Date: Wed, 15 Aug 2007 11:13:15 -0400 Subject: [PATCH 123/259] Fix where the #ifdef CFG_BOOTMAPSZ is placed. Commit 073e1b509980cefe6f53c2d7fbbcd135df1e3924 "Fix initrd/dtb interaction" put the new code outside of the #if defined(CONFIG_OF_LIBFDT) when it should have gone inside of the conditional. As a result, it broke non-LIBFDT board builds. Also added a missing "not." to the comment. Signed-off-by: Gerald Van Baren --- common/cmd_bootm.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/common/cmd_bootm.c b/common/cmd_bootm.c index 8249dceb4..df1d0380d 100644 --- a/common/cmd_bootm.c +++ b/common/cmd_bootm.c @@ -924,16 +924,17 @@ do_bootm_linux (cmd_tbl_t *cmdtp, int flag, initrd_end = 0; } +#if defined(CONFIG_OF_LIBFDT) + #ifdef CFG_BOOTMAPSZ /* * The blob must be within CFG_BOOTMAPSZ, - * so we flag it to be copied if it is + * so we flag it to be copied if it is not. */ if (of_flat_tree >= (char *)CFG_BOOTMAPSZ) of_data = of_flat_tree; #endif -#if defined(CONFIG_OF_LIBFDT) /* move of_flat_tree if needed */ if (of_data) { int err; From 8662577fe36fdb6a44b55b998d9daac6392a736a Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Wed, 15 Aug 2007 11:46:22 -0500 Subject: [PATCH 124/259] 86xx: Fix lingering CFG_CMD_* references in sbc8641d.h Remove a leftover in net/tftp.c while we're at it. Signed-off-by: Jon Loeliger --- include/configs/sbc8641d.h | 6 +++--- net/tftp.c | 2 +- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/include/configs/sbc8641d.h b/include/configs/sbc8641d.h index 68d31ca1d..277b61140 100644 --- a/include/configs/sbc8641d.h +++ b/include/configs/sbc8641d.h @@ -492,7 +492,7 @@ #define CFG_LOAD_ADDR 0x2000000 /* default load address */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -513,7 +513,7 @@ /* Cache Configuration */ #define CFG_DCACHE_SIZE 32768 #define CFG_CACHELINE_SIZE 32 -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/ #endif @@ -525,7 +525,7 @@ #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif diff --git a/net/tftp.c b/net/tftp.c index 888ec987c..d6db91c05 100644 --- a/net/tftp.c +++ b/net/tftp.c @@ -614,4 +614,4 @@ static void parse_multicast_oack(char *pkt, int len) #endif /* Multicast TFTP */ -#endif /* CFG_CMD_NET */ +#endif From 4ce917742b1e48faa9bf9a9757545e56fb4cfe44 Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Wed, 15 Aug 2007 12:20:40 -0500 Subject: [PATCH 125/259] Move the MPC8641HPCN board under board/freescale. Minor path corrections needed to ensure buildability. Signed-off-by: Jon Loeliger --- Makefile | 2 +- board/{mpc8641hpcn => freescale/common}/sys_eeprom.c | 0 board/{ => freescale}/mpc8641hpcn/Makefile | 7 ++++--- board/{ => freescale}/mpc8641hpcn/config.mk | 0 board/{ => freescale}/mpc8641hpcn/init.S | 0 board/{ => freescale}/mpc8641hpcn/mpc8641hpcn.c | 2 +- board/{ => freescale}/mpc8641hpcn/u-boot.lds | 2 +- 7 files changed, 7 insertions(+), 6 deletions(-) rename board/{mpc8641hpcn => freescale/common}/sys_eeprom.c (100%) rename board/{ => freescale}/mpc8641hpcn/Makefile (93%) rename board/{ => freescale}/mpc8641hpcn/config.mk (100%) rename board/{ => freescale}/mpc8641hpcn/init.S (100%) rename board/{ => freescale}/mpc8641hpcn/mpc8641hpcn.c (99%) rename board/{ => freescale}/mpc8641hpcn/u-boot.lds (98%) diff --git a/Makefile b/Makefile index 9dee9483c..65efd3f5e 100644 --- a/Makefile +++ b/Makefile @@ -1900,7 +1900,7 @@ TQM8560_config: unconfig ######################################################################### MPC8641HPCN_config: unconfig - @$(MKCONFIG) $(@:_config=) ppc mpc86xx mpc8641hpcn + @$(MKCONFIG) $(@:_config=) ppc mpc86xx mpc8641hpcn freescale sbc8641d_config: unconfig @./mkconfig $(@:_config=) ppc mpc86xx sbc8641d diff --git a/board/mpc8641hpcn/sys_eeprom.c b/board/freescale/common/sys_eeprom.c similarity index 100% rename from board/mpc8641hpcn/sys_eeprom.c rename to board/freescale/common/sys_eeprom.c diff --git a/board/mpc8641hpcn/Makefile b/board/freescale/mpc8641hpcn/Makefile similarity index 93% rename from board/mpc8641hpcn/Makefile rename to board/freescale/mpc8641hpcn/Makefile index df56b31e5..93b015d47 100644 --- a/board/mpc8641hpcn/Makefile +++ b/board/freescale/mpc8641hpcn/Makefile @@ -24,13 +24,14 @@ include $(TOPDIR)/config.mk ifneq ($(OBJTREE),$(SRCTREE)) -$(shell mkdir -p $(obj)../freescale/common) +$(shell mkdir -p $(obj)../common) endif LIB = $(obj)lib$(BOARD).a -COBJS := $(BOARD).o sys_eeprom.o \ - ../freescale/common/pixis.o +COBJS := $(BOARD).o \ + ../common/sys_eeprom.o \ + ../common/pixis.o SOBJS := init.o diff --git a/board/mpc8641hpcn/config.mk b/board/freescale/mpc8641hpcn/config.mk similarity index 100% rename from board/mpc8641hpcn/config.mk rename to board/freescale/mpc8641hpcn/config.mk diff --git a/board/mpc8641hpcn/init.S b/board/freescale/mpc8641hpcn/init.S similarity index 100% rename from board/mpc8641hpcn/init.S rename to board/freescale/mpc8641hpcn/init.S diff --git a/board/mpc8641hpcn/mpc8641hpcn.c b/board/freescale/mpc8641hpcn/mpc8641hpcn.c similarity index 99% rename from board/mpc8641hpcn/mpc8641hpcn.c rename to board/freescale/mpc8641hpcn/mpc8641hpcn.c index 1bfbe88b5..ffd11cb5f 100644 --- a/board/mpc8641hpcn/mpc8641hpcn.c +++ b/board/freescale/mpc8641hpcn/mpc8641hpcn.c @@ -33,7 +33,7 @@ extern void ft_cpu_setup(void *blob, bd_t *bd); #endif -#include "../freescale/common/pixis.h" +#include "../common/pixis.h" #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) extern void ddr_enable_ecc(unsigned int dram_size); diff --git a/board/mpc8641hpcn/u-boot.lds b/board/freescale/mpc8641hpcn/u-boot.lds similarity index 98% rename from board/mpc8641hpcn/u-boot.lds rename to board/freescale/mpc8641hpcn/u-boot.lds index 58644648c..fd163622a 100644 --- a/board/mpc8641hpcn/u-boot.lds +++ b/board/freescale/mpc8641hpcn/u-boot.lds @@ -51,7 +51,7 @@ SECTIONS .text : { cpu/mpc86xx/start.o (.text) - board/mpc8641hpcn/init.o (.bootpg) + board/freescale/mpc8641hpcn/init.o (.bootpg) cpu/mpc86xx/traps.o (.text) cpu/mpc86xx/interrupts.o (.text) cpu/mpc86xx/cpu_init.o (.text) From 30b52df9e906bf0e465916c2c6bb5192b438e0b8 Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Wed, 15 Aug 2007 11:55:35 -0500 Subject: [PATCH 126/259] 86xx: Fix lingering CFG_CMD_* references in sbc8641d.h Remove a leftover in net/tftp.c while we're at it. Signed-off-by: Jon Loeliger --- include/configs/sbc8641d.h | 6 +++--- net/tftp.c | 2 +- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/include/configs/sbc8641d.h b/include/configs/sbc8641d.h index 68d31ca1d..277b61140 100644 --- a/include/configs/sbc8641d.h +++ b/include/configs/sbc8641d.h @@ -492,7 +492,7 @@ #define CFG_LOAD_ADDR 0x2000000 /* default load address */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -513,7 +513,7 @@ /* Cache Configuration */ #define CFG_DCACHE_SIZE 32768 #define CFG_CACHELINE_SIZE 32 -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/ #endif @@ -525,7 +525,7 @@ #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif diff --git a/net/tftp.c b/net/tftp.c index 888ec987c..d6db91c05 100644 --- a/net/tftp.c +++ b/net/tftp.c @@ -614,4 +614,4 @@ static void parse_multicast_oack(char *pkt, int len) #endif /* Multicast TFTP */ -#endif /* CFG_CMD_NET */ +#endif From 19fa1c35368484d4ed10ddce8a7793c21862e3a3 Mon Sep 17 00:00:00 2001 From: Kim Phillips Date: Wed, 15 Aug 2007 22:30:05 -0500 Subject: [PATCH 127/259] mpc83xx: add MAINTAINER and MAKEALL entries for the mpc8323erdb and reorder the existing 83xx maintainers alpha. Signed-off-by: Kim Phillips --- MAINTAINERS | 30 +++++++++++++++++------------- MAKEALL | 1 + 2 files changed, 18 insertions(+), 13 deletions(-) diff --git a/MAINTAINERS b/MAINTAINERS index f812431b8..3371e0f58 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -42,6 +42,10 @@ Yuli Barcohen Rattler MPC8248 ZPC1900 MPC8265 +Michael Barkowski + + MPC8323ERDB MPC8323 + Jerry Van Baren sacsng MPC8260 @@ -217,6 +221,10 @@ The LEOX team ELPT860 MPC860T +Dave Liu + + MPC8360EMDS MPC8360 + Nye Liu ZUMA MPC7xx_74xx @@ -273,6 +281,10 @@ Denis Peter MIP405 PPC4xx PIP405 PPC4xx +Kim Phillips + + MPC8349EMDS MPC8349 + Daniel Poirot sbc8240 MPC8240 @@ -320,6 +332,11 @@ Peter De Schrijver ML2 PPC4xx +Timur Tabi + + MPC8349E-mITX MPC8349 + MPC8349E-mITX-GP MPC8349 + Erik Theisen W7OLMC PPC4xx @@ -352,19 +369,6 @@ John Zhan svm_sc8xx MPC8xx -Timur Tabi - - MPC8349E-mITX MPC8349 - MPC8349E-mITX-GP MPC8349 - -Kim Phillips - - MPC8349EMDS MPC8349 - -Dave Liu - - MPC8360EMDS MPC8360 - ------------------------------------------------------------------------- Unknown / orphaned boards: diff --git a/MAKEALL b/MAKEALL index 1219fb373..d50ff8b6d 100755 --- a/MAKEALL +++ b/MAKEALL @@ -298,6 +298,7 @@ LIST_8260=" \ LIST_83xx=" \ MPC8313ERDB_33 \ MPC8313ERDB_66 \ + MPC8323ERDB \ MPC832XEMDS \ MPC8349EMDS \ MPC8349ITX \ From f4b2ac5ed9aaff9920d487bff8a59696c083a524 Mon Sep 17 00:00:00 2001 From: Kim Phillips Date: Wed, 15 Aug 2007 22:30:12 -0500 Subject: [PATCH 128/259] mpc83xx: fix UEC2->1 typo in libfdt setup code Signed-off-by: Kim Phillips --- cpu/mpc83xx/cpu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/cpu/mpc83xx/cpu.c b/cpu/mpc83xx/cpu.c index adf808301..a0754d185 100644 --- a/cpu/mpc83xx/cpu.c +++ b/cpu/mpc83xx/cpu.c @@ -481,7 +481,7 @@ static const struct { "local-mac-address", fdt_set_eth1 }, -#elif CFG_UEC1_UCC_NUM == 3 /* UCC4 */ +#elif CFG_UEC2_UCC_NUM == 3 /* UCC4 */ { "/" OF_QE "/ucc@3200", "mac-address", fdt_set_eth1 From 8f9e0e9f339aee4ce31a338d5f27356eb5457f85 Mon Sep 17 00:00:00 2001 From: Kim Phillips Date: Wed, 15 Aug 2007 22:30:19 -0500 Subject: [PATCH 129/259] mpc83xx: remaining 8360 libfdt fixes PCI clocks and QE frequencies weren't being updated, and the core clock was being updated incorrectly. This patch also adds a /memory node if it doesn't already exist prior to update. plus some cosmetic trimming to single line comments. Signed-off-by: Kim Phillips --- board/mpc8360emds/mpc8360emds.c | 8 ++++ board/mpc8360emds/pci.c | 8 +++- cpu/mpc83xx/cpu.c | 66 +++++++++++++++++++++++---------- cpu/mpc83xx/speed.c | 1 + 4 files changed, 61 insertions(+), 22 deletions(-) diff --git a/board/mpc8360emds/mpc8360emds.c b/board/mpc8360emds/mpc8360emds.c index 3fa093d1d..e37d2dcbe 100644 --- a/board/mpc8360emds/mpc8360emds.c +++ b/board/mpc8360emds/mpc8360emds.c @@ -305,7 +305,15 @@ ft_board_setup(void *blob, bd_t *bd) int tmp[2]; nodeoffset = fdt_find_node_by_path(blob, "/memory"); + if (nodeoffset < 0) { + nodeoffset = fdt_add_subnode(blob, 0, "memory"); + if (nodeoffset < 0) + printf("WARNING: failed to add /memory node: %s\n", + fdt_strerror(nodeoffset)); + } if (nodeoffset >= 0) { + fdt_setprop(blob, nodeoffset, "device_type", + "memory", sizeof("memory")); tmp[0] = cpu_to_be32(bd->bi_memstart); tmp[1] = cpu_to_be32(bd->bi_memsize); fdt_setprop(blob, nodeoffset, "reg", tmp, sizeof(tmp)); diff --git a/board/mpc8360emds/pci.c b/board/mpc8360emds/pci.c index 8f904710c..79812853e 100644 --- a/board/mpc8360emds/pci.c +++ b/board/mpc8360emds/pci.c @@ -22,7 +22,6 @@ #include #elif defined(CONFIG_OF_LIBFDT) #include -#include #endif #include @@ -314,7 +313,12 @@ ft_pci_setup(void *blob, bd_t *bd) if (nodeoffset >= 0) { tmp[0] = cpu_to_be32(hose[0].first_busno); tmp[1] = cpu_to_be32(hose[0].last_busno); - err = fdt_setprop(blob, nodeoffset, "bus-range", tmp, sizeof(tmp)); + err = fdt_setprop(blob, nodeoffset, "bus-range", + tmp, sizeof(tmp)); + + tmp[0] = cpu_to_be32(gd->pci_clk); + err = fdt_setprop(blob, nodeoffset, "clock-frequency", + tmp, sizeof(tmp[0])); } } #elif defined(CONFIG_OF_FLAT_TREE) diff --git a/cpu/mpc83xx/cpu.c b/cpu/mpc83xx/cpu.c index a0754d185..4deb5e516 100644 --- a/cpu/mpc83xx/cpu.c +++ b/cpu/mpc83xx/cpu.c @@ -35,12 +35,10 @@ #include #elif defined(CONFIG_OF_LIBFDT) #include -#include #endif DECLARE_GLOBAL_DATA_PTR; - int checkcpu(void) { volatile immap_t *immr; @@ -333,9 +331,7 @@ void watchdog_reset (void) */ static int fdt_set_eth0(void *blob, int nodeoffset, const char *name, bd_t *bd) { - /* - * Fix it up if it exists, don't create it if it doesn't exist. - */ + /* Fix it up if it exists, don't create it if it doesn't exist */ if (fdt_get_property(blob, nodeoffset, name, 0)) { return fdt_setprop(blob, nodeoffset, name, bd->bi_enetaddr, 6); } @@ -345,9 +341,7 @@ static int fdt_set_eth0(void *blob, int nodeoffset, const char *name, bd_t *bd) /* second onboard ethernet port */ static int fdt_set_eth1(void *blob, int nodeoffset, const char *name, bd_t *bd) { - /* - * Fix it up if it exists, don't create it if it doesn't exist. - */ + /* Fix it up if it exists, don't create it if it doesn't exist */ if (fdt_get_property(blob, nodeoffset, name, 0)) { return fdt_setprop(blob, nodeoffset, name, bd->bi_enet1addr, 6); } @@ -358,9 +352,7 @@ static int fdt_set_eth1(void *blob, int nodeoffset, const char *name, bd_t *bd) /* third onboard ethernet port */ static int fdt_set_eth2(void *blob, int nodeoffset, const char *name, bd_t *bd) { - /* - * Fix it up if it exists, don't create it if it doesn't exist. - */ + /* Fix it up if it exists, don't create it if it doesn't exist */ if (fdt_get_property(blob, nodeoffset, name, 0)) { return fdt_setprop(blob, nodeoffset, name, bd->bi_enet2addr, 6); } @@ -371,9 +363,7 @@ static int fdt_set_eth2(void *blob, int nodeoffset, const char *name, bd_t *bd) /* fourth onboard ethernet port */ static int fdt_set_eth3(void *blob, int nodeoffset, const char *name, bd_t *bd) { - /* - * Fix it up if it exists, don't create it if it doesn't exist. - */ + /* Fix it up if it exists, don't create it if it doesn't exist */ if (fdt_get_property(blob, nodeoffset, name, 0)) { return fdt_setprop(blob, nodeoffset, name, bd->bi_enet3addr, 6); } @@ -384,9 +374,7 @@ static int fdt_set_eth3(void *blob, int nodeoffset, const char *name, bd_t *bd) static int fdt_set_busfreq(void *blob, int nodeoffset, const char *name, bd_t *bd) { u32 tmp; - /* - * Create or update the property. - */ + /* Create or update the property */ tmp = cpu_to_be32(bd->bi_busfreq); return fdt_setprop(blob, nodeoffset, name, &tmp, sizeof(tmp)); } @@ -394,14 +382,38 @@ static int fdt_set_busfreq(void *blob, int nodeoffset, const char *name, bd_t *b static int fdt_set_tbfreq(void *blob, int nodeoffset, const char *name, bd_t *bd) { u32 tmp; - /* - * Create or update the property. - */ + /* Create or update the property */ tmp = cpu_to_be32(OF_TBCLK); return fdt_setprop(blob, nodeoffset, name, &tmp, sizeof(tmp)); } +static int fdt_set_clockfreq(void *blob, int nodeoffset, const char *name, bd_t *bd) +{ + u32 tmp; + /* Create or update the property */ + tmp = cpu_to_be32(gd->core_clk); + return fdt_setprop(blob, nodeoffset, name, &tmp, sizeof(tmp)); +} + +#ifdef CONFIG_QE +static int fdt_set_qe_busfreq(void *blob, int nodeoffset, const char *name, bd_t *bd) +{ + u32 tmp; + /* Create or update the property */ + tmp = cpu_to_be32(gd->qe_clk); + return fdt_setprop(blob, nodeoffset, name, &tmp, sizeof(tmp)); +} + +static int fdt_set_qe_brgfreq(void *blob, int nodeoffset, const char *name, bd_t *bd) +{ + u32 tmp; + /* Create or update the property */ + tmp = cpu_to_be32(gd->brg_clk); + return fdt_setprop(blob, nodeoffset, name, &tmp, sizeof(tmp)); +} +#endif + /* * Fixups to the fdt. */ @@ -420,6 +432,10 @@ static const struct { }, { "/cpus/" OF_CPU, "clock-frequency", + fdt_set_clockfreq + }, + { "/" OF_SOC, + "bus-frequency", fdt_set_busfreq }, { "/" OF_SOC "/serial@4500", @@ -450,6 +466,15 @@ static const struct { fdt_set_eth1 }, #endif +#ifdef CONFIG_QE + { "/" OF_QE, + "brg-frequency", + fdt_set_qe_brgfreq + }, + { "/" OF_QE, + "bus-frequency", + fdt_set_qe_busfreq + }, #ifdef CONFIG_UEC_ETH1 #if CFG_UEC1_UCC_NUM == 0 /* UCC1 */ { "/" OF_QE "/ucc@2000", @@ -492,6 +517,7 @@ static const struct { }, #endif #endif /* CONFIG_UEC_ETH2 */ +#endif /* CONFIG_QE */ }; void diff --git a/cpu/mpc83xx/speed.c b/cpu/mpc83xx/speed.c index bf3061654..cba57fadb 100644 --- a/cpu/mpc83xx/speed.c +++ b/cpu/mpc83xx/speed.c @@ -351,6 +351,7 @@ int get_clocks(void) gd->qe_clk = qe_clk; gd->brg_clk = brg_clk; #endif + gd->pci_clk = pci_sync_in; gd->cpu_clk = gd->core_clk; gd->bus_clk = gd->csb_clk; return 0; From 6a16e0dfcc4119b46adb1dce2d6c8fb3c5d108e1 Mon Sep 17 00:00:00 2001 From: Kim Phillips Date: Wed, 15 Aug 2007 22:30:26 -0500 Subject: [PATCH 130/259] mpc83xx: move common /memory node update mechanism to cpu.c also adds common prototypes to include/common.h. Signed-off-by: Kim Phillips --- board/freescale/mpc8323erdb/mpc8323erdb.c | 22 ---------------- board/mpc8360emds/mpc8360emds.c | 31 +---------------------- cpu/mpc83xx/cpu.c | 31 +++++++++++++++++------ include/common.h | 7 +++++ 4 files changed, 31 insertions(+), 60 deletions(-) diff --git a/board/freescale/mpc8323erdb/mpc8323erdb.c b/board/freescale/mpc8323erdb/mpc8323erdb.c index 1886f196b..81b82b760 100644 --- a/board/freescale/mpc8323erdb/mpc8323erdb.c +++ b/board/freescale/mpc8323erdb/mpc8323erdb.c @@ -17,7 +17,6 @@ #include #include #include -#include #if defined(CONFIG_PCI) #include #endif @@ -185,31 +184,10 @@ void pci_init_board(void) } #if defined(CONFIG_OF_BOARD_SETUP) - -/* - * Prototypes of functions that we use. - */ -void ft_cpu_setup(void *blob, bd_t *bd); - -#ifdef CONFIG_PCI -void ft_pci_setup(void *blob, bd_t *bd); -#endif - void ft_board_setup(void *blob, bd_t *bd) { - int nodeoffset; - int tmp[2]; - - nodeoffset = fdt_find_node_by_path(blob, "/memory"); - if (nodeoffset >= 0) { - tmp[0] = cpu_to_be32(bd->bi_memstart); - tmp[1] = cpu_to_be32(bd->bi_memsize); - fdt_setprop(blob, nodeoffset, "reg", tmp, sizeof(tmp)); - } - ft_cpu_setup(blob, bd); - #ifdef CONFIG_PCI ft_pci_setup(blob, bd); #endif diff --git a/board/mpc8360emds/mpc8360emds.c b/board/mpc8360emds/mpc8360emds.c index e37d2dcbe..eec46fb3a 100644 --- a/board/mpc8360emds/mpc8360emds.c +++ b/board/mpc8360emds/mpc8360emds.c @@ -29,7 +29,6 @@ #include #elif defined(CONFIG_OF_LIBFDT) #include -#include #endif const qe_iop_conf_t qe_iop_conf_tab[] = { @@ -287,38 +286,10 @@ void sdram_init(void) #if (defined(CONFIG_OF_FLAT_TREE) || defined(CONFIG_OF_LIBFDT)) \ && defined(CONFIG_OF_BOARD_SETUP) - -/* - * Prototypes of functions that we use. - */ -void ft_cpu_setup(void *blob, bd_t *bd); - -#ifdef CONFIG_PCI -void ft_pci_setup(void *blob, bd_t *bd); -#endif - void ft_board_setup(void *blob, bd_t *bd) { -#if defined(CONFIG_OF_LIBFDT) - int nodeoffset; - int tmp[2]; - - nodeoffset = fdt_find_node_by_path(blob, "/memory"); - if (nodeoffset < 0) { - nodeoffset = fdt_add_subnode(blob, 0, "memory"); - if (nodeoffset < 0) - printf("WARNING: failed to add /memory node: %s\n", - fdt_strerror(nodeoffset)); - } - if (nodeoffset >= 0) { - fdt_setprop(blob, nodeoffset, "device_type", - "memory", sizeof("memory")); - tmp[0] = cpu_to_be32(bd->bi_memstart); - tmp[1] = cpu_to_be32(bd->bi_memsize); - fdt_setprop(blob, nodeoffset, "reg", tmp, sizeof(tmp)); - } -#else +#if defined(CONFIG_OF_FLAT_TREE) u32 *p; int len; diff --git a/cpu/mpc83xx/cpu.c b/cpu/mpc83xx/cpu.c index 4deb5e516..e634f0a25 100644 --- a/cpu/mpc83xx/cpu.c +++ b/cpu/mpc83xx/cpu.c @@ -523,9 +523,10 @@ static const struct { void ft_cpu_setup(void *blob, bd_t *bd) { - int nodeoffset; - int err; - int j; + int nodeoffset; + int err; + int j; + int tmp[2]; for (j = 0; j < (sizeof(fixup_props) / sizeof(fixup_props[0])); j++) { nodeoffset = fdt_find_node_by_path(blob, fixup_props[j].node); @@ -534,15 +535,29 @@ ft_cpu_setup(void *blob, bd_t *bd) fixup_props[j].prop, bd); if (err < 0) debug("Problem setting %s = %s: %s\n", - fixup_props[j].node, - fixup_props[j].prop, - fdt_strerror(err)); + fixup_props[j].node, fixup_props[j].prop, + fdt_strerror(err)); } else { debug("Couldn't find %s: %s\n", - fixup_props[j].node, - fdt_strerror(nodeoffset)); + fixup_props[j].node, fdt_strerror(nodeoffset)); } } + + /* update, or add and update /memory node */ + nodeoffset = fdt_find_node_by_path(blob, "/memory"); + if (nodeoffset < 0) { + nodeoffset = fdt_add_subnode(blob, 0, "memory"); + if (nodeoffset < 0) + debug("failed to add /memory node: %s\n", + fdt_strerror(nodeoffset)); + } + if (nodeoffset >= 0) { + fdt_setprop(blob, nodeoffset, "device_type", + "memory", sizeof("memory")); + tmp[0] = cpu_to_be32(bd->bi_memstart); + tmp[1] = cpu_to_be32(bd->bi_memsize); + fdt_setprop(blob, nodeoffset, "reg", tmp, sizeof(tmp)); + } } #elif defined(CONFIG_OF_FLAT_TREE) void diff --git a/include/common.h b/include/common.h index 27a660a4d..9a5a0ab79 100644 --- a/include/common.h +++ b/include/common.h @@ -434,6 +434,13 @@ int checkdcache (void); void upmconfig (unsigned int, unsigned int *, unsigned int); ulong get_tbclk (void); void reset_cpu (ulong addr); +#if defined (CONFIG_OF_LIBFDT) && defined (CONFIG_OF_BOARD_SETUP) +void ft_cpu_setup(void *blob, bd_t *bd); +#ifdef CONFIG_PCI +void ft_pci_setup(void *blob, bd_t *bd); +#endif +#endif + /* $(CPU)/serial.c */ int serial_init (void); From 3fde9e8b22cfbd7af489214758f9839a206576cb Mon Sep 17 00:00:00 2001 From: Kim Phillips Date: Wed, 15 Aug 2007 22:30:33 -0500 Subject: [PATCH 131/259] mpc83xx: migrate remaining freescale boards to libfdt this adds libfdt support code for the freescale mpc8313erdb, mpc832xemds, mpc8349emds, mpc8349itx, and gp boards. Boards remain compatible with OF_FLAT_TREE. Signed-off-by: Kim Phillips --- board/freescale/mpc8323erdb/mpc8323erdb.c | 15 +++++++-- board/mpc8313erdb/mpc8313erdb.c | 19 +++++++---- board/mpc832xemds/mpc832xemds.c | 18 +++++----- board/mpc832xemds/pci.c | 24 ++++++++++++- board/mpc8349emds/mpc8349emds.c | 18 +++++----- board/mpc8349emds/pci.c | 41 ++++++++++++++++++++++- board/mpc8349itx/mpc8349itx.c | 18 +++++----- board/mpc8349itx/pci.c | 39 +++++++++++++++++++-- board/mpc8360emds/mpc8360emds.c | 11 +++--- cpu/mpc83xx/pci.c | 15 +++++++-- 10 files changed, 170 insertions(+), 48 deletions(-) diff --git a/board/freescale/mpc8323erdb/mpc8323erdb.c b/board/freescale/mpc8323erdb/mpc8323erdb.c index 81b82b760..850d1c370 100644 --- a/board/freescale/mpc8323erdb/mpc8323erdb.c +++ b/board/freescale/mpc8323erdb/mpc8323erdb.c @@ -184,12 +184,21 @@ void pci_init_board(void) } #if defined(CONFIG_OF_BOARD_SETUP) -void -ft_board_setup(void *blob, bd_t *bd) +void ft_board_setup(void *blob, bd_t *bd) { +#if defined(CONFIG_OF_FLAT_TREE) + u32 *p; + int len; + + p = ft_get_prop(blob, "/memory/reg", &len); + if (p != NULL) { + *p++ = cpu_to_be32(bd->bi_memstart); + *p = cpu_to_be32(bd->bi_memsize); + } +#endif ft_cpu_setup(blob, bd); #ifdef CONFIG_PCI ft_pci_setup(blob, bd); #endif } -#endif /* CONFIG_OF_BOARD_SETUP */ +#endif diff --git a/board/mpc8313erdb/mpc8313erdb.c b/board/mpc8313erdb/mpc8313erdb.c index 999fe9e39..861c143df 100644 --- a/board/mpc8313erdb/mpc8313erdb.c +++ b/board/mpc8313erdb/mpc8313erdb.c @@ -23,7 +23,11 @@ */ #include +#if defined(CONFIG_OF_FLAT_TREE) #include +#elif defined(CONFIG_OF_LIBFDT) +#include +#endif #include #include @@ -96,21 +100,22 @@ void pci_init_board(void) mpc83xx_pci_init(1, reg, warmboot); } -#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP) +#if defined(CONFIG_OF_BOARD_SETUP) void ft_board_setup(void *blob, bd_t *bd) { +#if defined(CONFIG_OF_FLAT_TREE) u32 *p; int len; -#ifdef CONFIG_PCI - ft_pci_setup(blob, bd); -#endif - ft_cpu_setup(blob, bd); - p = ft_get_prop(blob, "/memory/reg", &len); - if (p) { + if (p != NULL) { *p++ = cpu_to_be32(bd->bi_memstart); *p = cpu_to_be32(bd->bi_memsize); } +#endif + ft_cpu_setup(blob, bd); +#ifdef CONFIG_PCI + ft_pci_setup(blob, bd); +#endif } #endif diff --git a/board/mpc832xemds/mpc832xemds.c b/board/mpc832xemds/mpc832xemds.c index 772da678f..f70783e73 100644 --- a/board/mpc832xemds/mpc832xemds.c +++ b/board/mpc832xemds/mpc832xemds.c @@ -29,6 +29,8 @@ #endif #if defined(CONFIG_OF_FLAT_TREE) #include +#elif defined(CONFIG_OF_LIBFDT) +#include #endif const qe_iop_conf_t qe_iop_conf_tab[] = { @@ -155,22 +157,22 @@ int checkboard(void) return 0; } -#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP) -void -ft_board_setup(void *blob, bd_t *bd) +#if defined(CONFIG_OF_BOARD_SETUP) +void ft_board_setup(void *blob, bd_t *bd) { +#if defined(CONFIG_OF_FLAT_TREE) u32 *p; int len; -#ifdef CONFIG_PCI - ft_pci_setup(blob, bd); -#endif - ft_cpu_setup(blob, bd); - p = ft_get_prop(blob, "/memory/reg", &len); if (p != NULL) { *p++ = cpu_to_be32(bd->bi_memstart); *p = cpu_to_be32(bd->bi_memsize); } +#endif + ft_cpu_setup(blob, bd); +#ifdef CONFIG_PCI + ft_pci_setup(blob, bd); +#endif } #endif diff --git a/board/mpc832xemds/pci.c b/board/mpc832xemds/pci.c index d0a407ae8..c2f61ea6a 100644 --- a/board/mpc832xemds/pci.c +++ b/board/mpc832xemds/pci.c @@ -20,6 +20,8 @@ #include #if defined(CONFIG_OF_FLAT_TREE) #include +#elif defined(CONFIG_OF_LIBFDT) +#include #endif #include @@ -299,7 +301,27 @@ void pci_init_board(void) } #endif /* CONFIG_PCISLAVE */ -#ifdef CONFIG_OF_FLAT_TREE +#if defined(CONFIG_OF_LIBFDT) +void +ft_pci_setup(void *blob, bd_t *bd) +{ + int nodeoffset; + int err; + int tmp[2]; + + nodeoffset = fdt_find_node_by_path(blob, "/" OF_SOC "/pci@8500"); + if (nodeoffset >= 0) { + tmp[0] = cpu_to_be32(hose[0].first_busno); + tmp[1] = cpu_to_be32(hose[0].last_busno); + err = fdt_setprop(blob, nodeoffset, "bus-range", + tmp, sizeof(tmp)); + + tmp[0] = cpu_to_be32(gd->pci_clk); + err = fdt_setprop(blob, nodeoffset, "clock-frequency", + tmp, sizeof(tmp[0])); + } +} +#elif defined(CONFIG_OF_FLAT_TREE) void ft_pci_setup(void *blob, bd_t *bd) { diff --git a/board/mpc8349emds/mpc8349emds.c b/board/mpc8349emds/mpc8349emds.c index 521d1bbd4..2ad25ec50 100644 --- a/board/mpc8349emds/mpc8349emds.c +++ b/board/mpc8349emds/mpc8349emds.c @@ -34,6 +34,8 @@ #endif #if defined(CONFIG_OF_FLAT_TREE) #include +#elif defined(CONFIG_OF_LIBFDT) +#include #endif int fixed_sdram(void); @@ -257,22 +259,22 @@ void sdram_init(void) } #endif -#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP) -void -ft_board_setup(void *blob, bd_t *bd) +#if defined(CONFIG_OF_BOARD_SETUP) +void ft_board_setup(void *blob, bd_t *bd) { +#if defined(CONFIG_OF_FLAT_TREE) u32 *p; int len; -#ifdef CONFIG_PCI - ft_pci_setup(blob, bd); -#endif - ft_cpu_setup(blob, bd); - p = ft_get_prop(blob, "/memory/reg", &len); if (p != NULL) { *p++ = cpu_to_be32(bd->bi_memstart); *p = cpu_to_be32(bd->bi_memsize); } +#endif + ft_cpu_setup(blob, bd); +#ifdef CONFIG_PCI + ft_pci_setup(blob, bd); +#endif } #endif diff --git a/board/mpc8349emds/pci.c b/board/mpc8349emds/pci.c index d6a12b82a..ae94a2f38 100644 --- a/board/mpc8349emds/pci.c +++ b/board/mpc8349emds/pci.c @@ -25,6 +25,12 @@ #include #include #include +#if defined(CONFIG_OF_FLAT_TREE) +#include +#elif defined(CONFIG_OF_LIBFDT) +#include +#endif + DECLARE_GLOBAL_DATA_PTR; @@ -382,7 +388,40 @@ pci_init_board(void) } -#ifdef CONFIG_OF_FLAT_TREE +#if defined(CONFIG_OF_LIBFDT) +void +ft_pci_setup(void *blob, bd_t *bd) +{ + int nodeoffset; + int err; + int tmp[2]; + + nodeoffset = fdt_find_node_by_path(blob, "/" OF_SOC "/pci@8500"); + if (nodeoffset >= 0) { + tmp[0] = cpu_to_be32(pci_hose[0].first_busno); + tmp[1] = cpu_to_be32(pci_hose[0].last_busno); + err = fdt_setprop(blob, nodeoffset, "bus-range", + tmp, sizeof(tmp)); + + tmp[0] = cpu_to_be32(gd->pci_clk); + err = fdt_setprop(blob, nodeoffset, "clock-frequency", + tmp, sizeof(tmp[0])); + } +#ifdef CONFIG_MPC83XX_PCI2 + nodeoffset = fdt_find_node_by_path(blob, "/" OF_SOC "/pci@8600"); + if (nodeoffset >= 0) { + tmp[0] = cpu_to_be32(pci_hose[1].first_busno); + tmp[1] = cpu_to_be32(pci_hose[1].last_busno); + err = fdt_setprop(blob, nodeoffset, "bus-range", + tmp, sizeof(tmp)); + + tmp[0] = cpu_to_be32(gd->pci_clk); + err = fdt_setprop(blob, nodeoffset, "clock-frequency", + tmp, sizeof(tmp[0])); + } +#endif +} +#elif defined(CONFIG_OF_FLAT_TREE) void ft_pci_setup(void *blob, bd_t *bd) { diff --git a/board/mpc8349itx/mpc8349itx.c b/board/mpc8349itx/mpc8349itx.c index 178b1d36f..125e6c086 100644 --- a/board/mpc8349itx/mpc8349itx.c +++ b/board/mpc8349itx/mpc8349itx.c @@ -39,6 +39,8 @@ #endif #if defined(CONFIG_OF_FLAT_TREE) #include +#elif defined(CONFIG_OF_LIBFDT) +#include #endif #ifndef CONFIG_SPD_EEPROM @@ -385,22 +387,22 @@ int misc_init_r(void) return rc; } -#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP) -void -ft_board_setup(void *blob, bd_t *bd) +#if defined(CONFIG_OF_BOARD_SETUP) +void ft_board_setup(void *blob, bd_t *bd) { +#if defined(CONFIG_OF_FLAT_TREE) u32 *p; int len; -#ifdef CONFIG_PCI - ft_pci_setup(blob, bd); -#endif - ft_cpu_setup(blob, bd); - p = ft_get_prop(blob, "/memory/reg", &len); if (p != NULL) { *p++ = cpu_to_be32(bd->bi_memstart); *p = cpu_to_be32(bd->bi_memsize); } +#endif + ft_cpu_setup(blob, bd); +#ifdef CONFIG_PCI + ft_pci_setup(blob, bd); +#endif } #endif diff --git a/board/mpc8349itx/pci.c b/board/mpc8349itx/pci.c index e81ad2735..5ca094d4c 100644 --- a/board/mpc8349itx/pci.c +++ b/board/mpc8349itx/pci.c @@ -31,6 +31,8 @@ #include #if defined(CONFIG_OF_FLAT_TREE) #include +#elif defined(CONFIG_OF_LIBFDT) +#include #endif DECLARE_GLOBAL_DATA_PTR; @@ -332,8 +334,40 @@ void pci_init_board(void) #endif } -#endif /* CONFIG_PCI */ -#ifdef CONFIG_OF_FLAT_TREE +#if defined(CONFIG_OF_LIBFDT) +void +ft_pci_setup(void *blob, bd_t *bd) +{ + int nodeoffset; + int err; + int tmp[2]; + + nodeoffset = fdt_find_node_by_path(blob, "/" OF_SOC "/pci@8500"); + if (nodeoffset >= 0) { + tmp[0] = cpu_to_be32(pci_hose[0].first_busno); + tmp[1] = cpu_to_be32(pci_hose[0].last_busno); + err = fdt_setprop(blob, nodeoffset, "bus-range", + tmp, sizeof(tmp)); + + tmp[0] = cpu_to_be32(gd->pci_clk); + err = fdt_setprop(blob, nodeoffset, "clock-frequency", + tmp, sizeof(tmp[0])); + } +#ifdef CONFIG_MPC83XX_PCI2 + nodeoffset = fdt_find_node_by_path(blob, "/" OF_SOC "/pci@8500"); + if (nodeoffset >= 0) { + tmp[0] = cpu_to_be32(pci_hose[1].first_busno); + tmp[1] = cpu_to_be32(pci_hose[1].last_busno); + err = fdt_setprop(blob, nodeoffset, "bus-range", + tmp, sizeof(tmp)); + + tmp[0] = cpu_to_be32(gd->pci_clk); + err = fdt_setprop(blob, nodeoffset, "clock-frequency", + tmp, sizeof(tmp[0])); + } +#endif +} +#elif defined(CONFIG_OF_FLAT_TREE) void ft_pci_setup(void *blob, bd_t *bd) { @@ -355,3 +389,4 @@ ft_pci_setup(void *blob, bd_t *bd) #endif } #endif /* CONFIG_OF_FLAT_TREE */ +#endif /* CONFIG_PCI */ diff --git a/board/mpc8360emds/mpc8360emds.c b/board/mpc8360emds/mpc8360emds.c index eec46fb3a..386173351 100644 --- a/board/mpc8360emds/mpc8360emds.c +++ b/board/mpc8360emds/mpc8360emds.c @@ -284,10 +284,8 @@ void sdram_init(void) } #endif -#if (defined(CONFIG_OF_FLAT_TREE) || defined(CONFIG_OF_LIBFDT)) \ - && defined(CONFIG_OF_BOARD_SETUP) -void -ft_board_setup(void *blob, bd_t *bd) +#if defined(CONFIG_OF_BOARD_SETUP) +void ft_board_setup(void *blob, bd_t *bd) { #if defined(CONFIG_OF_FLAT_TREE) u32 *p; @@ -299,10 +297,9 @@ ft_board_setup(void *blob, bd_t *bd) *p = cpu_to_be32(bd->bi_memsize); } #endif - + ft_cpu_setup(blob, bd); #ifdef CONFIG_PCI ft_pci_setup(blob, bd); #endif - ft_cpu_setup(blob, bd); } -#endif /* CONFIG_OF_x */ +#endif diff --git a/cpu/mpc83xx/pci.c b/cpu/mpc83xx/pci.c index 229821887..5675afe97 100644 --- a/cpu/mpc83xx/pci.c +++ b/cpu/mpc83xx/pci.c @@ -28,7 +28,6 @@ #if defined(CONFIG_OF_LIBFDT) #include -#include #elif defined(CONFIG_OF_FLAT_TREE) #include #endif @@ -184,7 +183,12 @@ void ft_pci_setup(void *blob, bd_t *bd) if (nodeoffset >= 0) { tmp[0] = cpu_to_be32(pci_hose[0].first_busno); tmp[1] = cpu_to_be32(pci_hose[0].last_busno); - err = fdt_setprop(blob, nodeoffset, "bus-range", tmp, sizeof(tmp)); + err = fdt_setprop(blob, nodeoffset, "bus-range", + tmp, sizeof(tmp)); + + tmp[0] = cpu_to_be32(gd->pci_clk); + err = fdt_setprop(blob, nodeoffset, "clock-frequency", + tmp, sizeof(tmp[0])); } if (pci_num_buses < 2) @@ -194,7 +198,12 @@ void ft_pci_setup(void *blob, bd_t *bd) if (nodeoffset >= 0) { tmp[0] = cpu_to_be32(pci_hose[0].first_busno); tmp[1] = cpu_to_be32(pci_hose[0].last_busno); - err = fdt_setprop(blob, nodeoffset, "bus-range", tmp, sizeof(tmp)); + err = fdt_setprop(blob, nodeoffset, "bus-range", + tmp, sizeof(tmp)); + + tmp[0] = cpu_to_be32(gd->pci_clk); + err = fdt_setprop(blob, nodeoffset, "clock-frequency", + tmp, sizeof(tmp[0])); } } #elif CONFIG_OF_FLAT_TREE From 35cc4e4823668e8745854899cfaedd4489beb0ef Mon Sep 17 00:00:00 2001 From: Kim Phillips Date: Wed, 15 Aug 2007 22:30:39 -0500 Subject: [PATCH 132/259] mpc83xx: enable libfdt by default on freescale boards this enables libfdt code by default for the freescale mpc8313erdb, mpc832xemds, mpc8349emds, mpc8349itx and gp boards. Signed-off-by: Kim Phillips --- include/configs/MPC8313ERDB.h | 2 +- include/configs/MPC832XEMDS.h | 2 +- include/configs/MPC8349EMDS.h | 2 +- include/configs/MPC8349ITX.h | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/include/configs/MPC8313ERDB.h b/include/configs/MPC8313ERDB.h index 81db96f46..e2ec0bc22 100644 --- a/include/configs/MPC8313ERDB.h +++ b/include/configs/MPC8313ERDB.h @@ -228,7 +228,7 @@ #define CFG_LBLAWAR3_PRELIM 0x8000000E /* 32KB */ /* pass open firmware flat tree */ -#define CONFIG_OF_FLAT_TREE 1 +#define CONFIG_OF_LIBFDT 1 #define CONFIG_OF_BOARD_SETUP 1 /* maximum size of the flat tree (8K) */ diff --git a/include/configs/MPC832XEMDS.h b/include/configs/MPC832XEMDS.h index f62ca2c42..e8c6b7502 100644 --- a/include/configs/MPC832XEMDS.h +++ b/include/configs/MPC832XEMDS.h @@ -315,7 +315,7 @@ #endif /* pass open firmware flat tree */ -#define CONFIG_OF_FLAT_TREE 1 +#define CONFIG_OF_LIBFDT 1 #define CONFIG_OF_BOARD_SETUP 1 /* maximum size of the flat tree (8K) */ diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h index 1567fcfae..d28e0f365 100644 --- a/include/configs/MPC8349EMDS.h +++ b/include/configs/MPC8349EMDS.h @@ -339,7 +339,7 @@ #endif /* pass open firmware flat tree */ -#define CONFIG_OF_FLAT_TREE 1 +#define CONFIG_OF_LIBFDT 1 #define CONFIG_OF_BOARD_SETUP 1 /* maximum size of the flat tree (8K) */ diff --git a/include/configs/MPC8349ITX.h b/include/configs/MPC8349ITX.h index 44649d050..82ef4da5d 100644 --- a/include/configs/MPC8349ITX.h +++ b/include/configs/MPC8349ITX.h @@ -296,7 +296,7 @@ boards, we say we have two, but don't display a message if we find only one. */ #define CFG_NS16550_COM2 (CFG_IMMR + 0x4600) /* pass open firmware flat tree */ -#define CONFIG_OF_FLAT_TREE +#define CONFIG_OF_LIBFDT 1 #define CONFIG_OF_BOARD_SETUP /* maximum size of the flat tree (8K) */ From 02ba7022f62bb75908296c58c63866e1d294b69a Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Thu, 16 Aug 2007 09:52:29 +0200 Subject: [PATCH 133/259] ppc4xx: Update Sequoia/Rainier bootstrap command As suggested by David Mitchell, here an update for the Sequoia/Rainier bootstrap command. Signed-off-by: Stefan Roese --- board/amcc/sequoia/cmd_sequoia.c | 209 +++++++++++++++++++++++-------- 1 file changed, 159 insertions(+), 50 deletions(-) diff --git a/board/amcc/sequoia/cmd_sequoia.c b/board/amcc/sequoia/cmd_sequoia.c index 6fc60eaaa..f3803c09f 100644 --- a/board/amcc/sequoia/cmd_sequoia.c +++ b/board/amcc/sequoia/cmd_sequoia.c @@ -26,76 +26,185 @@ #include #include -static u8 boot_533_nor[] = { - 0x87, 0x78, 0x82, 0x52, 0x09, 0x57, 0xa0, 0x30, - 0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00 +/* + * There are 2 versions of production Sequoia & Rainier platforms. + * The primary difference is the reference clock. Those with + * 33333333 reference clocks will also have 667MHz rated + * processors. Not enough differences to have unique clock + * settings. + * + * NOR and NAND boot options change bytes 6, 7, 8, 9, 11. The + * values are independent of the rest of the clock settings. + * + * All Sequoias & Rainiers select from two possible EEPROMs in Boot + * Config F. One for 33MHz PCI, one for 66MHz PCI. The following + * values are for the 33MHz PCI configuration. Byte 5 (0 base) is + * the only value affected for a 66MHz PCI and simply needs a +0x10. + */ + +#define NAND_COMPATIBLE 0x01 +#define NOR_COMPATIBLE 0x02 + +/* check with Stefan on CFG_I2C_EEPROM_ADDR */ +#define I2C_EEPROM_ADDR 0x52 + +static char *config_labels[] = { + "CPU: 333 PLB: 133 OPB: 66 EBC: 66", + "CPU: 333 PLB: 166 OPB: 83 EBC: 55", + "CPU: 400 PLB: 133 OPB: 66 EBC: 66", + "CPU: 400 PLB: 160 OPB: 80 EBC: 53", + "CPU: 416 PLB: 166 OPB: 83 EBC: 55", + "CPU: 500 PLB: 166 OPB: 83 EBC: 55", + "CPU: 533 PLB: 133 OPB: 66 EBC: 66", + "CPU: 667 PLB: 166 OPB: 83 EBC: 55", + NULL }; -static u8 boot_533_nand[] = { - 0x87, 0x78, 0x82, 0x52, 0x09, 0x57, 0xd0, 0x10, - 0xa0, 0x68, 0x23, 0x58, 0x0d, 0x05, 0x00, 0x00 +static u8 boot_configs[][17] = { + { + (NOR_COMPATIBLE), + 0x84, 0x70, 0xa2, 0xa6, 0x05, 0x57, 0xa0, 0x10, 0x40, + 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00 + }, + { + (NAND_COMPATIBLE | NOR_COMPATIBLE), + 0xc7, 0x78, 0xf3, 0x4e, 0x05, 0xd7, 0xa0, 0x30, 0x40, + 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00 + }, + { + (NOR_COMPATIBLE), + 0x86, 0x78, 0xc2, 0xc6, 0x05, 0x57, 0xa0, 0x30, 0x40, + 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00 + }, + { + (NOR_COMPATIBLE), + 0x86, 0x78, 0xc2, 0xa6, 0x05, 0xd7, 0xa0, 0x10, 0x40, + 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00 + }, + { + (NAND_COMPATIBLE | NOR_COMPATIBLE), + 0xc6, 0x78, 0x52, 0xa6, 0x05, 0xd7, 0xa0, 0x10, 0x40, + 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00 + }, + { + (NAND_COMPATIBLE | NOR_COMPATIBLE), + 0xc7, 0x78, 0x52, 0xc6, 0x05, 0xd7, 0xa0, 0x30, 0x40, + 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00 + }, + { + (NOR_COMPATIBLE), + 0x87, 0x78, 0x82, 0x52, 0x09, 0x57, 0xa0, 0x30, 0x40, + 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00 + }, + { + (NAND_COMPATIBLE | NOR_COMPATIBLE), + 0x87, 0x78, 0xa2, 0x52, 0x09, 0xd7, 0xa0, 0x30, 0x40, + 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00 + }, + { + 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 + } }; -static u8 boot_667_nor[] = { - 0x87, 0x78, 0xa2, 0x52, 0x09, 0xd7, 0xa0, 0x30, - 0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00 -}; - -static u8 boot_667_nand[] = { - 0x87, 0x78, 0xa2, 0x52, 0x09, 0xd7, 0xd0, 0x10, - 0xa0, 0x68, 0x23, 0x58, 0x0d, 0x05, 0x00, 0x00 +/* + * Bytes 6,8,9,11 change for NAND boot + */ +static u8 nand_boot[] = { + 0xd0, 0xa0, 0x68, 0x58 }; static int do_bootstrap(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { - u8 chip; - u8 *buf; - int cpu_freq; + u8 *buf, bNAND; + int x, y, nbytes, selcfg; + extern char console_buffer[]; - if (argc < 3) { + if (argc < 2) { printf("Usage:\n%s\n", cmdtp->usage); return 1; } - cpu_freq = simple_strtol(argv[1], NULL, 10); - if (!((cpu_freq == 533) || (cpu_freq == 667))) { - printf("Unsupported cpu-frequency - only 533 and 667 supported\n"); - return 1; - } - - /* use 0x52 as I2C EEPROM address for now */ - chip = 0x52; - - if ((strcmp(argv[2], "nor") != 0) && - (strcmp(argv[2], "nand") != 0)) { + if ((strcmp(argv[1], "nor") != 0) && + (strcmp(argv[1], "nand") != 0)) { printf("Unsupported boot-device - only nor|nand support\n"); return 1; } - if (strcmp(argv[2], "nand") == 0) { - switch (cpu_freq) { - default: - case 533: - buf = boot_533_nand; - break; - case 667: - buf = boot_667_nand; - break; + /* set the nand flag based on provided input */ + if ((strcmp(argv[1], "nand") == 0)) + bNAND = 1; + else + bNAND = 0; + + printf("Available configurations: \n\n"); + + if (bNAND) { + for(x = 0, y = 0; boot_configs[x][0] != 0; x++) { + /* filter on nand compatible */ + if (boot_configs[x][0] & NAND_COMPATIBLE) { + printf(" %d - %s\n", (y+1), config_labels[x]); + y++; + } } } else { - switch (cpu_freq) { - default: - case 533: - buf = boot_533_nor; - break; - case 667: - buf = boot_667_nor; - break; + for(x = 0, y = 0; boot_configs[x][0] != 0; x++) { + /* filter on nor compatible */ + if (boot_configs[x][0] & NOR_COMPATIBLE) { + printf(" %d - %s\n", (y+1), config_labels[x]); + y++; + } } } - if (i2c_write(chip, 0, 1, buf, 16) != 0) - printf("Error writing to EEPROM at address 0x%x\n", chip); + do { + nbytes = readline(" Selection [1-x / quit]: "); + + if (nbytes) { + if (strcmp(console_buffer, "quit") == 0) + return 0; + selcfg = simple_strtol(console_buffer, NULL, 10); + if ((selcfg < 1) || (selcfg > y)) + nbytes = 0; + } + } while (nbytes == 0); + + + y = (selcfg - 1); + + for (x = 0; boot_configs[x][0] != 0; x++) { + if (bNAND) { + if (boot_configs[x][0] & NAND_COMPATIBLE) { + if (y > 0) + y--; + else if (y < 1) + break; + } + } else { + if (boot_configs[x][0] & NOR_COMPATIBLE) { + if (y > 0) + y--; + else if (y < 1) + break; + } + } + } + + buf = &boot_configs[x][1]; + + if (bNAND) { + buf[6] = nand_boot[0]; + buf[8] = nand_boot[1]; + buf[9] = nand_boot[2]; + buf[11] = nand_boot[3]; + } + + /* check CPLD register +5 for PCI 66MHz flag */ + if (in8(CFG_BCSR_BASE + 5) & 0x01) + buf[5] += 0x10; + + if (i2c_write(I2C_EEPROM_ADDR, 0, 1, buf, 16) != 0) + printf("Error writing to EEPROM at address 0x%x\n", I2C_EEPROM_ADDR); udelay(CFG_EEPROM_PAGE_WRITE_DELAY_MS * 1000); printf("Done\n"); @@ -105,7 +214,7 @@ static int do_bootstrap(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) } U_BOOT_CMD( - bootstrap, 3, 0, do_bootstrap, + bootstrap, 2, 0, do_bootstrap, "bootstrap - program the I2C bootstrap EEPROM\n", - " - program the I2C bootstrap EEPROM\n" + " - strap to boot from NAND or NOR flash\n" ); From 6da0c5bd4a53e40eb4f7eb72a4c051ecabad783c Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Thu, 16 Aug 2007 09:54:51 +0200 Subject: [PATCH 134/259] Add missing rainier (PPC440GRx) target to MAKEALL and MAINTAINERs files Signed-off-by: Stefan Roese --- MAINTAINERS | 1 + MAKEALL | 1 + 2 files changed, 2 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index f812431b8..bb329ad7a 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -296,6 +296,7 @@ Stefan Roese ocotea PPC440GX p3p440 PPC440GP pcs440ep PPC440EP + rainier PPC440GRx sequoia PPC440EPx sycamore PPC405GPr taishan PPC440GX diff --git a/MAKEALL b/MAKEALL index 1219fb373..ea3751365 100755 --- a/MAKEALL +++ b/MAKEALL @@ -204,6 +204,7 @@ LIST_4xx=" \ PLU405 \ PMC405 \ PPChameleonEVB \ + rainier \ sbc405 \ sc3 \ sequoia \ From 9de469bd960cc1870bb40d6672ed42726b8b50d7 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Thu, 16 Aug 2007 10:18:33 +0200 Subject: [PATCH 135/259] ppc4xx: Only enable POST FPU test on Sequoia and not Rainier Signed-off-by: Stefan Roese --- include/configs/sequoia.h | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/include/configs/sequoia.h b/include/configs/sequoia.h index 3f75a441a..824a81240 100644 --- a/include/configs/sequoia.h +++ b/include/configs/sequoia.h @@ -343,6 +343,11 @@ #define CONFIG_CMD_USB #endif +#ifndef CONFIG_RAINIER +#define CFG_POST_FPU_ON CFG_POST_FPU +#else +#define CFG_POST_FPU_ON 0 +#endif /* POST support */ #define CONFIG_POST (CFG_POST_MEMORY | \ @@ -350,7 +355,7 @@ CFG_POST_UART | \ CFG_POST_I2C | \ CFG_POST_CACHE | \ - CFG_POST_FPU | \ + CFG_POST_FPU_ON | \ CFG_POST_ETHER | \ CFG_POST_SPR) From 2d78074d2e806edc380c1464eb9e5df335ece65e Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Fri, 22 Jun 2007 17:32:28 +0200 Subject: [PATCH 136/259] ppc7xx: Update CPCI750 board This small CPCI750 update extends the board specific command "show_config" to display the Marvell strapping registers and extends the PCI IDE controller. Signed-off-by: Reinhard Arlt Signed-off-by: Stefan Roese --- board/esd/cpci750/cpci750.c | 89 +++++++++++++++++++++++++++++++++++-- board/esd/cpci750/ide.c | 2 + 2 files changed, 87 insertions(+), 4 deletions(-) diff --git a/board/esd/cpci750/cpci750.c b/board/esd/cpci750/cpci750.c index 17e356894..298aa6a19 100644 --- a/board/esd/cpci750/cpci750.c +++ b/board/esd/cpci750/cpci750.c @@ -55,6 +55,71 @@ #define DP(x) #endif +static char show_config_tab[][15] = {{"PCI0DLL_2 "}, /* 31 */ + {"PCI0DLL_1 "}, /* 30 */ + {"PCI0DLL_0 "}, /* 29 */ + {"PCI1DLL_2 "}, /* 28 */ + {"PCI1DLL_1 "}, /* 27 */ + {"PCI1DLL_0 "}, /* 26 */ + {"BbEP2En "}, /* 25 */ + {"SDRAMRdDataDel"}, /* 24 */ + {"SDRAMRdDel "}, /* 23 */ + {"SDRAMSync "}, /* 22 */ + {"SDRAMPipeSel_1"}, /* 21 */ + {"SDRAMPipeSel_0"}, /* 20 */ + {"SDRAMAddDel "}, /* 19 */ + {"SDRAMClkSel "}, /* 18 */ + {"Reserved(1!) "}, /* 17 */ + {"PCIRty "}, /* 16 */ + {"BootCSWidth_1 "}, /* 15 */ + {"BootCSWidth_0 "}, /* 14 */ + {"PCI1PadsCal "}, /* 13 */ + {"PCI0PadsCal "}, /* 12 */ + {"MultiMVId_1 "}, /* 11 */ + {"MultiMVId_0 "}, /* 10 */ + {"MultiGTEn "}, /* 09 */ + {"Int60xArb "}, /* 08 */ + {"CPUBusConfig_1"}, /* 07 */ + {"CPUBusConfig_0"}, /* 06 */ + {"DefIntSpc "}, /* 05 */ + {0 }, /* 04 */ + {"SROMAdd_1 "}, /* 03 */ + {"SROMAdd_0 "}, /* 02 */ + {"DRAMPadCal "}, /* 01 */ + {"SInitEn "}, /* 00 */ + {0 }, /* 31 */ + {0 }, /* 30 */ + {0 }, /* 29 */ + {0 }, /* 28 */ + {0 }, /* 27 */ + {0 }, /* 26 */ + {0 }, /* 25 */ + {0 }, /* 24 */ + {0 }, /* 23 */ + {0 }, /* 22 */ + {"JTAGCalBy "}, /* 21 */ + {"GB2Sel "}, /* 20 */ + {"GB1Sel "}, /* 19 */ + {"DRAMPLL_MDiv_5"}, /* 18 */ + {"DRAMPLL_MDiv_4"}, /* 17 */ + {"DRAMPLL_MDiv_3"}, /* 16 */ + {"DRAMPLL_MDiv_2"}, /* 15 */ + {"DRAMPLL_MDiv_1"}, /* 14 */ + {"DRAMPLL_MDiv_0"}, /* 13 */ + {"GB0Sel "}, /* 12 */ + {"DRAMPLLPU "}, /* 11 */ + {"DRAMPLL_HIKVCO"}, /* 10 */ + {"DRAMPLLNP "}, /* 09 */ + {"DRAMPLL_NDiv_7"}, /* 08 */ + {"DRAMPLL_NDiv_6"}, /* 07 */ + {"CPUPadCal "}, /* 06 */ + {"DRAMPLL_NDiv_5"}, /* 05 */ + {"DRAMPLL_NDiv_4"}, /* 04 */ + {"DRAMPLL_NDiv_3"}, /* 03 */ + {"DRAMPLL_NDiv_2"}, /* 02 */ + {"DRAMPLL_NDiv_1"}, /* 01 */ + {"DRAMPLL_NDiv_0"}}; /* 00 */ + extern void flush_data_cache (void); extern void invalidate_l1_instruction_cache (void); extern flash_info_t flash_info[]; @@ -901,21 +966,37 @@ void board_prebootm_init () dcache_disable (); } - -int do_show_cfg(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) +int do_show_config(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) { unsigned int reset_sample_low; unsigned int reset_sample_high; + unsigned int l, l1, l2; GT_REG_READ(0x3c4, &reset_sample_low); GT_REG_READ(0x3d4, &reset_sample_high); printf("Reset configuration 0x%08x 0x%08x\n", reset_sample_low, reset_sample_high); + l2 = 0; + for (l=0; l<63; l++) { + if (show_config_tab[l][0] != 0) { + printf("%14s:%1x ", show_config_tab[l], + ((reset_sample_low >> (31 - (l & 0x1f)))) & 0x01); + l2++; + if ((l2 % 4) == 0) + printf("\n"); + } else { + l1++; + } + if (l == 32) + reset_sample_low = reset_sample_high; + } + printf("\n"); + return(0); } U_BOOT_CMD( - show_cfg, 1, 1, do_show_cfg, - "show_cfg- Show Marvell strapping register\n", + show_config, 1, 1, do_show_config, + "show_config - Show Marvell strapping register\n", "Show Marvell strapping register (ResetSampleLow ResetSampleHigh)\n" ); diff --git a/board/esd/cpci750/ide.c b/board/esd/cpci750/ide.c index 01b90c631..0adafe2d0 100644 --- a/board/esd/cpci750/ide.c +++ b/board/esd/cpci750/ide.c @@ -43,6 +43,8 @@ int ide_preinit (void) ide_bus_offset[l] = -ATA_STATUS; } devbusfn = pci_find_device (0x1103, 0x0004, 0); + if (devbusfn == -1) + devbusfn = pci_find_device (0x1095, 0x3114, 0); if (devbusfn != -1) { status = 0; From 8fb6e80c06849e3013ac5c9350d8ed9e52967991 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Thu, 16 Aug 2007 11:21:49 +0200 Subject: [PATCH 137/259] ppc4xx: Remove #warning in esd auto_update.c Signed-off-by: Stefan Roese --- board/esd/common/auto_update.c | 4 ---- 1 file changed, 4 deletions(-) diff --git a/board/esd/common/auto_update.c b/board/esd/common/auto_update.c index 62f6c2043..c4a095787 100644 --- a/board/esd/common/auto_update.c +++ b/board/esd/common/auto_update.c @@ -24,10 +24,6 @@ #include -#if defined(CONFIG_CMD_NAND) && !defined(CFG_NAND_LEGACY) -#warning CFG_NAND_LEGACY not defined in a file using the legacy NAND support! -#endif - #include #include #include From a5a38f4fd7e5366d706ff6a985f9b6715ddbc98b Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Thu, 16 Aug 2007 11:51:04 +0200 Subject: [PATCH 138/259] Minor Coding Style fix; Update CHANGELOG file. Signed-off-by: Wolfgang Denk --- CHANGELOG | 577 ++++++++++++++++++++++++++++++++++++++++++++++++++++ MAINTAINERS | 6 +- 2 files changed, 580 insertions(+), 3 deletions(-) diff --git a/CHANGELOG b/CHANGELOG index a83456814..da67d366c 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -1,3 +1,91 @@ +commit 2d78074d2e806edc380c1464eb9e5df335ece65e +Author: Stefan Roese +Date: Fri Jun 22 17:32:28 2007 +0200 + + ppc7xx: Update CPCI750 board + + This small CPCI750 update extends the board specific command + "show_config" to display the Marvell strapping registers and + extends the PCI IDE controller. + + Signed-off-by: Reinhard Arlt + Signed-off-by: Stefan Roese + +commit 30b52df9e906bf0e465916c2c6bb5192b438e0b8 +Author: Jon Loeliger +Date: Wed Aug 15 11:55:35 2007 -0500 + + 86xx: Fix lingering CFG_CMD_* references in sbc8641d.h + + Remove a leftover in net/tftp.c while we're at it. + + Signed-off-by: Jon Loeliger + +commit 4ce917742b1e48faa9bf9a9757545e56fb4cfe44 +Author: Jon Loeliger +Date: Wed Aug 15 12:20:40 2007 -0500 + + Move the MPC8641HPCN board under board/freescale. + + Minor path corrections needed to ensure buildability. + + Signed-off-by: Jon Loeliger + +commit 8662577fe36fdb6a44b55b998d9daac6392a736a +Author: Jon Loeliger +Date: Wed Aug 15 11:46:22 2007 -0500 + + 86xx: Fix lingering CFG_CMD_* references in sbc8641d.h + + Remove a leftover in net/tftp.c while we're at it. + + Signed-off-by: Jon Loeliger + +commit 210f463c71917b7a4495c2103c228b9c179ae64d +Author: Jerry Van Baren +Date: Wed Aug 15 11:13:15 2007 -0400 + + Fix where the #ifdef CFG_BOOTMAPSZ is placed. + + Commit 073e1b509980cefe6f53c2d7fbbcd135df1e3924 "Fix initrd/dtb + interaction" put the new code outside of the #if defined(CONFIG_OF_LIBFDT) + when it should have gone inside of the conditional. As a result, it + broke non-LIBFDT board builds. + + Also added a missing "not." to the comment. + + Signed-off-by: Gerald Van Baren + +commit 594e79838ce5078a90d0c27abb2b2d61d5f8e8a7 +Author: Ed Swarthout +Date: Tue Aug 14 14:06:45 2007 -0500 + + Fix malloc size error in ahci_init_one. + + Typically this causes scsi init to corrupt the + devlist and break the coninfo command. + Fix a compiler size warning. + + Signed-off-by: Jason Jin + Signed-off-by: Ed Swarthout + Acked-by: Andy Fleming + +commit b361acd64fd2525c081b9b288b0804efe209c0e9 +Author: ksi@koi8.net +Date: Tue Aug 14 10:02:16 2007 -0700 + + TI DaVinci - fix unsupported %hhx format + + Signed-off-by: Sergey Kubushyn + +commit f01dbb5424a81453c81190dd30e945891466f621 +Author: Wolfgang Denk +Date: Tue Aug 14 18:42:36 2007 +0200 + + Coding style cleanup. Update CHANGELOG. + + Signed-off-by: Wolfgang Denk + commit 073e1b509980cefe6f53c2d7fbbcd135df1e3924 Author: Andy Fleming Date: Tue Aug 14 10:32:59 2007 -0500 @@ -20,6 +108,50 @@ Date: Tue Aug 14 15:40:00 2007 +0100 Supply spi interface in at45.c +commit 4ce846ec59f36b85d6644a769690ad3feb667575 +Author: Stefan Roese +Date: Tue Aug 14 15:12:01 2007 +0200 + + POST: Fix merge problem + + Signed-off-by: Stefan Roese + +commit 429d9571f60631ae8a2fe12b11be4c75b0c2b37c +Author: Stefan Roese +Date: Tue Aug 14 15:03:17 2007 +0200 + + Coding style cleanup + + Signed-off-by: Stefan Roese + +commit 779e975117a75e91fcebe226a63104dbfb924ab1 +Author: Stefan Roese +Date: Tue Aug 14 14:44:41 2007 +0200 + + ppc4xx: Add initial Zeus (PPC405EP) board support + + Signed-off-by: Stefan Roese + +commit c5a172a5fd636c12467429e3f7910e53773979c6 +Author: Stefan Roese +Date: Tue Aug 14 14:41:55 2007 +0200 + + POST: Add option for external ethernet loopback test + + When CFG_POST_ETHER_EXT_LOOPBACK is defined, the ethernet POST + is not done using an internal loopback connection, but by assuming + that an external loopback connector is plugged into the board. + + Signed-off-by: Stefan Roese + +commit eb2b4010ae426245172988804ee8d9193fb41038 +Author: Stefan Roese +Date: Tue Aug 14 14:39:44 2007 +0200 + + POST: Add ppc405 support to cache and UART POST + + Signed-off-by: Stefan Roese + commit 0c42f36f15074bd9808a7dbd7ef611fad9bf537c Author: Peter Pearse Date: Tue Aug 14 10:46:32 2007 +0100 @@ -391,6 +523,17 @@ Date: Wed Jun 27 13:34:26 2007 +0200 Signed-off-by: Haavard Skinnemoen Acked-by: Hans-Christian Egtvedt +commit 273db7e1bdd1937e32f1d4507321bb721ebd3118 +Author: Stefan Roese +Date: Mon Aug 13 09:05:33 2007 +0200 + + ppc4xx: Fix problem in PLL clock calculation + + This patch was originall provided by David Mitchell + and fixes a bug in the PLL clock calculation. + + Signed-off-by: Stefan Roese + commit 9986bc3e40e899bea372a99a2bca4071bdf2e24b Author: Wolfgang Denk Date: Sun Aug 12 21:34:50 2007 +0200 @@ -849,6 +992,14 @@ Date: Thu Aug 2 14:42:20 2007 -0500 Signed-off-by: Ed Swarthout Signed-off-by: Jon Loeliger +commit 35d22f957a85a22bb3cd1ad084fa5404620d1c42 +Author: Stefan Roese +Date: Fri Aug 10 10:42:25 2007 +0200 + + Coding style cleanup + + Signed-off-by: Stefan Roese + commit 3a6d56c20989fe27360afe743bd2a7ad4d76e48f Author: Dirk Behme Date: Thu Aug 2 17:42:08 2007 +0200 @@ -873,6 +1024,105 @@ Date: Thu Aug 2 17:41:14 2007 +0200 Signed-off-by: Dirk Behme +commit 157cda4d0c3d592ccbb19bbfc07d9251894f0894 +Author: Niklaus Giger +Date: Fri Jul 27 11:31:22 2007 +0200 + + Add PPC4xx-HCU4 and HCU5 boards: HCU5 files + + Signed-off-by: Niklaus Giger + +commit 6e5de26c6e7580faf16e87745cd488b92b492d0c +Author: Niklaus Giger +Date: Fri Jul 27 11:30:33 2007 +0200 + + Add PPC4xx-HCU4 and HCU5 boards: HCU4 files + + Signed-off-by: Niklaus Giger + +commit e8397fc78c9394d71de233a4d810fbc9047e4c76 +Author: Niklaus Giger +Date: Fri Jul 27 11:38:26 2007 +0200 + + Add PPC4xx-HCU4 and HCU5 boards: common files + + Signed-off-by: Niklaus Giger + +commit ac982ea5a4f2f993efcf52dca122f5a59df047d8 +Author: Niklaus Giger +Date: Fri Jul 27 11:28:44 2007 +0200 + + Add PPC4xx-HCU4 and HCU5 boards: make related + + Signed-off-by: Niklaus Giger + +commit 137fdd9f474ecb853efdace5200576308c67f18d +Author: Niklaus Giger +Date: Fri Jul 27 11:28:03 2007 +0200 + + Add PPC4xx-HCU4 and HCU5 boards: HCU5 config + + Signed-off-by: Niklaus Giger + +commit 714bc55b35b6f6a65cc8740a3842a543e88cdef2 +Author: Niklaus Giger +Date: Fri Jul 27 11:27:15 2007 +0200 + + Add PPC4xx-HCU4 and HCU5 boards: HCU4 config + + Signed-off-by: Niklaus Giger + +commit 1894dd381124bdbfbdae7cf3a6ca52a8eb1f4421 +Author: Niklaus Giger +Date: Fri Jul 27 11:25:31 2007 +0200 + + Add PPC4xx-HCU4 and HCU5 boards: READMEs + + Signed-off-by: Niklaus Giger + +commit 641cca9569ce351ddb287fd3343d8b1dcb591db4 +Author: Niklaus Giger +Date: Fri Jul 27 11:37:40 2007 +0200 + + Add PPC4xx-HCU4 and HCU5 boards: Infrastructure + + This series of patches adds support for 2 boards from Netstal Maschinen. + + The HCU4 has a PPC405Gpr and + the HCU5 has a PPC440EPX. + + The HCU4 has a somehow complicated flash setup, as the booteprom is + only 8 bits and the CFI 16 bits wide, which makes it impossible to use a more + elegant solution. + + The HCU5 has only a booteprom as the whole code will be downloaded from a + different board which has HD, CD-ROM, etc and where all code is stored. + + This is my third try. I incorporated all suggestions made by Wolfgang and Stefan. + Thanks them a lot. + + Signed-off-by: Niklaus Giger + +commit 3e4c90c6233618fc1806e63fde68df5f3d6a0171 +Author: Stefan Roese +Date: Fri Aug 10 08:42:55 2007 +0200 + + ppc4xx: Update lwmon5 POST configuration + + Signed-off-by: Stefan Roese + +commit 29cb25da56afe18cf5e7072a92a9d98ea8af1fd4 +Author: Yuri Tikhonov +Date: Fri Aug 10 08:25:22 2007 +0200 + + POST: Add ppc4xx UART POST support without external uart clock (lwmon5) + + The patch adds support for UART POST on ppc44x-based boards with no + external serial clocks installed. + + Signed-off-by: Yuri Tikhonov + Acked-by: Stefan Roese + commit 99c2fdab91bc633e46fb41dbaa629f87ccf6e00f Author: Kim Phillips Date: Mon Aug 6 18:18:34 2007 -0500 @@ -1169,6 +1419,17 @@ Date: Mon Aug 6 23:21:05 2007 +0200 Signed-off-by: Wolfgang Denk +commit 537223afa61f64480df31ce440a9cb386df4a814 +Author: Stefan Roese +Date: Mon Aug 6 21:10:17 2007 +0200 + + ppc4xx: Update AMCC Bamboo README doc/README.bamboo + + As suggested by Eugene O'Brien , + here an updated Bamboo README. + + Signed-off-by: Stefan Roese + commit 9c7e4b06214db61bb21f1bcbe57c97519669baae Author: Wolfgang Denk Date: Mon Aug 6 02:17:36 2007 +0200 @@ -1316,6 +1577,42 @@ Date: Thu Aug 2 10:11:18 2007 +0200 Minor cleanup of _nand build rules. +commit 9ca8d79de096c65b9b9c867259b3ff4685f775ef +Author: Stefan Roese +Date: Thu Aug 2 08:33:56 2007 +0200 + + ppc4xx: Code cleanup + + Signed-off-by: Stefan Roese + +commit c92409812206ac67a7fa7aae298539a9c3804a46 +Author: Grzegorz Bernacki +Date: Tue Jul 31 18:51:48 2007 +0200 + + [ppc440SPe] Graceful recovery from machine check during PCIe configuration + + During config transactions on the PCIe bus an attempt to scan for a + non-existent device can lead to a machine check exception with certain + peripheral devices. In order to avoid crashing in such scenarios the + instrumented versions of the config cycle read routines are introduced, so + the exceptions fixups framework can gracefully recover. + + Signed-off-by: Grzegorz Bernacki + Acked-by: Rafal Jaworowski + +commit dec99558b9ea75a37940d07f41a3565a50b54ad1 +Author: Rafal Jaworowski +Date: Tue Jul 31 18:19:54 2007 +0200 + + [ppc4xx] Separate settings for PCIe bus numbering on 440SPe rev.A + + This brings back separate settings for PCIe bus numbers depending on chip + revision, which got eliminated in 2b393b0f0af8402ef43b25c1968bfd29714ddffa + commit. 440SPe rev. A does NOT work properly with the same settings as for + the rev. B (no devices are seen on the bus during enumeration). + + Signed-off-by: Rafal Jaworowski + commit cdd917a43da6fa7fc8f54a3cc9f420ce5ecf3197 Author: Wolfgang Denk Date: Thu Aug 2 00:48:45 2007 +0200 @@ -1324,6 +1621,55 @@ Date: Thu Aug 2 00:48:45 2007 +0200 Signed-off-by: Wolfgang Denk +commit d2f68006627eda6cb6c7f364bddf621dbfd2fc68 +Author: Eugene OBrien +Date: Tue Jul 31 10:24:56 2007 +0200 + + ppc4xx: Update AMCC Bamboo 440EP support + + Changed storage type of cfg_simulate_spd_eeprom to const + Changed storage type of gpio_tab to stack storage + (Cannot access global data declarations in .bss until afer code relocation) + + Improved SDRAM tests to catch problems where data is not uniquely addressable + (e.g. incorrectly programmed SDRAM row or columns) + + Added CONFIG_PROG_SDRAM_TLB to support Bamboo SIMM/DIMM modules + Fixed AM29LV320DT (OpCode Flash) sector map + + Signed-off-by: Eugene OBrien + Signed-off-by: Stefan Roese + +commit ea9f6bce383cc9fbcdee28b5836109b1a6dba574 +Author: Stefan Roese +Date: Tue Jul 31 08:37:01 2007 +0200 + + ppc4xx: Update 440EPx lwmon5 board support + + - Clear ECC status regs after ECC POST test + - Set dcbz for ECC generation with caches enabled as default + - Code cleanup + + Signed-off-by: Stefan Roese + +commit 27a528fb41433c4c1e2b5d6bd3fd8d78606fc724 +Author: Stefan Roese +Date: Mon Jul 30 11:04:57 2007 +0200 + + ppc4xx: Only print ECC related info when the error bis are set + + Signed-off-by: Stefan Roese + +commit e36220a4baf1f188ba60f17e9d0f043069b1362a +Author: Matthias Fuchs +Date: Fri Jul 27 16:44:31 2007 +0200 + + new FPGA image for PLU405 board + + new FPGA image for PLU405 board with improved CompactFlash timing + + Signed-off-by: Matthias Fuchs + commit 8993e54b6f397973794f3d6f47d3b3c0c98dd4f6 Author: Rafal Jaworowski Date: Fri Jul 27 14:43:59 2007 +0200 @@ -1351,6 +1697,73 @@ Date: Fri Jul 27 14:22:04 2007 +0200 Signed-off-by: Rafal Jaworowski +commit d4024bb72dd81695ec099b2199eda0d27c623e62 +Author: John Otken +Date: Thu Jul 26 17:49:11 2007 +0200 + + ppc4xx: Add support for AMCC 405EP Taihu board + + Signed-off-by: John Otken + +commit b66091de6c7390620312c2501db23d8391e7cabb +Author: Anatolij Gustschin +Date: Thu Jul 26 15:08:01 2007 +0200 + + ppc4xx: lwmon5: Update Lime initialization + + Change Lime SDRAM initialization to now support 100MHz and + 133MHz (if enabled). Also the framebuffer is initialized to + display a blue rectangle with a white border. + + Signed-off-by: Anatolij Gustschin + Signed-off-by: Stefan Roese + +commit 9f24a808f17fc0f37b7fb4805f734741335caecc +Author: Stefan Roese +Date: Tue Jul 24 09:52:52 2007 +0200 + + ppc4xx: lwmon5: Support for 128 MByte NOR FLASH added + + The used Intel NOR FLASH chips have internally two dies, and are now + treated as two seperate chips. + + Signed-off-by: Stefan Roese + +commit aedf5bde179ecfbd0a96130d18996a96518b785f +Author: Stefan Roese +Date: Tue Jul 24 07:20:09 2007 +0200 + + ppc4xx: Fix lwmon5 interrupt controller setup (polarity, trigger...) + + As suggested by Hakan Eryigit, here an updated setup for the lwmon5 + interrupt controller. + + Signed-off-by: Stefan Roese + +commit a71d96eac8130b53a91f93cd10c70fca0db18d52 +Author: Stefan Roese +Date: Fri Jul 20 15:03:44 2007 +0200 + + ppc4xx: Fix bug with default GPIO output value + + As spotted by Matthias Fuchs, the default output values for all GPIO1 + outputs were not setup correctly. This patch fixes this issue. + + Signed-off-by: Stefan Roese + +commit 531e3e8b831f357056448fa573137d5fb37000fd +Author: Pavel Kolesnikov +Date: Fri Jul 20 15:03:03 2007 +0200 + + POST: Add ECC POST for the lwmon5 board + + This patch adds ECC Post test for the Lwmon5 board based + on PPC440EPx to U-Boot. + + Signed-off-by: Pavel Kolesnikov + Acked-by: Yuri Tikhonov + Acked-by: Stefan Roese + commit cc3023b9f95d7ac959a764471a65001062aecf41 Author: Rafal Jaworowski Date: Thu Jul 19 17:12:28 2007 +0200 @@ -1362,6 +1775,58 @@ Date: Thu Jul 19 17:12:28 2007 +0200 Signed-off-by: Rafal Jaworowski +commit 8848ec858f74ed6dab06fb6d5ddc933e0a1328bf +Author: Stefan Roese +Date: Mon Jul 16 10:02:12 2007 +0200 + + ppc4xx: Code cleanup + + Signed-off-by: Stefan Roese + +commit 2a49fc17d09020e7ebd9536694d99d20e419fcb8 +Author: Stefan Roese +Date: Mon Jul 16 10:01:38 2007 +0200 + + ppc4xx: AMCC Luan uses the new boardspecific DDR2 controller setup + + Signed-off-by: Stefan Roese + +commit df3f17422aeb03fb81a7ac8c78d2b05d05aa4cf9 +Author: Stefan Roese +Date: Mon Jul 16 10:00:43 2007 +0200 + + ppc4xx: Support for Yucca board with 440SPe Rev A added to 44x_spd_ddr2.c + + The new boardspecific DDR2 controller configuration is used for the Yucca + board. Now the Yucca board with 440SPe Rev. A chips is also supported. + + Signed-off-by: Stefan Roese + +commit 6ed14addf97c8cd8f531e9ae7b2d3e222fffd53e +Author: Stefan Roese +Date: Mon Jul 16 09:57:00 2007 +0200 + + ppc4xx: Add new weak functions to support boardspecific DDR2 configuration + + The new "weak" functions ddr_wrdtr() and ddr_clktr() are added to better + support non default, boardspecific DDR(2) controller configuration. + + Signed-off-by: Stefan Roese + +commit 5743a9207a370b90f09b20ebd61167c806b937f3 +Author: Stefan Roese +Date: Mon Jul 16 08:53:51 2007 +0200 + + ppc4xx: Add remove_tlb() function to remove a mem area from TLB setup + + The new function remove_tlb() can be used to remove the TLB's used to + map a specific memory region. This is especially useful for the DDR(2) + setup routines which configure the SDRAM area temporarily as a cached + area (for speedup on auto-calibration and ECC generation) and later + need this area uncached for normal usage. + + Signed-off-by: Stefan Roese + commit 3a6cab844cf74f76639d795e0be8717e02c86af7 Author: Wolfgang Denk Date: Sat Jul 14 22:51:02 2007 +0200 @@ -1393,6 +1858,17 @@ Date: Fri Jul 13 08:26:05 2007 +0200 Signed-off-by: Heiko Schocher +commit a2e1c7098cf9574386b0c96841dfc8ea5cc93578 +Author: Stefan Roese +Date: Thu Jul 12 16:32:08 2007 +0200 + + ppc4xx: Change receive buffer handling in the 4xx emac driver + + This change fixes a bug in the receive buffer handling, that + could lead to problems upon high network traffic (broadcasts...). + + Signed-off-by: Stefan Roese + commit 239f05ee4dd4cfe0b50f251b533dcebe9e67c360 Author: Wolfgang Denk Date: Thu Jul 12 01:45:34 2007 +0200 @@ -1975,6 +2451,50 @@ Date: Tue Jul 10 00:01:28 2007 +0200 Signed-off-by: Wolfgang Denk +commit c8603cfbd4573379a6076c9c208545ba2bbf019a +Author: Stefan Roese +Date: Mon Jul 9 11:00:24 2007 +0200 + + Small coding style cleanup + + Signed-off-by: Stefan Roese + +commit 0f92c7e7c9a62755b1457d3c46f93c8c1f6c19fc +Author: Matthias Fuchs +Date: Mon Jul 9 10:10:08 2007 +0200 + + Migrate esd 405EP boards to new NAND subsystem + + Remove unused CFG_NAND_LEGACY define + + These boards to not have NAND. + + Signed-off-by: Matthias Fuchs + +commit bd84ee4c2020c3a6861f4bb2e7ea0fb49f82e803 +Author: Matthias Fuchs +Date: Mon Jul 9 10:10:06 2007 +0200 + + Migrate esd 405EP boards to new NAND subsystem + + Migrate esd 405EP boards to new NAND subsystem + + -cleanup + -use correct io accessors (in/out_be32()) + + Signed-off-by: Matthias Fuchs + +commit e09f7ab5749c345f924da272bea0521a73af5b11 +Author: Matthias Fuchs +Date: Mon Jul 9 10:10:04 2007 +0200 + + Migrate esd 405EP boards to new NAND subsystem + + This patch prepares the migration from the legacy NAND driver + to U-Boot's new NAND subsystem for esd boards. + + Signed-off-by: Matthias Fuchs + commit c3517f919d0f61650cf3027fd4faf0f631142f6c Author: Jon Loeliger Date: Sun Jul 8 18:10:08 2007 -0500 @@ -2162,6 +2682,41 @@ Date: Thu Jul 5 19:13:52 2007 -0500 Signed-off-by: Jon Loeliger +commit 10e038932f22ee80ebd53de312531e70e6590a2f +Author: Thomas Knobloch +Date: Fri Jul 6 14:58:39 2007 +0200 + + [NAND] Bad block skipping for command nboot + + The old implementation of command nboot does not support reading the image from + NAND flash with skipping of bad blocks. The patch implements a new version of + the nboot command: by calling nboot.jffs2 from the u-boot command line the + command will load the image from NAND flash with respect to bad blocks (by using + nand_read_opts()). This is similar to e.g. the NAND read command: "nand + read.jffs2 ...". + + Signed-off-by: Thomas Knobloch + Signed-off-by: Stefan Roese + +commit 334043f601a90ac53e5ecc846fbb73a1ef38cb1f +Author: Stefan Roese +Date: Fri Jul 6 12:26:51 2007 +0200 + + ppc4xx: Update lwmon5 default environment + + Signed-off-by: Stefan Roese + +commit 5d187430a055d62f17ca84d75e7245439d1f7e75 +Author: Stefan Roese +Date: Fri Jul 6 11:48:24 2007 +0200 + + ppc4xx: Update lwmon5 board + + Add unlock=yes environment variable to default variables to unlock + the CFI flash by default. + + Signed-off-by: Stefan Roese + commit 6b0a174a1e6f55e1f5a1fbb223cdad7645a4646e Author: Stefan Roese Date: Fri Jul 6 09:45:47 2007 +0200 @@ -3151,6 +3706,18 @@ Date: Fri Jun 22 14:58:04 2007 +0200 - adapt to the more generic EXCEPTION_PROLOG and CRIT_EXCEPTION macros - minor 4xx cleanup +commit d677b32855f577ae2690dcd64a172cdd706e0ffc +Author: Mike Frysinger +Date: Fri Jun 22 10:34:12 2007 +0200 + + [patch] add nand_init() prototype to nand.h + + since nand_init() is expected to be called by other parts of u-boot, there + should be a prototype for it in nand.h + + Signed-off-by: Mike Frysinger + Signed-off-by: Stefan Roese + commit 83b4cfa3d629dff0264366263c5e94d9a50ad80b Author: Wolfgang Denk Date: Wed Jun 20 18:14:24 2007 +0200 @@ -3767,6 +4334,16 @@ Date: Sun May 27 16:51:48 2007 +0200 Signed-off-by: Marian Balakowicz Acked-by: Bartlomiej Sieka +commit 7ebb4479b07ff294eb4d76e420753a0349f7c93b +Author: Ulf Samuelsson +Date: Thu May 24 12:12:47 2007 +0200 + + [PATCH][NAND] Define the Vendor Id for Micron NAND Flash + + Signed-off-by: Ulf Samuelsson + Signed-off-by: Ladislav Michl + Signed-off-by: Stefan Roese + commit d756894722c888d09a9fa1df8323753772d3dcce Author: Stefan Roese Date: Thu May 24 09:49:00 2007 +0200 diff --git a/MAINTAINERS b/MAINTAINERS index f812431b8..d5249e515 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -158,12 +158,12 @@ Matthias Fuchs VOH405 PPC405EP VOM405 PPC405EP WUH405 PPC405EP - CMS700 PPC405EP + CMS700 PPC405EP Niklaus Giger - HCU4 PPC405GPr - HCU5 PPC440EPx + HCU4 PPC405GPr + HCU5 PPC440EPx Frank Gottschling From 002275a3ed8b114885f6702d6d544d0780dfe689 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Thu, 16 Aug 2007 08:54:10 +0200 Subject: [PATCH 139/259] Bios emulator - fix microblaze toolchain problem microblaze CPU have problem with bios_emulator code. Microblaze toolchain doesn't support PRAGMA PACK. Signed-off-by: Michal Simek --- drivers/bios_emulator/besys.c | 5 ++++- drivers/bios_emulator/bios.c | 5 ++++- drivers/bios_emulator/biosemu.c | 4 +++- drivers/bios_emulator/x86emu/debug.c | 4 +++- drivers/bios_emulator/x86emu/decode.c | 5 +++-- drivers/bios_emulator/x86emu/ops.c | 4 +++- drivers/bios_emulator/x86emu/ops2.c | 4 +++- drivers/bios_emulator/x86emu/prim_ops.c | 5 ++++- drivers/bios_emulator/x86emu/sys.c | 4 +++- 9 files changed, 30 insertions(+), 10 deletions(-) diff --git a/drivers/bios_emulator/besys.c b/drivers/bios_emulator/besys.c index 4c4bc8d7b..8f1d8b29d 100644 --- a/drivers/bios_emulator/besys.c +++ b/drivers/bios_emulator/besys.c @@ -47,9 +47,12 @@ * ****************************************************************************/ -#include "biosemui.h" +#include #if defined(CONFIG_BIOSEMU) + +#include "biosemui.h" + /*------------------------- Global Variables ------------------------------*/ #ifndef __i386__ diff --git a/drivers/bios_emulator/bios.c b/drivers/bios_emulator/bios.c index 7aa1bfb2e..70e9ce143 100644 --- a/drivers/bios_emulator/bios.c +++ b/drivers/bios_emulator/bios.c @@ -41,9 +41,12 @@ * ****************************************************************************/ -#include "biosemui.h" +#include #if defined(CONFIG_BIOSEMU) + +#include "biosemui.h" + /*----------------------------- Implementation ----------------------------*/ /**************************************************************************** diff --git a/drivers/bios_emulator/biosemu.c b/drivers/bios_emulator/biosemu.c index 4c3aedf41..ccfc872f7 100644 --- a/drivers/bios_emulator/biosemu.c +++ b/drivers/bios_emulator/biosemu.c @@ -45,11 +45,13 @@ * ****************************************************************************/ -#include "biosemui.h" #include +#include #if defined(CONFIG_BIOSEMU) +#include "biosemui.h" + BE_sysEnv _BE_env = {{0}}; static X86EMU_memFuncs _BE_mem __attribute__((section(".got2"))) = { BE_rdb, diff --git a/drivers/bios_emulator/x86emu/debug.c b/drivers/bios_emulator/x86emu/debug.c index 915739c5b..5cbcc9501 100644 --- a/drivers/bios_emulator/x86emu/debug.c +++ b/drivers/bios_emulator/x86emu/debug.c @@ -37,11 +37,13 @@ * ****************************************************************************/ -#include "x86emu/x86emui.h" #include +#include #if defined(CONFIG_BIOSEMU) +#include "x86emu/x86emui.h" + /*----------------------------- Implementation ----------------------------*/ #ifdef DEBUG diff --git a/drivers/bios_emulator/x86emu/decode.c b/drivers/bios_emulator/x86emu/decode.c index 879f0a06d..7a9a1ddbf 100644 --- a/drivers/bios_emulator/x86emu/decode.c +++ b/drivers/bios_emulator/x86emu/decode.c @@ -36,11 +36,12 @@ * instruction decoding and accessess of immediate data via IP. etc. * ****************************************************************************/ - -#include "x86emu/x86emui.h" +#include #if defined(CONFIG_BIOSEMU) +#include "x86emu/x86emui.h" + /*----------------------------- Implementation ----------------------------*/ /**************************************************************************** diff --git a/drivers/bios_emulator/x86emu/ops.c b/drivers/bios_emulator/x86emu/ops.c index d334fb5b1..a77bd9b49 100644 --- a/drivers/bios_emulator/x86emu/ops.c +++ b/drivers/bios_emulator/x86emu/ops.c @@ -75,10 +75,12 @@ * ****************************************************************************/ -#include "x86emu/x86emui.h" +#include #if defined(CONFIG_BIOSEMU) +#include "x86emu/x86emui.h" + /*----------------------------- Implementation ----------------------------*/ /* constant arrays to do several instructions in just one function */ diff --git a/drivers/bios_emulator/x86emu/ops2.c b/drivers/bios_emulator/x86emu/ops2.c index 81c0d49a3..d6a210c97 100644 --- a/drivers/bios_emulator/x86emu/ops2.c +++ b/drivers/bios_emulator/x86emu/ops2.c @@ -44,10 +44,12 @@ * ****************************************************************************/ -#include "x86emu/x86emui.h" +#include #if defined(CONFIG_BIOSEMU) +#include "x86emu/x86emui.h" + /*----------------------------- Implementation ----------------------------*/ /**************************************************************************** diff --git a/drivers/bios_emulator/x86emu/prim_ops.c b/drivers/bios_emulator/x86emu/prim_ops.c index c1152eae3..2a254a4e6 100644 --- a/drivers/bios_emulator/x86emu/prim_ops.c +++ b/drivers/bios_emulator/x86emu/prim_ops.c @@ -97,11 +97,14 @@ * ****************************************************************************/ +#include + #define PRIM_OPS_NO_REDEFINE_ASM -#include "x86emu/x86emui.h" #if defined(CONFIG_BIOSEMU) +#include "x86emu/x86emui.h" + /*------------------------- Global Variables ------------------------------*/ static u32 x86emu_parity_tab[8] = diff --git a/drivers/bios_emulator/x86emu/sys.c b/drivers/bios_emulator/x86emu/sys.c index 566389f58..dd44ff1e7 100644 --- a/drivers/bios_emulator/x86emu/sys.c +++ b/drivers/bios_emulator/x86emu/sys.c @@ -39,10 +39,12 @@ * ****************************************************************************/ -#include "x86emu/x86emui.h" +#include #if defined(CONFIG_BIOSEMU) +#include "x86emu/x86emui.h" + /*------------------------- Global Variables ------------------------------*/ X86EMU_sysEnv _X86EMU_env; /* Global emulator machine state */ From 78f9fef7f406078c8bf7191e665a73f795157746 Mon Sep 17 00:00:00 2001 From: Scott Wood Date: Wed, 15 Aug 2007 15:46:46 -0500 Subject: [PATCH 140/259] mpc885ads: Don't define CONFIG_BZIP2. bzip2 requires a significant chunk of malloc space, and there isn't enough room on mpc885ads (with only 8MB RAM) for both bzip2's malloc area and a downloaded image at 0x400000. Signed-off-by: Scott Wood --- board/fads/fads.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/board/fads/fads.h b/board/fads/fads.h index c6f7ccde0..a7fe2e901 100644 --- a/board/fads/fads.h +++ b/board/fads/fads.h @@ -71,7 +71,10 @@ #undef CONFIG_BOOTARGS #undef CONFIG_WATCHDOG /* watchdog disabled */ + +#if !defined(CONFIG_MPC885ADS) #define CONFIG_BZIP2 /* include support for bzip2 compressed images */ +#endif /* * New MPC86xADS and MPC885ADS provide two Ethernet connectivity options: From 10aaf716cb0dc6614df54ef78bed5144afd23ef8 Mon Sep 17 00:00:00 2001 From: Andy Fleming Date: Wed, 15 Aug 2007 17:30:56 -0500 Subject: [PATCH 141/259] Fix of_data copying for CONFIG_OF_FLAT_TREE-using boards The fix, "Fix where the #ifdef CFG_BOOTMAPSZ is placed" neglected to *also* put the code inside the similar #ifdef for CONFIG_OF_FLAT_TREE. Signed-off-by: Andy Fleming --- common/cmd_bootm.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/common/cmd_bootm.c b/common/cmd_bootm.c index df1d0380d..90e3f8b9a 100644 --- a/common/cmd_bootm.c +++ b/common/cmd_bootm.c @@ -987,6 +987,15 @@ do_bootm_linux (cmd_tbl_t *cmdtp, int flag, #endif #endif /* CONFIG_OF_LIBFDT */ #if defined(CONFIG_OF_FLAT_TREE) +#ifdef CFG_BOOTMAPSZ + /* + * The blob must be within CFG_BOOTMAPSZ, + * so we flag it to be copied if it is not. + */ + if (of_flat_tree >= (char *)CFG_BOOTMAPSZ) + of_data = of_flat_tree; +#endif + /* move of_flat_tree if needed */ if (of_data) { ulong of_start, of_len; From ec7238229507e7f47533a611ea8c53319d234cf3 Mon Sep 17 00:00:00 2001 From: Andy Fleming Date: Wed, 15 Aug 2007 20:03:13 -0500 Subject: [PATCH 142/259] Add support for building all boards with a TSEC Changes to the TSEC driver affect almost all 83xx, 85xx, and 86xx boards. Now we can do a MAKEALL test on all of them! Signed-off-by: Andy Fleming --- MAKEALL | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/MAKEALL b/MAKEALL index 1219fb373..9f47f5f85 100755 --- a/MAKEALL +++ b/MAKEALL @@ -358,6 +358,12 @@ LIST_74xx=" \ ZUMA \ " +LIST_TSEC=" \ + ${LIST_85xx} \ + ${LIST_86xx} \ + ${LIST_83xx} \ +" + LIST_7xx=" \ BAB7xx \ CPCI750 \ @@ -672,7 +678,7 @@ do mips|mips_el| \ nios|nios2| \ ppc|5xx|5xxx|512x|8xx|8220|824x|8260|83xx|85xx|86xx|4xx|7xx|74xx| \ - x86|I486) + x86|I486|TSEC) for target in `eval echo '$LIST_'${arg}` do build_target ${target} From 3a79013e2adda53332dfd0b511066a805e929a9d Mon Sep 17 00:00:00 2001 From: Andy Fleming Date: Wed, 15 Aug 2007 20:03:25 -0500 Subject: [PATCH 143/259] Define tsec flag values in config files The tsec_info structure and array has a "flags" field for each ethernet controller. This field is the only reason there are settings. Switch to defining TSECn_FLAGS for each controller in the config header, and we can greatly simplify the array, and also simplify the addition of future boards. Signed-off-by: Andy Fleming --- drivers/tsec.c | 30 +++++++++++------------------- include/configs/MPC8313ERDB.h | 2 ++ include/configs/MPC8349EMDS.h | 2 ++ include/configs/MPC8349ITX.h | 2 ++ include/configs/MPC8540ADS.h | 3 +++ include/configs/MPC8540EVAL.h | 4 ++++ include/configs/MPC8541CDS.h | 5 ++--- include/configs/MPC8544DS.h | 8 +++----- include/configs/MPC8548CDS.h | 4 ++++ include/configs/MPC8555CDS.h | 5 ++--- include/configs/MPC8560ADS.h | 3 ++- include/configs/MPC8568MDS.h | 6 +++--- include/configs/MPC8641HPCN.h | 4 ++++ include/configs/PM854.h | 3 +++ include/configs/PM856.h | 3 ++- include/configs/TQM834x.h | 2 ++ include/configs/TQM85xx.h | 3 +++ include/configs/sbc8349.h | 2 ++ include/configs/sbc8641d.h | 4 ++++ include/configs/stxgp3.h | 3 ++- include/configs/stxssa.h | 3 ++- 21 files changed, 64 insertions(+), 37 deletions(-) diff --git a/drivers/tsec.c b/drivers/tsec.c index fd21ed4ed..1df8f7dc2 100644 --- a/drivers/tsec.c +++ b/drivers/tsec.c @@ -65,38 +65,30 @@ struct tsec_info_struct { * FEC_PHYIDX */ static struct tsec_info_struct tsec_info[] = { -#if defined(CONFIG_TSEC1) -#if defined(CONFIG_MPC8544DS) || defined(CONFIG_MPC8641HPCN) - {TSEC1_PHY_ADDR, TSEC_GIGABIT | TSEC_REDUCED, TSEC1_PHYIDX}, -#else - {TSEC1_PHY_ADDR, TSEC_GIGABIT, TSEC1_PHYIDX}, -#endif +#ifdef CONFIG_TSEC1 + {TSEC1_PHY_ADDR, TSEC1_FLAGS, TSEC1_PHYIDX}, #else {0, 0, 0}, #endif -#if defined(CONFIG_TSEC2) -#if defined(CONFIG_MPC8641HPCN) - {TSEC2_PHY_ADDR, TSEC_GIGABIT | TSEC_REDUCED, TSEC2_PHYIDX}, -#else - {TSEC2_PHY_ADDR, TSEC_GIGABIT, TSEC2_PHYIDX}, -#endif +#ifdef CONFIG_TSEC2 + {TSEC2_PHY_ADDR, TSEC2_FLAGS, TSEC2_PHYIDX}, #else {0, 0, 0}, #endif #ifdef CONFIG_MPC85XX_FEC - {FEC_PHY_ADDR, 0, FEC_PHYIDX}, + {FEC_PHY_ADDR, FEC_FLAGS, FEC_PHYIDX}, #else -#if defined(CONFIG_TSEC3) - {TSEC3_PHY_ADDR, TSEC_GIGABIT | TSEC_REDUCED, TSEC3_PHYIDX}, +#ifdef CONFIG_TSEC3 + {TSEC3_PHY_ADDR, TSEC3_FLAGS, TSEC3_PHYIDX}, #else {0, 0, 0}, #endif -#if defined(CONFIG_TSEC4) - {TSEC4_PHY_ADDR, TSEC_GIGABIT | TSEC_REDUCED, TSEC4_PHYIDX}, +#ifdef CONFIG_TSEC4 + {TSEC4_PHY_ADDR, TSEC4_FLAGS, TSEC4_PHYIDX}, #else {0, 0, 0}, -#endif -#endif +#endif /* CONFIG_TSEC4 */ +#endif /* CONFIG_MPC85XX_FEC */ }; #define MAXCONTROLLERS (4) diff --git a/include/configs/MPC8313ERDB.h b/include/configs/MPC8313ERDB.h index 81db96f46..f92dce541 100644 --- a/include/configs/MPC8313ERDB.h +++ b/include/configs/MPC8313ERDB.h @@ -310,6 +310,8 @@ #define CONFIG_TSEC2_NAME "TSEC1" #define TSEC1_PHY_ADDR 0x1c #define TSEC2_PHY_ADDR 4 +#define TSEC1_FLAGS TSEC_GIGABIT +#define TSEC2_FLAGS TSEC_GIGABIT #define TSEC1_PHYIDX 0 #define TSEC2_PHYIDX 0 diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h index 1567fcfae..10af5f0bc 100644 --- a/include/configs/MPC8349EMDS.h +++ b/include/configs/MPC8349EMDS.h @@ -440,6 +440,8 @@ #define TSEC2_PHY_ADDR 1 #define TSEC1_PHYIDX 0 #define TSEC2_PHYIDX 0 +#define TSEC1_FLAGS TSEC_GIGABIT +#define TSEC2_FLAGS TSEC_GIGABIT /* Options are: TSEC[0-1] */ #define CONFIG_ETHPRIME "TSEC0" diff --git a/include/configs/MPC8349ITX.h b/include/configs/MPC8349ITX.h index 44649d050..58ee13d3f 100644 --- a/include/configs/MPC8349ITX.h +++ b/include/configs/MPC8349ITX.h @@ -382,6 +382,7 @@ boards, we say we have two, but don't display a message if we find only one. */ #define CFG_TSEC1_OFFSET 0x24000 #define TSEC1_PHY_ADDR 0x1c /* VSC8201 uses address 0x1c */ #define TSEC1_PHYIDX 0 +#define TSEC1_FLAGS TSEC_GIGABIT #endif #ifdef CONFIG_TSEC2 @@ -391,6 +392,7 @@ boards, we say we have two, but don't display a message if we find only one. */ #define CONFIG_UNKNOWN_TSEC /* TSEC2 is proprietary */ #define TSEC2_PHY_ADDR 4 #define TSEC2_PHYIDX 0 +#define TSEC2_FLAGS TSEC_GIGABIT #endif #define CONFIG_ETHPRIME "Freescale TSEC" diff --git a/include/configs/MPC8540ADS.h b/include/configs/MPC8540ADS.h index 5a7c879a5..b77499267 100644 --- a/include/configs/MPC8540ADS.h +++ b/include/configs/MPC8540ADS.h @@ -374,6 +374,8 @@ #define TSEC2_PHY_ADDR 1 #define TSEC1_PHYIDX 0 #define TSEC2_PHYIDX 0 +#define TSEC1_FLAGS TSEC_GIGABIT +#define TSEC2_FLAGS TSEC_GIGABIT #if CONFIG_HAS_FEC @@ -381,6 +383,7 @@ #define CONFIG_MPC85XX_FEC_NAME "FEC" #define FEC_PHY_ADDR 3 #define FEC_PHYIDX 0 +#define FEC_FLAGS 0 #endif /* Options are: TSEC[0-1], FEC */ diff --git a/include/configs/MPC8540EVAL.h b/include/configs/MPC8540EVAL.h index 0ce25cf24..5c03ac8c9 100644 --- a/include/configs/MPC8540EVAL.h +++ b/include/configs/MPC8540EVAL.h @@ -224,6 +224,10 @@ #define TSEC1_PHYIDX 0 #define TSEC2_PHYIDX 0 #define FEC_PHYIDX 0 +#define TSEC1_FLAGS TSEC_GIGABIT +#define TSEC2_FLAGS TSEC_GIGABIT +#define FEC_FLAGS 0 + /* Options are: TSEC[0-1], FEC */ #define CONFIG_ETHPRIME "TSEC0" diff --git a/include/configs/MPC8541CDS.h b/include/configs/MPC8541CDS.h index 232f1716b..33a153e34 100644 --- a/include/configs/MPC8541CDS.h +++ b/include/configs/MPC8541CDS.h @@ -384,13 +384,12 @@ extern unsigned long get_clock_freq(void); #define CONFIG_TSEC1_NAME "TSEC0" #define CONFIG_TSEC2 1 #define CONFIG_TSEC2_NAME "TSEC1" -#undef CONFIG_MPC85XX_FEC #define TSEC1_PHY_ADDR 0 #define TSEC2_PHY_ADDR 1 -#define FEC_PHY_ADDR 3 #define TSEC1_PHYIDX 0 #define TSEC2_PHYIDX 0 -#define FEC_PHYIDX 0 +#define TSEC1_FLAGS TSEC_GIGABIT +#define TSEC2_FLAGS TSEC_GIGABIT /* Options are: TSEC[0-1] */ #define CONFIG_ETHPRIME "TSEC0" diff --git a/include/configs/MPC8544DS.h b/include/configs/MPC8544DS.h index 32934e155..786344733 100644 --- a/include/configs/MPC8544DS.h +++ b/include/configs/MPC8544DS.h @@ -364,15 +364,13 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_TSEC1_NAME "eTSEC1" #define CONFIG_TSEC3 1 #define CONFIG_TSEC3_NAME "eTSEC3" -#undef CONFIG_MPC85XX_FEC - -#define CONFIG_TSEC_TBI 1 /* enable internal TBI phy */ -#define CONFIG_SGMII_RISER -#define TSEC1_SGMII_PHY_ADDR_OFFSET 0x1c /* sgmii phy base */ #define TSEC1_PHY_ADDR 0 #define TSEC3_PHY_ADDR 1 +#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) +#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) + #define TSEC1_PHYIDX 0 #define TSEC3_PHYIDX 0 diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h index cda9fd5c1..7345a3e10 100644 --- a/include/configs/MPC8548CDS.h +++ b/include/configs/MPC8548CDS.h @@ -447,6 +447,10 @@ extern unsigned long get_clock_freq(void); #define TSEC2_PHYIDX 0 #define TSEC3_PHYIDX 0 #define TSEC4_PHYIDX 0 +#define TSEC1_FLAGS TSEC_GIGABIT +#define TSEC2_FLAGS TSEC_GIGABIT +#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) +#define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) /* Options are: eTSEC[0-3] */ #define CONFIG_ETHPRIME "eTSEC0" diff --git a/include/configs/MPC8555CDS.h b/include/configs/MPC8555CDS.h index e8fe99aaf..48a2663b5 100644 --- a/include/configs/MPC8555CDS.h +++ b/include/configs/MPC8555CDS.h @@ -384,13 +384,12 @@ extern unsigned long get_clock_freq(void); #define CONFIG_TSEC1_NAME "TSEC0" #define CONFIG_TSEC2 1 #define CONFIG_TSEC2_NAME "TSEC1" -#undef CONFIG_MPC85XX_FEC #define TSEC1_PHY_ADDR 0 #define TSEC2_PHY_ADDR 1 -#define FEC_PHY_ADDR 3 #define TSEC1_PHYIDX 0 #define TSEC2_PHYIDX 0 -#define FEC_PHYIDX 0 +#define TSEC1_FLAGS TSEC_GIGABIT +#define TSEC2_FLAGS TSEC_GIGABIT /* Options are: TSEC[0-1] */ #define CONFIG_ETHPRIME "TSEC0" diff --git a/include/configs/MPC8560ADS.h b/include/configs/MPC8560ADS.h index c10e551e4..da41dadcd 100644 --- a/include/configs/MPC8560ADS.h +++ b/include/configs/MPC8560ADS.h @@ -360,11 +360,12 @@ #define CONFIG_TSEC1_NAME "TSEC0" #define CONFIG_TSEC2 1 #define CONFIG_TSEC2_NAME "TSEC1" -#undef CONFIG_MPC85XX_FEC #define TSEC1_PHY_ADDR 0 #define TSEC2_PHY_ADDR 1 #define TSEC1_PHYIDX 0 #define TSEC2_PHYIDX 0 +#define TSEC1_FLAGS TSEC_GIGABIT +#define TSEC2_FLAGS TSEC_GIGABIT /* Options are: TSEC[0-1] */ #define CONFIG_ETHPRIME "TSEC0" diff --git a/include/configs/MPC8568MDS.h b/include/configs/MPC8568MDS.h index dc9cb1ff5..6b824ed9d 100644 --- a/include/configs/MPC8568MDS.h +++ b/include/configs/MPC8568MDS.h @@ -399,9 +399,6 @@ extern unsigned long get_clock_freq(void); #define CONFIG_TSEC1_NAME "eTSEC0" #define CONFIG_TSEC2 1 #define CONFIG_TSEC2_NAME "eTSEC1" -#undef CONFIG_TSEC3 -#undef CONFIG_TSEC4 -#undef CONFIG_MPC85XX_FEC #define TSEC1_PHY_ADDR 2 #define TSEC2_PHY_ADDR 3 @@ -409,6 +406,9 @@ extern unsigned long get_clock_freq(void); #define TSEC1_PHYIDX 0 #define TSEC2_PHYIDX 0 +#define TSEC1_FLAGS TSEC_GIGABIT +#define TSEC2_FLAGS TSEC_GIGABIT + /* Options are: eTSEC[0-3] */ #define CONFIG_ETHPRIME "eTSEC0" diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h index 64dcbd010..e912331f3 100644 --- a/include/configs/MPC8641HPCN.h +++ b/include/configs/MPC8641HPCN.h @@ -417,6 +417,10 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define TSEC2_PHYIDX 0 #define TSEC3_PHYIDX 0 #define TSEC4_PHYIDX 0 +#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) +#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) +#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) +#define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) #define CONFIG_ETHPRIME "eTSEC1" diff --git a/include/configs/PM854.h b/include/configs/PM854.h index dbf94228a..93090b981 100644 --- a/include/configs/PM854.h +++ b/include/configs/PM854.h @@ -270,11 +270,14 @@ #define TSEC2_PHY_ADDR 1 #define TSEC1_PHYIDX 0 #define TSEC2_PHYIDX 0 +#define TSEC1_FLAGS TSEC_GIGABIT +#define TSEC2_FLAGS TSEC_GIGABIT #define CONFIG_MPC85XX_FEC 1 #define CONFIG_MPC85XX_FEC_NAME "FEC" #define FEC_PHY_ADDR 3 #define FEC_PHYIDX 0 +#define FEC_FLAGS 0 /* Options are: TSEC[0-1] */ #define CONFIG_ETHPRIME "TSEC0" diff --git a/include/configs/PM856.h b/include/configs/PM856.h index 6bdfa5d8f..6105747c7 100644 --- a/include/configs/PM856.h +++ b/include/configs/PM856.h @@ -262,11 +262,12 @@ #define CONFIG_TSEC1_NAME "TSEC0" #define CONFIG_TSEC2 1 #define CONFIG_TSEC2_NAME "TSEC1" -#undef CONFIG_MPC85XX_FEC #define TSEC1_PHY_ADDR 0 #define TSEC2_PHY_ADDR 1 #define TSEC1_PHYIDX 0 #define TSEC2_PHYIDX 0 +#define TSEC1_FLAGS TSEC_GIGABIT +#define TSEC2_FLAGS TSEC_GIGABIT #endif /* CONFIG_TSEC_ENET */ diff --git a/include/configs/TQM834x.h b/include/configs/TQM834x.h index 661712b22..91c1694f2 100644 --- a/include/configs/TQM834x.h +++ b/include/configs/TQM834x.h @@ -253,6 +253,8 @@ extern int tqm834x_num_flash_banks; #define TSEC2_PHY_ADDR 1 #define TSEC1_PHYIDX 0 #define TSEC2_PHYIDX 0 +#define TSEC1_FLAGS TSEC_GIGABIT +#define TSEC2_FLAGS TSEC_GIGABIT /* Options are: TSEC[0-1] */ #define CONFIG_ETHPRIME "TSEC0" diff --git a/include/configs/TQM85xx.h b/include/configs/TQM85xx.h index d5ce3ba71..cb9bf5492 100644 --- a/include/configs/TQM85xx.h +++ b/include/configs/TQM85xx.h @@ -266,8 +266,11 @@ #define TSEC2_PHY_ADDR 1 #define TSEC1_PHYIDX 0 #define TSEC2_PHYIDX 0 +#define TSEC1_FLAGS TSEC_GIGABIT +#define TSEC2_FLAGS TSEC_GIGABIT #define FEC_PHY_ADDR 3 #define FEC_PHYIDX 0 +#define FEC_FLAGS 0 #define CONFIG_HAS_ETH1 #define CONFIG_HAS_ETH2 diff --git a/include/configs/sbc8349.h b/include/configs/sbc8349.h index 1831bef0d..aa515ea61 100644 --- a/include/configs/sbc8349.h +++ b/include/configs/sbc8349.h @@ -410,6 +410,8 @@ #define TSEC2_PHY_ADDR 0x1a #define TSEC1_PHYIDX 0 #define TSEC2_PHYIDX 0 +#define TSEC1_FLAGS TSEC_GIGABIT +#define TSEC2_FLAGS TSEC_GIGABIT /* Options are: TSEC[0-1] */ #define CONFIG_ETHPRIME "TSEC0" diff --git a/include/configs/sbc8641d.h b/include/configs/sbc8641d.h index 277b61140..760b754e6 100644 --- a/include/configs/sbc8641d.h +++ b/include/configs/sbc8641d.h @@ -380,6 +380,10 @@ #define TSEC2_PHYIDX 0 #define TSEC3_PHYIDX 0 #define TSEC4_PHYIDX 0 +#define TSEC1_FLAGS TSEC_GIGABIT +#define TSEC2_FLAGS TSEC_GIGABIT +#define TSEC3_FLAGS TSEC_GIGABIT +#define TSEC4_FLAGS TSEC_GIGABIT #define CFG_TBIPA_VALUE 0x1e /* Set TBI address not to conflict with TSEC1_PHY_ADDR */ diff --git a/include/configs/stxgp3.h b/include/configs/stxgp3.h index 1f41cf769..43b185bee 100644 --- a/include/configs/stxgp3.h +++ b/include/configs/stxgp3.h @@ -234,12 +234,13 @@ #define CONFIG_TSEC1_NAME "TSEC0" #define CONFIG_TSEC2 1 #define CONFIG_TSEC2_NAME "TSEC1" -#undef CONFIG_MPS85XX_FEC #define TSEC1_PHY_ADDR 2 #define TSEC2_PHY_ADDR 4 #define TSEC1_PHYIDX 0 #define TSEC2_PHYIDX 0 +#define TSEC1_FLAGS TSEC_GIGABIT +#define TSEC2_FLAGS TSEC_GIGABIT #define CONFIG_ETHPRIME "TSEC0" #elif defined(CONFIG_ETHER_ON_FCC) /* CPM FCC Ethernet */ diff --git a/include/configs/stxssa.h b/include/configs/stxssa.h index 55e2c8da2..3dae27ac1 100644 --- a/include/configs/stxssa.h +++ b/include/configs/stxssa.h @@ -260,12 +260,13 @@ #define CONFIG_TSEC1_NAME "TSEC0" #define CONFIG_TSEC2 1 #define CONFIG_TSEC2_NAME "TSEC1" -#define CONFIG_MPS85XX_FEC #define TSEC1_PHY_ADDR 2 #define TSEC2_PHY_ADDR 4 #define TSEC1_PHYIDX 0 #define TSEC2_PHYIDX 0 +#define TSEC1_FLAGS TSEC_GIGABIT +#define TSEC2_FLAGS TSEC_GIGABIT #define CONFIG_ETHPRIME "TSEC0" #elif defined(CONFIG_ETHER_ON_FCC) /* CPM FCC Ethernet */ From b96c83d4ae475a70ef2635cd0e748174c44c8601 Mon Sep 17 00:00:00 2001 From: Andy Fleming Date: Wed, 15 Aug 2007 20:03:34 -0500 Subject: [PATCH 144/259] Fix numerous bugs in the 8568 UEC support Actually, fixed a large bug in the UEC for *all* platforms. How did this ever work? uec_init() did not follow the spec for eth_init(), and returned 0 on success. Switch it to return the link like tsec_init() (and 0 on error) The immap for the 8568 was defined based on MPC8568, rather than CONFIG_MPC8568 CONFIG_QE was off CONFIG_ETHPRIME was set to "Freescale GETH". Now is "FSL UEC0" Fixed a comment about the ranges for CONFIG_ETHPRIME if TSEC_ENET is enabled Signed-off-by: Andy Fleming --- drivers/qe/uec.c | 6 +++--- include/asm-ppc/immap_85xx.h | 2 +- include/configs/MPC8568MDS.h | 6 +++--- 3 files changed, 7 insertions(+), 7 deletions(-) diff --git a/drivers/qe/uec.c b/drivers/qe/uec.c index 89a727982..dc2765bb0 100644 --- a/drivers/qe/uec.c +++ b/drivers/qe/uec.c @@ -1110,7 +1110,7 @@ static int uec_init(struct eth_device* dev, bd_t *bd) if (dev->enetaddr[0] & 0x01) { printf("%s: MacAddress is multcast address\n", __FUNCTION__); - return -EINVAL; + return 0; } uec_set_mac_address(uec, dev->enetaddr); uec->the_first_run = 1; @@ -1119,10 +1119,10 @@ static int uec_init(struct eth_device* dev, bd_t *bd) err = uec_open(uec, COMM_DIR_RX_AND_TX); if (err) { printf("%s: cannot enable UEC device\n", dev->name); - return err; + return 0; } - return 0; + return uec->mii_info->link; } static void uec_halt(struct eth_device* dev) diff --git a/include/asm-ppc/immap_85xx.h b/include/asm-ppc/immap_85xx.h index 3d4816f3a..496fc72da 100644 --- a/include/asm-ppc/immap_85xx.h +++ b/include/asm-ppc/immap_85xx.h @@ -1596,7 +1596,7 @@ typedef struct ccsr_gur { uint svr; /* 0xe00a4 - System version register */ char res10a[8]; uint rstcr; /* 0xe00b0 - Reset control register */ -#ifdef MPC8568 +#ifdef CONFIG_MPC8568 char res10b[76]; par_io_t qe_par_io[7]; /* 0xe0100 - 0xe01bf */ char res10c[3136]; diff --git a/include/configs/MPC8568MDS.h b/include/configs/MPC8568MDS.h index 6b824ed9d..80ccda51f 100644 --- a/include/configs/MPC8568MDS.h +++ b/include/configs/MPC8568MDS.h @@ -35,7 +35,7 @@ #define CONFIG_PCI #define CONFIG_TSEC_ENET /* tsec ethernet support */ -#undef CONFIG_QE /* Enable QE */ +#define CONFIG_QE /* Enable QE */ #define CONFIG_ENV_OVERWRITE #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ #define CONFIG_DDR_DLL /* possible DLL fix needed */ @@ -348,7 +348,7 @@ extern unsigned long get_clock_freq(void); */ #define CONFIG_UEC_ETH #ifndef CONFIG_TSEC_ENET -#define CONFIG_ETHPRIME "Freescale GETH" +#define CONFIG_ETHPRIME "FSL UEC0" #endif #define CONFIG_PHY_MODE_NEED_CHANGE #define CONFIG_eTSEC_MDIO_BUS @@ -409,7 +409,7 @@ extern unsigned long get_clock_freq(void); #define TSEC1_FLAGS TSEC_GIGABIT #define TSEC2_FLAGS TSEC_GIGABIT -/* Options are: eTSEC[0-3] */ +/* Options are: eTSEC[0-1] */ #define CONFIG_ETHPRIME "eTSEC0" #endif /* CONFIG_TSEC_ENET */ From 7613afda77d5eec0f47d303025b0c661b70e4c73 Mon Sep 17 00:00:00 2001 From: Andy Fleming Date: Wed, 15 Aug 2007 20:03:44 -0500 Subject: [PATCH 145/259] Don't wait for disconnected TSECs The TSEC driver's PHY code waits a long time for autonegotiation to complete, even if the link is down. The PHY knows the link is down or up before autonegotiation completes, so we can short-circuit the process if the link is down. Signed-off-by: Andy Fleming --- drivers/tsec.c | 30 +++++++++++++++++------------- 1 file changed, 17 insertions(+), 13 deletions(-) diff --git a/drivers/tsec.c b/drivers/tsec.c index 1df8f7dc2..6bca4dc0f 100644 --- a/drivers/tsec.c +++ b/drivers/tsec.c @@ -347,17 +347,16 @@ uint mii_cr_init(uint mii_reg, struct tsec_private * priv) uint mii_parse_sr(uint mii_reg, struct tsec_private * priv) { /* - * Wait if PHY is capable of autonegotiation and autonegotiation - * is not complete. + * Wait if the link is up, and autonegotiation is in progress + * (ie - we're capable and it's not done) */ mii_reg = read_phy_reg(priv, MIIM_STATUS); - if ((mii_reg & PHY_BMSR_AUTN_ABLE) + if ((mii_reg & MIIM_STATUS_LINK) && (mii_reg & PHY_BMSR_AUTN_ABLE) && !(mii_reg & PHY_BMSR_AUTN_COMP)) { int i = 0; puts("Waiting for PHY auto negotiation to complete"); - while (!((mii_reg & PHY_BMSR_AUTN_COMP) - && (mii_reg & MIIM_STATUS_LINK))) { + while (!(mii_reg & PHY_BMSR_AUTN_COMP)) { /* * Timeout reached ? */ @@ -377,7 +376,10 @@ uint mii_parse_sr(uint mii_reg, struct tsec_private * priv) priv->link = 1; udelay(500000); /* another 500 ms (results in faster booting) */ } else { - priv->link = 1; + if (mii_reg & MIIM_STATUS_LINK) + priv->link = 1; + else + priv->link = 0; } return 0; @@ -517,16 +519,13 @@ uint mii_parse_88E1011_psr(uint mii_reg, struct tsec_private * priv) mii_reg = read_phy_reg(priv, MIIM_88E1011_PHY_STATUS); - if (!((mii_reg & MIIM_88E1011_PHYSTAT_SPDDONE) && - (mii_reg & MIIM_88E1011_PHYSTAT_LINK))) { + if ((mii_reg & MIIM_88E1011_PHYSTAT_LINK) && + !(mii_reg & MIIM_88E1011_PHYSTAT_SPDDONE)) { int i = 0; puts("Waiting for PHY realtime link"); - while (!((mii_reg & MIIM_88E1011_PHYSTAT_SPDDONE) && - (mii_reg & MIIM_88E1011_PHYSTAT_LINK))) { - /* - * Timeout reached ? - */ + while (!(mii_reg & MIIM_88E1011_PHYSTAT_SPDDONE)) { + /* Timeout reached ? */ if (i > PHY_AUTONEGOTIATE_TIMEOUT) { puts(" TIMEOUT !\n"); priv->link = 0; @@ -541,6 +540,11 @@ uint mii_parse_88E1011_psr(uint mii_reg, struct tsec_private * priv) } puts(" done\n"); udelay(500000); /* another 500 ms (results in faster booting) */ + } else { + if (mii_reg & MIIM_88E1011_PHYSTAT_LINK) + priv->link = 1; + else + priv->link = 0; } if (mii_reg & MIIM_88E1011_PHYSTAT_DUPLEX) From 82bd9ee77490588d4da785d75829ca63d0176baf Mon Sep 17 00:00:00 2001 From: Andy Fleming Date: Wed, 15 Aug 2007 20:06:50 -0500 Subject: [PATCH 146/259] Fix warnings from of_data copy fix Forgot to cast of_flat_tree to ulong. Signed-off-by: Andy Fleming --- common/cmd_bootm.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/common/cmd_bootm.c b/common/cmd_bootm.c index 90e3f8b9a..bcb927fd1 100644 --- a/common/cmd_bootm.c +++ b/common/cmd_bootm.c @@ -932,7 +932,7 @@ do_bootm_linux (cmd_tbl_t *cmdtp, int flag, * so we flag it to be copied if it is not. */ if (of_flat_tree >= (char *)CFG_BOOTMAPSZ) - of_data = of_flat_tree; + of_data = (ulong)of_flat_tree; #endif /* move of_flat_tree if needed */ @@ -993,7 +993,7 @@ do_bootm_linux (cmd_tbl_t *cmdtp, int flag, * so we flag it to be copied if it is not. */ if (of_flat_tree >= (char *)CFG_BOOTMAPSZ) - of_data = of_flat_tree; + of_data = (ulong)of_flat_tree; #endif /* move of_flat_tree if needed */ From d35b508a55508535b6e8445b718585d27df733d3 Mon Sep 17 00:00:00 2001 From: Kim Phillips Date: Wed, 15 Aug 2007 22:29:56 -0500 Subject: [PATCH 147/259] fdt: suppress unused variable 'bd' warning Signed-off-by: Kim Phillips --- common/fdt_support.c | 1 - 1 file changed, 1 deletion(-) diff --git a/common/fdt_support.c b/common/fdt_support.c index caaa682a4..175d59eb9 100644 --- a/common/fdt_support.c +++ b/common/fdt_support.c @@ -46,7 +46,6 @@ struct fdt_header *fdt; int fdt_chosen(void *fdt, ulong initrd_start, ulong initrd_end, int force) { - bd_t *bd = gd->bd; int nodeoffset; int err; u32 tmp; /* used to set 32 bit integer properties */ From 1e6b07c64967c1eb2cd84faa4c32bf2a769bc8eb Mon Sep 17 00:00:00 2001 From: Niklaus Giger Date: Thu, 16 Aug 2007 15:16:02 +0200 Subject: [PATCH 148/259] PPC4xx:HCU4/5 cleanup ecc/sdram init Make ecc initialisation robust, as DDR2-ECC errors may be generated while zeroing the RAM. Return 16 bytes (a cacheline) less than the available memory, as the board and/or PPC440EPx might have problems accessing the last bytes. Signed-off-by: Niklaus Giger --- board/netstal/hcu5/sdram.c | 15 ++++++++++++--- 1 file changed, 12 insertions(+), 3 deletions(-) diff --git a/board/netstal/hcu5/sdram.c b/board/netstal/hcu5/sdram.c index 40391958d..5d457f7b2 100644 --- a/board/netstal/hcu5/sdram.c +++ b/board/netstal/hcu5/sdram.c @@ -36,7 +36,7 @@ #include #include -void sysLedSet(u32 value); +void hcu_led_set(u32 value); void dcbz_area(u32 start_address, u32 num_bytes); void dflush(void); @@ -138,7 +138,7 @@ static int wait_for_dlllock(void) void sdram_panic(const char *reason) { printf("\n%s: reason %s", __FUNCTION__, reason); - sysLedSet(0xff); + hcu_led_set(0xff); while (1) { } /* Never return */ @@ -197,6 +197,13 @@ static void program_ecc(unsigned long start_address, unsigned long num_bytes, mfsdram(DDR0_00, val); mtsdram(DDR0_00, val | DDR0_00_INT_ACK_ALL); + /* + * Clear possible errors + * If not done, then we could get an interrupt later on when + * exceptions are enabled. + */ + mtspr(mcsr, mfspr(mcsr)); + /* Set 'int_mask' parameter to functionnal value */ mfsdram(DDR0_01, val); mtsdram(DDR0_01, ((val &~ DDR0_01_INT_MASK_MASK) | @@ -244,7 +251,6 @@ long int initdram (int board_type) sdram_panic(INVALID_HW_CONFIG); break; } - dram_size -= 16 * 1024 * 1024; mtsdram(DDR0_07, 0x00090100); /* * TCPD=200 cycles of clock input is required to lock the DLL. @@ -283,6 +289,7 @@ long int initdram (int board_type) /* * Program tlb entries for this size (dynamic) */ + remove_tlb(CFG_SDRAM_BASE, 256 << 20); program_tlb(0, 0, dram_size, MY_TLB_WORD2_I_ENABLE); /* @@ -291,6 +298,8 @@ long int initdram (int board_type) */ program_tlb(0, CFG_DDR_CACHED_ADDR, dram_size, 0); + /* Diminish RAM to initialize */ + dram_size = dram_size - 32 ; #ifdef CONFIG_DDR_ECC /* * If ECC is enabled, initialize the parity bits. From 07bc20560cb9d3d186cca268c05c82762e8c55ad Mon Sep 17 00:00:00 2001 From: Niklaus Giger Date: Thu, 16 Aug 2007 15:16:03 +0200 Subject: [PATCH 149/259] PPC4xx:HCU4/5 cleanup Minor cleanups to confirm to the u-boot coding style. Some german expressions -> english. HCU5 enforces a unique IP adress for a given slot in the rack. Signed-off-by: Niklaus Giger --- board/netstal/hcu4/hcu4.c | 20 +++++++----- board/netstal/hcu5/hcu5.c | 69 +++++++++++++++++++++++++++------------ 2 files changed, 60 insertions(+), 29 deletions(-) diff --git a/board/netstal/hcu4/hcu4.c b/board/netstal/hcu4/hcu4.c index 2b9560484..48a3f13ba 100644 --- a/board/netstal/hcu4/hcu4.c +++ b/board/netstal/hcu4/hcu4.c @@ -43,7 +43,7 @@ enum { HW_GENERATION_MCU25 = 0x09, }; -void sysLedSet(u32 value); +void hcu_led_set(u32 value); long int spd_sdram(int(read_spd)(uint addr)); #ifdef CONFIG_SPD_EEPROM @@ -121,22 +121,24 @@ int checkboard (void) printf ("HCU3: index %d\n\n", index); else if (generation == HW_GENERATION_HCU4) printf ("HCU4: index %d\n\n", index); - /* GPIO here noch nicht richtig initialisert !!! */ - sysLedSet(0); + hcu_led_set(0); for (j = 0; j < 7; j++) { - sysLedSet(1 << j); + hcu_led_set(1 << j); udelay(50 * 1000); } return 0; } -u32 sysLedGet(void) +u32 hcu_led_get(void) { return (~((*(u32 *)GPIO0_OR)) >> 23) & 0xff; } -void sysLedSet(u32 value /* value to place in LEDs */) +/*---------------------------------------------------------------------------+ + * hcu_led_set value to be placed into the LEDs (max 6 bit) + *---------------------------------------------------------------------------*/ +void hcu_led_set(u32 value) { u32 tmp = ~value; u32 *ledReg; @@ -243,9 +245,9 @@ long int fixed_hcu4_sdram (int board_type) } /*---------------------------------------------------------------------------+ - * getSerialNr + * hcu_serial_number *---------------------------------------------------------------------------*/ -static u32 getSerialNr(void) +static u32 hcu_serial_number(void) { u32 *serial = (u32 *)CFG_FLASH_BASE; @@ -265,7 +267,7 @@ int misc_init_r(void) char *s = getenv("ethaddr"); char *e; int i; - u32 serial = getSerialNr(); + u32 serial = hcu_serial_number(); for (i = 0; i < 6; ++i) { gd->bd->bi_enetaddr[i] = s ? simple_strtoul (s, &e, 16) : 0; diff --git a/board/netstal/hcu5/hcu5.c b/board/netstal/hcu5/hcu5.c index 23df0814f..b9b10fdc2 100644 --- a/board/netstal/hcu5/hcu5.c +++ b/board/netstal/hcu5/hcu5.c @@ -22,10 +22,11 @@ #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; -void sysLedSet(u32 value); +void hcu_led_set(u32 value); extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; @@ -41,7 +42,8 @@ extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; #define SDR0_ECID2 0x0082 #define SDR0_ECID3 0x0083 -#define SYS_IO_ADDRESS 0xcce00000 +#define SYS_IO_ADDRESS (CFG_CS_2 + 0x00e00000) +#define SYS_SLOT_ADDRESS (CFG_CPLD + 0x00400000) #define DEFAULT_ETH_ADDR "ethaddr" /* ethaddr for first or etha1ddr for second ethernet */ @@ -182,11 +184,14 @@ int board_early_init_f(void) return 0; } +#ifdef CONFIG_BOARD_PRE_INIT int board_pre_init(void) { return board_early_init_f(); } +#endif + int checkboard(void) { unsigned int j; @@ -211,37 +216,50 @@ int checkboard(void) printf("Chip ID 0x%x 0x%x 0x%x 0x%x\n", ecid0, ecid1, ecid2, ecid3); for (j = 0;j < 6; j++) { - sysLedSet(1 << j); + hcu_led_set(1 << j); udelay(200 * 1000); } return 0; } -u32 sysLedGet(void) +u32 hcu_led_get(void) { return in16(SYS_IO_ADDRESS) & 0x3f; } -void sysLedSet(u32 value /* value to place in LEDs */) +/*---------------------------------------------------------------------------+ + * hcu_led_set value to be placed into the LEDs (max 6 bit) + *---------------------------------------------------------------------------*/ +void hcu_led_set(u32 value) { out16(SYS_IO_ADDRESS, value); } /*---------------------------------------------------------------------------+ - * getSerialNr + * get_serial_number *---------------------------------------------------------------------------*/ -static u32 getSerialNr(void) +static u32 get_serial_number(void) { u32 *serial = (u32 *)CFG_FLASH_BASE; if (*serial == 0xffffffff) - return get_ticks(); + return 0; return *serial; } +/*---------------------------------------------------------------------------+ + * hcu_get_slot + *---------------------------------------------------------------------------*/ +u32 hcu_get_slot(void) +{ + u16 *slot = (u16 *)SYS_SLOT_ADDRESS; + return (*slot) & 0x7f; +} + + /*---------------------------------------------------------------------------+ * misc_init_r. *---------------------------------------------------------------------------*/ @@ -250,7 +268,7 @@ int misc_init_r(void) char *s = getenv(DEFAULT_ETH_ADDR); char *e; int i; - u32 serial = getSerialNr(); + u32 serial = get_serial_number(); unsigned long usb2d0cr = 0; unsigned long usb2phy0cr, usb2h0cr = 0; unsigned long sdr0_pfc1; @@ -272,8 +290,7 @@ int misc_init_r(void) gd->bd->bi_enetaddr[2] = 0x13; gd->bd->bi_enetaddr[3] = (serial >> 16) & 0xff; gd->bd->bi_enetaddr[4] = (serial >> 8) & 0xff; - /* byte[5].bit 0 must be zero */ - gd->bd->bi_enetaddr[5] = (serial >> 0) & 0xfe; + gd->bd->bi_enetaddr[5] = hcu_get_slot(); sprintf(ethaddr, "%02X:%02X:%02X:%02X:%02X:%02X\0", gd->bd->bi_enetaddr[0], gd->bd->bi_enetaddr[1], gd->bd->bi_enetaddr[2], gd->bd->bi_enetaddr[3], @@ -283,6 +300,25 @@ int misc_init_r(void) setenv(DEFAULT_ETH_ADDR, ethaddr); } + /* IP-Adress update */ + { + IPaddr_t ipaddr; + char *ipstring; + + ipstring = getenv("ipaddr"); + if (ipstring == 0) + ipaddr = string_to_ip("172.25.1.99"); + else + ipaddr = string_to_ip(ipstring); + if ((ipaddr & 0xff) != (32 + hcu_get_slot())) { + char tmp[22]; + + ipaddr = (ipaddr & 0xffffff00) + 32 + hcu_get_slot(); + ip_to_string (ipaddr, tmp); + printf("%s: enforce %s\n", __FUNCTION__, tmp); + setenv("ipaddr", tmp); + } + } #ifdef CFG_ENV_IS_IN_FLASH /* Monitor protection ON by default */ (void)flash_protect(FLAG_PROTECT_SET, @@ -346,6 +382,7 @@ int misc_init_r(void) return 0; } +#if defined(CONFIG_PCI) /************************************************************************* * pci_pre_init * @@ -358,7 +395,6 @@ int misc_init_r(void) * certain pre-initialization actions. * ************************************************************************/ -#if defined(CONFIG_PCI) int pci_pre_init(struct pci_controller *hose) { unsigned long addr; @@ -411,7 +447,6 @@ int pci_pre_init(struct pci_controller *hose) return 1; } -#endif /* defined(CONFIG_PCI) */ /************************************************************************* * pci_target_init @@ -421,7 +456,6 @@ int pci_pre_init(struct pci_controller *hose) * may not be sufficient for a given board. * ************************************************************************/ -#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) void pci_target_init(struct pci_controller *hose) { /*-------------------------------------------------------------+ @@ -478,13 +512,11 @@ void pci_target_init(struct pci_controller *hose) pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101); } -#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */ /************************************************************************* * pci_master_init * ************************************************************************/ -#if defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) void pci_master_init(struct pci_controller *hose) { unsigned short temp_short; @@ -499,8 +531,6 @@ void pci_master_init(struct pci_controller *hose) temp_short | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); } -#endif -/* defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) */ /************************************************************************* * is_pci_host @@ -517,9 +547,8 @@ void pci_master_init(struct pci_controller *hose) * * ************************************************************************/ -#if defined(CONFIG_PCI) int is_pci_host(struct pci_controller *hose) { return 1; } -#endif /* defined(CONFIG_PCI) */ +#endif /* defined(CONFIG_PCI) */ From ea5877e31ed63ade948fd1293895ec23fe01472e Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Thu, 16 Aug 2007 11:01:21 -0500 Subject: [PATCH 150/259] Fix up some fdt issues on 8544DS It looks like we had a merge issue that duplicated a bit of code in ft_board_setup. Also, we need to set CONFIG_HAS_ETH0 to get the MAC address properly set in the device tree on boot for TSEC1 Signed-off-by: Kumar Gala --- board/freescale/mpc8544ds/mpc8544ds.c | 7 ------- include/configs/MPC8544DS.h | 1 + 2 files changed, 1 insertion(+), 7 deletions(-) diff --git a/board/freescale/mpc8544ds/mpc8544ds.c b/board/freescale/mpc8544ds/mpc8544ds.c index 8ddbb0101..80822bec7 100644 --- a/board/freescale/mpc8544ds/mpc8544ds.c +++ b/board/freescale/mpc8544ds/mpc8544ds.c @@ -540,12 +540,5 @@ ft_board_setup(void *blob, bd_t *bd) debug("PCI@b000 first_busno=%d last_busno=%d\n",p[0],p[1]); } #endif - ft_cpu_setup(blob, bd); - - p = ft_get_prop(blob, "/memory/reg", &len); - if (p != NULL) { - *p++ = cpu_to_be32(bd->bi_memstart); - *p = cpu_to_be32(bd->bi_memsize); - } } #endif diff --git a/include/configs/MPC8544DS.h b/include/configs/MPC8544DS.h index 786344733..fcb92fac4 100644 --- a/include/configs/MPC8544DS.h +++ b/include/configs/MPC8544DS.h @@ -472,6 +472,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); /* The mac addresses for all ethernet interface */ #if defined(CONFIG_TSEC_ENET) +#define CONFIG_HAS_ETH0 #define CONFIG_ETHADDR 00:E0:0C:02:00:FD #define CONFIG_HAS_ETH1 #define CONFIG_ETH1ADDR 00:E0:0C:02:01:FD From d64ee908a1b525e5bb2b4cbeb5c449ad6a469666 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Thu, 16 Aug 2007 15:05:04 -0500 Subject: [PATCH 151/259] Update MPC8544 DS PCI memory map The PCIe bus that the ULI M1575 is connected to has no possible way of needing more than the fixed amount of IO & Memory space needed by the ULI. So make it use far less IO & memory space and have it use the shared LAW. This free's up a LAW for PCIe1 IO space. Also reduce the amount of IO space needed by each bus. Signed-off-by: Kumar Gala --- board/freescale/mpc8544ds/init.S | 13 ++++++------- include/configs/MPC8544DS.h | 21 +++++++++------------ 2 files changed, 15 insertions(+), 19 deletions(-) diff --git a/board/freescale/mpc8544ds/init.S b/board/freescale/mpc8544ds/init.S index ea7d54dc3..900c3680c 100644 --- a/board/freescale/mpc8544ds/init.S +++ b/board/freescale/mpc8544ds/init.S @@ -218,7 +218,7 @@ law_entry: .long LAWAR_EN | LAWAR_TRGT_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_512M) .long (CFG_PCI1_IO_PHYS>>12) & 0xfffff - .long LAWAR_EN | LAWAR_TRGT_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_16M) + .long LAWAR_EN | LAWAR_TRGT_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_64K) .long (CFG_LBC_CACHE_BASE>>12) & 0xfffff .long LAWAR_EN | LAWAR_TRGT_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M) @@ -226,18 +226,17 @@ law_entry: .long (CFG_PCIE1_MEM_PHYS>>12) & 0xfffff .long LAWAR_EN | LAWAR_TRGT_PCIE1 | (LAWAR_SIZE & LAWAR_SIZE_256M) - /* To keep to 10 LAWs, PCIE1_IO_PHYS must use top of mem region */ + .long (CFG_PCIE1_IO_PHYS>>12) & 0xfffff + .long LAWAR_EN | LAWAR_TRGT_PCIE1 | (LAWAR_SIZE & LAWAR_SIZE_64K) .long (CFG_PCIE2_MEM_PHYS>>12) & 0xfffff .long LAWAR_EN | LAWAR_TRGT_PCIE2 | (LAWAR_SIZE & LAWAR_SIZE_512M) .long (CFG_PCIE2_IO_PHYS>>12) & 0xfffff - .long LAWAR_EN | LAWAR_TRGT_PCIE2 | (LAWAR_SIZE & LAWAR_SIZE_16M) + .long LAWAR_EN | LAWAR_TRGT_PCIE2 | (LAWAR_SIZE & LAWAR_SIZE_64K) + /* contains both PCIE3 MEM & IO space */ .long (CFG_PCIE3_MEM_PHYS>>12) & 0xfffff - .long LAWAR_EN | LAWAR_TRGT_PCIE3 | (LAWAR_SIZE & LAWAR_SIZE_256M) - - .long (CFG_PCIE3_IO_PHYS>>12) & 0xfffff - .long LAWAR_EN | LAWAR_TRGT_PCIE3 | (LAWAR_SIZE & LAWAR_SIZE_16M) + .long LAWAR_EN | LAWAR_TRGT_PCIE3 | (LAWAR_SIZE & LAWAR_SIZE_2M) 4: entry_end diff --git a/include/configs/MPC8544DS.h b/include/configs/MPC8544DS.h index fcb92fac4..746f360f9 100644 --- a/include/configs/MPC8544DS.h +++ b/include/configs/MPC8544DS.h @@ -282,7 +282,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */ #define CFG_PCI1_IO_BASE 0x00000000 #define CFG_PCI1_IO_PHYS 0xe1000000 -#define CFG_PCI1_IO_SIZE 0x00100000 /* 1M */ +#define CFG_PCI1_IO_SIZE 0x00010000 /* 64k */ /* PCI view of System Memory */ #define CFG_PCI_MEMORY_BUS 0x00000000 @@ -294,26 +294,23 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CFG_PCIE2_MEM_PHYS CFG_PCIE2_MEM_BASE #define CFG_PCIE2_MEM_SIZE 0x20000000 /* 512M */ #define CFG_PCIE2_IO_BASE 0x00000000 -#define CFG_PCIE2_IO_PHYS 0xe2000000 -#define CFG_PCIE2_IO_SIZE 0x00100000 /* 1M */ +#define CFG_PCIE2_IO_PHYS 0xe1010000 +#define CFG_PCIE2_IO_SIZE 0x00010000 /* 64k */ /* controller 1, Slot 2,tgtid 2, Base address a000 */ #define CFG_PCIE1_MEM_BASE 0xa0000000 #define CFG_PCIE1_MEM_PHYS CFG_PCIE1_MEM_BASE -#define CFG_PCIE1_MEM_SIZE 0x08000000 /* 128M */ -#define CFG_PCIE1_MEM_BASE2 0xa8000000 -#define CFG_PCIE1_MEM_PHYS2 CFG_PCIE1_MEM_BASE2 -#define CFG_PCIE1_MEM_SIZE2 0x04000000 /* 64M */ -#define CFG_PCIE1_IO_BASE 0x00000000 /* reuse mem LAW */ -#define CFG_PCIE1_IO_PHYS 0xaf000000 -#define CFG_PCIE1_IO_SIZE 0x00100000 /* 1M */ +#define CFG_PCIE1_MEM_SIZE 0x10000000 /* 256M */ +#define CFG_PCIE1_IO_BASE 0x00000000 +#define CFG_PCIE1_IO_PHYS 0xe1020000 +#define CFG_PCIE1_IO_SIZE 0x00010000 /* 64k */ /* controller 3, direct to uli, tgtid 3, Base address b000 */ #define CFG_PCIE3_MEM_BASE 0xb0000000 #define CFG_PCIE3_MEM_PHYS CFG_PCIE3_MEM_BASE -#define CFG_PCIE3_MEM_SIZE 0x10000000 /* 256M */ +#define CFG_PCIE3_MEM_SIZE 0x00100000 /* 1M */ #define CFG_PCIE3_IO_BASE 0x00000000 -#define CFG_PCIE3_IO_PHYS 0xe3000000 +#define CFG_PCIE3_IO_PHYS 0xb0100000 /* reuse mem LAW */ #define CFG_PCIE3_IO_SIZE 0x00100000 /* 1M */ #if defined(CONFIG_PCI) From 10327dc5541f947c0cf7e31fef86c4706169607a Mon Sep 17 00:00:00 2001 From: Andy Fleming Date: Thu, 16 Aug 2007 16:35:02 -0500 Subject: [PATCH 152/259] Add CONFIG_HAS_ETH0 to all boards with TSEC The 85xx code now relies on CONFIG_HAS_ETH0 to determine whether to update TSEC1's device-tree node, so we need to add it to all the boards with TSECs. Do this for 83xx and 86xx, too, since they will eventually do something similar. Signed-off-by: Andy Fleming --- include/configs/MPC8313ERDB.h | 1 + include/configs/MPC8349EMDS.h | 1 + include/configs/MPC8349ITX.h | 1 + include/configs/MPC8540ADS.h | 1 + include/configs/MPC8540EVAL.h | 3 +++ include/configs/MPC8541CDS.h | 1 + include/configs/MPC8548CDS.h | 1 + include/configs/MPC8555CDS.h | 1 + include/configs/MPC8560ADS.h | 1 + include/configs/MPC8641HPCN.h | 1 + include/configs/PM854.h | 1 + include/configs/PM856.h | 1 + include/configs/TQM834x.h | 1 + include/configs/TQM85xx.h | 1 + include/configs/sbc8349.h | 1 + include/configs/sbc8641d.h | 1 + include/configs/stxgp3.h | 1 + include/configs/stxssa.h | 1 + 18 files changed, 20 insertions(+) diff --git a/include/configs/MPC8313ERDB.h b/include/configs/MPC8313ERDB.h index f92dce541..377503782 100644 --- a/include/configs/MPC8313ERDB.h +++ b/include/configs/MPC8313ERDB.h @@ -509,6 +509,7 @@ #define CONFIG_ETHADDR 00:E0:0C:00:95:01 #define CONFIG_HAS_ETH1 +#define CONFIG_HAS_ETH0 #define CONFIG_ETH1ADDR 00:E0:0C:00:95:02 #define CONFIG_IPADDR 10.0.0.2 diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h index 10af5f0bc..48616c08b 100644 --- a/include/configs/MPC8349EMDS.h +++ b/include/configs/MPC8349EMDS.h @@ -701,6 +701,7 @@ #if defined(CONFIG_TSEC_ENET) #define CONFIG_ETHADDR 00:04:9f:ef:23:33 #define CONFIG_HAS_ETH1 +#define CONFIG_HAS_ETH0 #define CONFIG_ETH1ADDR 00:E0:0C:00:7E:21 #endif diff --git a/include/configs/MPC8349ITX.h b/include/configs/MPC8349ITX.h index 58ee13d3f..c5d036296 100644 --- a/include/configs/MPC8349ITX.h +++ b/include/configs/MPC8349ITX.h @@ -378,6 +378,7 @@ boards, we say we have two, but don't display a message if we find only one. */ #define CONFIG_TSEC1 #ifdef CONFIG_TSEC1 +#define CONFIG_HAS_ETH0 #define CONFIG_TSEC1_NAME "TSEC0" #define CFG_TSEC1_OFFSET 0x24000 #define TSEC1_PHY_ADDR 0x1c /* VSC8201 uses address 0x1c */ diff --git a/include/configs/MPC8540ADS.h b/include/configs/MPC8540ADS.h index b77499267..22de2fb2c 100644 --- a/include/configs/MPC8540ADS.h +++ b/include/configs/MPC8540ADS.h @@ -492,6 +492,7 @@ /* The mac addresses for all ethernet interface */ #if defined(CONFIG_TSEC_ENET) +#define CONFIG_HAS_ETH0 #define CONFIG_ETHADDR 00:E0:0C:00:00:FD #define CONFIG_HAS_ETH1 #define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD diff --git a/include/configs/MPC8540EVAL.h b/include/configs/MPC8540EVAL.h index 5c03ac8c9..e376c1165 100644 --- a/include/configs/MPC8540EVAL.h +++ b/include/configs/MPC8540EVAL.h @@ -213,10 +213,13 @@ #define CONFIG_NET_MULTI 1 #define CONFIG_MII 1 /* MII PHY management */ #define CONFIG_TSEC1 1 +#define CONFIG_HAS_ETH0 #define CONFIG_TSEC1_NAME "TSEC0" #define CONFIG_TSEC2 1 +#define CONFIG_HAS_ETH1 #define CONFIG_TSEC2_NAME "TSEC1" #define CONFIG_MPC85XX_FEC 1 +#define CONFIG_HAS_ETH2 #define CONFIG_MPC85XX_FEC_NAME "FEC" #define TSEC1_PHY_ADDR 7 #define TSEC2_PHY_ADDR 4 diff --git a/include/configs/MPC8541CDS.h b/include/configs/MPC8541CDS.h index 33a153e34..a4727b29b 100644 --- a/include/configs/MPC8541CDS.h +++ b/include/configs/MPC8541CDS.h @@ -481,6 +481,7 @@ extern unsigned long get_clock_freq(void); /* The mac addresses for all ethernet interface */ #if defined(CONFIG_TSEC_ENET) +#define CONFIG_HAS_ETH0 #define CONFIG_ETHADDR 00:E0:0C:00:00:FD #define CONFIG_HAS_ETH1 #define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h index 7345a3e10..58a8ea55c 100644 --- a/include/configs/MPC8548CDS.h +++ b/include/configs/MPC8548CDS.h @@ -542,6 +542,7 @@ extern unsigned long get_clock_freq(void); /* The mac addresses for all ethernet interface */ #if defined(CONFIG_TSEC_ENET) +#define CONFIG_HAS_ETH0 #define CONFIG_ETHADDR 00:E0:0C:00:00:FD #define CONFIG_HAS_ETH1 #define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD diff --git a/include/configs/MPC8555CDS.h b/include/configs/MPC8555CDS.h index 48a2663b5..8d7d6579d 100644 --- a/include/configs/MPC8555CDS.h +++ b/include/configs/MPC8555CDS.h @@ -481,6 +481,7 @@ extern unsigned long get_clock_freq(void); /* The mac addresses for all ethernet interface */ #if defined(CONFIG_TSEC_ENET) +#define CONFIG_HAS_ETH0 #define CONFIG_ETHADDR 00:E0:0C:00:00:FD #define CONFIG_HAS_ETH1 #define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD diff --git a/include/configs/MPC8560ADS.h b/include/configs/MPC8560ADS.h index da41dadcd..b3c33d9f7 100644 --- a/include/configs/MPC8560ADS.h +++ b/include/configs/MPC8560ADS.h @@ -522,6 +522,7 @@ /* The mac addresses for all ethernet interface */ #if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC) +#define CONFIG_HAS_ETH0 #define CONFIG_ETHADDR 00:E0:0C:00:00:FD #define CONFIG_HAS_ETH1 #define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h index e912331f3..03e815d87 100644 --- a/include/configs/MPC8641HPCN.h +++ b/include/configs/MPC8641HPCN.h @@ -608,6 +608,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_ETH3ADDR 00:E0:0C:00:03:FD #endif +#define CONFIG_HAS_ETH0 1 #define CONFIG_HAS_ETH1 1 #define CONFIG_HAS_ETH2 1 #define CONFIG_HAS_ETH3 1 diff --git a/include/configs/PM854.h b/include/configs/PM854.h index 93090b981..a6a1e738a 100644 --- a/include/configs/PM854.h +++ b/include/configs/PM854.h @@ -282,6 +282,7 @@ /* Options are: TSEC[0-1] */ #define CONFIG_ETHPRIME "TSEC0" +#define CONFIG_HAS_ETH0 #define CONFIG_HAS_ETH1 1 #define CONFIG_HAS_ETH2 1 diff --git a/include/configs/PM856.h b/include/configs/PM856.h index 6105747c7..9a17e3d73 100644 --- a/include/configs/PM856.h +++ b/include/configs/PM856.h @@ -392,6 +392,7 @@ /* The mac addresses for all ethernet interface */ #if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC) +#define CONFIG_HAS_ETH0 #define CONFIG_ETHADDR 00:40:42:01:00:00 #define CONFIG_HAS_ETH1 #define CONFIG_ETH1ADDR 00:40:42:01:00:01 diff --git a/include/configs/TQM834x.h b/include/configs/TQM834x.h index 91c1694f2..01472529d 100644 --- a/include/configs/TQM834x.h +++ b/include/configs/TQM834x.h @@ -501,6 +501,7 @@ extern int tqm834x_num_flash_banks; */ #if defined(CONFIG_TSEC_ENET) +#define CONFIG_HAS_ETH0 #define CONFIG_ETHADDR D2:DA:5E:44:BC:29 #define CONFIG_HAS_ETH1 #define CONFIG_ETH1ADDR 1E:F3:40:21:92:53 diff --git a/include/configs/TQM85xx.h b/include/configs/TQM85xx.h index cb9bf5492..a330c4220 100644 --- a/include/configs/TQM85xx.h +++ b/include/configs/TQM85xx.h @@ -271,6 +271,7 @@ #define FEC_PHY_ADDR 3 #define FEC_PHYIDX 0 #define FEC_FLAGS 0 +#define CONFIG_HAS_ETH0 #define CONFIG_HAS_ETH1 #define CONFIG_HAS_ETH2 diff --git a/include/configs/sbc8349.h b/include/configs/sbc8349.h index aa515ea61..37a8f8705 100644 --- a/include/configs/sbc8349.h +++ b/include/configs/sbc8349.h @@ -662,6 +662,7 @@ #define CONFIG_ENV_OVERWRITE #if defined(CONFIG_TSEC_ENET) +#define CONFIG_HAS_ETH0 #define CONFIG_ETHADDR 00:a0:1e:a0:13:8d #define CONFIG_HAS_ETH1 #define CONFIG_ETH1ADDR 00:a0:1e:a0:13:8e diff --git a/include/configs/sbc8641d.h b/include/configs/sbc8641d.h index 760b754e6..3525ab4c5 100644 --- a/include/configs/sbc8641d.h +++ b/include/configs/sbc8641d.h @@ -546,6 +546,7 @@ #define CONFIG_ETH3ADDR 02:E0:0C:00:03:FD #endif +#define CONFIG_HAS_ETH0 1 #define CONFIG_HAS_ETH1 1 #define CONFIG_HAS_ETH2 1 #define CONFIG_HAS_ETH3 1 diff --git a/include/configs/stxgp3.h b/include/configs/stxgp3.h index 43b185bee..c5ae0cde3 100644 --- a/include/configs/stxgp3.h +++ b/include/configs/stxgp3.h @@ -379,6 +379,7 @@ /*Note: change below for your network setting!!! */ #if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC) +#define CONFIG_HAS_ETH0 #define CONFIG_ETHADDR 00:e0:0c:07:9b:8a #define CONFIG_HAS_ETH1 #define CONFIG_ETH1ADDR 00:e0:0c:07:9b:8b diff --git a/include/configs/stxssa.h b/include/configs/stxssa.h index 3dae27ac1..f32ff67d9 100644 --- a/include/configs/stxssa.h +++ b/include/configs/stxssa.h @@ -407,6 +407,7 @@ /*Note: change below for your network setting!!! */ #if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC) +#define CONFIG_HAS_ETH0 #define CONFIG_ETHADDR 00:e0:0c:07:9b:8a #define CONFIG_HAS_ETH1 #define CONFIG_ETH1ADDR 00:e0:0c:07:9b:8b From ab77bc547ba561c25ea34457ed17aa0b2f7c2723 Mon Sep 17 00:00:00 2001 From: TsiChungLiew Date: Wed, 15 Aug 2007 15:39:17 -0500 Subject: [PATCH 153/259] ColdFire: MCF5329 Update and cleanup Signed-off-by: TsiChungLiew --- Makefile | 2 +- board/freescale/m5329evb/mii.c | 8 ++-- board/freescale/m5329evb/nand.c | 2 +- common/cmd_bdinfo.c | 12 +++--- drivers/net/mcffec.c | 10 ++--- include/asm-m68k/immap.h | 2 + include/asm-m68k/io.h | 60 ++++++++++++++-------------- include/asm-m68k/timer.h | 14 +++++++ include/configs/M5329EVB.h | 69 +++++++++++++++------------------ lib_m68k/board.c | 2 +- lib_m68k/time.c | 3 +- rtc/mcfrtc.c | 4 +- 12 files changed, 99 insertions(+), 89 deletions(-) diff --git a/Makefile b/Makefile index 2bb11b6f8..79ab40b1a 100644 --- a/Makefile +++ b/Makefile @@ -1682,7 +1682,7 @@ M5329BFEE_config : unconfig esac; \ >include/config.h ; \ if [ "$${NAND}" != "0" ] ; then \ - echo "#define NANDFLASH_SIZE $${NAND}" >> include/config.h ; \ + echo "#define NANDFLASH_SIZE $${NAND}" > $(obj)include/config.h ; \ fi @$(MKCONFIG) -a M5329EVB m68k mcf532x m5329evb freescale diff --git a/board/freescale/m5329evb/mii.c b/board/freescale/m5329evb/mii.c index 68dc04fd9..31f1510cc 100644 --- a/board/freescale/m5329evb/mii.c +++ b/board/freescale/m5329evb/mii.c @@ -30,7 +30,7 @@ DECLARE_GLOBAL_DATA_PTR; -#if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(CONFIG_NET_MULTI) +#if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI) #undef MII_DEBUG #undef ET_DEBUG @@ -50,7 +50,7 @@ int fecpin_setclear(struct eth_device *dev, int setclear) return 0; } -#if defined(CFG_DISCOVER_PHY) || (CONFIG_COMMANDS & CFG_CMD_MII) +#if defined(CFG_DISCOVER_PHY) || defined(CONFIG_CMD_MII) #include /* Make MII read/write commands for the FEC. */ @@ -134,7 +134,7 @@ uint mii_send(uint mii_cmd) return (mii_reply & 0xffff); /* data read from phy */ } -#endif /* CFG_DISCOVER_PHY || (CONFIG_COMMANDS & CFG_CMD_MII) */ +#endif /* CFG_DISCOVER_PHY || CONFIG_CMD_MII */ #if defined(CFG_DISCOVER_PHY) int mii_discover_phy(struct eth_device *dev) @@ -303,4 +303,4 @@ int mcffec_miiphy_write(char *devname, unsigned char addr, unsigned char reg, return 0; } -#endif /* CFG_CMD_NET, FEC_ENET & NET_MULTI */ +#endif /* CONFIG_CMD_NET, FEC_ENET & NET_MULTI */ diff --git a/board/freescale/m5329evb/nand.c b/board/freescale/m5329evb/nand.c index 2272a2446..fefb42e61 100644 --- a/board/freescale/m5329evb/nand.c +++ b/board/freescale/m5329evb/nand.c @@ -31,7 +31,7 @@ DECLARE_GLOBAL_DATA_PTR; -#if (CONFIG_COMMANDS & CFG_CMD_NAND) +#if defined(CONFIG_CMD_NAND) #include #include diff --git a/common/cmd_bdinfo.c b/common/cmd_bdinfo.c index 58ee9f350..889cff841 100644 --- a/common/cmd_bdinfo.c +++ b/common/cmd_bdinfo.c @@ -225,7 +225,7 @@ int do_bdinfo ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) #if defined(CFG_MBAR) print_num ("mbar", bd->bi_mbar_base ); #endif -#if defined(CFG_CMD_NET) +#if defined(CONFIG_CMD_NET) puts ("ethaddr ="); for (i=0; i<6; ++i) { printf ("%c%02X", i ? ':' : ' ', bd->bi_enetaddr[i]); @@ -239,22 +239,22 @@ int do_bdinfo ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) #endif #if defined(CONFIG_HAS_ETH2) - puts ("\neth2addr ="); - for (i=0; i<6; ++i) { + puts ("\neth2addr ="); + for (i=0; i<6; ++i) { printf ("%c%02X", i ? ':' : ' ', bd->bi_enet2addr[i]); } #endif #if defined(CONFIG_HAS_ETH3) - puts ("\neth3addr ="); - for (i=0; i<6; ++i) { + puts ("\neth3addr ="); + for (i=0; i<6; ++i) { printf ("%c%02X", i ? ':' : ' ', bd->bi_enet3addr[i]); } #endif puts ("\nip_addr = "); print_IPaddr (bd->bi_ip_addr); -#endif /* CFG_CMD_NET */ +#endif /* CONFIG_CMD_NET */ printf ("\nbaudrate = %d bps\n", bd->bi_baudrate); return 0; diff --git a/drivers/net/mcffec.c b/drivers/net/mcffec.c index fde1aaecb..68a0ee640 100644 --- a/drivers/net/mcffec.c +++ b/drivers/net/mcffec.c @@ -51,7 +51,7 @@ DECLARE_GLOBAL_DATA_PTR; -#if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(CONFIG_NET_MULTI) +#if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI) struct fec_info_s fec_info[] = { #ifdef CFG_FEC0_IOBASE @@ -410,7 +410,7 @@ int fec_init(struct eth_device *dev, bd_t * bd) fec_reset(dev); -#if (CONFIG_COMMANDS & CFG_CMD_MII) || defined (CONFIG_MII) || \ +#if defined(CONFIG_CMD_MII) || defined (CONFIG_MII) || \ defined (CFG_DISCOVER_PHY) mii_init(); @@ -420,7 +420,7 @@ int fec_init(struct eth_device *dev, bd_t * bd) #ifndef CFG_DISCOVER_PHY setFecDuplexSpeed(fecp, bd, (FECDUPLEX << 16) | FECSPEED); #endif /* ifndef CFG_DISCOVER_PHY */ -#endif /* CFG_CMD_MII || CONFIG_MII */ +#endif /* CONFIG_CMD_MII || CONFIG_MII */ /* We use strictly polling mode only */ fecp->eimr = 0; @@ -568,7 +568,7 @@ int mcffec_initialize(bd_t * bis) eth_register(dev); -#if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII) +#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) miiphy_register(dev->name, mcffec_miiphy_read, mcffec_miiphy_write); #endif @@ -580,5 +580,5 @@ int mcffec_initialize(bd_t * bis) return 1; } -#endif /* CFG_CMD_NET, FEC_ENET & NET_MULTI */ +#endif /* CONFIG_CMD_NET, FEC_ENET & NET_MULTI */ #endif /* CONFIG_MCFFEC */ diff --git a/include/asm-m68k/immap.h b/include/asm-m68k/immap.h index 7c267af56..2555e7e82 100644 --- a/include/asm-m68k/immap.h +++ b/include/asm-m68k/immap.h @@ -38,8 +38,10 @@ #ifdef CONFIG_MCFTMR #define CFG_UDELAY_BASE (MMAP_DTMR0) #define CFG_TMR_BASE (MMAP_DTMR1) +#define CFG_TMRPND_REG (((volatile int0_t *)(CFG_INTR_BASE))->iprh0) #define CFG_TMRINTR_NO (INT0_HI_DTMR1) #define CFG_TMRINTR_MASK (INTC_IPRH_INT33) +#define CFG_TMRINTR_PEND (CFG_TMRINTR_MASK) #define CFG_TMRINTR_PRI (6) #define CFG_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8) #endif diff --git a/include/asm-m68k/io.h b/include/asm-m68k/io.h index 114efb15d..e14a581dc 100644 --- a/include/asm-m68k/io.h +++ b/include/asm-m68k/io.h @@ -28,18 +28,18 @@ #include -#define readb(addr) in_8((volatile u8 *)(addr)) -#define writeb(b,addr) out_8((volatile u8 *)(addr), (b)) +#define readb(addr) in_8((volatile u8 *)(addr)) +#define writeb(b,addr) out_8((volatile u8 *)(addr), (b)) #if !defined(__BIG_ENDIAN) -#define readw(addr) (*(volatile u16 *) (addr)) -#define readl(addr) (*(volatile u32 *) (addr)) -#define writew(b,addr) ((*(volatile u16 *) (addr)) = (b)) -#define writel(b,addr) ((*(volatile u32 *) (addr)) = (b)) +#define readw(addr) (*(volatile u16 *) (addr)) +#define readl(addr) (*(volatile u32 *) (addr)) +#define writew(b,addr) ((*(volatile u16 *) (addr)) = (b)) +#define writel(b,addr) ((*(volatile u32 *) (addr)) = (b)) #else -#define readw(addr) in_le16((volatile u16 *)(addr)) -#define readl(addr) in_le32((volatile u32 *)(addr)) -#define writew(b,addr) out_le16((volatile u16 *)(addr),(b)) -#define writel(b,addr) out_le32((volatile u32 *)(addr),(b)) +#define readw(addr) in_le16((volatile u16 *)(addr)) +#define readl(addr) in_le32((volatile u32 *)(addr)) +#define writew(b,addr) out_le16((volatile u16 *)(addr),(b)) +#define writel(b,addr) out_le32((volatile u32 *)(addr),(b)) #endif /* @@ -48,25 +48,25 @@ * are arrays of bytes, and byte-swapping is not appropriate in * that case. - paulus */ -#define insb(port, buf, ns) _insb((u8 *)((port)+_IO_BASE), (buf), (ns)) -#define outsb(port, buf, ns) _outsb((u8 *)((port)+_IO_BASE), (buf), (ns)) -#define insw(port, buf, ns) _insw_ns((u16 *)((port)+_IO_BASE), (buf), (ns)) -#define outsw(port, buf, ns) _outsw_ns((u16 *)((port)+_IO_BASE), (buf), (ns)) -#define insl(port, buf, nl) _insl_ns((u32 *)((port)+_IO_BASE), (buf), (nl)) -#define outsl(port, buf, nl) _outsl_ns((u32 *)((port)+_IO_BASE), (buf), (nl)) +#define insb(port, buf, ns) _insb((u8 *)((port)+_IO_BASE), (buf), (ns)) +#define outsb(port, buf, ns) _outsb((u8 *)((port)+_IO_BASE), (buf), (ns)) +#define insw(port, buf, ns) _insw_ns((u16 *)((port)+_IO_BASE), (buf), (ns)) +#define outsw(port, buf, ns) _outsw_ns((u16 *)((port)+_IO_BASE), (buf), (ns)) +#define insl(port, buf, nl) _insl_ns((u32 *)((port)+_IO_BASE), (buf), (nl)) +#define outsl(port, buf, nl) _outsl_ns((u32 *)((port)+_IO_BASE), (buf), (nl)) -#define inb(port) in_8((u8 *)((port)+_IO_BASE)) -#define outb(val, port) out_8((u8 *)((port)+_IO_BASE), (val)) +#define inb(port) in_8((u8 *)((port)+_IO_BASE)) +#define outb(val, port) out_8((u8 *)((port)+_IO_BASE), (val)) #if !defined(__BIG_ENDIAN) -#define inw(port) in_be16((u16 *)((port)+_IO_BASE)) -#define outw(val, port) out_be16((u16 *)((port)+_IO_BASE), (val)) -#define inl(port) in_be32((u32 *)((port)+_IO_BASE)) -#define outl(val, port) out_be32((u32 *)((port)+_IO_BASE), (val)) +#define inw(port) in_be16((u16 *)((port)+_IO_BASE)) +#define outw(val, port) out_be16((u16 *)((port)+_IO_BASE), (val)) +#define inl(port) in_be32((u32 *)((port)+_IO_BASE)) +#define outl(val, port) out_be32((u32 *)((port)+_IO_BASE), (val)) #else -#define inw(port) in_le16((u16 *)((port)+_IO_BASE)) -#define outw(val, port) out_le16((u16 *)((port)+_IO_BASE), (val)) -#define inl(port) in_le32((u32 *)((port)+_IO_BASE)) -#define outl(val, port) out_le32((u32 *)((port)+_IO_BASE), (val)) +#define inw(port) in_le16((u16 *)((port)+_IO_BASE)) +#define outw(val, port) out_le16((u16 *)((port)+_IO_BASE), (val)) +#define inl(port) in_le32((u32 *)((port)+_IO_BASE)) +#define outl(val, port) out_le32((u32 *)((port)+_IO_BASE), (val)) #endif extern inline void _insb(volatile u8 * port, void *buf, int ns) @@ -151,10 +151,10 @@ extern inline void _outsl_ns(volatile u32 * port, const void *buf, int nl) * Neither do the standard versions now, these are just here * for older code. */ -#define insw_ns(port, buf, ns) _insw_ns((u16 *)((port)+_IO_BASE), (buf), (ns)) -#define outsw_ns(port, buf, ns) _outsw_ns((u16 *)((port)+_IO_BASE), (buf), (ns)) -#define insl_ns(port, buf, nl) _insl_ns((u32 *)((port)+_IO_BASE), (buf), (nl)) -#define outsl_ns(port, buf, nl) _outsl_ns((u32 *)((port)+_IO_BASE), (buf), (nl)) +#define insw_ns(port, buf, ns) _insw_ns((u16 *)((port)+_IO_BASE), (buf), (ns)) +#define outsw_ns(port, buf, ns) _outsw_ns((u16 *)((port)+_IO_BASE), (buf), (ns)) +#define insl_ns(port, buf, nl) _insl_ns((u32 *)((port)+_IO_BASE), (buf), (nl)) +#define outsl_ns(port, buf, nl) _outsl_ns((u32 *)((port)+_IO_BASE), (buf), (nl)) #define IO_SPACE_LIMIT ~0 diff --git a/include/asm-m68k/timer.h b/include/asm-m68k/timer.h index d8f4e2a6a..3ec710d1f 100644 --- a/include/asm-m68k/timer.h +++ b/include/asm-m68k/timer.h @@ -33,12 +33,26 @@ /****************************************************************************/ /* DMA Timer module registers */ typedef struct dtimer_ctrl { +#if defined(CONFIG_M5249) || defined(CONFIG_M5253) u16 tmr; /* 0x00 Mode register */ + u16 res1; /* 0x02 */ + u16 trr; /* 0x04 Reference register */ + u16 res2; /* 0x06 */ + u16 tcr; /* 0x08 Capture register */ + u16 res3; /* 0x0A */ + u16 tcn; /* 0x0C Counter register */ + u16 res4; /* 0x0E */ + u8 res6; /* 0x10 */ + u8 ter; /* 0x11 Event register */ + u16 res7; /* 0x12 */ +#else + u16 tmr; /* 0x00 Mode register */ u8 txmr; /* 0x02 Extended Mode register */ u8 ter; /* 0x03 Event register */ u32 trr; /* 0x04 Reference register */ u32 tcr; /* 0x08 Capture register */ u32 tcn; /* 0x0C Counter register */ +#endif } dtmr_t; /*Programmable Interrupt Timer */ diff --git a/include/configs/M5329EVB.h b/include/configs/M5329EVB.h index 6a7e052a0..d3b160505 100644 --- a/include/configs/M5329EVB.h +++ b/include/configs/M5329EVB.h @@ -47,25 +47,23 @@ #undef CONFIG_WATCHDOG #define CONFIG_WATCHDOG_TIMEOUT 5000 /* timeout in milliseconds, max timeout is 6.71sec */ -#define DEFAULT_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_CACHE | \ - CFG_CMD_DATE | \ - CFG_CMD_ELF | \ - CFG_CMD_FLASH | \ - CFG_CMD_I2C | \ - (CFG_CMD_LOADB | CFG_CMD_LOADS) | \ - CFG_CMD_MEMORY | \ - CFG_CMD_MISC | \ - CFG_CMD_MII | \ - CFG_CMD_NET | \ - CFG_CMD_PING | \ - CFG_CMD_REGINFO \ - ) +/* Command line configuration */ +#include + +#define CONFIG_CMD_CACHE +#define CONFIG_CMD_DATE +#define CONFIG_CMD_ELF +#define CONFIG_CMD_FLASH +#define CONFIG_CMD_I2C +#define CONFIG_CMD_MEMORY +#define CONFIG_CMD_MISC +#define CONFIG_CMD_MII +#define CONFIG_CMD_NET +#define CONFIG_CMD_PING +#define CONFIG_CMD_REGINFO #ifdef NANDFLASH_SIZE -# define CONFIG_COMMANDS (DEFAULT_COMMANDS | CFG_CMD_NAND) -#else -# define CONFIG_COMMANDS (DEFAULT_COMMANDS) +# define CONFIG_CMD_NAND #endif #define CFG_UNIFY_CACHE @@ -108,9 +106,9 @@ #define CFG_I2C_OFFSET 0x58000 #define CFG_IMMR CFG_MBAR -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include #define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */ +#define CONFIG_UDP_CHECKSUM + #ifdef CONFIG_MCFFEC # define CONFIG_ETHADDR 00:e0:0c:bc:e5:60 # define CONFIG_IPADDR 192.162.1.2 @@ -137,7 +135,7 @@ #define CFG_PROMPT "-> " #define CFG_LONGHELP /* undef to save memory */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#ifdef CONFIG_CMD_KGDB # define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else # define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -154,7 +152,7 @@ #define CFG_MBAR 0xFC000000 -#define CFG_LATCH_ADDR (CFG_CS1_BASE + 0x80000) +#define CFG_LATCH_ADDR (CFG_CS1_BASE + 0x80000) /* * Low Level Configuration Settings @@ -168,7 +166,7 @@ #define CFG_INIT_RAM_END 0x8000 /* End of used area in internal SRAM */ #define CFG_INIT_RAM_CTRL 0x221 #define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_GBL_DATA_OFFSET ((CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) - 0x10) #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET /*----------------------------------------------------------------------- @@ -198,7 +196,7 @@ * have to be in the first 8 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization ?? */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ +#define CFG_BOOTMAPSZ (CFG_SDRAM_BASE + (CFG_SDRAM_SIZE << 20)) /*----------------------------------------------------------------------- * FLASH organization @@ -214,20 +212,19 @@ #endif #ifdef NANDFLASH_SIZE -# define CFG_MAX_NAND_DEVICE 1 -# define CFG_NAND_BASE (CFG_CS2_BASE << 16) -# define CFG_NAND_SIZE 1 -# define CFG_NAND_BASE_LIST { CFG_NAND_BASE } -# define NAND_MAX_CHIPS 1 -# define NAND_ALLOW_ERASE_ALL 1 -# define CONFIG_JFFS2_NAND 1 -# define CONFIG_JFFS2_DEV "nand0" -# define CONFIG_JFFS2_PART_SIZE (CFG_CS2_MASK & ~1) -# define CONFIG_JFFS2_PART_OFFSET 0x00000000 +# define CFG_MAX_NAND_DEVICE 1 +# define CFG_NAND_BASE (CFG_CS2_BASE << 16) +# define CFG_NAND_SIZE 1 +# define CFG_NAND_BASE_LIST { CFG_NAND_BASE } +# define NAND_MAX_CHIPS 1 +# define NAND_ALLOW_ERASE_ALL 1 +# define CONFIG_JFFS2_NAND 1 +# define CONFIG_JFFS2_DEV "nand0" +# define CONFIG_JFFS2_PART_SIZE (CFG_CS2_MASK & ~1) +# define CONFIG_JFFS2_PART_OFFSET 0x00000000 #endif -#define CFG_FLASH_BASE 0 -#define CFG_FLASH0_BASE (CFG_CS0_BASE << 16) +#define CFG_FLASH_BASE (CFG_CS0_BASE << 16) /* Configuration for environment * Environment is embedded in u-boot in the second sector of the flash @@ -267,6 +264,4 @@ #define CFG_CS2_CTRL 0x00001f60 #endif -#define CONFIG_UDP_CHECKSUM - #endif /* _M5329EVB_H */ diff --git a/lib_m68k/board.c b/lib_m68k/board.c index 395018c41..778ec788a 100644 --- a/lib_m68k/board.c +++ b/lib_m68k/board.c @@ -692,7 +692,7 @@ void board_init_r (gd_t *id, ulong dest_addr) #endif #if defined(CONFIG_NET_MULTI) puts ("Net: "); - eth_initialize (bd); + eth_initialize (bd); #endif #endif diff --git a/lib_m68k/time.c b/lib_m68k/time.c index 3dbce0721..6c19059e6 100644 --- a/lib_m68k/time.c +++ b/lib_m68k/time.c @@ -347,10 +347,9 @@ void udelay(unsigned long usec) void dtimer_interrupt(void *not_used) { volatile dtmr_t *timerp = (dtmr_t *) (CFG_TMR_BASE); - volatile int0_t *intp = (int0_t *) (CFG_INTR_BASE); /* check for timer interrupt asserted */ - if ((intp->iprh0 & CFG_TMRINTR_MASK) == CFG_TMRINTR_MASK) { + if ((CFG_TMRPND_REG & CFG_TMRINTR_MASK) == CFG_TMRINTR_PEND) { timerp->ter = (DTIM_DTER_CAP | DTIM_DTER_REF); timestamp++; return; diff --git a/rtc/mcfrtc.c b/rtc/mcfrtc.c index 0be587426..76bb5107f 100644 --- a/rtc/mcfrtc.c +++ b/rtc/mcfrtc.c @@ -28,7 +28,7 @@ #include #include -#if defined(CONFIG_MCFRTC) && (CONFIG_COMMANDS & CFG_CMD_DATE) +#if defined(CONFIG_MCFRTC) && defined(CONFIG_CMD_DATE) #undef RTC_DEBUG @@ -118,4 +118,4 @@ void rtc_reset(void) rtc->cr |= RTC_CR_SWR; } -#endif /* CONFIG_MCFRTC && CFG_CMD_DATE */ +#endif /* CONFIG_MCFRTC && CONFIG_CMD_DATE */ From 7171977fb8fd77cfb6676953fa9a05789c450513 Mon Sep 17 00:00:00 2001 From: TsiChungLiew Date: Wed, 15 Aug 2007 15:40:20 -0500 Subject: [PATCH 154/259] ColdFire: MCF5329 header file clean up Signed-off-by: TsiChungLiew --- include/asm-m68k/m5329.h | 2791 +++++++++++++++++--------------------- 1 file changed, 1213 insertions(+), 1578 deletions(-) diff --git a/include/asm-m68k/m5329.h b/include/asm-m68k/m5329.h index 15bb121ed..cd69fb0b5 100644 --- a/include/asm-m68k/m5329.h +++ b/include/asm-m68k/m5329.h @@ -31,1993 +31,1628 @@ * System Control Module (SCM) *********************************************************************/ /* Bit definitions and macros for SCM_MPR */ -#define SCM_MPR_MPROT0(x) (((x)&0x0F)<<28) -#define SCM_MPR_MPROT1(x) (((x)&0x0F)<<24) -#define SCM_MPR_MPROT2(x) (((x)&0x0F)<<20) -#define SCM_MPR_MPROT4(x) (((x)&0x0F)<<12) -#define SCM_MPR_MPROT5(x) (((x)&0x0F)<<8) -#define SCM_MPR_MPROT6(x) (((x)&0x0F)<<4) -#define MPROT_MTR 4 -#define MPROT_MTW 2 -#define MPROT_MPL 1 +#define SCM_MPR_MPROT0(x) (((x)&0x0F)<<28) +#define SCM_MPR_MPROT1(x) (((x)&0x0F)<<24) +#define SCM_MPR_MPROT2(x) (((x)&0x0F)<<20) +#define SCM_MPR_MPROT4(x) (((x)&0x0F)<<12) +#define SCM_MPR_MPROT5(x) (((x)&0x0F)<<8) +#define SCM_MPR_MPROT6(x) (((x)&0x0F)<<4) +#define MPROT_MTR 4 +#define MPROT_MTW 2 +#define MPROT_MPL 1 /* Bit definitions and macros for SCM_BMT */ -#define BMT_BME (0x08) -#define BMT_8 (0x07) -#define BMT_16 (0x06) -#define BMT_32 (0x05) -#define BMT_64 (0x04) -#define BMT_128 (0x03) -#define BMT_256 (0x02) -#define BMT_512 (0x01) -#define BMT_1024 (0x00) +#define BMT_BME (0x08) +#define BMT_8 (0x07) +#define BMT_16 (0x06) +#define BMT_32 (0x05) +#define BMT_64 (0x04) +#define BMT_128 (0x03) +#define BMT_256 (0x02) +#define BMT_512 (0x01) +#define BMT_1024 (0x00) /* Bit definitions and macros for SCM_PACRA */ -#define SCM_PACRA_PACR0(x) (((x)&0x0F)<<28) -#define SCM_PACRA_PACR1(x) (((x)&0x0F)<<24) -#define SCM_PACRA_PACR2(x) (((x)&0x0F)<<20) -#define PACR_SP 4 -#define PACR_WP 2 -#define PACR_TP 1 +#define SCM_PACRA_PACR0(x) (((x)&0x0F)<<28) +#define SCM_PACRA_PACR1(x) (((x)&0x0F)<<24) +#define SCM_PACRA_PACR2(x) (((x)&0x0F)<<20) +#define PACR_SP 4 +#define PACR_WP 2 +#define PACR_TP 1 /* Bit definitions and macros for SCM_PACRB */ -#define SCM_PACRB_PACR8(x) (((x)&0x0F)<<28) -#define SCM_PACRB_PACR12(x) (((x)&0x0F)<<12) +#define SCM_PACRB_PACR8(x) (((x)&0x0F)<<28) +#define SCM_PACRB_PACR12(x) (((x)&0x0F)<<12) /* Bit definitions and macros for SCM_PACRC */ -#define SCM_PACRC_PACR16(x) (((x)&0x0F)<<28) -#define SCM_PACRC_PACR17(x) (((x)&0x0F)<<24) -#define SCM_PACRC_PACR18(x) (((x)&0x0F)<<20) -#define SCM_PACRC_PACR19(x) (((x)&0x0F)<<16) -#define SCM_PACRC_PACR21(x) (((x)&0x0F)<<8) -#define SCM_PACRC_PACR22(x) (((x)&0x0F)<<4) -#define SCM_PACRC_PACR23(x) (((x)&0x0F)<<0) +#define SCM_PACRC_PACR16(x) (((x)&0x0F)<<28) +#define SCM_PACRC_PACR17(x) (((x)&0x0F)<<24) +#define SCM_PACRC_PACR18(x) (((x)&0x0F)<<20) +#define SCM_PACRC_PACR19(x) (((x)&0x0F)<<16) +#define SCM_PACRC_PACR21(x) (((x)&0x0F)<<8) +#define SCM_PACRC_PACR22(x) (((x)&0x0F)<<4) +#define SCM_PACRC_PACR23(x) (((x)&0x0F)<<0) /* Bit definitions and macros for SCM_PACRD */ -#define SCM_PACRD_PACR24(x) (((x)&0x0F)<<28) -#define SCM_PACRD_PACR25(x) (((x)&0x0F)<<24) -#define SCM_PACRD_PACR26(x) (((x)&0x0F)<<20) -#define SCM_PACRD_PACR28(x) (((x)&0x0F)<<12) -#define SCM_PACRD_PACR29(x) (((x)&0x0F)<<8) -#define SCM_PACRD_PACR30(x) (((x)&0x0F)<<4) -#define SCM_PACRD_PACR31(x) (((x)&0x0F)<<0) +#define SCM_PACRD_PACR24(x) (((x)&0x0F)<<28) +#define SCM_PACRD_PACR25(x) (((x)&0x0F)<<24) +#define SCM_PACRD_PACR26(x) (((x)&0x0F)<<20) +#define SCM_PACRD_PACR28(x) (((x)&0x0F)<<12) +#define SCM_PACRD_PACR29(x) (((x)&0x0F)<<8) +#define SCM_PACRD_PACR30(x) (((x)&0x0F)<<4) +#define SCM_PACRD_PACR31(x) (((x)&0x0F)<<0) /* Bit definitions and macros for SCM_PACRE */ -#define SCM_PACRE_PACR32(x) (((x)&0x0F)<<28) -#define SCM_PACRE_PACR33(x) (((x)&0x0F)<<24) -#define SCM_PACRE_PACR34(x) (((x)&0x0F)<<20) -#define SCM_PACRE_PACR35(x) (((x)&0x0F)<<16) -#define SCM_PACRE_PACR36(x) (((x)&0x0F)<<12) -#define SCM_PACRE_PACR37(x) (((x)&0x0F)<<8) -#define SCM_PACRE_PACR38(x) (((x)&0x0F)<<4) +#define SCM_PACRE_PACR32(x) (((x)&0x0F)<<28) +#define SCM_PACRE_PACR33(x) (((x)&0x0F)<<24) +#define SCM_PACRE_PACR34(x) (((x)&0x0F)<<20) +#define SCM_PACRE_PACR35(x) (((x)&0x0F)<<16) +#define SCM_PACRE_PACR36(x) (((x)&0x0F)<<12) +#define SCM_PACRE_PACR37(x) (((x)&0x0F)<<8) +#define SCM_PACRE_PACR38(x) (((x)&0x0F)<<4) /* Bit definitions and macros for SCM_PACRF */ -#define SCM_PACRF_PACR40(x) (((x)&0x0F)<<28) -#define SCM_PACRF_PACR41(x) (((x)&0x0F)<<24) -#define SCM_PACRF_PACR42(x) (((x)&0x0F)<<20) -#define SCM_PACRF_PACR43(x) (((x)&0x0F)<<16) -#define SCM_PACRF_PACR44(x) (((x)&0x0F)<<12) -#define SCM_PACRF_PACR45(x) (((x)&0x0F)<<8) -#define SCM_PACRF_PACR46(x) (((x)&0x0F)<<4) -#define SCM_PACRF_PACR47(x) (((x)&0x0F)<<0) +#define SCM_PACRF_PACR40(x) (((x)&0x0F)<<28) +#define SCM_PACRF_PACR41(x) (((x)&0x0F)<<24) +#define SCM_PACRF_PACR42(x) (((x)&0x0F)<<20) +#define SCM_PACRF_PACR43(x) (((x)&0x0F)<<16) +#define SCM_PACRF_PACR44(x) (((x)&0x0F)<<12) +#define SCM_PACRF_PACR45(x) (((x)&0x0F)<<8) +#define SCM_PACRF_PACR46(x) (((x)&0x0F)<<4) +#define SCM_PACRF_PACR47(x) (((x)&0x0F)<<0) /* Bit definitions and macros for SCM_PACRG */ -#define SCM_PACRG_PACR48(x) (((x)&0x0F)<<28) +#define SCM_PACRG_PACR48(x) (((x)&0x0F)<<28) /* Bit definitions and macros for SCM_PACRH */ -#define SCM_PACRH_PACR56(x) (((x)&0x0F)<<28) -#define SCM_PACRH_PACR57(x) (((x)&0x0F)<<24) -#define SCM_PACRH_PACR58(x) (((x)&0x0F)<<20) +#define SCM_PACRH_PACR56(x) (((x)&0x0F)<<28) +#define SCM_PACRH_PACR57(x) (((x)&0x0F)<<24) +#define SCM_PACRH_PACR58(x) (((x)&0x0F)<<20) /* PACRn Assignments */ -#define PACR0(x) SCM_PACRA_PACR0(x) -#define PACR1(x) SCM_PACRA_PACR1(x) -#define PACR2(x) SCM_PACRA_PACR2(x) -#define PACR8(x) SCM_PACRB_PACR8(x) -#define PACR12(x) SCM_PACRB_PACR12(x) -#define PACR16(x) SCM_PACRC_PACR16(x) -#define PACR17(x) SCM_PACRC_PACR17(x) -#define PACR18(x) SCM_PACRC_PACR18(x) -#define PACR19(x) SCM_PACRC_PACR19(x) -#define PACR21(x) SCM_PACRC_PACR21(x) -#define PACR22(x) SCM_PACRC_PACR22(x) -#define PACR23(x) SCM_PACRC_PACR23(x) -#define PACR24(x) SCM_PACRD_PACR24(x) -#define PACR25(x) SCM_PACRD_PACR25(x) -#define PACR26(x) SCM_PACRD_PACR26(x) -#define PACR28(x) SCM_PACRD_PACR28(x) -#define PACR29(x) SCM_PACRD_PACR29(x) -#define PACR30(x) SCM_PACRD_PACR30(x) -#define PACR31(x) SCM_PACRD_PACR31(x) -#define PACR32(x) SCM_PACRE_PACR32(x) -#define PACR33(x) SCM_PACRE_PACR33(x) -#define PACR34(x) SCM_PACRE_PACR34(x) -#define PACR35(x) SCM_PACRE_PACR35(x) -#define PACR36(x) SCM_PACRE_PACR36(x) -#define PACR37(x) SCM_PACRE_PACR37(x) -#define PACR38(x) SCM_PACRE_PACR38(x) -#define PACR40(x) SCM_PACRF_PACR40(x) -#define PACR41(x) SCM_PACRF_PACR41(x) -#define PACR42(x) SCM_PACRF_PACR42(x) -#define PACR43(x) SCM_PACRF_PACR43(x) -#define PACR44(x) SCM_PACRF_PACR44(x) -#define PACR45(x) SCM_PACRF_PACR45(x) -#define PACR46(x) SCM_PACRF_PACR46(x) -#define PACR47(x) SCM_PACRF_PACR47(x) -#define PACR48(x) SCM_PACRG_PACR48(x) -#define PACR56(x) SCM_PACRH_PACR56(x) -#define PACR57(x) SCM_PACRH_PACR57(x) -#define PACR58(x) SCM_PACRH_PACR58(x) +#define PACR0(x) SCM_PACRA_PACR0(x) +#define PACR1(x) SCM_PACRA_PACR1(x) +#define PACR2(x) SCM_PACRA_PACR2(x) +#define PACR8(x) SCM_PACRB_PACR8(x) +#define PACR12(x) SCM_PACRB_PACR12(x) +#define PACR16(x) SCM_PACRC_PACR16(x) +#define PACR17(x) SCM_PACRC_PACR17(x) +#define PACR18(x) SCM_PACRC_PACR18(x) +#define PACR19(x) SCM_PACRC_PACR19(x) +#define PACR21(x) SCM_PACRC_PACR21(x) +#define PACR22(x) SCM_PACRC_PACR22(x) +#define PACR23(x) SCM_PACRC_PACR23(x) +#define PACR24(x) SCM_PACRD_PACR24(x) +#define PACR25(x) SCM_PACRD_PACR25(x) +#define PACR26(x) SCM_PACRD_PACR26(x) +#define PACR28(x) SCM_PACRD_PACR28(x) +#define PACR29(x) SCM_PACRD_PACR29(x) +#define PACR30(x) SCM_PACRD_PACR30(x) +#define PACR31(x) SCM_PACRD_PACR31(x) +#define PACR32(x) SCM_PACRE_PACR32(x) +#define PACR33(x) SCM_PACRE_PACR33(x) +#define PACR34(x) SCM_PACRE_PACR34(x) +#define PACR35(x) SCM_PACRE_PACR35(x) +#define PACR36(x) SCM_PACRE_PACR36(x) +#define PACR37(x) SCM_PACRE_PACR37(x) +#define PACR38(x) SCM_PACRE_PACR38(x) +#define PACR40(x) SCM_PACRF_PACR40(x) +#define PACR41(x) SCM_PACRF_PACR41(x) +#define PACR42(x) SCM_PACRF_PACR42(x) +#define PACR43(x) SCM_PACRF_PACR43(x) +#define PACR44(x) SCM_PACRF_PACR44(x) +#define PACR45(x) SCM_PACRF_PACR45(x) +#define PACR46(x) SCM_PACRF_PACR46(x) +#define PACR47(x) SCM_PACRF_PACR47(x) +#define PACR48(x) SCM_PACRG_PACR48(x) +#define PACR56(x) SCM_PACRH_PACR56(x) +#define PACR57(x) SCM_PACRH_PACR57(x) +#define PACR58(x) SCM_PACRH_PACR58(x) /* Bit definitions and macros for SCM_CWCR */ -#define CWCR_RO (0x8000) -#define CWCR_CWR_WH (0x0100) -#define CWCR_CWE (0x0080) -#define CWRI_WINDOW (0x0060) -#define CWRI_RESET (0x0040) -#define CWRI_INT_RESET (0x0020) -#define CWRI_INT (0x0000) -#define CWCR_CWT(x) (((x)&0x001F)) +#define CWCR_RO (0x8000) +#define CWCR_CWR_WH (0x0100) +#define CWCR_CWE (0x0080) +#define CWRI_WINDOW (0x0060) +#define CWRI_RESET (0x0040) +#define CWRI_INT_RESET (0x0020) +#define CWRI_INT (0x0000) +#define CWCR_CWT(x) (((x)&0x001F)) /* Bit definitions and macros for SCM_ISR */ -#define SCMISR_CFEI (0x02) -#define SCMISR_CWIC (0x01) +#define SCMISR_CFEI (0x02) +#define SCMISR_CWIC (0x01) /* Bit definitions and macros for SCM_BCR */ -#define BCR_GBR (0x00000200) -#define BCR_GBW (0x00000100) -#define BCR_S7 (0x00000080) -#define BCR_S6 (0x00000040) -#define BCR_S4 (0x00000010) -#define BCR_S1 (0x00000002) +#define BCR_GBR (0x00000200) +#define BCR_GBW (0x00000100) +#define BCR_S7 (0x00000080) +#define BCR_S6 (0x00000040) +#define BCR_S4 (0x00000010) +#define BCR_S1 (0x00000002) /* Bit definitions and macros for SCM_CFIER */ -#define CFIER_ECFEI (0x01) +#define CFIER_ECFEI (0x01) /* Bit definitions and macros for SCM_CFLOC */ -#define CFLOC_LOC (0x80) +#define CFLOC_LOC (0x80) /* Bit definitions and macros for SCM_CFATR */ -#define CFATR_WRITE (0x80) -#define CFATR_SZ32 (0x20) -#define CFATR_SZ16 (0x10) -#define CFATR_SZ08 (0x00) -#define CFATR_CACHE (0x08) -#define CFATR_MODE (0x02) -#define CFATR_TYPE (0x01) - -/********************************************************************* -* -* Random Number Generator (RNG) -* -*********************************************************************/ -/* Bit definitions and macros for RNG_RNGCR */ -#define RNGCR_CI (0x00000008) -#define RNGCR_IM (0x00000004) -#define RNGCR_HA (0x00000002) -#define RNGCR_GO (0x00000001) - -/* Bit definitions and macros for RNG_RNGSR */ -#define RNGSR_OFS(x) (((x)&0xFF)<<16) -#define RNGSR_OFL(x) (((x)&0xFF)<<8) -#define RNGSR_EI (0x00000008) -#define RNGSR_FUF (0x00000004) -#define RNGSR_LRS (0x00000002) -#define RNGSR_SV (0x00000001) +#define CFATR_WRITE (0x80) +#define CFATR_SZ32 (0x20) +#define CFATR_SZ16 (0x10) +#define CFATR_SZ08 (0x00) +#define CFATR_CACHE (0x08) +#define CFATR_MODE (0x02) +#define CFATR_TYPE (0x01) /********************************************************************* * FlexBus Chip Selects (FBCS) *********************************************************************/ /* Bit definitions and macros for FBCS_CSAR */ -#define CSAR_BA(x) (((x)&0xFFFF)<<16) +#define CSAR_BA(x) (((x)&0xFFFF)<<16) /* Bit definitions and macros for FBCS_CSMR */ -#define CSMR_BAM(x) (((x)&0xFFFF)<<16) -#define CSMR_BAM_4G (0xFFFF0000) -#define CSMR_BAM_2G (0x7FFF0000) -#define CSMR_BAM_1G (0x3FFF0000) -#define CSMR_BAM_1024M (0x3FFF0000) -#define CSMR_BAM_512M (0x1FFF0000) -#define CSMR_BAM_256M (0x0FFF0000) -#define CSMR_BAM_128M (0x07FF0000) -#define CSMR_BAM_64M (0x03FF0000) -#define CSMR_BAM_32M (0x01FF0000) -#define CSMR_BAM_16M (0x00FF0000) -#define CSMR_BAM_8M (0x007F0000) -#define CSMR_BAM_4M (0x003F0000) -#define CSMR_BAM_2M (0x001F0000) -#define CSMR_BAM_1M (0x000F0000) -#define CSMR_BAM_1024K (0x000F0000) -#define CSMR_BAM_512K (0x00070000) -#define CSMR_BAM_256K (0x00030000) -#define CSMR_BAM_128K (0x00010000) -#define CSMR_BAM_64K (0x00000000) -#define CSMR_WP (0x00000100) -#define CSMR_V (0x00000001) +#define CSMR_BAM(x) (((x)&0xFFFF)<<16) +#define CSMR_BAM_4G (0xFFFF0000) +#define CSMR_BAM_2G (0x7FFF0000) +#define CSMR_BAM_1G (0x3FFF0000) +#define CSMR_BAM_1024M (0x3FFF0000) +#define CSMR_BAM_512M (0x1FFF0000) +#define CSMR_BAM_256M (0x0FFF0000) +#define CSMR_BAM_128M (0x07FF0000) +#define CSMR_BAM_64M (0x03FF0000) +#define CSMR_BAM_32M (0x01FF0000) +#define CSMR_BAM_16M (0x00FF0000) +#define CSMR_BAM_8M (0x007F0000) +#define CSMR_BAM_4M (0x003F0000) +#define CSMR_BAM_2M (0x001F0000) +#define CSMR_BAM_1M (0x000F0000) +#define CSMR_BAM_1024K (0x000F0000) +#define CSMR_BAM_512K (0x00070000) +#define CSMR_BAM_256K (0x00030000) +#define CSMR_BAM_128K (0x00010000) +#define CSMR_BAM_64K (0x00000000) +#define CSMR_WP (0x00000100) +#define CSMR_V (0x00000001) /* Bit definitions and macros for FBCS_CSCR */ -#define CSCR_SWS(x) (((x)&0x3F)<<26) -#define CSCR_ASET(x) (((x)&0x03)<<20) -#define CSCR_SWSEN (0x00800000) -#define CSCR_ASET_4CLK (0x00300000) -#define CSCR_ASET_3CLK (0x00200000) -#define CSCR_ASET_2CLK (0x00100000) -#define CSCR_ASET_1CLK (0x00000000) -#define CSCR_RDAH(x) (((x)&0x03)<<18) -#define CSCR_RDAH_4CYC (0x000C0000) -#define CSCR_RDAH_3CYC (0x00080000) -#define CSCR_RDAH_2CYC (0x00040000) -#define CSCR_RDAH_1CYC (0x00000000) -#define CSCR_WRAH(x) (((x)&0x03)<<16) -#define CSCR_WDAH_4CYC (0x00003000) -#define CSCR_WDAH_3CYC (0x00002000) -#define CSCR_WDAH_2CYC (0x00001000) -#define CSCR_WDAH_1CYC (0x00000000) -#define CSCR_WS(x) (((x)&0x3F)<<10) -#define CSCR_SBM (0x00000200) -#define CSCR_AA (0x00000100) -#define CSCR_PS_MASK (0x000000C0) -#define CSCR_PS_32 (0x00000000) -#define CSCR_PS_16 (0x00000080) -#define CSCR_PS_8 (0x00000040) -#define CSCR_BEM (0x00000020) -#define CSCR_BSTR (0x00000010) -#define CSCR_BSTW (0x00000008) +#define CSCR_SWS(x) (((x)&0x3F)<<26) +#define CSCR_ASET(x) (((x)&0x03)<<20) +#define CSCR_SWSEN (0x00800000) +#define CSCR_ASET_4CLK (0x00300000) +#define CSCR_ASET_3CLK (0x00200000) +#define CSCR_ASET_2CLK (0x00100000) +#define CSCR_ASET_1CLK (0x00000000) +#define CSCR_RDAH(x) (((x)&0x03)<<18) +#define CSCR_RDAH_4CYC (0x000C0000) +#define CSCR_RDAH_3CYC (0x00080000) +#define CSCR_RDAH_2CYC (0x00040000) +#define CSCR_RDAH_1CYC (0x00000000) +#define CSCR_WRAH(x) (((x)&0x03)<<16) +#define CSCR_WDAH_4CYC (0x00003000) +#define CSCR_WDAH_3CYC (0x00002000) +#define CSCR_WDAH_2CYC (0x00001000) +#define CSCR_WDAH_1CYC (0x00000000) +#define CSCR_WS(x) (((x)&0x3F)<<10) +#define CSCR_SBM (0x00000200) +#define CSCR_AA (0x00000100) +#define CSCR_PS_MASK (0x000000C0) +#define CSCR_PS_32 (0x00000000) +#define CSCR_PS_16 (0x00000080) +#define CSCR_PS_8 (0x00000040) +#define CSCR_BEM (0x00000020) +#define CSCR_BSTR (0x00000010) +#define CSCR_BSTW (0x00000008) /********************************************************************* * FlexCAN Module (CAN) *********************************************************************/ /* Bit definitions and macros for CAN_CANMCR */ -#define CANMCR_MDIS (0x80000000) -#define CANMCR_FRZ (0x40000000) -#define CANMCR_HALT (0x10000000) -#define CANMCR_NORDY (0x08000000) -#define CANMCR_SOFTRST (0x02000000) -#define CANMCR_FRZACK (0x01000000) -#define CANMCR_SUPV (0x00800000) -#define CANMCR_LPMACK (0x00100000) -#define CANMCR_MAXMB(x) (((x)&0x0F)) +#define CANMCR_MDIS (0x80000000) +#define CANMCR_FRZ (0x40000000) +#define CANMCR_HALT (0x10000000) +#define CANMCR_NORDY (0x08000000) +#define CANMCR_SOFTRST (0x02000000) +#define CANMCR_FRZACK (0x01000000) +#define CANMCR_SUPV (0x00800000) +#define CANMCR_LPMACK (0x00100000) +#define CANMCR_MAXMB(x) (((x)&0x0F)) /* Bit definitions and macros for CAN_CANCTRL */ -#define CANCTRL_PRESDIV(x) (((x)&0xFF)<<24) -#define CANCTRL_RJW(x) (((x)&0x03)<<22) -#define CANCTRL_PSEG1(x) (((x)&0x07)<<19) -#define CANCTRL_PSEG2(x) (((x)&0x07)<<16) -#define CANCTRL_BOFFMSK (0x00008000) -#define CANCTRL_ERRMSK (0x00004000) -#define CANCTRL_CLKSRC (0x00002000) -#define CANCTRL_LPB (0x00001000) -#define CANCTRL_SMP (0x00000080) -#define CANCTRL_BOFFREC (0x00000040) -#define CANCTRL_TSYNC (0x00000020) -#define CANCTRL_LBUF (0x00000010) -#define CANCTRL_LOM (0x00000008) -#define CANCTRL_PROPSEG(x) (((x)&0x07)) +#define CANCTRL_PRESDIV(x) (((x)&0xFF)<<24) +#define CANCTRL_RJW(x) (((x)&0x03)<<22) +#define CANCTRL_PSEG1(x) (((x)&0x07)<<19) +#define CANCTRL_PSEG2(x) (((x)&0x07)<<16) +#define CANCTRL_BOFFMSK (0x00008000) +#define CANCTRL_ERRMSK (0x00004000) +#define CANCTRL_CLKSRC (0x00002000) +#define CANCTRL_LPB (0x00001000) +#define CANCTRL_SMP (0x00000080) +#define CANCTRL_BOFFREC (0x00000040) +#define CANCTRL_TSYNC (0x00000020) +#define CANCTRL_LBUF (0x00000010) +#define CANCTRL_LOM (0x00000008) +#define CANCTRL_PROPSEG(x) (((x)&0x07)) /* Bit definitions and macros for CAN_TIMER */ -#define TIMER_TIMER(x) ((x)&0xFFFF) +#define TIMER_TIMER(x) ((x)&0xFFFF) /* Bit definitions and macros for CAN_RXGMASK */ -#define RXGMASK_MI(x) ((x)&0x1FFFFFFF) +#define RXGMASK_MI(x) ((x)&0x1FFFFFFF) /* Bit definitions and macros for CAN_ERRCNT */ -#define ERRCNT_TXECTR(x) (((x)&0xFF)) -#define ERRCNT_RXECTR(x) (((x)&0xFF)<<8) +#define ERRCNT_TXECTR(x) (((x)&0xFF)) +#define ERRCNT_RXECTR(x) (((x)&0xFF)<<8) /* Bit definitions and macros for CAN_ERRSTAT */ -#define ERRSTAT_BITERR1 (0x00008000) -#define ERRSTAT_BITERR0 (0x00004000) -#define ERRSTAT_ACKERR (0x00002000) -#define ERRSTAT_CRCERR (0x00001000) -#define ERRSTAT_FRMERR (0x00000800) -#define ERRSTAT_STFERR (0x00000400) -#define ERRSTAT_TXWRN (0x00000200) -#define ERRSTAT_RXWRN (0x00000100) -#define ERRSTAT_IDLE (0x00000080) -#define ERRSTAT_TXRX (0x00000040) -#define ERRSTAT_FLT_BUSOFF (0x00000020) -#define ERRSTAT_FLT_PASSIVE (0x00000010) -#define ERRSTAT_FLT_ACTIVE (0x00000000) -#define ERRSTAT_BOFFINT (0x00000004) -#define ERRSTAT_ERRINT (0x00000002) -#define ERRSTAT_WAKINT (0x00000001) +#define ERRSTAT_BITERR1 (0x00008000) +#define ERRSTAT_BITERR0 (0x00004000) +#define ERRSTAT_ACKERR (0x00002000) +#define ERRSTAT_CRCERR (0x00001000) +#define ERRSTAT_FRMERR (0x00000800) +#define ERRSTAT_STFERR (0x00000400) +#define ERRSTAT_TXWRN (0x00000200) +#define ERRSTAT_RXWRN (0x00000100) +#define ERRSTAT_IDLE (0x00000080) +#define ERRSTAT_TXRX (0x00000040) +#define ERRSTAT_FLT_BUSOFF (0x00000020) +#define ERRSTAT_FLT_PASSIVE (0x00000010) +#define ERRSTAT_FLT_ACTIVE (0x00000000) +#define ERRSTAT_BOFFINT (0x00000004) +#define ERRSTAT_ERRINT (0x00000002) +#define ERRSTAT_WAKINT (0x00000001) /* Bit definitions and macros for CAN_IMASK */ -#define IMASK_BUF15M (0x00008000) -#define IMASK_BUF14M (0x00004000) -#define IMASK_BUF13M (0x00002000) -#define IMASK_BUF12M (0x00001000) -#define IMASK_BUF11M (0x00000800) -#define IMASK_BUF10M (0x00000400) -#define IMASK_BUF9M (0x00000200) -#define IMASK_BUF8M (0x00000100) -#define IMASK_BUF7M (0x00000080) -#define IMASK_BUF6M (0x00000040) -#define IMASK_BUF5M (0x00000020) -#define IMASK_BUF4M (0x00000010) -#define IMASK_BUF3M (0x00000008) -#define IMASK_BUF2M (0x00000004) -#define IMASK_BUF1M (0x00000002) -#define IMASK_BUF0M (0x00000001) +#define IMASK_BUF15M (0x00008000) +#define IMASK_BUF14M (0x00004000) +#define IMASK_BUF13M (0x00002000) +#define IMASK_BUF12M (0x00001000) +#define IMASK_BUF11M (0x00000800) +#define IMASK_BUF10M (0x00000400) +#define IMASK_BUF9M (0x00000200) +#define IMASK_BUF8M (0x00000100) +#define IMASK_BUF7M (0x00000080) +#define IMASK_BUF6M (0x00000040) +#define IMASK_BUF5M (0x00000020) +#define IMASK_BUF4M (0x00000010) +#define IMASK_BUF3M (0x00000008) +#define IMASK_BUF2M (0x00000004) +#define IMASK_BUF1M (0x00000002) +#define IMASK_BUF0M (0x00000001) /* Bit definitions and macros for CAN_IFLAG */ -#define IFLAG_BUF15I (0x00008000) -#define IFLAG_BUF14I (0x00004000) -#define IFLAG_BUF13I (0x00002000) -#define IFLAG_BUF12I (0x00001000) -#define IFLAG_BUF11I (0x00000800) -#define IFLAG_BUF10I (0x00000400) -#define IFLAG_BUF9I (0x00000200) -#define IFLAG_BUF8I (0x00000100) -#define IFLAG_BUF7I (0x00000080) -#define IFLAG_BUF6I (0x00000040) -#define IFLAG_BUF5I (0x00000020) -#define IFLAG_BUF4I (0x00000010) -#define IFLAG_BUF3I (0x00000008) -#define IFLAG_BUF2I (0x00000004) -#define IFLAG_BUF1I (0x00000002) -#define IFLAG_BUF0I (0x00000001) +#define IFLAG_BUF15I (0x00008000) +#define IFLAG_BUF14I (0x00004000) +#define IFLAG_BUF13I (0x00002000) +#define IFLAG_BUF12I (0x00001000) +#define IFLAG_BUF11I (0x00000800) +#define IFLAG_BUF10I (0x00000400) +#define IFLAG_BUF9I (0x00000200) +#define IFLAG_BUF8I (0x00000100) +#define IFLAG_BUF7I (0x00000080) +#define IFLAG_BUF6I (0x00000040) +#define IFLAG_BUF5I (0x00000020) +#define IFLAG_BUF4I (0x00000010) +#define IFLAG_BUF3I (0x00000008) +#define IFLAG_BUF2I (0x00000004) +#define IFLAG_BUF1I (0x00000002) +#define IFLAG_BUF0I (0x00000001) /********************************************************************* * Interrupt Controller (INTC) *********************************************************************/ -#define INTC0_EPORT INTC_IPRL_INT1 +#define INTC0_EPORT INTC_IPRL_INT1 -#define INT0_LO_RSVD0 (0) -#define INT0_LO_EPORT1 (1) -#define INT0_LO_EPORT2 (2) -#define INT0_LO_EPORT3 (3) -#define INT0_LO_EPORT4 (4) -#define INT0_LO_EPORT5 (5) -#define INT0_LO_EPORT6 (6) -#define INT0_LO_EPORT7 (7) -#define INT0_LO_EDMA_00 (8) -#define INT0_LO_EDMA_01 (9) -#define INT0_LO_EDMA_02 (10) -#define INT0_LO_EDMA_03 (11) -#define INT0_LO_EDMA_04 (12) -#define INT0_LO_EDMA_05 (13) -#define INT0_LO_EDMA_06 (14) -#define INT0_LO_EDMA_07 (15) -#define INT0_LO_EDMA_08 (16) -#define INT0_LO_EDMA_09 (17) -#define INT0_LO_EDMA_10 (18) -#define INT0_LO_EDMA_11 (19) -#define INT0_LO_EDMA_12 (20) -#define INT0_LO_EDMA_13 (21) -#define INT0_LO_EDMA_14 (22) -#define INT0_LO_EDMA_15 (23) -#define INT0_LO_EDMA_ERR (24) -#define INT0_LO_SCM (25) -#define INT0_LO_UART0 (26) -#define INT0_LO_UART1 (27) -#define INT0_LO_UART2 (28) -#define INT0_LO_RSVD1 (29) -#define INT0_LO_I2C (30) -#define INT0_LO_QSPI (31) -#define INT0_HI_DTMR0 (32) -#define INT0_HI_DTMR1 (33) -#define INT0_HI_DTMR2 (34) -#define INT0_HI_DTMR3 (35) -#define INT0_HI_FEC_TXF (36) -#define INT0_HI_FEC_TXB (37) -#define INT0_HI_FEC_UN (38) -#define INT0_HI_FEC_RL (39) -#define INT0_HI_FEC_RXF (40) -#define INT0_HI_FEC_RXB (41) -#define INT0_HI_FEC_MII (42) -#define INT0_HI_FEC_LC (43) -#define INT0_HI_FEC_HBERR (44) -#define INT0_HI_FEC_GRA (45) -#define INT0_HI_FEC_EBERR (46) -#define INT0_HI_FEC_BABT (47) -#define INT0_HI_FEC_BABR (48) +#define INT0_LO_RSVD0 (0) +#define INT0_LO_EPORT1 (1) +#define INT0_LO_EPORT2 (2) +#define INT0_LO_EPORT3 (3) +#define INT0_LO_EPORT4 (4) +#define INT0_LO_EPORT5 (5) +#define INT0_LO_EPORT6 (6) +#define INT0_LO_EPORT7 (7) +#define INT0_LO_EDMA_00 (8) +#define INT0_LO_EDMA_01 (9) +#define INT0_LO_EDMA_02 (10) +#define INT0_LO_EDMA_03 (11) +#define INT0_LO_EDMA_04 (12) +#define INT0_LO_EDMA_05 (13) +#define INT0_LO_EDMA_06 (14) +#define INT0_LO_EDMA_07 (15) +#define INT0_LO_EDMA_08 (16) +#define INT0_LO_EDMA_09 (17) +#define INT0_LO_EDMA_10 (18) +#define INT0_LO_EDMA_11 (19) +#define INT0_LO_EDMA_12 (20) +#define INT0_LO_EDMA_13 (21) +#define INT0_LO_EDMA_14 (22) +#define INT0_LO_EDMA_15 (23) +#define INT0_LO_EDMA_ERR (24) +#define INT0_LO_SCM (25) +#define INT0_LO_UART0 (26) +#define INT0_LO_UART1 (27) +#define INT0_LO_UART2 (28) +#define INT0_LO_RSVD1 (29) +#define INT0_LO_I2C (30) +#define INT0_LO_QSPI (31) +#define INT0_HI_DTMR0 (32) +#define INT0_HI_DTMR1 (33) +#define INT0_HI_DTMR2 (34) +#define INT0_HI_DTMR3 (35) +#define INT0_HI_FEC_TXF (36) +#define INT0_HI_FEC_TXB (37) +#define INT0_HI_FEC_UN (38) +#define INT0_HI_FEC_RL (39) +#define INT0_HI_FEC_RXF (40) +#define INT0_HI_FEC_RXB (41) +#define INT0_HI_FEC_MII (42) +#define INT0_HI_FEC_LC (43) +#define INT0_HI_FEC_HBERR (44) +#define INT0_HI_FEC_GRA (45) +#define INT0_HI_FEC_EBERR (46) +#define INT0_HI_FEC_BABT (47) +#define INT0_HI_FEC_BABR (48) /* 49 - 61 Reserved */ -#define INT0_HI_SCM (62) - -/*#define INT1_HI_ */ +#define INT0_HI_SCM (62) /* Bit definitions and macros for INTC_IPRH */ -#define INTC_IPRH_INT63 (0x80000000) -#define INTC_IPRH_INT62 (0x40000000) -#define INTC_IPRH_INT61 (0x20000000) -#define INTC_IPRH_INT60 (0x10000000) -#define INTC_IPRH_INT59 (0x08000000) -#define INTC_IPRH_INT58 (0x04000000) -#define INTC_IPRH_INT57 (0x02000000) -#define INTC_IPRH_INT56 (0x01000000) -#define INTC_IPRH_INT55 (0x00800000) -#define INTC_IPRH_INT54 (0x00400000) -#define INTC_IPRH_INT53 (0x00200000) -#define INTC_IPRH_INT52 (0x00100000) -#define INTC_IPRH_INT51 (0x00080000) -#define INTC_IPRH_INT50 (0x00040000) -#define INTC_IPRH_INT49 (0x00020000) -#define INTC_IPRH_INT48 (0x00010000) -#define INTC_IPRH_INT47 (0x00008000) -#define INTC_IPRH_INT46 (0x00004000) -#define INTC_IPRH_INT45 (0x00002000) -#define INTC_IPRH_INT44 (0x00001000) -#define INTC_IPRH_INT43 (0x00000800) -#define INTC_IPRH_INT42 (0x00000400) -#define INTC_IPRH_INT41 (0x00000200) -#define INTC_IPRH_INT40 (0x00000100) -#define INTC_IPRH_INT39 (0x00000080) -#define INTC_IPRH_INT38 (0x00000040) -#define INTC_IPRH_INT37 (0x00000020) -#define INTC_IPRH_INT36 (0x00000010) -#define INTC_IPRH_INT35 (0x00000008) -#define INTC_IPRH_INT34 (0x00000004) -#define INTC_IPRH_INT33 (0x00000002) -#define INTC_IPRH_INT32 (0x00000001) +#define INTC_IPRH_INT63 (0x80000000) +#define INTC_IPRH_INT62 (0x40000000) +#define INTC_IPRH_INT61 (0x20000000) +#define INTC_IPRH_INT60 (0x10000000) +#define INTC_IPRH_INT59 (0x08000000) +#define INTC_IPRH_INT58 (0x04000000) +#define INTC_IPRH_INT57 (0x02000000) +#define INTC_IPRH_INT56 (0x01000000) +#define INTC_IPRH_INT55 (0x00800000) +#define INTC_IPRH_INT54 (0x00400000) +#define INTC_IPRH_INT53 (0x00200000) +#define INTC_IPRH_INT52 (0x00100000) +#define INTC_IPRH_INT51 (0x00080000) +#define INTC_IPRH_INT50 (0x00040000) +#define INTC_IPRH_INT49 (0x00020000) +#define INTC_IPRH_INT48 (0x00010000) +#define INTC_IPRH_INT47 (0x00008000) +#define INTC_IPRH_INT46 (0x00004000) +#define INTC_IPRH_INT45 (0x00002000) +#define INTC_IPRH_INT44 (0x00001000) +#define INTC_IPRH_INT43 (0x00000800) +#define INTC_IPRH_INT42 (0x00000400) +#define INTC_IPRH_INT41 (0x00000200) +#define INTC_IPRH_INT40 (0x00000100) +#define INTC_IPRH_INT39 (0x00000080) +#define INTC_IPRH_INT38 (0x00000040) +#define INTC_IPRH_INT37 (0x00000020) +#define INTC_IPRH_INT36 (0x00000010) +#define INTC_IPRH_INT35 (0x00000008) +#define INTC_IPRH_INT34 (0x00000004) +#define INTC_IPRH_INT33 (0x00000002) +#define INTC_IPRH_INT32 (0x00000001) /* Bit definitions and macros for INTC_IPRL */ -#define INTC_IPRL_INT31 (0x80000000) -#define INTC_IPRL_INT30 (0x40000000) -#define INTC_IPRL_INT29 (0x20000000) -#define INTC_IPRL_INT28 (0x10000000) -#define INTC_IPRL_INT27 (0x08000000) -#define INTC_IPRL_INT26 (0x04000000) -#define INTC_IPRL_INT25 (0x02000000) -#define INTC_IPRL_INT24 (0x01000000) -#define INTC_IPRL_INT23 (0x00800000) -#define INTC_IPRL_INT22 (0x00400000) -#define INTC_IPRL_INT21 (0x00200000) -#define INTC_IPRL_INT20 (0x00100000) -#define INTC_IPRL_INT19 (0x00080000) -#define INTC_IPRL_INT18 (0x00040000) -#define INTC_IPRL_INT17 (0x00020000) -#define INTC_IPRL_INT16 (0x00010000) -#define INTC_IPRL_INT15 (0x00008000) -#define INTC_IPRL_INT14 (0x00004000) -#define INTC_IPRL_INT13 (0x00002000) -#define INTC_IPRL_INT12 (0x00001000) -#define INTC_IPRL_INT11 (0x00000800) -#define INTC_IPRL_INT10 (0x00000400) -#define INTC_IPRL_INT9 (0x00000200) -#define INTC_IPRL_INT8 (0x00000100) -#define INTC_IPRL_INT7 (0x00000080) -#define INTC_IPRL_INT6 (0x00000040) -#define INTC_IPRL_INT5 (0x00000020) -#define INTC_IPRL_INT4 (0x00000010) -#define INTC_IPRL_INT3 (0x00000008) -#define INTC_IPRL_INT2 (0x00000004) -#define INTC_IPRL_INT1 (0x00000002) -#define INTC_IPRL_INT0 (0x00000001) +#define INTC_IPRL_INT31 (0x80000000) +#define INTC_IPRL_INT30 (0x40000000) +#define INTC_IPRL_INT29 (0x20000000) +#define INTC_IPRL_INT28 (0x10000000) +#define INTC_IPRL_INT27 (0x08000000) +#define INTC_IPRL_INT26 (0x04000000) +#define INTC_IPRL_INT25 (0x02000000) +#define INTC_IPRL_INT24 (0x01000000) +#define INTC_IPRL_INT23 (0x00800000) +#define INTC_IPRL_INT22 (0x00400000) +#define INTC_IPRL_INT21 (0x00200000) +#define INTC_IPRL_INT20 (0x00100000) +#define INTC_IPRL_INT19 (0x00080000) +#define INTC_IPRL_INT18 (0x00040000) +#define INTC_IPRL_INT17 (0x00020000) +#define INTC_IPRL_INT16 (0x00010000) +#define INTC_IPRL_INT15 (0x00008000) +#define INTC_IPRL_INT14 (0x00004000) +#define INTC_IPRL_INT13 (0x00002000) +#define INTC_IPRL_INT12 (0x00001000) +#define INTC_IPRL_INT11 (0x00000800) +#define INTC_IPRL_INT10 (0x00000400) +#define INTC_IPRL_INT9 (0x00000200) +#define INTC_IPRL_INT8 (0x00000100) +#define INTC_IPRL_INT7 (0x00000080) +#define INTC_IPRL_INT6 (0x00000040) +#define INTC_IPRL_INT5 (0x00000020) +#define INTC_IPRL_INT4 (0x00000010) +#define INTC_IPRL_INT3 (0x00000008) +#define INTC_IPRL_INT2 (0x00000004) +#define INTC_IPRL_INT1 (0x00000002) +#define INTC_IPRL_INT0 (0x00000001) /* Bit definitions and macros for INTC_ICONFIG */ -#define INTC_ICFG_ELVLPRI7 (0x8000) -#define INTC_ICFG_ELVLPRI6 (0x4000) -#define INTC_ICFG_ELVLPRI5 (0x2000) -#define INTC_ICFG_ELVLPRI4 (0x1000) -#define INTC_ICFG_ELVLPRI3 (0x0800) -#define INTC_ICFG_ELVLPRI2 (0x0400) -#define INTC_ICFG_ELVLPRI1 (0x0200) -#define INTC_ICFG_EMASK (0x0020) +#define INTC_ICFG_ELVLPRI7 (0x8000) +#define INTC_ICFG_ELVLPRI6 (0x4000) +#define INTC_ICFG_ELVLPRI5 (0x2000) +#define INTC_ICFG_ELVLPRI4 (0x1000) +#define INTC_ICFG_ELVLPRI3 (0x0800) +#define INTC_ICFG_ELVLPRI2 (0x0400) +#define INTC_ICFG_ELVLPRI1 (0x0200) +#define INTC_ICFG_EMASK (0x0020) /* Bit definitions and macros for INTC_SIMR */ -#define INTC_SIMR_SALL (0x40) -#define INTC_SIMR_SIMR(x) ((x)&0x3F) +#define INTC_SIMR_SALL (0x40) +#define INTC_SIMR_SIMR(x) ((x)&0x3F) /* Bit definitions and macros for INTC_CIMR */ -#define INTC_CIMR_CALL (0x40) -#define INTC_CIMR_CIMR(x) ((x)&0x3F) +#define INTC_CIMR_CALL (0x40) +#define INTC_CIMR_CIMR(x) ((x)&0x3F) /* Bit definitions and macros for INTC_CLMASK */ -#define INTC_CLMASK_CLMASK(x) ((x)&0x0F) +#define INTC_CLMASK_CLMASK(x) ((x)&0x0F) /* Bit definitions and macros for INTC_SLMASK */ -#define INTC_SLMASK_SLMASK(x) ((x)&0x0F) +#define INTC_SLMASK_SLMASK(x) ((x)&0x0F) /* Bit definitions and macros for INTC_ICR */ -#define INTC_ICR_IL(x) ((x)&0x07) - -/********************************************************************* -* I2C Module (I2C) -*********************************************************************/ -/* Bit definitions and macros for I2C_AR */ -#define I2C_AR_ADR(x) (((x)&0x7F)<<1) - -/* Bit definitions and macros for I2C_FDR */ -#define I2C_FDR_IC(x) ((x)&0x3F) - -/* Bit definitions and macros for I2C_CR */ -#define I2C_CR_IEN (0x80) -#define I2C_CR_IIEN (0x40) -#define I2C_CR_MSTA (0x20) -#define I2C_CR_MTX (0x10) -#define I2C_CR_TXAK (0x08) -#define I2C_CR_RSTA (0x04) - -/* Bit definitions and macros for I2C_SR */ -#define I2C_SR_ICF (0x80) -#define I2C_SR_IAAS (0x40) -#define I2C_SR_IBB (0x20) -#define I2C_SR_IAL (0x10) -#define I2C_SR_SRW (0x04) -#define I2C_SR_IIF (0x02) -#define I2C_SR_RXAK (0x01) - -/* Bit definitions and macros for I2C_ICR */ -#define I2C_ICR_BNBE (0x08) -#define I2C_ICR_TE (0x04) -#define I2C_ICR_RE (0x02) -#define I2C_ICR_IE (0x01) +#define INTC_ICR_IL(x) ((x)&0x07) /********************************************************************* * Queued Serial Peripheral Interface (QSPI) *********************************************************************/ /* Bit definitions and macros for QSPI_QMR */ -#define QSPI_QMR_MSTR (0x8000) -#define QSPI_QMR_DOHIE (0x4000) -#define QSPI_QMR_BITS(x) (((x)&0x000F)<<10) -#define QSPI_QMR_CPOL (0x0200) -#define QSPI_QMR_CPHA (0x0100) -#define QSPI_QMR_BAUD(x) ((x)&0x00FF) +#define QSPI_QMR_MSTR (0x8000) +#define QSPI_QMR_DOHIE (0x4000) +#define QSPI_QMR_BITS(x) (((x)&0x000F)<<10) +#define QSPI_QMR_CPOL (0x0200) +#define QSPI_QMR_CPHA (0x0100) +#define QSPI_QMR_BAUD(x) ((x)&0x00FF) /* Bit definitions and macros for QSPI_QDLYR */ -#define QSPI_QDLYR_SPE (0x8000) -#define QSPI_QDLYR_QCD(x) (((x)&0x007F)<<8) -#define QSPI_QDLYR_DTL(x) ((x)&0x00FF) +#define QSPI_QDLYR_SPE (0x8000) +#define QSPI_QDLYR_QCD(x) (((x)&0x007F)<<8) +#define QSPI_QDLYR_DTL(x) ((x)&0x00FF) /* Bit definitions and macros for QSPI_QWR */ -#define QSPI_QWR_NEWQP(x) ((x)&0x000F) -#define QSPI_QWR_ENDQP(x) (((x)&0x000F)<<8) -#define QSPI_QWR_CSIV (0x1000) -#define QSPI_QWR_WRTO (0x2000) -#define QSPI_QWR_WREN (0x4000) -#define QSPI_QWR_HALT (0x8000) +#define QSPI_QWR_NEWQP(x) ((x)&0x000F) +#define QSPI_QWR_ENDQP(x) (((x)&0x000F)<<8) +#define QSPI_QWR_CSIV (0x1000) +#define QSPI_QWR_WRTO (0x2000) +#define QSPI_QWR_WREN (0x4000) +#define QSPI_QWR_HALT (0x8000) /* Bit definitions and macros for QSPI_QIR */ -#define QSPI_QIR_WCEFB (0x8000) -#define QSPI_QIR_ABRTB (0x4000) -#define QSPI_QIR_ABRTL (0x1000) -#define QSPI_QIR_WCEFE (0x0800) -#define QSPI_QIR_ABRTE (0x0400) -#define QSPI_QIR_SPIFE (0x0100) -#define QSPI_QIR_WCEF (0x0008) -#define QSPI_QIR_ABRT (0x0004) -#define QSPI_QIR_SPIF (0x0001) +#define QSPI_QIR_WCEFB (0x8000) +#define QSPI_QIR_ABRTB (0x4000) +#define QSPI_QIR_ABRTL (0x1000) +#define QSPI_QIR_WCEFE (0x0800) +#define QSPI_QIR_ABRTE (0x0400) +#define QSPI_QIR_SPIFE (0x0100) +#define QSPI_QIR_WCEF (0x0008) +#define QSPI_QIR_ABRT (0x0004) +#define QSPI_QIR_SPIF (0x0001) /* Bit definitions and macros for QSPI_QAR */ -#define QSPI_QAR_ADDR(x) ((x)&0x003F) -#define QSPI_QAR_TRANS (0x0000) -#define QSPI_QAR_RECV (0x0010) -#define QSPI_QAR_CMD (0x0020) +#define QSPI_QAR_ADDR(x) ((x)&0x003F) +#define QSPI_QAR_TRANS (0x0000) +#define QSPI_QAR_RECV (0x0010) +#define QSPI_QAR_CMD (0x0020) /* Bit definitions and macros for QSPI_QDR */ -#define QSPI_QDR_CONT (0x8000) -#define QSPI_QDR_BITSE (0x4000) -#define QSPI_QDR_DT (0x2000) -#define QSPI_QDR_DSCK (0x1000) -#define QSPI_QDR_QSPI_CS3 (0x0800) -#define QSPI_QDR_QSPI_CS2 (0x0400) -#define QSPI_QDR_QSPI_CS1 (0x0200) -#define QSPI_QDR_QSPI_CS0 (0x0100) +#define QSPI_QDR_CONT (0x8000) +#define QSPI_QDR_BITSE (0x4000) +#define QSPI_QDR_DT (0x2000) +#define QSPI_QDR_DSCK (0x1000) +#define QSPI_QDR_QSPI_CS3 (0x0800) +#define QSPI_QDR_QSPI_CS2 (0x0400) +#define QSPI_QDR_QSPI_CS1 (0x0200) +#define QSPI_QDR_QSPI_CS0 (0x0100) /********************************************************************* * Pulse Width Modulation (PWM) *********************************************************************/ /* Bit definitions and macros for PWM_E */ -#define PWM_EN_PWME7 (0x80) -#define PWM_EN_PWME5 (0x20) -#define PWM_EN_PWME3 (0x08) -#define PWM_EN_PWME1 (0x02) +#define PWM_EN_PWME7 (0x80) +#define PWM_EN_PWME5 (0x20) +#define PWM_EN_PWME3 (0x08) +#define PWM_EN_PWME1 (0x02) /* Bit definitions and macros for PWM_POL */ -#define PWM_POL_PPOL7 (0x80) -#define PWM_POL_PPOL5 (0x20) -#define PWM_POL_PPOL3 (0x08) -#define PWM_POL_PPOL1 (0x02) +#define PWM_POL_PPOL7 (0x80) +#define PWM_POL_PPOL5 (0x20) +#define PWM_POL_PPOL3 (0x08) +#define PWM_POL_PPOL1 (0x02) /* Bit definitions and macros for PWM_CLK */ -#define PWM_CLK_PCLK7 (0x80) -#define PWM_CLK_PCLK5 (0x20) -#define PWM_CLK_PCLK3 (0x08) -#define PWM_CLK_PCLK1 (0x02) +#define PWM_CLK_PCLK7 (0x80) +#define PWM_CLK_PCLK5 (0x20) +#define PWM_CLK_PCLK3 (0x08) +#define PWM_CLK_PCLK1 (0x02) /* Bit definitions and macros for PWM_PRCLK */ -#define PWM_PRCLK_PCKB(x) (((x)&0x07)<<4) -#define PWM_PRCLK_PCKA(x) ((x)&0x07) +#define PWM_PRCLK_PCKB(x) (((x)&0x07)<<4) +#define PWM_PRCLK_PCKA(x) ((x)&0x07) /* Bit definitions and macros for PWM_CAE */ -#define PWM_CAE_CAE7 (0x80) -#define PWM_CAE_CAE5 (0x20) -#define PWM_CAE_CAE3 (0x08) -#define PWM_CAE_CAE1 (0x02) +#define PWM_CAE_CAE7 (0x80) +#define PWM_CAE_CAE5 (0x20) +#define PWM_CAE_CAE3 (0x08) +#define PWM_CAE_CAE1 (0x02) /* Bit definitions and macros for PWM_CTL */ -#define PWM_CTL_CON67 (0x80) -#define PWM_CTL_CON45 (0x40) -#define PWM_CTL_CON23 (0x20) -#define PWM_CTL_CON01 (0x10) -#define PWM_CTL_PSWAR (0x08) -#define PWM_CTL_PFRZ (0x04) +#define PWM_CTL_CON67 (0x80) +#define PWM_CTL_CON45 (0x40) +#define PWM_CTL_CON23 (0x20) +#define PWM_CTL_CON01 (0x10) +#define PWM_CTL_PSWAR (0x08) +#define PWM_CTL_PFRZ (0x04) /* Bit definitions and macros for PWM_SDN */ -#define PWM_SDN_IF (0x80) -#define PWM_SDN_IE (0x40) -#define PWM_SDN_RESTART (0x20) -#define PWM_SDN_LVL (0x10) -#define PWM_SDN_PWM7IN (0x04) -#define PWM_SDN_PWM7IL (0x02) -#define PWM_SDN_SDNEN (0x01) +#define PWM_SDN_IF (0x80) +#define PWM_SDN_IE (0x40) +#define PWM_SDN_RESTART (0x20) +#define PWM_SDN_LVL (0x10) +#define PWM_SDN_PWM7IN (0x04) +#define PWM_SDN_PWM7IL (0x02) +#define PWM_SDN_SDNEN (0x01) /********************************************************************* * Watchdog Timer Modules (WTM) *********************************************************************/ /* Bit definitions and macros for WTM_WCR */ -#define WTM_WCR_WAIT (0x0008) -#define WTM_WCR_DOZE (0x0004) -#define WTM_WCR_HALTED (0x0002) -#define WTM_WCR_EN (0x0001) +#define WTM_WCR_WAIT (0x0008) +#define WTM_WCR_DOZE (0x0004) +#define WTM_WCR_HALTED (0x0002) +#define WTM_WCR_EN (0x0001) /********************************************************************* * Chip Configuration Module (CCM) *********************************************************************/ /* Bit definitions and macros for CCM_CCR */ -#define CCM_CCR_CSC(x) (((x)&0x0003)<<8|0x0001) -#define CCM_CCR_LIMP (0x0041) -#define CCM_CCR_LOAD (0x0021) -#define CCM_CCR_BOOTPS(x) (((x)&0x0003)<<3|0x0001) -#define CCM_CCR_OSC_MODE (0x0005) -#define CCM_CCR_PLL_MODE (0x0003) -#define CCM_CCR_RESERVED (0x0001) +#define CCM_CCR_CSC(x) (((x)&0x0003)<<8|0x0001) +#define CCM_CCR_LIMP (0x0041) +#define CCM_CCR_LOAD (0x0021) +#define CCM_CCR_BOOTPS(x) (((x)&0x0003)<<3|0x0001) +#define CCM_CCR_OSC_MODE (0x0005) +#define CCM_CCR_PLL_MODE (0x0003) +#define CCM_CCR_RESERVED (0x0001) /* Bit definitions and macros for CCM_RCON */ -#define CCM_RCON_CSC(x) (((x)&0x0003)<<8|0x0001) -#define CCM_RCON_LIMP (0x0041) -#define CCM_RCON_LOAD (0x0021) -#define CCM_RCON_BOOTPS(x) (((x)&0x0003)<<3|0x0001) -#define CCM_RCON_OSC_MODE (0x0005) -#define CCM_RCON_PLL_MODE (0x0003) -#define CCM_RCON_RESERVED (0x0001) +#define CCM_RCON_CSC(x) (((x)&0x0003)<<8|0x0001) +#define CCM_RCON_LIMP (0x0041) +#define CCM_RCON_LOAD (0x0021) +#define CCM_RCON_BOOTPS(x) (((x)&0x0003)<<3|0x0001) +#define CCM_RCON_OSC_MODE (0x0005) +#define CCM_RCON_PLL_MODE (0x0003) +#define CCM_RCON_RESERVED (0x0001) /* Bit definitions and macros for CCM_CIR */ -#define CCM_CIR_PIN(x) (((x)&0x03FF)<<6) -#define CCM_CIR_PRN(x) ((x)&0x003F) +#define CCM_CIR_PIN(x) (((x)&0x03FF)<<6) +#define CCM_CIR_PRN(x) ((x)&0x003F) /* Bit definitions and macros for CCM_MISCCR */ -#define CCM_MISCCR_PLL_LOCK (0x2000) -#define CCM_MISCCR_LIMP (0x1000) -#define CCM_MISCCR_LCD_CHEN (0x0100) -#define CCM_MISCCR_SSI_PUE (0x0080) -#define CCM_MISCCR_SSI_PUS (0x0040) -#define CCM_MISCCR_TIM_DMA (0x0020) -#define CCM_MISCCR_SSI_SRC (0x0010) -#define CCM_MISCCR_USBDIV (0x0002) -#define CCM_MISCCR_USBSRC (0x0001) +#define CCM_MISCCR_PLL_LOCK (0x2000) +#define CCM_MISCCR_LIMP (0x1000) +#define CCM_MISCCR_LCD_CHEN (0x0100) +#define CCM_MISCCR_SSI_PUE (0x0080) +#define CCM_MISCCR_SSI_PUS (0x0040) +#define CCM_MISCCR_TIM_DMA (0x0020) +#define CCM_MISCCR_SSI_SRC (0x0010) +#define CCM_MISCCR_USBDIV (0x0002) +#define CCM_MISCCR_USBSRC (0x0001) /* Bit definitions and macros for CCM_CDR */ -#define CCM_CDR_LPDIV(x) (((x)&0x000F)<<8) -#define CCM_CDR_SSIDIV(x) ((x)&0x000F) +#define CCM_CDR_LPDIV(x) (((x)&0x000F)<<8) +#define CCM_CDR_SSIDIV(x) ((x)&0x000F) /* Bit definitions and macros for CCM_UHCSR */ -#define CCM_UHCSR_PORTIND(x) (((x)&0x0003)<<14) -#define CCM_UHCSR_WKUP (0x0004) -#define CCM_UHCSR_UHMIE (0x0002) -#define CCM_UHCSR_XPDE (0x0001) +#define CCM_UHCSR_PORTIND(x) (((x)&0x0003)<<14) +#define CCM_UHCSR_WKUP (0x0004) +#define CCM_UHCSR_UHMIE (0x0002) +#define CCM_UHCSR_XPDE (0x0001) /* Bit definitions and macros for CCM_UOCSR */ -#define CCM_UOCSR_PORTIND(x) (((x)&0x0003)<<14) -#define CCM_UOCSR_DPPD (0x2000) -#define CCM_UOCSR_DMPD (0x1000) -#define CCM_UOCSR_DRV_VBUS (0x0800) -#define CCM_UOCSR_CRG_VBUS (0x0400) -#define CCM_UOCSR_DCR_VBUS (0x0200) -#define CCM_UOCSR_DPPU (0x0100) -#define CCM_UOCSR_AVLD (0x0080) -#define CCM_UOCSR_BVLD (0x0040) -#define CCM_UOCSR_VVLD (0x0020) -#define CCM_UOCSR_SEND (0x0010) -#define CCM_UOCSR_PWRFLT (0x0008) -#define CCM_UOCSR_WKUP (0x0004) -#define CCM_UOCSR_UOMIE (0x0002) -#define CCM_UOCSR_XPDE (0x0001) +#define CCM_UOCSR_PORTIND(x) (((x)&0x0003)<<14) +#define CCM_UOCSR_DPPD (0x2000) +#define CCM_UOCSR_DMPD (0x1000) +#define CCM_UOCSR_DRV_VBUS (0x0800) +#define CCM_UOCSR_CRG_VBUS (0x0400) +#define CCM_UOCSR_DCR_VBUS (0x0200) +#define CCM_UOCSR_DPPU (0x0100) +#define CCM_UOCSR_AVLD (0x0080) +#define CCM_UOCSR_BVLD (0x0040) +#define CCM_UOCSR_VVLD (0x0020) +#define CCM_UOCSR_SEND (0x0010) +#define CCM_UOCSR_PWRFLT (0x0008) +#define CCM_UOCSR_WKUP (0x0004) +#define CCM_UOCSR_UOMIE (0x0002) +#define CCM_UOCSR_XPDE (0x0001) /* not done yet */ /********************************************************************* * General Purpose I/O (GPIO) *********************************************************************/ /* Bit definitions and macros for GPIO_PODR_FECH_L */ -#define GPIO_PODR_FECH_L7 (0x80) -#define GPIO_PODR_FECH_L6 (0x40) -#define GPIO_PODR_FECH_L5 (0x20) -#define GPIO_PODR_FECH_L4 (0x10) -#define GPIO_PODR_FECH_L3 (0x08) -#define GPIO_PODR_FECH_L2 (0x04) -#define GPIO_PODR_FECH_L1 (0x02) -#define GPIO_PODR_FECH_L0 (0x01) +#define GPIO_PODR_FECH_L7 (0x80) +#define GPIO_PODR_FECH_L6 (0x40) +#define GPIO_PODR_FECH_L5 (0x20) +#define GPIO_PODR_FECH_L4 (0x10) +#define GPIO_PODR_FECH_L3 (0x08) +#define GPIO_PODR_FECH_L2 (0x04) +#define GPIO_PODR_FECH_L1 (0x02) +#define GPIO_PODR_FECH_L0 (0x01) /* Bit definitions and macros for GPIO_PODR_SSI */ -#define GPIO_PODR_SSI_4 (0x10) -#define GPIO_PODR_SSI_3 (0x08) -#define GPIO_PODR_SSI_2 (0x04) -#define GPIO_PODR_SSI_1 (0x02) -#define GPIO_PODR_SSI_0 (0x01) +#define GPIO_PODR_SSI_4 (0x10) +#define GPIO_PODR_SSI_3 (0x08) +#define GPIO_PODR_SSI_2 (0x04) +#define GPIO_PODR_SSI_1 (0x02) +#define GPIO_PODR_SSI_0 (0x01) /* Bit definitions and macros for GPIO_PODR_BUSCTL */ -#define GPIO_PODR_BUSCTL_3 (0x08) -#define GPIO_PODR_BUSCTL_2 (0x04) -#define GPIO_PODR_BUSCTL_1 (0x02) -#define GPIO_PODR_BUSCTL_0 (0x01) +#define GPIO_PODR_BUSCTL_3 (0x08) +#define GPIO_PODR_BUSCTL_2 (0x04) +#define GPIO_PODR_BUSCTL_1 (0x02) +#define GPIO_PODR_BUSCTL_0 (0x01) /* Bit definitions and macros for GPIO_PODR_BE */ -#define GPIO_PODR_BE_3 (0x08) -#define GPIO_PODR_BE_2 (0x04) -#define GPIO_PODR_BE_1 (0x02) -#define GPIO_PODR_BE_0 (0x01) +#define GPIO_PODR_BE_3 (0x08) +#define GPIO_PODR_BE_2 (0x04) +#define GPIO_PODR_BE_1 (0x02) +#define GPIO_PODR_BE_0 (0x01) /* Bit definitions and macros for GPIO_PODR_CS */ -#define GPIO_PODR_CS_5 (0x20) -#define GPIO_PODR_CS_4 (0x10) -#define GPIO_PODR_CS_3 (0x08) -#define GPIO_PODR_CS_2 (0x04) -#define GPIO_PODR_CS_1 (0x02) +#define GPIO_PODR_CS_5 (0x20) +#define GPIO_PODR_CS_4 (0x10) +#define GPIO_PODR_CS_3 (0x08) +#define GPIO_PODR_CS_2 (0x04) +#define GPIO_PODR_CS_1 (0x02) /* Bit definitions and macros for GPIO_PODR_PWM */ -#define GPIO_PODR_PWM_5 (0x20) -#define GPIO_PODR_PWM_4 (0x10) -#define GPIO_PODR_PWM_3 (0x08) -#define GPIO_PODR_PWM_2 (0x04) +#define GPIO_PODR_PWM_5 (0x20) +#define GPIO_PODR_PWM_4 (0x10) +#define GPIO_PODR_PWM_3 (0x08) +#define GPIO_PODR_PWM_2 (0x04) /* Bit definitions and macros for GPIO_PODR_FECI2C */ -#define GPIO_PODR_FECI2C_3 (0x08) -#define GPIO_PODR_FECI2C_2 (0x04) -#define GPIO_PODR_FECI2C_1 (0x02) -#define GPIO_PODR_FECI2C_0 (0x01) +#define GPIO_PODR_FECI2C_3 (0x08) +#define GPIO_PODR_FECI2C_2 (0x04) +#define GPIO_PODR_FECI2C_1 (0x02) +#define GPIO_PODR_FECI2C_0 (0x01) /* Bit definitions and macros for GPIO_PODR_UART */ -#define GPIO_PODR_UART_7 (0x80) -#define GPIO_PODR_UART_6 (0x40) -#define GPIO_PODR_UART_5 (0x20) -#define GPIO_PODR_UART_4 (0x10) -#define GPIO_PODR_UART_3 (0x08) -#define GPIO_PODR_UART_2 (0x04) -#define GPIO_PODR_UART_1 (0x02) -#define GPIO_PODR_UART_0 (0x01) +#define GPIO_PODR_UART_7 (0x80) +#define GPIO_PODR_UART_6 (0x40) +#define GPIO_PODR_UART_5 (0x20) +#define GPIO_PODR_UART_4 (0x10) +#define GPIO_PODR_UART_3 (0x08) +#define GPIO_PODR_UART_2 (0x04) +#define GPIO_PODR_UART_1 (0x02) +#define GPIO_PODR_UART_0 (0x01) /* Bit definitions and macros for GPIO_PODR_QSPI */ -#define GPIO_PODR_QSPI_5 (0x20) -#define GPIO_PODR_QSPI_4 (0x10) -#define GPIO_PODR_QSPI_3 (0x08) -#define GPIO_PODR_QSPI_2 (0x04) -#define GPIO_PODR_QSPI_1 (0x02) -#define GPIO_PODR_QSPI_0 (0x01) +#define GPIO_PODR_QSPI_5 (0x20) +#define GPIO_PODR_QSPI_4 (0x10) +#define GPIO_PODR_QSPI_3 (0x08) +#define GPIO_PODR_QSPI_2 (0x04) +#define GPIO_PODR_QSPI_1 (0x02) +#define GPIO_PODR_QSPI_0 (0x01) /* Bit definitions and macros for GPIO_PODR_TIMER */ -#define GPIO_PODR_TIMER_3 (0x08) -#define GPIO_PODR_TIMER_2 (0x04) -#define GPIO_PODR_TIMER_1 (0x02) -#define GPIO_PODR_TIMER_0 (0x01) +#define GPIO_PODR_TIMER_3 (0x08) +#define GPIO_PODR_TIMER_2 (0x04) +#define GPIO_PODR_TIMER_1 (0x02) +#define GPIO_PODR_TIMER_0 (0x01) /* Bit definitions and macros for GPIO_PODR_LCDDATAH */ -#define GPIO_PODR_LCDDATAH_1 (0x02) -#define GPIO_PODR_LCDDATAH_0 (0x01) +#define GPIO_PODR_LCDDATAH_1 (0x02) +#define GPIO_PODR_LCDDATAH_0 (0x01) /* Bit definitions and macros for GPIO_PODR_LCDDATAM */ -#define GPIO_PODR_LCDDATAM_7 (0x80) -#define GPIO_PODR_LCDDATAM_6 (0x40) -#define GPIO_PODR_LCDDATAM_5 (0x20) -#define GPIO_PODR_LCDDATAM_4 (0x10) -#define GPIO_PODR_LCDDATAM_3 (0x08) -#define GPIO_PODR_LCDDATAM_2 (0x04) -#define GPIO_PODR_LCDDATAM_1 (0x02) -#define GPIO_PODR_LCDDATAM_0 (0x01) +#define GPIO_PODR_LCDDATAM_7 (0x80) +#define GPIO_PODR_LCDDATAM_6 (0x40) +#define GPIO_PODR_LCDDATAM_5 (0x20) +#define GPIO_PODR_LCDDATAM_4 (0x10) +#define GPIO_PODR_LCDDATAM_3 (0x08) +#define GPIO_PODR_LCDDATAM_2 (0x04) +#define GPIO_PODR_LCDDATAM_1 (0x02) +#define GPIO_PODR_LCDDATAM_0 (0x01) /* Bit definitions and macros for GPIO_PODR_LCDDATAL */ -#define GPIO_PODR_LCDDATAL_7 (0x80) -#define GPIO_PODR_LCDDATAL_6 (0x40) -#define GPIO_PODR_LCDDATAL_5 (0x20) -#define GPIO_PODR_LCDDATAL_4 (0x10) -#define GPIO_PODR_LCDDATAL_3 (0x08) -#define GPIO_PODR_LCDDATAL_2 (0x04) -#define GPIO_PODR_LCDDATAL_1 (0x02) -#define GPIO_PODR_LCDDATAL_0 (0x01) +#define GPIO_PODR_LCDDATAL_7 (0x80) +#define GPIO_PODR_LCDDATAL_6 (0x40) +#define GPIO_PODR_LCDDATAL_5 (0x20) +#define GPIO_PODR_LCDDATAL_4 (0x10) +#define GPIO_PODR_LCDDATAL_3 (0x08) +#define GPIO_PODR_LCDDATAL_2 (0x04) +#define GPIO_PODR_LCDDATAL_1 (0x02) +#define GPIO_PODR_LCDDATAL_0 (0x01) /* Bit definitions and macros for GPIO_PODR_LCDCTLH */ -#define GPIO_PODR_LCDCTLH_0 (0x01) +#define GPIO_PODR_LCDCTLH_0 (0x01) /* Bit definitions and macros for GPIO_PODR_LCDCTLL */ -#define GPIO_PODR_LCDCTLL_7 (0x80) -#define GPIO_PODR_LCDCTLL_6 (0x40) -#define GPIO_PODR_LCDCTLL_5 (0x20) -#define GPIO_PODR_LCDCTLL_4 (0x10) -#define GPIO_PODR_LCDCTLL_3 (0x08) -#define GPIO_PODR_LCDCTLL_2 (0x04) -#define GPIO_PODR_LCDCTLL_1 (0x02) -#define GPIO_PODR_LCDCTLL_0 (0x01) +#define GPIO_PODR_LCDCTLL_7 (0x80) +#define GPIO_PODR_LCDCTLL_6 (0x40) +#define GPIO_PODR_LCDCTLL_5 (0x20) +#define GPIO_PODR_LCDCTLL_4 (0x10) +#define GPIO_PODR_LCDCTLL_3 (0x08) +#define GPIO_PODR_LCDCTLL_2 (0x04) +#define GPIO_PODR_LCDCTLL_1 (0x02) +#define GPIO_PODR_LCDCTLL_0 (0x01) /* Bit definitions and macros for GPIO_PDDR_FECH */ -#define GPIO_PDDR_FECH_L7 (0x80) -#define GPIO_PDDR_FECH_L6 (0x40) -#define GPIO_PDDR_FECH_L5 (0x20) -#define GPIO_PDDR_FECH_L4 (0x10) -#define GPIO_PDDR_FECH_L3 (0x08) -#define GPIO_PDDR_FECH_L2 (0x04) -#define GPIO_PDDR_FECH_L1 (0x02) -#define GPIO_PDDR_FECH_L0 (0x01) +#define GPIO_PDDR_FECH_L7 (0x80) +#define GPIO_PDDR_FECH_L6 (0x40) +#define GPIO_PDDR_FECH_L5 (0x20) +#define GPIO_PDDR_FECH_L4 (0x10) +#define GPIO_PDDR_FECH_L3 (0x08) +#define GPIO_PDDR_FECH_L2 (0x04) +#define GPIO_PDDR_FECH_L1 (0x02) +#define GPIO_PDDR_FECH_L0 (0x01) /* Bit definitions and macros for GPIO_PDDR_SSI */ -#define GPIO_PDDR_SSI_4 (0x10) -#define GPIO_PDDR_SSI_3 (0x08) -#define GPIO_PDDR_SSI_2 (0x04) -#define GPIO_PDDR_SSI_1 (0x02) -#define GPIO_PDDR_SSI_0 (0x01) +#define GPIO_PDDR_SSI_4 (0x10) +#define GPIO_PDDR_SSI_3 (0x08) +#define GPIO_PDDR_SSI_2 (0x04) +#define GPIO_PDDR_SSI_1 (0x02) +#define GPIO_PDDR_SSI_0 (0x01) /* Bit definitions and macros for GPIO_PDDR_BUSCTL */ -#define GPIO_PDDR_BUSCTL_3 (0x08) -#define GPIO_PDDR_BUSCTL_2 (0x04) -#define GPIO_PDDR_BUSCTL_1 (0x02) -#define GPIO_PDDR_BUSCTL_0 (0x01) +#define GPIO_PDDR_BUSCTL_3 (0x08) +#define GPIO_PDDR_BUSCTL_2 (0x04) +#define GPIO_PDDR_BUSCTL_1 (0x02) +#define GPIO_PDDR_BUSCTL_0 (0x01) /* Bit definitions and macros for GPIO_PDDR_BE */ -#define GPIO_PDDR_BE_3 (0x08) -#define GPIO_PDDR_BE_2 (0x04) -#define GPIO_PDDR_BE_1 (0x02) -#define GPIO_PDDR_BE_0 (0x01) +#define GPIO_PDDR_BE_3 (0x08) +#define GPIO_PDDR_BE_2 (0x04) +#define GPIO_PDDR_BE_1 (0x02) +#define GPIO_PDDR_BE_0 (0x01) /* Bit definitions and macros for GPIO_PDDR_CS */ -#define GPIO_PDDR_CS_1 (0x02) -#define GPIO_PDDR_CS_2 (0x04) -#define GPIO_PDDR_CS_3 (0x08) -#define GPIO_PDDR_CS_4 (0x10) -#define GPIO_PDDR_CS_5 (0x20) +#define GPIO_PDDR_CS_1 (0x02) +#define GPIO_PDDR_CS_2 (0x04) +#define GPIO_PDDR_CS_3 (0x08) +#define GPIO_PDDR_CS_4 (0x10) +#define GPIO_PDDR_CS_5 (0x20) /* Bit definitions and macros for GPIO_PDDR_PWM */ -#define GPIO_PDDR_PWM_2 (0x04) -#define GPIO_PDDR_PWM_3 (0x08) -#define GPIO_PDDR_PWM_4 (0x10) -#define GPIO_PDDR_PWM_5 (0x20) +#define GPIO_PDDR_PWM_2 (0x04) +#define GPIO_PDDR_PWM_3 (0x08) +#define GPIO_PDDR_PWM_4 (0x10) +#define GPIO_PDDR_PWM_5 (0x20) /* Bit definitions and macros for GPIO_PDDR_FECI2C */ -#define GPIO_PDDR_FECI2C_0 (0x01) -#define GPIO_PDDR_FECI2C_1 (0x02) -#define GPIO_PDDR_FECI2C_2 (0x04) -#define GPIO_PDDR_FECI2C_3 (0x08) +#define GPIO_PDDR_FECI2C_0 (0x01) +#define GPIO_PDDR_FECI2C_1 (0x02) +#define GPIO_PDDR_FECI2C_2 (0x04) +#define GPIO_PDDR_FECI2C_3 (0x08) /* Bit definitions and macros for GPIO_PDDR_UART */ -#define GPIO_PDDR_UART_0 (0x01) -#define GPIO_PDDR_UART_1 (0x02) -#define GPIO_PDDR_UART_2 (0x04) -#define GPIO_PDDR_UART_3 (0x08) -#define GPIO_PDDR_UART_4 (0x10) -#define GPIO_PDDR_UART_5 (0x20) -#define GPIO_PDDR_UART_6 (0x40) -#define GPIO_PDDR_UART_7 (0x80) +#define GPIO_PDDR_UART_0 (0x01) +#define GPIO_PDDR_UART_1 (0x02) +#define GPIO_PDDR_UART_2 (0x04) +#define GPIO_PDDR_UART_3 (0x08) +#define GPIO_PDDR_UART_4 (0x10) +#define GPIO_PDDR_UART_5 (0x20) +#define GPIO_PDDR_UART_6 (0x40) +#define GPIO_PDDR_UART_7 (0x80) /* Bit definitions and macros for GPIO_PDDR_QSPI */ -#define GPIO_PDDR_QSPI_0 (0x01) -#define GPIO_PDDR_QSPI_1 (0x02) -#define GPIO_PDDR_QSPI_2 (0x04) -#define GPIO_PDDR_QSPI_3 (0x08) -#define GPIO_PDDR_QSPI_4 (0x10) -#define GPIO_PDDR_QSPI_5 (0x20) +#define GPIO_PDDR_QSPI_0 (0x01) +#define GPIO_PDDR_QSPI_1 (0x02) +#define GPIO_PDDR_QSPI_2 (0x04) +#define GPIO_PDDR_QSPI_3 (0x08) +#define GPIO_PDDR_QSPI_4 (0x10) +#define GPIO_PDDR_QSPI_5 (0x20) /* Bit definitions and macros for GPIO_PDDR_TIMER */ -#define GPIO_PDDR_TIMER_0 (0x01) -#define GPIO_PDDR_TIMER_1 (0x02) -#define GPIO_PDDR_TIMER_2 (0x04) -#define GPIO_PDDR_TIMER_3 (0x08) +#define GPIO_PDDR_TIMER_0 (0x01) +#define GPIO_PDDR_TIMER_1 (0x02) +#define GPIO_PDDR_TIMER_2 (0x04) +#define GPIO_PDDR_TIMER_3 (0x08) /* Bit definitions and macros for GPIO_PDDR_LCDDATAH */ -#define GPIO_PDDR_LCDDATAH_0 (0x01) -#define GPIO_PDDR_LCDDATAH_1 (0x02) +#define GPIO_PDDR_LCDDATAH_0 (0x01) +#define GPIO_PDDR_LCDDATAH_1 (0x02) /* Bit definitions and macros for GPIO_PDDR_LCDDATAM */ -#define GPIO_PDDR_LCDDATAM_0 (0x01) -#define GPIO_PDDR_LCDDATAM_1 (0x02) -#define GPIO_PDDR_LCDDATAM_2 (0x04) -#define GPIO_PDDR_LCDDATAM_3 (0x08) -#define GPIO_PDDR_LCDDATAM_4 (0x10) -#define GPIO_PDDR_LCDDATAM_5 (0x20) -#define GPIO_PDDR_LCDDATAM_6 (0x40) -#define GPIO_PDDR_LCDDATAM_7 (0x80) +#define GPIO_PDDR_LCDDATAM_0 (0x01) +#define GPIO_PDDR_LCDDATAM_1 (0x02) +#define GPIO_PDDR_LCDDATAM_2 (0x04) +#define GPIO_PDDR_LCDDATAM_3 (0x08) +#define GPIO_PDDR_LCDDATAM_4 (0x10) +#define GPIO_PDDR_LCDDATAM_5 (0x20) +#define GPIO_PDDR_LCDDATAM_6 (0x40) +#define GPIO_PDDR_LCDDATAM_7 (0x80) /* Bit definitions and macros for GPIO_PDDR_LCDDATAL */ -#define GPIO_PDDR_LCDDATAL_0 (0x01) -#define GPIO_PDDR_LCDDATAL_1 (0x02) -#define GPIO_PDDR_LCDDATAL_2 (0x04) -#define GPIO_PDDR_LCDDATAL_3 (0x08) -#define GPIO_PDDR_LCDDATAL_4 (0x10) -#define GPIO_PDDR_LCDDATAL_5 (0x20) -#define GPIO_PDDR_LCDDATAL_6 (0x40) -#define GPIO_PDDR_LCDDATAL_7 (0x80) +#define GPIO_PDDR_LCDDATAL_0 (0x01) +#define GPIO_PDDR_LCDDATAL_1 (0x02) +#define GPIO_PDDR_LCDDATAL_2 (0x04) +#define GPIO_PDDR_LCDDATAL_3 (0x08) +#define GPIO_PDDR_LCDDATAL_4 (0x10) +#define GPIO_PDDR_LCDDATAL_5 (0x20) +#define GPIO_PDDR_LCDDATAL_6 (0x40) +#define GPIO_PDDR_LCDDATAL_7 (0x80) /* Bit definitions and macros for GPIO_PDDR_LCDCTLH */ -#define GPIO_PDDR_LCDCTLH_0 (0x01) +#define GPIO_PDDR_LCDCTLH_0 (0x01) /* Bit definitions and macros for GPIO_PDDR_LCDCTLL */ -#define GPIO_PDDR_LCDCTLL_0 (0x01) -#define GPIO_PDDR_LCDCTLL_1 (0x02) -#define GPIO_PDDR_LCDCTLL_2 (0x04) -#define GPIO_PDDR_LCDCTLL_3 (0x08) -#define GPIO_PDDR_LCDCTLL_4 (0x10) -#define GPIO_PDDR_LCDCTLL_5 (0x20) -#define GPIO_PDDR_LCDCTLL_6 (0x40) -#define GPIO_PDDR_LCDCTLL_7 (0x80) +#define GPIO_PDDR_LCDCTLL_0 (0x01) +#define GPIO_PDDR_LCDCTLL_1 (0x02) +#define GPIO_PDDR_LCDCTLL_2 (0x04) +#define GPIO_PDDR_LCDCTLL_3 (0x08) +#define GPIO_PDDR_LCDCTLL_4 (0x10) +#define GPIO_PDDR_LCDCTLL_5 (0x20) +#define GPIO_PDDR_LCDCTLL_6 (0x40) +#define GPIO_PDDR_LCDCTLL_7 (0x80) /* Bit definitions and macros for GPIO_PPDSDR_FECH */ -#define GPIO_PPDSDR_FECH_L0 (0x01) -#define GPIO_PPDSDR_FECH_L1 (0x02) -#define GPIO_PPDSDR_FECH_L2 (0x04) -#define GPIO_PPDSDR_FECH_L3 (0x08) -#define GPIO_PPDSDR_FECH_L4 (0x10) -#define GPIO_PPDSDR_FECH_L5 (0x20) -#define GPIO_PPDSDR_FECH_L6 (0x40) -#define GPIO_PPDSDR_FECH_L7 (0x80) +#define GPIO_PPDSDR_FECH_L0 (0x01) +#define GPIO_PPDSDR_FECH_L1 (0x02) +#define GPIO_PPDSDR_FECH_L2 (0x04) +#define GPIO_PPDSDR_FECH_L3 (0x08) +#define GPIO_PPDSDR_FECH_L4 (0x10) +#define GPIO_PPDSDR_FECH_L5 (0x20) +#define GPIO_PPDSDR_FECH_L6 (0x40) +#define GPIO_PPDSDR_FECH_L7 (0x80) /* Bit definitions and macros for GPIO_PPDSDR_SSI */ -#define GPIO_PPDSDR_SSI_0 (0x01) -#define GPIO_PPDSDR_SSI_1 (0x02) -#define GPIO_PPDSDR_SSI_2 (0x04) -#define GPIO_PPDSDR_SSI_3 (0x08) -#define GPIO_PPDSDR_SSI_4 (0x10) +#define GPIO_PPDSDR_SSI_0 (0x01) +#define GPIO_PPDSDR_SSI_1 (0x02) +#define GPIO_PPDSDR_SSI_2 (0x04) +#define GPIO_PPDSDR_SSI_3 (0x08) +#define GPIO_PPDSDR_SSI_4 (0x10) /* Bit definitions and macros for GPIO_PPDSDR_BUSCTL */ -#define GPIO_PPDSDR_BUSCTL_0 (0x01) -#define GPIO_PPDSDR_BUSCTL_1 (0x02) -#define GPIO_PPDSDR_BUSCTL_2 (0x04) -#define GPIO_PPDSDR_BUSCTL_3 (0x08) +#define GPIO_PPDSDR_BUSCTL_0 (0x01) +#define GPIO_PPDSDR_BUSCTL_1 (0x02) +#define GPIO_PPDSDR_BUSCTL_2 (0x04) +#define GPIO_PPDSDR_BUSCTL_3 (0x08) /* Bit definitions and macros for GPIO_PPDSDR_BE */ -#define GPIO_PPDSDR_BE_0 (0x01) -#define GPIO_PPDSDR_BE_1 (0x02) -#define GPIO_PPDSDR_BE_2 (0x04) -#define GPIO_PPDSDR_BE_3 (0x08) +#define GPIO_PPDSDR_BE_0 (0x01) +#define GPIO_PPDSDR_BE_1 (0x02) +#define GPIO_PPDSDR_BE_2 (0x04) +#define GPIO_PPDSDR_BE_3 (0x08) /* Bit definitions and macros for GPIO_PPDSDR_CS */ -#define GPIO_PPDSDR_CS_1 (0x02) -#define GPIO_PPDSDR_CS_2 (0x04) -#define GPIO_PPDSDR_CS_3 (0x08) -#define GPIO_PPDSDR_CS_4 (0x10) -#define GPIO_PPDSDR_CS_5 (0x20) +#define GPIO_PPDSDR_CS_1 (0x02) +#define GPIO_PPDSDR_CS_2 (0x04) +#define GPIO_PPDSDR_CS_3 (0x08) +#define GPIO_PPDSDR_CS_4 (0x10) +#define GPIO_PPDSDR_CS_5 (0x20) /* Bit definitions and macros for GPIO_PPDSDR_PWM */ -#define GPIO_PPDSDR_PWM_2 (0x04) -#define GPIO_PPDSDR_PWM_3 (0x08) -#define GPIO_PPDSDR_PWM_4 (0x10) -#define GPIO_PPDSDR_PWM_5 (0x20) +#define GPIO_PPDSDR_PWM_2 (0x04) +#define GPIO_PPDSDR_PWM_3 (0x08) +#define GPIO_PPDSDR_PWM_4 (0x10) +#define GPIO_PPDSDR_PWM_5 (0x20) /* Bit definitions and macros for GPIO_PPDSDR_FECI2C */ -#define GPIO_PPDSDR_FECI2C_0 (0x01) -#define GPIO_PPDSDR_FECI2C_1 (0x02) -#define GPIO_PPDSDR_FECI2C_2 (0x04) -#define GPIO_PPDSDR_FECI2C_3 (0x08) +#define GPIO_PPDSDR_FECI2C_0 (0x01) +#define GPIO_PPDSDR_FECI2C_1 (0x02) +#define GPIO_PPDSDR_FECI2C_2 (0x04) +#define GPIO_PPDSDR_FECI2C_3 (0x08) /* Bit definitions and macros for GPIO_PPDSDR_UART */ -#define GPIO_PPDSDR_UART_0 (0x01) -#define GPIO_PPDSDR_UART_1 (0x02) -#define GPIO_PPDSDR_UART_2 (0x04) -#define GPIO_PPDSDR_UART_3 (0x08) -#define GPIO_PPDSDR_UART_4 (0x10) -#define GPIO_PPDSDR_UART_5 (0x20) -#define GPIO_PPDSDR_UART_6 (0x40) -#define GPIO_PPDSDR_UART_7 (0x80) +#define GPIO_PPDSDR_UART_0 (0x01) +#define GPIO_PPDSDR_UART_1 (0x02) +#define GPIO_PPDSDR_UART_2 (0x04) +#define GPIO_PPDSDR_UART_3 (0x08) +#define GPIO_PPDSDR_UART_4 (0x10) +#define GPIO_PPDSDR_UART_5 (0x20) +#define GPIO_PPDSDR_UART_6 (0x40) +#define GPIO_PPDSDR_UART_7 (0x80) /* Bit definitions and macros for GPIO_PPDSDR_QSPI */ -#define GPIO_PPDSDR_QSPI_0 (0x01) -#define GPIO_PPDSDR_QSPI_1 (0x02) -#define GPIO_PPDSDR_QSPI_2 (0x04) -#define GPIO_PPDSDR_QSPI_3 (0x08) -#define GPIO_PPDSDR_QSPI_4 (0x10) -#define GPIO_PPDSDR_QSPI_5 (0x20) +#define GPIO_PPDSDR_QSPI_0 (0x01) +#define GPIO_PPDSDR_QSPI_1 (0x02) +#define GPIO_PPDSDR_QSPI_2 (0x04) +#define GPIO_PPDSDR_QSPI_3 (0x08) +#define GPIO_PPDSDR_QSPI_4 (0x10) +#define GPIO_PPDSDR_QSPI_5 (0x20) /* Bit definitions and macros for GPIO_PPDSDR_TIMER */ -#define GPIO_PPDSDR_TIMER_0 (0x01) -#define GPIO_PPDSDR_TIMER_1 (0x02) -#define GPIO_PPDSDR_TIMER_2 (0x04) -#define GPIO_PPDSDR_TIMER_3 (0x08) +#define GPIO_PPDSDR_TIMER_0 (0x01) +#define GPIO_PPDSDR_TIMER_1 (0x02) +#define GPIO_PPDSDR_TIMER_2 (0x04) +#define GPIO_PPDSDR_TIMER_3 (0x08) /* Bit definitions and macros for GPIO_PPDSDR_LCDDATAH */ -#define GPIO_PPDSDR_LCDDATAH_0 (0x01) -#define GPIO_PPDSDR_LCDDATAH_1 (0x02) +#define GPIO_PPDSDR_LCDDATAH_0 (0x01) +#define GPIO_PPDSDR_LCDDATAH_1 (0x02) /* Bit definitions and macros for GPIO_PPDSDR_LCDDATAM */ -#define GPIO_PPDSDR_LCDDATAM_0 (0x01) -#define GPIO_PPDSDR_LCDDATAM_1 (0x02) -#define GPIO_PPDSDR_LCDDATAM_2 (0x04) -#define GPIO_PPDSDR_LCDDATAM_3 (0x08) -#define GPIO_PPDSDR_LCDDATAM_4 (0x10) -#define GPIO_PPDSDR_LCDDATAM_5 (0x20) -#define GPIO_PPDSDR_LCDDATAM_6 (0x40) -#define GPIO_PPDSDR_LCDDATAM_7 (0x80) +#define GPIO_PPDSDR_LCDDATAM_0 (0x01) +#define GPIO_PPDSDR_LCDDATAM_1 (0x02) +#define GPIO_PPDSDR_LCDDATAM_2 (0x04) +#define GPIO_PPDSDR_LCDDATAM_3 (0x08) +#define GPIO_PPDSDR_LCDDATAM_4 (0x10) +#define GPIO_PPDSDR_LCDDATAM_5 (0x20) +#define GPIO_PPDSDR_LCDDATAM_6 (0x40) +#define GPIO_PPDSDR_LCDDATAM_7 (0x80) /* Bit definitions and macros for GPIO_PPDSDR_LCDDATAL */ -#define GPIO_PPDSDR_LCDDATAL_0 (0x01) -#define GPIO_PPDSDR_LCDDATAL_1 (0x02) -#define GPIO_PPDSDR_LCDDATAL_2 (0x04) -#define GPIO_PPDSDR_LCDDATAL_3 (0x08) -#define GPIO_PPDSDR_LCDDATAL_4 (0x10) -#define GPIO_PPDSDR_LCDDATAL_5 (0x20) -#define GPIO_PPDSDR_LCDDATAL_6 (0x40) -#define GPIO_PPDSDR_LCDDATAL_7 (0x80) +#define GPIO_PPDSDR_LCDDATAL_0 (0x01) +#define GPIO_PPDSDR_LCDDATAL_1 (0x02) +#define GPIO_PPDSDR_LCDDATAL_2 (0x04) +#define GPIO_PPDSDR_LCDDATAL_3 (0x08) +#define GPIO_PPDSDR_LCDDATAL_4 (0x10) +#define GPIO_PPDSDR_LCDDATAL_5 (0x20) +#define GPIO_PPDSDR_LCDDATAL_6 (0x40) +#define GPIO_PPDSDR_LCDDATAL_7 (0x80) /* Bit definitions and macros for GPIO_PPDSDR_LCDCTLH */ -#define GPIO_PPDSDR_LCDCTLH_0 (0x01) +#define GPIO_PPDSDR_LCDCTLH_0 (0x01) /* Bit definitions and macros for GPIO_PPDSDR_LCDCTLL */ -#define GPIO_PPDSDR_LCDCTLL_0 (0x01) -#define GPIO_PPDSDR_LCDCTLL_1 (0x02) -#define GPIO_PPDSDR_LCDCTLL_2 (0x04) -#define GPIO_PPDSDR_LCDCTLL_3 (0x08) -#define GPIO_PPDSDR_LCDCTLL_4 (0x10) -#define GPIO_PPDSDR_LCDCTLL_5 (0x20) -#define GPIO_PPDSDR_LCDCTLL_6 (0x40) -#define GPIO_PPDSDR_LCDCTLL_7 (0x80) +#define GPIO_PPDSDR_LCDCTLL_0 (0x01) +#define GPIO_PPDSDR_LCDCTLL_1 (0x02) +#define GPIO_PPDSDR_LCDCTLL_2 (0x04) +#define GPIO_PPDSDR_LCDCTLL_3 (0x08) +#define GPIO_PPDSDR_LCDCTLL_4 (0x10) +#define GPIO_PPDSDR_LCDCTLL_5 (0x20) +#define GPIO_PPDSDR_LCDCTLL_6 (0x40) +#define GPIO_PPDSDR_LCDCTLL_7 (0x80) /* Bit definitions and macros for GPIO_PCLRR_FECH */ -#define GPIO_PCLRR_FECH_L0 (0x01) -#define GPIO_PCLRR_FECH_L1 (0x02) -#define GPIO_PCLRR_FECH_L2 (0x04) -#define GPIO_PCLRR_FECH_L3 (0x08) -#define GPIO_PCLRR_FECH_L4 (0x10) -#define GPIO_PCLRR_FECH_L5 (0x20) -#define GPIO_PCLRR_FECH_L6 (0x40) -#define GPIO_PCLRR_FECH_L7 (0x80) +#define GPIO_PCLRR_FECH_L0 (0x01) +#define GPIO_PCLRR_FECH_L1 (0x02) +#define GPIO_PCLRR_FECH_L2 (0x04) +#define GPIO_PCLRR_FECH_L3 (0x08) +#define GPIO_PCLRR_FECH_L4 (0x10) +#define GPIO_PCLRR_FECH_L5 (0x20) +#define GPIO_PCLRR_FECH_L6 (0x40) +#define GPIO_PCLRR_FECH_L7 (0x80) /* Bit definitions and macros for GPIO_PCLRR_SSI */ -#define GPIO_PCLRR_SSI_0 (0x01) -#define GPIO_PCLRR_SSI_1 (0x02) -#define GPIO_PCLRR_SSI_2 (0x04) -#define GPIO_PCLRR_SSI_3 (0x08) -#define GPIO_PCLRR_SSI_4 (0x10) +#define GPIO_PCLRR_SSI_0 (0x01) +#define GPIO_PCLRR_SSI_1 (0x02) +#define GPIO_PCLRR_SSI_2 (0x04) +#define GPIO_PCLRR_SSI_3 (0x08) +#define GPIO_PCLRR_SSI_4 (0x10) /* Bit definitions and macros for GPIO_PCLRR_BUSCTL */ -#define GPIO_PCLRR_BUSCTL_L0 (0x01) -#define GPIO_PCLRR_BUSCTL_L1 (0x02) -#define GPIO_PCLRR_BUSCTL_L2 (0x04) -#define GPIO_PCLRR_BUSCTL_L3 (0x08) +#define GPIO_PCLRR_BUSCTL_L0 (0x01) +#define GPIO_PCLRR_BUSCTL_L1 (0x02) +#define GPIO_PCLRR_BUSCTL_L2 (0x04) +#define GPIO_PCLRR_BUSCTL_L3 (0x08) /* Bit definitions and macros for GPIO_PCLRR_BE */ -#define GPIO_PCLRR_BE_0 (0x01) -#define GPIO_PCLRR_BE_1 (0x02) -#define GPIO_PCLRR_BE_2 (0x04) -#define GPIO_PCLRR_BE_3 (0x08) +#define GPIO_PCLRR_BE_0 (0x01) +#define GPIO_PCLRR_BE_1 (0x02) +#define GPIO_PCLRR_BE_2 (0x04) +#define GPIO_PCLRR_BE_3 (0x08) /* Bit definitions and macros for GPIO_PCLRR_CS */ -#define GPIO_PCLRR_CS_1 (0x02) -#define GPIO_PCLRR_CS_2 (0x04) -#define GPIO_PCLRR_CS_3 (0x08) -#define GPIO_PCLRR_CS_4 (0x10) -#define GPIO_PCLRR_CS_5 (0x20) +#define GPIO_PCLRR_CS_1 (0x02) +#define GPIO_PCLRR_CS_2 (0x04) +#define GPIO_PCLRR_CS_3 (0x08) +#define GPIO_PCLRR_CS_4 (0x10) +#define GPIO_PCLRR_CS_5 (0x20) /* Bit definitions and macros for GPIO_PCLRR_PWM */ -#define GPIO_PCLRR_PWM_2 (0x04) -#define GPIO_PCLRR_PWM_3 (0x08) -#define GPIO_PCLRR_PWM_4 (0x10) -#define GPIO_PCLRR_PWM_5 (0x20) +#define GPIO_PCLRR_PWM_2 (0x04) +#define GPIO_PCLRR_PWM_3 (0x08) +#define GPIO_PCLRR_PWM_4 (0x10) +#define GPIO_PCLRR_PWM_5 (0x20) /* Bit definitions and macros for GPIO_PCLRR_FECI2C */ -#define GPIO_PCLRR_FECI2C_0 (0x01) -#define GPIO_PCLRR_FECI2C_1 (0x02) -#define GPIO_PCLRR_FECI2C_2 (0x04) -#define GPIO_PCLRR_FECI2C_3 (0x08) +#define GPIO_PCLRR_FECI2C_0 (0x01) +#define GPIO_PCLRR_FECI2C_1 (0x02) +#define GPIO_PCLRR_FECI2C_2 (0x04) +#define GPIO_PCLRR_FECI2C_3 (0x08) /* Bit definitions and macros for GPIO_PCLRR_UART */ -#define GPIO_PCLRR_UART0 (0x01) -#define GPIO_PCLRR_UART1 (0x02) -#define GPIO_PCLRR_UART2 (0x04) -#define GPIO_PCLRR_UART3 (0x08) -#define GPIO_PCLRR_UART4 (0x10) -#define GPIO_PCLRR_UART5 (0x20) -#define GPIO_PCLRR_UART6 (0x40) -#define GPIO_PCLRR_UART7 (0x80) +#define GPIO_PCLRR_UART0 (0x01) +#define GPIO_PCLRR_UART1 (0x02) +#define GPIO_PCLRR_UART2 (0x04) +#define GPIO_PCLRR_UART3 (0x08) +#define GPIO_PCLRR_UART4 (0x10) +#define GPIO_PCLRR_UART5 (0x20) +#define GPIO_PCLRR_UART6 (0x40) +#define GPIO_PCLRR_UART7 (0x80) /* Bit definitions and macros for GPIO_PCLRR_QSPI */ -#define GPIO_PCLRR_QSPI0 (0x01) -#define GPIO_PCLRR_QSPI1 (0x02) -#define GPIO_PCLRR_QSPI2 (0x04) -#define GPIO_PCLRR_QSPI3 (0x08) -#define GPIO_PCLRR_QSPI4 (0x10) -#define GPIO_PCLRR_QSPI5 (0x20) +#define GPIO_PCLRR_QSPI0 (0x01) +#define GPIO_PCLRR_QSPI1 (0x02) +#define GPIO_PCLRR_QSPI2 (0x04) +#define GPIO_PCLRR_QSPI3 (0x08) +#define GPIO_PCLRR_QSPI4 (0x10) +#define GPIO_PCLRR_QSPI5 (0x20) /* Bit definitions and macros for GPIO_PCLRR_TIMER */ -#define GPIO_PCLRR_TIMER0 (0x01) -#define GPIO_PCLRR_TIMER1 (0x02) -#define GPIO_PCLRR_TIMER2 (0x04) -#define GPIO_PCLRR_TIMER3 (0x08) +#define GPIO_PCLRR_TIMER0 (0x01) +#define GPIO_PCLRR_TIMER1 (0x02) +#define GPIO_PCLRR_TIMER2 (0x04) +#define GPIO_PCLRR_TIMER3 (0x08) /* Bit definitions and macros for GPIO_PCLRR_LCDDATAH */ -#define GPIO_PCLRR_LCDDATAH0 (0x01) -#define GPIO_PCLRR_LCDDATAH1 (0x02) +#define GPIO_PCLRR_LCDDATAH0 (0x01) +#define GPIO_PCLRR_LCDDATAH1 (0x02) /* Bit definitions and macros for GPIO_PCLRR_LCDDATAM */ -#define GPIO_PCLRR_LCDDATAM0 (0x01) -#define GPIO_PCLRR_LCDDATAM1 (0x02) -#define GPIO_PCLRR_LCDDATAM2 (0x04) -#define GPIO_PCLRR_LCDDATAM3 (0x08) -#define GPIO_PCLRR_LCDDATAM4 (0x10) -#define GPIO_PCLRR_LCDDATAM5 (0x20) -#define GPIO_PCLRR_LCDDATAM6 (0x40) -#define GPIO_PCLRR_LCDDATAM7 (0x80) +#define GPIO_PCLRR_LCDDATAM0 (0x01) +#define GPIO_PCLRR_LCDDATAM1 (0x02) +#define GPIO_PCLRR_LCDDATAM2 (0x04) +#define GPIO_PCLRR_LCDDATAM3 (0x08) +#define GPIO_PCLRR_LCDDATAM4 (0x10) +#define GPIO_PCLRR_LCDDATAM5 (0x20) +#define GPIO_PCLRR_LCDDATAM6 (0x40) +#define GPIO_PCLRR_LCDDATAM7 (0x80) /* Bit definitions and macros for GPIO_PCLRR_LCDDATAL */ -#define GPIO_PCLRR_LCDDATAL0 (0x01) -#define GPIO_PCLRR_LCDDATAL1 (0x02) -#define GPIO_PCLRR_LCDDATAL2 (0x04) -#define GPIO_PCLRR_LCDDATAL3 (0x08) -#define GPIO_PCLRR_LCDDATAL4 (0x10) -#define GPIO_PCLRR_LCDDATAL5 (0x20) -#define GPIO_PCLRR_LCDDATAL6 (0x40) -#define GPIO_PCLRR_LCDDATAL7 (0x80) +#define GPIO_PCLRR_LCDDATAL0 (0x01) +#define GPIO_PCLRR_LCDDATAL1 (0x02) +#define GPIO_PCLRR_LCDDATAL2 (0x04) +#define GPIO_PCLRR_LCDDATAL3 (0x08) +#define GPIO_PCLRR_LCDDATAL4 (0x10) +#define GPIO_PCLRR_LCDDATAL5 (0x20) +#define GPIO_PCLRR_LCDDATAL6 (0x40) +#define GPIO_PCLRR_LCDDATAL7 (0x80) /* Bit definitions and macros for GPIO_PCLRR_LCDCTLH */ -#define GPIO_PCLRR_LCDCTLH_PCLRR_LCDCTLH0 (0x01) +#define GPIO_PCLRR_LCDCTLH_PCLRR_LCDCTLH0 (0x01) /* Bit definitions and macros for GPIO_PCLRR_LCDCTLL */ -#define GPIO_PCLRR_LCDCTLL0 (0x01) -#define GPIO_PCLRR_LCDCTLL1 (0x02) -#define GPIO_PCLRR_LCDCTLL2 (0x04) -#define GPIO_PCLRR_LCDCTLL3 (0x08) -#define GPIO_PCLRR_LCDCTLL4 (0x10) -#define GPIO_PCLRR_LCDCTLL5 (0x20) -#define GPIO_PCLRR_LCDCTLL6 (0x40) -#define GPIO_PCLRR_LCDCTLL7 (0x80) +#define GPIO_PCLRR_LCDCTLL0 (0x01) +#define GPIO_PCLRR_LCDCTLL1 (0x02) +#define GPIO_PCLRR_LCDCTLL2 (0x04) +#define GPIO_PCLRR_LCDCTLL3 (0x08) +#define GPIO_PCLRR_LCDCTLL4 (0x10) +#define GPIO_PCLRR_LCDCTLL5 (0x20) +#define GPIO_PCLRR_LCDCTLL6 (0x40) +#define GPIO_PCLRR_LCDCTLL7 (0x80) /* Bit definitions and macros for GPIO_PAR_FEC */ -#define GPIO_PAR_FEC_MII(x) (((x)&0x03)<<0) -#define GPIO_PAR_FEC_7W(x) (((x)&0x03)<<2) -#define GPIO_PAR_FEC_7W_GPIO (0x00) -#define GPIO_PAR_FEC_7W_URTS1 (0x04) -#define GPIO_PAR_FEC_7W_FEC (0x0C) -#define GPIO_PAR_FEC_MII_GPIO (0x00) -#define GPIO_PAR_FEC_MII_UART (0x01) -#define GPIO_PAR_FEC_MII_FEC (0x03) +#define GPIO_PAR_FEC_MII(x) (((x)&0x03)<<0) +#define GPIO_PAR_FEC_7W(x) (((x)&0x03)<<2) +#define GPIO_PAR_FEC_7W_GPIO (0x00) +#define GPIO_PAR_FEC_7W_URTS1 (0x04) +#define GPIO_PAR_FEC_7W_FEC (0x0C) +#define GPIO_PAR_FEC_MII_GPIO (0x00) +#define GPIO_PAR_FEC_MII_UART (0x01) +#define GPIO_PAR_FEC_MII_FEC (0x03) /* Bit definitions and macros for GPIO_PAR_PWM */ -#define GPIO_PAR_PWM1(x) (((x)&0x03)<<0) -#define GPIO_PAR_PWM3(x) (((x)&0x03)<<2) -#define GPIO_PAR_PWM5 (0x10) -#define GPIO_PAR_PWM7 (0x20) +#define GPIO_PAR_PWM1(x) (((x)&0x03)<<0) +#define GPIO_PAR_PWM3(x) (((x)&0x03)<<2) +#define GPIO_PAR_PWM5 (0x10) +#define GPIO_PAR_PWM7 (0x20) /* Bit definitions and macros for GPIO_PAR_BUSCTL */ -#define GPIO_PAR_BUSCTL_TS(x) (((x)&0x03)<<3) -#define GPIO_PAR_BUSCTL_RWB (0x20) -#define GPIO_PAR_BUSCTL_TA (0x40) -#define GPIO_PAR_BUSCTL_OE (0x80) -#define GPIO_PAR_BUSCTL_OE_GPIO (0x00) -#define GPIO_PAR_BUSCTL_OE_OE (0x80) -#define GPIO_PAR_BUSCTL_TA_GPIO (0x00) -#define GPIO_PAR_BUSCTL_TA_TA (0x40) -#define GPIO_PAR_BUSCTL_RWB_GPIO (0x00) -#define GPIO_PAR_BUSCTL_RWB_RWB (0x20) -#define GPIO_PAR_BUSCTL_TS_GPIO (0x00) -#define GPIO_PAR_BUSCTL_TS_DACK0 (0x10) -#define GPIO_PAR_BUSCTL_TS_TS (0x18) +#define GPIO_PAR_BUSCTL_TS(x) (((x)&0x03)<<3) +#define GPIO_PAR_BUSCTL_RWB (0x20) +#define GPIO_PAR_BUSCTL_TA (0x40) +#define GPIO_PAR_BUSCTL_OE (0x80) +#define GPIO_PAR_BUSCTL_OE_GPIO (0x00) +#define GPIO_PAR_BUSCTL_OE_OE (0x80) +#define GPIO_PAR_BUSCTL_TA_GPIO (0x00) +#define GPIO_PAR_BUSCTL_TA_TA (0x40) +#define GPIO_PAR_BUSCTL_RWB_GPIO (0x00) +#define GPIO_PAR_BUSCTL_RWB_RWB (0x20) +#define GPIO_PAR_BUSCTL_TS_GPIO (0x00) +#define GPIO_PAR_BUSCTL_TS_DACK0 (0x10) +#define GPIO_PAR_BUSCTL_TS_TS (0x18) /* Bit definitions and macros for GPIO_PAR_FECI2C */ -#define GPIO_PAR_FECI2C_SDA(x) (((x)&0x03)<<0) -#define GPIO_PAR_FECI2C_SCL(x) (((x)&0x03)<<2) -#define GPIO_PAR_FECI2C_MDIO(x) (((x)&0x03)<<4) -#define GPIO_PAR_FECI2C_MDC(x) (((x)&0x03)<<6) -#define GPIO_PAR_FECI2C_MDC_GPIO (0x00) -#define GPIO_PAR_FECI2C_MDC_UTXD2 (0x40) -#define GPIO_PAR_FECI2C_MDC_SCL (0x80) -#define GPIO_PAR_FECI2C_MDC_EMDC (0xC0) -#define GPIO_PAR_FECI2C_MDIO_GPIO (0x00) -#define GPIO_PAR_FECI2C_MDIO_URXD2 (0x10) -#define GPIO_PAR_FECI2C_MDIO_SDA (0x20) -#define GPIO_PAR_FECI2C_MDIO_EMDIO (0x30) -#define GPIO_PAR_FECI2C_SCL_GPIO (0x00) -#define GPIO_PAR_FECI2C_SCL_UTXD2 (0x04) -#define GPIO_PAR_FECI2C_SCL_SCL (0x0C) -#define GPIO_PAR_FECI2C_SDA_GPIO (0x00) -#define GPIO_PAR_FECI2C_SDA_URXD2 (0x02) -#define GPIO_PAR_FECI2C_SDA_SDA (0x03) +#define GPIO_PAR_FECI2C_SDA(x) (((x)&0x03)<<0) +#define GPIO_PAR_FECI2C_SCL(x) (((x)&0x03)<<2) +#define GPIO_PAR_FECI2C_MDIO(x) (((x)&0x03)<<4) +#define GPIO_PAR_FECI2C_MDC(x) (((x)&0x03)<<6) +#define GPIO_PAR_FECI2C_MDC_GPIO (0x00) +#define GPIO_PAR_FECI2C_MDC_UTXD2 (0x40) +#define GPIO_PAR_FECI2C_MDC_SCL (0x80) +#define GPIO_PAR_FECI2C_MDC_EMDC (0xC0) +#define GPIO_PAR_FECI2C_MDIO_GPIO (0x00) +#define GPIO_PAR_FECI2C_MDIO_URXD2 (0x10) +#define GPIO_PAR_FECI2C_MDIO_SDA (0x20) +#define GPIO_PAR_FECI2C_MDIO_EMDIO (0x30) +#define GPIO_PAR_FECI2C_SCL_GPIO (0x00) +#define GPIO_PAR_FECI2C_SCL_UTXD2 (0x04) +#define GPIO_PAR_FECI2C_SCL_SCL (0x0C) +#define GPIO_PAR_FECI2C_SDA_GPIO (0x00) +#define GPIO_PAR_FECI2C_SDA_URXD2 (0x02) +#define GPIO_PAR_FECI2C_SDA_SDA (0x03) /* Bit definitions and macros for GPIO_PAR_BE */ -#define GPIO_PAR_BE0 (0x01) -#define GPIO_PAR_BE1 (0x02) -#define GPIO_PAR_BE2 (0x04) -#define GPIO_PAR_BE3 (0x08) +#define GPIO_PAR_BE0 (0x01) +#define GPIO_PAR_BE1 (0x02) +#define GPIO_PAR_BE2 (0x04) +#define GPIO_PAR_BE3 (0x08) /* Bit definitions and macros for GPIO_PAR_CS */ -#define GPIO_PAR_CS1 (0x02) -#define GPIO_PAR_CS2 (0x04) -#define GPIO_PAR_CS3 (0x08) -#define GPIO_PAR_CS4 (0x10) -#define GPIO_PAR_CS5 (0x20) -#define GPIO_PAR_CS1_GPIO (0x00) -#define GPIO_PAR_CS1_SDCS1 (0x01) -#define GPIO_PAR_CS1_CS1 (0x03) +#define GPIO_PAR_CS1 (0x02) +#define GPIO_PAR_CS2 (0x04) +#define GPIO_PAR_CS3 (0x08) +#define GPIO_PAR_CS4 (0x10) +#define GPIO_PAR_CS5 (0x20) +#define GPIO_PAR_CS1_GPIO (0x00) +#define GPIO_PAR_CS1_SDCS1 (0x01) +#define GPIO_PAR_CS1_CS1 (0x03) /* Bit definitions and macros for GPIO_PAR_SSI */ -#define GPIO_PAR_SSI_MCLK (0x0080) -#define GPIO_PAR_SSI_TXD(x) (((x)&0x0003)<<8) -#define GPIO_PAR_SSI_RXD(x) (((x)&0x0003)<<10) -#define GPIO_PAR_SSI_FS(x) (((x)&0x0003)<<12) -#define GPIO_PAR_SSI_BCLK(x) (((x)&0x0003)<<14) +#define GPIO_PAR_SSI_MCLK (0x0080) +#define GPIO_PAR_SSI_TXD(x) (((x)&0x0003)<<8) +#define GPIO_PAR_SSI_RXD(x) (((x)&0x0003)<<10) +#define GPIO_PAR_SSI_FS(x) (((x)&0x0003)<<12) +#define GPIO_PAR_SSI_BCLK(x) (((x)&0x0003)<<14) /* Bit definitions and macros for GPIO_PAR_UART */ -#define GPIO_PAR_UART_TXD0 (0x0001) -#define GPIO_PAR_UART_RXD0 (0x0002) -#define GPIO_PAR_UART_RTS0 (0x0004) -#define GPIO_PAR_UART_CTS0 (0x0008) -#define GPIO_PAR_UART_TXD1(x) (((x)&0x0003)<<4) -#define GPIO_PAR_UART_RXD1(x) (((x)&0x0003)<<6) -#define GPIO_PAR_UART_RTS1(x) (((x)&0x0003)<<8) -#define GPIO_PAR_UART_CTS1(x) (((x)&0x0003)<<10) -#define GPIO_PAR_UART_CTS1_GPIO (0x0000) -#define GPIO_PAR_UART_CTS1_SSI_BCLK (0x0800) -#define GPIO_PAR_UART_CTS1_ULPI_D7 (0x0400) -#define GPIO_PAR_UART_CTS1_UCTS1 (0x0C00) -#define GPIO_PAR_UART_RTS1_GPIO (0x0000) -#define GPIO_PAR_UART_RTS1_SSI_FS (0x0200) -#define GPIO_PAR_UART_RTS1_ULPI_D6 (0x0100) -#define GPIO_PAR_UART_RTS1_URTS1 (0x0300) -#define GPIO_PAR_UART_RXD1_GPIO (0x0000) -#define GPIO_PAR_UART_RXD1_SSI_RXD (0x0080) -#define GPIO_PAR_UART_RXD1_ULPI_D5 (0x0040) -#define GPIO_PAR_UART_RXD1_URXD1 (0x00C0) -#define GPIO_PAR_UART_TXD1_GPIO (0x0000) -#define GPIO_PAR_UART_TXD1_SSI_TXD (0x0020) -#define GPIO_PAR_UART_TXD1_ULPI_D4 (0x0010) -#define GPIO_PAR_UART_TXD1_UTXD1 (0x0030) +#define GPIO_PAR_UART_TXD0 (0x0001) +#define GPIO_PAR_UART_RXD0 (0x0002) +#define GPIO_PAR_UART_RTS0 (0x0004) +#define GPIO_PAR_UART_CTS0 (0x0008) +#define GPIO_PAR_UART_TXD1(x) (((x)&0x0003)<<4) +#define GPIO_PAR_UART_RXD1(x) (((x)&0x0003)<<6) +#define GPIO_PAR_UART_RTS1(x) (((x)&0x0003)<<8) +#define GPIO_PAR_UART_CTS1(x) (((x)&0x0003)<<10) +#define GPIO_PAR_UART_CTS1_GPIO (0x0000) +#define GPIO_PAR_UART_CTS1_SSI_BCLK (0x0800) +#define GPIO_PAR_UART_CTS1_ULPI_D7 (0x0400) +#define GPIO_PAR_UART_CTS1_UCTS1 (0x0C00) +#define GPIO_PAR_UART_RTS1_GPIO (0x0000) +#define GPIO_PAR_UART_RTS1_SSI_FS (0x0200) +#define GPIO_PAR_UART_RTS1_ULPI_D6 (0x0100) +#define GPIO_PAR_UART_RTS1_URTS1 (0x0300) +#define GPIO_PAR_UART_RXD1_GPIO (0x0000) +#define GPIO_PAR_UART_RXD1_SSI_RXD (0x0080) +#define GPIO_PAR_UART_RXD1_ULPI_D5 (0x0040) +#define GPIO_PAR_UART_RXD1_URXD1 (0x00C0) +#define GPIO_PAR_UART_TXD1_GPIO (0x0000) +#define GPIO_PAR_UART_TXD1_SSI_TXD (0x0020) +#define GPIO_PAR_UART_TXD1_ULPI_D4 (0x0010) +#define GPIO_PAR_UART_TXD1_UTXD1 (0x0030) /* Bit definitions and macros for GPIO_PAR_QSPI */ -#define GPIO_PAR_QSPI_SCK(x) (((x)&0x0003)<<4) -#define GPIO_PAR_QSPI_DOUT(x) (((x)&0x0003)<<6) -#define GPIO_PAR_QSPI_DIN(x) (((x)&0x0003)<<8) -#define GPIO_PAR_QSPI_PCS0(x) (((x)&0x0003)<<10) -#define GPIO_PAR_QSPI_PCS1(x) (((x)&0x0003)<<12) -#define GPIO_PAR_QSPI_PCS2(x) (((x)&0x0003)<<14) +#define GPIO_PAR_QSPI_SCK(x) (((x)&0x0003)<<4) +#define GPIO_PAR_QSPI_DOUT(x) (((x)&0x0003)<<6) +#define GPIO_PAR_QSPI_DIN(x) (((x)&0x0003)<<8) +#define GPIO_PAR_QSPI_PCS0(x) (((x)&0x0003)<<10) +#define GPIO_PAR_QSPI_PCS1(x) (((x)&0x0003)<<12) +#define GPIO_PAR_QSPI_PCS2(x) (((x)&0x0003)<<14) /* Bit definitions and macros for GPIO_PAR_TIMER */ -#define GPIO_PAR_TIN0(x) (((x)&0x03)<<0) -#define GPIO_PAR_TIN1(x) (((x)&0x03)<<2) -#define GPIO_PAR_TIN2(x) (((x)&0x03)<<4) -#define GPIO_PAR_TIN3(x) (((x)&0x03)<<6) -#define GPIO_PAR_TIN3_GPIO (0x00) -#define GPIO_PAR_TIN3_TOUT3 (0x80) -#define GPIO_PAR_TIN3_URXD2 (0x40) -#define GPIO_PAR_TIN3_TIN3 (0xC0) -#define GPIO_PAR_TIN2_GPIO (0x00) -#define GPIO_PAR_TIN2_TOUT2 (0x20) -#define GPIO_PAR_TIN2_UTXD2 (0x10) -#define GPIO_PAR_TIN2_TIN2 (0x30) -#define GPIO_PAR_TIN1_GPIO (0x00) -#define GPIO_PAR_TIN1_TOUT1 (0x08) -#define GPIO_PAR_TIN1_DACK1 (0x04) -#define GPIO_PAR_TIN1_TIN1 (0x0C) -#define GPIO_PAR_TIN0_GPIO (0x00) -#define GPIO_PAR_TIN0_TOUT0 (0x02) -#define GPIO_PAR_TIN0_DREQ0 (0x01) -#define GPIO_PAR_TIN0_TIN0 (0x03) +#define GPIO_PAR_TIN0(x) (((x)&0x03)<<0) +#define GPIO_PAR_TIN1(x) (((x)&0x03)<<2) +#define GPIO_PAR_TIN2(x) (((x)&0x03)<<4) +#define GPIO_PAR_TIN3(x) (((x)&0x03)<<6) +#define GPIO_PAR_TIN3_GPIO (0x00) +#define GPIO_PAR_TIN3_TOUT3 (0x80) +#define GPIO_PAR_TIN3_URXD2 (0x40) +#define GPIO_PAR_TIN3_TIN3 (0xC0) +#define GPIO_PAR_TIN2_GPIO (0x00) +#define GPIO_PAR_TIN2_TOUT2 (0x20) +#define GPIO_PAR_TIN2_UTXD2 (0x10) +#define GPIO_PAR_TIN2_TIN2 (0x30) +#define GPIO_PAR_TIN1_GPIO (0x00) +#define GPIO_PAR_TIN1_TOUT1 (0x08) +#define GPIO_PAR_TIN1_DACK1 (0x04) +#define GPIO_PAR_TIN1_TIN1 (0x0C) +#define GPIO_PAR_TIN0_GPIO (0x00) +#define GPIO_PAR_TIN0_TOUT0 (0x02) +#define GPIO_PAR_TIN0_DREQ0 (0x01) +#define GPIO_PAR_TIN0_TIN0 (0x03) /* Bit definitions and macros for GPIO_PAR_LCDDATA */ -#define GPIO_PAR_LCDDATA_LD7_0(x) ((x)&0x03) -#define GPIO_PAR_LCDDATA_LD15_8(x) (((x)&0x03)<<2) -#define GPIO_PAR_LCDDATA_LD16(x) (((x)&0x03)<<4) -#define GPIO_PAR_LCDDATA_LD17(x) (((x)&0x03)<<6) +#define GPIO_PAR_LCDDATA_LD7_0(x) ((x)&0x03) +#define GPIO_PAR_LCDDATA_LD15_8(x) (((x)&0x03)<<2) +#define GPIO_PAR_LCDDATA_LD16(x) (((x)&0x03)<<4) +#define GPIO_PAR_LCDDATA_LD17(x) (((x)&0x03)<<6) /* Bit definitions and macros for GPIO_PAR_LCDCTL */ -#define GPIO_PAR_LCDCTL_CLS (0x0001) -#define GPIO_PAR_LCDCTL_PS (0x0002) -#define GPIO_PAR_LCDCTL_REV (0x0004) -#define GPIO_PAR_LCDCTL_SPL_SPR (0x0008) -#define GPIO_PAR_LCDCTL_CONTRAST (0x0010) -#define GPIO_PAR_LCDCTL_LSCLK (0x0020) -#define GPIO_PAR_LCDCTL_LP_HSYNC (0x0040) -#define GPIO_PAR_LCDCTL_FLM_VSYNC (0x0080) -#define GPIO_PAR_LCDCTL_ACD_OE (0x0100) +#define GPIO_PAR_LCDCTL_CLS (0x0001) +#define GPIO_PAR_LCDCTL_PS (0x0002) +#define GPIO_PAR_LCDCTL_REV (0x0004) +#define GPIO_PAR_LCDCTL_SPL_SPR (0x0008) +#define GPIO_PAR_LCDCTL_CONTRAST (0x0010) +#define GPIO_PAR_LCDCTL_LSCLK (0x0020) +#define GPIO_PAR_LCDCTL_LP_HSYNC (0x0040) +#define GPIO_PAR_LCDCTL_FLM_VSYNC (0x0080) +#define GPIO_PAR_LCDCTL_ACD_OE (0x0100) /* Bit definitions and macros for GPIO_PAR_IRQ */ -#define GPIO_PAR_IRQ1(x) (((x)&0x0003)<<4) -#define GPIO_PAR_IRQ2(x) (((x)&0x0003)<<6) -#define GPIO_PAR_IRQ4(x) (((x)&0x0003)<<8) -#define GPIO_PAR_IRQ5(x) (((x)&0x0003)<<10) -#define GPIO_PAR_IRQ6(x) (((x)&0x0003)<<12) +#define GPIO_PAR_IRQ1(x) (((x)&0x0003)<<4) +#define GPIO_PAR_IRQ2(x) (((x)&0x0003)<<6) +#define GPIO_PAR_IRQ4(x) (((x)&0x0003)<<8) +#define GPIO_PAR_IRQ5(x) (((x)&0x0003)<<10) +#define GPIO_PAR_IRQ6(x) (((x)&0x0003)<<12) /* Bit definitions and macros for GPIO_MSCR_FLEXBUS */ -#define GPIO_MSCR_FLEXBUS_ADDRCTL(x) ((x)&0x03) -#define GPIO_MSCR_FLEXBUS_DLOWER(x) (((x)&0x03)<<2) -#define GPIO_MSCR_FLEXBUS_DUPPER(x) (((x)&0x03)<<4) +#define GPIO_MSCR_FLEXBUS_ADDRCTL(x) ((x)&0x03) +#define GPIO_MSCR_FLEXBUS_DLOWER(x) (((x)&0x03)<<2) +#define GPIO_MSCR_FLEXBUS_DUPPER(x) (((x)&0x03)<<4) /* Bit definitions and macros for GPIO_MSCR_SDRAM */ -#define GPIO_MSCR_SDRAM_SDRAM(x) ((x)&0x03) -#define GPIO_MSCR_SDRAM_SDCLK(x) (((x)&0x03)<<2) -#define GPIO_MSCR_SDRAM_SDCLKB(x) (((x)&0x03)<<4) +#define GPIO_MSCR_SDRAM_SDRAM(x) ((x)&0x03) +#define GPIO_MSCR_SDRAM_SDCLK(x) (((x)&0x03)<<2) +#define GPIO_MSCR_SDRAM_SDCLKB(x) (((x)&0x03)<<4) /* Bit definitions and macros for GPIO_DSCR_I2C */ -#define GPIO_DSCR_I2C_DSE(x) ((x)&0x03) +#define GPIO_DSCR_I2C_DSE(x) ((x)&0x03) /* Bit definitions and macros for GPIO_DSCR_PWM */ -#define GPIO_DSCR_PWM_DSE(x) ((x)&0x03) +#define GPIO_DSCR_PWM_DSE(x) ((x)&0x03) /* Bit definitions and macros for GPIO_DSCR_FEC */ -#define GPIO_DSCR_FEC_DSE(x) ((x)&0x03) +#define GPIO_DSCR_FEC_DSE(x) ((x)&0x03) /* Bit definitions and macros for GPIO_DSCR_UART */ -#define GPIO_DSCR_UART0_DSE(x) ((x)&0x03) -#define GPIO_DSCR_UART1_DSE(x) (((x)&0x03)<<2) +#define GPIO_DSCR_UART0_DSE(x) ((x)&0x03) +#define GPIO_DSCR_UART1_DSE(x) (((x)&0x03)<<2) /* Bit definitions and macros for GPIO_DSCR_QSPI */ -#define GPIO_DSCR_QSPI_DSE(x) ((x)&0x03) +#define GPIO_DSCR_QSPI_DSE(x) ((x)&0x03) /* Bit definitions and macros for GPIO_DSCR_TIMER */ -#define GPIO_DSCR_TIMER_DSE(x) ((x)&0x03) +#define GPIO_DSCR_TIMER_DSE(x) ((x)&0x03) /* Bit definitions and macros for GPIO_DSCR_SSI */ -#define GPIO_DSCR_SSI_DSE(x) ((x)&0x03) +#define GPIO_DSCR_SSI_DSE(x) ((x)&0x03) /* Bit definitions and macros for GPIO_DSCR_LCD */ -#define GPIO_DSCR_LCD_DSE(x) ((x)&0x03) +#define GPIO_DSCR_LCD_DSE(x) ((x)&0x03) /* Bit definitions and macros for GPIO_DSCR_DEBUG */ -#define GPIO_DSCR_DEBUG_DSE(x) ((x)&0x03) +#define GPIO_DSCR_DEBUG_DSE(x) ((x)&0x03) /* Bit definitions and macros for GPIO_DSCR_CLKRST */ -#define GPIO_DSCR_CLKRST_DSE(x) ((x)&0x03) +#define GPIO_DSCR_CLKRST_DSE(x) ((x)&0x03) /* Bit definitions and macros for GPIO_DSCR_IRQ */ -#define GPIO_DSCR_IRQ_DSE(x) ((x)&0x03) +#define GPIO_DSCR_IRQ_DSE(x) ((x)&0x03) /* not done yet */ /********************************************************************* * LCD Controller (LCDC) *********************************************************************/ /* Bit definitions and macros for LCDC_LSSAR */ -#define LCDC_LSSAR_SSA(x) (((x)&0x3FFFFFFF)<<2) +#define LCDC_LSSAR_SSA(x) (((x)&0x3FFFFFFF)<<2) /* Bit definitions and macros for LCDC_LSR */ -#define LCDC_LSR_YMAX(x) (((x)&0x000003FF)<<0) -#define LCDC_LSR_XMAX(x) (((x)&0x0000003F)<<20) +#define LCDC_LSR_YMAX(x) (((x)&0x000003FF)<<0) +#define LCDC_LSR_XMAX(x) (((x)&0x0000003F)<<20) /* Bit definitions and macros for LCDC_LVPWR */ -#define LCDC_LVPWR_VPW(x) (((x)&0x000003FF)<<0) +#define LCDC_LVPWR_VPW(x) (((x)&0x000003FF)<<0) /* Bit definitions and macros for LCDC_LCPR */ -#define LCDC_LCPR_CYP(x) (((x)&0x000003FF)<<0) -#define LCDC_LCPR_CXP(x) (((x)&0x000003FF)<<16) -#define LCDC_LCPR_OP (0x10000000) -#define LCDC_LCPR_CC(x) (((x)&0x00000003)<<30) -#define LCDC_LCPR_CC_TRANSPARENT (0x00000000) -#define LCDC_LCPR_CC_OR (0x40000000) -#define LCDC_LCPR_CC_XOR (0x80000000) -#define LCDC_LCPR_CC_AND (0xC0000000) -#define LCDC_LCPR_OP_ON (0x10000000) -#define LCDC_LCPR_OP_OFF (0x00000000) +#define LCDC_LCPR_CYP(x) (((x)&0x000003FF)<<0) +#define LCDC_LCPR_CXP(x) (((x)&0x000003FF)<<16) +#define LCDC_LCPR_OP (0x10000000) +#define LCDC_LCPR_CC(x) (((x)&0x00000003)<<30) +#define LCDC_LCPR_CC_TRANSPARENT (0x00000000) +#define LCDC_LCPR_CC_OR (0x40000000) +#define LCDC_LCPR_CC_XOR (0x80000000) +#define LCDC_LCPR_CC_AND (0xC0000000) +#define LCDC_LCPR_OP_ON (0x10000000) +#define LCDC_LCPR_OP_OFF (0x00000000) /* Bit definitions and macros for LCDC_LCWHBR */ -#define LCDC_LCWHBR_BD(x) (((x)&0x000000FF)<<0) -#define LCDC_LCWHBR_CH(x) (((x)&0x0000001F)<<16) -#define LCDC_LCWHBR_CW(x) (((x)&0x0000001F)<<24) -#define LCDC_LCWHBR_BK_EN (0x80000000) -#define LCDC_LCWHBR_BK_EN_ON (0x80000000) -#define LCDC_LCWHBR_BK_EN_OFF (0x00000000) +#define LCDC_LCWHBR_BD(x) (((x)&0x000000FF)<<0) +#define LCDC_LCWHBR_CH(x) (((x)&0x0000001F)<<16) +#define LCDC_LCWHBR_CW(x) (((x)&0x0000001F)<<24) +#define LCDC_LCWHBR_BK_EN (0x80000000) +#define LCDC_LCWHBR_BK_EN_ON (0x80000000) +#define LCDC_LCWHBR_BK_EN_OFF (0x00000000) /* Bit definitions and macros for LCDC_LCCMR */ -#define LCDC_LCCMR_CUR_COL_B(x) (((x)&0x0000003F)<<0) -#define LCDC_LCCMR_CUR_COL_G(x) (((x)&0x0000003F)<<6) -#define LCDC_LCCMR_CUR_COL_R(x) (((x)&0x0000003F)<<12) +#define LCDC_LCCMR_CUR_COL_B(x) (((x)&0x0000003F)<<0) +#define LCDC_LCCMR_CUR_COL_G(x) (((x)&0x0000003F)<<6) +#define LCDC_LCCMR_CUR_COL_R(x) (((x)&0x0000003F)<<12) /* Bit definitions and macros for LCDC_LPCR */ -#define LCDC_LPCR_PCD(x) (((x)&0x0000003F)<<0) -#define LCDC_LPCR_SHARP (0x00000040) -#define LCDC_LPCR_SCLKSEL (0x00000080) -#define LCDC_LPCR_ACD(x) (((x)&0x0000007F)<<8) -#define LCDC_LPCR_ACDSEL (0x00008000) -#define LCDC_LPCR_REV_VS (0x00010000) -#define LCDC_LPCR_SWAP_SEL (0x00020000) -#define LCDC_LPCR_ENDSEL (0x00040000) -#define LCDC_LPCR_SCLKIDLE (0x00080000) -#define LCDC_LPCR_OEPOL (0x00100000) -#define LCDC_LPCR_CLKPOL (0x00200000) -#define LCDC_LPCR_LPPOL (0x00400000) -#define LCDC_LPCR_FLM (0x00800000) -#define LCDC_LPCR_PIXPOL (0x01000000) -#define LCDC_LPCR_BPIX(x) (((x)&0x00000007)<<25) -#define LCDC_LPCR_PBSIZ(x) (((x)&0x00000003)<<28) -#define LCDC_LPCR_COLOR (0x40000000) -#define LCDC_LPCR_TFT (0x80000000) -#define LCDC_LPCR_MODE_MONOCHROME (0x00000000) -#define LCDC_LPCR_MODE_CSTN (0x40000000) -#define LCDC_LPCR_MODE_TFT (0xC0000000) -#define LCDC_LPCR_PBSIZ_1 (0x00000000) -#define LCDC_LPCR_PBSIZ_2 (0x10000000) -#define LCDC_LPCR_PBSIZ_4 (0x20000000) -#define LCDC_LPCR_PBSIZ_8 (0x30000000) -#define LCDC_LPCR_BPIX_1bpp (0x00000000) -#define LCDC_LPCR_BPIX_2bpp (0x02000000) -#define LCDC_LPCR_BPIX_4bpp (0x04000000) -#define LCDC_LPCR_BPIX_8bpp (0x06000000) -#define LCDC_LPCR_BPIX_12bpp (0x08000000) -#define LCDC_LPCR_BPIX_16bpp (0x0A000000) -#define LCDC_LPCR_BPIX_18bpp (0x0C000000) +#define LCDC_LPCR_PCD(x) (((x)&0x0000003F)<<0) +#define LCDC_LPCR_SHARP (0x00000040) +#define LCDC_LPCR_SCLKSEL (0x00000080) +#define LCDC_LPCR_ACD(x) (((x)&0x0000007F)<<8) +#define LCDC_LPCR_ACDSEL (0x00008000) +#define LCDC_LPCR_REV_VS (0x00010000) +#define LCDC_LPCR_SWAP_SEL (0x00020000) +#define LCDC_LPCR_ENDSEL (0x00040000) +#define LCDC_LPCR_SCLKIDLE (0x00080000) +#define LCDC_LPCR_OEPOL (0x00100000) +#define LCDC_LPCR_CLKPOL (0x00200000) +#define LCDC_LPCR_LPPOL (0x00400000) +#define LCDC_LPCR_FLM (0x00800000) +#define LCDC_LPCR_PIXPOL (0x01000000) +#define LCDC_LPCR_BPIX(x) (((x)&0x00000007)<<25) +#define LCDC_LPCR_PBSIZ(x) (((x)&0x00000003)<<28) +#define LCDC_LPCR_COLOR (0x40000000) +#define LCDC_LPCR_TFT (0x80000000) +#define LCDC_LPCR_MODE_MONOCHROME (0x00000000) +#define LCDC_LPCR_MODE_CSTN (0x40000000) +#define LCDC_LPCR_MODE_TFT (0xC0000000) +#define LCDC_LPCR_PBSIZ_1 (0x00000000) +#define LCDC_LPCR_PBSIZ_2 (0x10000000) +#define LCDC_LPCR_PBSIZ_4 (0x20000000) +#define LCDC_LPCR_PBSIZ_8 (0x30000000) +#define LCDC_LPCR_BPIX_1bpp (0x00000000) +#define LCDC_LPCR_BPIX_2bpp (0x02000000) +#define LCDC_LPCR_BPIX_4bpp (0x04000000) +#define LCDC_LPCR_BPIX_8bpp (0x06000000) +#define LCDC_LPCR_BPIX_12bpp (0x08000000) +#define LCDC_LPCR_BPIX_16bpp (0x0A000000) +#define LCDC_LPCR_BPIX_18bpp (0x0C000000) -#define LCDC_LPCR_PANEL_TYPE(x) (((x)&0x00000003)<<30) +#define LCDC_LPCR_PANEL_TYPE(x) (((x)&0x00000003)<<30) /* Bit definitions and macros for LCDC_LHCR */ -#define LCDC_LHCR_H_WAIT_2(x) (((x)&0x000000FF)<<0) -#define LCDC_LHCR_H_WAIT_1(x) (((x)&0x000000FF)<<8) -#define LCDC_LHCR_H_WIDTH(x) (((x)&0x0000003F)<<26) +#define LCDC_LHCR_H_WAIT_2(x) (((x)&0x000000FF)<<0) +#define LCDC_LHCR_H_WAIT_1(x) (((x)&0x000000FF)<<8) +#define LCDC_LHCR_H_WIDTH(x) (((x)&0x0000003F)<<26) /* Bit definitions and macros for LCDC_LVCR */ -#define LCDC_LVCR_V_WAIT_2(x) (((x)&0x000000FF)<<0) -#define LCDC_LVCR_V_WAIT_1(x) (((x)&0x000000FF)<<8) -#define LCDC_LVCR_V_WIDTH(x) (((x)&0x0000003F)<<26) +#define LCDC_LVCR_V_WAIT_2(x) (((x)&0x000000FF)<<0) +#define LCDC_LVCR_V_WAIT_1(x) (((x)&0x000000FF)<<8) +#define LCDC_LVCR_V_WIDTH(x) (((x)&0x0000003F)<<26) /* Bit definitions and macros for LCDC_LPOR */ -#define LCDC_LPOR_POS(x) (((x)&0x0000001F)<<0) +#define LCDC_LPOR_POS(x) (((x)&0x0000001F)<<0) /* Bit definitions and macros for LCDC_LPCCR */ -#define LCDC_LPCCR_PW(x) (((x)&0x000000FF)<<0) -#define LCDC_LPCCR_CC_EN (0x00000100) -#define LCDC_LPCCR_SCR(x) (((x)&0x00000003)<<9) -#define LCDC_LPCCR_LDMSK (0x00008000) -#define LCDC_LPCCR_CLS_HI_WIDTH(x) (((x)&0x000001FF)<<16) -#define LCDC_LPCCR_SCR_LINEPULSE (0x00000000) -#define LCDC_LPCCR_SCR_PIXELCLK (0x00002000) -#define LCDC_LPCCR_SCR_LCDCLOCK (0x00004000) +#define LCDC_LPCCR_PW(x) (((x)&0x000000FF)<<0) +#define LCDC_LPCCR_CC_EN (0x00000100) +#define LCDC_LPCCR_SCR(x) (((x)&0x00000003)<<9) +#define LCDC_LPCCR_LDMSK (0x00008000) +#define LCDC_LPCCR_CLS_HI_WIDTH(x) (((x)&0x000001FF)<<16) +#define LCDC_LPCCR_SCR_LINEPULSE (0x00000000) +#define LCDC_LPCCR_SCR_PIXELCLK (0x00002000) +#define LCDC_LPCCR_SCR_LCDCLOCK (0x00004000) /* Bit definitions and macros for LCDC_LDCR */ -#define LCDC_LDCR_TM(x) (((x)&0x0000001F)<<0) -#define LCDC_LDCR_HM(x) (((x)&0x0000001F)<<16) -#define LCDC_LDCR_BURST (0x80000000) +#define LCDC_LDCR_TM(x) (((x)&0x0000001F)<<0) +#define LCDC_LDCR_HM(x) (((x)&0x0000001F)<<16) +#define LCDC_LDCR_BURST (0x80000000) /* Bit definitions and macros for LCDC_LRMCR */ -#define LCDC_LRMCR_SEL_REF (0x00000001) +#define LCDC_LRMCR_SEL_REF (0x00000001) /* Bit definitions and macros for LCDC_LICR */ -#define LCDC_LICR_INTCON (0x00000001) -#define LCDC_LICR_INTSYN (0x00000004) -#define LCDC_LICR_GW_INT_CON (0x00000010) +#define LCDC_LICR_INTCON (0x00000001) +#define LCDC_LICR_INTSYN (0x00000004) +#define LCDC_LICR_GW_INT_CON (0x00000010) /* Bit definitions and macros for LCDC_LIER */ -#define LCDC_LIER_BOF_EN (0x00000001) -#define LCDC_LIER_EOF_EN (0x00000002) -#define LCDC_LIER_ERR_RES_EN (0x00000004) -#define LCDC_LIER_UDR_ERR_EN (0x00000008) -#define LCDC_LIER_GW_BOF_EN (0x00000010) -#define LCDC_LIER_GW_EOF_EN (0x00000020) -#define LCDC_LIER_GW_ERR_RES_EN (0x00000040) -#define LCDC_LIER_GW_UDR_ERR_EN (0x00000080) +#define LCDC_LIER_BOF_EN (0x00000001) +#define LCDC_LIER_EOF_EN (0x00000002) +#define LCDC_LIER_ERR_RES_EN (0x00000004) +#define LCDC_LIER_UDR_ERR_EN (0x00000008) +#define LCDC_LIER_GW_BOF_EN (0x00000010) +#define LCDC_LIER_GW_EOF_EN (0x00000020) +#define LCDC_LIER_GW_ERR_RES_EN (0x00000040) +#define LCDC_LIER_GW_UDR_ERR_EN (0x00000080) /* Bit definitions and macros for LCDC_LISR */ -#define LCDC_LISR_BOF (0x00000001) -#define LCDC_LISR_EOF (0x00000002) -#define LCDC_LISR_ERR_RES (0x00000004) -#define LCDC_LISR_UDR_ERR (0x00000008) -#define LCDC_LISR_GW_BOF (0x00000010) -#define LCDC_LISR_GW_EOF (0x00000020) -#define LCDC_LISR_GW_ERR_RES (0x00000040) -#define LCDC_LISR_GW_UDR_ERR (0x00000080) +#define LCDC_LISR_BOF (0x00000001) +#define LCDC_LISR_EOF (0x00000002) +#define LCDC_LISR_ERR_RES (0x00000004) +#define LCDC_LISR_UDR_ERR (0x00000008) +#define LCDC_LISR_GW_BOF (0x00000010) +#define LCDC_LISR_GW_EOF (0x00000020) +#define LCDC_LISR_GW_ERR_RES (0x00000040) +#define LCDC_LISR_GW_UDR_ERR (0x00000080) /* Bit definitions and macros for LCDC_LGWSAR */ -#define LCDC_LGWSAR_GWSA(x) (((x)&0x3FFFFFFF)<<2) +#define LCDC_LGWSAR_GWSA(x) (((x)&0x3FFFFFFF)<<2) /* Bit definitions and macros for LCDC_LGWSR */ -#define LCDC_LGWSR_GWH(x) (((x)&0x000003FF)<<0) -#define LCDC_LGWSR_GWW(x) (((x)&0x0000003F)<<20) +#define LCDC_LGWSR_GWH(x) (((x)&0x000003FF)<<0) +#define LCDC_LGWSR_GWW(x) (((x)&0x0000003F)<<20) /* Bit definitions and macros for LCDC_LGWVPWR */ -#define LCDC_LGWVPWR_GWVPW(x) (((x)&0x000003FF)<<0) +#define LCDC_LGWVPWR_GWVPW(x) (((x)&0x000003FF)<<0) /* Bit definitions and macros for LCDC_LGWPOR */ -#define LCDC_LGWPOR_GWPO(x) (((x)&0x0000001F)<<0) +#define LCDC_LGWPOR_GWPO(x) (((x)&0x0000001F)<<0) /* Bit definitions and macros for LCDC_LGWPR */ -#define LCDC_LGWPR_GWYP(x) (((x)&0x000003FF)<<0) -#define LCDC_LGWPR_GWXP(x) (((x)&0x000003FF)<<16) +#define LCDC_LGWPR_GWYP(x) (((x)&0x000003FF)<<0) +#define LCDC_LGWPR_GWXP(x) (((x)&0x000003FF)<<16) /* Bit definitions and macros for LCDC_LGWCR */ -#define LCDC_LGWCR_GWCKB(x) (((x)&0x0000003F)<<0) -#define LCDC_LGWCR_GWCKG(x) (((x)&0x0000003F)<<6) -#define LCDC_LGWCR_GWCKR(x) (((x)&0x0000003F)<<12) -#define LCDC_LGWCR_GW_RVS (0x00200000) -#define LCDC_LGWCR_GWE (0x00400000) -#define LCDC_LGWCR_GWCKE (0x00800000) -#define LCDC_LGWCR_GWAV(x) (((x)&0x000000FF)<<24) +#define LCDC_LGWCR_GWCKB(x) (((x)&0x0000003F)<<0) +#define LCDC_LGWCR_GWCKG(x) (((x)&0x0000003F)<<6) +#define LCDC_LGWCR_GWCKR(x) (((x)&0x0000003F)<<12) +#define LCDC_LGWCR_GW_RVS (0x00200000) +#define LCDC_LGWCR_GWE (0x00400000) +#define LCDC_LGWCR_GWCKE (0x00800000) +#define LCDC_LGWCR_GWAV(x) (((x)&0x000000FF)<<24) /* Bit definitions and macros for LCDC_LGWDCR */ -#define LCDC_LGWDCR_GWTM(x) (((x)&0x0000001F)<<0) -#define LCDC_LGWDCR_GWHM(x) (((x)&0x0000001F)<<16) -#define LCDC_LGWDCR_GWBT (0x80000000) - -/* Bit definitions and macros for LCDC_BPLUT_BASE */ -#define LCDC_BPLUT_BASE_BASE(x) (((x)&0xFFFFFFFF)<<0) - -/* Bit definitions and macros for LCDC_GWLUT_BASE */ -#define LCDC_GWLUT_BASE_BASE(x) (((x)&0xFFFFFFFF)<<0) - -/* not done yet */ -/********************************************************************* -* USB Controller (USB) -*********************************************************************/ -/* Bit definitions and macros for USB_HCSPARAMS */ -#define USB_HCSPARAMS_N_PORTS(x) ((x)&0x0000000F) -#define USB_HCSPARAMS_PPC (0x00000010) -#define USB_HCSPARAMS_N_PCC(x) (((x)&0x0000000F)<<8) -#define USB_HCSPARAMS_N_CC(x) (((x)&0x0000000F)<<12) -#define USB_HCSPARAMS_PI (0x00010000) -#define USB_HCSPARAMS_N_PTT(x) (((x)&0x0000000F)<<20) -#define USB_HCSPARAMS_N_TT(x) (((x)&0x0000000F)<<24) - -/* Bit definitions and macros for USB_HCCPARAMS */ -#define USB_HCCPARAMS_ADC (0x00000001) -#define USB_HCCPARAMS_PFL (0x00000002) -#define USB_HCCPARAMS_ASP (0x00000004) -#define USB_HCCPARAMS_IST(x) (((x)&0x0000000F)<<4) -#define USB_HCCPARAMS_EECP(x) (((x)&0x000000FF)<<8) - -/* Bit definitions and macros for USB_DCIVERSION */ -#define USB_DCIVERSION_DCIVERSION(x) (((x)&0xFFFF)<<0) - -/* Bit definitions and macros for USB_DCCPARAMS */ -#define USB_DCCPARAMS_DEN(x) (((x)&0x0000001F)<<0) -#define USB_DCCPARAMS_DC (0x00000080) -#define USB_DCCPARAMS_HC (0x00000100) - -/* Bit definitions and macros for USB_USBCMD */ -#define USB_USBCMD_RS (0x00000001) -#define USB_USBCMD_RST (0x00000002) -#define USB_USBCMD_FS0 (0x00000004) -#define USB_USBCMD_FS1 (0x00000008) -#define USB_USBCMD_PSE (0x00000010) -#define USB_USBCMD_ASE (0x00000020) -#define USB_USBCMD_IAA (0x00000040) -#define USB_USBCMD_LR (0x00000080) -#define USB_USBCMD_ASP(x) (((x)&0x00000003)<<8) -#define USB_USBCMD_ASPE (0x00000800) -#define USB_USBCMD_SUTW (0x00002000) -#define USB_USBCMD_ATDTW (0x00004000) -#define USB_USBCMD_FS2 (0x00008000) -#define USB_USBCMD_ITC(x) (((x)&0x000000FF)<<16) -#define USB_USBCMD_ITC_IMM (0x00000000) -#define USB_USBCMD_ITC_1 (0x00010000) -#define USB_USBCMD_ITC_2 (0x00020000) -#define USB_USBCMD_ITC_4 (0x00040000) -#define USB_USBCMD_ITC_8 (0x00080000) -#define USB_USBCMD_ITC_16 (0x00100000) -#define USB_USBCMD_ITC_32 (0x00200000) -#define USB_USBCMD_ITC_40 (0x00400000) -#define USB_USBCMD_FS_1024 (0x00000000) -#define USB_USBCMD_FS_512 (0x00000004) -#define USB_USBCMD_FS_256 (0x00000008) -#define USB_USBCMD_FS_128 (0x0000000C) -#define USB_USBCMD_FS_64 (0x00008000) -#define USB_USBCMD_FS_32 (0x00008004) -#define USB_USBCMD_FS_16 (0x00008008) -#define USB_USBCMD_FS_8 (0x0000800C) - -/* Bit definitions and macros for USB_USBSTS */ -#define USB_USBSTS_UI (0x00000001) -#define USB_USBSTS_UEI (0x00000002) -#define USB_USBSTS_PCI (0x00000004) -#define USB_USBSTS_FRI (0x00000008) -#define USB_USBSTS_SEI (0x00000010) -#define USB_USBSTS_AAI (0x00000020) -#define USB_USBSTS_URI (0x00000040) -#define USB_USBSTS_SRI (0x00000080) -#define USB_USBSTS_SLI (0x00000100) -#define USB_USBSTS_HCH (0x00001000) -#define USB_USBSTS_RCL (0x00002000) -#define USB_USBSTS_PS (0x00004000) -#define USB_USBSTS_AS (0x00008000) - -/* Bit definitions and macros for USB_USBINTR */ -#define USB_USBINTR_UE (0x00000001) -#define USB_USBINTR_UEE (0x00000002) -#define USB_USBINTR_PCE (0x00000004) -#define USB_USBINTR_FRE (0x00000008) -#define USB_USBINTR_SEE (0x00000010) -#define USB_USBINTR_AAE (0x00000020) -#define USB_USBINTR_URE (0x00000040) -#define USB_USBINTR_SRE (0x00000080) -#define USB_USBINTR_SLE (0x00000100) - -/* Bit definitions and macros for USB_FRINDEX */ -#define USB_FRINDEX_FRINDEX(x) (((x)&0x00003FFF)<<0) - -/* Bit definitions and macros for USB_PERIODICLISTBASE */ -#define USB_PERIODICLISTBASE_PERBASE(x) (((x)&0x000FFFFF)<<12) - -/* Bit definitions and macros for USB_DEVICEADDR */ -#define USB_DEVICEADDR_USBADR(x) (((x)&0x0000007F)<<25) - -/* Bit definitions and macros for USB_ASYNCLISTADDR */ -#define USB_ASYNCLISTADDR_ASYBASE(x) (((x)&0x07FFFFFF)<<5) - -/* Bit definitions and macros for USB_EPLISTADDR */ -#define USB_EPLISTADDR_EPBASE(x) (((x)&0x001FFFFF)<<11) - -/* Bit definitions and macros for USB_ASNCTTSTS */ -#define USB_ASNCTTSTS_TTAS (0x00000001) -#define USB_ASNCTTSTS_TTAC (0x00000002) - -/* Bit definitions and macros for USB_BURSTSIZE */ -#define USB_BURSTSIZE_RXPBURST(x) (((x)&0x000000FF)<<0) -#define USB_BURSTSIZE_TXPBURST(x) (((x)&0x000000FF)<<8) - -/* Bit definitions and macros for USB_TXFILLTUNING */ -#define USB_TXFILLTUNING_TXSCHOH(x) (((x)&0x000000FF)<<0) -#define USB_TXFILLTUNING_TXSCHHEALTH(x) (((x)&0x0000001F)<<8) -#define USB_TXFILLTUNING_TXFIFOTHRES(x) (((x)&0x0000003F)<<16) - -/* Bit definitions and macros for USB_TXTTFILLTUNING */ -#define USB_TXTTFILLTUNING_TXTTSCHOH(x) (((x)&0x0000001F)<<0) -#define USB_TXTTFILLTUNING_TXTTSCHHEALTH(x) (((x)&0x0000001F)<<8) - -/* Bit definitions and macros for USB_ULPI_VIEWPORT */ -#define USB_ULPI_VIEWPORT_ULPI_DATWR(x) (((x)&0x000000FF)<<0) -#define USB_ULPI_VIEWPORT_ULPI_DATRD(x) (((x)&0x000000FF)<<8) -#define USB_ULPI_VIEWPORT_ULPI_ADDR(x) (((x)&0x000000FF)<<16) -#define USB_ULPI_VIEWPORT_ULPI_PORT(x) (((x)&0x00000007)<<24) -#define USB_ULPI_VIEWPORT_ULPI_SS (0x08000000) -#define USB_ULPI_VIEWPORT_ULPI_RW (0x20000000) -#define USB_ULPI_VIEWPORT_ULPI_RUN (0x40000000) -#define USB_ULPI_VIEWPORT_ULPI_WU (0x80000000) - -/* Bit definitions and macros for USB_CONFIGFLAG */ -#define USB_CONFIGFLAG_CONFIGFLAG(x) (((x)&0xFFFFFFFF)<<0) - -/* Bit definitions and macros for USB_PORTSC */ -#define USB_PORTSC_CCS (0x00000001) -#define USB_PORTSC_CSC (0x00000002) -#define USB_PORTSC_PE (0x00000004) -#define USB_PORTSC_PEC (0x00000008) -#define USB_PORTSC_OCA (0x00000010) -#define USB_PORTSC_OCC (0x00000020) -#define USB_PORTSC_FPR (0x00000040) -#define USB_PORTSC_SUSP (0x00000080) -#define USB_PORTSC_PR (0x00000100) -#define USB_PORTSC_LS(x) (((x)&0x00000003)<<10) -#define USB_PORTSC_PP (0x00001000) -#define USB_PORTSC_PO (0x00002000) -#define USB_PORTSC_PIC(x) (((x)&0x00000003)<<14) -#define USB_PORTSC_PTC(x) (((x)&0x0000000F)<<16) -#define USB_PORTSC_WLCN (0x00100000) -#define USB_PORTSC_WKDS (0x00200000) -#define USB_PORTSC_WKOC (0x00400000) -#define USB_PORTSC_PHCD (0x00800000) -#define USB_PORTSC_PFSC (0x01000000) -#define USB_PORTSC_PSPD(x) (((x)&0x00000003)<<26) -#define USB_PORTSC_PTS(x) (((x)&0x00000003)<<30) -#define USB_PORTSC_PTS_ULPI (0x80000000) -#define USB_PORTSC_PTS_FS_LS (0xC0000000) -#define USB_PORTSC_PSPD_FULL (0x00000000) -#define USB_PORTSC_PSPD_LOW (0x04000000) -#define USB_PORTSC_PSPD_HIGH (0x08000000) -#define USB_PORTSC_PTC_DISBALE (0x00000000) -#define USB_PORTSC_PTC_JSTATE (0x00010000) -#define USB_PORTSC_PTC_KSTATE (0x00020000) -#define USB_PORTSC_PTC_SEQ_NAK (0x00030000) -#define USB_PORTSC_PTC_PACKET (0x00040000) -#define USB_PORTSC_PTC_FORCE_ENABLE (0x00050000) -#define USB_PORTSC_PIC_OFF (0x00000000) -#define USB_PORTSC_PIC_AMBER (0x00004000) -#define USB_PORTSC_PIC_GREEN (0x00008000) -#define USB_PORTSC_LS_SE0 (0x00000000) -#define USB_PORTSC_LS_JSTATE (0x00000400) -#define USB_PORTSC_LS_KSTATE (0x00000800) - -/* Bit definitions and macros for USB_OTGSC */ -#define USB_OTGSC_VD (0x00000001) -#define USB_OTGSC_VC (0x00000002) -#define USB_OTGSC_OT (0x00000008) -#define USB_OTGSC_DP (0x00000010) -#define USB_OTGSC_ID (0x00000100) -#define USB_OTGSC_AVV (0x00000200) -#define USB_OTGSC_ASV (0x00000400) -#define USB_OTGSC_BSV (0x00000800) -#define USB_OTGSC_BSE (0x00001000) -#define USB_OTGSC_1MST (0x00002000) -#define USB_OTGSC_DPS (0x00004000) -#define USB_OTGSC_IDIS (0x00010000) -#define USB_OTGSC_AVVIS (0x00020000) -#define USB_OTGSC_ASVIS (0x00040000) -#define USB_OTGSC_BSVIS (0x00080000) -#define USB_OTGSC_BSEIS (0x00100000) -#define USB_OTGSC_1MSS (0x00200000) -#define USB_OTGSC_DPIS (0x00400000) -#define USB_OTGSC_IDIE (0x01000000) -#define USB_OTGSC_AVVIE (0x02000000) -#define USB_OTGSC_ASVIE (0x04000000) -#define USB_OTGSC_BSVIE (0x08000000) -#define USB_OTGSC_BSEIE (0x10000000) -#define USB_OTGSC_1MSE (0x20000000) -#define USB_OTGSC_DPIE (0x40000000) -#define USB_OTGSC_CLEAR (0x007F0000) -#define USB_OTGSC_ENABLE_ALL (0x7F000000) - -/* Bit definitions and macros for USB_USBMODE */ -#define USB_USBMODE_CM(x) (((x)&0x00000003)<<0) -#define USB_USBMODE_SLOM (0x00000008) -#define USB_USBMODE_SDIS (0x00000010) -#define USB_USBMODE_CM_IDLE (0x00000000) -#define USB_USBMODE_CM_DEVICE (0x00000002) -#define USB_USBMODE_CM_HOST (0x00000003) -#define USB_USBMODE_ES (0x00000004) - -/* Bit definitions and macros for USB_EPSETUPSR */ -#define USB_EPSETUPSR_EPSETUPSTAT(x) (((x)&0x0000003F)<<0) - -/* Bit definitions and macros for USB_EPPRIME */ -#define USB_EPPRIME_PERB(x) (((x)&0x0000003F)<<0) -#define USB_EPPRIME_PETB(x) (((x)&0x0000003F)<<16) -#define USB_EPPRIME_PETB0 (0x00010000) -#define USB_EPPRIME_PETB1 (0x00020000) -#define USB_EPPRIME_PETB2 (0x00040000) -#define USB_EPPRIME_PETB3 (0x00080000) -#define USB_EPPRIME_PETB4 (0x00100000) -#define USB_EPPRIME_PETB5 (0x00200000) -#define USB_EPPRIME_PERB0 (0x00000001) -#define USB_EPPRIME_PERB1 (0x00000002) -#define USB_EPPRIME_PERB2 (0x00000004) -#define USB_EPPRIME_PERB3 (0x00000008) -#define USB_EPPRIME_PERB4 (0x00000010) -#define USB_EPPRIME_PERB5 (0x00000020) - -/* Bit definitions and macros for USB_EPFLUSH */ -#define USB_EPFLUSH_FERB(x) (((x)&0x0000003F)<<0) -#define USB_EPFLUSH_FETB(x) (((x)&0x0000003F)<<16) -#define USB_EPFLUSH_FETB0 (0x00010000) -#define USB_EPFLUSH_FETB1 (0x00020000) -#define USB_EPFLUSH_FETB2 (0x00040000) -#define USB_EPFLUSH_FETB3 (0x00080000) -#define USB_EPFLUSH_FETB4 (0x00100000) -#define USB_EPFLUSH_FETB5 (0x00200000) -#define USB_EPFLUSH_FERB0 (0x00000001) -#define USB_EPFLUSH_FERB1 (0x00000002) -#define USB_EPFLUSH_FERB2 (0x00000004) -#define USB_EPFLUSH_FERB3 (0x00000008) -#define USB_EPFLUSH_FERB4 (0x00000010) -#define USB_EPFLUSH_FERB5 (0x00000020) - -/* Bit definitions and macros for USB_EPSR */ -#define USB_EPSR_ERBR(x) (((x)&0x0000003F)<<0) -#define USB_EPSR_ETBR(x) (((x)&0x0000003F)<<16) -#define USB_EPSR_ETBR0 (0x00010000) -#define USB_EPSR_ETBR1 (0x00020000) -#define USB_EPSR_ETBR2 (0x00040000) -#define USB_EPSR_ETBR3 (0x00080000) -#define USB_EPSR_ETBR4 (0x00100000) -#define USB_EPSR_ETBR5 (0x00200000) -#define USB_EPSR_ERBR0 (0x00000001) -#define USB_EPSR_ERBR1 (0x00000002) -#define USB_EPSR_ERBR2 (0x00000004) -#define USB_EPSR_ERBR3 (0x00000008) -#define USB_EPSR_ERBR4 (0x00000010) -#define USB_EPSR_ERBR5 (0x00000020) - -/* Bit definitions and macros for USB_EPCOMPLETE */ -#define USB_EPCOMPLETE_ERCE(x) (((x)&0x0000003F)<<0) -#define USB_EPCOMPLETE_ETCE(x) (((x)&0x0000003F)<<16) -#define USB_EPCOMPLETE_ETCE0 (0x00010000) -#define USB_EPCOMPLETE_ETCE1 (0x00020000) -#define USB_EPCOMPLETE_ETCE2 (0x00040000) -#define USB_EPCOMPLETE_ETCE3 (0x00080000) -#define USB_EPCOMPLETE_ETCE4 (0x00100000) -#define USB_EPCOMPLETE_ETCE5 (0x00200000) -#define USB_EPCOMPLETE_ERCE0 (0x00000001) -#define USB_EPCOMPLETE_ERCE1 (0x00000002) -#define USB_EPCOMPLETE_ERCE2 (0x00000004) -#define USB_EPCOMPLETE_ERCE3 (0x00000008) -#define USB_EPCOMPLETE_ERCE4 (0x00000010) -#define USB_EPCOMPLETE_ERCE5 (0x00000020) - -/* Bit definitions and macros for USB_EPCR0 */ -#define USB_EPCR0_RXS (0x00000001) -#define USB_EPCR0_RXT(x) (((x)&0x00000003)<<2) -#define USB_EPCR0_RXE (0x00000080) -#define USB_EPCR0_TXS (0x00010000) -#define USB_EPCR0_TXT(x) (((x)&0x00000003)<<18) -#define USB_EPCR0_TXE (0x00800000) - -/* Bit definitions and macros for USB_EPCR */ -#define USB_EPCR_RXS (0x00000001) -#define USB_EPCR_RXD (0x00000002) -#define USB_EPCR_RXT(x) (((x)&0x00000003)<<2) -#define USB_EPCR_RXI (0x00000020) -#define USB_EPCR_RXR (0x00000040) -#define USB_EPCR_RXE (0x00000080) -#define USB_EPCR_TXS (0x00010000) -#define USB_EPCR_TXD (0x00020000) -#define USB_EPCR_TXT(x) (((x)&0x00000003)<<18) -#define USB_EPCR_TXI (0x00200000) -#define USB_EPCR_TXR (0x00400000) -#define USB_EPCR_TXE (0x00800000) -#define USB_EPCR_TXT_CONTROL (0x00000000) -#define USB_EPCR_TXT_ISO (0x00040000) -#define USB_EPCR_TXT_BULK (0x00080000) -#define USB_EPCR_TXT_INT (0x000C0000) -#define USB_EPCR_RXT_CONTROL (0x00000000) -#define USB_EPCR_RXT_ISO (0x00000004) -#define USB_EPCR_RXT_BULK (0x00000008) -#define USB_EPCR_RXT_INT (0x0000000C) +#define LCDC_LGWDCR_GWTM(x) (((x)&0x0000001F)<<0) +#define LCDC_LGWDCR_GWHM(x) (((x)&0x0000001F)<<16) +#define LCDC_LGWDCR_GWBT (0x80000000) /********************************************************************* * SDRAM Controller (SDRAMC) *********************************************************************/ /* Bit definitions and macros for SDRAMC_SDMR */ -#define SDRAMC_SDMR_BNKAD_LEMR (0x40000000) -#define SDRAMC_SDMR_BNKAD_LMR (0x00000000) -#define SDRAMC_SDMR_AD(x) (((x)&0x00000FFF)<<18) -#define SDRAMC_SDMR_CMD (0x00010000) +#define SDRAMC_SDMR_BNKAD_LEMR (0x40000000) +#define SDRAMC_SDMR_BNKAD_LMR (0x00000000) +#define SDRAMC_SDMR_AD(x) (((x)&0x00000FFF)<<18) +#define SDRAMC_SDMR_CMD (0x00010000) /* Bit definitions and macros for SDRAMC_SDCR */ -#define SDRAMC_SDCR_MODE_EN (0x80000000) -#define SDRAMC_SDCR_CKE (0x40000000) -#define SDRAMC_SDCR_DDR (0x20000000) -#define SDRAMC_SDCR_REF (0x10000000) -#define SDRAMC_SDCR_MUX(x) (((x)&0x00000003)<<24) -#define SDRAMC_SDCR_OE_RULE (0x00400000) -#define SDRAMC_SDCR_RCNT(x) (((x)&0x0000003F)<<16) -#define SDRAMC_SDCR_PS_32 (0x00000000) -#define SDRAMC_SDCR_PS_16 (0x00002000) -#define SDRAMC_SDCR_DQS_OE(x) (((x)&0x0000000F)<<8) -#define SDRAMC_SDCR_IREF (0x00000004) -#define SDRAMC_SDCR_IPALL (0x00000002) +#define SDRAMC_SDCR_MODE_EN (0x80000000) +#define SDRAMC_SDCR_CKE (0x40000000) +#define SDRAMC_SDCR_DDR (0x20000000) +#define SDRAMC_SDCR_REF (0x10000000) +#define SDRAMC_SDCR_MUX(x) (((x)&0x00000003)<<24) +#define SDRAMC_SDCR_OE_RULE (0x00400000) +#define SDRAMC_SDCR_RCNT(x) (((x)&0x0000003F)<<16) +#define SDRAMC_SDCR_PS_32 (0x00000000) +#define SDRAMC_SDCR_PS_16 (0x00002000) +#define SDRAMC_SDCR_DQS_OE(x) (((x)&0x0000000F)<<8) +#define SDRAMC_SDCR_IREF (0x00000004) +#define SDRAMC_SDCR_IPALL (0x00000002) /* Bit definitions and macros for SDRAMC_SDCFG1 */ -#define SDRAMC_SDCFG1_SRD2RW(x) (((x)&0x0000000F)<<28) -#define SDRAMC_SDCFG1_SWT2RD(x) (((x)&0x00000007)<<24) -#define SDRAMC_SDCFG1_RDLAT(x) (((x)&0x0000000F)<<20) -#define SDRAMC_SDCFG1_ACT2RW(x) (((x)&0x00000007)<<16) -#define SDRAMC_SDCFG1_PRE2ACT(x) (((x)&0x00000007)<<12) -#define SDRAMC_SDCFG1_REF2ACT(x) (((x)&0x0000000F)<<8) -#define SDRAMC_SDCFG1_WTLAT(x) (((x)&0x00000007)<<4) +#define SDRAMC_SDCFG1_SRD2RW(x) (((x)&0x0000000F)<<28) +#define SDRAMC_SDCFG1_SWT2RD(x) (((x)&0x00000007)<<24) +#define SDRAMC_SDCFG1_RDLAT(x) (((x)&0x0000000F)<<20) +#define SDRAMC_SDCFG1_ACT2RW(x) (((x)&0x00000007)<<16) +#define SDRAMC_SDCFG1_PRE2ACT(x) (((x)&0x00000007)<<12) +#define SDRAMC_SDCFG1_REF2ACT(x) (((x)&0x0000000F)<<8) +#define SDRAMC_SDCFG1_WTLAT(x) (((x)&0x00000007)<<4) /* Bit definitions and macros for SDRAMC_SDCFG2 */ -#define SDRAMC_SDCFG2_BRD2PRE(x) (((x)&0x0000000F)<<28) -#define SDRAMC_SDCFG2_BWT2RW(x) (((x)&0x0000000F)<<24) -#define SDRAMC_SDCFG2_BRD2WT(x) (((x)&0x0000000F)<<20) -#define SDRAMC_SDCFG2_BL(x) (((x)&0x0000000F)<<16) +#define SDRAMC_SDCFG2_BRD2PRE(x) (((x)&0x0000000F)<<28) +#define SDRAMC_SDCFG2_BWT2RW(x) (((x)&0x0000000F)<<24) +#define SDRAMC_SDCFG2_BRD2WT(x) (((x)&0x0000000F)<<20) +#define SDRAMC_SDCFG2_BL(x) (((x)&0x0000000F)<<16) /* Bit definitions and macros for SDRAMC_SDDS */ -#define SDRAMC_SDDS_SB_E(x) (((x)&0x00000003)<<8) -#define SDRAMC_SDDS_SB_C(x) (((x)&0x00000003)<<6) -#define SDRAMC_SDDS_SB_A(x) (((x)&0x00000003)<<4) -#define SDRAMC_SDDS_SB_S(x) (((x)&0x00000003)<<2) -#define SDRAMC_SDDS_SB_D(x) ((x)&0x00000003) +#define SDRAMC_SDDS_SB_E(x) (((x)&0x00000003)<<8) +#define SDRAMC_SDDS_SB_C(x) (((x)&0x00000003)<<6) +#define SDRAMC_SDDS_SB_A(x) (((x)&0x00000003)<<4) +#define SDRAMC_SDDS_SB_S(x) (((x)&0x00000003)<<2) +#define SDRAMC_SDDS_SB_D(x) ((x)&0x00000003) /* Bit definitions and macros for SDRAMC_SDCS */ -#define SDRAMC_SDCS_BASE(x) (((x)&0x00000FFF)<<20) -#define SDRAMC_SDCS_CSSZ(x) ((x)&0x0000001F) -#define SDRAMC_SDCS_CSSZ_4GBYTE (0x0000001F) -#define SDRAMC_SDCS_CSSZ_2GBYTE (0x0000001E) -#define SDRAMC_SDCS_CSSZ_1GBYTE (0x0000001D) -#define SDRAMC_SDCS_CSSZ_512MBYTE (0x0000001C) -#define SDRAMC_SDCS_CSSZ_256MBYTE (0x0000001B) -#define SDRAMC_SDCS_CSSZ_128MBYTE (0x0000001A) -#define SDRAMC_SDCS_CSSZ_64MBYTE (0x00000019) -#define SDRAMC_SDCS_CSSZ_32MBYTE (0x00000018) -#define SDRAMC_SDCS_CSSZ_16MBYTE (0x00000017) -#define SDRAMC_SDCS_CSSZ_8MBYTE (0x00000016) -#define SDRAMC_SDCS_CSSZ_4MBYTE (0x00000015) -#define SDRAMC_SDCS_CSSZ_2MBYTE (0x00000014) -#define SDRAMC_SDCS_CSSZ_1MBYTE (0x00000013) -#define SDRAMC_SDCS_CSSZ_DIABLE (0x00000000) +#define SDRAMC_SDCS_BASE(x) (((x)&0x00000FFF)<<20) +#define SDRAMC_SDCS_CSSZ(x) ((x)&0x0000001F) +#define SDRAMC_SDCS_CSSZ_4GBYTE (0x0000001F) +#define SDRAMC_SDCS_CSSZ_2GBYTE (0x0000001E) +#define SDRAMC_SDCS_CSSZ_1GBYTE (0x0000001D) +#define SDRAMC_SDCS_CSSZ_512MBYTE (0x0000001C) +#define SDRAMC_SDCS_CSSZ_256MBYTE (0x0000001B) +#define SDRAMC_SDCS_CSSZ_128MBYTE (0x0000001A) +#define SDRAMC_SDCS_CSSZ_64MBYTE (0x00000019) +#define SDRAMC_SDCS_CSSZ_32MBYTE (0x00000018) +#define SDRAMC_SDCS_CSSZ_16MBYTE (0x00000017) +#define SDRAMC_SDCS_CSSZ_8MBYTE (0x00000016) +#define SDRAMC_SDCS_CSSZ_4MBYTE (0x00000015) +#define SDRAMC_SDCS_CSSZ_2MBYTE (0x00000014) +#define SDRAMC_SDCS_CSSZ_1MBYTE (0x00000013) +#define SDRAMC_SDCS_CSSZ_DIABLE (0x00000000) /********************************************************************* * Synchronous Serial Interface (SSI) *********************************************************************/ /* Bit definitions and macros for SSI_CR */ -#define SSI_CR_CIS (0x00000200) -#define SSI_CR_TCH (0x00000100) -#define SSI_CR_MCE (0x00000080) -#define SSI_CR_I2S_SLAVE (0x00000040) -#define SSI_CR_I2S_MASTER (0x00000020) -#define SSI_CR_I2S_NORMAL (0x00000000) -#define SSI_CR_SYN (0x00000010) -#define SSI_CR_NET (0x00000008) -#define SSI_CR_RE (0x00000004) -#define SSI_CR_TE (0x00000002) -#define SSI_CR_SSI_EN (0x00000001) +#define SSI_CR_CIS (0x00000200) +#define SSI_CR_TCH (0x00000100) +#define SSI_CR_MCE (0x00000080) +#define SSI_CR_I2S_SLAVE (0x00000040) +#define SSI_CR_I2S_MASTER (0x00000020) +#define SSI_CR_I2S_NORMAL (0x00000000) +#define SSI_CR_SYN (0x00000010) +#define SSI_CR_NET (0x00000008) +#define SSI_CR_RE (0x00000004) +#define SSI_CR_TE (0x00000002) +#define SSI_CR_SSI_EN (0x00000001) /* Bit definitions and macros for SSI_ISR */ -#define SSI_ISR_CMDAU (0x00040000) -#define SSI_ISR_CMDDU (0x00020000) -#define SSI_ISR_RXT (0x00010000) -#define SSI_ISR_RDR1 (0x00008000) -#define SSI_ISR_RDR0 (0x00004000) -#define SSI_ISR_TDE1 (0x00002000) -#define SSI_ISR_TDE0 (0x00001000) -#define SSI_ISR_ROE1 (0x00000800) -#define SSI_ISR_ROE0 (0x00000400) -#define SSI_ISR_TUE1 (0x00000200) -#define SSI_ISR_TUE0 (0x00000100) -#define SSI_ISR_TFS (0x00000080) -#define SSI_ISR_RFS (0x00000040) -#define SSI_ISR_TLS (0x00000020) -#define SSI_ISR_RLS (0x00000010) -#define SSI_ISR_RFF1 (0x00000008) -#define SSI_ISR_RFF0 (0x00000004) -#define SSI_ISR_TFE1 (0x00000002) -#define SSI_ISR_TFE0 (0x00000001) +#define SSI_ISR_CMDAU (0x00040000) +#define SSI_ISR_CMDDU (0x00020000) +#define SSI_ISR_RXT (0x00010000) +#define SSI_ISR_RDR1 (0x00008000) +#define SSI_ISR_RDR0 (0x00004000) +#define SSI_ISR_TDE1 (0x00002000) +#define SSI_ISR_TDE0 (0x00001000) +#define SSI_ISR_ROE1 (0x00000800) +#define SSI_ISR_ROE0 (0x00000400) +#define SSI_ISR_TUE1 (0x00000200) +#define SSI_ISR_TUE0 (0x00000100) +#define SSI_ISR_TFS (0x00000080) +#define SSI_ISR_RFS (0x00000040) +#define SSI_ISR_TLS (0x00000020) +#define SSI_ISR_RLS (0x00000010) +#define SSI_ISR_RFF1 (0x00000008) +#define SSI_ISR_RFF0 (0x00000004) +#define SSI_ISR_TFE1 (0x00000002) +#define SSI_ISR_TFE0 (0x00000001) /* Bit definitions and macros for SSI_IER */ -#define SSI_IER_RDMAE (0x00400000) -#define SSI_IER_RIE (0x00200000) -#define SSI_IER_TDMAE (0x00100000) -#define SSI_IER_TIE (0x00080000) -#define SSI_IER_CMDAU (0x00040000) -#define SSI_IER_CMDU (0x00020000) -#define SSI_IER_RXT (0x00010000) -#define SSI_IER_RDR1 (0x00008000) -#define SSI_IER_RDR0 (0x00004000) -#define SSI_IER_TDE1 (0x00002000) -#define SSI_IER_TDE0 (0x00001000) -#define SSI_IER_ROE1 (0x00000800) -#define SSI_IER_ROE0 (0x00000400) -#define SSI_IER_TUE1 (0x00000200) -#define SSI_IER_TUE0 (0x00000100) -#define SSI_IER_TFS (0x00000080) -#define SSI_IER_RFS (0x00000040) -#define SSI_IER_TLS (0x00000020) -#define SSI_IER_RLS (0x00000010) -#define SSI_IER_RFF1 (0x00000008) -#define SSI_IER_RFF0 (0x00000004) -#define SSI_IER_TFE1 (0x00000002) -#define SSI_IER_TFE0 (0x00000001) +#define SSI_IER_RDMAE (0x00400000) +#define SSI_IER_RIE (0x00200000) +#define SSI_IER_TDMAE (0x00100000) +#define SSI_IER_TIE (0x00080000) +#define SSI_IER_CMDAU (0x00040000) +#define SSI_IER_CMDU (0x00020000) +#define SSI_IER_RXT (0x00010000) +#define SSI_IER_RDR1 (0x00008000) +#define SSI_IER_RDR0 (0x00004000) +#define SSI_IER_TDE1 (0x00002000) +#define SSI_IER_TDE0 (0x00001000) +#define SSI_IER_ROE1 (0x00000800) +#define SSI_IER_ROE0 (0x00000400) +#define SSI_IER_TUE1 (0x00000200) +#define SSI_IER_TUE0 (0x00000100) +#define SSI_IER_TFS (0x00000080) +#define SSI_IER_RFS (0x00000040) +#define SSI_IER_TLS (0x00000020) +#define SSI_IER_RLS (0x00000010) +#define SSI_IER_RFF1 (0x00000008) +#define SSI_IER_RFF0 (0x00000004) +#define SSI_IER_TFE1 (0x00000002) +#define SSI_IER_TFE0 (0x00000001) /* Bit definitions and macros for SSI_TCR */ -#define SSI_TCR_TXBIT0 (0x00000200) -#define SSI_TCR_TFEN1 (0x00000100) -#define SSI_TCR_TFEN0 (0x00000080) -#define SSI_TCR_TFDIR (0x00000040) -#define SSI_TCR_TXDIR (0x00000020) -#define SSI_TCR_TSHFD (0x00000010) -#define SSI_TCR_TSCKP (0x00000008) -#define SSI_TCR_TFSI (0x00000004) -#define SSI_TCR_TFSL (0x00000002) -#define SSI_TCR_TEFS (0x00000001) +#define SSI_TCR_TXBIT0 (0x00000200) +#define SSI_TCR_TFEN1 (0x00000100) +#define SSI_TCR_TFEN0 (0x00000080) +#define SSI_TCR_TFDIR (0x00000040) +#define SSI_TCR_TXDIR (0x00000020) +#define SSI_TCR_TSHFD (0x00000010) +#define SSI_TCR_TSCKP (0x00000008) +#define SSI_TCR_TFSI (0x00000004) +#define SSI_TCR_TFSL (0x00000002) +#define SSI_TCR_TEFS (0x00000001) /* Bit definitions and macros for SSI_RCR */ -#define SSI_RCR_RXEXT (0x00000400) -#define SSI_RCR_RXBIT0 (0x00000200) -#define SSI_RCR_RFEN1 (0x00000100) -#define SSI_RCR_RFEN0 (0x00000080) -#define SSI_RCR_RSHFD (0x00000010) -#define SSI_RCR_RSCKP (0x00000008) -#define SSI_RCR_RFSI (0x00000004) -#define SSI_RCR_RFSL (0x00000002) -#define SSI_RCR_REFS (0x00000001) +#define SSI_RCR_RXEXT (0x00000400) +#define SSI_RCR_RXBIT0 (0x00000200) +#define SSI_RCR_RFEN1 (0x00000100) +#define SSI_RCR_RFEN0 (0x00000080) +#define SSI_RCR_RSHFD (0x00000010) +#define SSI_RCR_RSCKP (0x00000008) +#define SSI_RCR_RFSI (0x00000004) +#define SSI_RCR_RFSL (0x00000002) +#define SSI_RCR_REFS (0x00000001) /* Bit definitions and macros for SSI_CCR */ -#define SSI_CCR_DIV2 (0x00040000) -#define SSI_CCR_PSR (0x00020000) -#define SSI_CCR_WL(x) (((x)&0x0000000F)<<13) -#define SSI_CCR_DC(x) (((x)&0x0000001F)<<8) -#define SSI_CCR_PM(x) ((x)&0x000000FF) +#define SSI_CCR_DIV2 (0x00040000) +#define SSI_CCR_PSR (0x00020000) +#define SSI_CCR_WL(x) (((x)&0x0000000F)<<13) +#define SSI_CCR_DC(x) (((x)&0x0000001F)<<8) +#define SSI_CCR_PM(x) ((x)&0x000000FF) /* Bit definitions and macros for SSI_FCSR */ -#define SSI_FCSR_RFCNT1(x) (((x)&0x0000000F)<<28) -#define SSI_FCSR_TFCNT1(x) (((x)&0x0000000F)<<24) -#define SSI_FCSR_RFWM1(x) (((x)&0x0000000F)<<20) -#define SSI_FCSR_TFWM1(x) (((x)&0x0000000F)<<16) -#define SSI_FCSR_RFCNT0(x) (((x)&0x0000000F)<<12) -#define SSI_FCSR_TFCNT0(x) (((x)&0x0000000F)<<8) -#define SSI_FCSR_RFWM0(x) (((x)&0x0000000F)<<4) -#define SSI_FCSR_TFWM0(x) ((x)&0x0000000F) +#define SSI_FCSR_RFCNT1(x) (((x)&0x0000000F)<<28) +#define SSI_FCSR_TFCNT1(x) (((x)&0x0000000F)<<24) +#define SSI_FCSR_RFWM1(x) (((x)&0x0000000F)<<20) +#define SSI_FCSR_TFWM1(x) (((x)&0x0000000F)<<16) +#define SSI_FCSR_RFCNT0(x) (((x)&0x0000000F)<<12) +#define SSI_FCSR_TFCNT0(x) (((x)&0x0000000F)<<8) +#define SSI_FCSR_RFWM0(x) (((x)&0x0000000F)<<4) +#define SSI_FCSR_TFWM0(x) ((x)&0x0000000F) /* Bit definitions and macros for SSI_ACR */ -#define SSI_ACR_FRDIV(x) (((x)&0x0000003F)<<5) -#define SSI_ACR_WR (0x00000010) -#define SSI_ACR_RD (0x00000008) -#define SSI_ACR_TIF (0x00000004) -#define SSI_ACR_FV (0x00000002) -#define SSI_ACR_AC97EN (0x00000001) +#define SSI_ACR_FRDIV(x) (((x)&0x0000003F)<<5) +#define SSI_ACR_WR (0x00000010) +#define SSI_ACR_RD (0x00000008) +#define SSI_ACR_TIF (0x00000004) +#define SSI_ACR_FV (0x00000002) +#define SSI_ACR_AC97EN (0x00000001) /* Bit definitions and macros for SSI_ACADD */ -#define SSI_ACADD_SSI_ACADD(x) ((x)&0x0007FFFF) +#define SSI_ACADD_SSI_ACADD(x) ((x)&0x0007FFFF) /* Bit definitions and macros for SSI_ACDAT */ -#define SSI_ACDAT_SSI_ACDAT(x) ((x)&0x0007FFFF) +#define SSI_ACDAT_SSI_ACDAT(x) ((x)&0x0007FFFF) /* Bit definitions and macros for SSI_ATAG */ -#define SSI_ATAG_DDI_ATAG(x) ((x)&0x0000FFFF) +#define SSI_ATAG_DDI_ATAG(x) ((x)&0x0000FFFF) /********************************************************************* * Phase Locked Loop (PLL) *********************************************************************/ /* Bit definitions and macros for PLL_PODR */ -#define PLL_PODR_CPUDIV(x) (((x)&0x0F)<<4) -#define PLL_PODR_BUSDIV(x) ((x)&0x0F) +#define PLL_PODR_CPUDIV(x) (((x)&0x0F)<<4) +#define PLL_PODR_BUSDIV(x) ((x)&0x0F) /* Bit definitions and macros for PLL_PLLCR */ -#define PLL_PLLCR_DITHEN (0x80) -#define PLL_PLLCR_DITHDEV(x) ((x)&0x07) +#define PLL_PLLCR_DITHEN (0x80) +#define PLL_PLLCR_DITHDEV(x) ((x)&0x07) #endif /* mcf5329_h */ From f52e78304dcc0ac459c0ea1fa5be275c7d1642cf Mon Sep 17 00:00:00 2001 From: TsiChungLiew Date: Wed, 15 Aug 2007 18:46:11 -0500 Subject: [PATCH 155/259] ColdFire: MCF5329 update cache Signed-off-by: TsiChungLiew --- cpu/mcf532x/start.S | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/cpu/mcf532x/start.S b/cpu/mcf532x/start.S index ac44aaabe..5cc1c87cd 100644 --- a/cpu/mcf532x/start.S +++ b/cpu/mcf532x/start.S @@ -268,7 +268,7 @@ _int_handler: icache_enable: move.l #0x01000000, %d0 /* Invalidate cache cmd */ movec %d0, %CACR /* Invalidate cache */ - move.l #(CFG_SDRAM_BASE + 0xc000), %d0 /* Setup cache mask */ + move.l #(CFG_SDRAM_BASE + 0xc000 + ((CFG_SDRAM_SIZE & 0x1fe0) << 11)), %d0 movec %d0, %ACR0 /* Enable cache */ move.l #0x80000200, %d0 /* Setup cache mask */ From 83ec20bc4380eebddfde45da6e3a69a92d4db21d Mon Sep 17 00:00:00 2001 From: TsiChungLiew Date: Wed, 15 Aug 2007 19:21:21 -0500 Subject: [PATCH 156/259] ColdFire: MCF52x2 update Signed-off-by: TsiChungLiew --- cpu/mcf52x2/Makefile | 4 +- cpu/mcf52x2/cpu.c | 154 +++++----- cpu/mcf52x2/cpu_init.c | 380 +++++++++++++----------- cpu/mcf52x2/fec.c | 605 --------------------------------------- cpu/mcf52x2/interrupts.c | 185 +++--------- cpu/mcf52x2/serial.c | 215 -------------- cpu/mcf52x2/start.S | 48 +++- lib_m68k/time.c | 276 ------------------ 8 files changed, 369 insertions(+), 1498 deletions(-) delete mode 100644 cpu/mcf52x2/fec.c delete mode 100644 cpu/mcf52x2/serial.c diff --git a/cpu/mcf52x2/Makefile b/cpu/mcf52x2/Makefile index 70d57cf60..937cdd058 100644 --- a/cpu/mcf52x2/Makefile +++ b/cpu/mcf52x2/Makefile @@ -27,8 +27,8 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(CPU).a -START = -COBJS = serial.o interrupts.o cpu.o speed.o cpu_init.o fec.o +START = start.o +COBJS = interrupts.o cpu.o speed.o cpu_init.o SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) diff --git a/cpu/mcf52x2/cpu.c b/cpu/mcf52x2/cpu.c index ce59d39cf..96fe3711b 100644 --- a/cpu/mcf52x2/cpu.c +++ b/cpu/mcf52x2/cpu.c @@ -28,33 +28,15 @@ #include #include #include +#include #ifdef CONFIG_M5271 -#include -#include -#endif - -#ifdef CONFIG_M5272 -#include -#include -#endif - -#ifdef CONFIG_M5282 -#include -#include -#endif - -#ifdef CONFIG_M5249 -#include -#endif - -#ifdef CONFIG_M5271 /* * Both MCF5270 and MCF5271 are members of the MPC5271 family. Try to * determine which one we are running on, based on the Chip Identification * Register (CIR). */ -int checkcpu (void) +int checkcpu(void) { char buf[32]; unsigned short cir; /* Chip Identification Register */ @@ -80,156 +62,164 @@ int checkcpu (void) if (cpu_model) printf("CPU: Freescale ColdFire MCF%s rev. %hu, at %s MHz\n", - cpu_model, prn, strmhz(buf, CFG_CLK)); + cpu_model, prn, strmhz(buf, CFG_CLK)); else printf("CPU: Unknown - Freescale ColdFire MCF5271 family" - " (PIN: 0x%x) rev. %hu, at %s MHz\n", - pin, prn, strmhz(buf, CFG_CLK)); + " (PIN: 0x%x) rev. %hu, at %s MHz\n", + pin, prn, strmhz(buf, CFG_CLK)); return 0; } -int do_reset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]) { +int do_reset(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char *argv[]) +{ mbar_writeByte(MCF_RCM_RCR, - MCF_RCM_RCR_SOFTRST | MCF_RCM_RCR_FRCRSTOUT); + MCF_RCM_RCR_SOFTRST | MCF_RCM_RCR_FRCRSTOUT); return 0; }; #if defined(CONFIG_WATCHDOG) -void watchdog_reset (void) +void watchdog_reset(void) { mbar_writeShort(MCF_WTM_WSR, 0x5555); mbar_writeShort(MCF_WTM_WSR, 0xAAAA); } -int watchdog_disable (void) +int watchdog_disable(void) { mbar_writeShort(MCF_WTM_WCR, 0); return (0); } -int watchdog_init (void) +int watchdog_init(void) { mbar_writeShort(MCF_WTM_WCR, MCF_WTM_WCR_EN); return (0); } -#endif /* #ifdef CONFIG_WATCHDOG */ +#endif /* #ifdef CONFIG_WATCHDOG */ #endif #ifdef CONFIG_M5272 -int do_reset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]) { - volatile wdog_t * wdp = (wdog_t *)(CFG_MBAR + MCFSIM_WRRR); +int do_reset(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char *argv[]) +{ + volatile wdog_t *wdp = (wdog_t *) (MMAP_WDOG); wdp->wdog_wrrr = 0; - udelay (1000); + udelay(1000); /* enable watchdog, set timeout to 0 and wait */ wdp->wdog_wrrr = 1; - while (1); + while (1) ; /* we don't return! */ return 0; }; -int checkcpu(void) { - ulong *dirp = (ulong *)(CFG_MBAR + MCFSIM_DIR); +int checkcpu(void) +{ + volatile sysctrl_t *sysctrl = (sysctrl_t *) (MMAP_CFG); uchar msk; - char *suf; + char *suf; - puts ("CPU: "); - msk = (*dirp > 28) & 0xf; + puts("CPU: "); + msk = (sysctrl->sc_dir > 28) & 0xf; switch (msk) { - case 0x2: suf = "1K75N"; break; - case 0x4: suf = "3K75N"; break; - default: - suf = NULL; - printf ("Freescale MCF5272 (Mask:%01x)\n", msk); - break; - } + case 0x2: + suf = "1K75N"; + break; + case 0x4: + suf = "3K75N"; + break; + default: + suf = NULL; + printf("Freescale MCF5272 (Mask:%01x)\n", msk); + break; + } if (suf) - printf ("Freescale MCF5272 %s\n", suf); + printf("Freescale MCF5272 %s\n", suf); return 0; }; #if defined(CONFIG_WATCHDOG) /* Called by macro WATCHDOG_RESET */ -void watchdog_reset (void) +void watchdog_reset(void) { - volatile immap_t * regp = (volatile immap_t *)CFG_MBAR; - regp->wdog_reg.wdog_wcr = 0; + volatile wdog_t *wdt = (volatile wdog_t *)(MMAP_WDOG); + wdt->wdog_wcr = 0; } -int watchdog_disable (void) +int watchdog_disable(void) { - volatile immap_t *regp = (volatile immap_t *)CFG_MBAR; + volatile wdog_t *wdt = (volatile wdog_t *)(MMAP_WDOG); - regp->wdog_reg.wdog_wcr = 0; /* reset watchdog counter */ - regp->wdog_reg.wdog_wirr = 0; /* disable watchdog interrupt */ - regp->wdog_reg.wdog_wrrr = 0; /* disable watchdog timer */ + wdt->wdog_wcr = 0; /* reset watchdog counter */ + wdt->wdog_wirr = 0; /* disable watchdog interrupt */ + wdt->wdog_wrrr = 0; /* disable watchdog timer */ - puts ("WATCHDOG:disabled\n"); + puts("WATCHDOG:disabled\n"); return (0); } -int watchdog_init (void) +int watchdog_init(void) { - volatile immap_t *regp = (volatile immap_t *)CFG_MBAR; + volatile wdog_t *wdt = (volatile wdog_t *)(MMAP_WDOG); - regp->wdog_reg.wdog_wirr = 0; /* disable watchdog interrupt */ + wdt->wdog_wirr = 0; /* disable watchdog interrupt */ /* set timeout and enable watchdog */ - regp->wdog_reg.wdog_wrrr = ((CONFIG_WATCHDOG_TIMEOUT * CFG_HZ) / (32768 * 1000)) - 1; - regp->wdog_reg.wdog_wcr = 0; /* reset watchdog counter */ + wdt->wdog_wrrr = + ((CONFIG_WATCHDOG_TIMEOUT * CFG_HZ) / (32768 * 1000)) - 1; + wdt->wdog_wcr = 0; /* reset watchdog counter */ - puts ("WATCHDOG:enabled\n"); + puts("WATCHDOG:enabled\n"); return (0); } -#endif /* #ifdef CONFIG_WATCHDOG */ - -#endif /* #ifdef CONFIG_M5272 */ +#endif /* #ifdef CONFIG_WATCHDOG */ +#endif /* #ifdef CONFIG_M5272 */ #ifdef CONFIG_M5282 -int checkcpu (void) +int checkcpu(void) { unsigned char resetsource = MCFRESET_RSR; - printf ("CPU: Freescale Coldfire MCF5282 (PIN: %2.2x REV: %2.2x)\n", - MCFCCM_CIR>>8,MCFCCM_CIR & MCFCCM_CIR_PRN_MASK); - printf ("Reset:%s%s%s%s%s%s%s\n", - (resetsource & MCFRESET_RSR_LOL) ? " Loss of Lock" : "", - (resetsource & MCFRESET_RSR_LOC) ? " Loss of Clock" : "", - (resetsource & MCFRESET_RSR_EXT) ? " External" : "", - (resetsource & MCFRESET_RSR_POR) ? " Power On" : "", - (resetsource & MCFRESET_RSR_WDR) ? " Watchdog" : "", - (resetsource & MCFRESET_RSR_SOFT) ? " Software" : "", - (resetsource & MCFRESET_RSR_LVD) ? " Low Voltage" : "" - ); + printf("CPU: Freescale Coldfire MCF5282 (PIN: %2.2x REV: %2.2x)\n", + MCFCCM_CIR >> 8, MCFCCM_CIR & MCFCCM_CIR_PRN_MASK); + printf("Reset:%s%s%s%s%s%s%s\n", + (resetsource & MCFRESET_RSR_LOL) ? " Loss of Lock" : "", + (resetsource & MCFRESET_RSR_LOC) ? " Loss of Clock" : "", + (resetsource & MCFRESET_RSR_EXT) ? " External" : "", + (resetsource & MCFRESET_RSR_POR) ? " Power On" : "", + (resetsource & MCFRESET_RSR_WDR) ? " Watchdog" : "", + (resetsource & MCFRESET_RSR_SOFT) ? " Software" : "", + (resetsource & MCFRESET_RSR_LVD) ? " Low Voltage" : ""); return 0; } -int do_reset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]) +int do_reset(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char *argv[]) { MCFRESET_RCR = MCFRESET_RCR_SOFTRST; return 0; }; #endif -#ifdef CONFIG_M5249 /* test-only: todo... */ -int checkcpu (void) +#ifdef CONFIG_M5249 /* test-only: todo... */ +int checkcpu(void) { char buf[32]; - printf ("CPU: Freescale Coldfire MCF5249 at %s MHz\n", strmhz(buf, CFG_CLK)); + printf("CPU: Freescale Coldfire MCF5249 at %s MHz\n", + strmhz(buf, CFG_CLK)); return 0; } -int do_reset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]) { +int do_reset(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char *argv[]) +{ /* enable watchdog, set timeout to 0 and wait */ mbar_writeByte(MCFSIM_SYPCR, 0xc0); - while (1); + while (1) ; /* we don't return! */ return 0; diff --git a/cpu/mcf52x2/cpu_init.c b/cpu/mcf52x2/cpu_init.c index 1748ea9d9..5736d0f26 100644 --- a/cpu/mcf52x2/cpu_init.c +++ b/cpu/mcf52x2/cpu_init.c @@ -27,28 +27,10 @@ #include #include - -#ifdef CONFIG_M5271 -#include -#include -#endif - -#ifdef CONFIG_M5272 -#include -#include -#endif - -#ifdef CONFIG_M5282 -#include -#include -#endif - -#ifdef CONFIG_M5249 -#include -#endif +#include #if defined(CONFIG_M5271) -void cpu_init_f (void) +void cpu_init_f(void) { #ifndef CONFIG_WATCHDOG /* Disable the watchdog if we aren't using it */ @@ -58,25 +40,35 @@ void cpu_init_f (void) /* Set clockspeed to 100MHz */ mbar_writeShort(MCF_FMPLL_SYNCR, MCF_FMPLL_SYNCR_MFD(0) | MCF_FMPLL_SYNCR_RFD(0)); - while (!mbar_readByte(MCF_FMPLL_SYNSR) & MCF_FMPLL_SYNSR_LOCK); - - /* Enable UART pins */ - mbar_writeShort(MCF_GPIO_PAR_UART, MCF_GPIO_PAR_UART_U0TXD | - MCF_GPIO_PAR_UART_U0RXD | - MCF_GPIO_PAR_UART_U1RXD_UART1 | - MCF_GPIO_PAR_UART_U1TXD_UART1); - - /* Enable Ethernet pins */ - mbar_writeByte(MCF_GPIO_PAR_FECI2C, CFG_FECI2C); + while (!mbar_readByte(MCF_FMPLL_SYNSR) & MCF_FMPLL_SYNSR_LOCK) ; } /* * initialize higher level parts of CPU like timers */ -int cpu_init_r (void) +int cpu_init_r(void) { return (0); } + +void uart_port_conf(void) +{ + /* Setup Ports: */ + switch (CFG_UART_PORT) { + case 0: + mbar_writeShort(MCF_GPIO_PAR_UART, MCF_GPIO_PAR_UART_U0TXD | + MCF_GPIO_PAR_UART_U0RXD); + break; + case 1: + mbar_writeShort(MCF_GPIO_PAR_UART, + MCF_GPIO_PAR_UART_U1RXD_UART1 | + MCF_GPIO_PAR_UART_U1TXD_UART1); + break; + case 2: + mbar_writeShort(MCF_GPIO_PAR_UART, 0x3000); + break; + } +} #endif #if defined(CONFIG_M5272) @@ -87,69 +79,68 @@ int cpu_init_r (void) * initialize a bunch of registers, * initialize the UPM's */ -void cpu_init_f (void) +void cpu_init_f(void) { /* if we come from RAM we assume the CPU is * already initialized. */ #ifndef CONFIG_MONITOR_IS_IN_RAM - volatile immap_t *regp = (immap_t *)CFG_MBAR; + volatile sysctrl_t *sysctrl = (sysctrl_t *) (CFG_MBAR); + volatile gpio_t *gpio = (gpio_t *) (MMAP_GPIO); + volatile csctrl_t *csctrl = (csctrl_t *) (MMAP_FBCS); - volatile unsigned char *mbar; - mbar = (volatile unsigned char *) CFG_MBAR; - - regp->sysctrl_reg.sc_scr = CFG_SCR; - regp->sysctrl_reg.sc_spr = CFG_SPR; + sysctrl->sc_scr = CFG_SCR; + sysctrl->sc_spr = CFG_SPR; /* Setup Ports: */ - regp->gpio_reg.gpio_pacnt = CFG_PACNT; - regp->gpio_reg.gpio_paddr = CFG_PADDR; - regp->gpio_reg.gpio_padat = CFG_PADAT; - regp->gpio_reg.gpio_pbcnt = CFG_PBCNT; - regp->gpio_reg.gpio_pbddr = CFG_PBDDR; - regp->gpio_reg.gpio_pbdat = CFG_PBDAT; - regp->gpio_reg.gpio_pdcnt = CFG_PDCNT; + gpio->gpio_pacnt = CFG_PACNT; + gpio->gpio_paddr = CFG_PADDR; + gpio->gpio_padat = CFG_PADAT; + gpio->gpio_pbcnt = CFG_PBCNT; + gpio->gpio_pbddr = CFG_PBDDR; + gpio->gpio_pbdat = CFG_PBDAT; + gpio->gpio_pdcnt = CFG_PDCNT; /* Memory Controller: */ - regp->csctrl_reg.cs_br0 = CFG_BR0_PRELIM; - regp->csctrl_reg.cs_or0 = CFG_OR0_PRELIM; + csctrl->cs_br0 = CFG_BR0_PRELIM; + csctrl->cs_or0 = CFG_OR0_PRELIM; #if (defined(CFG_OR1_PRELIM) && defined(CFG_BR1_PRELIM)) - regp->csctrl_reg.cs_br1 = CFG_BR1_PRELIM; - regp->csctrl_reg.cs_or1 = CFG_OR1_PRELIM; + csctrl->cs_br1 = CFG_BR1_PRELIM; + csctrl->cs_or1 = CFG_OR1_PRELIM; #endif #if defined(CFG_OR2_PRELIM) && defined(CFG_BR2_PRELIM) - regp->csctrl_reg.cs_br2 = CFG_BR2_PRELIM; - regp->csctrl_reg.cs_or2 = CFG_OR2_PRELIM; + csctrl->cs_br2 = CFG_BR2_PRELIM; + csctrl->cs_or2 = CFG_OR2_PRELIM; #endif #if defined(CFG_OR3_PRELIM) && defined(CFG_BR3_PRELIM) - regp->csctrl_reg.cs_br3 = CFG_BR3_PRELIM; - regp->csctrl_reg.cs_or3 = CFG_OR3_PRELIM; + csctrl->cs_br3 = CFG_BR3_PRELIM; + csctrl->cs_or3 = CFG_OR3_PRELIM; #endif #if defined(CFG_OR4_PRELIM) && defined(CFG_BR4_PRELIM) - regp->csctrl_reg.cs_br4 = CFG_BR4_PRELIM; - regp->csctrl_reg.cs_or4 = CFG_OR4_PRELIM; + csctrl->cs_br4 = CFG_BR4_PRELIM; + csctrl->cs_or4 = CFG_OR4_PRELIM; #endif #if defined(CFG_OR5_PRELIM) && defined(CFG_BR5_PRELIM) - regp->csctrl_reg.cs_br5 = CFG_BR5_PRELIM; - regp->csctrl_reg.cs_or5 = CFG_OR5_PRELIM; + csctrl->cs_br5 = CFG_BR5_PRELIM; + csctrl->cs_or5 = CFG_OR5_PRELIM; #endif #if defined(CFG_OR6_PRELIM) && defined(CFG_BR6_PRELIM) - regp->csctrl_reg.cs_br6 = CFG_BR6_PRELIM; - regp->csctrl_reg.cs_or6 = CFG_OR6_PRELIM; + csctrl->cs_br6 = CFG_BR6_PRELIM; + csctrl->cs_or6 = CFG_OR6_PRELIM; #endif #if defined(CFG_OR7_PRELIM) && defined(CFG_BR7_PRELIM) - regp->csctrl_reg.cs_br7 = CFG_BR7_PRELIM; - regp->csctrl_reg.cs_or7 = CFG_OR7_PRELIM; + csctrl->cs_br7 = CFG_BR7_PRELIM; + csctrl->cs_or7 = CFG_OR7_PRELIM; #endif -#endif /* #ifndef CONFIG_MONITOR_IS_IN_RAM */ +#endif /* #ifndef CONFIG_MONITOR_IS_IN_RAM */ /* enable instruction cache now */ icache_enable(); @@ -159,14 +150,30 @@ void cpu_init_f (void) /* * initialize higher level parts of CPU like timers */ -int cpu_init_r (void) +int cpu_init_r(void) { return (0); } -#endif /* #if defined(CONFIG_M5272) */ +void uart_port_conf(void) +{ + volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; -#ifdef CONFIG_M5282 + /* Setup Ports: */ + switch (CFG_UART_PORT) { + case 0: + gpio->gpio_pbcnt &= ~(GPIO_PBCNT_PB0MSK | GPIO_PBCNT_PB1MSK); + gpio->gpio_pbcnt |= (GPIO_PBCNT_URT0_TXD | GPIO_PBCNT_URT0_RXD); + break; + case 1: + gpio->gpio_pdcnt &= ~(GPIO_PDCNT_PD1MSK | GPIO_PDCNT_PD4MSK); + gpio->gpio_pdcnt |= (GPIO_PDCNT_URT1_RXD | GPIO_PDCNT_URT1_TXD); + break; + } +} +#endif /* #if defined(CONFIG_M5272) */ + +#if defined(CONFIG_M5282) /* * Breath some life into the CPU... * @@ -174,7 +181,7 @@ int cpu_init_r (void) * initialize a bunch of registers, * initialize the UPM's */ -void cpu_init_f (void) +void cpu_init_f(void) { #ifndef CONFIG_WATCHDOG /* disable watchdog if we aren't using it */ @@ -183,7 +190,11 @@ void cpu_init_f (void) #ifndef CONFIG_MONITOR_IS_IN_RAM /* Set speed /PLL */ - MCFCLOCK_SYNCR = MCFCLOCK_SYNCR_MFD(CFG_MFD) | MCFCLOCK_SYNCR_RFD(CFG_RFD); + MCFCLOCK_SYNCR = + MCFCLOCK_SYNCR_MFD(CFG_MFD) | MCFCLOCK_SYNCR_RFD(CFG_RFD); + while (!(MCFCLOCK_SYNSR & MCFCLOCK_SYNSR_LOCK)) ; + + MCFGPIO_PBCDPAR = 0xc0; /* Set up the GPIO ports */ #ifdef CFG_PEPAR @@ -228,29 +239,28 @@ void cpu_init_f (void) defined(CFG_CS0_WIDTH) & defined(CFG_CS0_RO) & \ defined(CFG_CS0_WS) - MCFCSM_CSAR0 = (CFG_CS0_BASE >> 16) & 0xFFFF; + MCFCSM_CSAR0 = (CFG_CS0_BASE >> 16) & 0xFFFF; - #if (CFG_CS0_WIDTH == 8) - #define CFG_CS0_PS MCFCSM_CSCR_PS_8 - #elif (CFG_CS0_WIDTH == 16) - #define CFG_CS0_PS MCFCSM_CSCR_PS_16 - #elif (CFG_CS0_WIDTH == 32) - #define CFG_CS0_PS MCFCSM_CSCR_PS_32 - #else - #error "CFG_CS0_WIDTH: Fault - wrong bus with for CS0" - #endif - MCFCSM_CSCR0 = MCFCSM_CSCR_WS(CFG_CS0_WS) - |CFG_CS0_PS - |MCFCSM_CSCR_AA; - - #if (CFG_CS0_RO != 0) - MCFCSM_CSMR0 = MCFCSM_CSMR_BAM(CFG_CS0_SIZE-1) - |MCFCSM_CSMR_WP|MCFCSM_CSMR_V; - #else - MCFCSM_CSMR0 = MCFCSM_CSMR_BAM(CFG_CS0_SIZE-1)|MCFCSM_CSMR_V; - #endif +#if (CFG_CS0_WIDTH == 8) +#define CFG_CS0_PS MCFCSM_CSCR_PS_8 +#elif (CFG_CS0_WIDTH == 16) +#define CFG_CS0_PS MCFCSM_CSCR_PS_16 +#elif (CFG_CS0_WIDTH == 32) +#define CFG_CS0_PS MCFCSM_CSCR_PS_32 #else - #waring "Chip Select 0 are not initialized/used" +#error "CFG_CS0_WIDTH: Fault - wrong bus with for CS0" +#endif + MCFCSM_CSCR0 = MCFCSM_CSCR_WS(CFG_CS0_WS) + | CFG_CS0_PS | MCFCSM_CSCR_AA; + +#if (CFG_CS0_RO != 0) + MCFCSM_CSMR0 = MCFCSM_CSMR_BAM(CFG_CS0_SIZE - 1) + | MCFCSM_CSMR_WP | MCFCSM_CSMR_V; +#else + MCFCSM_CSMR0 = MCFCSM_CSMR_BAM(CFG_CS0_SIZE - 1) | MCFCSM_CSMR_V; +#endif +#else +#waring "Chip Select 0 are not initialized/used" #endif #if defined(CFG_CS1_BASE) & defined(CFG_CS1_SIZE) & \ @@ -259,29 +269,27 @@ void cpu_init_f (void) MCFCSM_CSAR1 = (CFG_CS1_BASE >> 16) & 0xFFFF; - #if (CFG_CS1_WIDTH == 8) - #define CFG_CS1_PS MCFCSM_CSCR_PS_8 - #elif (CFG_CS1_WIDTH == 16) - #define CFG_CS1_PS MCFCSM_CSCR_PS_16 - #elif (CFG_CS1_WIDTH == 32) - #define CFG_CS1_PS MCFCSM_CSCR_PS_32 - #else - #error "CFG_CS1_WIDTH: Fault - wrong bus with for CS1" - #endif - MCFCSM_CSCR1 = MCFCSM_CSCR_WS(CFG_CS1_WS) - |CFG_CS1_PS - |MCFCSM_CSCR_AA; - - #if (CFG_CS1_RO != 0) - MCFCSM_CSMR1 = MCFCSM_CSMR_BAM(CFG_CS1_SIZE-1) - |MCFCSM_CSMR_WP - |MCFCSM_CSMR_V; - #else - MCFCSM_CSMR1 = MCFCSM_CSMR_BAM(CFG_CS1_SIZE-1) - |MCFCSM_CSMR_V; - #endif +#if (CFG_CS1_WIDTH == 8) +#define CFG_CS1_PS MCFCSM_CSCR_PS_8 +#elif (CFG_CS1_WIDTH == 16) +#define CFG_CS1_PS MCFCSM_CSCR_PS_16 +#elif (CFG_CS1_WIDTH == 32) +#define CFG_CS1_PS MCFCSM_CSCR_PS_32 #else - #warning "Chip Select 1 are not initialized/used" +#error "CFG_CS1_WIDTH: Fault - wrong bus with for CS1" +#endif + MCFCSM_CSCR1 = MCFCSM_CSCR_WS(CFG_CS1_WS) + | CFG_CS1_PS | MCFCSM_CSCR_AA; + +#if (CFG_CS1_RO != 0) + MCFCSM_CSMR1 = MCFCSM_CSMR_BAM(CFG_CS1_SIZE - 1) + | MCFCSM_CSMR_WP | MCFCSM_CSMR_V; +#else + MCFCSM_CSMR1 = MCFCSM_CSMR_BAM(CFG_CS1_SIZE - 1) + | MCFCSM_CSMR_V; +#endif +#else +#warning "Chip Select 1 are not initialized/used" #endif #if defined(CFG_CS2_BASE) & defined(CFG_CS2_SIZE) & \ @@ -290,29 +298,27 @@ void cpu_init_f (void) MCFCSM_CSAR2 = (CFG_CS2_BASE >> 16) & 0xFFFF; - #if (CFG_CS2_WIDTH == 8) - #define CFG_CS2_PS MCFCSM_CSCR_PS_8 - #elif (CFG_CS2_WIDTH == 16) - #define CFG_CS2_PS MCFCSM_CSCR_PS_16 - #elif (CFG_CS2_WIDTH == 32) - #define CFG_CS2_PS MCFCSM_CSCR_PS_32 - #else - #error "CFG_CS2_WIDTH: Fault - wrong bus with for CS2" - #endif - MCFCSM_CSCR2 = MCFCSM_CSCR_WS(CFG_CS2_WS) - |CFG_CS2_PS - |MCFCSM_CSCR_AA; - - #if (CFG_CS2_RO != 0) - MCFCSM_CSMR2 = MCFCSM_CSMR_BAM(CFG_CS2_SIZE-1) - |MCFCSM_CSMR_WP - |MCFCSM_CSMR_V; - #else - MCFCSM_CSMR2 = MCFCSM_CSMR_BAM(CFG_CS2_SIZE-1) - |MCFCSM_CSMR_V; - #endif +#if (CFG_CS2_WIDTH == 8) +#define CFG_CS2_PS MCFCSM_CSCR_PS_8 +#elif (CFG_CS2_WIDTH == 16) +#define CFG_CS2_PS MCFCSM_CSCR_PS_16 +#elif (CFG_CS2_WIDTH == 32) +#define CFG_CS2_PS MCFCSM_CSCR_PS_32 #else - #warning "Chip Select 2 are not initialized/used" +#error "CFG_CS2_WIDTH: Fault - wrong bus with for CS2" +#endif + MCFCSM_CSCR2 = MCFCSM_CSCR_WS(CFG_CS2_WS) + | CFG_CS2_PS | MCFCSM_CSCR_AA; + +#if (CFG_CS2_RO != 0) + MCFCSM_CSMR2 = MCFCSM_CSMR_BAM(CFG_CS2_SIZE - 1) + | MCFCSM_CSMR_WP | MCFCSM_CSMR_V; +#else + MCFCSM_CSMR2 = MCFCSM_CSMR_BAM(CFG_CS2_SIZE - 1) + | MCFCSM_CSMR_V; +#endif +#else +#warning "Chip Select 2 are not initialized/used" #endif #if defined(CFG_CS3_BASE) & defined(CFG_CS3_SIZE) & \ @@ -321,32 +327,30 @@ void cpu_init_f (void) MCFCSM_CSAR3 = (CFG_CS3_BASE >> 16) & 0xFFFF; - #if (CFG_CS3_WIDTH == 8) - #define CFG_CS3_PS MCFCSM_CSCR_PS_8 - #elif (CFG_CS3_WIDTH == 16) - #define CFG_CS3_PS MCFCSM_CSCR_PS_16 - #elif (CFG_CS3_WIDTH == 32) - #define CFG_CS3_PS MCFCSM_CSCR_PS_32 - #else - #error "CFG_CS3_WIDTH: Fault - wrong bus with for CS1" - #endif - MCFCSM_CSCR3 = MCFCSM_CSCR_WS(CFG_CS3_WS) - |CFG_CS3_PS - |MCFCSM_CSCR_AA; - - #if (CFG_CS3_RO != 0) - MCFCSM_CSMR3 = MCFCSM_CSMR_BAM(CFG_CS3_SIZE-1) - |MCFCSM_CSMR_WP - |MCFCSM_CSMR_V; - #else - MCFCSM_CSMR3 = MCFCSM_CSMR_BAM(CFG_CS3_SIZE-1) - |MCFCSM_CSMR_V; - #endif +#if (CFG_CS3_WIDTH == 8) +#define CFG_CS3_PS MCFCSM_CSCR_PS_8 +#elif (CFG_CS3_WIDTH == 16) +#define CFG_CS3_PS MCFCSM_CSCR_PS_16 +#elif (CFG_CS3_WIDTH == 32) +#define CFG_CS3_PS MCFCSM_CSCR_PS_32 #else - #warning "Chip Select 3 are not initialized/used" +#error "CFG_CS3_WIDTH: Fault - wrong bus with for CS1" +#endif + MCFCSM_CSCR3 = MCFCSM_CSCR_WS(CFG_CS3_WS) + | CFG_CS3_PS | MCFCSM_CSCR_AA; + +#if (CFG_CS3_RO != 0) + MCFCSM_CSMR3 = MCFCSM_CSMR_BAM(CFG_CS3_SIZE - 1) + | MCFCSM_CSMR_WP | MCFCSM_CSMR_V; +#else + MCFCSM_CSMR3 = MCFCSM_CSMR_BAM(CFG_CS3_SIZE - 1) + | MCFCSM_CSMR_V; +#endif +#else +#warning "Chip Select 3 are not initialized/used" #endif -#endif /* CONFIG_MONITOR_IS_IN_RAM */ +#endif /* CONFIG_MONITOR_IS_IN_RAM */ /* defer enabling cache until boot (see do_go) */ /* icache_enable(); */ @@ -355,10 +359,29 @@ void cpu_init_f (void) /* * initialize higher level parts of CPU like timers */ -int cpu_init_r (void) +int cpu_init_r(void) { return (0); } + +void uart_port_conf(void) +{ + /* Setup Ports: */ + switch (CFG_UART_PORT) { + case 0: + MCFGPIO_PUAPAR &= 0xFc; + MCFGPIO_PUAPAR |= 0x03; + break; + case 1: + MCFGPIO_PUAPAR &= 0xF3; + MCFGPIO_PUAPAR |= 0x0C; + break; + case 2: + MCFGPIO_PASPAR &= 0xFF0F; + MCFGPIO_PASPAR |= 0x00A0; + break; + } +} #endif #if defined(CONFIG_M5249) @@ -369,7 +392,7 @@ int cpu_init_r (void) * initialize a bunch of registers, * initialize the UPM's */ -void cpu_init_f (void) +void cpu_init_f(void) { #ifndef CFG_PLL_BYPASS /* @@ -379,23 +402,23 @@ void cpu_init_f (void) volatile unsigned long cpll = mbar2_readLong(MCFSIM_PLLCR); unsigned long pllcr; #ifdef CFG_FAST_CLK - pllcr = 0x925a3100; /* ~140MHz clock (PLL bypass = 0) */ + pllcr = 0x925a3100; /* ~140MHz clock (PLL bypass = 0) */ #else - pllcr = 0x135a4140; /* ~72MHz clock (PLL bypass = 0) */ + pllcr = 0x135a4140; /* ~72MHz clock (PLL bypass = 0) */ #endif - cpll = cpll & 0xfffffffe; /* Set PLL bypass mode = 0 (PSTCLK = crystal) */ - mbar2_writeLong(MCFSIM_PLLCR, cpll); /* Set the PLL to bypass mode (PSTCLK = crystal) */ - mbar2_writeLong(MCFSIM_PLLCR, pllcr); /* set the clock speed */ - pllcr ^= 0x00000001; /* Set pll bypass to 1 */ - mbar2_writeLong(MCFSIM_PLLCR, pllcr); /* Start locking (pll bypass = 1) */ - udelay(0x20); /* Wait for a lock ... */ -#endif /* #ifndef CFG_PLL_BYPASS */ + cpll = cpll & 0xfffffffe; /* Set PLL bypass mode = 0 (PSTCLK = crystal) */ + mbar2_writeLong(MCFSIM_PLLCR, cpll); /* Set the PLL to bypass mode (PSTCLK = crystal) */ + mbar2_writeLong(MCFSIM_PLLCR, pllcr); /* set the clock speed */ + pllcr ^= 0x00000001; /* Set pll bypass to 1 */ + mbar2_writeLong(MCFSIM_PLLCR, pllcr); /* Start locking (pll bypass = 1) */ + udelay(0x20); /* Wait for a lock ... */ +#endif /* #ifndef CFG_PLL_BYPASS */ /* * NOTE: by setting the GPIO_FUNCTION registers, we ensure that the UART pins - * (UART0: gpio 30,27, UART1: gpio 31, 28) will be used as UART pins - * which is their primary function. - * ~Jeremy + * (UART0: gpio 30,27, UART1: gpio 31, 28) will be used as UART pins + * which is their primary function. + * ~Jeremy */ mbar2_writeLong(MCFSIM_GPIO_FUNC, CFG_GPIO_FUNC); mbar2_writeLong(MCFSIM_GPIO1_FUNC, CFG_GPIO1_FUNC); @@ -411,7 +434,7 @@ void cpu_init_f (void) * ~Jeremy * */ - mbar_writeByte(MCFSIM_MPARK, 0x30); /* 5249 Internal Core takes priority over DMA */ + mbar_writeByte(MCFSIM_MPARK, 0x30); /* 5249 Internal Core takes priority over DMA */ mbar_writeByte(MCFSIM_SYPCR, 0x00); mbar_writeByte(MCFSIM_SWIVR, 0x0f); mbar_writeByte(MCFSIM_SWSR, 0x00); @@ -431,7 +454,7 @@ void cpu_init_f (void) mbar2_writeLong(MCFSIM_GPIO_INT_EN, 0x00000080); mbar2_writeByte(MCFSIM_INTBASE, 0x40); /* Base interrupts at 64 */ mbar2_writeByte(MCFSIM_SPURVEC, 0x00); - mbar2_writeLong(MCFSIM_IDECONFIG1, 0x00000020); /* Enable a 1 cycle pre-drive cycle on CS1 */ + mbar2_writeLong(MCFSIM_IDECONFIG1, 0x00000020); /* Enable a 1 cycle pre-drive cycle on CS1 */ /* Setup interrupt priorities for gpio7 */ /* mbar2_writeLong(MCFSIM_INTLEV5, 0x70000000); */ @@ -459,8 +482,19 @@ void cpu_init_f (void) /* * initialize higher level parts of CPU like timers */ -int cpu_init_r (void) +int cpu_init_r(void) { return (0); } -#endif /* #if defined(CONFIG_M5249) */ + +void uart_port_conf(void) +{ + /* Setup Ports: */ + switch (CFG_UART_PORT) { + case 0: + break; + case 1: + break; + } +} +#endif /* #if defined(CONFIG_M5249) */ diff --git a/cpu/mcf52x2/fec.c b/cpu/mcf52x2/fec.c deleted file mode 100644 index ef9c7984c..000000000 --- a/cpu/mcf52x2/fec.c +++ /dev/null @@ -1,605 +0,0 @@ -/* - * (C) Copyright 2000-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include - -#ifdef CONFIG_M5271 -#include -#include -#endif - -#ifdef CONFIG_M5272 -#include -#include -#endif - -#ifdef CONFIG_M5282 -#include -#include -#endif - -#include -#include - -#ifdef CONFIG_M5272 -#define FEC_ADDR (CFG_MBAR + 0x840) -#endif -#if defined(CONFIG_M5282) || defined(CONFIG_M5271) -#define FEC_ADDR (CFG_MBAR + 0x1000) -#endif - -#undef ET_DEBUG -#undef MII_DEBUG - -#if defined(CONFIG_CMD_NET) && defined(FEC_ENET) - -#ifdef CFG_DISCOVER_PHY -#include -static void mii_discover_phy (void); -#endif - -/* Ethernet Transmit and Receive Buffers */ -#define DBUF_LENGTH 1520 - -#define TX_BUF_CNT 2 - -#define TOUT_LOOP 100 - -#define PKT_MAXBUF_SIZE 1518 -#define PKT_MINBUF_SIZE 64 -#define PKT_MAXBLR_SIZE 1520 - - -static char txbuf[DBUF_LENGTH]; - -static uint rxIdx; /* index of the current RX buffer */ -static uint txIdx; /* index of the current TX buffer */ - -/* - * FEC Ethernet Tx and Rx buffer descriptors allocated at the - * immr->udata_bd address on Dual-Port RAM - * Provide for Double Buffering - */ - -typedef volatile struct CommonBufferDescriptor { - cbd_t rxbd[PKTBUFSRX]; /* Rx BD */ - cbd_t txbd[TX_BUF_CNT]; /* Tx BD */ -} RTXBD; - -static RTXBD *rtx = NULL; - -int eth_send (volatile void *packet, int length) -{ - int j, rc; - volatile fec_t *fecp = (fec_t *) (FEC_ADDR); - - /* section 16.9.23.3 - * Wait for ready - */ - j = 0; - while ((rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY) - && (j < TOUT_LOOP)) { - udelay (1); - j++; - } - if (j >= TOUT_LOOP) { - printf ("TX not ready\n"); - } - - rtx->txbd[txIdx].cbd_bufaddr = (uint) packet; - rtx->txbd[txIdx].cbd_datlen = length; - rtx->txbd[txIdx].cbd_sc |= BD_ENET_TX_READY | BD_ENET_TX_LAST; - - /* Activate transmit Buffer Descriptor polling */ - fecp->fec_x_des_active = 0x01000000; /* Descriptor polling active */ - - j = 0; - while ((rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY) - && (j < TOUT_LOOP)) { - udelay (1); - j++; - } - if (j >= TOUT_LOOP) { - printf ("TX timeout\n"); - } -#ifdef ET_DEBUG - printf ("%s[%d] %s: cycles: %d status: %x retry cnt: %d\n", - __FILE__, __LINE__, __FUNCTION__, j, rtx->txbd[txIdx].cbd_sc, - (rtx->txbd[txIdx].cbd_sc & 0x003C) >> 2); -#endif - - /* return only status bits */ ; - rc = (rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_STATS); - - txIdx = (txIdx + 1) % TX_BUF_CNT; - - return rc; -} - -int eth_rx (void) -{ - int length; - volatile fec_t *fecp = (fec_t *) FEC_ADDR; - - for (;;) { - /* section 16.9.23.2 */ - if (rtx->rxbd[rxIdx].cbd_sc & BD_ENET_RX_EMPTY) { - length = -1; - break; /* nothing received - leave for() loop */ - } - - length = rtx->rxbd[rxIdx].cbd_datlen; - - if (rtx->rxbd[rxIdx].cbd_sc & 0x003f) { -#ifdef ET_DEBUG - printf ("%s[%d] err: %x\n", - __FUNCTION__, __LINE__, - rtx->rxbd[rxIdx].cbd_sc); -#endif - } else { - /* Pass the packet up to the protocol layers. */ - NetReceive (NetRxPackets[rxIdx], length - 4); - } - - /* Give the buffer back to the FEC. */ - rtx->rxbd[rxIdx].cbd_datlen = 0; - - /* wrap around buffer index when necessary */ - if ((rxIdx + 1) >= PKTBUFSRX) { - rtx->rxbd[PKTBUFSRX - 1].cbd_sc = - (BD_ENET_RX_WRAP | BD_ENET_RX_EMPTY); - rxIdx = 0; - } else { - rtx->rxbd[rxIdx].cbd_sc = BD_ENET_RX_EMPTY; - rxIdx++; - } - - /* Try to fill Buffer Descriptors */ - fecp->fec_r_des_active = 0x01000000; /* Descriptor polling active */ - } - - return length; -} - -/************************************************************** - * - * FEC Ethernet Initialization Routine - * - *************************************************************/ -#define FEC_ECNTRL_ETHER_EN 0x00000002 -#define FEC_ECNTRL_RESET 0x00000001 - -#define FEC_RCNTRL_BC_REJ 0x00000010 -#define FEC_RCNTRL_PROM 0x00000008 -#define FEC_RCNTRL_MII_MODE 0x00000004 -#define FEC_RCNTRL_DRT 0x00000002 -#define FEC_RCNTRL_LOOP 0x00000001 - -#define FEC_TCNTRL_FDEN 0x00000004 -#define FEC_TCNTRL_HBC 0x00000002 -#define FEC_TCNTRL_GTS 0x00000001 - -#define FEC_RESET_DELAY 50000 - -int eth_init (bd_t * bd) -{ -#ifndef CFG_ENET_BD_BASE - DECLARE_GLOBAL_DATA_PTR; -#endif - int i; - volatile fec_t *fecp = (fec_t *) (FEC_ADDR); - - /* Whack a reset. - * A delay is required between a reset of the FEC block and - * initialization of other FEC registers because the reset takes - * some time to complete. If you don't delay, subsequent writes - * to FEC registers might get killed by the reset routine which is - * still in progress. - */ - fecp->fec_ecntrl = FEC_ECNTRL_RESET; - for (i = 0; - (fecp->fec_ecntrl & FEC_ECNTRL_RESET) && (i < FEC_RESET_DELAY); - ++i) { - udelay (1); - } - if (i == FEC_RESET_DELAY) { - printf ("FEC_RESET_DELAY timeout\n"); - return 0; - } - - /* We use strictly polling mode only - */ - fecp->fec_imask = 0; - - /* Clear any pending interrupt */ - fecp->fec_ievent = 0xffffffff; - - /* Set station address */ -#define ea bd->bi_enetaddr - fecp->fec_addr_low = (ea[0] << 24) | (ea[1] << 16) | - (ea[2] << 8) | (ea[3]); - fecp->fec_addr_high = (ea[4] << 24) | (ea[5] << 16); -#ifdef ET_DEBUG - printf ("Eth Addrs: %02x:%02x:%02x:%02x:%02x:%02x\n", - ea[0], ea[1], ea[2], ea[3], ea[4], ea[5]); -#endif -#undef ea - -#ifdef CONFIG_M5271 - /* Clear multicast address hash table - */ - fecp->fec_ghash_table_high = 0; - fecp->fec_ghash_table_low = 0; - - /* Clear individual address hash table - */ - fecp->fec_ihash_table_high = 0; - fecp->fec_ihash_table_low = 0; -#else - /* Clear multicast address hash table - */ -#ifdef CONFIG_M5282 - fecp->fec_ihash_table_high = 0; - fecp->fec_ihash_table_low = 0; -#else - fecp->fec_hash_table_high = 0; - fecp->fec_hash_table_low = 0; -#endif -#endif - - /* Set maximum receive buffer size. - */ - fecp->fec_r_buff_size = PKT_MAXBLR_SIZE; - - /* - * Setup Buffers and Buffer Desriptors - */ - rxIdx = 0; - txIdx = 0; - - if (!rtx) { -#ifdef CFG_ENET_BD_BASE - rtx = (RTXBD *) CFG_ENET_BD_BASE; -#else - rtx = (RTXBD *) (CFG_MONITOR_BASE+gd->reloc_off - - (((PKTBUFSRX+TX_BUF_CNT)*+sizeof(cbd_t) - +0xFF) - & ~0xFF) - ); - debug("set ENET_DB_BASE to %lX\n",(long) rtx); -#endif - } - - /* - * Setup Receiver Buffer Descriptors (13.14.24.18) - * Settings: - * Empty, Wrap - */ - for (i = 0; i < PKTBUFSRX; i++) { - rtx->rxbd[i].cbd_sc = BD_ENET_RX_EMPTY; - rtx->rxbd[i].cbd_datlen = 0; /* Reset */ - rtx->rxbd[i].cbd_bufaddr = (uint) NetRxPackets[i]; - } - rtx->rxbd[PKTBUFSRX - 1].cbd_sc |= BD_ENET_RX_WRAP; - - /* - * Setup Ethernet Transmitter Buffer Descriptors (13.14.24.19) - * Settings: - * Last, Tx CRC - */ - for (i = 0; i < TX_BUF_CNT; i++) { - rtx->txbd[i].cbd_sc = BD_ENET_TX_LAST | BD_ENET_TX_TC; - rtx->txbd[i].cbd_datlen = 0; /* Reset */ - rtx->txbd[i].cbd_bufaddr = (uint) (&txbuf[0]); - } - rtx->txbd[TX_BUF_CNT - 1].cbd_sc |= BD_ENET_TX_WRAP; - - /* Set receive and transmit descriptor base - */ - fecp->fec_r_des_start = (unsigned int) (&rtx->rxbd[0]); - fecp->fec_x_des_start = (unsigned int) (&rtx->txbd[0]); - - /* Enable MII mode - */ - -#if 0 /* Full duplex mode */ - fecp->fec_r_cntrl = FEC_RCNTRL_MII_MODE; - fecp->fec_x_cntrl = FEC_TCNTRL_FDEN; -#else /* Half duplex mode */ - fecp->fec_r_cntrl = (PKT_MAXBUF_SIZE << 16); /* set max frame length */ - fecp->fec_r_cntrl |= FEC_RCNTRL_MII_MODE | FEC_RCNTRL_DRT; - fecp->fec_x_cntrl = 0; -#endif - /* Set MII speed */ - fecp->fec_mii_speed = (((CFG_CLK / 2) / (2500000 / 10)) + 5) / 10; - fecp->fec_mii_speed *= 2; - - /* Configure port B for MII. - */ - /* port initialization was already made in cpu_init_f() */ - - /* Now enable the transmit and receive processing - */ - fecp->fec_ecntrl = FEC_ECNTRL_ETHER_EN; - -#ifdef CFG_DISCOVER_PHY - /* wait for the PHY to wake up after reset */ - mii_discover_phy (); -#endif - - /* And last, try to fill Rx Buffer Descriptors */ - fecp->fec_r_des_active = 0x01000000; /* Descriptor polling active */ - - return 1; -} - -void eth_halt (void) -{ - volatile fec_t *fecp = (fec_t *) FEC_ADDR; - - fecp->fec_ecntrl = 0; -} - - -#if defined(CFG_DISCOVER_PHY) || defined(CONFIG_CMD_MII) - -static int phyaddr = -1; /* didn't find a PHY yet */ -static uint phytype; - -/* Make MII read/write commands for the FEC. -*/ - -#define mk_mii_read(ADDR, REG) (0x60020000 | ((ADDR << 23) | \ - (REG & 0x1f) << 18)) - -#define mk_mii_write(ADDR, REG, VAL) (0x50020000 | ((ADDR << 23) | \ - (REG & 0x1f) << 18) | \ - (VAL & 0xffff)) - -/* Interrupt events/masks. -*/ -#define FEC_ENET_HBERR ((uint)0x80000000) /* Heartbeat error */ -#define FEC_ENET_BABR ((uint)0x40000000) /* Babbling receiver */ -#define FEC_ENET_BABT ((uint)0x20000000) /* Babbling transmitter */ -#define FEC_ENET_GRA ((uint)0x10000000) /* Graceful stop complete */ -#define FEC_ENET_TXF ((uint)0x08000000) /* Full frame transmitted */ -#define FEC_ENET_TXB ((uint)0x04000000) /* A buffer was transmitted */ -#define FEC_ENET_RXF ((uint)0x02000000) /* Full frame received */ -#define FEC_ENET_RXB ((uint)0x01000000) /* A buffer was received */ -#define FEC_ENET_MII ((uint)0x00800000) /* MII interrupt */ -#define FEC_ENET_EBERR ((uint)0x00400000) /* SDMA bus error */ - -/* PHY identification - */ -#define PHY_ID_LXT970 0x78100000 /* LXT970 */ -#define PHY_ID_LXT971 0x001378e0 /* LXT971 and 972 */ -#define PHY_ID_82555 0x02a80150 /* Intel 82555 */ -#define PHY_ID_QS6612 0x01814400 /* QS6612 */ -#define PHY_ID_AMD79C784 0x00225610 /* AMD 79C784 */ -#define PHY_ID_LSI80225 0x0016f870 /* LSI 80225 */ -#define PHY_ID_LSI80225B 0x0016f880 /* LSI 80225/B */ - -/* send command to phy using mii, wait for result */ -static uint mii_send (uint mii_cmd) -{ - uint mii_reply; - volatile fec_t *ep = (fec_t *) (FEC_ADDR); - - ep->fec_mii_data = mii_cmd; /* command to phy */ - - /* wait for mii complete */ - while (!(ep->fec_ievent & FEC_ENET_MII)); /* spin until done */ - mii_reply = ep->fec_mii_data; /* result from phy */ - ep->fec_ievent = FEC_ENET_MII; /* clear MII complete */ -#ifdef ET_DEBUG - printf ("%s[%d] %s: sent=0x%8.8x, reply=0x%8.8x\n", - __FILE__, __LINE__, __FUNCTION__, mii_cmd, mii_reply); -#endif - return (mii_reply & 0xffff); /* data read from phy */ -} -#endif - -#if defined(CFG_DISCOVER_PHY) -static void mii_discover_phy (void) -{ -#define MAX_PHY_PASSES 11 - uint phyno; - int pass; - - phyaddr = -1; /* didn't find a PHY yet */ - for (pass = 1; pass <= MAX_PHY_PASSES && phyaddr < 0; ++pass) { - if (pass > 1) { - /* PHY may need more time to recover from reset. - * The LXT970 needs 50ms typical, no maximum is - * specified, so wait 10ms before try again. - * With 11 passes this gives it 100ms to wake up. - */ - udelay (10000); /* wait 10ms */ - } - for (phyno = 1; phyno < 32 && phyaddr < 0; ++phyno) { - phytype = mii_send (mk_mii_read (phyno, PHY_PHYIDR1)); -#ifdef ET_DEBUG - printf ("PHY type 0x%x pass %d type ", phytype, pass); -#endif - if (phytype != 0xffff) { - phyaddr = phyno; - phytype <<= 16; - phytype |= mii_send (mk_mii_read (phyno, - PHY_PHYIDR2)); - -#ifdef ET_DEBUG - printf ("PHY @ 0x%x pass %d type ", phyno, - pass); - switch (phytype & 0xfffffff0) { - case PHY_ID_LXT970: - printf ("LXT970\n"); - break; - case PHY_ID_LXT971: - printf ("LXT971\n"); - break; - case PHY_ID_82555: - printf ("82555\n"); - break; - case PHY_ID_QS6612: - printf ("QS6612\n"); - break; - case PHY_ID_AMD79C784: - printf ("AMD79C784\n"); - break; - case PHY_ID_LSI80225B: - printf ("LSI L80225/B\n"); - break; - default: - printf ("0x%08x\n", phytype); - break; - } -#endif - } - } - } - if (phyaddr < 0) { - printf ("No PHY device found.\n"); - } -} -#endif /* CFG_DISCOVER_PHY */ - -#if defined(CONFIG_CMD_MII) && !defined(CONFIG_BITBANGMII) - -static int mii_init_done = 0; - -/**************************************************************************** - * mii_init -- Initialize the MII for MII command without ethernet - * This function is a subset of eth_init - **************************************************************************** - */ -void mii_init (void) -{ - volatile fec_t *fecp = (fec_t *) (FEC_ADDR); - - int i; - - if (mii_init_done != 0) { - return; - } - - /* Whack a reset. - * A delay is required between a reset of the FEC block and - * initialization of other FEC registers because the reset takes - * some time to complete. If you don't delay, subsequent writes - * to FEC registers might get killed by the reset routine which is - * still in progress. - */ - - fecp->fec_ecntrl = FEC_ECNTRL_RESET; - for (i = 0; - (fecp->fec_ecntrl & FEC_ECNTRL_RESET) && (i < FEC_RESET_DELAY); - ++i) { - udelay (1); - } - if (i == FEC_RESET_DELAY) { - printf ("FEC_RESET_DELAY timeout\n"); - return; - } - - /* We use strictly polling mode only - */ - fecp->fec_imask = 0; - - /* Clear any pending interrupt - */ - fecp->fec_ievent = 0xffffffff; - - /* Set MII speed */ - fecp->fec_mii_speed = 0x0e; - - /* Configure port B for MII. - */ - /* port initialization was already made in cpu_init_f() */ - - /* Now enable the transmit and receive processing */ - fecp->fec_ecntrl = FEC_ECNTRL_ETHER_EN; - - mii_init_done = 1; -} - -/***************************************************************************** - * Read and write a MII PHY register, routines used by MII Utilities - * - * FIXME: These routines are expected to return 0 on success, but mii_send - * does _not_ return an error code. Maybe 0xFFFF means error, i.e. - * no PHY connected... - * For now always return 0. - * FIXME: These routines only work after calling eth_init() at least once! - * Otherwise they hang in mii_send() !!! Sorry! - *****************************************************************************/ - -int mcf52x2_miiphy_read (char *devname, unsigned char addr, - unsigned char reg, unsigned short *value) -{ - short rdreg; /* register working value */ - -#ifdef MII_DEBUG - printf ("miiphy_read(0x%x) @ 0x%x = ", reg, addr); -#endif - rdreg = mii_send (mk_mii_read (addr, reg)); - - *value = rdreg; - -#ifdef MII_DEBUG - printf ("0x%04x\n", *value); -#endif - - return 0; -} - -int mcf52x2_miiphy_write (char *devname, unsigned char addr, - unsigned char reg, unsigned short value) -{ - short rdreg; /* register working value */ - -#ifdef MII_DEBUG - printf ("miiphy_write(0x%x) @ 0x%x = ", reg, addr); -#endif - - rdreg = mii_send (mk_mii_write (addr, reg, value)); - -#ifdef MII_DEBUG - printf ("0x%04x\n", value); -#endif - - return 0; -} -#endif -#endif - -int mcf52x2_miiphy_initialize(bd_t *bis) -{ -#if defined(CONFIG_CMD_NET) && defined(FEC_ENET) -#if defined(CONFIG_CMD_MII) && !defined(CONFIG_BITBANGMII) - miiphy_register("mcf52x2phy", mcf52x2_miiphy_read, mcf52x2_miiphy_write); -#endif -#endif - return 0; -} diff --git a/cpu/mcf52x2/interrupts.c b/cpu/mcf52x2/interrupts.c index 116747ad3..d9a35bb8c 100644 --- a/cpu/mcf52x2/interrupts.c +++ b/cpu/mcf52x2/interrupts.c @@ -26,140 +26,12 @@ #include #include #include - -#ifdef CONFIG_M5271 -#include -#include -#endif +#include #ifdef CONFIG_M5272 -#include -#include -#endif - -#ifdef CONFIG_M5282 -#include -#include -#endif - -#ifdef CONFIG_M5249 -#include -#endif - - -#define NR_IRQS 31 - -/* - * Interrupt vector functions. - */ -struct interrupt_action { - interrupt_handler_t *handler; - void *arg; -}; - -static struct interrupt_action irq_vecs[NR_IRQS]; - -static __inline__ unsigned short get_sr (void) +int interrupt_init(void) { - unsigned short sr; - - asm volatile ("move.w %%sr,%0":"=r" (sr):); - - return sr; -} - -static __inline__ void set_sr (unsigned short sr) -{ - asm volatile ("move.w %0,%%sr"::"r" (sr)); -} - -/************************************************************************/ -/* - * Install and free an interrupt handler - */ -void irq_install_handler (int vec, interrupt_handler_t * handler, void *arg) -{ -#ifdef CONFIG_M5272 - volatile intctrl_t *intp = (intctrl_t *) (CFG_MBAR + MCFSIM_ICR1); -#endif - int vec_base = 0; - -#ifdef CONFIG_M5272 - vec_base = intp->int_pivr & 0xe0; -#endif - - if ((vec < vec_base) || (vec > vec_base + NR_IRQS)) { - printf ("irq_install_handler: wrong interrupt vector %d\n", - vec); - return; - } - - irq_vecs[vec - vec_base].handler = handler; - irq_vecs[vec - vec_base].arg = arg; -} - -void irq_free_handler (int vec) -{ -#ifdef CONFIG_M5272 - volatile intctrl_t *intp = (intctrl_t *) (CFG_MBAR + MCFSIM_ICR1); -#endif - int vec_base = 0; - -#ifdef CONFIG_M5272 - vec_base = intp->int_pivr & 0xe0; -#endif - - if ((vec < vec_base) || (vec > vec_base + NR_IRQS)) { - return; - } - - irq_vecs[vec - vec_base].handler = NULL; - irq_vecs[vec - vec_base].arg = NULL; -} - -void enable_interrupts (void) -{ - unsigned short sr; - - sr = get_sr (); - set_sr (sr & ~0x0700); -} - -int disable_interrupts (void) -{ - unsigned short sr; - - sr = get_sr (); - set_sr (sr | 0x0700); - - return ((sr & 0x0700) == 0); /* return TRUE, if interrupts were enabled before */ -} - -void int_handler (struct pt_regs *fp) -{ -#ifdef CONFIG_M5272 - volatile intctrl_t *intp = (intctrl_t *) (CFG_MBAR + MCFSIM_ICR1); -#endif - int vec, vec_base = 0; - - vec = (fp->vector >> 2) & 0xff; -#ifdef CONFIG_M5272 - vec_base = intp->int_pivr & 0xe0; -#endif - - if (irq_vecs[vec - vec_base].handler != NULL) { - irq_vecs[vec - - vec_base].handler (irq_vecs[vec - vec_base].arg); - } else { - printf ("\nBogus External Interrupt Vector %d\n", vec); - } -} - - -#ifdef CONFIG_M5272 -int interrupt_init (void) -{ - volatile intctrl_t *intp = (intctrl_t *) (CFG_MBAR + MCFSIM_ICR1); + volatile intctrl_t *intp = (intctrl_t *) (MMAP_INTC); /* disable all external interrupts */ intp->int_icr1 = 0x88888888; @@ -170,24 +42,61 @@ int interrupt_init (void) /* initialize vector register */ intp->int_pivr = 0x40; - enable_interrupts (); + enable_interrupts(); return 0; } -#endif + +#if defined(CONFIG_MCFTMR) +void dtimer_intr_setup(void) +{ + volatile intctrl_t *intp = (intctrl_t *) (CFG_INTR_BASE); + + intp->int_icr1 &= ~INT_ICR1_TMR3MASK; + intp->int_icr1 |= CFG_TMRINTR_PRI; +} +#endif /* CONFIG_MCFTMR */ +#endif /* CONFIG_M5272 */ #if defined(CONFIG_M5282) || defined(CONFIG_M5271) -int interrupt_init (void) +int interrupt_init(void) { + volatile int0_t *intp = (int0_t *) (CFG_INTR_BASE); + + /* Make sure all interrupts are disabled */ + intp->imrl0 |= 0x1; + + enable_interrupts(); return 0; } -#endif + +#if defined(CONFIG_MCFTMR) +void dtimer_intr_setup(void) +{ + volatile int0_t *intp = (int0_t *) (CFG_INTR_BASE); + + intp->icr0[CFG_TMRINTR_NO] = CFG_TMRINTR_PRI; + intp->imrl0 &= ~0xFFFFFFFE; + intp->imrl0 &= ~CFG_TMRINTR_MASK; +} +#endif /* CONFIG_MCFTMR */ +#endif /* CONFIG_M5282 | CONFIG_M5271 */ #ifdef CONFIG_M5249 -int interrupt_init (void) +int interrupt_init(void) { - enable_interrupts (); + enable_interrupts(); return 0; } -#endif + +#if defined(CONFIG_MCFTMR) +void dtimer_intr_setup(void) +{ + mbar_writeLong(MCFSIM_IMR, mbar_readLong(MCFSIM_IMR) & ~0x00000400); + mbar_writeByte(MCFSIM_TIMER2ICR, + MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL7 | + MCFSIM_ICR_PRI3); +} +#endif /* CONFIG_MCFTMR */ +#endif /* CONFIG_M5249 */ diff --git a/cpu/mcf52x2/serial.c b/cpu/mcf52x2/serial.c deleted file mode 100644 index 8be09e34f..000000000 --- a/cpu/mcf52x2/serial.c +++ /dev/null @@ -1,215 +0,0 @@ -/* - * (C) Copyright 2000-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include - -#include - -#ifdef CONFIG_M5271 -#include -#endif - -#ifdef CONFIG_M5272 -#include -#endif - -#ifdef CONFIG_M5282 -#include -#endif - -#ifdef CONFIG_M5249 -#include -#endif - -DECLARE_GLOBAL_DATA_PTR; - -#if defined(CONFIG_M5249) || defined(CONFIG_M5271) -#define DoubleClock(a) ((double)(CFG_CLK/2) / 32.0 / (double)(a)) -#else -#define DoubleClock(a) ((double)(CFG_CLK) / 32.0 / (double)(a)) -#endif - -void rs_serial_setbaudrate(int port,int baudrate) -{ -#if defined(CONFIG_M5272) || defined(CONFIG_M5249) || defined(CONFIG_M5271) - volatile unsigned char *uartp; -# ifndef CONFIG_M5271 - double fraction; -# endif - double clock; - - if (port == 0) - uartp = (volatile unsigned char *) (CFG_MBAR + MCFUART_BASE1); - else - uartp = (volatile unsigned char *) (CFG_MBAR + MCFUART_BASE2); - - clock = DoubleClock(baudrate); /* Set baud above */ - - uartp[MCFUART_UBG1] = (((int)clock >> 8) & 0xff); /* set msb baud */ - uartp[MCFUART_UBG2] = ((int)clock & 0xff); /* set lsb baud */ - -# ifndef CONFIG_M5271 - fraction = ((clock - (int)clock) * 16.0) + 0.5; - uartp[MCFUART_UFPD] = ((int)fraction & 0xf); /* set baud fraction adjust */ -# endif -#endif - -#if defined(CONFIG_M5282) - volatile unsigned char *uartp; - long clock; - - switch (port) { - case 1: - uartp = (volatile unsigned char *) (CFG_MBAR + MCFUART_BASE2); - break; - case 2: - uartp = (volatile unsigned char *) (CFG_MBAR + MCFUART_BASE3); - break; - default: - uartp = (volatile unsigned char *) (CFG_MBAR + MCFUART_BASE1); - } - - clock = (long) CFG_CLK / ((long) 32 * baudrate); /* Set baud above */ - - uartp[MCFUART_UBG1] = (((int)clock >> 8) & 0xff); /* set msb baud */ - uartp[MCFUART_UBG2] = ((int) clock & 0xff); /* set lsb baud */ - -#endif -}; - -void rs_serial_init (int port, int baudrate) -{ - volatile unsigned char *uartp; - - /* - * Reset UART, get it into known state... - */ - switch (port) { - case 1: - uartp = (volatile unsigned char *) (CFG_MBAR + MCFUART_BASE2); - break; -#if defined(CONFIG_M5282) - case 2: - uartp = (volatile unsigned char *) (CFG_MBAR + MCFUART_BASE3); - break; -#endif - default: - uartp = (volatile unsigned char *) (CFG_MBAR + MCFUART_BASE1); - } - - uartp[MCFUART_UCR] = MCFUART_UCR_CMDRESETTX; /* reset TX */ - uartp[MCFUART_UCR] = MCFUART_UCR_CMDRESETRX; /* reset RX */ - - uartp[MCFUART_UCR] = MCFUART_UCR_CMDRESETMRPTR; /* reset MR pointer */ - uartp[MCFUART_UCR] = MCFUART_UCR_CMDRESETERR; /* reset Error pointer */ - - /* - * Set port for CONSOLE_BAUD_RATE, 8 data bits, 1 stop bit, no parity. - */ - uartp[MCFUART_UMR] = MCFUART_MR1_PARITYNONE | MCFUART_MR1_CS8; - uartp[MCFUART_UMR] = MCFUART_MR2_STOP1; - - /* Mask UART interrupts */ - uartp[MCFUART_UIMR] = 0; - - /* Set clock Select Register: Tx/Rx clock is timer */ - uartp[MCFUART_UCSR] = MCFUART_UCSR_RXCLKTIMER | MCFUART_UCSR_TXCLKTIMER; - - rs_serial_setbaudrate (port, baudrate); - - /* Enable Tx/Rx */ - uartp[MCFUART_UCR] = MCFUART_UCR_RXENABLE | MCFUART_UCR_TXENABLE; - - return; -} - -/****************************************************************************/ -/* - * Output a single character, using UART polled mode. - * This is used for console output. - */ - -void rs_put_char(char ch) -{ - volatile unsigned char *uartp; - int i; - - uartp = (volatile unsigned char *) (CFG_MBAR + MCFUART_BASE1); - - for (i = 0; (i < 0x10000); i++) { - if (uartp[MCFUART_USR] & MCFUART_USR_TXREADY) - break; - } - uartp[MCFUART_UTB] = ch; - return; -} - -int rs_is_char(void) -{ - volatile unsigned char *uartp; - - uartp = (volatile unsigned char *) (CFG_MBAR + MCFUART_BASE1); - return((uartp[MCFUART_USR] & MCFUART_USR_RXREADY) ? 1 : 0); -} - -int rs_get_char(void) -{ - volatile unsigned char *uartp; - - uartp = (volatile unsigned char *) (CFG_MBAR + MCFUART_BASE1); - return(uartp[MCFUART_URB]); -} - -void serial_setbrg(void) { - rs_serial_setbaudrate(0,gd->bd->bi_baudrate); -} - -int serial_init(void) { - rs_serial_init(0,gd->baudrate); - return 0; -} - - -void serial_putc(const char c) { - if (c == '\n') - serial_putc ('\r'); - rs_put_char(c); -} - -void serial_puts (const char *s) { - while (*s) - serial_putc(*s++); -} - -int serial_getc(void) { - while(!rs_is_char()) - WATCHDOG_RESET(); - - return rs_get_char(); -} - -int serial_tstc() { - return rs_is_char(); -} diff --git a/cpu/mcf52x2/start.S b/cpu/mcf52x2/start.S index 7c9a7d2d2..6783d4d94 100644 --- a/cpu/mcf52x2/start.S +++ b/cpu/mcf52x2/start.S @@ -159,7 +159,7 @@ _copy_flash: _flashbar_setup: /* Initialize FLASHBAR: locate internal Flash and validate it */ - move.l #(CFG_INT_FLASH_BASE + 0x21), %d0 + move.l #(CFG_INT_FLASH_BASE + CFG_INT_FLASH_ENABLE), %d0 movec %d0, %RAMBAR0 jmp _after_flashbar_copy.L /* Force jump to absolute address */ _flashbar_setup_end: @@ -167,7 +167,7 @@ _flashbar_setup_end: _after_flashbar_copy: #else /* Setup code to initialize FLASHBAR, if start from external Memory */ - move.l #(CFG_INT_FLASH_BASE + 0x21), %d0 + move.l #(CFG_INT_FLASH_BASE + CFG_INT_FLASH_ENABLE), %d0 movec %d0, %RAMBAR0 #endif /* (TEXT_BASE == CFG_INT_FLASH_BASE) */ @@ -326,10 +326,10 @@ clear_bss: /* set parameters for board_init_r */ move.l %a0,-(%sp) /* dest_addr */ move.l %d0,-(%sp) /* gd */ - #if defined(DEBUG) && (TEXT_BASE != CFG_INT_FLASH_BASE) && \ - defined(CFG_HALT_BEFOR_RAM_JUMP) - halt - #endif +#if defined(DEBUG) && (TEXT_BASE != CFG_INT_FLASH_BASE) && \ + defined(CFG_HALT_BEFOR_RAM_JUMP) + halt +#endif jsr (%a1) /*------------------------------------------------------------------------------*/ @@ -356,6 +356,24 @@ _int_handler: /*------------------------------------------------------------------------------*/ /* cache functions */ +#ifdef CONFIG_M5271 + .globl icache_enable +icache_enable: + move.l #0x01000000, %d0 /* Invalidate cache cmd */ + movec %d0, %CACR /* Invalidate cache */ + move.l #(CFG_SDRAM_BASE + 0xc000), %d0 /* Setup cache mask */ + movec %d0, %ACR0 /* Enable cache */ + + move.l #0x80000200, %d0 /* Setup cache mask */ + movec %d0, %CACR /* Enable cache */ + nop + + move.l #(CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END-8), %a1 + moveq #1, %d0 + move.l %d0, (%a1) + rts +#endif + #ifdef CONFIG_M5272 .globl icache_enable icache_enable: @@ -426,13 +444,29 @@ icache_state_access_2: .globl icache_status icache_status: icache_state_access_3: - move.l icache_state, %d0 + move.l #(icache_state), %a0 + move.l (%a0), %d0 rts .data icache_state: .long 0 /* cache is diabled on inirialization */ + .globl dcache_enable +dcache_enable: + /* dummy function */ + rts + + .globl dcache_disable +dcache_disable: + /* dummy function */ + rts + + .globl dcache_status +dcache_status: + /* dummy function */ + rts + /*------------------------------------------------------------------------------*/ .globl version_string diff --git a/lib_m68k/time.c b/lib_m68k/time.c index 6c19059e6..28d371d5e 100644 --- a/lib_m68k/time.c +++ b/lib_m68k/time.c @@ -25,288 +25,12 @@ #include -#include #include #include -#ifdef CONFIG_M5271 -#include -#include -#endif - -#ifdef CONFIG_M5272 -#include -#include -#endif - -#ifdef CONFIG_M5282 -#include -#endif - -#ifdef CONFIG_M5249 -#include -#include -#endif - DECLARE_GLOBAL_DATA_PTR; static ulong timestamp; -#if defined(CONFIG_M5282) || defined(CONFIG_M5271) -static unsigned short lastinc; -#endif - -#if defined(CONFIG_M5272) -/* - * We use timer 3 which is running with a period of 1 us - */ -void udelay(unsigned long usec) -{ - volatile timer_t *timerp = (timer_t *) (CFG_MBAR + MCFTIMER_BASE3); - uint start, now, tmp; - - while (usec > 0) { - if (usec > 65000) - tmp = 65000; - else - tmp = usec; - usec = usec - tmp; - - /* Set up TIMER 3 as timebase clock */ - timerp->timer_tmr = MCFTIMER_TMR_DISABLE; - timerp->timer_tcn = 0; - /* set period to 1 us */ - timerp->timer_tmr = - (((CFG_CLK / 1000000) - - 1) << 8) | MCFTIMER_TMR_CLK1 | MCFTIMER_TMR_FREERUN | - MCFTIMER_TMR_ENABLE; - - start = now = timerp->timer_tcn; - while (now < start + tmp) - now = timerp->timer_tcn; - } -} - -void mcf_timer_interrupt(void *not_used) -{ - volatile timer_t *timerp = (timer_t *) (CFG_MBAR + MCFTIMER_BASE4); - volatile intctrl_t *intp = (intctrl_t *) (CFG_MBAR + MCFSIM_ICR1); - - /* check for timer 4 interrupts */ - if ((intp->int_isr & 0x01000000) != 0) { - return; - } - - /* reset timer */ - timerp->timer_ter = MCFTIMER_TER_CAP | MCFTIMER_TER_REF; - timestamp++; -} - -void timer_init(void) -{ - volatile timer_t *timerp = (timer_t *) (CFG_MBAR + MCFTIMER_BASE4); - volatile intctrl_t *intp = (intctrl_t *) (CFG_MBAR + MCFSIM_ICR1); - - timestamp = 0; - - /* Set up TIMER 4 as clock */ - timerp->timer_tmr = MCFTIMER_TMR_DISABLE; - - /* initialize and enable timer 4 interrupt */ - irq_install_handler(72, mcf_timer_interrupt, 0); - intp->int_icr1 |= 0x0000000d; - - timerp->timer_tcn = 0; - timerp->timer_trr = 1000; /* Interrupt every ms */ - /* set a period of 1us, set timer mode to restart and enable timer and interrupt */ - timerp->timer_tmr = - (((CFG_CLK / 1000000) - - 1) << 8) | MCFTIMER_TMR_CLK1 | MCFTIMER_TMR_RESTART | - MCFTIMER_TMR_ENORI | MCFTIMER_TMR_ENABLE; -} - -void reset_timer(void) -{ - timestamp = 0; -} - -ulong get_timer(ulong base) -{ - return (timestamp - base); -} - -void set_timer(ulong t) -{ - timestamp = t; -} -#endif - -#if defined(CONFIG_M5282) || defined(CONFIG_M5271) - -void udelay(unsigned long usec) -{ - volatile unsigned short *timerp; - uint tmp; - - timerp = (volatile unsigned short *)(CFG_MBAR + MCFTIMER_BASE3); - - while (usec > 0) { - if (usec > 65000) - tmp = 65000; - else - tmp = usec; - usec = usec - tmp; - - /* Set up TIMER 3 as timebase clock */ - timerp[MCFTIMER_PCSR] = MCFTIMER_PCSR_OVW; - timerp[MCFTIMER_PMR] = 0; - /* set period to 1 us */ - timerp[MCFTIMER_PCSR] = -#ifdef CONFIG_M5271 - (6 << 8) | MCFTIMER_PCSR_EN | MCFTIMER_PCSR_OVW; -#else /* !CONFIG_M5271 */ - (5 << 8) | MCFTIMER_PCSR_EN | MCFTIMER_PCSR_OVW; -#endif /* CONFIG_M5271 */ - - timerp[MCFTIMER_PMR] = tmp; - while (timerp[MCFTIMER_PCNTR] > 0) ; - } -} - -void timer_init(void) -{ - volatile unsigned short *timerp; - - timerp = (volatile unsigned short *)(CFG_MBAR + MCFTIMER_BASE4); - timestamp = 0; - - /* Set up TIMER 4 as poll clock */ - timerp[MCFTIMER_PCSR] = MCFTIMER_PCSR_OVW; - timerp[MCFTIMER_PMR] = lastinc = 0; - timerp[MCFTIMER_PCSR] = -#ifdef CONFIG_M5271 - (6 << 8) | MCFTIMER_PCSR_EN | MCFTIMER_PCSR_OVW; -#else /* !CONFIG_M5271 */ - (5 << 8) | MCFTIMER_PCSR_EN | MCFTIMER_PCSR_OVW; -#endif /* CONFIG_M5271 */ -} - -void set_timer(ulong t) -{ - volatile unsigned short *timerp; - - timerp = (volatile unsigned short *)(CFG_MBAR + MCFTIMER_BASE4); - timestamp = 0; - timerp[MCFTIMER_PMR] = lastinc = 0; -} - -ulong get_timer(ulong base) -{ - unsigned short now, diff; - volatile unsigned short *timerp; - - timerp = (volatile unsigned short *)(CFG_MBAR + MCFTIMER_BASE4); - now = timerp[MCFTIMER_PCNTR]; - diff = -(now - lastinc); - - timestamp += diff; - lastinc = now; - return timestamp - base; -} - -void wait_ticks(unsigned long ticks) -{ - set_timer(0); - while (get_timer(0) < ticks) ; -} -#endif - -#if defined(CONFIG_M5249) -/* - * We use timer 1 which is running with a period of 1 us - */ -void udelay(unsigned long usec) -{ - volatile timer_t *timerp = (timer_t *) (CFG_MBAR + MCFTIMER_BASE1); - uint start, now, tmp; - - while (usec > 0) { - if (usec > 65000) - tmp = 65000; - else - tmp = usec; - usec = usec - tmp; - - /* Set up TIMER 1 as timebase clock */ - timerp->timer_tmr = MCFTIMER_TMR_DISABLE; - timerp->timer_tcn = 0; - /* set period to 1 us */ - /* on m5249 the system clock is (cpu_clk / 2) -> divide by 2000000 */ - timerp->timer_tmr = - (((CFG_CLK / 2000000) - - 1) << 8) | MCFTIMER_TMR_CLK1 | MCFTIMER_TMR_FREERUN | - MCFTIMER_TMR_ENABLE; - - start = now = timerp->timer_tcn; - while (now < start + tmp) - now = timerp->timer_tcn; - } -} - -void mcf_timer_interrupt(void *not_used) -{ - volatile timer_t *timerp = (timer_t *) (CFG_MBAR + MCFTIMER_BASE2); - - /* check for timer 2 interrupts */ - if ((mbar_readLong(MCFSIM_IPR) & 0x00000400) == 0) { - return; - } - - /* reset timer */ - timerp->timer_ter = MCFTIMER_TER_CAP | MCFTIMER_TER_REF; - timestamp++; -} - -void timer_init(void) -{ - volatile timer_t *timerp = (timer_t *) (CFG_MBAR + MCFTIMER_BASE2); - - timestamp = 0; - - /* Set up TIMER 2 as clock */ - timerp->timer_tmr = MCFTIMER_TMR_DISABLE; - - /* initialize and enable timer 2 interrupt */ - irq_install_handler(31, mcf_timer_interrupt, 0); - mbar_writeLong(MCFSIM_IMR, mbar_readLong(MCFSIM_IMR) & ~0x00000400); - mbar_writeByte(MCFSIM_TIMER2ICR, - MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL7 | - MCFSIM_ICR_PRI3); - - timerp->timer_tcn = 0; - timerp->timer_trr = 1000; /* Interrupt every ms */ - /* set a period of 1us, set timer mode to restart and enable timer and interrupt */ - /* on m5249 the system clock is (cpu_clk / 2) -> divide by 2000000 */ - timerp->timer_tmr = - (((CFG_CLK / 2000000) - - 1) << 8) | MCFTIMER_TMR_CLK1 | MCFTIMER_TMR_RESTART | - MCFTIMER_TMR_ENORI | MCFTIMER_TMR_ENABLE; -} - -void reset_timer(void) -{ - timestamp = 0; -} - -ulong get_timer(ulong base) -{ - return (timestamp - base); -} - -void set_timer(ulong t) -{ - timestamp = t; -} -#endif #if defined(CONFIG_MCFTMR) #ifndef CFG_UDELAY_BASE From 56115665b4a64c10c01440c57749b265e0908fa4 Mon Sep 17 00:00:00 2001 From: TsiChungLiew Date: Wed, 15 Aug 2007 19:38:15 -0500 Subject: [PATCH 157/259] ColdFire: MCF52x2 Header files update Signed-off-by: TsiChungLiew --- include/asm-m68k/fec.h | 44 ++- include/asm-m68k/immap.h | 91 +++++ include/asm-m68k/immap_5249.h | 22 +- include/asm-m68k/immap_5271.h | 136 +++---- include/asm-m68k/immap_5272.h | 689 +++++++++++++++------------------- include/asm-m68k/immap_5282.h | 217 ++++++++--- include/asm-m68k/m5249.h | 183 +++++---- include/asm-m68k/m5271.h | 105 +++++- include/asm-m68k/m5272.h | 221 ++++++++--- include/asm-m68k/m5282.h | 262 ++++++++----- include/asm-m68k/mcftimer.h | 111 ------ include/asm-m68k/mcfuart.h | 217 ----------- include/asm-m68k/timer.h | 2 +- 13 files changed, 1193 insertions(+), 1107 deletions(-) delete mode 100644 include/asm-m68k/mcftimer.h delete mode 100644 include/asm-m68k/mcfuart.h diff --git a/include/asm-m68k/fec.h b/include/asm-m68k/fec.h index 9a5e7d5ab..344c5e197 100644 --- a/include/asm-m68k/fec.h +++ b/include/asm-m68k/fec.h @@ -121,6 +121,41 @@ struct fec_info_s { /* Register read/write struct */ typedef struct fec { +#ifdef CONFIG_M5272 + u32 ecr; /* 0x00 */ + u32 eir; /* 0x04 */ + u32 eimr; /* 0x08 */ + u32 ivsr; /* 0x0C */ + u32 rdar; /* 0x10 */ + u32 tdar; /* 0x14 */ + u8 resv1[0x28]; /* 0x18 */ + u32 mmfr; /* 0x40 */ + u32 mscr; /* 0x44 */ + u8 resv2[0x44]; /* 0x48 */ + u32 frbr; /* 0x8C */ + u32 frsr; /* 0x90 */ + u8 resv3[0x10]; /* 0x94 */ + u32 tfwr; /* 0xA4 */ + u32 res4; /* 0xA8 */ + u32 tfsr; /* 0xAC */ + u8 resv4[0x50]; /* 0xB0 */ + u32 opd; /* 0x100 - dummy */ + u32 rcr; /* 0x104 */ + u32 mibc; /* 0x108 */ + u8 resv5[0x38]; /* 0x10C */ + u32 tcr; /* 0x144 */ + u8 resv6[0x270]; /* 0x148 */ + u32 iaur; /* 0x3B8 - dummy */ + u32 ialr; /* 0x3BC - dummy */ + u32 palr; /* 0x3C0 */ + u32 paur; /* 0x3C4 */ + u32 gaur; /* 0x3C8 */ + u32 galr; /* 0x3CC */ + u32 erdsr; /* 0x3D0 */ + u32 etdsr; /* 0x3D4 */ + u32 emrbr; /* 0x3D8 */ + u8 resv12[0x74]; /* 0x18C */ +#else u8 resv0[0x4]; u32 eir; u32 eimr; @@ -157,6 +192,7 @@ typedef struct fec { u32 etdsr; u32 emrbr; u8 resv12[0x74]; +#endif u32 rmon_t_drop; u32 rmon_t_packets; @@ -304,16 +340,16 @@ typedef struct fec { #define FEC_FRSR_R_FSTART(x) (((x)&0xFF)<<2) /* Bit definitions and macros for FEC_ERDSR */ -#define FEC_ERDSR_R_DES_START(x)(((x)&0x3FFFFFFF)<<2) +#define FEC_ERDSR_R_DES_START(x) (((x)&0x3FFFFFFF)<<2) /* Bit definitions and macros for FEC_ETDSR */ -#define FEC_ETDSR_X_DES_START(x)(((x)&0x3FFFFFFF)<<2) +#define FEC_ETDSR_X_DES_START(x) (((x)&0x3FFFFFFF)<<2) /* Bit definitions and macros for FEC_EMRBR */ -#define FEC_EMRBR_R_BUF_SIZE(x) (((x)&0x7F)<<4) +#define FEC_EMRBR_R_BUF_SIZE(x) (((x)&0x7F)<<4) #define FEC_RESET_DELAY 100 -#define FEC_RX_TOUT 100 +#define FEC_RX_TOUT 100 #endif /* CONFIG_MCFFEC */ #endif /* fec_h */ diff --git a/include/asm-m68k/immap.h b/include/asm-m68k/immap.h index 2555e7e82..3ee7071f3 100644 --- a/include/asm-m68k/immap.h +++ b/include/asm-m68k/immap.h @@ -26,6 +26,97 @@ #ifndef __IMMAP_H #define __IMMAP_H +#ifdef CONFIG_M5249 +#include +#include + +#define CFG_UART_BASE (MMAP_UART0 + (CFG_UART_PORT * 0x40)) + +#define CFG_INTR_BASE (MMAP_INTC) +#define CFG_NUM_IRQS (64) + +/* Timer */ +#ifdef CONFIG_MCFTMR +#define CFG_UDELAY_BASE (MMAP_DTMR0) +#define CFG_TMR_BASE (MMAP_DTMR1) +#define CFG_TMRPND_REG (mbar_readLong(MCFSIM_IPR)) +#define CFG_TMRINTR_NO (31) +#define CFG_TMRINTR_MASK (0x00000400) +#define CFG_TMRINTR_PEND (CFG_TMRINTR_MASK) +#define CFG_TMRINTR_PRI (0) /* Level must include inorder to work */ +#define CFG_TIMER_PRESCALER (((gd->bus_clk / 2000000) - 1) << 8) +#endif +#endif /* CONFIG_M5249 */ + +#ifdef CONFIG_M5271 +#include +#include + +#define CFG_FEC0_IOBASE (MMAP_FEC) +#define CFG_UART_BASE (MMAP_UART0 + (CFG_UART_PORT * 0x40)) + +/* Timer */ +#ifdef CONFIG_MCFTMR +#define CFG_UDELAY_BASE (MMAP_DTMR0) +#define CFG_TMR_BASE (MMAP_DTMR3) +#define CFG_TMRPND_REG (((volatile int0_t *)(CFG_INTR_BASE))->iprl0) +#define CFG_TMRINTR_NO (INT0_LO_DTMR3) +#define CFG_TMRINTR_MASK (INTC_IPRL_INT22) +#define CFG_TMRINTR_PEND (CFG_TMRINTR_MASK) +#define CFG_TMRINTR_PRI (0) /* Level must include inorder to work */ +#define CFG_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8) +#endif + +#define CFG_INTR_BASE (MMAP_INTC0) +#define CFG_NUM_IRQS (128) +#endif /* CONFIG_M5271 */ + +#ifdef CONFIG_M5272 +#include +#include + +#define CFG_FEC0_IOBASE (MMAP_FEC) +#define CFG_UART_BASE (MMAP_UART0 + (CFG_UART_PORT * 0x40)) + +#define CFG_INTR_BASE (MMAP_INTC) +#define CFG_NUM_IRQS (64) + +/* Timer */ +#ifdef CONFIG_MCFTMR +#define CFG_UDELAY_BASE (MMAP_TMR0) +#define CFG_TMR_BASE (MMAP_TMR3) +#define CFG_TMRPND_REG (((volatile intctrl_t *)(CFG_INTR_BASE))->int_isr) +#define CFG_TMRINTR_NO (INT_TMR3) +#define CFG_TMRINTR_MASK (INT_ISR_INT24) +#define CFG_TMRINTR_PEND (0) +#define CFG_TMRINTR_PRI (INT_ICR1_TMR3PI | INT_ICR1_TMR3IPL(5)) +#define CFG_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8) +#endif +#endif /* CONFIG_M5272 */ + +#ifdef CONFIG_M5282 +#include +#include + +#define CFG_FEC0_IOBASE (MMAP_FEC) +#define CFG_UART_BASE (MMAP_UART0 + (CFG_UART_PORT * 0x40)) + +#define CFG_INTR_BASE (MMAP_INTC0) +#define CFG_NUM_IRQS (128) + +/* Timer */ +#ifdef CONFIG_MCFTMR +#define CFG_UDELAY_BASE (MMAP_DTMR0) +#define CFG_TMR_BASE (MMAP_DTMR3) +#define CFG_TMRPND_REG (((volatile int0_t *)(CFG_INTR_BASE))->iprl0) +#define CFG_TMRINTR_NO (INT0_LO_DTMR3) +#define CFG_TMRINTR_MASK (1 << INT0_LO_DTMR3) +#define CFG_TMRINTR_PEND (CFG_TMRINTR_MASK) +#define CFG_TMRINTR_PRI (0x1E) /* Level must include inorder to work */ +#define CFG_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8) +#endif +#endif /* CONFIG_M5282 */ + #ifdef CONFIG_M5329 #include #include diff --git a/include/asm-m68k/immap_5249.h b/include/asm-m68k/immap_5249.h index a2c127182..6c6fbcce4 100644 --- a/include/asm-m68k/immap_5249.h +++ b/include/asm-m68k/immap_5249.h @@ -25,19 +25,11 @@ #ifndef __IMMAP_5249__ #define __IMMAP_5249__ -/* Timer module registers - */ -typedef struct timer_ctrl { - ushort timer_tmr; - ushort res1; - ushort timer_trr; - ushort res2; - ushort timer_tcap; - ushort res3; - ushort timer_tcn; - ushort res4; - ushort timer_ter; - uchar res5[14]; -} timer_t; +#define MMAP_INTC (CFG_MBAR + 0x00000040) +#define MMAP_DTMR0 (CFG_MBAR + 0x00000140) +#define MMAP_DTMR1 (CFG_MBAR + 0x00000180) +#define MMAP_UART0 (CFG_MBAR + 0x000001C0) +#define MMAP_UART1 (CFG_MBAR + 0x00000200) +#define MMAP_QSPI (CFG_MBAR + 0x00000400) -#endif /* __IMMAP_5249__ */ +#endif /* __IMMAP_5249__ */ diff --git a/include/asm-m68k/immap_5271.h b/include/asm-m68k/immap_5271.h index 424dc1d1f..d9dc01591 100644 --- a/include/asm-m68k/immap_5271.h +++ b/include/asm-m68k/immap_5271.h @@ -26,73 +26,73 @@ #ifndef __IMMAP_5271__ #define __IMMAP_5271__ -/* Interrupt module registers -*/ -typedef struct int_ctrl { - uint int_icr1; - uint int_icr2; - uint int_icr3; - uint int_icr4; - uint int_isr; - uint int_pitr; - uint int_piwr; - uchar res1[3]; - uchar int_pivr; -} intctrl_t; +#define MMAP_SCM (CFG_MBAR + 0x00000000) +#define MMAP_SDRAM (CFG_MBAR + 0x00000040) +#define MMAP_FBCS (CFG_MBAR + 0x00000080) +#define MMAP_DMA0 (CFG_MBAR + 0x00000100) +#define MMAP_DMA1 (CFG_MBAR + 0x00000110) +#define MMAP_DMA2 (CFG_MBAR + 0x00000120) +#define MMAP_DMA3 (CFG_MBAR + 0x00000130) +#define MMAP_UART0 (CFG_MBAR + 0x00000200) +#define MMAP_UART1 (CFG_MBAR + 0x00000240) +#define MMAP_UART2 (CFG_MBAR + 0x00000280) +#define MMAP_I2C (CFG_MBAR + 0x00000300) +#define MMAP_QSPI (CFG_MBAR + 0x00000340) +#define MMAP_DTMR0 (CFG_MBAR + 0x00000400) +#define MMAP_DTMR1 (CFG_MBAR + 0x00000440) +#define MMAP_DTMR2 (CFG_MBAR + 0x00000480) +#define MMAP_DTMR3 (CFG_MBAR + 0x000004C0) +#define MMAP_INTC0 (CFG_MBAR + 0x00000C00) +#define MMAP_INTC1 (CFG_MBAR + 0x00000D00) +#define MMAP_INTCACK (CFG_MBAR + 0x00000F00) +#define MMAP_FEC (CFG_MBAR + 0x00001000) +#define MMAP_FECFIFO (CFG_MBAR + 0x00001400) +#define MMAP_GPIO (CFG_MBAR + 0x00100000) +#define MMAP_CCM (CFG_MBAR + 0x00110000) +#define MMAP_PLL (CFG_MBAR + 0x00120000) +#define MMAP_EPORT (CFG_MBAR + 0x00130000) +#define MMAP_WDOG (CFG_MBAR + 0x00140000) +#define MMAP_PIT0 (CFG_MBAR + 0x00150000) +#define MMAP_PIT1 (CFG_MBAR + 0x00160000) +#define MMAP_PIT2 (CFG_MBAR + 0x00170000) +#define MMAP_PIT3 (CFG_MBAR + 0x00180000) +#define MMAP_MDHA (CFG_MBAR + 0x00190000) +#define MMAP_RNG (CFG_MBAR + 0x001A0000) +#define MMAP_SKHA (CFG_MBAR + 0x001B0000) +#define MMAP_CAN1 (CFG_MBAR + 0x001C0000) +#define MMAP_ETPU (CFG_MBAR + 0x001D0000) +#define MMAP_CAN2 (CFG_MBAR + 0x001F0000) -/* Timer module registers - */ -typedef struct timer_ctrl { - ushort timer_tmr; - ushort res1; - ushort timer_trr; - ushort res2; - ushort timer_tcap; - ushort res3; - ushort timer_tcn; - ushort res4; - ushort timer_ter; - uchar res5[14]; -} timer_t; +/* Interrupt module registers */ +typedef struct int0_ctrl { + /* Interrupt Controller 0 */ + u32 iprh0; /* 0x00 Pending Register High */ + u32 iprl0; /* 0x04 Pending Register Low */ + u32 imrh0; /* 0x08 Mask Register High */ + u32 imrl0; /* 0x0C Mask Register Low */ + u32 frch0; /* 0x10 Force Register High */ + u32 frcl0; /* 0x14 Force Register Low */ + u8 irlr; /* 0x18 */ + u8 iacklpr; /* 0x19 */ + u16 res1[19]; /* 0x1a - 0x3c */ + u8 icr0[64]; /* 0x40 - 0x7F Control registers */ + u32 res3[24]; /* 0x80 - 0xDF */ + u8 swiack0; /* 0xE0 Software Interrupt Acknowledge */ + u8 res4[3]; /* 0xE1 - 0xE3 */ + u8 Lniack0_1; /* 0xE4 Level n interrupt acknowledge resister */ + u8 res5[3]; /* 0xE5 - 0xE7 */ + u8 Lniack0_2; /* 0xE8 Level n interrupt acknowledge resister */ + u8 res6[3]; /* 0xE9 - 0xEB */ + u8 Lniack0_3; /* 0xEC Level n interrupt acknowledge resister */ + u8 res7[3]; /* 0xED - 0xEF */ + u8 Lniack0_4; /* 0xF0 Level n interrupt acknowledge resister */ + u8 res8[3]; /* 0xF1 - 0xF3 */ + u8 Lniack0_5; /* 0xF4 Level n interrupt acknowledge resister */ + u8 res9[3]; /* 0xF5 - 0xF7 */ + u8 Lniack0_6; /* 0xF8 Level n interrupt acknowledge resister */ + u8 resa[3]; /* 0xF9 - 0xFB */ + u8 Lniack0_7; /* 0xFC Level n interrupt acknowledge resister */ + u8 resb[3]; /* 0xFD - 0xFF */ +} int0_t; - /* Fast ethernet controller registers - */ -typedef struct fec { - uint res1; - uint fec_ievent; - uint fec_imask; - uint res2; - uint fec_r_des_active; - uint fec_x_des_active; - uint res3[3]; - uint fec_ecntrl; - uint res4[6]; - uint fec_mii_data; - uint fec_mii_speed; - uint res5[7]; - uint fec_mibc; - uint res6[7]; - uint fec_r_cntrl; - uint res7[15]; - uint fec_x_cntrl; - uint res8[7]; - uint fec_addr_low; - uint fec_addr_high; - uint fec_opd; - uint res9[10]; - uint fec_ihash_table_high; - uint fec_ihash_table_low; - uint fec_ghash_table_high; - uint fec_ghash_table_low; - uint res10[7]; - uint fec_tfwr; - uint res11; - uint fec_r_bound; - uint fec_r_fstart; - uint res12[11]; - uint fec_r_des_start; - uint fec_x_des_start; - uint fec_r_buff_size; -} fec_t; - -#endif /* __IMMAP_5271__ */ +#endif /* __IMMAP_5271__ */ diff --git a/include/asm-m68k/immap_5272.h b/include/asm-m68k/immap_5272.h index ecb4906f3..2ebb140b0 100644 --- a/include/asm-m68k/immap_5272.h +++ b/include/asm-m68k/immap_5272.h @@ -25,423 +25,326 @@ #ifndef __IMMAP_5272__ #define __IMMAP_5272__ -/* System configuration registers -*/ -typedef struct sys_ctrl { - uint sc_mbar; - ushort sc_scr; - ushort sc_spr; - uint sc_pmr; - char res1[2]; - ushort sc_alpr; - uint sc_dir; - char res2[12]; +#define MMAP_CFG (CFG_MBAR + 0x00000000) +#define MMAP_INTC (CFG_MBAR + 0x00000020) +#define MMAP_FBCS (CFG_MBAR + 0x00000040) +#define MMAP_GPIO (CFG_MBAR + 0x00000080) +#define MMAP_QSPI (CFG_MBAR + 0x000000A0) +#define MMAP_PWM (CFG_MBAR + 0x000000C0) +#define MMAP_DMA0 (CFG_MBAR + 0x000000E0) +#define MMAP_UART0 (CFG_MBAR + 0x00000100) +#define MMAP_UART1 (CFG_MBAR + 0x00000140) +#define MMAP_SDRAM (CFG_MBAR + 0x00000180) +#define MMAP_TMR0 (CFG_MBAR + 0x00000200) +#define MMAP_TMR1 (CFG_MBAR + 0x00000220) +#define MMAP_TMR2 (CFG_MBAR + 0x00000240) +#define MMAP_TMR3 (CFG_MBAR + 0x00000260) +#define MMAP_WDOG (CFG_MBAR + 0x00000280) +#define MMAP_PLIC (CFG_MBAR + 0x00000300) +#define MMAP_FEC (CFG_MBAR + 0x00000840) +#define MMAP_USB (CFG_MBAR + 0x00001000) + +/* System configuration registers */ +typedef struct sys_ctrl { + uint sc_mbar; + ushort sc_scr; + ushort sc_spr; + uint sc_pmr; + char res1[2]; + ushort sc_alpr; + uint sc_dir; + char res2[12]; } sysctrl_t; -/* Interrupt module registers -*/ +/* Interrupt module registers */ typedef struct int_ctrl { - uint int_icr1; - uint int_icr2; - uint int_icr3; - uint int_icr4; - uint int_isr; - uint int_pitr; - uint int_piwr; - uchar res1[3]; - uchar int_pivr; + uint int_icr1; + uint int_icr2; + uint int_icr3; + uint int_icr4; + uint int_isr; + uint int_pitr; + uint int_piwr; + uchar res1[3]; + uchar int_pivr; } intctrl_t; -/* Chip select module registers. -*/ -typedef struct cs_ctlr { - uint cs_br0; - uint cs_or0; - uint cs_br1; - uint cs_or1; - uint cs_br2; - uint cs_or2; - uint cs_br3; - uint cs_or3; - uint cs_br4; - uint cs_or4; - uint cs_br5; - uint cs_or5; - uint cs_br6; - uint cs_or6; - uint cs_br7; - uint cs_or7; +/* Chip select module registers */ +typedef struct cs_ctlr { + uint cs_br0; + uint cs_or0; + uint cs_br1; + uint cs_or1; + uint cs_br2; + uint cs_or2; + uint cs_br3; + uint cs_or3; + uint cs_br4; + uint cs_or4; + uint cs_br5; + uint cs_or5; + uint cs_br6; + uint cs_or6; + uint cs_br7; + uint cs_or7; } csctrl_t; -/* GPIO port registers -*/ -typedef struct gpio_ctrl { - uint gpio_pacnt; - ushort gpio_paddr; - ushort gpio_padat; - uint gpio_pbcnt; - ushort gpio_pbddr; - ushort gpio_pbdat; - uchar res1[4]; - ushort gpio_pcddr; - ushort gpio_pcdat; - uint gpio_pdcnt; - uchar res2[4]; +/* GPIO port registers */ +typedef struct gpio_ctrl { + uint gpio_pacnt; + ushort gpio_paddr; + ushort gpio_padat; + uint gpio_pbcnt; + ushort gpio_pbddr; + ushort gpio_pbdat; + uchar res1[4]; + ushort gpio_pcddr; + ushort gpio_pcdat; + uint gpio_pdcnt; + uchar res2[4]; } gpio_t; -/* QSPI module registers - */ -typedef struct qspi_ctrl { - ushort qspi_qmr; - uchar res1[2]; - ushort qspi_qdlyr; - uchar res2[2]; - ushort qspi_qwr; - uchar res3[2]; - ushort qspi_qir; - uchar res4[2]; - ushort qspi_qar; - uchar res5[2]; - ushort qspi_qdr; - uchar res6[10]; +/* QSPI module registers */ +typedef struct qspi_ctrl { + ushort qspi_qmr; + uchar res1[2]; + ushort qspi_qdlyr; + uchar res2[2]; + ushort qspi_qwr; + uchar res3[2]; + ushort qspi_qir; + uchar res4[2]; + ushort qspi_qar; + uchar res5[2]; + ushort qspi_qdr; + uchar res6[10]; } qspi_t; -/* PWM module registers - */ -typedef struct pwm_ctrl { - uchar pwm_pwcr0; - uchar res1[3]; - uchar pwm_pwcr1; - uchar res2[3]; - uchar pwm_pwcr2; - uchar res3[7]; - uchar pwm_pwwd0; - uchar res4[3]; - uchar pwm_pwwd1; - uchar res5[3]; - uchar pwm_pwwd2; - uchar res6[7]; +/* PWM module registers */ +typedef struct pwm_ctrl { + uchar pwm_pwcr0; + uchar res1[3]; + uchar pwm_pwcr1; + uchar res2[3]; + uchar pwm_pwcr2; + uchar res3[7]; + uchar pwm_pwwd0; + uchar res4[3]; + uchar pwm_pwwd1; + uchar res5[3]; + uchar pwm_pwwd2; + uchar res6[7]; } pwm_t; -/* DMA module registers - */ -typedef struct dma_ctrl { - ulong dma_dmr; - uchar res1[2]; - ushort dma_dir; - ulong dma_dbcr; - ulong dma_dsar; - ulong dma_ddar; - uchar res2[12]; +/* DMA module registers */ +typedef struct dma_ctrl { + ulong dma_dmr; + uchar res1[2]; + ushort dma_dir; + ulong dma_dbcr; + ulong dma_dsar; + ulong dma_ddar; + uchar res2[12]; } dma_t; -/* UART module registers - */ -typedef struct uart_ctrl { - uchar uart_umr; - uchar res1[3]; - uchar uart_usr_ucsr; - uchar res2[3]; - uchar uart_ucr; - uchar res3[3]; - uchar uart_urb_utb; - uchar res4[3]; - uchar uart_uipcr_uacr; - uchar res5[3]; - uchar uart_uisr_uimr; - uchar res6[3]; - uchar uart_udu; - uchar res7[3]; - uchar uart_udl; - uchar res8[3]; - uchar uart_uabu; - uchar res9[3]; - uchar uart_uabl; - uchar res10[3]; - uchar uart_utf; - uchar res11[3]; - uchar uart_urf; - uchar res12[3]; - uchar uart_ufpd; - uchar res13[3]; - uchar uart_uip; - uchar res14[3]; - uchar uart_uop1; - uchar res15[3]; - uchar uart_uop0; - uchar res16[3]; -} uart_t; - -/* SDRAM controller registers, offset: 0x180 - */ +/* SDRAM controller registers, offset: 0x180 */ typedef struct sdram_ctrl { - uchar res1[2]; - ushort sdram_sdcr; - uchar res2[2]; - ushort sdram_sdtr; - uchar res3[120]; + uchar res1[2]; + ushort sdram_sdcr; + uchar res2[2]; + ushort sdram_sdtr; + uchar res3[120]; } sdramctrl_t; -/* Timer module registers - */ -typedef struct timer_ctrl { - ushort timer_tmr; - ushort res1; - ushort timer_trr; - ushort res2; - ushort timer_tcap; - ushort res3; - ushort timer_tcn; - ushort res4; - ushort timer_ter; - uchar res5[14]; -} timer_t; - -/* Watchdog registers - */ +/* Watchdog registers */ typedef struct wdog_ctrl { - ushort wdog_wrrr; - ushort res1; - ushort wdog_wirr; - ushort res2; - ushort wdog_wcr; - ushort res3; - ushort wdog_wer; - uchar res4[114]; + ushort wdog_wrrr; + ushort res1; + ushort wdog_wirr; + ushort res2; + ushort wdog_wcr; + ushort res3; + ushort wdog_wer; + uchar res4[114]; } wdog_t; -/* PLIC module registers - */ +/* PLIC module registers */ typedef struct plic_ctrl { - ulong plic_p0b1rr; - ulong plic_p1b1rr; - ulong plic_p2b1rr; - ulong plic_p3b1rr; - ulong plic_p0b2rr; - ulong plic_p1b2rr; - ulong plic_p2b2rr; - ulong plic_p3b2rr; - uchar plic_p0drr; - uchar plic_p1drr; - uchar plic_p2drr; - uchar plic_p3drr; - uchar res1[4]; - ulong plic_p0b1tr; - ulong plic_p1b1tr; - ulong plic_p2b1tr; - ulong plic_p3b1tr; - ulong plic_p0b2tr; - ulong plic_p1b2tr; - ulong plic_p2b2tr; - ulong plic_p3b2tr; - uchar plic_p0dtr; - uchar plic_p1dtr; - uchar plic_p2dtr; - uchar plic_p3dtr; - uchar res2[4]; - ushort plic_p0cr; - ushort plic_p1cr; - ushort plic_p2cr; - ushort plic_p3cr; - ushort plic_p0icr; - ushort plic_p1icr; - ushort plic_p2icr; - ushort plic_p3icr; - ushort plic_p0gmr; - ushort plic_p1gmr; - ushort plic_p2gmr; - ushort plic_p3gmr; - ushort plic_p0gmt; - ushort plic_p1gmt; - ushort plic_p2gmt; - ushort plic_p3gmt; - uchar res3; - uchar plic_pgmts; - uchar plic_pgmta; - uchar res4; - uchar plic_p0gcir; - uchar plic_p1gcir; - uchar plic_p2gcir; - uchar plic_p3gcir; - uchar plic_p0gcit; - uchar plic_p1gcit; - uchar plic_p2gcit; - uchar plic_p3gcit; - uchar res5[3]; - uchar plic_pgcitsr; - uchar res6[3]; - uchar plic_pdcsr; - ushort plic_p0psr; - ushort plic_p1psr; - ushort plic_p2psr; - ushort plic_p3psr; - ushort plic_pasr; - uchar res7; - uchar plic_plcr; - ushort res8; - ushort plic_pdrqr; - ushort plic_p0sdr; - ushort plic_p1sdr; - ushort plic_p2sdr; - ushort plic_p3sdr; - ushort res9; - ushort plic_pcsr; - uchar res10[1184]; + ulong plic_p0b1rr; + ulong plic_p1b1rr; + ulong plic_p2b1rr; + ulong plic_p3b1rr; + ulong plic_p0b2rr; + ulong plic_p1b2rr; + ulong plic_p2b2rr; + ulong plic_p3b2rr; + uchar plic_p0drr; + uchar plic_p1drr; + uchar plic_p2drr; + uchar plic_p3drr; + uchar res1[4]; + ulong plic_p0b1tr; + ulong plic_p1b1tr; + ulong plic_p2b1tr; + ulong plic_p3b1tr; + ulong plic_p0b2tr; + ulong plic_p1b2tr; + ulong plic_p2b2tr; + ulong plic_p3b2tr; + uchar plic_p0dtr; + uchar plic_p1dtr; + uchar plic_p2dtr; + uchar plic_p3dtr; + uchar res2[4]; + ushort plic_p0cr; + ushort plic_p1cr; + ushort plic_p2cr; + ushort plic_p3cr; + ushort plic_p0icr; + ushort plic_p1icr; + ushort plic_p2icr; + ushort plic_p3icr; + ushort plic_p0gmr; + ushort plic_p1gmr; + ushort plic_p2gmr; + ushort plic_p3gmr; + ushort plic_p0gmt; + ushort plic_p1gmt; + ushort plic_p2gmt; + ushort plic_p3gmt; + uchar res3; + uchar plic_pgmts; + uchar plic_pgmta; + uchar res4; + uchar plic_p0gcir; + uchar plic_p1gcir; + uchar plic_p2gcir; + uchar plic_p3gcir; + uchar plic_p0gcit; + uchar plic_p1gcit; + uchar plic_p2gcit; + uchar plic_p3gcit; + uchar res5[3]; + uchar plic_pgcitsr; + uchar res6[3]; + uchar plic_pdcsr; + ushort plic_p0psr; + ushort plic_p1psr; + ushort plic_p2psr; + ushort plic_p3psr; + ushort plic_pasr; + uchar res7; + uchar plic_plcr; + ushort res8; + ushort plic_pdrqr; + ushort plic_p0sdr; + ushort plic_p1sdr; + ushort plic_p2sdr; + ushort plic_p3sdr; + ushort res9; + ushort plic_pcsr; + uchar res10[1184]; } plic_t; -/* Fast ethernet controller registers - */ -typedef struct fec { - uint fec_ecntrl; /* ethernet control register */ - uint fec_ievent; /* interrupt event register */ - uint fec_imask; /* interrupt mask register */ - uint fec_ivec; /* interrupt level and vector status */ - uint fec_r_des_active; /* Rx ring updated flag */ - uint fec_x_des_active; /* Tx ring updated flag */ - uint res3[10]; /* reserved */ - uint fec_mii_data; /* MII data register */ - uint fec_mii_speed; /* MII speed control register */ - uint res4[17]; /* reserved */ - uint fec_r_bound; /* end of RAM (read-only) */ - uint fec_r_fstart; /* Rx FIFO start address */ - uint res5[6]; /* reserved */ - uint fec_x_fstart; /* Tx FIFO start address */ - uint res7[21]; /* reserved */ - uint fec_r_cntrl; /* Rx control register */ - uint fec_r_hash; /* Rx hash register */ - uint res8[14]; /* reserved */ - uint fec_x_cntrl; /* Tx control register */ - uint res9[0x9e]; /* reserved */ - uint fec_addr_low; /* lower 32 bits of station address */ - uint fec_addr_high; /* upper 16 bits of station address */ - uint fec_hash_table_high; /* upper 32-bits of hash table */ - uint fec_hash_table_low; /* lower 32-bits of hash table */ - uint fec_r_des_start; /* beginning of Rx descriptor ring */ - uint fec_x_des_start; /* beginning of Tx descriptor ring */ - uint fec_r_buff_size; /* Rx buffer size */ - uint res2[9]; /* reserved */ - uchar fec_fifo[960]; /* fifo RAM */ -} fec_t; - -/* USB module registers -*/ +/* USB module registers */ typedef struct usb { - ushort res1; - ushort usb_fnr; - ushort res2; - ushort usb_fnmr; - ushort res3; - ushort usb_rfmr; - ushort res4; - ushort usb_rfmmr; - uchar res5[3]; - uchar usb_far; - ulong usb_asr; - ulong usb_drr1; - ulong usb_drr2; - ushort res6; - ushort usb_specr; - ushort res7; - ushort usb_ep0sr; - ulong usb_iep0cfg; - ulong usb_oep0cfg; - ulong usb_ep1cfg; - ulong usb_ep2cfg; - ulong usb_ep3cfg; - ulong usb_ep4cfg; - ulong usb_ep5cfg; - ulong usb_ep6cfg; - ulong usb_ep7cfg; - ulong usb_ep0ctl; - ushort res8; - ushort usb_ep1ctl; - ushort res9; - ushort usb_ep2ctl; - ushort res10; - ushort usb_ep3ctl; - ushort res11; - ushort usb_ep4ctl; - ushort res12; - ushort usb_ep5ctl; - ushort res13; - ushort usb_ep6ctl; - ushort res14; - ushort usb_ep7ctl; - ulong usb_ep0isr; - ushort res15; - ushort usb_ep1isr; - ushort res16; - ushort usb_ep2isr; - ushort res17; - ushort usb_ep3isr; - ushort res18; - ushort usb_ep4isr; - ushort res19; - ushort usb_ep5isr; - ushort res20; - ushort usb_ep6isr; - ushort res21; - ushort usb_ep7isr; - ulong usb_ep0imr; - ushort res22; - ushort usb_ep1imr; - ushort res23; - ushort usb_ep2imr; - ushort res24; - ushort usb_ep3imr; - ushort res25; - ushort usb_ep4imr; - ushort res26; - ushort usb_ep5imr; - ushort res27; - ushort usb_ep6imr; - ushort res28; - ushort usb_ep7imr; - ulong usb_ep0dr; - ulong usb_ep1dr; - ulong usb_ep2dr; - ulong usb_ep3dr; - ulong usb_ep4dr; - ulong usb_ep5dr; - ulong usb_ep6dr; - ulong usb_ep7dr; - ushort res29; - ushort usb_ep0dpr; - ushort res30; - ushort usb_ep1dpr; - ushort res31; - ushort usb_ep2dpr; - ushort res32; - ushort usb_ep3dpr; - ushort res33; - ushort usb_ep4dpr; - ushort res34; - ushort usb_ep5dpr; - ushort res35; - ushort usb_ep6dpr; - ushort res36; - ushort usb_ep7dpr; - uchar res37[788]; - uchar usb_cfgram[1024]; + ushort res1; + ushort usb_fnr; + ushort res2; + ushort usb_fnmr; + ushort res3; + ushort usb_rfmr; + ushort res4; + ushort usb_rfmmr; + uchar res5[3]; + uchar usb_far; + ulong usb_asr; + ulong usb_drr1; + ulong usb_drr2; + ushort res6; + ushort usb_specr; + ushort res7; + ushort usb_ep0sr; + ulong usb_iep0cfg; + ulong usb_oep0cfg; + ulong usb_ep1cfg; + ulong usb_ep2cfg; + ulong usb_ep3cfg; + ulong usb_ep4cfg; + ulong usb_ep5cfg; + ulong usb_ep6cfg; + ulong usb_ep7cfg; + ulong usb_ep0ctl; + ushort res8; + ushort usb_ep1ctl; + ushort res9; + ushort usb_ep2ctl; + ushort res10; + ushort usb_ep3ctl; + ushort res11; + ushort usb_ep4ctl; + ushort res12; + ushort usb_ep5ctl; + ushort res13; + ushort usb_ep6ctl; + ushort res14; + ushort usb_ep7ctl; + ulong usb_ep0isr; + ushort res15; + ushort usb_ep1isr; + ushort res16; + ushort usb_ep2isr; + ushort res17; + ushort usb_ep3isr; + ushort res18; + ushort usb_ep4isr; + ushort res19; + ushort usb_ep5isr; + ushort res20; + ushort usb_ep6isr; + ushort res21; + ushort usb_ep7isr; + ulong usb_ep0imr; + ushort res22; + ushort usb_ep1imr; + ushort res23; + ushort usb_ep2imr; + ushort res24; + ushort usb_ep3imr; + ushort res25; + ushort usb_ep4imr; + ushort res26; + ushort usb_ep5imr; + ushort res27; + ushort usb_ep6imr; + ushort res28; + ushort usb_ep7imr; + ulong usb_ep0dr; + ulong usb_ep1dr; + ulong usb_ep2dr; + ulong usb_ep3dr; + ulong usb_ep4dr; + ulong usb_ep5dr; + ulong usb_ep6dr; + ulong usb_ep7dr; + ushort res29; + ushort usb_ep0dpr; + ushort res30; + ushort usb_ep1dpr; + ushort res31; + ushort usb_ep2dpr; + ushort res32; + ushort usb_ep3dpr; + ushort res33; + ushort usb_ep4dpr; + ushort res34; + ushort usb_ep5dpr; + ushort res35; + ushort usb_ep6dpr; + ushort res36; + ushort usb_ep7dpr; + uchar res37[788]; + uchar usb_cfgram[1024]; } usb_t; -/* Internal memory map. -*/ -typedef struct immap { - sysctrl_t sysctrl_reg; /* System configuration registers */ - intctrl_t intctrl_reg; /* Interrupt controller registers */ - csctrl_t csctrl_reg; /* Chip select controller registers */ - gpio_t gpio_reg; /* GPIO controller registers */ - qspi_t qspi_reg; /* QSPI controller registers */ - pwm_t pwm_reg; /* Pulse width modulation registers */ - dma_t dma_reg; /* DMA registers */ - uart_t uart_reg[2]; /* UART registers */ - sdramctrl_t sdram_reg; /* SDRAM controller registers */ - timer_t timer_reg[4]; /* Timer registers */ - wdog_t wdog_reg; /* Watchdog registers */ - plic_t plic_reg; /* Physical layer interface registers */ - fec_t fec_reg; /* Fast ethernet controller registers */ - usb_t usb_reg; /* USB controller registers */ -} immap_t; - -#endif /* __IMMAP_5272__ */ +#endif /* __IMMAP_5272__ */ diff --git a/include/asm-m68k/immap_5282.h b/include/asm-m68k/immap_5282.h index 6553b0869..e82960ac0 100644 --- a/include/asm-m68k/immap_5282.h +++ b/include/asm-m68k/immap_5282.h @@ -25,61 +25,168 @@ #ifndef __IMMAP_5282__ #define __IMMAP_5282__ -struct sys_ctrl { - uint ipsbar; - char res1[4]; - uint rambar; - char res2[4]; - uchar crsr; - uchar cwcr; - uchar lpicr; - uchar cwsr; - uint dmareqc; - char res3[4]; - uint mpark; +#define MMAP_SCM (CFG_MBAR + 0x00000000) +#define MMAP_SDRAMC (CFG_MBAR + 0x00000040) +#define MMAP_FBCS (CFG_MBAR + 0x00000080) +#define MMAP_DMA0 (CFG_MBAR + 0x00000100) +#define MMAP_DMA1 (CFG_MBAR + 0x00000140) +#define MMAP_DMA2 (CFG_MBAR + 0x00000180) +#define MMAP_DMA3 (CFG_MBAR + 0x000001C0) +#define MMAP_UART0 (CFG_MBAR + 0x00000200) +#define MMAP_UART1 (CFG_MBAR + 0x00000240) +#define MMAP_UART2 (CFG_MBAR + 0x00000280) +#define MMAP_I2C (CFG_MBAR + 0x00000300) +#define MMAP_QSPI (CFG_MBAR + 0x00000340) +#define MMAP_DTMR0 (CFG_MBAR + 0x00000400) +#define MMAP_DTMR1 (CFG_MBAR + 0x00000440) +#define MMAP_DTMR2 (CFG_MBAR + 0x00000480) +#define MMAP_DTMR3 (CFG_MBAR + 0x000004C0) +#define MMAP_INTC0 (CFG_MBAR + 0x00000C00) +#define MMAP_INTC1 (CFG_MBAR + 0x00000D00) +#define MMAP_INTCACK (CFG_MBAR + 0x00000F00) +#define MMAP_FEC (CFG_MBAR + 0x00001000) +#define MMAP_FECFIFO (CFG_MBAR + 0x00001400) +#define MMAP_GPIO (CFG_MBAR + 0x00100000) +#define MMAP_CCM (CFG_MBAR + 0x00110000) +#define MMAP_PLL (CFG_MBAR + 0x00120000) +#define MMAP_EPORT (CFG_MBAR + 0x00130000) +#define MMAP_WDOG (CFG_MBAR + 0x00140000) +#define MMAP_PIT0 (CFG_MBAR + 0x00150000) +#define MMAP_PIT1 (CFG_MBAR + 0x00160000) +#define MMAP_PIT2 (CFG_MBAR + 0x00170000) +#define MMAP_PIT3 (CFG_MBAR + 0x00180000) +#define MMAP_QADC (CFG_MBAR + 0x00190000) +#define MMAP_GPTMRA (CFG_MBAR + 0x001A0000) +#define MMAP_GPTMRB (CFG_MBAR + 0x001B0000) +#define MMAP_CAN (CFG_MBAR + 0x001C0000) +#define MMAP_CFMC (CFG_MBAR + 0x001D0000) +#define MMAP_CFMMEM (CFG_MBAR + 0x04000000) - /* TODO: finish these */ -}; +/* System Control Module */ +typedef struct scm_ctrl { + u32 ipsbar; + u32 res1; + u32 rambar; + u32 res2; + u8 crsr; + u8 cwcr; + u8 lpicr; + u8 cwsr; + u32 res3; + u8 mpark; + u8 res4[3]; + u8 pacr0; + u8 pacr1; + u8 pacr2; + u8 pacr3; + u8 pacr4; + u8 res5; + u8 pacr5; + u8 pacr6; + u8 pacr7; + u8 res6; + u8 pacr8; + u8 res7; + u8 gpacr0; + u8 gpacr1; + u16 res8; +} scm_t; -/* Fast ethernet controller registers - */ -typedef struct fec { - uint res1; /* reserved 1000*/ - uint fec_ievent; /* interrupt event register 1004*/ /* EIR */ - uint fec_imask; /* interrupt mask register 1008*/ /* EIMR */ - uint res2; /* reserved 100c*/ - uint fec_r_des_active; /* Rx ring updated flag 1010*/ /* RDAR */ - uint fec_x_des_active; /* Tx ring updated flag 1014*/ /* XDAR */ - uint res3[3]; /* reserved 1018*/ - uint fec_ecntrl; /* ethernet control register 1024*/ /* ECR */ - uint res4[6]; /* reserved 1028*/ - uint fec_mii_data; /* MII data register 1040*/ /* MDATA */ - uint fec_mii_speed; /* MII speed control register 1044*/ /* MSCR */ - /*1044*/ - uint res5[7]; /* reserved 1048*/ - uint fec_mibc; /* MIB Control/Status register 1064*/ /* MIBC */ - uint res6[7]; /* reserved 1068*/ - uint fec_r_cntrl; /* Rx control register 1084*/ /* RCR */ - uint res7[15]; /* reserved 1088*/ - uint fec_x_cntrl; /* Tx control register 10C4*/ /* TCR */ - uint res8[7]; /* reserved 10C8*/ - uint fec_addr_low; /* lower 32 bits of station address */ /* PALR */ - uint fec_addr_high; /* upper 16 bits of station address */ /* PAUR */ - uint fec_opd; /* opcode + pause duration 10EC*/ /* OPD */ - uint res9[10]; /* reserved 10F0*/ - uint fec_ihash_table_high; /* upper 32-bits of individual hash */ /* IAUR */ - uint fec_ihash_table_low; /* lower 32-bits of individual hash */ /* IALR */ - uint fec_ghash_table_high; /* upper 32-bits of group hash */ /* GAUR */ - uint fec_ghash_table_low; /* lower 32-bits of group hash */ /* GALR */ - uint res10[7]; /* reserved 1128*/ - uint fec_tfwr; /* Transmit FIFO watermark 1144*/ /* TFWR */ - uint res11; /* reserved 1148*/ - uint fec_r_bound; /* FIFO Receive Bound Register = end of */ /* FRBR */ - uint fec_r_fstart; /* FIFO Receive FIfo Start Registers = */ /* FRSR */ - uint res12[11]; /* reserved 1154*/ - uint fec_r_des_start;/* beginning of Rx descriptor ring 1180*/ /* ERDSR */ - uint fec_x_des_start;/* beginning of Tx descriptor ring 1184*/ /* ETDSR */ - uint fec_r_buff_size;/* Rx buffer size 1188*/ /* EMRBR */ -} fec_t; +/* Flexbus module Chip select registers */ +typedef struct fbcs_ctrl { + u16 csar0; /* 0x00 Chip-Select Address Register 0 */ + u16 res0; + u32 csmr0; /* 0x04 Chip-Select Mask Register 0 */ + u16 res1; /* 0x08 */ + u16 cscr0; /* 0x0A Chip-Select Control Register 0 */ -#endif /* __IMMAP_5282__ */ + u16 csar1; /* 0x0C Chip-Select Address Register 1 */ + u16 res2; + u32 csmr1; /* 0x10 Chip-Select Mask Register 1 */ + u16 res3; /* 0x14 */ + u16 cscr1; /* 0x16 Chip-Select Control Register 1 */ + + u16 csar2; /* 0x18 Chip-Select Address Register 2 */ + u16 res4; + u32 csmr2; /* 0x1C Chip-Select Mask Register 2 */ + u16 res5; /* 0x20 */ + u16 cscr2; /* 0x22 Chip-Select Control Register 2 */ + + u16 csar3; /* 0x24 Chip-Select Address Register 3 */ + u16 res6; + u32 csmr3; /* 0x28 Chip-Select Mask Register 3 */ + u16 res7; /* 0x2C */ + u16 cscr3; /* 0x2E Chip-Select Control Register 3 */ + + u16 csar4; /* 0x30 Chip-Select Address Register 4 */ + u16 res8; + u32 csmr4; /* 0x34 Chip-Select Mask Register 4 */ + u16 res9; /* 0x38 */ + u16 cscr4; /* 0x3A Chip-Select Control Register 4 */ + + u16 csar5; /* 0x3C Chip-Select Address Register 5 */ + u16 res10; + u32 csmr5; /* 0x40 Chip-Select Mask Register 5 */ + u16 res11; /* 0x44 */ + u16 cscr5; /* 0x46 Chip-Select Control Register 5 */ + + u16 csar6; /* 0x48 Chip-Select Address Register 5 */ + u16 res12; + u32 csmr6; /* 0x4C Chip-Select Mask Register 5 */ + u16 res13; /* 0x50 */ + u16 cscr6; /* 0x52 Chip-Select Control Register 5 */ + + u16 csar7; /* 0x54 Chip-Select Address Register 5 */ + u16 res14; + u32 csmr7; /* 0x58 Chip-Select Mask Register 5 */ + u16 res15; /* 0x5C */ + u16 cscr7; /* 0x5E Chip-Select Control Register 5 */ +} fbcs_t; + +/* Interrupt module registers */ +typedef struct int0_ctrl { + /* Interrupt Controller 0 */ + u32 iprh0; /* 0x00 Pending Register High */ + u32 iprl0; /* 0x04 Pending Register Low */ + u32 imrh0; /* 0x08 Mask Register High */ + u32 imrl0; /* 0x0C Mask Register Low */ + u32 frch0; /* 0x10 Force Register High */ + u32 frcl0; /* 0x14 Force Register Low */ + u8 irlr; /* 0x18 */ + u8 iacklpr; /* 0x19 */ + u16 res1[19]; /* 0x1a - 0x3c */ + u8 icr0[64]; /* 0x40 - 0x7F Control registers */ + u32 res3[24]; /* 0x80 - 0xDF */ + u8 swiack0; /* 0xE0 Software Interrupt Acknowledge */ + u8 res4[3]; /* 0xE1 - 0xE3 */ + u8 Lniack0_1; /* 0xE4 Level n interrupt acknowledge resister */ + u8 res5[3]; /* 0xE5 - 0xE7 */ + u8 Lniack0_2; /* 0xE8 Level n interrupt acknowledge resister */ + u8 res6[3]; /* 0xE9 - 0xEB */ + u8 Lniack0_3; /* 0xEC Level n interrupt acknowledge resister */ + u8 res7[3]; /* 0xED - 0xEF */ + u8 Lniack0_4; /* 0xF0 Level n interrupt acknowledge resister */ + u8 res8[3]; /* 0xF1 - 0xF3 */ + u8 Lniack0_5; /* 0xF4 Level n interrupt acknowledge resister */ + u8 res9[3]; /* 0xF5 - 0xF7 */ + u8 Lniack0_6; /* 0xF8 Level n interrupt acknowledge resister */ + u8 resa[3]; /* 0xF9 - 0xFB */ + u8 Lniack0_7; /* 0xFC Level n interrupt acknowledge resister */ + u8 resb[3]; /* 0xFD - 0xFF */ +} int0_t; + +/* Clock Module registers */ +typedef struct pll_ctrl { + u16 syncr; /* 0x00 synthesizer control register */ + u16 synsr; /* 0x02 synthesizer status register */ +} pll_t; + +/* Watchdog registers */ +typedef struct wdog_ctrl { + ushort wcr; + ushort wmr; + ushort wcntr; + ushort wsr; +} wdog_t; + +#endif /* __IMMAP_5282__ */ diff --git a/include/asm-m68k/m5249.h b/include/asm-m68k/m5249.h index 8c1b07755..5ed3cbc05 100644 --- a/include/asm-m68k/m5249.h +++ b/include/asm-m68k/m5249.h @@ -24,7 +24,6 @@ * MA 02111-1307 USA */ - #ifndef mcf5249_h #define mcf5249_h /****************************************************************************/ @@ -32,22 +31,21 @@ /* * useful definitions for reading/writing MBAR offset memory */ -#define mbar_readLong(x) *((volatile unsigned long *) (CFG_MBAR + x)) -#define mbar_writeLong(x,y) *((volatile unsigned long *) (CFG_MBAR + x)) = y -#define mbar_writeShort(x,y) *((volatile unsigned short *) (CFG_MBAR + x)) = y -#define mbar_writeByte(x,y) *((volatile unsigned char *) (CFG_MBAR + x)) = y -#define mbar2_readLong(x) *((volatile unsigned long *) (CFG_MBAR2 + x)) -#define mbar2_writeLong(x,y) *((volatile unsigned long *) (CFG_MBAR2 + x)) = y -#define mbar2_writeShort(x,y) *((volatile unsigned short *) (CFG_MBAR2 + x)) = y -#define mbar2_writeByte(x,y) *((volatile unsigned char *) (CFG_MBAR2 + x)) = y - +#define mbar_readLong(x) *((volatile unsigned long *) (CFG_MBAR + x)) +#define mbar_writeLong(x,y) *((volatile unsigned long *) (CFG_MBAR + x)) = y +#define mbar_writeShort(x,y) *((volatile unsigned short *) (CFG_MBAR + x)) = y +#define mbar_writeByte(x,y) *((volatile unsigned char *) (CFG_MBAR + x)) = y +#define mbar2_readLong(x) *((volatile unsigned long *) (CFG_MBAR2 + x)) +#define mbar2_writeLong(x,y) *((volatile unsigned long *) (CFG_MBAR2 + x)) = y +#define mbar2_writeShort(x,y) *((volatile unsigned short *) (CFG_MBAR2 + x)) = y +#define mbar2_writeByte(x,y) *((volatile unsigned char *) (CFG_MBAR2 + x)) = y /* * Size of internal RAM */ -#define INT_RAM_SIZE 32768 /* RAMBAR0 - 32k */ -#define INT_RAM_SIZE2 65536 /* RAMBAR1 - 64k */ +#define INT_RAM_SIZE 32768 /* RAMBAR0 - 32k */ +#define INT_RAM_SIZE2 65536 /* RAMBAR1 - 64k */ /* * Define the 5249 SIM register set addresses. @@ -56,51 +54,47 @@ /***************** ***** MBAR1 ***** *****************/ -#define MCFSIM_RSR 0x00 /* Reset Status reg (r/w) */ -#define MCFSIM_SYPCR 0x01 /* System Protection reg (r/w)*/ -#define MCFSIM_SWIVR 0x02 /* SW Watchdog intr reg (r/w) */ -#define MCFSIM_SWSR 0x03 /* SW Watchdog service (r/w) */ -#define MCFSIM_MPARK 0x0c /* Bus master park register (r/w) */ +#define MCFSIM_RSR 0x00 /* Reset Status reg (r/w) */ +#define MCFSIM_SYPCR 0x01 /* System Protection reg (r/w) */ +#define MCFSIM_SWIVR 0x02 /* SW Watchdog intr reg (r/w) */ +#define MCFSIM_SWSR 0x03 /* SW Watchdog service (r/w) */ +#define MCFSIM_MPARK 0x0c /* Bus master park register (r/w) */ -#define MCFSIM_SIMR 0x00 /* SIM Config reg (r/w) */ -#define MCFSIM_ICR0 0x4c /* Intr Ctrl reg 0 (r/w) */ -#define MCFSIM_ICR1 0x4d /* Intr Ctrl reg 1 (r/w) */ -#define MCFSIM_ICR2 0x4e /* Intr Ctrl reg 2 (r/w) */ -#define MCFSIM_ICR3 0x4f /* Intr Ctrl reg 3 (r/w) */ -#define MCFSIM_ICR4 0x50 /* Intr Ctrl reg 4 (r/w) */ -#define MCFSIM_ICR5 0x51 /* Intr Ctrl reg 5 (r/w) */ -#define MCFSIM_ICR6 0x52 /* Intr Ctrl reg 6 (r/w) */ -#define MCFSIM_ICR7 0x53 /* Intr Ctrl reg 7 (r/w) */ -#define MCFSIM_ICR8 0x54 /* Intr Ctrl reg 8 (r/w) */ -#define MCFSIM_ICR9 0x55 /* Intr Ctrl reg 9 (r/w) */ -#define MCFSIM_ICR10 0x56 /* Intr Ctrl reg 10 (r/w) */ -#define MCFSIM_ICR11 0x57 /* Intr Ctrl reg 11 (r/w) */ +#define MCFSIM_SIMR 0x00 /* SIM Config reg (r/w) */ +#define MCFSIM_ICR0 0x4c /* Intr Ctrl reg 0 (r/w) */ +#define MCFSIM_ICR1 0x4d /* Intr Ctrl reg 1 (r/w) */ +#define MCFSIM_ICR2 0x4e /* Intr Ctrl reg 2 (r/w) */ +#define MCFSIM_ICR3 0x4f /* Intr Ctrl reg 3 (r/w) */ +#define MCFSIM_ICR4 0x50 /* Intr Ctrl reg 4 (r/w) */ +#define MCFSIM_ICR5 0x51 /* Intr Ctrl reg 5 (r/w) */ +#define MCFSIM_ICR6 0x52 /* Intr Ctrl reg 6 (r/w) */ +#define MCFSIM_ICR7 0x53 /* Intr Ctrl reg 7 (r/w) */ +#define MCFSIM_ICR8 0x54 /* Intr Ctrl reg 8 (r/w) */ +#define MCFSIM_ICR9 0x55 /* Intr Ctrl reg 9 (r/w) */ +#define MCFSIM_ICR10 0x56 /* Intr Ctrl reg 10 (r/w) */ +#define MCFSIM_ICR11 0x57 /* Intr Ctrl reg 11 (r/w) */ -#define MCFSIM_IPR 0x40 /* Interrupt Pend reg (r/w) */ -#define MCFSIM_IMR 0x44 /* Interrupt Mask reg (r/w) */ +#define MCFSIM_IPR 0x40 /* Interrupt Pend reg (r/w) */ +#define MCFSIM_IMR 0x44 /* Interrupt Mask reg (r/w) */ -#define MCFSIM_CSAR0 0x80 /* CS 0 Address 0 reg (r/w) */ -#define MCFSIM_CSMR0 0x84 /* CS 0 Mask 0 reg (r/w) */ -#define MCFSIM_CSCR0 0x8a /* CS 0 Control reg (r/w) */ -#define MCFSIM_CSAR1 0x8c /* CS 1 Address reg (r/w) */ -#define MCFSIM_CSMR1 0x90 /* CS 1 Mask reg (r/w) */ -#define MCFSIM_CSCR1 0x96 /* CS 1 Control reg (r/w) */ -#define MCFSIM_CSAR2 0x98 /* CS 2 Address reg (r/w) */ -#define MCFSIM_CSMR2 0x9c /* CS 2 Mask reg (r/w) */ -#define MCFSIM_CSCR2 0xa2 /* CS 2 Control reg (r/w) */ -#define MCFSIM_CSAR3 0xa4 /* CS 3 Address reg (r/w) */ -#define MCFSIM_CSMR3 0xa8 /* CS 3 Mask reg (r/w) */ -#define MCFSIM_CSCR3 0xae /* CS 3 Control reg (r/w) */ +#define MCFSIM_CSAR0 0x80 /* CS 0 Address 0 reg (r/w) */ +#define MCFSIM_CSMR0 0x84 /* CS 0 Mask 0 reg (r/w) */ +#define MCFSIM_CSCR0 0x8a /* CS 0 Control reg (r/w) */ +#define MCFSIM_CSAR1 0x8c /* CS 1 Address reg (r/w) */ +#define MCFSIM_CSMR1 0x90 /* CS 1 Mask reg (r/w) */ +#define MCFSIM_CSCR1 0x96 /* CS 1 Control reg (r/w) */ +#define MCFSIM_CSAR2 0x98 /* CS 2 Address reg (r/w) */ +#define MCFSIM_CSMR2 0x9c /* CS 2 Mask reg (r/w) */ +#define MCFSIM_CSCR2 0xa2 /* CS 2 Control reg (r/w) */ +#define MCFSIM_CSAR3 0xa4 /* CS 3 Address reg (r/w) */ +#define MCFSIM_CSMR3 0xa8 /* CS 3 Mask reg (r/w) */ +#define MCFSIM_CSCR3 0xae /* CS 3 Control reg (r/w) */ -#define MCFSIM_DCR 0x100 /* DRAM Control reg (r/w) */ -#define MCFSIM_DACR0 0x108 /* DRAM 0 Addr and Ctrl (r/w) */ -#define MCFSIM_DMR0 0x10c /* DRAM 0 Mask reg (r/w) */ -#define MCFSIM_DACR1 0x110 /* DRAM 1 Addr and Ctrl (r/w) */ -#define MCFSIM_DMR1 0x114 /* DRAM 1 Mask reg (r/w) */ - -/** UART Bases **/ -#define MCFUART_BASE1 0x1c0 /* Base address of UART1 */ -#define MCFUART_BASE2 0x200 /* Base address of UART2 */ +#define MCFSIM_DCR 0x100 /* DRAM Control reg (r/w) */ +#define MCFSIM_DACR0 0x108 /* DRAM 0 Addr and Ctrl (r/w) */ +#define MCFSIM_DMR0 0x10c /* DRAM 0 Mask reg (r/w) */ +#define MCFSIM_DACR1 0x110 /* DRAM 1 Addr and Ctrl (r/w) */ +#define MCFSIM_DMR1 0x114 /* DRAM 1 Mask reg (r/w) */ /***************** ***** MBAR2 ***** @@ -109,39 +103,39 @@ /* GPIO Addresses * Note: These are offset from MBAR2! */ -#define MCFSIM_GPIO_READ 0x00 /* Read-Only access to gpio 0-31 (MBAR2) (r) */ -#define MCFSIM_GPIO_OUT 0x04 /* Output register for gpio 0-31 (MBAR2) (r/w)*/ -#define MCFSIM_GPIO_EN 0x08 /* gpio 0-31 enable (r/w)*/ -#define MCFSIM_GPIO_FUNC 0x0c /* gpio 0-31 function select (r/w) */ -#define MCFSIM_GPIO1_READ 0xb0 /* Read-Only access to gpio 32-63 (MBAR2) (r) */ -#define MCFSIM_GPIO1_OUT 0xb4 /* Output register for gpio 32-63 (MBAR2) (r/w) */ -#define MCFSIM_GPIO1_EN 0xb8 /* gpio 32-63 enable (r/w) */ -#define MCFSIM_GPIO1_FUNC 0xbc /* gpio 32-63 function select (r/w) */ +#define MCFSIM_GPIO_READ 0x00 /* Read-Only access to gpio 0-31 (MBAR2) (r) */ +#define MCFSIM_GPIO_OUT 0x04 /* Output register for gpio 0-31 (MBAR2) (r/w) */ +#define MCFSIM_GPIO_EN 0x08 /* gpio 0-31 enable (r/w) */ +#define MCFSIM_GPIO_FUNC 0x0c /* gpio 0-31 function select (r/w) */ +#define MCFSIM_GPIO1_READ 0xb0 /* Read-Only access to gpio 32-63 (MBAR2) (r) */ +#define MCFSIM_GPIO1_OUT 0xb4 /* Output register for gpio 32-63 (MBAR2) (r/w) */ +#define MCFSIM_GPIO1_EN 0xb8 /* gpio 32-63 enable (r/w) */ +#define MCFSIM_GPIO1_FUNC 0xbc /* gpio 32-63 function select (r/w) */ -#define MCFSIM_GPIO_INT_STAT 0xc0 /* Secondary Interrupt status (r) */ -#define MCFSIM_GPIO_INT_CLEAR 0xc0 /* Secondary Interrupt status (w) */ -#define MCFSIM_GPIO_INT_EN 0xc4 /* Secondary Interrupt status (r/w) */ +#define MCFSIM_GPIO_INT_STAT 0xc0 /* Secondary Interrupt status (r) */ +#define MCFSIM_GPIO_INT_CLEAR 0xc0 /* Secondary Interrupt status (w) */ +#define MCFSIM_GPIO_INT_EN 0xc4 /* Secondary Interrupt status (r/w) */ -#define MCFSIM_INT_STAT3 0xe0 /* 3rd Interrupt ctrl status (r) */ -#define MCFSIM_INT_CLEAR3 0xe0 /* 3rd Interrupt ctrl clear (w) */ -#define MCFSIM_INT_EN3 0xe4 /* 3rd Interrupt ctrl enable (r/w) */ +#define MCFSIM_INT_STAT3 0xe0 /* 3rd Interrupt ctrl status (r) */ +#define MCFSIM_INT_CLEAR3 0xe0 /* 3rd Interrupt ctrl clear (w) */ +#define MCFSIM_INT_EN3 0xe4 /* 3rd Interrupt ctrl enable (r/w) */ -#define MCFSIM_INTLEV1 0x140 /* Interrupts 0 - 7 (r/w) */ -#define MCFSIM_INTLEV2 0x144 /* Interrupts 8 -15 (r/w) */ -#define MCFSIM_INTLEV3 0x148 /* Interrupts 16-23 (r/w) */ -#define MCFSIM_INTLEV4 0x14c /* Interrupts 24-31 (r/w) */ -#define MCFSIM_INTLEV5 0x150 /* Interrupts 32-39 (r/w) */ -#define MCFSIM_INTLEV6 0x154 /* Interrupts 40-47 (r/w) */ -#define MCFSIM_INTLEV7 0x158 /* Interrupts 48-55 (r/w) */ -#define MCFSIM_INTLEV8 0x15c /* Interrupts 56-63 (r/w) */ +#define MCFSIM_INTLEV1 0x140 /* Interrupts 0 - 7 (r/w) */ +#define MCFSIM_INTLEV2 0x144 /* Interrupts 8 -15 (r/w) */ +#define MCFSIM_INTLEV3 0x148 /* Interrupts 16-23 (r/w) */ +#define MCFSIM_INTLEV4 0x14c /* Interrupts 24-31 (r/w) */ +#define MCFSIM_INTLEV5 0x150 /* Interrupts 32-39 (r/w) */ +#define MCFSIM_INTLEV6 0x154 /* Interrupts 40-47 (r/w) */ +#define MCFSIM_INTLEV7 0x158 /* Interrupts 48-55 (r/w) */ +#define MCFSIM_INTLEV8 0x15c /* Interrupts 56-63 (r/w) */ -#define MCFSIM_SPURVEC 0x167 /* Spurious Vector Register (r/w) */ -#define MCFSIM_INTBASE 0x16b /* Software interrupt base address (r/w) */ +#define MCFSIM_SPURVEC 0x167 /* Spurious Vector Register (r/w) */ +#define MCFSIM_INTBASE 0x16b /* Software interrupt base address (r/w) */ -#define MCFSIM_IDECONFIG1 0x18c /* IDE config register 1 (r/w) */ -#define MCFSIM_IDECONFIG2 0x190 /* IDE config register 1 (r/w) */ +#define MCFSIM_IDECONFIG1 0x18c /* IDE config register 1 (r/w) */ +#define MCFSIM_IDECONFIG2 0x190 /* IDE config register 1 (r/w) */ -#define MCFSIM_PLLCR 0x180 /* PLL Control register */ +#define MCFSIM_PLLCR 0x180 /* PLL Control register */ /* * Some symbol defines for the above... @@ -158,21 +152,20 @@ /* * Bit definitions for the ICR family of registers. */ -#define MCFSIM_ICR_AUTOVEC 0x80 /* Auto-vectored intr */ -#define MCFSIM_ICR_LEVEL0 0x00 /* Level 0 intr */ -#define MCFSIM_ICR_LEVEL1 0x04 /* Level 1 intr */ -#define MCFSIM_ICR_LEVEL2 0x08 /* Level 2 intr */ -#define MCFSIM_ICR_LEVEL3 0x0c /* Level 3 intr */ -#define MCFSIM_ICR_LEVEL4 0x10 /* Level 4 intr */ -#define MCFSIM_ICR_LEVEL5 0x14 /* Level 5 intr */ -#define MCFSIM_ICR_LEVEL6 0x18 /* Level 6 intr */ -#define MCFSIM_ICR_LEVEL7 0x1c /* Level 7 intr */ - -#define MCFSIM_ICR_PRI0 0x00 /* Priority 0 intr */ -#define MCFSIM_ICR_PRI1 0x01 /* Priority 1 intr */ -#define MCFSIM_ICR_PRI2 0x02 /* Priority 2 intr */ -#define MCFSIM_ICR_PRI3 0x03 /* Priority 3 intr */ +#define MCFSIM_ICR_AUTOVEC 0x80 /* Auto-vectored intr */ +#define MCFSIM_ICR_LEVEL0 0x00 /* Level 0 intr */ +#define MCFSIM_ICR_LEVEL1 0x04 /* Level 1 intr */ +#define MCFSIM_ICR_LEVEL2 0x08 /* Level 2 intr */ +#define MCFSIM_ICR_LEVEL3 0x0c /* Level 3 intr */ +#define MCFSIM_ICR_LEVEL4 0x10 /* Level 4 intr */ +#define MCFSIM_ICR_LEVEL5 0x14 /* Level 5 intr */ +#define MCFSIM_ICR_LEVEL6 0x18 /* Level 6 intr */ +#define MCFSIM_ICR_LEVEL7 0x1c /* Level 7 intr */ +#define MCFSIM_ICR_PRI0 0x00 /* Priority 0 intr */ +#define MCFSIM_ICR_PRI1 0x01 /* Priority 1 intr */ +#define MCFSIM_ICR_PRI2 0x02 /* Priority 2 intr */ +#define MCFSIM_ICR_PRI3 0x03 /* Priority 3 intr */ /* * Macros to read/set IMR register. It is 32 bits on the 5249. @@ -184,4 +177,4 @@ #define mcf_setimr(imr) \ *((volatile unsigned long *) (MCF_MBAR + MCFSIM_IMR)) = (imr); -#endif /* mcf5249_h */ +#endif /* mcf5249_h */ diff --git a/include/asm-m68k/m5271.h b/include/asm-m68k/m5271.h index e0f02cf7f..be343987f 100644 --- a/include/asm-m68k/m5271.h +++ b/include/asm-m68k/m5271.h @@ -25,7 +25,6 @@ * MA 02111-1307 USA */ - #ifndef _MCF5271_H_ #define _MCF5271_H_ @@ -91,7 +90,7 @@ #define MCF_GPIO_PAR_UART_U1RXD_UART1 0x0C00 #define MCF_GPIO_PAR_UART_U1TXD_UART1 0x0300 -#define MCF_GPIO_PAR_SDRAM_PAR_CSSDCS(x) (((x)&0x03)<<6) +#define MCF_GPIO_PAR_SDRAM_PAR_CSSDCS(x) (((x)&0x03)<<6) #define MCF_SDRAMC_DCR 0x000040 #define MCF_SDRAMC_DACR0 0x000048 @@ -117,4 +116,104 @@ #define MCFSIM_ICR1 0x000C41 -#endif /* _MCF5271_H_ */ +/********************************************************************* +* Interrupt Controller (INTC) +*********************************************************************/ +#define INT0_LO_RSVD0 (0) +#define INT0_LO_EPORT1 (1) +#define INT0_LO_EPORT2 (2) +#define INT0_LO_EPORT3 (3) +#define INT0_LO_EPORT4 (4) +#define INT0_LO_EPORT5 (5) +#define INT0_LO_EPORT6 (6) +#define INT0_LO_EPORT7 (7) +#define INT0_LO_SCM (8) +#define INT0_LO_DMA0 (9) +#define INT0_LO_DMA1 (10) +#define INT0_LO_DMA2 (11) +#define INT0_LO_DMA3 (12) +#define INT0_LO_UART0 (13) +#define INT0_LO_UART1 (14) +#define INT0_LO_UART2 (15) +#define INT0_LO_RSVD1 (16) +#define INT0_LO_I2C (17) +#define INT0_LO_QSPI (18) +#define INT0_LO_DTMR0 (19) +#define INT0_LO_DTMR1 (20) +#define INT0_LO_DTMR2 (21) +#define INT0_LO_DTMR3 (22) +#define INT0_LO_FEC_TXF (23) +#define INT0_LO_FEC_TXB (24) +#define INT0_LO_FEC_UN (25) +#define INT0_LO_FEC_RL (26) +#define INT0_LO_FEC_RXF (27) +#define INT0_LO_FEC_RXB (28) +#define INT0_LO_FEC_MII (29) +#define INT0_LO_FEC_LC (30) +#define INT0_LO_FEC_HBERR (31) +#define INT0_HI_FEC_GRA (32) +#define INT0_HI_FEC_EBERR (33) +#define INT0_HI_FEC_BABT (34) +#define INT0_HI_FEC_BABR (35) +#define INT0_HI_PIT0 (36) +#define INT0_HI_PIT1 (37) +#define INT0_HI_PIT2 (38) +#define INT0_HI_PIT3 (39) +#define INT0_HI_RNG (40) +#define INT0_HI_SKHA (41) +#define INT0_HI_MDHA (42) +#define INT0_HI_CAN1_BUF0I (43) +#define INT0_HI_CAN1_BUF1I (44) +#define INT0_HI_CAN1_BUF2I (45) +#define INT0_HI_CAN1_BUF3I (46) +#define INT0_HI_CAN1_BUF4I (47) +#define INT0_HI_CAN1_BUF5I (48) +#define INT0_HI_CAN1_BUF6I (49) +#define INT0_HI_CAN1_BUF7I (50) +#define INT0_HI_CAN1_BUF8I (51) +#define INT0_HI_CAN1_BUF9I (52) +#define INT0_HI_CAN1_BUF10I (53) +#define INT0_HI_CAN1_BUF11I (54) +#define INT0_HI_CAN1_BUF12I (55) +#define INT0_HI_CAN1_BUF13I (56) +#define INT0_HI_CAN1_BUF14I (57) +#define INT0_HI_CAN1_BUF15I (58) +#define INT0_HI_CAN1_ERRINT (59) +#define INT0_HI_CAN1_BOFFINT (60) +/* 60-63 Reserved */ + +/* Bit definitions and macros for INTC_IPRL */ +#define INTC_IPRL_INT31 (0x80000000) +#define INTC_IPRL_INT30 (0x40000000) +#define INTC_IPRL_INT29 (0x20000000) +#define INTC_IPRL_INT28 (0x10000000) +#define INTC_IPRL_INT27 (0x08000000) +#define INTC_IPRL_INT26 (0x04000000) +#define INTC_IPRL_INT25 (0x02000000) +#define INTC_IPRL_INT24 (0x01000000) +#define INTC_IPRL_INT23 (0x00800000) +#define INTC_IPRL_INT22 (0x00400000) +#define INTC_IPRL_INT21 (0x00200000) +#define INTC_IPRL_INT20 (0x00100000) +#define INTC_IPRL_INT19 (0x00080000) +#define INTC_IPRL_INT18 (0x00040000) +#define INTC_IPRL_INT17 (0x00020000) +#define INTC_IPRL_INT16 (0x00010000) +#define INTC_IPRL_INT15 (0x00008000) +#define INTC_IPRL_INT14 (0x00004000) +#define INTC_IPRL_INT13 (0x00002000) +#define INTC_IPRL_INT12 (0x00001000) +#define INTC_IPRL_INT11 (0x00000800) +#define INTC_IPRL_INT10 (0x00000400) +#define INTC_IPRL_INT9 (0x00000200) +#define INTC_IPRL_INT8 (0x00000100) +#define INTC_IPRL_INT7 (0x00000080) +#define INTC_IPRL_INT6 (0x00000040) +#define INTC_IPRL_INT5 (0x00000020) +#define INTC_IPRL_INT4 (0x00000010) +#define INTC_IPRL_INT3 (0x00000008) +#define INTC_IPRL_INT2 (0x00000004) +#define INTC_IPRL_INT1 (0x00000002) +#define INTC_IPRL_INT0 (0x00000001) + +#endif /* _MCF5271_H_ */ diff --git a/include/asm-m68k/m5272.h b/include/asm-m68k/m5272.h index 54d4a3209..895f89df7 100644 --- a/include/asm-m68k/m5272.h +++ b/include/asm-m68k/m5272.h @@ -24,7 +24,6 @@ * MA 02111-1307 USA */ - #ifndef mcf5272_h #define mcf5272_h /****************************************************************************/ @@ -35,65 +34,173 @@ #define INT_RAM_SIZE 4096 +#define GPIO_PACNT_PA15MSK (0xC0000000) +#define GPIO_PACNT_DGNT1 (0x40000000) +#define GPIO_PACNT_PA14MSK (0x30000000) +#define GPIO_PACNT_DREQ1 (0x10000000) +#define GPIO_PACNT_PA13MSK (0x0C000000) +#define GPIO_PACNT_DFSC3 (0x04000000) +#define GPIO_PACNT_PA12MSK (0x03000000) +#define GPIO_PACNT_DFSC2 (0x01000000) +#define GPIO_PACNT_PA11MSK (0x00C00000) +#define GPIO_PACNT_QSPI_CS1 (0x00800000) +#define GPIO_PACNT_PA10MSK (0x00300000) +#define GPIO_PACNT_DREQ0 (0x00100000) +#define GPIO_PACNT_PA9MSK (0x000C0000) +#define GPIO_PACNT_DGNT0 (0x00040000) +#define GPIO_PACNT_PA8MSK (0x00030000) +#define GPIO_PACNT_FSC0 (0x00010000) +#define GPIO_PACNT_FSR0 (0x00010000) +#define GPIO_PACNT_PA7MSK (0x0000C000) +#define GPIO_PACNT_DOUT3 (0x00008000) +#define GPIO_PACNT_QSPI_CS3 (0x00004000) +#define GPIO_PACNT_PA6MSK (0x00003000) +#define GPIO_PACNT_USB_RXD (0x00001000) +#define GPIO_PACNT_PA5MSK (0x00000C00) +#define GPIO_PACNT_USB_TXEN (0x00000400) +#define GPIO_PACNT_PA4MSK (0x00000300) +#define GPIO_PACNT_USB_SUSP (0x00000100) +#define GPIO_PACNT_PA3MSK (0x000000C0) +#define GPIO_PACNT_USB_TN (0x00000040) +#define GPIO_PACNT_PA2MSK (0x00000030) +#define GPIO_PACNT_USB_RN (0x00000010) +#define GPIO_PACNT_PA1MSK (0x0000000C) +#define GPIO_PACNT_USB_RP (0x00000004) +#define GPIO_PACNT_PA0MSK (0x00000003) +#define GPIO_PACNT_USB_TP (0x00000001) -/* - * Define the 5272 SIM register set addresses. - */ -#define MCFSIM_SCR 0x04 /* SIM Config reg (r/w) */ -#define MCFSIM_SPR 0x06 /* System Protection reg (r/w)*/ -#define MCFSIM_PMR 0x08 /* Power Management reg (r/w) */ -#define MCFSIM_APMR 0x0e /* Active Low Power reg (r/w) */ -#define MCFSIM_DIR 0x10 /* Device Identity reg (r/w) */ +#define GPIO_PBCNT_PB15MSK (0xC0000000) +#define GPIO_PBCNT_E_MDC (0x40000000) +#define GPIO_PBCNT_PB14MSK (0x30000000) +#define GPIO_PBCNT_E_RXER (0x10000000) +#define GPIO_PBCNT_PB13MSK (0x0C000000) +#define GPIO_PBCNT_E_RXD1 (0x04000000) +#define GPIO_PBCNT_PB12MSK (0x03000000) +#define GPIO_PBCNT_E_RXD2 (0x01000000) +#define GPIO_PBCNT_PB11MSK (0x00C00000) +#define GPIO_PBCNT_E_RXD3 (0x00400000) +#define GPIO_PBCNT_PB10MSK (0x00300000) +#define GPIO_PBCNT_E_TXD1 (0x00100000) +#define GPIO_PBCNT_PB9MSK (0x000C0000) +#define GPIO_PBCNT_E_TXD2 (0x00040000) +#define GPIO_PBCNT_PB8MSK (0x00030000) +#define GPIO_PBCNT_E_TXD3 (0x00010000) +#define GPIO_PBCNT_PB7MSK (0x0000C000) +#define GPIO_PBCNT_TOUT0 (0x00004000) +#define GPIO_PBCNT_PB6MSK (0x00003000) +#define GPIO_PBCNT_TA (0x00001000) +#define GPIO_PBCNT_PB4MSK (0x00000300) +#define GPIO_PBCNT_URT0_CLK (0x00000100) +#define GPIO_PBCNT_PB3MSK (0x000000C0) +#define GPIO_PBCNT_URT0_RTS (0x00000040) +#define GPIO_PBCNT_PB2MSK (0x00000030) +#define GPIO_PBCNT_URT0_CTS (0x00000010) +#define GPIO_PBCNT_PB1MSK (0x0000000C) +#define GPIO_PBCNT_URT0_RXD (0x00000004) +#define GPIO_PBCNT_URT0_TIN2 (0x00000004) +#define GPIO_PBCNT_PB0MSK (0x00000003) +#define GPIO_PBCNT_URT0_TXD (0x00000001) -#define MCFSIM_ICR1 0x20 /* Intr Ctrl reg 1 (r/w) */ -#define MCFSIM_ICR2 0x24 /* Intr Ctrl reg 2 (r/w) */ -#define MCFSIM_ICR3 0x28 /* Intr Ctrl reg 3 (r/w) */ -#define MCFSIM_ICR4 0x2c /* Intr Ctrl reg 4 (r/w) */ +#define GPIO_PDCNT_PD7MSK (0x0000C000) +#define GPIO_PDCNT_TIN1 (0x00008000) +#define GPIO_PDCNT_PWM_OUT2 (0x00004000) +#define GPIO_PDCNT_PD6MSK (0x00003000) +#define GPIO_PDCNT_TOUT1 (0x00002000) +#define GPIO_PDCNT_PWM_OUT1 (0x00001000) +#define GPIO_PDCNT_PD5MSK (0x00000C00) +#define GPIO_PDCNT_INT4 (0x00000C00) +#define GPIO_PDCNT_DIN3 (0x00000800) +#define GPIO_PDCNT_PD4MSK (0x00000300) +#define GPIO_PDCNT_URT1_TXD (0x00000200) +#define GPIO_PDCNT_DOUT0 (0x00000100) +#define GPIO_PDCNT_PD3MSK (0x000000C0) +#define GPIO_PDCNT_INT5 (0x000000C0) +#define GPIO_PDCNT_URT1_RTS (0x00000080) +#define GPIO_PDCNT_PD2MSK (0x00000030) +#define GPIO_PDCNT_QSPI_CS2 (0x00000030) +#define GPIO_PDCNT_URT1_CTS (0x00000020) +#define GPIO_PDCNT_PD1MSK (0x0000000C) +#define GPIO_PDCNT_URT1_RXD (0x00000008) +#define GPIO_PDCNT_URT1_TIN3 (0x00000008) +#define GPIO_PDCNT_DIN0 (0x00000004) +#define GPIO_PDCNT_PD0MSK (0x00000003) +#define GPIO_PDCNT_URT1_CLK (0x00000002) +#define GPIO_PDCNT_DCL0 (0x00000001) -#define MCFSIM_ISR 0x30 /* Interrupt Source reg (r/w) */ -#define MCFSIM_PITR 0x34 /* Interrupt Transition (r/w) */ -#define MCFSIM_PIWR 0x38 /* Interrupt Wakeup reg (r/w) */ -#define MCFSIM_PIVR 0x3f /* Interrupt Vector reg (r/w( */ +#define INT_RSVD0 (0) +#define INT_INT1 (1) +#define INT_INT2 (2) +#define INT_INT3 (3) +#define INT_INT4 (4) +#define INT_TMR0 (5) +#define INT_TMR1 (6) +#define INT_TMR2 (7) +#define INT_TMR3 (8) +#define INT_UART1 (9) +#define INT_UART2 (10) +#define INT_PLIP (11) +#define INT_PLIA (12) +#define INT_USB0 (13) +#define INT_USB1 (14) +#define INT_USB2 (15) +#define INT_USB3 (16) +#define INT_USB4 (17) +#define INT_USB5 (18) +#define INT_USB6 (19) +#define INT_USB7 (20) +#define INT_DMA (21) +#define INT_ERX (22) +#define INT_ETX (23) +#define INT_ENTC (24) +#define INT_QSPI (25) +#define INT_INT5 (26) +#define INT_INT6 (27) +#define INT_SWTO (28) -#define MCFSIM_WRRR 0x280 /* Watchdog reference (r/w) */ -#define MCFSIM_WIRR 0x284 /* Watchdog interrupt (r/w) */ -#define MCFSIM_WCR 0x288 /* Watchdog counter (r/w) */ -#define MCFSIM_WER 0x28c /* Watchdog event (r/w) */ +#define INT_ICR1_TMR0MASK (0x000F000) +#define INT_ICR1_TMR0PI (0x0008000) +#define INT_ICR1_TMR0IPL(x) (((x)&0x7)<<12) +#define INT_ICR1_TMR1MASK (0x0000F00) +#define INT_ICR1_TMR1PI (0x0000800) +#define INT_ICR1_TMR1IPL(x) (((x)&0x7)<<8) +#define INT_ICR1_TMR2MASK (0x00000F0) +#define INT_ICR1_TMR2PI (0x0000080) +#define INT_ICR1_TMR2IPL(x) (((x)&0x7)<<4) +#define INT_ICR1_TMR3MASK (0x000000F) +#define INT_ICR1_TMR3PI (0x0000008) +#define INT_ICR1_TMR3IPL(x) (((x)&0x7)) -#define MCFSIM_CSBR0 0x40 /* CS0 Base Address (r/w) */ -#define MCFSIM_CSOR0 0x44 /* CS0 Option (r/w) */ -#define MCFSIM_CSBR1 0x48 /* CS1 Base Address (r/w) */ -#define MCFSIM_CSOR1 0x4c /* CS1 Option (r/w) */ -#define MCFSIM_CSBR2 0x50 /* CS2 Base Address (r/w) */ -#define MCFSIM_CSOR2 0x54 /* CS2 Option (r/w) */ -#define MCFSIM_CSBR3 0x58 /* CS3 Base Address (r/w) */ -#define MCFSIM_CSOR3 0x5c /* CS3 Option (r/w) */ -#define MCFSIM_CSBR4 0x60 /* CS4 Base Address (r/w) */ -#define MCFSIM_CSOR4 0x64 /* CS4 Option (r/w) */ -#define MCFSIM_CSBR5 0x68 /* CS5 Base Address (r/w) */ -#define MCFSIM_CSOR5 0x6c /* CS5 Option (r/w) */ -#define MCFSIM_CSBR6 0x70 /* CS6 Base Address (r/w) */ -#define MCFSIM_CSOR6 0x74 /* CS6 Option (r/w) */ -#define MCFSIM_CSBR7 0x78 /* CS7 Base Address (r/w) */ -#define MCFSIM_CSOR7 0x7c /* CS7 Option (r/w) */ +#define INT_ISR_INT31 (0x80000000) +#define INT_ISR_INT30 (0x40000000) +#define INT_ISR_INT29 (0x20000000) +#define INT_ISR_INT28 (0x10000000) +#define INT_ISR_INT27 (0x08000000) +#define INT_ISR_INT26 (0x04000000) +#define INT_ISR_INT25 (0x02000000) +#define INT_ISR_INT24 (0x01000000) +#define INT_ISR_INT23 (0x00800000) +#define INT_ISR_INT22 (0x00400000) +#define INT_ISR_INT21 (0x00200000) +#define INT_ISR_INT20 (0x00100000) +#define INT_ISR_INT19 (0x00080000) +#define INT_ISR_INT18 (0x00040000) +#define INT_ISR_INT17 (0x00020000) +#define INT_ISR_INT16 (0x00010000) +#define INT_ISR_INT15 (0x00008000) +#define INT_ISR_INT14 (0x00004000) +#define INT_ISR_INT13 (0x00002000) +#define INT_ISR_INT12 (0x00001000) +#define INT_ISR_INT11 (0x00000800) +#define INT_ISR_INT10 (0x00000400) +#define INT_ISR_INT9 (0x00000200) +#define INT_ISR_INT8 (0x00000100) +#define INT_ISR_INT7 (0x00000080) +#define INT_ISR_INT6 (0x00000040) +#define INT_ISR_INT5 (0x00000020) +#define INT_ISR_INT4 (0x00000010) +#define INT_ISR_INT3 (0x00000008) +#define INT_ISR_INT2 (0x00000004) +#define INT_ISR_INT1 (0x00000002) +#define INT_ISR_INT0 (0x00000001) -#define MCFSIM_SDCR 0x180 /* SDRAM Configuration (r/w) */ -#define MCFSIM_SDTR 0x184 /* SDRAM Timing (r/w) */ -#define MCFSIM_DCAR0 0x4c /* DRAM 0 Address reg(r/w) */ -#define MCFSIM_DCMR0 0x50 /* DRAM 0 Mask reg (r/w) */ -#define MCFSIM_DCCR0 0x57 /* DRAM 0 Control reg (r/w) */ -#define MCFSIM_DCAR1 0x58 /* DRAM 1 Address reg (r/w) */ -#define MCFSIM_DCMR1 0x5c /* DRAM 1 Mask reg (r/w) */ -#define MCFSIM_DCCR1 0x63 /* DRAM 1 Control reg (r/w) */ - -#define MCFSIM_PACNT 0x80 /* Port A Control (r/w) */ -#define MCFSIM_PADDR 0x84 /* Port A Direction (r/w) */ -#define MCFSIM_PADAT 0x86 /* Port A Data (r/w) */ -#define MCFSIM_PBCNT 0x88 /* Port B Control (r/w) */ -#define MCFSIM_PBDDR 0x8c /* Port B Direction (r/w) */ -#define MCFSIM_PBDAT 0x8e /* Port B Data (r/w) */ -#define MCFSIM_PCDDR 0x94 /* Port C Direction (r/w) */ -#define MCFSIM_PCDAT 0x96 /* Port C Data (r/w) */ -#define MCFSIM_PDCNT 0x98 /* Port D Control (r/w) */ - -#endif /* mcf5272_h */ +#endif /* mcf5272_h */ diff --git a/include/asm-m68k/m5282.h b/include/asm-m68k/m5282.h index e5058a46a..7473bb9be 100644 --- a/include/asm-m68k/m5282.h +++ b/include/asm-m68k/m5282.h @@ -23,7 +23,99 @@ /****************************************************************************/ #ifndef m5282_h #define m5282_h -/****************************************************************************/ + +/********************************************************************* +* PLL Clock Module +*********************************************************************/ +/* Bit definitions and macros for PLL_SYNCR */ +#define PLL_SYNCR_LOLRE (0x8000) +#define PLL_SYNCR_MFD2 (0x4000) +#define PLL_SYNCR_MFD1 (0x2000) +#define PLL_SYNCR_MFD0 (0x1000) +#define PLL_SYNCR_LOCRE (0x0800) +#define PLL_SYNCR_RFC2 (0x0400) +#define PLL_SYNCR_RFC1 (0x0200) +#define PLL_SYNCR_RFC0 (0x0100) +#define PLL_SYNCR_LOCEN (0x0080) +#define PLL_SYNCR_DISCLK (0x0040) +#define PLL_SYNCR_FWKUP (0x0020) +#define PLL_SYNCR_STPMD1 (0x0008) +#define PLL_SYNCR_STPMD0 (0x0004) + +/* Bit definitions and macros for PLL_SYNSR */ +#define PLL_SYNSR_MODE (0x0080) +#define PLL_SYNSR_PLLSEL (0x0040) +#define PLL_SYNSR_PLLREF (0x0020) +#define PLL_SYNSR_LOCKS (0x0010) +#define PLL_SYNSR_LOCK (0x0008) +#define PLL_SYNSR_LOCS (0x0004) + +/********************************************************************* +* Interrupt Controller (INTC) +*********************************************************************/ +#define INT0_LO_RSVD0 (0) +#define INT0_LO_EPORT1 (1) +#define INT0_LO_EPORT2 (2) +#define INT0_LO_EPORT3 (3) +#define INT0_LO_EPORT4 (4) +#define INT0_LO_EPORT5 (5) +#define INT0_LO_EPORT6 (6) +#define INT0_LO_EPORT7 (7) +#define INT0_LO_SCM_SWT1 (8) +#define INT0_LO_DMA_00 (9) +#define INT0_LO_DMA_01 (10) +#define INT0_LO_DMA_02 (11) +#define INT0_LO_DMA_03 (12) +#define INT0_LO_UART0 (13) +#define INT0_LO_UART1 (14) +#define INT0_LO_UART2 (15) +#define INT0_LO_RSVD1 (16) +#define INT0_LO_I2C (17) +#define INT0_LO_QSPI (18) +#define INT0_LO_DTMR0 (19) +#define INT0_LO_DTMR1 (20) +#define INT0_LO_DTMR2 (21) +#define INT0_LO_DTMR3 (22) +#define INT0_LO_FEC_TXF (23) +#define INT0_LO_FEC_TXB (24) +#define INT0_LO_FEC_UN (25) +#define INT0_LO_FEC_RL (26) +#define INT0_LO_FEC_RXF (27) +#define INT0_LO_FEC_RXB (28) +#define INT0_LO_FEC_MII (29) +#define INT0_LO_FEC_LC (30) +#define INT0_LO_FEC_HBERR (31) +#define INT0_HI_FEC_GRA (32) +#define INT0_HI_FEC_EBERR (33) +#define INT0_HI_FEC_BABT (34) +#define INT0_HI_FEC_BABR (35) +#define INT0_HI_PMM_LVDF (36) +#define INT0_HI_QADC_CF1 (37) +#define INT0_HI_QADC_CF2 (38) +#define INT0_HI_QADC_PF1 (39) +#define INT0_HI_QADC_PF2 (40) +#define INT0_HI_GPTA_TOF (41) +#define INT0_HI_GPTA_PAIF (42) +#define INT0_HI_GPTA_PAOVF (43) +#define INT0_HI_GPTA_C0F (44) +#define INT0_HI_GPTA_C1F (45) +#define INT0_HI_GPTA_C2F (46) +#define INT0_HI_GPTA_C3F (47) +#define INT0_HI_GPTB_TOF (48) +#define INT0_HI_GPTB_PAIF (49) +#define INT0_HI_GPTB_PAOVF (50) +#define INT0_HI_GPTB_C0F (51) +#define INT0_HI_GPTB_C1F (52) +#define INT0_HI_GPTB_C2F (53) +#define INT0_HI_GPTB_C3F (54) +#define INT0_HI_PIT0 (55) +#define INT0_HI_PIT1 (56) +#define INT0_HI_PIT2 (57) +#define INT0_HI_PIT3 (58) +#define INT0_HI_CFM_CBEIF (59) +#define INT0_HI_CFM_CCIF (60) +#define INT0_HI_CFM_PVIF (61) +#define INT0_HI_CFM_AEIF (62) /* * Size of internal RAM @@ -96,49 +188,49 @@ #define MCFGPIO_SETD (*(vu_char *) (CFG_MBAR+0x10002B)) #define MCFGPIO_SETE (*(vu_char *) (CFG_MBAR+0x10002C)) #define MCFGPIO_SETF (*(vu_char *) (CFG_MBAR+0x10002D)) -#define MCFGPIO_SETG (*(vu_char *) (CFG_MBAR+0x10002E)) -#define MCFGPIO_SETH (*(vu_char *) (CFG_MBAR+0x10002F)) -#define MCFGPIO_SETJ (*(vu_char *) (CFG_MBAR+0x100030)) -#define MCFGPIO_SETDD (*(vu_char *) (CFG_MBAR+0x100031)) -#define MCFGPIO_SETEH (*(vu_char *) (CFG_MBAR+0x100032)) -#define MCFGPIO_SETEL (*(vu_char *) (CFG_MBAR+0x100033)) -#define MCFGPIO_SETAS (*(vu_char *) (CFG_MBAR+0x100034)) -#define MCFGPIO_SETQS (*(vu_char *) (CFG_MBAR+0x100035)) -#define MCFGPIO_SETSD (*(vu_char *) (CFG_MBAR+0x100036)) -#define MCFGPIO_SETTC (*(vu_char *) (CFG_MBAR+0x100037)) -#define MCFGPIO_SETTD (*(vu_char *) (CFG_MBAR+0x100038)) -#define MCFGPIO_SETUA (*(vu_char *) (CFG_MBAR+0x100039)) +#define MCFGPIO_SETG (*(vu_char *) (CFG_MBAR+0x10002E)) +#define MCFGPIO_SETH (*(vu_char *) (CFG_MBAR+0x10002F)) +#define MCFGPIO_SETJ (*(vu_char *) (CFG_MBAR+0x100030)) +#define MCFGPIO_SETDD (*(vu_char *) (CFG_MBAR+0x100031)) +#define MCFGPIO_SETEH (*(vu_char *) (CFG_MBAR+0x100032)) +#define MCFGPIO_SETEL (*(vu_char *) (CFG_MBAR+0x100033)) +#define MCFGPIO_SETAS (*(vu_char *) (CFG_MBAR+0x100034)) +#define MCFGPIO_SETQS (*(vu_char *) (CFG_MBAR+0x100035)) +#define MCFGPIO_SETSD (*(vu_char *) (CFG_MBAR+0x100036)) +#define MCFGPIO_SETTC (*(vu_char *) (CFG_MBAR+0x100037)) +#define MCFGPIO_SETTD (*(vu_char *) (CFG_MBAR+0x100038)) +#define MCFGPIO_SETUA (*(vu_char *) (CFG_MBAR+0x100039)) -#define MCFGPIO_CLRA (*(vu_char *) (CFG_MBAR+0x10003C)) -#define MCFGPIO_CLRB (*(vu_char *) (CFG_MBAR+0x10003D)) -#define MCFGPIO_CLRC (*(vu_char *) (CFG_MBAR+0x10003E)) -#define MCFGPIO_CLRD (*(vu_char *) (CFG_MBAR+0x10003F)) -#define MCFGPIO_CLRE (*(vu_char *) (CFG_MBAR+0x100040)) -#define MCFGPIO_CLRF (*(vu_char *) (CFG_MBAR+0x100041)) -#define MCFGPIO_CLRG (*(vu_char *) (CFG_MBAR+0x100042)) -#define MCFGPIO_CLRH (*(vu_char *) (CFG_MBAR+0x100043)) -#define MCFGPIO_CLRJ (*(vu_char *) (CFG_MBAR+0x100044)) -#define MCFGPIO_CLRDD (*(vu_char *) (CFG_MBAR+0x100045)) -#define MCFGPIO_CLREH (*(vu_char *) (CFG_MBAR+0x100046)) -#define MCFGPIO_CLREL (*(vu_char *) (CFG_MBAR+0x100047)) -#define MCFGPIO_CLRAS (*(vu_char *) (CFG_MBAR+0x100048)) -#define MCFGPIO_CLRQS (*(vu_char *) (CFG_MBAR+0x100049)) -#define MCFGPIO_CLRSD (*(vu_char *) (CFG_MBAR+0x10004A)) -#define MCFGPIO_CLRTC (*(vu_char *) (CFG_MBAR+0x10004B)) -#define MCFGPIO_CLRTD (*(vu_char *) (CFG_MBAR+0x10004C)) -#define MCFGPIO_CLRUA (*(vu_char *) (CFG_MBAR+0x10004D)) +#define MCFGPIO_CLRA (*(vu_char *) (CFG_MBAR+0x10003C)) +#define MCFGPIO_CLRB (*(vu_char *) (CFG_MBAR+0x10003D)) +#define MCFGPIO_CLRC (*(vu_char *) (CFG_MBAR+0x10003E)) +#define MCFGPIO_CLRD (*(vu_char *) (CFG_MBAR+0x10003F)) +#define MCFGPIO_CLRE (*(vu_char *) (CFG_MBAR+0x100040)) +#define MCFGPIO_CLRF (*(vu_char *) (CFG_MBAR+0x100041)) +#define MCFGPIO_CLRG (*(vu_char *) (CFG_MBAR+0x100042)) +#define MCFGPIO_CLRH (*(vu_char *) (CFG_MBAR+0x100043)) +#define MCFGPIO_CLRJ (*(vu_char *) (CFG_MBAR+0x100044)) +#define MCFGPIO_CLRDD (*(vu_char *) (CFG_MBAR+0x100045)) +#define MCFGPIO_CLREH (*(vu_char *) (CFG_MBAR+0x100046)) +#define MCFGPIO_CLREL (*(vu_char *) (CFG_MBAR+0x100047)) +#define MCFGPIO_CLRAS (*(vu_char *) (CFG_MBAR+0x100048)) +#define MCFGPIO_CLRQS (*(vu_char *) (CFG_MBAR+0x100049)) +#define MCFGPIO_CLRSD (*(vu_char *) (CFG_MBAR+0x10004A)) +#define MCFGPIO_CLRTC (*(vu_char *) (CFG_MBAR+0x10004B)) +#define MCFGPIO_CLRTD (*(vu_char *) (CFG_MBAR+0x10004C)) +#define MCFGPIO_CLRUA (*(vu_char *) (CFG_MBAR+0x10004D)) -#define MCFGPIO_PBCDPAR (*(vu_char *) (CFG_MBAR+0x100050)) -#define MCFGPIO_PFPAR (*(vu_char *) (CFG_MBAR+0x100051)) -#define MCFGPIO_PEPAR (*(vu_short *)(CFG_MBAR+0x100052)) -#define MCFGPIO_PJPAR (*(vu_char *) (CFG_MBAR+0x100054)) -#define MCFGPIO_PSDPAR (*(vu_char *) (CFG_MBAR+0x100055)) -#define MCFGPIO_PASPAR (*(vu_short *)(CFG_MBAR+0x100056)) -#define MCFGPIO_PEHLPAR (*(vu_char *) (CFG_MBAR+0x100058)) -#define MCFGPIO_PQSPAR (*(vu_char *) (CFG_MBAR+0x100059)) -#define MCFGPIO_PTCPAR (*(vu_char *) (CFG_MBAR+0x10005A)) -#define MCFGPIO_PTDPAR (*(vu_char *) (CFG_MBAR+0x10005B)) -#define MCFGPIO_PUAPAR (*(vu_char *) (CFG_MBAR+0x10005C)) +#define MCFGPIO_PBCDPAR (*(vu_char *) (CFG_MBAR+0x100050)) +#define MCFGPIO_PFPAR (*(vu_char *) (CFG_MBAR+0x100051)) +#define MCFGPIO_PEPAR (*(vu_short *)(CFG_MBAR+0x100052)) +#define MCFGPIO_PJPAR (*(vu_char *) (CFG_MBAR+0x100054)) +#define MCFGPIO_PSDPAR (*(vu_char *) (CFG_MBAR+0x100055)) +#define MCFGPIO_PASPAR (*(vu_short *)(CFG_MBAR+0x100056)) +#define MCFGPIO_PEHLPAR (*(vu_char *) (CFG_MBAR+0x100058)) +#define MCFGPIO_PQSPAR (*(vu_char *) (CFG_MBAR+0x100059)) +#define MCFGPIO_PTCPAR (*(vu_char *) (CFG_MBAR+0x10005A)) +#define MCFGPIO_PTDPAR (*(vu_char *) (CFG_MBAR+0x10005B)) +#define MCFGPIO_PUAPAR (*(vu_char *) (CFG_MBAR+0x10005C)) /* Bit level definitions and macros */ #define MCFGPIO_PORT7 (0x80) @@ -171,7 +263,6 @@ #define MCFGPIO_Px0 (0x01) #define MCFGPIO_Px(x) (0x01< - -/* - * Get address specific defines for this ColdFire member. - */ -#if defined(CONFIG_M5204) || defined(CONFIG_M5206) || defined(CONFIG_M5206e) -#define MCFTIMER_BASE1 0x100 /* Base address of TIMER1 */ -#define MCFTIMER_BASE2 0x120 /* Base address of TIMER2 */ -#elif defined(CONFIG_M5272) -#define MCFTIMER_BASE1 0x200 /* Base address of TIMER1 */ -#define MCFTIMER_BASE2 0x220 /* Base address of TIMER2 */ -#define MCFTIMER_BASE3 0x240 /* Base address of TIMER4 */ -#define MCFTIMER_BASE4 0x260 /* Base address of TIMER3 */ -#elif defined(CONFIG_M5249) || defined(CONFIG_M5307) || defined(CONFIG_M5407) -#define MCFTIMER_BASE1 0x140 /* Base address of TIMER1 */ -#define MCFTIMER_BASE2 0x180 /* Base address of TIMER2 */ -#elif defined(CONFIG_M5282) | defined(CONFIG_M5271) -#define MCFTIMER_BASE1 0x150000 /* Base address of TIMER1 */ -#define MCFTIMER_BASE2 0x160000 /* Base address of TIMER2 */ -#define MCFTIMER_BASE3 0x170000 /* Base address of TIMER4 */ -#define MCFTIMER_BASE4 0x180000 /* Base address of TIMER3 */ -#endif - -/* - * Define the TIMER register set addresses. - */ -#define MCFTIMER_TMR 0x00 /* Timer Mode reg (r/w) */ -#define MCFTIMER_TRR 0x02 /* Timer Reference (r/w) */ -#define MCFTIMER_TCR 0x04 /* Timer Capture reg (r/w) */ -#define MCFTIMER_TCN 0x06 /* Timer Counter reg (r/w) */ -#define MCFTIMER_TER 0x11 /* Timer Event reg (r/w) */ - -/* - * Define the TIMER register set addresses for 5282. - */ -#define MCFTIMER_PCSR 0 -#define MCFTIMER_PMR 1 -#define MCFTIMER_PCNTR 2 - -/* - * Bit definitions for the Timer Mode Register (TMR). - * Register bit flags are common accross ColdFires. - */ -#define MCFTIMER_TMR_PREMASK 0xff00 /* Prescalar mask */ -#define MCFTIMER_TMR_DISCE 0x0000 /* Disable capture */ -#define MCFTIMER_TMR_ANYCE 0x00c0 /* Capture any edge */ -#define MCFTIMER_TMR_FALLCE 0x0080 /* Capture fallingedge */ -#define MCFTIMER_TMR_RISECE 0x0040 /* Capture rising edge */ -#define MCFTIMER_TMR_ENOM 0x0020 /* Enable output toggle */ -#define MCFTIMER_TMR_DISOM 0x0000 /* Do single output pulse */ -#define MCFTIMER_TMR_ENORI 0x0010 /* Enable ref interrupt */ -#define MCFTIMER_TMR_DISORI 0x0000 /* Disable ref interrupt */ -#define MCFTIMER_TMR_RESTART 0x0008 /* Restart counter */ -#define MCFTIMER_TMR_FREERUN 0x0000 /* Free running counter */ -#define MCFTIMER_TMR_CLKTIN 0x0006 /* Input clock is TIN */ -#define MCFTIMER_TMR_CLK16 0x0004 /* Input clock is /16 */ -#define MCFTIMER_TMR_CLK1 0x0002 /* Input clock is /1 */ -#define MCFTIMER_TMR_CLKSTOP 0x0000 /* Stop counter */ -#define MCFTIMER_TMR_ENABLE 0x0001 /* Enable timer */ -#define MCFTIMER_TMR_DISABLE 0x0000 /* Disable timer */ - -/* - * Bit definitions for the Timer Event Registers (TER). - */ -#define MCFTIMER_TER_CAP 0x01 /* Capture event */ -#define MCFTIMER_TER_REF 0x02 /* Refernece event */ - -/* - * Bit definitions for the 5282 PIT Control and Status Register (PCSR). - */ -#define MCFTIMER_PCSR_EN 0x0001 -#define MCFTIMER_PCSR_RLD 0x0002 -#define MCFTIMER_PCSR_PIF 0x0004 -#define MCFTIMER_PCSR_PIE 0x0008 -#define MCFTIMER_PCSR_OVW 0x0010 -#define MCFTIMER_PCSR_HALTED 0x0020 -#define MCFTIMER_PCSR_DOZE 0x0040 - -/****************************************************************************/ -#endif /* mcftimer_h */ diff --git a/include/asm-m68k/mcfuart.h b/include/asm-m68k/mcfuart.h deleted file mode 100644 index 1ccc43f0f..000000000 --- a/include/asm-m68k/mcfuart.h +++ /dev/null @@ -1,217 +0,0 @@ -/* - * mcfuart.h -- ColdFire internal UART support defines. - * - * File copied from mcfuart.h of uCLinux distribution: - * (C) Copyright 1999, Greg Ungerer (gerg@snapgear.com) - * (C) Copyright 2000, Lineo Inc. (www.lineo.com) - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/****************************************************************************/ -#ifndef mcfuart_h -#define mcfuart_h -/****************************************************************************/ - -#include - -/* - * Define the base address of the UARTS within the MBAR address - * space. - */ -#if defined(CONFIG_M5272) -#define MCFUART_BASE1 0x100 /* Base address of UART1 */ -#define MCFUART_BASE2 0x140 /* Base address of UART2 */ -#elif defined(CONFIG_M5204) || defined(CONFIG_M5206) || defined(CONFIG_M5206e) -#if defined(CONFIG_NETtel) -#define MCFUART_BASE1 0x180 /* Base address of UART1 */ -#define MCFUART_BASE2 0x140 /* Base address of UART2 */ -#else -#define MCFUART_BASE1 0x140 /* Base address of UART1 */ -#define MCFUART_BASE2 0x180 /* Base address of UART2 */ -#endif -#elif defined(CONFIG_M5282) || defined(CONFIG_M5271) -#define MCFUART_BASE1 0x200 /* Base address of UART1 */ -#define MCFUART_BASE2 0x240 /* Base address of UART2 */ -#define MCFUART_BASE3 0x280 /* Base address of UART3 */ -#elif defined(CONFIG_M5249) || defined(CONFIG_M5307) || defined(CONFIG_M5407) -#if defined(CONFIG_NETtel) || defined(CONFIG_DISKtel) || defined(CONFIG_SECUREEDGEMP3) -#define MCFUART_BASE1 0x200 /* Base address of UART1 */ -#define MCFUART_BASE2 0x1c0 /* Base address of UART2 */ -#else -#define MCFUART_BASE1 0x1c0 /* Base address of UART1 */ -#define MCFUART_BASE2 0x200 /* Base address of UART2 */ -#endif -#endif - -/* - * Define the ColdFire UART register set addresses. - */ -#define MCFUART_UMR 0x00 /* Mode register (r/w) */ -#define MCFUART_USR 0x04 /* Status register (r) */ -#define MCFUART_UCSR 0x04 /* Clock Select (w) */ -#define MCFUART_UCR 0x08 /* Command register (w) */ -#define MCFUART_URB 0x0c /* Receiver Buffer (r) */ -#define MCFUART_UTB 0x0c /* Transmit Buffer (w) */ -#define MCFUART_UIPCR 0x10 /* Input Port Change (r) */ -#define MCFUART_UACR 0x10 /* Auxiliary Control (w) */ -#define MCFUART_UISR 0x14 /* Interrup Status (r) */ -#define MCFUART_UIMR 0x14 /* Interrupt Mask (w) */ -#define MCFUART_UBG1 0x18 /* Baud Rate MSB (r/w) */ -#define MCFUART_UBG2 0x1c /* Baud Rate LSB (r/w) */ -#ifdef CONFIG_M5272 -#define MCFUART_UTF 0x28 /* Transmitter FIFO (r/w) */ -#define MCFUART_URF 0x2c /* Receiver FIFO (r/w) */ -#define MCFUART_UFPD 0x30 /* Frac Prec. Divider (r/w) */ -#else -#define MCFUART_UIVR 0x30 /* Interrupt Vector (r/w) */ -#endif -#define MCFUART_UIPR 0x34 /* Input Port (r) */ -#define MCFUART_UOP1 0x38 /* Output Port Bit Set (w) */ -#define MCFUART_UOP0 0x3c /* Output Port Bit Reset (w) */ - -#ifdef CONFIG_M5249 -/* Note: This isn't in the 5249 docs */ -#define MCFUART_UFPD 0x30 /* Frac Prec. Divider (r/w) */ -#endif - -/* - * Define bit flags in Mode Register 1 (MR1). - */ -#define MCFUART_MR1_RXRTS 0x80 /* Auto RTS flow control */ -#define MCFUART_MR1_RXIRQFULL 0x40 /* RX IRQ type FULL */ -#define MCFUART_MR1_RXIRQRDY 0x00 /* RX IRQ type RDY */ -#define MCFUART_MR1_RXERRBLOCK 0x20 /* RX block error mode */ -#define MCFUART_MR1_RXERRCHAR 0x00 /* RX char error mode */ - -#define MCFUART_MR1_PARITYNONE 0x10 /* No parity */ -#define MCFUART_MR1_PARITYEVEN 0x00 /* Even parity */ -#define MCFUART_MR1_PARITYODD 0x04 /* Odd parity */ -#define MCFUART_MR1_PARITYSPACE 0x08 /* Space parity */ -#define MCFUART_MR1_PARITYMARK 0x0c /* Mark parity */ - -#define MCFUART_MR1_CS5 0x00 /* 5 bits per char */ -#define MCFUART_MR1_CS6 0x01 /* 6 bits per char */ -#define MCFUART_MR1_CS7 0x02 /* 7 bits per char */ -#define MCFUART_MR1_CS8 0x03 /* 8 bits per char */ - -/* - * Define bit flags in Mode Register 2 (MR2). - */ -#define MCFUART_MR2_LOOPBACK 0x80 /* Loopback mode */ -#define MCFUART_MR2_REMOTELOOP 0xc0 /* Remote loopback mode */ -#define MCFUART_MR2_AUTOECHO 0x40 /* Automatic echo */ -#define MCFUART_MR2_TXRTS 0x20 /* Assert RTS on TX */ -#define MCFUART_MR2_TXCTS 0x10 /* Auto CTS flow control */ - -#define MCFUART_MR2_STOP1 0x07 /* 1 stop bit */ -#define MCFUART_MR2_STOP15 0x08 /* 1.5 stop bits */ -#define MCFUART_MR2_STOP2 0x0f /* 2 stop bits */ - -/* - * Define bit flags in Status Register (USR). - */ -#define MCFUART_USR_RXBREAK 0x80 /* Received BREAK */ -#define MCFUART_USR_RXFRAMING 0x40 /* Received framing error */ -#define MCFUART_USR_RXPARITY 0x20 /* Received parity error */ -#define MCFUART_USR_RXOVERRUN 0x10 /* Received overrun error */ -#define MCFUART_USR_TXEMPTY 0x08 /* Transmitter empty */ -#define MCFUART_USR_TXREADY 0x04 /* Transmitter ready */ -#define MCFUART_USR_RXFULL 0x02 /* Receiver full */ -#define MCFUART_USR_RXREADY 0x01 /* Receiver ready */ - -#define MCFUART_USR_RXERR (MCFUART_USR_RXBREAK | MCFUART_USR_RXFRAMING | \ - MCFUART_USR_RXPARITY | MCFUART_USR_RXOVERRUN) - -/* - * Define bit flags in Clock Select Register (UCSR). - */ -#define MCFUART_UCSR_RXCLKTIMER 0xd0 /* RX clock is timer */ -#define MCFUART_UCSR_RXCLKEXT16 0xe0 /* RX clock is external x16 */ -#define MCFUART_UCSR_RXCLKEXT1 0xf0 /* RX clock is external x1 */ - -#define MCFUART_UCSR_TXCLKTIMER 0x0d /* TX clock is timer */ -#define MCFUART_UCSR_TXCLKEXT16 0x0e /* TX clock is external x16 */ -#define MCFUART_UCSR_TXCLKEXT1 0x0f /* TX clock is external x1 */ - -/* - * Define bit flags in Command Register (UCR). - */ -#define MCFUART_UCR_CMDNULL 0x00 /* No command */ -#define MCFUART_UCR_CMDRESETMRPTR 0x10 /* Reset MR pointer */ -#define MCFUART_UCR_CMDRESETRX 0x20 /* Reset receiver */ -#define MCFUART_UCR_CMDRESETTX 0x30 /* Reset transmitter */ -#define MCFUART_UCR_CMDRESETERR 0x40 /* Reset error status */ -#define MCFUART_UCR_CMDRESETBREAK 0x50 /* Reset BREAK change */ -#define MCFUART_UCR_CMDBREAKSTART 0x60 /* Start BREAK */ -#define MCFUART_UCR_CMDBREAKSTOP 0x70 /* Stop BREAK */ - -#define MCFUART_UCR_TXNULL 0x00 /* No TX command */ -#define MCFUART_UCR_TXENABLE 0x04 /* Enable TX */ -#define MCFUART_UCR_TXDISABLE 0x08 /* Disable TX */ -#define MCFUART_UCR_RXNULL 0x00 /* No RX command */ -#define MCFUART_UCR_RXENABLE 0x01 /* Enable RX */ -#define MCFUART_UCR_RXDISABLE 0x02 /* Disable RX */ - -/* - * Define bit flags in Input Port Change Register (UIPCR). - */ -#define MCFUART_UIPCR_CTSCOS 0x10 /* CTS change of state */ -#define MCFUART_UIPCR_CTS 0x01 /* CTS value */ - -/* - * Define bit flags in Input Port Register (UIP). - */ -#define MCFUART_UIPR_CTS 0x01 /* CTS value */ - -/* - * Define bit flags in Output Port Registers (UOP). - * Clear bit by writing to UOP0, set by writing to UOP1. - */ -#define MCFUART_UOP_RTS 0x01 /* RTS set or clear */ - -/* - * Define bit flags in the Auxiliary Control Register (UACR). - */ -#define MCFUART_UACR_IEC 0x01 /* Input enable control */ - -/* - * Define bit flags in Interrupt Status Register (UISR). - * These same bits are used for the Interrupt Mask Register (UIMR). - */ -#define MCFUART_UIR_COS 0x80 /* Change of state (CTS) */ -#define MCFUART_UIR_DELTABREAK 0x04 /* Break start or stop */ -#define MCFUART_UIR_RXREADY 0x02 /* Receiver ready */ -#define MCFUART_UIR_TXREADY 0x01 /* Transmitter ready */ - -#ifdef CONFIG_M5272 -/* - * Define bit flags in the Transmitter FIFO Register (UTF). - */ -#define MCFUART_UTF_TXB 0x1f /* transmitter data level */ -#define MCFUART_UTF_FULL 0x20 /* transmitter fifo full */ -#define MCFUART_UTF_TXS 0xc0 /* transmitter status */ - -/* - * Define bit flags in the Receiver FIFO Register (URF). - */ -#define MCFUART_URF_RXB 0x1f /* receiver data level */ -#define MCFUART_URF_FULL 0x20 /* receiver fifo full */ -#define MCFUART_URF_RXS 0xc0 /* receiver status */ -#endif diff --git a/include/asm-m68k/timer.h b/include/asm-m68k/timer.h index 3ec710d1f..030720c89 100644 --- a/include/asm-m68k/timer.h +++ b/include/asm-m68k/timer.h @@ -46,7 +46,7 @@ typedef struct dtimer_ctrl { u8 ter; /* 0x11 Event register */ u16 res7; /* 0x12 */ #else - u16 tmr; /* 0x00 Mode register */ + u16 tmr; /* 0x00 Mode register */ u8 txmr; /* 0x02 Extended Mode register */ u8 ter; /* 0x03 Event register */ u32 trr; /* 0x04 Reference register */ From 6706424d0bb851fb52af00cd1c3301e91ee7f2b0 Mon Sep 17 00:00:00 2001 From: TsiChungLiew Date: Wed, 15 Aug 2007 19:41:06 -0500 Subject: [PATCH 158/259] ColdFire: cobra5272 platform for MCF52x2 update Signed-off-by: TsiChungLiew --- board/cobra5272/Makefile | 2 +- board/cobra5272/cobra5272.c | 5 +- board/cobra5272/mii.c | 303 ++++++++++++++++++++++++++++++++++++ include/configs/cobra5272.h | 26 +++- 4 files changed, 331 insertions(+), 5 deletions(-) create mode 100644 board/cobra5272/mii.c diff --git a/board/cobra5272/Makefile b/board/cobra5272/Makefile index cf07cf40f..be704b76f 100644 --- a/board/cobra5272/Makefile +++ b/board/cobra5272/Makefile @@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a -COBJS = $(BOARD).o flash.o +COBJS = $(BOARD).o flash.o mii.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/board/cobra5272/cobra5272.c b/board/cobra5272/cobra5272.c index 26adb4abb..86c7ee1ee 100644 --- a/board/cobra5272/cobra5272.c +++ b/board/cobra5272/cobra5272.c @@ -22,8 +22,7 @@ */ #include -#include -#include +#include int checkboard (void) @@ -35,7 +34,7 @@ int checkboard (void) long int initdram (int board_type) { - volatile sdramctrl_t *sdp = (sdramctrl_t *) (CFG_MBAR + MCFSIM_SDCR); + volatile sdramctrl_t *sdp = (sdramctrl_t *) (MMAP_SDRAM); sdp->sdram_sdtr = 0xf539; sdp->sdram_sdcr = 0x4211; diff --git a/board/cobra5272/mii.c b/board/cobra5272/mii.c new file mode 100644 index 000000000..fadcbb3ef --- /dev/null +++ b/board/cobra5272/mii.c @@ -0,0 +1,303 @@ +/* + * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI) +#undef MII_DEBUG +#undef ET_DEBUG + +int fecpin_setclear(struct eth_device *dev, int setclear) +{ + volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; + + if (setclear) { + gpio->gpio_pbcnt |= GPIO_PBCNT_E_MDC | GPIO_PBCNT_E_RXER | GPIO_PBCNT_E_RXD1 | GPIO_PBCNT_E_RXD2 | GPIO_PBCNT_E_RXD3 | GPIO_PBCNT_E_TXD1 | GPIO_PBCNT_E_TXD2 | GPIO_PBCNT_E_TXD3; + } else { + } + return 0; +} + +#if defined(CFG_DISCOVER_PHY) || defined(CONFIG_CMD_MII) +#include + +/* Make MII read/write commands for the FEC. */ +#define mk_mii_read(ADDR, REG) (0x60020000 | ((ADDR << 23) | (REG & 0x1f) << 18)) + +#define mk_mii_write(ADDR, REG, VAL) (0x50020000 | ((ADDR << 23) | (REG & 0x1f) << 18) | (VAL & 0xffff)) + +/* PHY identification */ +#define PHY_ID_LXT970 0x78100000 /* LXT970 */ +#define PHY_ID_LXT971 0x001378e0 /* LXT971 and 972 */ +#define PHY_ID_82555 0x02a80150 /* Intel 82555 */ +#define PHY_ID_QS6612 0x01814400 /* QS6612 */ +#define PHY_ID_AMD79C784 0x00225610 /* AMD 79C784 */ +#define PHY_ID_AMD79C874VC 0x0022561B /* AMD 79C874 */ +#define PHY_ID_LSI80225 0x0016f870 /* LSI 80225 */ +#define PHY_ID_LSI80225B 0x0016f880 /* LSI 80225/B */ +#define PHY_ID_DP83848VV 0x20005C90 /* National 83848 */ +#define PHY_ID_DP83849 0x20005CA2 /* National 82849 */ + +#define STR_ID_LXT970 "LXT970" +#define STR_ID_LXT971 "LXT971" +#define STR_ID_82555 "Intel82555" +#define STR_ID_QS6612 "QS6612" +#define STR_ID_AMD79C784 "AMD79C784" +#define STR_ID_AMD79C874VC "AMD79C874VC" +#define STR_ID_LSI80225 "LSI80225" +#define STR_ID_LSI80225B "LSI80225/B" +#define STR_ID_DP83848VV "N83848" +#define STR_ID_DP83849 "N83849" + +/**************************************************************************** + * mii_init -- Initialize the MII for MII command without ethernet + * This function is a subset of eth_init + **************************************************************************** + */ +void mii_reset(struct fec_info_s *info) +{ + volatile fec_t *fecp = (fec_t *) (info->miibase); + int i; + + fecp->ecr = FEC_ECR_RESET; + for (i = 0; (fecp->ecr & FEC_ECR_RESET) && (i < FEC_RESET_DELAY); ++i) { + udelay(1); + } + if (i == FEC_RESET_DELAY) { + printf("FEC_RESET_DELAY timeout\n"); + } +} + +/* send command to phy using mii, wait for result */ +uint mii_send(uint mii_cmd) +{ + struct fec_info_s *info; + struct eth_device *dev; + volatile fec_t *ep; + uint mii_reply; + int j = 0; + + /* retrieve from register structure */ + dev = eth_get_dev(); + info = dev->priv; + + ep = (fec_t *) info->miibase; + + ep->mmfr = mii_cmd; /* command to phy */ + + /* wait for mii complete */ + while (!(ep->eir & FEC_EIR_MII) && (j < MCFFEC_TOUT_LOOP)) { + udelay(1); + j++; + } + if (j >= MCFFEC_TOUT_LOOP) { + printf("MII not complete\n"); + return -1; + } + + mii_reply = ep->mmfr; /* result from phy */ + ep->eir = FEC_EIR_MII; /* clear MII complete */ +#ifdef ET_DEBUG + printf("%s[%d] %s: sent=0x%8.8x, reply=0x%8.8x\n", + __FILE__, __LINE__, __FUNCTION__, mii_cmd, mii_reply); +#endif + + return (mii_reply & 0xffff); /* data read from phy */ +} +#endif /* CFG_DISCOVER_PHY || (CONFIG_COMMANDS & CONFIG_CMD_MII) */ + +#if defined(CFG_DISCOVER_PHY) +int mii_discover_phy(struct eth_device *dev) +{ +#define MAX_PHY_PASSES 11 + struct fec_info_s *info = dev->priv; + int phyaddr, pass; + uint phyno, phytype; + + if (info->phyname_init) + return info->phy_addr; + + phyaddr = -1; /* didn't find a PHY yet */ + for (pass = 1; pass <= MAX_PHY_PASSES && phyaddr < 0; ++pass) { + if (pass > 1) { + /* PHY may need more time to recover from reset. + * The LXT970 needs 50ms typical, no maximum is + * specified, so wait 10ms before try again. + * With 11 passes this gives it 100ms to wake up. + */ + udelay(10000); /* wait 10ms */ + } + + for (phyno = 0; phyno < 32 && phyaddr < 0; ++phyno) { + + phytype = mii_send(mk_mii_read(phyno, PHY_PHYIDR1)); +#ifdef ET_DEBUG + printf("PHY type 0x%x pass %d type\n", phytype, pass); +#endif + if (phytype != 0xffff) { + phyaddr = phyno; + phytype <<= 16; + phytype |= + mii_send(mk_mii_read(phyno, PHY_PHYIDR2)); + + switch (phytype & 0xffffffff) { + case PHY_ID_AMD79C874VC: + strcpy(info->phy_name, + STR_ID_AMD79C874VC); + info->phyname_init = 1; + break; + default: + strcpy(info->phy_name, "unknown"); + info->phyname_init = 1; + break; + } + +#ifdef ET_DEBUG + printf("PHY @ 0x%x pass %d type ", phyno, pass); + switch (phytype & 0xffffffff) { + case PHY_ID_AMD79C874VC: + printf(STR_ID_AMD79C874VC); + break; + default: + printf("0x%08x\n", phytype); + break; + } +#endif + } + } + } + if (phyaddr < 0) + printf("No PHY device found.\n"); + + return phyaddr; +} +#endif /* CFG_DISCOVER_PHY */ + +int mii_init(void) __attribute__((weak,alias("__mii_init"))); + +void __mii_init(void) +{ + volatile fec_t *fecp; + struct fec_info_s *info; + struct eth_device *dev; + int miispd = 0, i = 0; + u16 autoneg = 0; + + /* retrieve from register structure */ + dev = eth_get_dev(); + info = dev->priv; + + fecp = (fec_t *) info->miibase; + + fecpin_setclear(dev, 1); + + mii_reset(info); + + /* We use strictly polling mode only */ + fecp->eimr = 0; + + /* Clear any pending interrupt */ + fecp->eir = 0xffffffff; + + /* Set MII speed */ + miispd = (gd->bus_clk / 1000000) / 5; + fecp->mscr = miispd << 1; + + info->phy_addr = mii_discover_phy(dev); + +#define AUTONEGLINK (PHY_BMSR_AUTN_COMP | PHY_BMSR_LS) + while (i < MCFFEC_TOUT_LOOP) { + autoneg = 0; + miiphy_read(dev->name, info->phy_addr, PHY_BMSR, &autoneg); + i++; + + if ((autoneg & AUTONEGLINK) == AUTONEGLINK) + break; + + udelay(500); + } + if (i >= MCFFEC_TOUT_LOOP) { + printf("Auto Negotiation not complete\n"); + } + + /* adapt to the half/full speed settings */ + info->dup_spd = miiphy_duplex(dev->name, info->phy_addr) << 16; + info->dup_spd |= miiphy_speed(dev->name, info->phy_addr); +} + +/***************************************************************************** + * Read and write a MII PHY register, routines used by MII Utilities + * + * FIXME: These routines are expected to return 0 on success, but mii_send + * does _not_ return an error code. Maybe 0xFFFF means error, i.e. + * no PHY connected... + * For now always return 0. + * FIXME: These routines only work after calling eth_init() at least once! + * Otherwise they hang in mii_send() !!! Sorry! + *****************************************************************************/ + +int mcffec_miiphy_read(char *devname, unsigned char addr, unsigned char reg, + unsigned short *value) +{ + short rdreg; /* register working value */ + +#ifdef MII_DEBUG + printf("miiphy_read(0x%x) @ 0x%x = ", reg, addr); +#endif + rdreg = mii_send(mk_mii_read(addr, reg)); + + *value = rdreg; + +#ifdef MII_DEBUG + printf("0x%04x\n", *value); +#endif + + return 0; +} + +int mcffec_miiphy_write(char *devname, unsigned char addr, unsigned char reg, + unsigned short value) +{ + short rdreg; /* register working value */ + +#ifdef MII_DEBUG + printf("miiphy_write(0x%x) @ 0x%x = ", reg, addr); +#endif + + rdreg = mii_send(mk_mii_write(addr, reg, value)); + +#ifdef MII_DEBUG + printf("0x%04x\n", value); +#endif + + return 0; +} + +#endif /* CONFIG_CMD_NET, FEC_ENET & NET_MULTI */ diff --git a/include/configs/cobra5272.h b/include/configs/cobra5272.h index 510524ad3..104d94ec1 100644 --- a/include/configs/cobra5272.h +++ b/include/configs/cobra5272.h @@ -65,8 +65,10 @@ * Enable use of Ethernet * --- */ +#define CONFIG_MCFFEC -#define FEC_ENET +/* Enable Dma Timer */ +#define CONFIG_MCFTMR /* --- * Define baudrate for UART1 (console output, tftp, ...) @@ -76,6 +78,8 @@ * --- */ +#define CONFIG_MCFUART +#define CFG_UART_PORT (0) #define CONFIG_BAUDRATE 19200 #define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 } @@ -151,6 +155,26 @@ #undef CONFIG_CMD_LOADB #undef CONFIG_CMD_MII +#ifdef CONFIG_MCFFEC +# define CONFIG_NET_MULTI 1 +# define CONFIG_MII 1 +# define CFG_DISCOVER_PHY +# define CFG_RX_ETH_BUFFER 8 +# define CFG_FAULT_ECHO_LINK_DOWN + +# define CFG_FEC0_PINMUX 0 +# define CFG_FEC0_MIIBASE CFG_FEC0_IOBASE +# define MCFFEC_TOUT_LOOP 50000 +/* If CFG_DISCOVER_PHY is not defined - hardcoded */ +# ifndef CFG_DISCOVER_PHY +# define FECDUPLEX FULL +# define FECSPEED _100BASET +# else +# ifndef CFG_FAULT_ECHO_LINK_DOWN +# define CFG_FAULT_ECHO_LINK_DOWN +# endif +# endif /* CFG_DISCOVER_PHY */ +#endif /* *----------------------------------------------------------------------------- From 6cfd3c7bc813fb317ab7c0781f0d1874b1c0877c Mon Sep 17 00:00:00 2001 From: TsiChungLiew Date: Wed, 15 Aug 2007 19:43:20 -0500 Subject: [PATCH 159/259] ColdFire: idmr platform MCF52x2 update Signed-off-by: TsiChungLiew --- board/idmr/Makefile | 2 +- board/idmr/idmr.c | 3 +- board/idmr/mii.c | 303 +++++++++++++++++++++++++++++++++++++++++ include/configs/idmr.h | 34 ++++- 4 files changed, 332 insertions(+), 10 deletions(-) create mode 100644 board/idmr/mii.c diff --git a/board/idmr/Makefile b/board/idmr/Makefile index cf07cf40f..be704b76f 100644 --- a/board/idmr/Makefile +++ b/board/idmr/Makefile @@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a -COBJS = $(BOARD).o flash.o +COBJS = $(BOARD).o flash.o mii.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/board/idmr/idmr.c b/board/idmr/idmr.c index 58cdba1e1..081c37533 100644 --- a/board/idmr/idmr.c +++ b/board/idmr/idmr.c @@ -22,8 +22,7 @@ */ #include -#include -#include +#include int checkboard (void) { puts ("Board: iDMR\n"); diff --git a/board/idmr/mii.c b/board/idmr/mii.c new file mode 100644 index 000000000..f6c63c302 --- /dev/null +++ b/board/idmr/mii.c @@ -0,0 +1,303 @@ +/* + * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI) +#undef MII_DEBUG +#undef ET_DEBUG + +int fecpin_setclear(struct eth_device *dev, int setclear) +{ + if (setclear) { + /* Enable Ethernet pins */ + mbar_writeByte(MCF_GPIO_PAR_FECI2C, CFG_FECI2C); + } else { + } + + return 0; +} + +#if defined(CFG_DISCOVER_PHY) || defined(CONFIG_CMD_MII) +#include + +/* Make MII read/write commands for the FEC. */ +#define mk_mii_read(ADDR, REG) (0x60020000 | ((ADDR << 23) | (REG & 0x1f) << 18)) + +#define mk_mii_write(ADDR, REG, VAL) (0x50020000 | ((ADDR << 23) | (REG & 0x1f) << 18) | (VAL & 0xffff)) + +/* PHY identification */ +#define PHY_ID_LXT970 0x78100000 /* LXT970 */ +#define PHY_ID_LXT971 0x001378e0 /* LXT971 and 972 */ +#define PHY_ID_82555 0x02a80150 /* Intel 82555 */ +#define PHY_ID_QS6612 0x01814400 /* QS6612 */ +#define PHY_ID_AMD79C784 0x00225610 /* AMD 79C784 */ +#define PHY_ID_LSI80225 0x0016f870 /* LSI 80225 */ +#define PHY_ID_LSI80225B 0x0016f880 /* LSI 80225/B */ +#define PHY_ID_DP83848VV 0x20005C90 /* National 83848 */ +#define PHY_ID_DP83849 0x20005CA2 /* National 82849 */ +#define PHY_ID_KS8721BL 0x00221619 /* Micrel KS8721BL/SL */ + +#define STR_ID_LXT970 "LXT970" +#define STR_ID_LXT971 "LXT971" +#define STR_ID_82555 "Intel82555" +#define STR_ID_QS6612 "QS6612" +#define STR_ID_AMD79C784 "AMD79C784" +#define STR_ID_LSI80225 "LSI80225" +#define STR_ID_LSI80225B "LSI80225/B" +#define STR_ID_DP83848VV "N83848" +#define STR_ID_DP83849 "N83849" +#define STR_ID_KS8721BL "KS8721BL" + +/**************************************************************************** + * mii_init -- Initialize the MII for MII command without ethernet + * This function is a subset of eth_init + **************************************************************************** + */ +void mii_reset(struct fec_info_s *info) +{ + volatile fec_t *fecp = (fec_t *) (info->miibase); + int i; + + fecp->ecr = FEC_ECR_RESET; + for (i = 0; (fecp->ecr & FEC_ECR_RESET) && (i < FEC_RESET_DELAY); ++i) { + udelay(1); + } + if (i == FEC_RESET_DELAY) { + printf("FEC_RESET_DELAY timeout\n"); + } +} + +/* send command to phy using mii, wait for result */ +uint mii_send(uint mii_cmd) +{ + struct fec_info_s *info; + struct eth_device *dev; + volatile fec_t *ep; + uint mii_reply; + int j = 0; + + /* retrieve from register structure */ + dev = eth_get_dev(); + info = dev->priv; + + ep = (fec_t *) info->miibase; + + ep->mmfr = mii_cmd; /* command to phy */ + + /* wait for mii complete */ + while (!(ep->eir & FEC_EIR_MII) && (j < MCFFEC_TOUT_LOOP)) { + udelay(1); + j++; + } + if (j >= MCFFEC_TOUT_LOOP) { + printf("MII not complete\n"); + return -1; + } + + mii_reply = ep->mmfr; /* result from phy */ + ep->eir = FEC_EIR_MII; /* clear MII complete */ +#ifdef ET_DEBUG + printf("%s[%d] %s: sent=0x%8.8x, reply=0x%8.8x\n", + __FILE__, __LINE__, __FUNCTION__, mii_cmd, mii_reply); +#endif + + return (mii_reply & 0xffff); /* data read from phy */ +} +#endif /* CFG_DISCOVER_PHY || (CONFIG_COMMANDS & CONFIG_CMD_MII) */ + +#if defined(CFG_DISCOVER_PHY) +int mii_discover_phy(struct eth_device *dev) +{ +#define MAX_PHY_PASSES 11 + struct fec_info_s *info = dev->priv; + int phyaddr, pass; + uint phyno, phytype; + + if (info->phyname_init) + return info->phy_addr; + + phyaddr = -1; /* didn't find a PHY yet */ + for (pass = 1; pass <= MAX_PHY_PASSES && phyaddr < 0; ++pass) { + if (pass > 1) { + /* PHY may need more time to recover from reset. + * The LXT970 needs 50ms typical, no maximum is + * specified, so wait 10ms before try again. + * With 11 passes this gives it 100ms to wake up. + */ + udelay(10000); /* wait 10ms */ + } + + for (phyno = 0; phyno < 32 && phyaddr < 0; ++phyno) { + + phytype = mii_send(mk_mii_read(phyno, PHY_PHYIDR1)); +#ifdef ET_DEBUG + printf("PHY type 0x%x pass %d type\n", phytype, pass); +#endif + if (phytype != 0xffff) { + phyaddr = phyno; + phytype <<= 16; + phytype |= + mii_send(mk_mii_read(phyno, PHY_PHYIDR2)); + + switch (phytype & 0xffffffff) { + case PHY_ID_KS8721BL: + strcpy(info->phy_name, + STR_ID_KS8721BL); + info->phyname_init = 1; + break; + default: + strcpy(info->phy_name, "unknown"); + info->phyname_init = 1; + break; + } + +#ifdef ET_DEBUG + printf("PHY @ 0x%x pass %d type ", phyno, pass); + switch (phytype & 0xffffffff) { + case PHY_ID_KS8721BL: + printf(STR_ID_KS8721BL); + break; + default: + printf("0x%08x\n", phytype); + break; + } +#endif + } + } + } + if (phyaddr < 0) + printf("No PHY device found.\n"); + + return phyaddr; +} +#endif /* CFG_DISCOVER_PHY */ + +int mii_init(void) __attribute__((weak,alias("__mii_init"))); + +void __mii_init(void) +{ + volatile fec_t *fecp; + struct fec_info_s *info; + struct eth_device *dev; + int miispd = 0, i = 0; + u16 autoneg = 0; + + /* retrieve from register structure */ + dev = eth_get_dev(); + info = dev->priv; + + fecp = (fec_t *) info->miibase; + + fecpin_setclear(dev, 1); + + mii_reset(info); + + /* We use strictly polling mode only */ + fecp->eimr = 0; + + /* Clear any pending interrupt */ + fecp->eir = 0xffffffff; + + /* Set MII speed */ + miispd = (gd->bus_clk / 1000000) / 5; + fecp->mscr = miispd << 1; + + info->phy_addr = mii_discover_phy(dev); + +#define AUTONEGLINK (PHY_BMSR_AUTN_COMP | PHY_BMSR_LS) + while (i < MCFFEC_TOUT_LOOP) { + autoneg = 0; + miiphy_read(dev->name, info->phy_addr, PHY_BMSR, &autoneg); + i++; + + if ((autoneg & AUTONEGLINK) == AUTONEGLINK) + break; + + udelay(500); + } + if (i >= MCFFEC_TOUT_LOOP) { + printf("Auto Negotiation not complete\n"); + } + + /* adapt to the half/full speed settings */ + info->dup_spd = miiphy_duplex(dev->name, info->phy_addr) << 16; + info->dup_spd |= miiphy_speed(dev->name, info->phy_addr); +} + +/***************************************************************************** + * Read and write a MII PHY register, routines used by MII Utilities + * + * FIXME: These routines are expected to return 0 on success, but mii_send + * does _not_ return an error code. Maybe 0xFFFF means error, i.e. + * no PHY connected... + * For now always return 0. + * FIXME: These routines only work after calling eth_init() at least once! + * Otherwise they hang in mii_send() !!! Sorry! + *****************************************************************************/ + +int mcffec_miiphy_read(char *devname, unsigned char addr, unsigned char reg, + unsigned short *value) +{ + short rdreg; /* register working value */ + +#ifdef MII_DEBUG + printf("miiphy_read(0x%x) @ 0x%x = ", reg, addr); +#endif + rdreg = mii_send(mk_mii_read(addr, reg)); + + *value = rdreg; + +#ifdef MII_DEBUG + printf("0x%04x\n", *value); +#endif + + return 0; +} + +int mcffec_miiphy_write(char *devname, unsigned char addr, unsigned char reg, + unsigned short value) +{ + short rdreg; /* register working value */ + +#ifdef MII_DEBUG + printf("miiphy_write(0x%x) @ 0x%x = ", reg, addr); +#endif + + rdreg = mii_send(mk_mii_write(addr, reg, value)); + +#ifdef MII_DEBUG + printf("0x%04x\n", value); +#endif + + return 0; +} + +#endif /* CONFIG_CMD_NET, FEC_ENET & NET_MULTI */ diff --git a/include/configs/idmr.h b/include/configs/idmr.h index 1ab7b27a5..3ec4a7944 100644 --- a/include/configs/idmr.h +++ b/include/configs/idmr.h @@ -44,6 +44,8 @@ */ #define CONFIG_BOOTCOMMAND "run net_nfs" #define CONFIG_BOOTDELAY 5 +#define CONFIG_MCFUART +#define CFG_UART_PORT (0) #define CONFIG_BAUDRATE 19200 #define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 } #define CONFIG_ETHADDR 00:06:3b:01:41:55 @@ -58,6 +60,8 @@ #define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root " \ "filesystem over NFS; echo" +#define CONFIG_MCFTMR + #define CONFIG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0" \ "ramargs=setenv bootargs root=/dev/ram rw\0" \ @@ -147,11 +151,27 @@ /* * Ethernet */ -#define FEC_ENET -#define CONFIG_NET_RETRY_COUNT 5 -#define CFG_ENET_BD_BASE 0x480000 -#define CFG_DISCOVER_PHY 1 +#define CONFIG_MCFFEC +#ifdef CONFIG_MCFFEC +# define CONFIG_NET_MULTI 1 #define CONFIG_MII 1 +# define CFG_DISCOVER_PHY +# define CFG_RX_ETH_BUFFER 8 +# define CFG_FAULT_ECHO_LINK_DOWN + +# define CFG_FEC0_PINMUX 0 +# define CFG_FEC0_MIIBASE CFG_FEC0_IOBASE +# define MCFFEC_TOUT_LOOP 50000 +/* If CFG_DISCOVER_PHY is not defined - hardcoded */ +# ifndef CFG_DISCOVER_PHY +# define FECDUPLEX FULL +# define FECSPEED _100BASET +# else +# ifndef CFG_FAULT_ECHO_LINK_DOWN +# define CFG_FAULT_ECHO_LINK_DOWN +# endif +# endif /* CFG_DISCOVER_PHY */ +#endif /* * Definitions for initial stack pointer and data area (in DPRAM) @@ -186,7 +206,7 @@ * have to be in the first 8 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization ?? */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ +#define CFG_BOOTMAPSZ (CFG_SDRAM_BASE + (CFG_SDRAM_SIZE << 20)) /* FLASH organization */ #define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ @@ -215,8 +235,8 @@ "2m(rootfs)," \ "-(user)"; -#if defined(CONFIG_CMD_MII) +#if (CONFIG_COMMANDS & CFG_CMD_MII) #error MII commands don't work on iDMR board and sholud not be enabled. -#endif +#endif /* (CONFIG_COMMANDS & CFG_CMD_MII) */ #endif /* _IDMR_H */ From a9505510bf56a9b5558248dd8b73ec9d9a1556a2 Mon Sep 17 00:00:00 2001 From: TsiChungLiew Date: Wed, 15 Aug 2007 19:45:51 -0500 Subject: [PATCH 160/259] ColdFire: update r5200 platform for MCF52x2 Signed-off-by: TsiChungLiew --- board/r5200/Makefile | 2 +- board/r5200/mii.c | 303 ++++++++++++++++++++++++++++++++++++++++ include/configs/r5200.h | 30 +++- 3 files changed, 328 insertions(+), 7 deletions(-) create mode 100644 board/r5200/mii.c diff --git a/board/r5200/Makefile b/board/r5200/Makefile index 424ab1cf9..2ec71ee1d 100644 --- a/board/r5200/Makefile +++ b/board/r5200/Makefile @@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a -COBJS = $(BOARD).o +COBJS = $(BOARD).o mii.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/board/r5200/mii.c b/board/r5200/mii.c new file mode 100644 index 000000000..706c90f64 --- /dev/null +++ b/board/r5200/mii.c @@ -0,0 +1,303 @@ +/* + * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI) +#undef MII_DEBUG +#undef ET_DEBUG + +int fecpin_setclear(struct eth_device *dev, int setclear) +{ + if (setclear) { + /* Enable Ethernet pins */ + mbar_writeByte(MCF_GPIO_PAR_FECI2C, CFG_FECI2C); + } else { + } + + return 0; +} + +#if defined(CFG_DISCOVER_PHY) || defined(CONFIG_CMD_MII) +#include + +/* Make MII read/write commands for the FEC. */ +#define mk_mii_read(ADDR, REG) (0x60020000 | ((ADDR << 23) | (REG & 0x1f) << 18)) + +#define mk_mii_write(ADDR, REG, VAL) (0x50020000 | ((ADDR << 23) | (REG & 0x1f) << 18) | (VAL & 0xffff)) + +/* PHY identification */ +#define PHY_ID_LXT970 0x78100000 /* LXT970 */ +#define PHY_ID_LXT971 0x001378e0 /* LXT971 and 972 */ +#define PHY_ID_82555 0x02a80150 /* Intel 82555 */ +#define PHY_ID_QS6612 0x01814400 /* QS6612 */ +#define PHY_ID_AMD79C784 0x00225610 /* AMD 79C784 */ +#define PHY_ID_LSI80225 0x0016f870 /* LSI 80225 */ +#define PHY_ID_LSI80225B 0x0016f880 /* LSI 80225/B */ +#define PHY_ID_DP83848VV 0x20005C90 /* National 83848 */ +#define PHY_ID_DP83849 0x20005CA2 /* National 82849 */ +#define PHY_ID_KS8721BL 0x00221619 /* Micrel KS8721BL/SL */ + +#define STR_ID_LXT970 "LXT970" +#define STR_ID_LXT971 "LXT971" +#define STR_ID_82555 "Intel82555" +#define STR_ID_QS6612 "QS6612" +#define STR_ID_AMD79C784 "AMD79C784" +#define STR_ID_LSI80225 "LSI80225" +#define STR_ID_LSI80225B "LSI80225/B" +#define STR_ID_DP83848VV "N83848" +#define STR_ID_DP83849 "N83849" +#define STR_ID_KS8721BL "KS8721BL" + +/**************************************************************************** + * mii_init -- Initialize the MII for MII command without ethernet + * This function is a subset of eth_init + **************************************************************************** + */ +void mii_reset(struct fec_info_s *info) +{ + volatile fec_t *fecp = (fec_t *) (info->miibase); + int i; + + fecp->ecr = FEC_ECR_RESET; + for (i = 0; (fecp->ecr & FEC_ECR_RESET) && (i < FEC_RESET_DELAY); ++i) { + udelay(1); + } + if (i == FEC_RESET_DELAY) { + printf("FEC_RESET_DELAY timeout\n"); + } +} + +/* send command to phy using mii, wait for result */ +uint mii_send(uint mii_cmd) +{ + struct fec_info_s *info; + struct eth_device *dev; + volatile fec_t *ep; + uint mii_reply; + int j = 0; + + /* retrieve from register structure */ + dev = eth_get_dev(); + info = dev->priv; + + ep = (fec_t *) info->miibase; + + ep->mmfr = mii_cmd; /* command to phy */ + + /* wait for mii complete */ + while (!(ep->eir & FEC_EIR_MII) && (j < MCFFEC_TOUT_LOOP)) { + udelay(1); + j++; + } + if (j >= MCFFEC_TOUT_LOOP) { + printf("MII not complete\n"); + return -1; + } + + mii_reply = ep->mmfr; /* result from phy */ + ep->eir = FEC_EIR_MII; /* clear MII complete */ +#ifdef ET_DEBUG + printf("%s[%d] %s: sent=0x%8.8x, reply=0x%8.8x\n", + __FILE__, __LINE__, __FUNCTION__, mii_cmd, mii_reply); +#endif + + return (mii_reply & 0xffff); /* data read from phy */ +} +#endif /* CFG_DISCOVER_PHY || (CONFIG_CMD_MII) */ + +#if defined(CFG_DISCOVER_PHY) +int mii_discover_phy(struct eth_device *dev) +{ +#define MAX_PHY_PASSES 11 + struct fec_info_s *info = dev->priv; + int phyaddr, pass; + uint phyno, phytype; + + if (info->phyname_init) + return info->phy_addr; + + phyaddr = -1; /* didn't find a PHY yet */ + for (pass = 1; pass <= MAX_PHY_PASSES && phyaddr < 0; ++pass) { + if (pass > 1) { + /* PHY may need more time to recover from reset. + * The LXT970 needs 50ms typical, no maximum is + * specified, so wait 10ms before try again. + * With 11 passes this gives it 100ms to wake up. + */ + udelay(10000); /* wait 10ms */ + } + + for (phyno = 0; phyno < 32 && phyaddr < 0; ++phyno) { + + phytype = mii_send(mk_mii_read(phyno, PHY_PHYIDR1)); +#ifdef ET_DEBUG + printf("PHY type 0x%x pass %d type\n", phytype, pass); +#endif + if (phytype != 0xffff) { + phyaddr = phyno; + phytype <<= 16; + phytype |= + mii_send(mk_mii_read(phyno, PHY_PHYIDR2)); + + switch (phytype & 0xffffffff) { + case PHY_ID_KS8721BL: + strcpy(info->phy_name, + STR_ID_KS8721BL); + info->phyname_init = 1; + break; + default: + strcpy(info->phy_name, "unknown"); + info->phyname_init = 1; + break; + } + +#ifdef ET_DEBUG + printf("PHY @ 0x%x pass %d type ", phyno, pass); + switch (phytype & 0xffffffff) { + case PHY_ID_KS8721BL: + printf(STR_ID_KS8721BL); + break; + default: + printf("0x%08x\n", phytype); + break; + } +#endif + } + } + } + if (phyaddr < 0) + printf("No PHY device found.\n"); + + return phyaddr; +} +#endif /* CFG_DISCOVER_PHY */ + +int mii_init(void) __attribute__((weak,alias("__mii_init"))); + +void __mii_init(void) +{ + volatile fec_t *fecp; + struct fec_info_s *info; + struct eth_device *dev; + int miispd = 0, i = 0; + u16 autoneg = 0; + + /* retrieve from register structure */ + dev = eth_get_dev(); + info = dev->priv; + + fecp = (fec_t *) info->miibase; + + fecpin_setclear(dev, 1); + + mii_reset(info); + + /* We use strictly polling mode only */ + fecp->eimr = 0; + + /* Clear any pending interrupt */ + fecp->eir = 0xffffffff; + + /* Set MII speed */ + miispd = (gd->bus_clk / 1000000) / 5; + fecp->mscr = miispd << 1; + + info->phy_addr = mii_discover_phy(dev); + +#define AUTONEGLINK (PHY_BMSR_AUTN_COMP | PHY_BMSR_LS) + while (i < MCFFEC_TOUT_LOOP) { + autoneg = 0; + miiphy_read(dev->name, info->phy_addr, PHY_BMSR, &autoneg); + i++; + + if ((autoneg & AUTONEGLINK) == AUTONEGLINK) + break; + + udelay(500); + } + if (i >= MCFFEC_TOUT_LOOP) { + printf("Auto Negotiation not complete\n"); + } + + /* adapt to the half/full speed settings */ + info->dup_spd = miiphy_duplex(dev->name, info->phy_addr) << 16; + info->dup_spd |= miiphy_speed(dev->name, info->phy_addr); +} + +/***************************************************************************** + * Read and write a MII PHY register, routines used by MII Utilities + * + * FIXME: These routines are expected to return 0 on success, but mii_send + * does _not_ return an error code. Maybe 0xFFFF means error, i.e. + * no PHY connected... + * For now always return 0. + * FIXME: These routines only work after calling eth_init() at least once! + * Otherwise they hang in mii_send() !!! Sorry! + *****************************************************************************/ + +int mcffec_miiphy_read(char *devname, unsigned char addr, unsigned char reg, + unsigned short *value) +{ + short rdreg; /* register working value */ + +#ifdef MII_DEBUG + printf("miiphy_read(0x%x) @ 0x%x = ", reg, addr); +#endif + rdreg = mii_send(mk_mii_read(addr, reg)); + + *value = rdreg; + +#ifdef MII_DEBUG + printf("0x%04x\n", *value); +#endif + + return 0; +} + +int mcffec_miiphy_write(char *devname, unsigned char addr, unsigned char reg, + unsigned short value) +{ + short rdreg; /* register working value */ + +#ifdef MII_DEBUG + printf("miiphy_write(0x%x) @ 0x%x = ", reg, addr); +#endif + + rdreg = mii_send(mk_mii_write(addr, reg, value)); + +#ifdef MII_DEBUG + printf("0x%04x\n", value); +#endif + + return 0; +} + +#endif /* CONFIG_CMD_NET, FEC_ENET & NET_MULTI */ diff --git a/include/configs/r5200.h b/include/configs/r5200.h index 0e743bb2e..fc7658b9f 100644 --- a/include/configs/r5200.h +++ b/include/configs/r5200.h @@ -39,13 +39,10 @@ #define CONFIG_M5271 /* define processor type */ #define CONFIG_R5200 /* define board type */ -#define FEC_ENET -#define CONFIG_NET_RETRY_COUNT 5 - -#define CONFIG_IPADDR 192.168.0.172 -#define CONFIG_SERVERIP 192.168.0.148 -#define CONFIG_ETHADDR 00:06:3b:00:44:55 +#define CONFIG_MCFTMR +#define CONFIG_MCFUART +#define CFG_UART_PORT (0) #define CONFIG_BAUDRATE 19200 #define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 } @@ -87,6 +84,27 @@ #undef CONFIG_CMD_LOADS #undef CONFIG_CMD_LOADB +#define CONFIG_MCFFEC +#ifdef CONFIG_MCFFEC +# define CONFIG_NET_MULTI 1 +# define CONFIG_MII 1 +# define CFG_DISCOVER_PHY +# define CFG_RX_ETH_BUFFER 8 +# define CFG_FAULT_ECHO_LINK_DOWN + +# define CFG_FEC0_PINMUX 0 +# define CFG_FEC0_MIIBASE CFG_FEC0_IOBASE +# define MCFFEC_TOUT_LOOP 50000 +/* If CFG_DISCOVER_PHY is not defined - hardcoded */ +# ifndef CFG_DISCOVER_PHY +# define FECDUPLEX FULL +# define FECSPEED _100BASET +# else +# ifndef CFG_FAULT_ECHO_LINK_DOWN +# define CFG_FAULT_ECHO_LINK_DOWN +# endif +# endif /* CFG_DISCOVER_PHY */ +#endif /* Note: We only copy one sectors worth of application code from location * 10200000 for speed purposes. Increase the size if necessary */ From aa93d859d9b1fcd8eea52d51b06e86c38f72111b Mon Sep 17 00:00:00 2001 From: TsiChungLiew Date: Wed, 15 Aug 2007 19:46:38 -0500 Subject: [PATCH 161/259] ColdFire: update TASREG platform for MCF52x2 Signed-off-by: TsiChungLiew --- include/configs/TASREG.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/include/configs/TASREG.h b/include/configs/TASREG.h index 2b2ae01f6..dccdf0ca9 100644 --- a/include/configs/TASREG.h +++ b/include/configs/TASREG.h @@ -43,6 +43,10 @@ #define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */ +#define CONFIG_MCFTMR + +#define CONFIG_MCFUART +#define CFG_UART_PORT (0) #define CONFIG_BAUDRATE 19200 #define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 } From 870470dbf6f4bb9864e0d97aeedbc17c167c6d1c Mon Sep 17 00:00:00 2001 From: TsiChungLiew Date: Wed, 15 Aug 2007 19:55:10 -0500 Subject: [PATCH 162/259] ColdFire: Update EB+MCF-EV123 platform Signed-off-by: TsiChungLiew --- board/BuS/EB+MCF-EV123/Makefile | 2 +- board/BuS/EB+MCF-EV123/mii.c | 304 ++++++++++++++++++++++++++++++++ include/configs/EB+MCF-EV123.h | 41 ++++- 3 files changed, 340 insertions(+), 7 deletions(-) create mode 100644 board/BuS/EB+MCF-EV123/mii.c diff --git a/board/BuS/EB+MCF-EV123/Makefile b/board/BuS/EB+MCF-EV123/Makefile index ed3ac0755..ceeffa775 100644 --- a/board/BuS/EB+MCF-EV123/Makefile +++ b/board/BuS/EB+MCF-EV123/Makefile @@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a -COBJS = $(BOARD).o cfm_flash.o flash.o VCxK.o +COBJS = $(BOARD).o cfm_flash.o flash.o VCxK.o mii.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/board/BuS/EB+MCF-EV123/mii.c b/board/BuS/EB+MCF-EV123/mii.c new file mode 100644 index 000000000..ebd3ed938 --- /dev/null +++ b/board/BuS/EB+MCF-EV123/mii.c @@ -0,0 +1,304 @@ +/* + * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI) +#undef MII_DEBUG +#undef ET_DEBUG + +int fecpin_setclear(struct eth_device *dev, int setclear) +{ + if (setclear) { + MCFGPIO_PASPAR |= 0x0F00; + MCFGPIO_PEHLPAR = CFG_PEHLPAR; + } else { + MCFGPIO_PASPAR &= 0xF0FF; + MCFGPIO_PEHLPAR &= ~CFG_PEHLPAR; + } + return 0; +} + +#if defined(CFG_DISCOVER_PHY) || defined(CONFIG_CMD_MII) +#include + +/* Make MII read/write commands for the FEC. */ +#define mk_mii_read(ADDR, REG) (0x60020000 | ((ADDR << 23) | (REG & 0x1f) << 18)) + +#define mk_mii_write(ADDR, REG, VAL) (0x50020000 | ((ADDR << 23) | (REG & 0x1f) << 18) | (VAL & 0xffff)) + +/* PHY identification */ +#define PHY_ID_LXT970 0x78100000 /* LXT970 */ +#define PHY_ID_LXT971 0x001378e0 /* LXT971 and 972 */ +#define PHY_ID_82555 0x02a80150 /* Intel 82555 */ +#define PHY_ID_QS6612 0x01814400 /* QS6612 */ +#define PHY_ID_AMD79C784 0x00225610 /* AMD 79C784 */ +#define PHY_ID_AMD79C874VC 0x0022561B /* AMD 79C874 */ +#define PHY_ID_LSI80225 0x0016f870 /* LSI 80225 */ +#define PHY_ID_LSI80225B 0x0016f880 /* LSI 80225/B */ +#define PHY_ID_DP83848VV 0x20005C90 /* National 83848 */ +#define PHY_ID_DP83849 0x20005CA2 /* National 82849 */ + +#define STR_ID_LXT970 "LXT970" +#define STR_ID_LXT971 "LXT971" +#define STR_ID_82555 "Intel82555" +#define STR_ID_QS6612 "QS6612" +#define STR_ID_AMD79C784 "AMD79C784" +#define STR_ID_AMD79C874VC "AMD79C874VC" +#define STR_ID_LSI80225 "LSI80225" +#define STR_ID_LSI80225B "LSI80225/B" +#define STR_ID_DP83848VV "N83848" +#define STR_ID_DP83849 "N83849" + +/**************************************************************************** + * mii_init -- Initialize the MII for MII command without ethernet + * This function is a subset of eth_init + **************************************************************************** + */ +void mii_reset(struct fec_info_s *info) +{ + volatile fec_t *fecp = (fec_t *) (info->miibase); + int i; + + fecp->ecr = FEC_ECR_RESET; + for (i = 0; (fecp->ecr & FEC_ECR_RESET) && (i < FEC_RESET_DELAY); ++i) { + udelay(1); + } + if (i == FEC_RESET_DELAY) { + printf("FEC_RESET_DELAY timeout\n"); + } +} + +/* send command to phy using mii, wait for result */ +uint mii_send(uint mii_cmd) +{ + struct fec_info_s *info; + struct eth_device *dev; + volatile fec_t *ep; + uint mii_reply; + int j = 0; + + /* retrieve from register structure */ + dev = eth_get_dev(); + info = dev->priv; + + ep = (fec_t *) info->miibase; + + ep->mmfr = mii_cmd; /* command to phy */ + + /* wait for mii complete */ + while (!(ep->eir & FEC_EIR_MII) && (j < MCFFEC_TOUT_LOOP)) { + udelay(1); + j++; + } + if (j >= MCFFEC_TOUT_LOOP) { + printf("MII not complete\n"); + return -1; + } + + mii_reply = ep->mmfr; /* result from phy */ + ep->eir = FEC_EIR_MII; /* clear MII complete */ +#ifdef ET_DEBUG + printf("%s[%d] %s: sent=0x%8.8x, reply=0x%8.8x\n", + __FILE__, __LINE__, __FUNCTION__, mii_cmd, mii_reply); +#endif + + return (mii_reply & 0xffff); /* data read from phy */ +} +#endif /* CFG_DISCOVER_PHY || (CONFIG_COMMANDS & CONFIG_CMD_MII) */ + +#if defined(CFG_DISCOVER_PHY) +int mii_discover_phy(struct eth_device *dev) +{ +#define MAX_PHY_PASSES 11 + struct fec_info_s *info = dev->priv; + int phyaddr, pass; + uint phyno, phytype; + + if (info->phyname_init) + return info->phy_addr; + + phyaddr = -1; /* didn't find a PHY yet */ + for (pass = 1; pass <= MAX_PHY_PASSES && phyaddr < 0; ++pass) { + if (pass > 1) { + /* PHY may need more time to recover from reset. + * The LXT970 needs 50ms typical, no maximum is + * specified, so wait 10ms before try again. + * With 11 passes this gives it 100ms to wake up. + */ + udelay(10000); /* wait 10ms */ + } + + for (phyno = 0; phyno < 32 && phyaddr < 0; ++phyno) { + + phytype = mii_send(mk_mii_read(phyno, PHY_PHYIDR1)); +#ifdef ET_DEBUG + printf("PHY type 0x%x pass %d type\n", phytype, pass); +#endif + if (phytype != 0xffff) { + phyaddr = phyno; + phytype <<= 16; + phytype |= + mii_send(mk_mii_read(phyno, PHY_PHYIDR2)); + + switch (phytype & 0xffffffff) { + case PHY_ID_AMD79C874VC: + strcpy(info->phy_name, + STR_ID_AMD79C874VC); + info->phyname_init = 1; + break; + default: + strcpy(info->phy_name, "unknown"); + info->phyname_init = 1; + break; + } + +#ifdef ET_DEBUG + printf("PHY @ 0x%x pass %d type ", phyno, pass); + switch (phytype & 0xffffffff) { + case PHY_ID_AMD79C874VC: + printf(STR_ID_AMD79C874VC); + break; + default: + printf("0x%08x\n", phytype); + break; + } +#endif + } + } + } + if (phyaddr < 0) + printf("No PHY device found.\n"); + + return phyaddr; +} +#endif /* CFG_DISCOVER_PHY */ + +int mii_init(void) __attribute__((weak,alias("__mii_init"))); + +void __mii_init(void) +{ + volatile fec_t *fecp; + struct fec_info_s *info; + struct eth_device *dev; + int miispd = 0, i = 0; + u16 autoneg = 0; + + /* retrieve from register structure */ + dev = eth_get_dev(); + info = dev->priv; + + fecp = (fec_t *) info->miibase; + + fecpin_setclear(dev, 1); + + mii_reset(info); + + /* We use strictly polling mode only */ + fecp->eimr = 0; + + /* Clear any pending interrupt */ + fecp->eir = 0xffffffff; + + /* Set MII speed */ + miispd = (gd->bus_clk / 1000000) / 5; + fecp->mscr = miispd << 1; + + info->phy_addr = mii_discover_phy(dev); + +#define AUTONEGLINK (PHY_BMSR_AUTN_COMP | PHY_BMSR_LS) + while (i < MCFFEC_TOUT_LOOP) { + autoneg = 0; + miiphy_read(dev->name, info->phy_addr, PHY_BMSR, &autoneg); + i++; + + if ((autoneg & AUTONEGLINK) == AUTONEGLINK) + break; + + udelay(500); + } + if (i >= MCFFEC_TOUT_LOOP) { + printf("Auto Negotiation not complete\n"); + } + + /* adapt to the half/full speed settings */ + info->dup_spd = miiphy_duplex(dev->name, info->phy_addr) << 16; + info->dup_spd |= miiphy_speed(dev->name, info->phy_addr); +} + +/***************************************************************************** + * Read and write a MII PHY register, routines used by MII Utilities + * + * FIXME: These routines are expected to return 0 on success, but mii_send + * does _not_ return an error code. Maybe 0xFFFF means error, i.e. + * no PHY connected... + * For now always return 0. + * FIXME: These routines only work after calling eth_init() at least once! + * Otherwise they hang in mii_send() !!! Sorry! + *****************************************************************************/ + +int mcffec_miiphy_read(char *devname, unsigned char addr, unsigned char reg, + unsigned short *value) +{ + short rdreg; /* register working value */ + +#ifdef MII_DEBUG + printf("miiphy_read(0x%x) @ 0x%x = ", reg, addr); +#endif + rdreg = mii_send(mk_mii_read(addr, reg)); + + *value = rdreg; + +#ifdef MII_DEBUG + printf("0x%04x\n", *value); +#endif + + return 0; +} + +int mcffec_miiphy_write(char *devname, unsigned char addr, unsigned char reg, + unsigned short value) +{ + short rdreg; /* register working value */ + +#ifdef MII_DEBUG + printf("miiphy_write(0x%x) @ 0x%x = ", reg, addr); +#endif + + rdreg = mii_send(mk_mii_write(addr, reg, value)); + +#ifdef MII_DEBUG + printf("0x%04x\n", value); +#endif + + return 0; +} + +#endif /* CONFIG_CMD_NET, FEC_ENET & NET_MULTI */ diff --git a/include/configs/EB+MCF-EV123.h b/include/configs/EB+MCF-EV123.h index a8697ec88..dae5295dd 100644 --- a/include/configs/EB+MCF-EV123.h +++ b/include/configs/EB+MCF-EV123.h @@ -40,9 +40,8 @@ #define CONFIG_MISC_INIT_R -#define FEC_ENET -#define CONFIG_ETHADDR 00:CF:52:82:EB:01 - +#define CONFIG_MCFUART +#define CFG_UART_PORT (0) #define CONFIG_BAUDRATE 9600 #define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 } @@ -84,7 +83,39 @@ #include #undef CONFIG_CMD_LOADB +#define CONFIG_CMD_MII +#define CONFIG_CMD_NET +#define CONFIG_MCFFEC +#ifdef CONFIG_MCFFEC +# define CONFIG_NET_MULTI 1 +# define CONFIG_MII 1 +# define CFG_DISCOVER_PHY +# define CFG_RX_ETH_BUFFER 8 +# define CFG_FAULT_ECHO_LINK_DOWN + +# define CFG_FEC0_PINMUX 0 +# define CFG_FEC0_MIIBASE CFG_FEC0_IOBASE +# define MCFFEC_TOUT_LOOP 50000 +/* If CFG_DISCOVER_PHY is not defined - hardcoded */ +# ifndef CFG_DISCOVER_PHY +# define FECDUPLEX FULL +# define FECSPEED _100BASET +# else +# ifndef CFG_FAULT_ECHO_LINK_DOWN +# define CFG_FAULT_ECHO_LINK_DOWN +# endif +# endif /* CFG_DISCOVER_PHY */ +#endif + +#ifdef CONFIG_MCFFEC +# define CONFIG_ETHADDR 00:CF:52:82:EB:01 +# define CONFIG_IPADDR 192.162.1.2 +# define CONFIG_NETMASK 255.255.255.0 +# define CONFIG_SERVERIP 192.162.1.1 +# define CONFIG_GATEWAYIP 192.162.1.1 +# define CONFIG_OVERWRITE_ETHADDR_ONCE +#endif /* CONFIG_MCFFEC */ #define CONFIG_BOOTDELAY 5 #define CFG_PROMPT "\nEV123 U-Boot> " @@ -122,9 +153,6 @@ */ #define CFG_MBAR 0x40000000 -#define CFG_DISCOVER_PHY -/* #define CFG_ENET_BD_BASE 0x380000 */ - /*----------------------------------------------------------------------- * Definitions for initial stack pointer and data area (in DPRAM) */ @@ -151,6 +179,7 @@ #define CFG_FLASH_BASE 0xFFE00000 #define CFG_INT_FLASH_BASE 0xF0000000 +#define CFG_INT_FLASH_ENABLE 0x21 /* If M5282 port is fully implemented the monitor base will be behind * the vector table. */ From f28e1bd9daa6de5eb33ae4822bda6b008ccb4e9e Mon Sep 17 00:00:00 2001 From: TsiChungLiew Date: Wed, 15 Aug 2007 20:32:06 -0500 Subject: [PATCH 163/259] ColdFire: Update Freescale MCF52x2 platforms Signed-off-by: TsiChungLiew --- board/m5271evb/Makefile | 2 +- board/m5271evb/m5271evb.c | 3 +- board/m5271evb/mii.c | 303 +++++++++++++++++++++++++++++ board/m5272c3/Makefile | 2 +- board/m5272c3/m5272c3.c | 7 +- board/m5272c3/mii.c | 303 +++++++++++++++++++++++++++++ board/m5282evb/Makefile | 2 +- board/m5282evb/config.mk | 2 +- board/m5282evb/flash.c | 378 ------------------------------------- board/m5282evb/m5282evb.c | 61 +++++- board/m5282evb/mii.c | 304 +++++++++++++++++++++++++++++ include/configs/M5271EVB.h | 100 +++++++--- include/configs/M5272C3.h | 105 +++++++---- include/configs/M5282EVB.h | 147 ++++++++++++--- 14 files changed, 1238 insertions(+), 481 deletions(-) create mode 100644 board/m5271evb/mii.c create mode 100644 board/m5272c3/mii.c delete mode 100644 board/m5282evb/flash.c create mode 100644 board/m5282evb/mii.c diff --git a/board/m5271evb/Makefile b/board/m5271evb/Makefile index 424ab1cf9..2ec71ee1d 100644 --- a/board/m5271evb/Makefile +++ b/board/m5271evb/Makefile @@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a -COBJS = $(BOARD).o +COBJS = $(BOARD).o mii.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/board/m5271evb/m5271evb.c b/board/m5271evb/m5271evb.c index c26c91d1b..9caad6325 100644 --- a/board/m5271evb/m5271evb.c +++ b/board/m5271evb/m5271evb.c @@ -22,8 +22,7 @@ */ #include -#include -#include +#include int checkboard (void) { puts ("Board: Freescale M5271EVB\n"); diff --git a/board/m5271evb/mii.c b/board/m5271evb/mii.c new file mode 100644 index 000000000..f6c63c302 --- /dev/null +++ b/board/m5271evb/mii.c @@ -0,0 +1,303 @@ +/* + * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI) +#undef MII_DEBUG +#undef ET_DEBUG + +int fecpin_setclear(struct eth_device *dev, int setclear) +{ + if (setclear) { + /* Enable Ethernet pins */ + mbar_writeByte(MCF_GPIO_PAR_FECI2C, CFG_FECI2C); + } else { + } + + return 0; +} + +#if defined(CFG_DISCOVER_PHY) || defined(CONFIG_CMD_MII) +#include + +/* Make MII read/write commands for the FEC. */ +#define mk_mii_read(ADDR, REG) (0x60020000 | ((ADDR << 23) | (REG & 0x1f) << 18)) + +#define mk_mii_write(ADDR, REG, VAL) (0x50020000 | ((ADDR << 23) | (REG & 0x1f) << 18) | (VAL & 0xffff)) + +/* PHY identification */ +#define PHY_ID_LXT970 0x78100000 /* LXT970 */ +#define PHY_ID_LXT971 0x001378e0 /* LXT971 and 972 */ +#define PHY_ID_82555 0x02a80150 /* Intel 82555 */ +#define PHY_ID_QS6612 0x01814400 /* QS6612 */ +#define PHY_ID_AMD79C784 0x00225610 /* AMD 79C784 */ +#define PHY_ID_LSI80225 0x0016f870 /* LSI 80225 */ +#define PHY_ID_LSI80225B 0x0016f880 /* LSI 80225/B */ +#define PHY_ID_DP83848VV 0x20005C90 /* National 83848 */ +#define PHY_ID_DP83849 0x20005CA2 /* National 82849 */ +#define PHY_ID_KS8721BL 0x00221619 /* Micrel KS8721BL/SL */ + +#define STR_ID_LXT970 "LXT970" +#define STR_ID_LXT971 "LXT971" +#define STR_ID_82555 "Intel82555" +#define STR_ID_QS6612 "QS6612" +#define STR_ID_AMD79C784 "AMD79C784" +#define STR_ID_LSI80225 "LSI80225" +#define STR_ID_LSI80225B "LSI80225/B" +#define STR_ID_DP83848VV "N83848" +#define STR_ID_DP83849 "N83849" +#define STR_ID_KS8721BL "KS8721BL" + +/**************************************************************************** + * mii_init -- Initialize the MII for MII command without ethernet + * This function is a subset of eth_init + **************************************************************************** + */ +void mii_reset(struct fec_info_s *info) +{ + volatile fec_t *fecp = (fec_t *) (info->miibase); + int i; + + fecp->ecr = FEC_ECR_RESET; + for (i = 0; (fecp->ecr & FEC_ECR_RESET) && (i < FEC_RESET_DELAY); ++i) { + udelay(1); + } + if (i == FEC_RESET_DELAY) { + printf("FEC_RESET_DELAY timeout\n"); + } +} + +/* send command to phy using mii, wait for result */ +uint mii_send(uint mii_cmd) +{ + struct fec_info_s *info; + struct eth_device *dev; + volatile fec_t *ep; + uint mii_reply; + int j = 0; + + /* retrieve from register structure */ + dev = eth_get_dev(); + info = dev->priv; + + ep = (fec_t *) info->miibase; + + ep->mmfr = mii_cmd; /* command to phy */ + + /* wait for mii complete */ + while (!(ep->eir & FEC_EIR_MII) && (j < MCFFEC_TOUT_LOOP)) { + udelay(1); + j++; + } + if (j >= MCFFEC_TOUT_LOOP) { + printf("MII not complete\n"); + return -1; + } + + mii_reply = ep->mmfr; /* result from phy */ + ep->eir = FEC_EIR_MII; /* clear MII complete */ +#ifdef ET_DEBUG + printf("%s[%d] %s: sent=0x%8.8x, reply=0x%8.8x\n", + __FILE__, __LINE__, __FUNCTION__, mii_cmd, mii_reply); +#endif + + return (mii_reply & 0xffff); /* data read from phy */ +} +#endif /* CFG_DISCOVER_PHY || (CONFIG_COMMANDS & CONFIG_CMD_MII) */ + +#if defined(CFG_DISCOVER_PHY) +int mii_discover_phy(struct eth_device *dev) +{ +#define MAX_PHY_PASSES 11 + struct fec_info_s *info = dev->priv; + int phyaddr, pass; + uint phyno, phytype; + + if (info->phyname_init) + return info->phy_addr; + + phyaddr = -1; /* didn't find a PHY yet */ + for (pass = 1; pass <= MAX_PHY_PASSES && phyaddr < 0; ++pass) { + if (pass > 1) { + /* PHY may need more time to recover from reset. + * The LXT970 needs 50ms typical, no maximum is + * specified, so wait 10ms before try again. + * With 11 passes this gives it 100ms to wake up. + */ + udelay(10000); /* wait 10ms */ + } + + for (phyno = 0; phyno < 32 && phyaddr < 0; ++phyno) { + + phytype = mii_send(mk_mii_read(phyno, PHY_PHYIDR1)); +#ifdef ET_DEBUG + printf("PHY type 0x%x pass %d type\n", phytype, pass); +#endif + if (phytype != 0xffff) { + phyaddr = phyno; + phytype <<= 16; + phytype |= + mii_send(mk_mii_read(phyno, PHY_PHYIDR2)); + + switch (phytype & 0xffffffff) { + case PHY_ID_KS8721BL: + strcpy(info->phy_name, + STR_ID_KS8721BL); + info->phyname_init = 1; + break; + default: + strcpy(info->phy_name, "unknown"); + info->phyname_init = 1; + break; + } + +#ifdef ET_DEBUG + printf("PHY @ 0x%x pass %d type ", phyno, pass); + switch (phytype & 0xffffffff) { + case PHY_ID_KS8721BL: + printf(STR_ID_KS8721BL); + break; + default: + printf("0x%08x\n", phytype); + break; + } +#endif + } + } + } + if (phyaddr < 0) + printf("No PHY device found.\n"); + + return phyaddr; +} +#endif /* CFG_DISCOVER_PHY */ + +int mii_init(void) __attribute__((weak,alias("__mii_init"))); + +void __mii_init(void) +{ + volatile fec_t *fecp; + struct fec_info_s *info; + struct eth_device *dev; + int miispd = 0, i = 0; + u16 autoneg = 0; + + /* retrieve from register structure */ + dev = eth_get_dev(); + info = dev->priv; + + fecp = (fec_t *) info->miibase; + + fecpin_setclear(dev, 1); + + mii_reset(info); + + /* We use strictly polling mode only */ + fecp->eimr = 0; + + /* Clear any pending interrupt */ + fecp->eir = 0xffffffff; + + /* Set MII speed */ + miispd = (gd->bus_clk / 1000000) / 5; + fecp->mscr = miispd << 1; + + info->phy_addr = mii_discover_phy(dev); + +#define AUTONEGLINK (PHY_BMSR_AUTN_COMP | PHY_BMSR_LS) + while (i < MCFFEC_TOUT_LOOP) { + autoneg = 0; + miiphy_read(dev->name, info->phy_addr, PHY_BMSR, &autoneg); + i++; + + if ((autoneg & AUTONEGLINK) == AUTONEGLINK) + break; + + udelay(500); + } + if (i >= MCFFEC_TOUT_LOOP) { + printf("Auto Negotiation not complete\n"); + } + + /* adapt to the half/full speed settings */ + info->dup_spd = miiphy_duplex(dev->name, info->phy_addr) << 16; + info->dup_spd |= miiphy_speed(dev->name, info->phy_addr); +} + +/***************************************************************************** + * Read and write a MII PHY register, routines used by MII Utilities + * + * FIXME: These routines are expected to return 0 on success, but mii_send + * does _not_ return an error code. Maybe 0xFFFF means error, i.e. + * no PHY connected... + * For now always return 0. + * FIXME: These routines only work after calling eth_init() at least once! + * Otherwise they hang in mii_send() !!! Sorry! + *****************************************************************************/ + +int mcffec_miiphy_read(char *devname, unsigned char addr, unsigned char reg, + unsigned short *value) +{ + short rdreg; /* register working value */ + +#ifdef MII_DEBUG + printf("miiphy_read(0x%x) @ 0x%x = ", reg, addr); +#endif + rdreg = mii_send(mk_mii_read(addr, reg)); + + *value = rdreg; + +#ifdef MII_DEBUG + printf("0x%04x\n", *value); +#endif + + return 0; +} + +int mcffec_miiphy_write(char *devname, unsigned char addr, unsigned char reg, + unsigned short value) +{ + short rdreg; /* register working value */ + +#ifdef MII_DEBUG + printf("miiphy_write(0x%x) @ 0x%x = ", reg, addr); +#endif + + rdreg = mii_send(mk_mii_write(addr, reg, value)); + +#ifdef MII_DEBUG + printf("0x%04x\n", value); +#endif + + return 0; +} + +#endif /* CONFIG_CMD_NET, FEC_ENET & NET_MULTI */ diff --git a/board/m5272c3/Makefile b/board/m5272c3/Makefile index cf07cf40f..be704b76f 100644 --- a/board/m5272c3/Makefile +++ b/board/m5272c3/Makefile @@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a -COBJS = $(BOARD).o flash.o +COBJS = $(BOARD).o flash.o mii.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/board/m5272c3/m5272c3.c b/board/m5272c3/m5272c3.c index 0dfeaf24f..6dcda4f25 100644 --- a/board/m5272c3/m5272c3.c +++ b/board/m5272c3/m5272c3.c @@ -22,18 +22,17 @@ */ #include -#include -#include +#include int checkboard (void) { puts ("Board: "); - puts("MOTOROLA MCF5272C3 EVB\n"); + puts ("Freescale MCF5272C3 EVB\n"); return 0; }; long int initdram (int board_type) { - volatile sdramctrl_t * sdp = (sdramctrl_t *)(CFG_MBAR + MCFSIM_SDCR); + volatile sdramctrl_t * sdp = (sdramctrl_t *)(MMAP_SDRAM); sdp->sdram_sdtr = 0xf539; sdp->sdram_sdcr = 0x4211; diff --git a/board/m5272c3/mii.c b/board/m5272c3/mii.c new file mode 100644 index 000000000..fadcbb3ef --- /dev/null +++ b/board/m5272c3/mii.c @@ -0,0 +1,303 @@ +/* + * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI) +#undef MII_DEBUG +#undef ET_DEBUG + +int fecpin_setclear(struct eth_device *dev, int setclear) +{ + volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; + + if (setclear) { + gpio->gpio_pbcnt |= GPIO_PBCNT_E_MDC | GPIO_PBCNT_E_RXER | GPIO_PBCNT_E_RXD1 | GPIO_PBCNT_E_RXD2 | GPIO_PBCNT_E_RXD3 | GPIO_PBCNT_E_TXD1 | GPIO_PBCNT_E_TXD2 | GPIO_PBCNT_E_TXD3; + } else { + } + return 0; +} + +#if defined(CFG_DISCOVER_PHY) || defined(CONFIG_CMD_MII) +#include + +/* Make MII read/write commands for the FEC. */ +#define mk_mii_read(ADDR, REG) (0x60020000 | ((ADDR << 23) | (REG & 0x1f) << 18)) + +#define mk_mii_write(ADDR, REG, VAL) (0x50020000 | ((ADDR << 23) | (REG & 0x1f) << 18) | (VAL & 0xffff)) + +/* PHY identification */ +#define PHY_ID_LXT970 0x78100000 /* LXT970 */ +#define PHY_ID_LXT971 0x001378e0 /* LXT971 and 972 */ +#define PHY_ID_82555 0x02a80150 /* Intel 82555 */ +#define PHY_ID_QS6612 0x01814400 /* QS6612 */ +#define PHY_ID_AMD79C784 0x00225610 /* AMD 79C784 */ +#define PHY_ID_AMD79C874VC 0x0022561B /* AMD 79C874 */ +#define PHY_ID_LSI80225 0x0016f870 /* LSI 80225 */ +#define PHY_ID_LSI80225B 0x0016f880 /* LSI 80225/B */ +#define PHY_ID_DP83848VV 0x20005C90 /* National 83848 */ +#define PHY_ID_DP83849 0x20005CA2 /* National 82849 */ + +#define STR_ID_LXT970 "LXT970" +#define STR_ID_LXT971 "LXT971" +#define STR_ID_82555 "Intel82555" +#define STR_ID_QS6612 "QS6612" +#define STR_ID_AMD79C784 "AMD79C784" +#define STR_ID_AMD79C874VC "AMD79C874VC" +#define STR_ID_LSI80225 "LSI80225" +#define STR_ID_LSI80225B "LSI80225/B" +#define STR_ID_DP83848VV "N83848" +#define STR_ID_DP83849 "N83849" + +/**************************************************************************** + * mii_init -- Initialize the MII for MII command without ethernet + * This function is a subset of eth_init + **************************************************************************** + */ +void mii_reset(struct fec_info_s *info) +{ + volatile fec_t *fecp = (fec_t *) (info->miibase); + int i; + + fecp->ecr = FEC_ECR_RESET; + for (i = 0; (fecp->ecr & FEC_ECR_RESET) && (i < FEC_RESET_DELAY); ++i) { + udelay(1); + } + if (i == FEC_RESET_DELAY) { + printf("FEC_RESET_DELAY timeout\n"); + } +} + +/* send command to phy using mii, wait for result */ +uint mii_send(uint mii_cmd) +{ + struct fec_info_s *info; + struct eth_device *dev; + volatile fec_t *ep; + uint mii_reply; + int j = 0; + + /* retrieve from register structure */ + dev = eth_get_dev(); + info = dev->priv; + + ep = (fec_t *) info->miibase; + + ep->mmfr = mii_cmd; /* command to phy */ + + /* wait for mii complete */ + while (!(ep->eir & FEC_EIR_MII) && (j < MCFFEC_TOUT_LOOP)) { + udelay(1); + j++; + } + if (j >= MCFFEC_TOUT_LOOP) { + printf("MII not complete\n"); + return -1; + } + + mii_reply = ep->mmfr; /* result from phy */ + ep->eir = FEC_EIR_MII; /* clear MII complete */ +#ifdef ET_DEBUG + printf("%s[%d] %s: sent=0x%8.8x, reply=0x%8.8x\n", + __FILE__, __LINE__, __FUNCTION__, mii_cmd, mii_reply); +#endif + + return (mii_reply & 0xffff); /* data read from phy */ +} +#endif /* CFG_DISCOVER_PHY || (CONFIG_COMMANDS & CONFIG_CMD_MII) */ + +#if defined(CFG_DISCOVER_PHY) +int mii_discover_phy(struct eth_device *dev) +{ +#define MAX_PHY_PASSES 11 + struct fec_info_s *info = dev->priv; + int phyaddr, pass; + uint phyno, phytype; + + if (info->phyname_init) + return info->phy_addr; + + phyaddr = -1; /* didn't find a PHY yet */ + for (pass = 1; pass <= MAX_PHY_PASSES && phyaddr < 0; ++pass) { + if (pass > 1) { + /* PHY may need more time to recover from reset. + * The LXT970 needs 50ms typical, no maximum is + * specified, so wait 10ms before try again. + * With 11 passes this gives it 100ms to wake up. + */ + udelay(10000); /* wait 10ms */ + } + + for (phyno = 0; phyno < 32 && phyaddr < 0; ++phyno) { + + phytype = mii_send(mk_mii_read(phyno, PHY_PHYIDR1)); +#ifdef ET_DEBUG + printf("PHY type 0x%x pass %d type\n", phytype, pass); +#endif + if (phytype != 0xffff) { + phyaddr = phyno; + phytype <<= 16; + phytype |= + mii_send(mk_mii_read(phyno, PHY_PHYIDR2)); + + switch (phytype & 0xffffffff) { + case PHY_ID_AMD79C874VC: + strcpy(info->phy_name, + STR_ID_AMD79C874VC); + info->phyname_init = 1; + break; + default: + strcpy(info->phy_name, "unknown"); + info->phyname_init = 1; + break; + } + +#ifdef ET_DEBUG + printf("PHY @ 0x%x pass %d type ", phyno, pass); + switch (phytype & 0xffffffff) { + case PHY_ID_AMD79C874VC: + printf(STR_ID_AMD79C874VC); + break; + default: + printf("0x%08x\n", phytype); + break; + } +#endif + } + } + } + if (phyaddr < 0) + printf("No PHY device found.\n"); + + return phyaddr; +} +#endif /* CFG_DISCOVER_PHY */ + +int mii_init(void) __attribute__((weak,alias("__mii_init"))); + +void __mii_init(void) +{ + volatile fec_t *fecp; + struct fec_info_s *info; + struct eth_device *dev; + int miispd = 0, i = 0; + u16 autoneg = 0; + + /* retrieve from register structure */ + dev = eth_get_dev(); + info = dev->priv; + + fecp = (fec_t *) info->miibase; + + fecpin_setclear(dev, 1); + + mii_reset(info); + + /* We use strictly polling mode only */ + fecp->eimr = 0; + + /* Clear any pending interrupt */ + fecp->eir = 0xffffffff; + + /* Set MII speed */ + miispd = (gd->bus_clk / 1000000) / 5; + fecp->mscr = miispd << 1; + + info->phy_addr = mii_discover_phy(dev); + +#define AUTONEGLINK (PHY_BMSR_AUTN_COMP | PHY_BMSR_LS) + while (i < MCFFEC_TOUT_LOOP) { + autoneg = 0; + miiphy_read(dev->name, info->phy_addr, PHY_BMSR, &autoneg); + i++; + + if ((autoneg & AUTONEGLINK) == AUTONEGLINK) + break; + + udelay(500); + } + if (i >= MCFFEC_TOUT_LOOP) { + printf("Auto Negotiation not complete\n"); + } + + /* adapt to the half/full speed settings */ + info->dup_spd = miiphy_duplex(dev->name, info->phy_addr) << 16; + info->dup_spd |= miiphy_speed(dev->name, info->phy_addr); +} + +/***************************************************************************** + * Read and write a MII PHY register, routines used by MII Utilities + * + * FIXME: These routines are expected to return 0 on success, but mii_send + * does _not_ return an error code. Maybe 0xFFFF means error, i.e. + * no PHY connected... + * For now always return 0. + * FIXME: These routines only work after calling eth_init() at least once! + * Otherwise they hang in mii_send() !!! Sorry! + *****************************************************************************/ + +int mcffec_miiphy_read(char *devname, unsigned char addr, unsigned char reg, + unsigned short *value) +{ + short rdreg; /* register working value */ + +#ifdef MII_DEBUG + printf("miiphy_read(0x%x) @ 0x%x = ", reg, addr); +#endif + rdreg = mii_send(mk_mii_read(addr, reg)); + + *value = rdreg; + +#ifdef MII_DEBUG + printf("0x%04x\n", *value); +#endif + + return 0; +} + +int mcffec_miiphy_write(char *devname, unsigned char addr, unsigned char reg, + unsigned short value) +{ + short rdreg; /* register working value */ + +#ifdef MII_DEBUG + printf("miiphy_write(0x%x) @ 0x%x = ", reg, addr); +#endif + + rdreg = mii_send(mk_mii_write(addr, reg, value)); + +#ifdef MII_DEBUG + printf("0x%04x\n", value); +#endif + + return 0; +} + +#endif /* CONFIG_CMD_NET, FEC_ENET & NET_MULTI */ diff --git a/board/m5282evb/Makefile b/board/m5282evb/Makefile index cf07cf40f..2ec71ee1d 100644 --- a/board/m5282evb/Makefile +++ b/board/m5282evb/Makefile @@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a -COBJS = $(BOARD).o flash.o +COBJS = $(BOARD).o mii.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/board/m5282evb/config.mk b/board/m5282evb/config.mk index 848430736..0aa236122 100644 --- a/board/m5282evb/config.mk +++ b/board/m5282evb/config.mk @@ -22,4 +22,4 @@ # MA 02111-1307 USA # -TEXT_BASE = 0x20000 +TEXT_BASE = 0xFFE00000 diff --git a/board/m5282evb/flash.c b/board/m5282evb/flash.c deleted file mode 100644 index 36a7c310f..000000000 --- a/board/m5282evb/flash.c +++ /dev/null @@ -1,378 +0,0 @@ -/* - * (C) Copyright 2000-2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include - -#define PHYS_FLASH_1 CFG_FLASH_BASE -#define FLASH_BANK_SIZE 0x200000 - -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; - -void flash_print_info (flash_info_t * info) -{ - int i; - - switch (info->flash_id & FLASH_VENDMASK) { - case (AMD_MANUFACT & FLASH_VENDMASK): - printf ("AMD: "); - break; - default: - printf ("Unknown Vendor "); - break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case (AMD_ID_PL160CB & FLASH_TYPEMASK): - printf ("AM29PL160CB (16Mbit)\n"); - break; - default: - printf ("Unknown Chip Type\n"); - goto Done; - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i = 0; i < info->sector_count; i++) { - if ((i % 5) == 0) { - printf ("\n "); - } - printf (" %08lX%s", info->start[i], - info->protect[i] ? " (RO)" : " "); - } - printf ("\n"); - - Done: - return; -} - - -unsigned long flash_init (void) -{ - int i, j; - ulong size = 0; - - for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) { - ulong flashbase = 0; - - flash_info[i].flash_id = - (AMD_MANUFACT & FLASH_VENDMASK) | - (AMD_ID_PL160CB & FLASH_TYPEMASK); - flash_info[i].size = FLASH_BANK_SIZE; - flash_info[i].sector_count = CFG_MAX_FLASH_SECT; - memset (flash_info[i].protect, 0, CFG_MAX_FLASH_SECT); - if (i == 0) - flashbase = PHYS_FLASH_1; - else - panic ("configured to many flash banks!\n"); - - for (j = 0; j < flash_info[i].sector_count; j++) { - if (j == 0) { - /* 1st is 16 KiB */ - flash_info[i].start[j] = flashbase; - } - if ((j >= 1) && (j <= 2)) { - /* 2nd and 3rd are 8 KiB */ - flash_info[i].start[j] = - flashbase + 0x4000 + 0x2000 * (j - 1); - } - if (j == 3) { - /* 4th is 32 KiB */ - flash_info[i].start[j] = flashbase + 0x8000; - } - if ((j >= 4) && (j <= 34)) { - /* rest is 256 KiB */ - flash_info[i].start[j] = - flashbase + 0x10000 + 0x10000 * (j - - 4); - } - } - size += flash_info[i].size; - } - - flash_protect (FLAG_PROTECT_SET, - CFG_FLASH_BASE, - CFG_FLASH_BASE + 0xffff, &flash_info[0]); - - return size; -} - - -#define CMD_READ_ARRAY 0x00F0 -#define CMD_UNLOCK1 0x00AA -#define CMD_UNLOCK2 0x0055 -#define CMD_ERASE_SETUP 0x0080 -#define CMD_ERASE_CONFIRM 0x0030 -#define CMD_PROGRAM 0x00A0 -#define CMD_UNLOCK_BYPASS 0x0020 - -#define MEM_FLASH_ADDR1 (*(volatile u16 *)(CFG_FLASH_BASE + (0x00000555<<1))) -#define MEM_FLASH_ADDR2 (*(volatile u16 *)(CFG_FLASH_BASE + (0x000002AA<<1))) - -#define BIT_ERASE_DONE 0x0080 -#define BIT_RDY_MASK 0x0080 -#define BIT_PROGRAM_ERROR 0x0020 -#define BIT_TIMEOUT 0x80000000 /* our flag */ - -#define READY 1 -#define ERR 2 -#define TMO 4 - - -int flash_erase (flash_info_t * info, int s_first, int s_last) -{ - ulong result; - int iflag, cflag, prot, sect; - int rc = ERR_OK; - int chip1; - - /* first look for protection bits */ - - if (info->flash_id == FLASH_UNKNOWN) - return ERR_UNKNOWN_FLASH_TYPE; - - if ((s_first < 0) || (s_first > s_last)) { - return ERR_INVAL; - } - - if ((info->flash_id & FLASH_VENDMASK) != - (AMD_MANUFACT & FLASH_VENDMASK)) { - return ERR_UNKNOWN_FLASH_VENDOR; - } - - prot = 0; - for (sect = s_first; sect <= s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - if (prot) - return ERR_PROTECTED; - - /* - * Disable interrupts which might cause a timeout - * here. Remember that our exception vectors are - * at address 0 in the flash, and we don't want a - * (ticker) exception to happen while the flash - * chip is in programming mode. - */ - - cflag = icache_status (); - icache_disable (); - iflag = disable_interrupts (); - - printf ("\n"); - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect <= s_last && !ctrlc (); sect++) { - printf ("Erasing sector %2d ... ", sect); - - /* arm simple, non interrupt dependent timer */ - set_timer (0); - - if (info->protect[sect] == 0) { /* not protected */ - volatile u16 *addr = - (volatile u16 *) (info->start[sect]); - - MEM_FLASH_ADDR1 = CMD_UNLOCK1; - MEM_FLASH_ADDR2 = CMD_UNLOCK2; - MEM_FLASH_ADDR1 = CMD_ERASE_SETUP; - - MEM_FLASH_ADDR1 = CMD_UNLOCK1; - MEM_FLASH_ADDR2 = CMD_UNLOCK2; - *addr = CMD_ERASE_CONFIRM; - - /* wait until flash is ready */ - chip1 = 0; - - do { - result = *addr; - - /* check timeout */ - if (get_timer (0) > CFG_FLASH_ERASE_TOUT) { - MEM_FLASH_ADDR1 = CMD_READ_ARRAY; - chip1 = TMO; - break; - } - - if (!chip1 - && (result & 0xFFFF) & BIT_ERASE_DONE) - chip1 = READY; - - } while (!chip1); - - MEM_FLASH_ADDR1 = CMD_READ_ARRAY; - - if (chip1 == ERR) { - rc = ERR_PROG_ERROR; - goto outahere; - } - if (chip1 == TMO) { - rc = ERR_TIMOUT; - goto outahere; - } - - printf ("ok.\n"); - } else { /* it was protected */ - - printf ("protected!\n"); - } - } - - if (ctrlc ()) - printf ("User Interrupt!\n"); - - outahere: - /* allow flash to settle - wait 10 ms */ - udelay (10000); - - if (iflag) - enable_interrupts (); - - if (cflag) - icache_enable (); - - return rc; -} - -static int write_word (flash_info_t * info, ulong dest, ulong data) -{ - volatile u16 *addr = (volatile u16 *) dest; - ulong result; - int rc = ERR_OK; - int cflag, iflag; - int chip1; - - /* - * Check if Flash is (sufficiently) erased - */ - result = *addr; - if ((result & data) != data) - return ERR_NOT_ERASED; - - - /* - * Disable interrupts which might cause a timeout - * here. Remember that our exception vectors are - * at address 0 in the flash, and we don't want a - * (ticker) exception to happen while the flash - * chip is in programming mode. - */ - - cflag = icache_status (); - icache_disable (); - iflag = disable_interrupts (); - - MEM_FLASH_ADDR1 = CMD_UNLOCK1; - MEM_FLASH_ADDR2 = CMD_UNLOCK2; - MEM_FLASH_ADDR1 = CMD_PROGRAM; - *addr = data; - - /* arm simple, non interrupt dependent timer */ - set_timer (0); - - /* wait until flash is ready */ - chip1 = 0; - do { - result = *addr; - - /* check timeout */ - if (get_timer (0) > CFG_FLASH_ERASE_TOUT) { - chip1 = ERR | TMO; - break; - } - if (!chip1 && ((result & 0x80) == (data & 0x80))) - chip1 = READY; - - } while (!chip1); - - *addr = CMD_READ_ARRAY; - - if (chip1 == ERR || *addr != data) - rc = ERR_PROG_ERROR; - - if (iflag) - enable_interrupts (); - - if (cflag) - icache_enable (); - - return rc; -} - - -int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) -{ - ulong wp, data; - int rc; - - if (addr & 1) { - printf ("unaligned destination not supported\n"); - return ERR_ALIGN; - } - -#if 0 - if (cnt & 1) { - printf ("odd transfer sizes not supported\n"); - return ERR_ALIGN; - } -#endif - - wp = addr; - - if (addr & 1) { - data = (*((volatile u8 *) addr) << 8) | *((volatile u8 *) - src); - if ((rc = write_word (info, wp - 1, data)) != 0) { - return (rc); - } - src += 1; - wp += 1; - cnt -= 1; - } - - while (cnt >= 2) { - data = *((volatile u16 *) src); - if ((rc = write_word (info, wp, data)) != 0) { - return (rc); - } - src += 2; - wp += 2; - cnt -= 2; - } - - if (cnt == 1) { - data = (*((volatile u8 *) src) << 8) | - *((volatile u8 *) (wp + 1)); - if ((rc = write_word (info, wp, data)) != 0) { - return (rc); - } - src += 1; - wp += 1; - cnt -= 1; - } - - return ERR_OK; -} diff --git a/board/m5282evb/m5282evb.c b/board/m5282evb/m5282evb.c index a08af68ae..243d6a4d8 100644 --- a/board/m5282evb/m5282evb.c +++ b/board/m5282evb/m5282evb.c @@ -22,14 +22,71 @@ */ #include +#include + +DECLARE_GLOBAL_DATA_PTR; int checkboard (void) { - puts ("MOTOROLA M5272EVB Evaluation Board\n"); + puts ("Board: Freescale M5282EVB Evaluation Board\n"); return 0; } long int initdram (int board_type) { - return 0x1000000; + u32 dramsize, i, dramclk; + + dramsize = CFG_SDRAM_SIZE * 0x100000; + for (i = 0x13; i < 0x20; i++) { + if (dramsize == (1 << i)) + break; + } + i--; + + if (!(MCFSDRAMC_DACR0 & MCFSDRAMC_DACR_RE)) + { + dramclk = gd->bus_clk / (CFG_HZ * CFG_HZ); + + /* Initialize DRAM Control Register: DCR */ + MCFSDRAMC_DCR = (0 + | MCFSDRAMC_DCR_RTIM_6 + | MCFSDRAMC_DCR_RC((15 * dramclk)>>4)); + + /* Initialize DACR0 */ + MCFSDRAMC_DACR0 = (0 + | MCFSDRAMC_DACR_BASE(CFG_SDRAM_BASE) + | MCFSDRAMC_DACR_CASL(1) + | MCFSDRAMC_DACR_CBM(3) + | MCFSDRAMC_DACR_PS_32); + + /* Initialize DMR0 */ + MCFSDRAMC_DMR0 = (0 + | ((dramsize - 1) & 0xFFFC0000) + | MCFSDRAMC_DMR_V); + + /* Set IP (bit 3) in DACR */ + MCFSDRAMC_DACR0 |= MCFSDRAMC_DACR_IP; + + /* Wait 30ns to allow banks to precharge */ + for (i = 0; i < 5; i++) { + asm ("nop"); + } + + /* Write to this block to initiate precharge */ + *(u32 *)(CFG_SDRAM_BASE) = 0xA5A59696; + + /* Set RE (bit 15) in DACR */ + MCFSDRAMC_DACR0 |= MCFSDRAMC_DACR_RE; + + /* Wait for at least 8 auto refresh cycles to occur */ + for (i = 0; i < 2000; i++) { + asm(" nop"); + } + + /* Finish the configuration by issuing the IMRS. */ + MCFSDRAMC_DACR0 |= MCFSDRAMC_DACR_IMRS; + + /* Write to the SDRAM Mode Register */ + *(u32 *)(CFG_SDRAM_BASE + 0x400) = 0xA5A59696; + } } diff --git a/board/m5282evb/mii.c b/board/m5282evb/mii.c new file mode 100644 index 000000000..ebd3ed938 --- /dev/null +++ b/board/m5282evb/mii.c @@ -0,0 +1,304 @@ +/* + * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI) +#undef MII_DEBUG +#undef ET_DEBUG + +int fecpin_setclear(struct eth_device *dev, int setclear) +{ + if (setclear) { + MCFGPIO_PASPAR |= 0x0F00; + MCFGPIO_PEHLPAR = CFG_PEHLPAR; + } else { + MCFGPIO_PASPAR &= 0xF0FF; + MCFGPIO_PEHLPAR &= ~CFG_PEHLPAR; + } + return 0; +} + +#if defined(CFG_DISCOVER_PHY) || defined(CONFIG_CMD_MII) +#include + +/* Make MII read/write commands for the FEC. */ +#define mk_mii_read(ADDR, REG) (0x60020000 | ((ADDR << 23) | (REG & 0x1f) << 18)) + +#define mk_mii_write(ADDR, REG, VAL) (0x50020000 | ((ADDR << 23) | (REG & 0x1f) << 18) | (VAL & 0xffff)) + +/* PHY identification */ +#define PHY_ID_LXT970 0x78100000 /* LXT970 */ +#define PHY_ID_LXT971 0x001378e0 /* LXT971 and 972 */ +#define PHY_ID_82555 0x02a80150 /* Intel 82555 */ +#define PHY_ID_QS6612 0x01814400 /* QS6612 */ +#define PHY_ID_AMD79C784 0x00225610 /* AMD 79C784 */ +#define PHY_ID_AMD79C874VC 0x0022561B /* AMD 79C874 */ +#define PHY_ID_LSI80225 0x0016f870 /* LSI 80225 */ +#define PHY_ID_LSI80225B 0x0016f880 /* LSI 80225/B */ +#define PHY_ID_DP83848VV 0x20005C90 /* National 83848 */ +#define PHY_ID_DP83849 0x20005CA2 /* National 82849 */ + +#define STR_ID_LXT970 "LXT970" +#define STR_ID_LXT971 "LXT971" +#define STR_ID_82555 "Intel82555" +#define STR_ID_QS6612 "QS6612" +#define STR_ID_AMD79C784 "AMD79C784" +#define STR_ID_AMD79C874VC "AMD79C874VC" +#define STR_ID_LSI80225 "LSI80225" +#define STR_ID_LSI80225B "LSI80225/B" +#define STR_ID_DP83848VV "N83848" +#define STR_ID_DP83849 "N83849" + +/**************************************************************************** + * mii_init -- Initialize the MII for MII command without ethernet + * This function is a subset of eth_init + **************************************************************************** + */ +void mii_reset(struct fec_info_s *info) +{ + volatile fec_t *fecp = (fec_t *) (info->miibase); + int i; + + fecp->ecr = FEC_ECR_RESET; + for (i = 0; (fecp->ecr & FEC_ECR_RESET) && (i < FEC_RESET_DELAY); ++i) { + udelay(1); + } + if (i == FEC_RESET_DELAY) { + printf("FEC_RESET_DELAY timeout\n"); + } +} + +/* send command to phy using mii, wait for result */ +uint mii_send(uint mii_cmd) +{ + struct fec_info_s *info; + struct eth_device *dev; + volatile fec_t *ep; + uint mii_reply; + int j = 0; + + /* retrieve from register structure */ + dev = eth_get_dev(); + info = dev->priv; + + ep = (fec_t *) info->miibase; + + ep->mmfr = mii_cmd; /* command to phy */ + + /* wait for mii complete */ + while (!(ep->eir & FEC_EIR_MII) && (j < MCFFEC_TOUT_LOOP)) { + udelay(1); + j++; + } + if (j >= MCFFEC_TOUT_LOOP) { + printf("MII not complete\n"); + return -1; + } + + mii_reply = ep->mmfr; /* result from phy */ + ep->eir = FEC_EIR_MII; /* clear MII complete */ +#ifdef ET_DEBUG + printf("%s[%d] %s: sent=0x%8.8x, reply=0x%8.8x\n", + __FILE__, __LINE__, __FUNCTION__, mii_cmd, mii_reply); +#endif + + return (mii_reply & 0xffff); /* data read from phy */ +} +#endif /* CFG_DISCOVER_PHY || (CONFIG_COMMANDS & CONFIG_CMD_MII) */ + +#if defined(CFG_DISCOVER_PHY) +int mii_discover_phy(struct eth_device *dev) +{ +#define MAX_PHY_PASSES 11 + struct fec_info_s *info = dev->priv; + int phyaddr, pass; + uint phyno, phytype; + + if (info->phyname_init) + return info->phy_addr; + + phyaddr = -1; /* didn't find a PHY yet */ + for (pass = 1; pass <= MAX_PHY_PASSES && phyaddr < 0; ++pass) { + if (pass > 1) { + /* PHY may need more time to recover from reset. + * The LXT970 needs 50ms typical, no maximum is + * specified, so wait 10ms before try again. + * With 11 passes this gives it 100ms to wake up. + */ + udelay(10000); /* wait 10ms */ + } + + for (phyno = 0; phyno < 32 && phyaddr < 0; ++phyno) { + + phytype = mii_send(mk_mii_read(phyno, PHY_PHYIDR1)); +#ifdef ET_DEBUG + printf("PHY type 0x%x pass %d type\n", phytype, pass); +#endif + if (phytype != 0xffff) { + phyaddr = phyno; + phytype <<= 16; + phytype |= + mii_send(mk_mii_read(phyno, PHY_PHYIDR2)); + + switch (phytype & 0xffffffff) { + case PHY_ID_AMD79C874VC: + strcpy(info->phy_name, + STR_ID_AMD79C874VC); + info->phyname_init = 1; + break; + default: + strcpy(info->phy_name, "unknown"); + info->phyname_init = 1; + break; + } + +#ifdef ET_DEBUG + printf("PHY @ 0x%x pass %d type ", phyno, pass); + switch (phytype & 0xffffffff) { + case PHY_ID_AMD79C874VC: + printf(STR_ID_AMD79C874VC); + break; + default: + printf("0x%08x\n", phytype); + break; + } +#endif + } + } + } + if (phyaddr < 0) + printf("No PHY device found.\n"); + + return phyaddr; +} +#endif /* CFG_DISCOVER_PHY */ + +int mii_init(void) __attribute__((weak,alias("__mii_init"))); + +void __mii_init(void) +{ + volatile fec_t *fecp; + struct fec_info_s *info; + struct eth_device *dev; + int miispd = 0, i = 0; + u16 autoneg = 0; + + /* retrieve from register structure */ + dev = eth_get_dev(); + info = dev->priv; + + fecp = (fec_t *) info->miibase; + + fecpin_setclear(dev, 1); + + mii_reset(info); + + /* We use strictly polling mode only */ + fecp->eimr = 0; + + /* Clear any pending interrupt */ + fecp->eir = 0xffffffff; + + /* Set MII speed */ + miispd = (gd->bus_clk / 1000000) / 5; + fecp->mscr = miispd << 1; + + info->phy_addr = mii_discover_phy(dev); + +#define AUTONEGLINK (PHY_BMSR_AUTN_COMP | PHY_BMSR_LS) + while (i < MCFFEC_TOUT_LOOP) { + autoneg = 0; + miiphy_read(dev->name, info->phy_addr, PHY_BMSR, &autoneg); + i++; + + if ((autoneg & AUTONEGLINK) == AUTONEGLINK) + break; + + udelay(500); + } + if (i >= MCFFEC_TOUT_LOOP) { + printf("Auto Negotiation not complete\n"); + } + + /* adapt to the half/full speed settings */ + info->dup_spd = miiphy_duplex(dev->name, info->phy_addr) << 16; + info->dup_spd |= miiphy_speed(dev->name, info->phy_addr); +} + +/***************************************************************************** + * Read and write a MII PHY register, routines used by MII Utilities + * + * FIXME: These routines are expected to return 0 on success, but mii_send + * does _not_ return an error code. Maybe 0xFFFF means error, i.e. + * no PHY connected... + * For now always return 0. + * FIXME: These routines only work after calling eth_init() at least once! + * Otherwise they hang in mii_send() !!! Sorry! + *****************************************************************************/ + +int mcffec_miiphy_read(char *devname, unsigned char addr, unsigned char reg, + unsigned short *value) +{ + short rdreg; /* register working value */ + +#ifdef MII_DEBUG + printf("miiphy_read(0x%x) @ 0x%x = ", reg, addr); +#endif + rdreg = mii_send(mk_mii_read(addr, reg)); + + *value = rdreg; + +#ifdef MII_DEBUG + printf("0x%04x\n", *value); +#endif + + return 0; +} + +int mcffec_miiphy_write(char *devname, unsigned char addr, unsigned char reg, + unsigned short value) +{ + short rdreg; /* register working value */ + +#ifdef MII_DEBUG + printf("miiphy_write(0x%x) @ 0x%x = ", reg, addr); +#endif + + rdreg = mii_send(mk_mii_write(addr, reg, value)); + +#ifdef MII_DEBUG + printf("0x%04x\n", value); +#endif + + return 0; +} + +#endif /* CONFIG_CMD_NET, FEC_ENET & NET_MULTI */ diff --git a/include/configs/M5271EVB.h b/include/configs/M5271EVB.h index 885a8821b..0f97050f2 100644 --- a/include/configs/M5271EVB.h +++ b/include/configs/M5271EVB.h @@ -31,7 +31,6 @@ #ifndef _M5271EVB_H #define _M5271EVB_H -#define DEBUG #undef DEBUG /* @@ -41,17 +40,15 @@ #define CONFIG_M5271 /* define processor type */ #define CONFIG_M5271EVB /* define board type */ -#define CONFIG_IPADDR 192.168.30.1 -#define CONFIG_SERVERIP 192.168.1.1 -#define CONFIG_ETHADDR 00:06:3b:01:41:55 +#define CONFIG_MCFTMR +#define CONFIG_MCFUART +#define CFG_UART_PORT (0) #define CONFIG_BAUDRATE 19200 #define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 } #undef CONFIG_WATCHDOG /* disable watchdog */ -#define CONFIG_BOOTDELAY 5 - /* Configuration for environment * Environment is embedded in u-boot in the second sector of the flash */ @@ -73,7 +70,6 @@ #define CONFIG_BOOTP_GATEWAY #define CONFIG_BOOTP_HOSTNAME - /* * Command line configuration. */ @@ -81,22 +77,83 @@ #define CONFIG_CMD_PING #define CONFIG_CMD_NET +#define CONFIG_CMD_MII +#define CONFIG_CMD_ELF +#define CONFIG_CMD_FLASH +#define CONFIG_CMD_I2C +#define CONFIG_CMD_MEMORY +#define CONFIG_CMD_MISC #undef CONFIG_CMD_LOADS #undef CONFIG_CMD_LOADB +#define CONFIG_MCFFEC +#ifdef CONFIG_MCFFEC +# define CONFIG_NET_MULTI 1 +# define CONFIG_MII 1 +# define CFG_DISCOVER_PHY +# define CFG_RX_ETH_BUFFER 8 +# define CFG_FAULT_ECHO_LINK_DOWN + +# define CFG_FEC0_PINMUX 0 +# define CFG_FEC0_MIIBASE CFG_FEC0_IOBASE +# define MCFFEC_TOUT_LOOP 50000 +/* If CFG_DISCOVER_PHY is not defined - hardcoded */ +# ifndef CFG_DISCOVER_PHY +# define FECDUPLEX FULL +# define FECSPEED _100BASET +# else +# ifndef CFG_FAULT_ECHO_LINK_DOWN +# define CFG_FAULT_ECHO_LINK_DOWN +# endif +# endif /* CFG_DISCOVER_PHY */ +#endif + +/* I2C */ +#define CONFIG_FSL_I2C +#define CONFIG_HARD_I2C /* I2C with hw support */ +#undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CFG_I2C_SPEED 80000 +#define CFG_I2C_SLAVE 0x7F +#define CFG_I2C_OFFSET 0x00000300 +#define CFG_IMMR CFG_MBAR + +#define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */ +#define CONFIG_BOOTFILE "u-boot.bin" +#ifdef CONFIG_MCFFEC +# define CONFIG_NET_RETRY_COUNT 5 +# define CONFIG_ETHADDR 00:e0:0c:bc:e5:60 +# define CONFIG_IPADDR 192.162.1.2 +# define CONFIG_NETMASK 255.255.255.0 +# define CONFIG_SERVERIP 192.162.1.1 +# define CONFIG_GATEWAYIP 192.162.1.1 +# define CONFIG_OVERWRITE_ETHADDR_ONCE +#endif /* FEC_ENET */ + +#define CONFIG_HOSTNAME M5235EVB +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "loadaddr=10000\0" \ + "u-boot=u-boot.bin\0" \ + "load=tftp ${loadaddr) ${u-boot}\0" \ + "upd=run load; run prog\0" \ + "prog=prot off ffe00000 ffe2ffff;" \ + "era ffe00000 ffe2ffff;" \ + "cp.b ${loadaddr} 0 ${filesize};" \ + "save\0" \ + "" #define CFG_PROMPT "=> " -#define CFG_LONGHELP /* undef to save memory */ +#define CFG_LONGHELP /* undef to save memory */ #if defined(CONFIG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ #endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ #define CFG_LOAD_ADDR 0x00100000 @@ -114,16 +171,11 @@ #define CFG_MBAR 0x40000000 /* Register Base Addrs */ -/* Enable FEC ethernet */ -#define FEC_ENET -#define CONFIG_NET_RETRY_COUNT 5 -#define CFG_ENET_BD_BASE 0x480000 - /* * Definitions for initial stack pointer and data area (in DPRAM) */ #define CFG_INIT_RAM_ADDR 0x20000000 -#define CFG_INIT_RAM_END 0x1000 /* End of used area in internal SRAM */ +#define CFG_INIT_RAM_END 0x1000 /* End of used area in internal SRAM */ #define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET @@ -134,7 +186,7 @@ * Please note that CFG_SDRAM_BASE _must_ start at 0 */ #define CFG_SDRAM_BASE 0x00000000 -#define CFG_SDRAM_SIZE 16 /* SDRAM size in MB */ +#define CFG_SDRAM_SIZE 16 /* SDRAM size in MB */ #define CFG_FLASH_BASE 0xffe00000 #ifdef CONFIG_MONITOR_IS_IN_RAM @@ -152,11 +204,11 @@ * have to be in the first 8 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization ?? */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ +#define CFG_BOOTMAPSZ (CFG_SDRAM_BASE + (CFG_SDRAM_SIZE << 20)) /* FLASH organization */ -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 11 /* max number of sectors on one chip */ +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 11 /* max number of sectors on one chip */ #define CFG_FLASH_ERASE_TOUT 1000 #define CFG_FLASH_CFI 1 @@ -169,4 +221,4 @@ /* Port configuration */ #define CFG_FECI2C 0xF0 -#endif /* _M5271EVB_H */ +#endif /* _M5271EVB_H */ diff --git a/include/configs/M5272C3.h b/include/configs/M5272C3.h index cc456dc08..2b8734b4c 100644 --- a/include/configs/M5272C3.h +++ b/include/configs/M5272C3.h @@ -33,18 +33,20 @@ * High Level Configuration Options * (easy to change) */ -#define CONFIG_MCF52x2 /* define processor family */ -#define CONFIG_M5272 /* define processor type */ +#define CONFIG_MCF52x2 /* define processor family */ +#define CONFIG_M5272 /* define processor type */ -#define FEC_ENET +#define CONFIG_MCFTMR +#define CONFIG_MCFUART +#define CFG_UART_PORT (0) #define CONFIG_BAUDRATE 19200 #define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 } -#define CONFIG_WATCHDOG +#undef CONFIG_WATCHDOG #define CONFIG_WATCHDOG_TIMEOUT 10000 /* timeout in milliseconds */ -#define CONFIG_MONITOR_IS_IN_RAM /* define if monitor is started from a pre-loader */ +#undef CONFIG_MONITOR_IS_IN_RAM /* define if monitor is started from a pre-loader */ /* Configuration for environment * Environment is embedded in u-boot in the second sector of the flash @@ -60,7 +62,6 @@ #define CFG_ENV_IS_IN_FLASH 1 #endif - /* * BOOTP options */ @@ -69,37 +70,82 @@ #define CONFIG_BOOTP_GATEWAY #define CONFIG_BOOTP_HOSTNAME - /* * Command line configuration. */ #include #define CONFIG_CMD_MII +#define CONFIG_CMD_NET +#define CONFIG_CMD_PING +#define CONFIG_CMD_MISC +#define CONFIG_CMD_ELF +#define CONFIG_CMD_FLASH +#define CONFIG_CMD_MEMORY #undef CONFIG_CMD_LOADS #undef CONFIG_CMD_LOADB - #define CONFIG_BOOTDELAY 5 +#define CONFIG_MCFFEC +#ifdef CONFIG_MCFFEC +# define CONFIG_NET_MULTI 1 +# define CONFIG_MII 1 +# define CFG_DISCOVER_PHY +# define CFG_RX_ETH_BUFFER 8 +# define CFG_FAULT_ECHO_LINK_DOWN + +# define CFG_FEC0_PINMUX 0 +# define CFG_FEC0_MIIBASE CFG_FEC0_IOBASE +# define MCFFEC_TOUT_LOOP 50000 +/* If CFG_DISCOVER_PHY is not defined - hardcoded */ +# ifndef CFG_DISCOVER_PHY +# define FECDUPLEX FULL +# define FECSPEED _100BASET +# else +# ifndef CFG_FAULT_ECHO_LINK_DOWN +# define CFG_FAULT_ECHO_LINK_DOWN +# endif +# endif /* CFG_DISCOVER_PHY */ +#endif + +#ifdef CONFIG_MCFFEC +# define CONFIG_ETHADDR 00:e0:0c:bc:e5:60 +# define CONFIG_IPADDR 192.162.1.2 +# define CONFIG_NETMASK 255.255.255.0 +# define CONFIG_SERVERIP 192.162.1.1 +# define CONFIG_GATEWAYIP 192.162.1.1 +# define CONFIG_OVERWRITE_ETHADDR_ONCE +#endif /* CONFIG_MCFFEC */ + +#define CONFIG_HOSTNAME M5272C3 +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "loadaddr=10000\0" \ + "u-boot=u-boot.bin\0" \ + "load=tftp ${loadaddr) ${u-boot}\0" \ + "upd=run load; run prog\0" \ + "prog=prot off ffe00000 ffe3ffff;" \ + "era ffe00000 ffe3ffff;" \ + "cp.b ${loadaddr} ffe00000 ${filesize};"\ + "save\0" \ + "" #define CFG_PROMPT "-> " -#define CFG_LONGHELP /* undef to save memory */ +#define CFG_LONGHELP /* undef to save memory */ #if defined(CONFIG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ #endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ #define CFG_LOAD_ADDR 0x20000 - #define CFG_MEMTEST_START 0x400 #define CFG_MEMTEST_END 0x380000 - #define CFG_HZ 1000 #define CFG_CLK 66000000 @@ -108,20 +154,15 @@ * (address mappings, register initial values, etc.) * You should know what you are doing if you make changes here. */ - #define CFG_MBAR 0x10000000 /* Register Base Addrs */ - #define CFG_SCR 0x0003; #define CFG_SPR 0xffff; -#define CFG_DISCOVER_PHY -#define CFG_ENET_BD_BASE 0x380000 - /*----------------------------------------------------------------------- * Definitions for initial stack pointer and data area (in DPRAM) */ #define CFG_INIT_RAM_ADDR 0x20000000 -#define CFG_INIT_RAM_END 0x1000 /* End of used area in internal SRAM */ +#define CFG_INIT_RAM_END 0x1000 /* End of used area in internal SRAM */ #define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET @@ -132,7 +173,7 @@ * Please note that CFG_SDRAM_BASE _must_ start at 0 */ #define CFG_SDRAM_BASE 0x00000000 -#define CFG_SDRAM_SIZE 4 /* SDRAM size in MB */ +#define CFG_SDRAM_SIZE 4 /* SDRAM size in MB */ #define CFG_FLASH_BASE 0xffe00000 #ifdef CONFIG_MONITOR_IS_IN_RAM @@ -150,13 +191,13 @@ * have to be in the first 8 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization ?? */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ +#define CFG_BOOTMAPSZ (CFG_SDRAM_BASE + (CFG_SDRAM_SIZE << 20)) /*----------------------------------------------------------------------- * FLASH organization */ -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 11 /* max number of sectors on one chip */ +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 11 /* max number of sectors on one chip */ #define CFG_FLASH_ERASE_TOUT 1000 /*----------------------------------------------------------------------- @@ -169,25 +210,18 @@ */ #define CFG_BR0_PRELIM 0xFFE00201 #define CFG_OR0_PRELIM 0xFFE00014 - #define CFG_BR1_PRELIM 0 #define CFG_OR1_PRELIM 0 - #define CFG_BR2_PRELIM 0x30000001 #define CFG_OR2_PRELIM 0xFFF80000 - #define CFG_BR3_PRELIM 0 #define CFG_OR3_PRELIM 0 - #define CFG_BR4_PRELIM 0 #define CFG_OR4_PRELIM 0 - #define CFG_BR5_PRELIM 0 #define CFG_OR5_PRELIM 0 - #define CFG_BR6_PRELIM 0 #define CFG_OR6_PRELIM 0 - #define CFG_BR7_PRELIM 0x00000701 #define CFG_OR7_PRELIM 0xFFC0007C @@ -197,9 +231,8 @@ #define CFG_PACNT 0x00000000 #define CFG_PADDR 0x0000 #define CFG_PADAT 0x0000 -#define CFG_PBCNT 0x55554155 /* Ethernet/UART configuration */ +#define CFG_PBCNT 0x55554155 /* Ethernet/UART configuration */ #define CFG_PBDDR 0x0000 #define CFG_PBDAT 0x0000 #define CFG_PDCNT 0x00000000 - -#endif /* _M5272C3_H */ +#endif /* _M5272C3_H */ diff --git a/include/configs/M5282EVB.h b/include/configs/M5282EVB.h index f2a764493..3c17c1ea1 100644 --- a/include/configs/M5282EVB.h +++ b/include/configs/M5282EVB.h @@ -33,15 +33,17 @@ * High Level Configuration Options * (easy to change) */ -#define CONFIG_MCF52x2 /* define processor family */ -#define CONFIG_M5282 /* define processor type */ +#define CONFIG_MCF52x2 /* define processor family */ +#define CONFIG_M5282 /* define processor type */ -#define FEC_ENET +#define CONFIG_MCFTMR +#define CONFIG_MCFUART +#define CFG_UART_PORT (0) #define CONFIG_BAUDRATE 19200 #define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 } -#define CONFIG_MONITOR_IS_IN_RAM /* define if monitor is started from a pre-loader */ +#undef CONFIG_MONITOR_IS_IN_RAM /* define if monitor is started from a pre-loader */ /* Configuration for environment * Environment is embedded in u-boot in the second sector of the flash @@ -50,7 +52,6 @@ #define CFG_ENV_SIZE 0x2000 #define CFG_ENV_IS_IN_FLASH 1 - /* * BOOTP options */ @@ -59,29 +60,73 @@ #define CONFIG_BOOTP_GATEWAY #define CONFIG_BOOTP_HOSTNAME - /* * Command line configuration. */ #include +#define CONFIG_CMD_NET +#define CONFIG_CMD_PING +#define CONFIG_CMD_MII #undef CONFIG_CMD_LOADS #undef CONFIG_CMD_LOADB +#define CONFIG_MCFFEC +#ifdef CONFIG_MCFFEC +# define CONFIG_NET_MULTI 1 +# define CONFIG_MII 1 +# define CFG_DISCOVER_PHY +# define CFG_RX_ETH_BUFFER 8 +# define CFG_FAULT_ECHO_LINK_DOWN + +# define CFG_FEC0_PINMUX 0 +# define CFG_FEC0_MIIBASE CFG_FEC0_IOBASE +# define MCFFEC_TOUT_LOOP 50000 +/* If CFG_DISCOVER_PHY is not defined - hardcoded */ +# ifndef CFG_DISCOVER_PHY +# define FECDUPLEX FULL +# define FECSPEED _100BASET +# else +# ifndef CFG_FAULT_ECHO_LINK_DOWN +# define CFG_FAULT_ECHO_LINK_DOWN +# endif +# endif /* CFG_DISCOVER_PHY */ +#endif #define CONFIG_BOOTDELAY 5 +#ifdef CONFIG_MCFFEC +# define CONFIG_ETHADDR 00:e0:0c:bc:e5:60 +# define CONFIG_IPADDR 192.162.1.2 +# define CONFIG_NETMASK 255.255.255.0 +# define CONFIG_SERVERIP 192.162.1.1 +# define CONFIG_GATEWAYIP 192.162.1.1 +# define CONFIG_OVERWRITE_ETHADDR_ONCE +#endif /* CONFIG_MCFFEC */ + +#define CONFIG_HOSTNAME M5272C3 +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "loadaddr=10000\0" \ + "u-boot=u-boot.bin\0" \ + "load=tftp ${loadaddr) ${u-boot}\0" \ + "upd=run load; run prog\0" \ + "prog=prot off ffe00000 ffe3ffff;" \ + "era ffe00000 ffe3ffff;" \ + "cp.b ${loadaddr} ffe00000 ${filesize};"\ + "save\0" \ + "" #define CFG_PROMPT "-> " -#define CFG_LONGHELP /* undef to save memory */ +#define CFG_LONGHELP /* undef to save memory */ #if defined(CONFIG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ #endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ #define CFG_LOAD_ADDR 0x20000 @@ -91,6 +136,10 @@ #define CFG_HZ 1000000 #define CFG_CLK 64000000 +/* PLL Configuration: Ext Clock * 6 (see table 9-4 of MCF user manual) */ + +#define CFG_MFD 0x02 /* PLL Multiplication Factor Devider */ +#define CFG_RFD 0x00 /* PLL Reduce Frecuency Devider */ /* * Low Level Configuration Settings @@ -99,15 +148,12 @@ */ #define CFG_MBAR 0x40000000 -#undef CFG_DISCOVER_PHY -#define CFG_ENET_BD_BASE 0x380000 - /*----------------------------------------------------------------------- * Definitions for initial stack pointer and data area (in DPRAM) */ -#define CFG_INIT_RAM_ADDR 0x20000000 -#define CFG_INIT_RAM_END 0x10000 /* End of used area in internal SRAM */ -#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ +#define CFG_INIT_RAM_ADDR 0x20000000 +#define CFG_INIT_RAM_END 0x10000 /* End of used area in internal SRAM */ +#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET @@ -117,49 +163,88 @@ * Please note that CFG_SDRAM_BASE _must_ start at 0 */ #define CFG_SDRAM_BASE 0x00000000 -#define CFG_SDRAM_SIZE 4 /* SDRAM size in MB */ +#define CFG_SDRAM_SIZE 8 /* SDRAM size in MB */ #define CFG_FLASH_BASE 0xffe00000 #define CFG_INT_FLASH_BASE 0xf0000000 +#define CFG_INT_FLASH_ENABLE 0x21 /* If M5282 port is fully implemented the monitor base will be behind * the vector table. */ -/* #define CFG_MONITOR_BASE (CFG_FLASH_BASE + 0x400) */ -#define CFG_MONITOR_BASE 0x20000 +#if (TEXT_BASE != CFG_INT_FLASH_BASE) +#define CFG_MONITOR_BASE (CFG_FLASH_BASE + 0x400) +#else +#define CFG_MONITOR_BASE (TEXT_BASE + 0x418) /* 24 Byte for CFM-Config */ +#endif #define CFG_MONITOR_LEN 0x20000 #define CFG_MALLOC_LEN (256 << 10) #define CFG_BOOTPARAMS_LEN 64*1024 - /* * For booting Linux, the board info and command line data * have to be in the first 8 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization ?? */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - +#define CFG_BOOTMAPSZ (CFG_SDRAM_BASE + (CFG_SDRAM_SIZE << 20)) /*----------------------------------------------------------------------- * FLASH organization */ -#define CFG_MAX_FLASH_SECT 35 -#define CFG_MAX_FLASH_BANKS 1 -#define CFG_FLASH_ERASE_TOUT 10000000 +#define CFG_FLASH_CFI +#ifdef CFG_FLASH_CFI + +# define CFG_FLASH_CFI_DRIVER 1 +# define CFG_FLASH_SIZE 0x1000000 /* Max size that the board might have */ +# define CFG_FLASH_CFI_WIDTH FLASH_CFI_16BIT +# define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +# define CFG_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ +# define CFG_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ +# define CFG_FLASH_CHECKSUM +# define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE } +#endif /*----------------------------------------------------------------------- * Cache Configuration */ #define CFG_CACHELINE_SIZE 16 - /*----------------------------------------------------------------------- * Memory bank definitions */ - - +#define CFG_CS0_BASE CFG_FLASH_BASE +#define CFG_CS0_SIZE 2*1024*1024 +#define CFG_CS0_WIDTH 16 +#define CFG_CS0_RO 0 +#define CFG_CS0_WS 6 +/* +#define CFG_CS3_BASE 0xE0000000 +#define CFG_CS3_SIZE 1*1024*1024 +#define CFG_CS3_WIDTH 16 +#define CFG_CS3_RO 0 +#define CFG_CS3_WS 6 +*/ /*----------------------------------------------------------------------- * Port configuration */ +#define CFG_PACNT 0x0000000 /* Port A D[31:24] */ +#define CFG_PADDR 0x0000000 +#define CFG_PADAT 0x0000000 +#define CFG_PBCNT 0x0000000 /* Port B D[23:16] */ +#define CFG_PBDDR 0x0000000 +#define CFG_PBDAT 0x0000000 -#endif /* _CONFIG_M5282EVB_H */ +#define CFG_PCCNT 0x0000000 /* Port C D[15:08] */ +#define CFG_PCDDR 0x0000000 +#define CFG_PCDAT 0x0000000 + +#define CFG_PDCNT 0x0000000 /* Port D D[07:00] */ +#define CFG_PCDDR 0x0000000 +#define CFG_PCDAT 0x0000000 + +#define CFG_PEHLPAR 0xC0 +#define CFG_PUAPAR 0x0F /* UA0..UA3 = Uart 0 +1 */ +#define CFG_DDRUA 0x05 +#define CFG_PJPAR 0xFF; + +#endif /* _CONFIG_M5282EVB_H */ From a605aacd8324094199402816cc6d9124aba57b8d Mon Sep 17 00:00:00 2001 From: TsiChungLiew Date: Thu, 16 Aug 2007 05:04:31 -0500 Subject: [PATCH 164/259] ColdFire: Add M5249EVB platform for MCF52x2 Signed-off-by: TsiChungLiew --- Makefile | 3 + board/freescale/m5249evb/Makefile | 44 +++++++ board/freescale/m5249evb/config.mk | 25 ++++ board/freescale/m5249evb/m5249evb.c | 114 ++++++++++++++++ board/freescale/m5249evb/u-boot.lds | 146 +++++++++++++++++++++ include/configs/M5249EVB.h | 195 ++++++++++++++++++++++++++++ 6 files changed, 527 insertions(+) create mode 100644 board/freescale/m5249evb/Makefile create mode 100644 board/freescale/m5249evb/config.mk create mode 100644 board/freescale/m5249evb/m5249evb.c create mode 100644 board/freescale/m5249evb/u-boot.lds create mode 100644 include/configs/M5249EVB.h diff --git a/Makefile b/Makefile index 79ab40b1a..af49438b4 100644 --- a/Makefile +++ b/Makefile @@ -1639,6 +1639,9 @@ ZPC1900_config: unconfig ## Coldfire ######################################################################### +M5249EVB_config : unconfig + @$(MKCONFIG) $(@:_config=) m68k mcf52x2 m5249evb freescale + cobra5272_config : unconfig @$(MKCONFIG) $(@:_config=) m68k mcf52x2 cobra5272 diff --git a/board/freescale/m5249evb/Makefile b/board/freescale/m5249evb/Makefile new file mode 100644 index 000000000..424ab1cf9 --- /dev/null +++ b/board/freescale/m5249evb/Makefile @@ -0,0 +1,44 @@ +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS = $(BOARD).o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/freescale/m5249evb/config.mk b/board/freescale/m5249evb/config.mk new file mode 100644 index 000000000..ccb2cf735 --- /dev/null +++ b/board/freescale/m5249evb/config.mk @@ -0,0 +1,25 @@ +# +# (C) Copyright 2000-2003 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# Coldfire contribution by Bernhard Kuhn +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +TEXT_BASE = 0xffe00000 diff --git a/board/freescale/m5249evb/m5249evb.c b/board/freescale/m5249evb/m5249evb.c new file mode 100644 index 000000000..b0bf41394 --- /dev/null +++ b/board/freescale/m5249evb/m5249evb.c @@ -0,0 +1,114 @@ +/* + * (C) Copyright 2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include + + +/* Prototypes */ +int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); + +int checkboard (void) { + ulong val; + uchar val8; + + puts ("Board: "); + puts("Freescale M5249EVB"); + val8 = ((uchar)~((uchar)mbar2_readLong(MCFSIM_GPIO1_READ) >> 4)) & 0xf; + printf(" (Switch=%1X)\n", val8); + + /* + * Set LED on + */ + val = mbar2_readLong(MCFSIM_GPIO1_OUT) & ~CFG_GPIO1_LED; + mbar2_writeLong(MCFSIM_GPIO1_OUT, val); /* Set LED on */ + + return 0; +}; + + +long int initdram (int board_type) { + unsigned long junk = 0xa5a59696; + + /* + * Note: + * RC = ([(RefreshTime/#rows) / (1/BusClk)] / 16) - 1 + */ + +#ifdef CFG_FAST_CLK + /* + * Busclk=70MHz, RefreshTime=64ms, #rows=4096 (4K) + * SO=1, NAM=0, COC=0, RTIM=01 (6clk refresh), RC=39 + */ + mbar_writeShort(MCFSIM_DCR, 0x8239); +#elif CFG_PLL_BYPASS + /* + * Busclk=5.6448MHz, RefreshTime=64ms, #rows=8192 (8K) + * SO=1, NAM=0, COC=0, RTIM=01 (6clk refresh), RC=02 + */ + mbar_writeShort(MCFSIM_DCR, 0x8202); +#else + /* + * Busclk=36MHz, RefreshTime=64ms, #rows=4096 (4K) + * SO=1, NAM=0, COC=0, RTIM=01 (6clk refresh), RC=22 (562 bus clock cycles) + */ + mbar_writeShort(MCFSIM_DCR, 0x8222); +#endif + + /* + * SDRAM starts at 0x0000_0000, CASL=10, CBM=010, PS=10 (16bit port), + * PM=1 (continuous page mode) + */ + + /* RE=0 (keep auto-refresh disabled while setting up registers) */ + mbar_writeLong(MCFSIM_DACR0, 0x00003324); + + /* BAM=007c (bits 22,21 are bank selects; 256kB blocks) */ + mbar_writeLong(MCFSIM_DMR0, 0x01fc0001); + + /** Precharge sequence **/ + mbar_writeLong(MCFSIM_DACR0, 0x0000332c); /* Set DACR0[IP] (bit 3) */ + *((volatile unsigned long *) 0x00) = junk; /* write to a memory location to init. precharge */ + udelay(0x10); /* Allow several Precharge cycles */ + + /** Refresh Sequence **/ + mbar_writeLong(MCFSIM_DACR0, 0x0000b324); /* Enable the refresh bit, DACR0[RE] (bit 15) */ + udelay(0x7d0); /* Allow gobs of refresh cycles */ + + /** Mode Register initialization **/ + mbar_writeLong(MCFSIM_DACR0, 0x0000b364); /* Enable DACR0[IMRS] (bit 6); RE remains enabled */ + *((volatile unsigned long *) 0x800) = junk; /* Access RAM to initialize the mode register */ + + return CFG_SDRAM_SIZE * 1024 * 1024; +}; + + +int testdram (void) { + /* TODO: XXX XXX XXX */ + printf ("DRAM test not implemented!\n"); + + return (0); +} + diff --git a/board/freescale/m5249evb/u-boot.lds b/board/freescale/m5249evb/u-boot.lds new file mode 100644 index 000000000..a803b1cba --- /dev/null +++ b/board/freescale/m5249evb/u-boot.lds @@ -0,0 +1,146 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(m68k) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/mcf52x2/start.o (.text) + lib_m68k/traps.o (.text) + cpu/mcf52x2/interrupts.o (.text) + common/dlmalloc.o (.text) + lib_generic/zlib.o (.text) + + . = DEFINED(env_offset) ? env_offset : .; + common/environment.o (.text) + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + + .reloc : + { + __got_start = .; + *(.got) + __got_end = .; + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + _sbss = .; + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + . = ALIGN(4); + _ebss = .; + } + _end = . ; + PROVIDE (end = .); +} diff --git a/include/configs/M5249EVB.h b/include/configs/M5249EVB.h new file mode 100644 index 000000000..b300b68bc --- /dev/null +++ b/include/configs/M5249EVB.h @@ -0,0 +1,195 @@ +/* + * Configuation settings for the esd TASREG board. + * + * (C) Copyright 2004 + * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef _M5249EVB_H +#define _M5249EVB_H + +/* + * High Level Configuration Options + * (easy to change) + */ +#define CONFIG_MCF52x2 /* define processor family */ +#define CONFIG_M5249 /* define processor type */ + +#define CONFIG_MCFTMR + +#define CONFIG_MCFUART +#define CFG_UART_PORT (0) +#define CONFIG_BAUDRATE 19200 +#define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 } + +#undef CONFIG_WATCHDOG + +#undef CONFIG_MONITOR_IS_IN_RAM /* no pre-loader required!!! ;-) */ + +/* + * BOOTP options + */ +#undef CONFIG_BOOTP_BOOTFILESIZE +#undef CONFIG_BOOTP_BOOTPATH +#undef CONFIG_BOOTP_GATEWAY +#undef CONFIG_BOOTP_HOSTNAME + +/* + * Command line configuration. + */ +#include +#undef CONFIG_CMD_NET + +#define CFG_PROMPT "=> " +#define CFG_LONGHELP /* undef to save memory */ + +#if defined(CONFIG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_DEVICE_NULLDEV 1 /* include nulldev device */ +#define CFG_CONSOLE_INFO_QUIET 1 /* don't print console @ startup */ +#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */ +#define CONFIG_LOOPW 1 /* enable loopw command */ +#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */ + +#define CFG_LOAD_ADDR 0x200000 /* default load address */ + +#define CFG_MEMTEST_START 0x400 +#define CFG_MEMTEST_END 0x380000 + +#define CFG_HZ 1000 + +/* + * Clock configuration: enable only one of the following options + */ + +#undef CFG_PLL_BYPASS /* bypass PLL for test purpose */ +#define CFG_FAST_CLK 1 /* MCF5249 can run at 140MHz */ +#define CFG_CLK 132025600 /* MCF5249 can run at 140MHz */ + +/* + * Low Level Configuration Settings + * (address mappings, register initial values, etc.) + * You should know what you are doing if you make changes here. + */ + +#define CFG_MBAR 0x10000000 /* Register Base Addrs */ +#define CFG_MBAR2 0x80000000 + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area (in DPRAM) + */ +#define CFG_INIT_RAM_ADDR 0x20000000 +#define CFG_INIT_RAM_END 0x1000 /* End of used area in internal SRAM */ +#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_OFFSET 0x4000 /* Address of Environment Sector*/ +#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */ +#define CFG_ENV_SECT_SIZE 0x2000 /* see README - env sector total size */ + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + */ +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_SDRAM_SIZE 16 /* SDRAM size in MB */ +#define CFG_FLASH_BASE (CFG_CSAR0 << 16) + +#if 0 /* test-only */ +#define CONFIG_PRAM 512 /* test-only for SDRAM problem!!!!!!!!!!!!!!!!!!!! */ +#endif + +#define CFG_MONITOR_BASE (CFG_FLASH_BASE + 0x400) + +#define CFG_MONITOR_LEN 0x20000 +#define CFG_MALLOC_LEN (1 * 1024*1024) /* Reserve 1 MB for malloc() */ +#define CFG_BOOTPARAMS_LEN 64*1024 + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization ?? + */ +#define CFG_BOOTMAPSZ (CFG_SDRAM_BASE + (CFG_SDRAM_SIZE << 20)) + +/*----------------------------------------------------------------------- + * FLASH organization + */ +#define CFG_FLASH_CFI +#ifdef CFG_FLASH_CFI + +# define CFG_FLASH_CFI_DRIVER 1 +# define CFG_FLASH_SIZE 0x1000000 /* Max size that the board might have */ +# define CFG_FLASH_CFI_WIDTH FLASH_CFI_16BIT +# define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +# define CFG_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ +# define CFG_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ +# define CFG_FLASH_CHECKSUM +# define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE } +#endif + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_CACHELINE_SIZE 16 + +/*----------------------------------------------------------------------- + * Memory bank definitions + */ + +/* CS0 - AMD Flash, address 0xffc00000 */ +#define CFG_CSAR0 0xffe0 +#define CFG_CSCR0 0x1980 /* WS=0110, AA=1, PS=10 */ +/** Note: There is a CSMR0/DRAM vector problem, need to disable C/I ***/ +#define CFG_CSMR0 0x003f0021 /* 4MB, AA=0, WP=0, C/I=1, V=1 */ + +/* CS1 - FPGA, address 0xe0000000 */ +#define CFG_CSAR1 0xe000 +#define CFG_CSCR1 0x0d80 /* WS=0011, AA=1, PS=10 */ +#define CFG_CSMR1 0x00010001 /* 128kB, AA=0, WP=0, C/I=0, V=1*/ + +/*----------------------------------------------------------------------- + * Port configuration + */ +#define CFG_GPIO_FUNC 0x00000008 /* Set gpio pins: none */ +#define CFG_GPIO1_FUNC 0x00df00f0 /* 36-39(SWITCH),48-52(FPGAs),54*/ +#define CFG_GPIO_EN 0x00000008 /* Set gpio output enable */ +#define CFG_GPIO1_EN 0x00c70000 /* Set gpio output enable */ +#define CFG_GPIO_OUT 0x00000008 /* Set outputs to default state */ +#define CFG_GPIO1_OUT 0x00c70000 /* Set outputs to default state */ +#define CFG_GPIO1_LED 0x00400000 /* user led */ + +#endif /* M5249 */ + From a1436a842654a8d3927d082a8ae9ee0a10da62d7 Mon Sep 17 00:00:00 2001 From: TsiChungLiew Date: Thu, 16 Aug 2007 13:20:50 -0500 Subject: [PATCH 165/259] ColdFire: Add M5253EVBE platform for MCF52x2 Signed-off-by: TsiChungLiew --- CREDITS | 5 + MAKEALL | 2 + Makefile | 3 + board/freescale/m5253evbe/Makefile | 44 ++++++ board/freescale/m5253evbe/config.mk | 25 +++ board/freescale/m5253evbe/m5253evbe.c | 133 ++++++++++++++++ board/freescale/m5253evbe/u-boot.lds | 144 +++++++++++++++++ cpu/mcf52x2/cpu.c | 32 +++- cpu/mcf52x2/cpu_init.c | 92 ++++++++--- cpu/mcf52x2/interrupts.c | 13 +- cpu/mcf52x2/speed.c | 35 ++++- cpu/mcf52x2/start.S | 6 +- doc/README.m5253evbe | 103 +++++++++++++ include/asm-m68k/immap.h | 25 ++- include/asm-m68k/immap_5253.h | 95 ++++++++++++ include/asm-m68k/m5253.h | 73 +++++++++ include/configs/M5253EVBE.h | 213 ++++++++++++++++++++++++++ lib_m68k/interrupts.c | 2 - 18 files changed, 1010 insertions(+), 35 deletions(-) create mode 100644 board/freescale/m5253evbe/Makefile create mode 100644 board/freescale/m5253evbe/config.mk create mode 100644 board/freescale/m5253evbe/m5253evbe.c create mode 100644 board/freescale/m5253evbe/u-boot.lds create mode 100644 doc/README.m5253evbe create mode 100644 include/asm-m68k/immap_5253.h create mode 100644 include/asm-m68k/m5253.h create mode 100644 include/configs/M5253EVBE.h mode change 100644 => 100755 lib_m68k/interrupts.c diff --git a/CREDITS b/CREDITS index b31125b68..b1abad32a 100644 --- a/CREDITS +++ b/CREDITS @@ -494,3 +494,8 @@ E: Tsi-Chung.Liew@freescale.com D: Support for ColdFire MCF532x W: www.freescale.com +N: Hayden Fraser +E: Hayden.Fraser@freescale.com +D: Support for ColdFire MCF5253 +W: www.freescale.com + diff --git a/MAKEALL b/MAKEALL index 4467d7570..890ee39a7 100755 --- a/MAKEALL +++ b/MAKEALL @@ -618,6 +618,8 @@ LIST_coldfire=" \ EB+MCF-EV123 \ EB+MCF-EV123_internal \ idmr \ + M5249EVB \ + M5253EVB \ M5271EVB \ M5272C3 \ M5282EVB \ diff --git a/Makefile b/Makefile index af49438b4..e5995ebfc 100644 --- a/Makefile +++ b/Makefile @@ -1642,6 +1642,9 @@ ZPC1900_config: unconfig M5249EVB_config : unconfig @$(MKCONFIG) $(@:_config=) m68k mcf52x2 m5249evb freescale +M5253EVBE_config : unconfig + @$(MKCONFIG) $(@:_config=) m68k mcf52x2 m5253evbe freescale + cobra5272_config : unconfig @$(MKCONFIG) $(@:_config=) m68k mcf52x2 cobra5272 diff --git a/board/freescale/m5253evbe/Makefile b/board/freescale/m5253evbe/Makefile new file mode 100644 index 000000000..424ab1cf9 --- /dev/null +++ b/board/freescale/m5253evbe/Makefile @@ -0,0 +1,44 @@ +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS = $(BOARD).o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/freescale/m5253evbe/config.mk b/board/freescale/m5253evbe/config.mk new file mode 100644 index 000000000..ccb2cf735 --- /dev/null +++ b/board/freescale/m5253evbe/config.mk @@ -0,0 +1,25 @@ +# +# (C) Copyright 2000-2003 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# Coldfire contribution by Bernhard Kuhn +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +TEXT_BASE = 0xffe00000 diff --git a/board/freescale/m5253evbe/m5253evbe.c b/board/freescale/m5253evbe/m5253evbe.c new file mode 100644 index 000000000..67fab5b02 --- /dev/null +++ b/board/freescale/m5253evbe/m5253evbe.c @@ -0,0 +1,133 @@ +/* + * (C) Copyright 2000-2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * Hayden Fraser (Hayden.Fraser@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +int checkboard(void) +{ + puts("Board: "); + puts("Freescale MCF5253 EVBE\n"); + return 0; +}; + +long int initdram(int board_type) +{ + int i; + + /* + * Check to see if the SDRAM has already been initialized + * by a run control tool + */ + if (!(mbar_readLong(MCFSIM_DCR) & 0x8000)) { + u32 RC, dramsize; + + RC = (CFG_CLK / 1000000) >> 1; + RC = (RC * 15) >> 4; + + /* Initialize DRAM Control Register: DCR */ + mbar_writeShort(MCFSIM_DCR, (0x8400 | RC)); + + mbar_writeLong(MCFSIM_DACR0, 0x00003224); + + /* Initialize DMR0 */ + dramsize = ((CFG_SDRAM_SIZE << 20) - 1) & 0xFFFC0000; + mbar_writeLong(MCFSIM_DMR0, dramsize | 1); + + mbar_writeLong(MCFSIM_DACR0, 0x0000322c); + + /* Write to this block to initiate precharge */ + *(u32 *) (CFG_SDRAM_BASE) = 0xa5a5a5a5; + + /* Set RE bit in DACR */ + mbar_writeLong(MCFSIM_DACR0, + mbar_readLong(MCFSIM_DACR0) | 0x8000); + + /* Wait for at least 8 auto refresh cycles to occur */ + udelay(500); + + /* Finish the configuration by issuing the MRS */ + mbar_writeLong(MCFSIM_DACR0, + mbar_readLong(MCFSIM_DACR0) | 0x0040); + + *(u32 *) (CFG_SDRAM_BASE + 0x800) = 0xa5a5a5a5; + } + + return CFG_SDRAM_SIZE * 1024 * 1024; +} + +int testdram(void) +{ + /* TODO: XXX XXX XXX */ + printf("DRAM test not implemented!\n"); + + return (0); +} + +#ifdef CONFIG_CMD_IDE +#include +int ide_preinit(void) +{ + return (0); +} + +void ide_set_reset(int idereset) +{ + volatile atac_t *ata = (atac_t *) CFG_ATA_BASE_ADDR; + long period; + /* t1, t2, t3, t4, t5, t6, t9, tRD, tA */ + int piotms[5][9] = { {70, 165, 60, 30, 50, 5, 20, 0, 35}, /* PIO 0 */ + {50, 125, 45, 20, 35, 5, 15, 0, 35}, /* PIO 1 */ + {30, 100, 30, 15, 20, 5, 10, 0, 35}, /* PIO 2 */ + {30, 80, 30, 10, 20, 5, 10, 0, 35}, /* PIO 3 */ + {25, 70, 20, 10, 20, 5, 10, 0, 35} /* PIO 4 */ + }; + + if (idereset) { + ata->cr = 0; /* control reset */ + udelay(100); + } else { + mbar2_writeLong(CIM_MISCCR, CIM_MISCCR_CPUEND); + +#define CALC_TIMING(t) (t + period - 1) / period + period = 1000000000 / (CFG_CLK / 2); /* period in ns */ + + /*ata->ton = CALC_TIMING (180); */ + ata->t1 = CALC_TIMING(piotms[2][0]); + ata->t2w = CALC_TIMING(piotms[2][1]); + ata->t2r = CALC_TIMING(piotms[2][1]); + ata->ta = CALC_TIMING(piotms[2][8]); + ata->trd = CALC_TIMING(piotms[2][7]); + ata->t4 = CALC_TIMING(piotms[2][3]); + ata->t9 = CALC_TIMING(piotms[2][6]); + + ata->cr = 0x40; /* IORDY enable */ + udelay(2000); + ata->cr |= 0x01; /* IORDY enable */ + } +} +#endif /* CONFIG_CMD_IDE */ + diff --git a/board/freescale/m5253evbe/u-boot.lds b/board/freescale/m5253evbe/u-boot.lds new file mode 100644 index 000000000..e2fd0708d --- /dev/null +++ b/board/freescale/m5253evbe/u-boot.lds @@ -0,0 +1,144 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(m68k) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/mcf52x2/start.o (.text) + lib_m68k/traps.o (.text) + cpu/mcf52x2/interrupts.o (.text) + common/dlmalloc.o (.text) + lib_generic/zlib.o (.text) + + . = DEFINED(env_offset) ? env_offset : .; + common/environment.o (.text) + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + + .reloc : + { + __got_start = .; + *(.got) + __got_end = .; + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + _sbss = .; + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + . = ALIGN(4); + _ebss = .; + } + _end = . ; + PROVIDE (end = .); +} diff --git a/cpu/mcf52x2/cpu.c b/cpu/mcf52x2/cpu.c index 96fe3711b..71ea408aa 100644 --- a/cpu/mcf52x2/cpu.c +++ b/cpu/mcf52x2/cpu.c @@ -205,7 +205,7 @@ int do_reset(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char *argv[]) }; #endif -#ifdef CONFIG_M5249 /* test-only: todo... */ +#ifdef CONFIG_M5249 int checkcpu(void) { char buf[32]; @@ -225,3 +225,33 @@ int do_reset(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char *argv[]) return 0; }; #endif + +#ifdef CONFIG_M5253 +int checkcpu(void) +{ + char buf[32]; + + unsigned char resetsource = mbar_readLong(SIM_RSR); + printf("CPU: Freescale Coldfire MCF5253 at %s MHz\n", + strmhz(buf, CFG_CLK)); + + if ((resetsource & SIM_RSR_HRST) || (resetsource & SIM_RSR_SWTR)) { + printf("Reset:%s%s\n", + (resetsource & SIM_RSR_HRST) ? " Hardware/ System Reset" + : "", + (resetsource & SIM_RSR_SWTR) ? " Software Watchdog" : + ""); + } + return 0; +} + +int do_reset(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char *argv[]) +{ + /* enable watchdog, set timeout to 0 and wait */ + mbar_writeByte(SIM_SYPCR, 0xc0); + while (1) ; + + /* we don't return! */ + return 0; +}; +#endif diff --git a/cpu/mcf52x2/cpu_init.c b/cpu/mcf52x2/cpu_init.c index 5736d0f26..f41d77bc5 100644 --- a/cpu/mcf52x2/cpu_init.c +++ b/cpu/mcf52x2/cpu_init.c @@ -6,6 +6,10 @@ * (C) Copyright 2005 * BuS Elektronik GmbH & Co. KG * + * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew@freescale.com) + * Hayden Fraser (Hayden.Fraser@freescale.com) + * * See file CREDITS for list of people who contributed to this * project. * @@ -29,6 +33,74 @@ #include #include +#if defined(CONFIG_M5253) +/* + * Breath some life into the CPU... + * + * Set up the memory map, + * initialize a bunch of registers, + * initialize the UPM's + */ +void cpu_init_f(void) +{ + mbar_writeByte(MCFSIM_MPARK, 0x40); /* 5249 Internal Core takes priority over DMA */ + mbar_writeByte(MCFSIM_SYPCR, 0x00); + mbar_writeByte(MCFSIM_SWIVR, 0x0f); + mbar_writeByte(MCFSIM_SWSR, 0x00); + mbar_writeByte(MCFSIM_SWDICR, 0x00); + mbar_writeByte(MCFSIM_TIMER1ICR, 0x00); + mbar_writeByte(MCFSIM_TIMER2ICR, 0x88); + mbar_writeByte(MCFSIM_I2CICR, 0x00); + mbar_writeByte(MCFSIM_UART1ICR, 0x00); + mbar_writeByte(MCFSIM_UART2ICR, 0x00); + mbar_writeByte(MCFSIM_ICR6, 0x00); + mbar_writeByte(MCFSIM_ICR7, 0x00); + mbar_writeByte(MCFSIM_ICR8, 0x00); + mbar_writeByte(MCFSIM_ICR9, 0x00); + mbar_writeByte(MCFSIM_QSPIICR, 0x00); + + mbar2_writeLong(MCFSIM_GPIO_INT_EN, 0x00000080); + mbar2_writeByte(MCFSIM_INTBASE, 0x40); /* Base interrupts at 64 */ + mbar2_writeByte(MCFSIM_SPURVEC, 0x00); + + /*mbar2_writeLong(MCFSIM_IDECONFIG1, 0x00000020); *//* Enable a 1 cycle pre-drive cycle on CS1 */ + + /* + * Setup chip selects... + */ + + mbar_writeShort(MCFSIM_CSAR1, CFG_CSAR1); + mbar_writeShort(MCFSIM_CSCR1, CFG_CSCR1); + mbar_writeLong(MCFSIM_CSMR1, CFG_CSMR1); + + mbar_writeShort(MCFSIM_CSAR0, CFG_CSAR0); + mbar_writeShort(MCFSIM_CSCR0, CFG_CSCR0); + mbar_writeLong(MCFSIM_CSMR0, CFG_CSMR0); + + /* enable instruction cache now */ + icache_enable(); +} + +/*initialize higher level parts of CPU like timers */ +int cpu_init_r(void) +{ + return (0); +} + +void uart_port_conf(void) +{ + /* Setup Ports: */ + switch (CFG_UART_PORT) { + case 0: + break; + case 1: + break; + case 2: + break; + } +} +#endif /* #if defined(CONFIG_M5253) */ + #if defined(CONFIG_M5271) void cpu_init_f(void) { @@ -394,26 +466,6 @@ void uart_port_conf(void) */ void cpu_init_f(void) { -#ifndef CFG_PLL_BYPASS - /* - * Setup the PLL to run at the specified speed - * - */ - volatile unsigned long cpll = mbar2_readLong(MCFSIM_PLLCR); - unsigned long pllcr; -#ifdef CFG_FAST_CLK - pllcr = 0x925a3100; /* ~140MHz clock (PLL bypass = 0) */ -#else - pllcr = 0x135a4140; /* ~72MHz clock (PLL bypass = 0) */ -#endif - cpll = cpll & 0xfffffffe; /* Set PLL bypass mode = 0 (PSTCLK = crystal) */ - mbar2_writeLong(MCFSIM_PLLCR, cpll); /* Set the PLL to bypass mode (PSTCLK = crystal) */ - mbar2_writeLong(MCFSIM_PLLCR, pllcr); /* set the clock speed */ - pllcr ^= 0x00000001; /* Set pll bypass to 1 */ - mbar2_writeLong(MCFSIM_PLLCR, pllcr); /* Start locking (pll bypass = 1) */ - udelay(0x20); /* Wait for a lock ... */ -#endif /* #ifndef CFG_PLL_BYPASS */ - /* * NOTE: by setting the GPIO_FUNCTION registers, we ensure that the UART pins * (UART0: gpio 30,27, UART1: gpio 31, 28) will be used as UART pins diff --git a/cpu/mcf52x2/interrupts.c b/cpu/mcf52x2/interrupts.c index d9a35bb8c..2ccbde587 100644 --- a/cpu/mcf52x2/interrupts.c +++ b/cpu/mcf52x2/interrupts.c @@ -1,9 +1,10 @@ /* - * (C) Copyright 2003 Josef Baumgartner - * * (C) Copyright 2000-2004 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * + * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew@freescale.com) + * * See file CREDITS for list of people who contributed to this * project. * @@ -82,7 +83,7 @@ void dtimer_intr_setup(void) #endif /* CONFIG_MCFTMR */ #endif /* CONFIG_M5282 | CONFIG_M5271 */ -#ifdef CONFIG_M5249 +#if defined(CONFIG_M5249) || defined(CONFIG_M5253) int interrupt_init(void) { enable_interrupts(); @@ -94,9 +95,7 @@ int interrupt_init(void) void dtimer_intr_setup(void) { mbar_writeLong(MCFSIM_IMR, mbar_readLong(MCFSIM_IMR) & ~0x00000400); - mbar_writeByte(MCFSIM_TIMER2ICR, - MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL7 | - MCFSIM_ICR_PRI3); + mbar_writeByte(MCFSIM_TIMER2ICR, CFG_TMRINTR_PRI); } #endif /* CONFIG_MCFTMR */ -#endif /* CONFIG_M5249 */ +#endif /* CONFIG_M5249 || CONFIG_M5253 */ diff --git a/cpu/mcf52x2/speed.c b/cpu/mcf52x2/speed.c index ac860b2c6..bc1e20023 100644 --- a/cpu/mcf52x2/speed.c +++ b/cpu/mcf52x2/speed.c @@ -2,6 +2,9 @@ * (C) Copyright 2003 * Josef Baumgartner * + * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * Hayden Fraser (Hayden.Fraser@freescale.com) + * * See file CREDITS for list of people who contributed to this * project. * @@ -23,6 +26,7 @@ #include #include +#include DECLARE_GLOBAL_DATA_PTR; @@ -31,8 +35,37 @@ DECLARE_GLOBAL_DATA_PTR; */ int get_clocks (void) { - gd->cpu_clk = CFG_CLK; +#if defined(CONFIG_M5249) || defined(CONFIG_M5253) + volatile unsigned long cpll = mbar2_readLong(MCFSIM_PLLCR); + unsigned long pllcr; + +#ifndef CFG_PLL_BYPASS + #ifdef CONFIG_M5249 + /* Setup the PLL to run at the specified speed */ +#ifdef CFG_FAST_CLK + pllcr = 0x925a3100; /* ~140MHz clock (PLL bypass = 0) */ +#else + pllcr = 0x135a4140; /* ~72MHz clock (PLL bypass = 0) */ +#endif +#endif /* CONFIG_M5249 */ + +#ifdef CONFIG_M5253 + pllcr = CFG_PLLCR; +#endif /* CONFIG_M5253 */ + + cpll = cpll & 0xfffffffe; /* Set PLL bypass mode = 0 (PSTCLK = crystal) */ + mbar2_writeLong(MCFSIM_PLLCR, cpll); /* Set the PLL to bypass mode (PSTCLK = crystal) */ + mbar2_writeLong(MCFSIM_PLLCR, pllcr); /* set the clock speed */ + pllcr ^= 0x00000001; /* Set pll bypass to 1 */ + mbar2_writeLong(MCFSIM_PLLCR, pllcr); /* Start locking (pll bypass = 1) */ + udelay(0x20); /* Wait for a lock ... */ +#endif /* #ifndef CFG_PLL_BYPASS */ + +#endif /* CONFIG_M5249 || CONFIG_M5253 */ + + gd->cpu_clk = CFG_CLK; +#if defined(CONFIG_M5249) || defined(CONFIG_M5253) gd->bus_clk = gd->cpu_clk / 2; #else gd->bus_clk = gd->cpu_clk; diff --git a/cpu/mcf52x2/start.S b/cpu/mcf52x2/start.S index 6783d4d94..686e2a533 100644 --- a/cpu/mcf52x2/start.S +++ b/cpu/mcf52x2/start.S @@ -121,7 +121,7 @@ _start: nop move.w #0x2700,%sr -#if defined(CONFIG_M5272) || defined(CONFIG_M5249) +#if defined(CONFIG_M5272) || defined(CONFIG_M5249) || defined(CONFIG_M5253) move.l #(CFG_MBAR + 1), %d0 /* set MBAR address + valid flag */ move.c %d0, %MBAR @@ -133,7 +133,7 @@ _start: move.l #(CFG_INIT_RAM_ADDR + 1), %d0 movec %d0, %RAMBAR0 -#endif /* #if defined(CONFIG_M5272) || defined(CONFIG_M5249) */ +#endif /* CONFIG_M5272 || CONFIG_M5249 || CONFIG_M5253 */ #if defined(CONFIG_M5282) || defined(CONFIG_M5271) /* Initialize IPSBAR */ @@ -407,7 +407,7 @@ icache_state_access_1: rts #endif -#ifdef CONFIG_M5249 +#if defined(CONFIG_M5249) || defined(CONFIG_M5253) .globl icache_enable icache_enable: /* diff --git a/doc/README.m5253evbe b/doc/README.m5253evbe new file mode 100644 index 000000000..7f2afcf15 --- /dev/null +++ b/doc/README.m5253evbe @@ -0,0 +1,103 @@ +Freescale Amadeus Plus M5253EVBE board +====================================== + +Hayden Fraser(Hayden.Fraser@freescale.com) +Created 06/05/2007 +=========================================== + + +1. SWITCH SETTINGS +================== +1.1 N/A + + +2. MEMORY MAP UNDER U-BOOT AND LINUX KERNEL +=========================================== +2.1. For the initial bringup, we adopted a consistent memory scheme between u-boot and + linux kernel, you can customize it based on your system requirements: + SDR: 0x00000000-0x00ffffff + SRAM0: 0x20010000-0x20017fff + SRAM1: 0x20000000-0x2000ffff + MBAR1: 0x10000000-0x4fffffff + MBAR2: 0x80000000-0xCfffffff + Flash: 0xffe00000-0xffffffff + +3. DEFINITIONS AND COMPILATION +============================== +3.1 Explanation on NEW definitions in include/configs/M5253EVBE.h + CONFIG_MCF52x2 Processor family + CONFIG_MCF5253 MCF5253 specific + CONFIG_M5253EVBE Amadeus Plus board specific + CFG_CLK Define Amadeus Plus CPU Clock + CFG_MBAR MBAR base address + CFG_MBAR2 MBAR2 base address + +3.2 Compilation + export CROSS_COMPILE=/usr/local/freescale-coldfire-4.1-elf/bin/m68k-elf- + cd u-boot-1-2-x + make distclean + make M5253EVBE_config + make + + +4. SCREEN DUMP +============== +4.1 U-Boot 1.2.0 (Jun 18 2007 - 18:20:00) + +CPU: Freescale Coldfire MCF5253 at 62 MHz +Board: Freescale MCF5253 EVBE +DRAM: 16 MB +FLASH: 2 MB +In: serial +Out: serial +Err: serial +=> flinfo + +Bank # 1: CFI conformant FLASH (16 x 16) Size: 2 MB in 35 Sectors + AMD Standard command set, Manufacturer ID: 0x01, Device ID: 0x49 + Erase timeout: 16384 ms, write timeout: 1 ms + + Sector Start Addresses: + FFE00000 RO FFE04000 RO FFE06000 RO FFE08000 RO FFE10000 RO + FFE20000 FFE30000 FFE40000 FFE50000 FFE60000 + FFE70000 FFE80000 FFE90000 FFEA0000 FFEB0000 + FFEC0000 FFED0000 FFEE0000 FFEF0000 FFF00000 + FFF10000 FFF20000 FFF30000 FFF40000 FFF50000 + FFF60000 FFF70000 FFF80000 FFF90000 FFFA0000 + FFFB0000 FFFC0000 FFFD0000 FFFE0000 FFFF0000 + +=> bdinfo +boot_params = 0x00F62F90 +memstart = 0x00000000 +memsize = 0x01000000 +flashstart = 0xFFE00000 +flashsize = 0x00200000 +flashoffset = 0x00000000 +baudrate = 19200 bps + +=> printenv +bootdelay=5 +baudrate=19200 +stdin=serial +stdout=serial +stderr=serial + +Environment size: 134/8188 bytes +=> saveenv +Saving Environment to Flash... +Un-Protected 1 sectors +Erasing Flash... +. done +Erased 1 sectors +Writing to Flash... done +Protected 1 sectors +=> + +5. COMPILER +----------- +To create U-Boot the CodeSourcery's version of the GNU Toolchain for the ColdFire architecture +compiler set (freescale-coldfire-4.1-elf) from www.codesourcery.com was used. +You can download it from:http://www.codesourcery.com/gnu_toolchains/coldfire/download.html + +compiler that you used - for example, codesourcery_elf requires -MQ in rules.mk, old M68K 2.95.3 just -M +codesourcery_elf requires -MQ in rules.mk, old M68K 2.95.3 just -M diff --git a/include/asm-m68k/immap.h b/include/asm-m68k/immap.h index 3ee7071f3..bf7b51bec 100644 --- a/include/asm-m68k/immap.h +++ b/include/asm-m68k/immap.h @@ -43,11 +43,34 @@ #define CFG_TMRINTR_NO (31) #define CFG_TMRINTR_MASK (0x00000400) #define CFG_TMRINTR_PEND (CFG_TMRINTR_MASK) -#define CFG_TMRINTR_PRI (0) /* Level must include inorder to work */ +#define CFG_TMRINTR_PRI (MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL7 | MCFSIM_ICR_PRI3) #define CFG_TIMER_PRESCALER (((gd->bus_clk / 2000000) - 1) << 8) #endif #endif /* CONFIG_M5249 */ +#ifdef CONFIG_M5253 +#include +#include +#include + +#define CFG_UART_BASE (MMAP_UART0 + (CFG_UART_PORT * 0x40)) + +#define CFG_INTR_BASE (MMAP_INTC) +#define CFG_NUM_IRQS (64) + +/* Timer */ +#ifdef CONFIG_MCFTMR +#define CFG_UDELAY_BASE (MMAP_DTMR0) +#define CFG_TMR_BASE (MMAP_DTMR1) +#define CFG_TMRPND_REG (mbar_readLong(MCFSIM_IPR)) +#define CFG_TMRINTR_NO (27) +#define CFG_TMRINTR_MASK (0x00000400) +#define CFG_TMRINTR_PEND (CFG_TMRINTR_MASK) +#define CFG_TMRINTR_PRI (MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL3 | MCFSIM_ICR_PRI3) +#define CFG_TIMER_PRESCALER (((gd->bus_clk / 2000000) - 1) << 8) +#endif +#endif /* CONFIG_M5253 */ + #ifdef CONFIG_M5271 #include #include diff --git a/include/asm-m68k/immap_5253.h b/include/asm-m68k/immap_5253.h new file mode 100644 index 000000000..aafbdd095 --- /dev/null +++ b/include/asm-m68k/immap_5253.h @@ -0,0 +1,95 @@ +/* + * MCF5253 Internal Memory Map + * + * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __IMMAP_5249__ +#define __IMMAP_5249__ + +#define MMAP_INTC (CFG_MBAR + 0x00000040) +#define MMAP_DTMR0 (CFG_MBAR + 0x00000140) +#define MMAP_DTMR1 (CFG_MBAR + 0x00000180) +#define MMAP_UART0 (CFG_MBAR + 0x000001C0) +#define MMAP_UART1 (CFG_MBAR + 0x00000200) +#define MMAP_I2C0 (CFG_MBAR + 0x00000280) +#define MMAP_QSPI (CFG_MBAR + 0x00000400) +#define MMAP_CAN0 (CFG_MBAR + 0x00010000) +#define MMAP_CAN1 (CFG_MBAR + 0x00011000) + +#define MMAP_I2C1 (CFG_MBAR2 + 0x00000440) +#define MMAP_UART2 (CFG_MBAR2 + 0x00000C00) + +/********************************************************************* +* ATA Module (ATAC) +*********************************************************************/ + +/* Register read/write struct */ +typedef struct atac { + /* PIO */ + u8 toff; /* 0x00 */ + u8 ton; /* 0x01 */ + u8 t1; /* 0x02 */ + u8 t2w; /* 0x03 */ + u8 t2r; /* 0x04 */ + u8 ta; /* 0x05 */ + u8 trd; /* 0x06 */ + u8 t4; /* 0x07 */ + u8 t9; /* 0x08 */ + + /* DMA */ + u8 tm; /* 0x09 */ + u8 tn; /* 0x0A */ + u8 td; /* 0x0B */ + u8 tk; /* 0x0C */ + u8 tack; /* 0x0D */ + u8 tenv; /* 0x0E */ + u8 trp; /* 0x0F */ + u8 tzah; /* 0x10 */ + u8 tmli; /* 0x11 */ + u8 tdvh; /* 0x12 */ + u8 tdzfs; /* 0x13 */ + u8 tdvs; /* 0x14 */ + u8 tcvh; /* 0x15 */ + u8 tss; /* 0x16 */ + u8 tcyc; /* 0x17 */ + + /* FIFO */ + u32 fifo32; /* 0x18 */ + u16 fifo16; /* 0x1C */ + u8 rsvd0[2]; + u8 ffill; /* 0x20 */ + u8 rsvd1[3]; + + /* ATA */ + u8 cr; /* 0x24 */ + u8 rsvd2[3]; + u8 isr; /* 0x28 */ + u8 rsvd3[3]; + u8 ier; /* 0x2C */ + u8 rsvd4[3]; + u8 icr; /* 0x30 */ + u8 rsvd5[3]; + u8 falarm; /* 0x34 */ +} atac_t; + +#endif /* __IMMAP_5249__ */ diff --git a/include/asm-m68k/m5253.h b/include/asm-m68k/m5253.h new file mode 100644 index 000000000..eda347273 --- /dev/null +++ b/include/asm-m68k/m5253.h @@ -0,0 +1,73 @@ +/* + * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef m5253_h +#define m5253_h +/****************************************************************************/ + +/* +* PLL Module (PLL) +*/ + +/* Register read/write macros */ +#define PLL_PLLCR (0x000180) + +#define SIM_RSR (0x000000) +#define SIM_SYPCR (0x000001) +#define SIM_SWIVR (0x000002) +#define SIM_SWSR (0x000003) +#define SIM_MPARK (0x00000C) + +/* Bit definitions and macros for RSR */ +#define SIM_RSR_SWTR (0x20) +#define SIM_RSR_HRST (0x80) + +/* Register read/write macros */ +#define CIM_MISCCR (0x000500) +#define CIM_ATA_DADDR (0x000504) +#define CIM_ATA_DCOUNT (0x000508) +#define CIM_RTC_TIME (0x00050C) +#define CIM_USB_CANCLK (0x000510) + +/* Bit definitions and macros for MISCCR */ +#define CIM_MISCCR_ADTA (0x00000001) +#define CIM_MISCCR_ADTD (0x00000002) +#define CIM_MISCCR_ADIE (0x00000004) +#define CIM_MISCCR_ADIC (0x00000008) +#define CIM_MISCCR_ADIP (0x00000010) +#define CIM_MISCCR_CPUEND (0x00000020) +#define CIM_MISCCR_DMAEND (0x00000040) +#define CIM_MISCCR_RTCCLR (0x00000080) +#define CIM_MISCCR_RTCPL (0x00000100) +#define CIM_MISCCR_URIE (0x00000800) +#define CIM_MISCCR_URIC (0x00001000) +#define CIM_MISCCR_URIP (0x00002000) + +/* Bit definitions and macros for ATA_DADDR */ +#define CIM_ATA_DADDR_ATAADDR(x) (((x)&0x00003FFF)<<2) +#define CIM_ATA_DADDR_RAMADDR(x) (((x)&0x00003FFF)<<18) + +/* Bit definitions and macros for ATA_DCOUNT */ +#define CIM_ATA_DCOUNT_COUNT(x) (((x)&0x0000FFFF)) + +#endif /* m5253_h */ diff --git a/include/configs/M5253EVBE.h b/include/configs/M5253EVBE.h new file mode 100644 index 000000000..9ad74e2bc --- /dev/null +++ b/include/configs/M5253EVBE.h @@ -0,0 +1,213 @@ +/* + * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * Hayden Fraser (Hayden.Fraser@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _M5253EVBE_H +#define _M5253EVBE_H + +#define CONFIG_MCF52x2 /* define processor family */ +#define CONFIG_M5253 /* define processor type */ +#define CONFIG_M5253EVBE /* define board type */ + +#define CONFIG_MCFTMR + +#define CONFIG_MCFUART +#define CFG_UART_PORT (0) +#define CONFIG_BAUDRATE 19200 +#define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 } + +#undef CONFIG_WATCHDOG /* disable watchdog */ + +#define CONFIG_BOOTDELAY 5 + +/* Configuration for environment + * Environment is embedded in u-boot in the second sector of the flash + */ +#ifndef CONFIG_MONITOR_IS_IN_RAM +#define CFG_ENV_OFFSET 0x4000 +#define CFG_ENV_SECT_SIZE 0x2000 +#define CFG_ENV_IS_IN_FLASH 1 +#else +#define CFG_ENV_ADDR 0xffe04000 +#define CFG_ENV_SECT_SIZE 0x2000 +#define CFG_ENV_IS_IN_FLASH 1 +#endif + +/* + * BOOTP options + */ +#undef CONFIG_BOOTP_BOOTFILESIZE +#undef CONFIG_BOOTP_BOOTPATH +#undef CONFIG_BOOTP_GATEWAY +#undef CONFIG_BOOTP_HOSTNAME + +/* + * Command line configuration. + */ +#include +#undef CONFIG_CMD_NET +#define CONFIG_CMD_LOADB +#define CONFIG_CMD_LOADS +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT +#define CONFIG_CMD_IDE +#define CONFIG_CMD_MEMORY +#define CONFIG_CMD_MISC + +/* ATA */ +#define CONFIG_DOS_PARTITION +#define CONFIG_MAC_PARTITION +#define CONFIG_IDE_RESET 1 +#define CONFIG_IDE_PREINIT 1 +#define CONFIG_ATAPI +#undef CONFIG_LBA48 + +#define CFG_IDE_MAXBUS 1 +#define CFG_IDE_MAXDEVICE 2 + +#define CFG_ATA_BASE_ADDR (CFG_MBAR2 + 0x800) +#define CFG_ATA_IDE0_OFFSET 0 + +#define CFG_ATA_DATA_OFFSET 0xA0 /* Offset for data I/O */ +#define CFG_ATA_REG_OFFSET 0xA0 /* Offset for normal register accesses */ +#define CFG_ATA_ALT_OFFSET 0xC0 /* Offset for alternate registers */ +#define CFG_ATA_STRIDE 4 /* Interval between registers */ +#define _IO_BASE 0 + +#define CFG_PROMPT "=> " +#define CFG_LONGHELP /* undef to save memory */ + +#if defined(CONFIG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_LOAD_ADDR 0x00100000 + +#define CFG_MEMTEST_START 0x400 +#define CFG_MEMTEST_END 0x380000 + +#define CFG_HZ 1000 + +#undef CFG_PLL_BYPASS /* bypass PLL for test purpose */ +#define CFG_FAST_CLK +#ifdef CFG_FAST_CLK +# define CFG_PLLCR 0x1243E054 +# define CFG_CLK 140000000 +#else +# define CFG_PLLCR 0x135a4140 +# define CFG_CLK 70000000 +#endif + +/* + * Low Level Configuration Settings + * (address mappings, register initial values, etc.) + * You should know what you are doing if you make changes here. + */ + +#define CFG_MBAR 0x10000000 /* Register Base Addrs */ +#define CFG_MBAR2 0x80000000 /* Module Base Addrs 2 */ + +/* + * Definitions for initial stack pointer and data area (in DPRAM) + */ +#define CFG_INIT_RAM_ADDR 0x20000000 +#define CFG_INIT_RAM_END 0x10000 /* End of used area in internal SRAM */ +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +/* + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + */ +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_SDRAM_SIZE 16 /* SDRAM size in MB */ + +#ifdef CONFIG_MONITOR_IS_IN_RAM +#define CFG_MONITOR_BASE 0x20000 +#else +#define CFG_MONITOR_BASE (CFG_FLASH_BASE + 0x400) +#endif + +#define CFG_MONITOR_LEN 0x40000 +#define CFG_MALLOC_LEN (256 << 10) +#define CFG_BOOTPARAMS_LEN (64*1024) + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization ?? + */ +#define CFG_BOOTMAPSZ (CFG_SDRAM_BASE + (CFG_SDRAM_SIZE << 20)) + +/* FLASH organization */ +#define CFG_FLASH_BASE 0xffe00000 +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 35 /* max number of sectors on one chip */ +#define CFG_FLASH_ERASE_TOUT 1000 + +#define CFG_FLASH_CFI 1 +#define CFG_FLASH_CFI_DRIVER 1 +#define CFG_FLASH_SIZE 0x200000 +#define CFG_FLASH_CFI_WIDTH FLASH_CFI_16BIT + +/* Cache Configuration */ +#define CFG_CACHELINE_SIZE 16 + +/* Port configuration */ +#define CFG_FECI2C 0xF0 + +#define CFG_CSAR0 0xFFE0 +#define CFG_CSMR0 0x001F0021 +#define CFG_CSCR0 0x1D80 + +#define CFG_CSAR1 0 +#define CFG_CSMR1 0 +#define CFG_CSCR1 0 + +#define CFG_CSAR2 0 +#define CFG_CSMR2 0 +#define CFG_CSCR2 0 + +#define CFG_CSAR3 0 +#define CFG_CSMR3 0 +#define CFG_CSCR3 0 + +/*----------------------------------------------------------------------- + * Port configuration + */ +#define CFG_GPIO_FUNC 0x00000008 /* Set gpio pins: none */ +#define CFG_GPIO1_FUNC 0x00df00f0 /* 36-39(SWITCH),48-52(FPGAs),54 */ +#define CFG_GPIO_EN 0x00000008 /* Set gpio output enable */ +#define CFG_GPIO1_EN 0x00c70000 /* Set gpio output enable */ +#define CFG_GPIO_OUT 0x00000008 /* Set outputs to default state */ +#define CFG_GPIO1_OUT 0x00c70000 /* Set outputs to default state */ +#define CFG_GPIO1_LED 0x00400000 /* user led */ + +#endif /* _M5253EVB_H */ + diff --git a/lib_m68k/interrupts.c b/lib_m68k/interrupts.c old mode 100644 new mode 100755 index 8919c0e8c..1635d6fed --- a/lib_m68k/interrupts.c +++ b/lib_m68k/interrupts.c @@ -106,8 +106,6 @@ void int_handler (struct pt_regs *fp) vec = (fp->vector >> 2) & 0xff; if (vec > 0x40) vec -= 0x40; - else - return; if (irq_vecs[vec].handler != NULL) { irq_vecs[vec].handler (irq_vecs[vec].arg); From 8ae158cd87a4a25722b27835261b6ff0fa2aa6a7 Mon Sep 17 00:00:00 2001 From: TsiChungLiew Date: Thu, 16 Aug 2007 15:05:11 -0500 Subject: [PATCH 166/259] ColdFire: Add M54455EVB for MCF5445x Signed-off-by: TsiChungLiew --- CREDITS | 2 +- MAINTAINERS | 9 + MAKEALL | 1 + Makefile | 28 + README | 1 + board/freescale/m54455evb/Makefile | 44 + board/freescale/m54455evb/config.mk | 25 + board/freescale/m54455evb/flash.c | 974 ++++++++++++++++ board/freescale/m54455evb/m54455evb.c | 165 +++ board/freescale/m54455evb/mii.c | 320 +++++ board/freescale/m54455evb/u-boot.lds | 144 +++ common/cmd_bdinfo.c | 22 +- cpu/mcf5445x/Makefile | 48 + cpu/mcf5445x/config.mk | 27 + cpu/mcf5445x/cpu.c | 97 ++ cpu/mcf5445x/cpu_init.c | 140 +++ cpu/mcf5445x/interrupts.c | 52 + cpu/mcf5445x/pci.c | 189 +++ cpu/mcf5445x/speed.c | 186 +++ cpu/mcf5445x/start.S | 388 +++++++ doc/README.m54455evb | 416 +++++++ drivers/net/mcffec.c | 27 +- include/asm-m68k/global_data.h | 8 + include/asm-m68k/immap.h | 40 + include/asm-m68k/immap_5445x.h | 937 +++++++++++++++ include/asm-m68k/m5445x.h | 1541 +++++++++++++++++++++++++ include/asm-m68k/rtc.h | 3 +- include/asm-m68k/u-boot.h | 8 + include/configs/M54455EVB.h | 391 +++++++ lib_m68k/board.c | 30 +- lib_m68k/interrupts.c | 0 lib_m68k/m68k_linux.c | 376 +++--- 32 files changed, 6459 insertions(+), 180 deletions(-) create mode 100644 board/freescale/m54455evb/Makefile create mode 100644 board/freescale/m54455evb/config.mk create mode 100644 board/freescale/m54455evb/flash.c create mode 100644 board/freescale/m54455evb/m54455evb.c create mode 100644 board/freescale/m54455evb/mii.c create mode 100644 board/freescale/m54455evb/u-boot.lds create mode 100644 cpu/mcf5445x/Makefile create mode 100644 cpu/mcf5445x/config.mk create mode 100644 cpu/mcf5445x/cpu.c create mode 100644 cpu/mcf5445x/cpu_init.c create mode 100644 cpu/mcf5445x/interrupts.c create mode 100644 cpu/mcf5445x/pci.c create mode 100644 cpu/mcf5445x/speed.c create mode 100644 cpu/mcf5445x/start.S create mode 100644 doc/README.m54455evb create mode 100644 include/asm-m68k/immap_5445x.h create mode 100644 include/asm-m68k/m5445x.h create mode 100644 include/configs/M54455EVB.h mode change 100755 => 100644 lib_m68k/interrupts.c diff --git a/CREDITS b/CREDITS index b1abad32a..f30b2228f 100644 --- a/CREDITS +++ b/CREDITS @@ -491,7 +491,7 @@ W: www.monstr.eu N: TsiChung Liew E: Tsi-Chung.Liew@freescale.com -D: Support for ColdFire MCF532x +D: Support for ColdFire MCF532x, MCF5445x W: www.freescale.com N: Hayden Fraser diff --git a/MAINTAINERS b/MAINTAINERS index d5249e515..7fde6d99e 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -606,6 +606,15 @@ Zachary P. Landau r5200 mcf52x2 +TsiChung Liew + + M5329EVB mcf532x + M54455EVB mcf5445x + +Hayden Fraser + + M5253EVBE mcf52x2 + ######################################################################### # AVR32 Systems: # # # diff --git a/MAKEALL b/MAKEALL index 890ee39a7..b7ed0f430 100755 --- a/MAKEALL +++ b/MAKEALL @@ -624,6 +624,7 @@ LIST_coldfire=" \ M5272C3 \ M5282EVB \ M5329EVB \ + M54455EVB \ r5200 \ TASREG \ " diff --git a/Makefile b/Makefile index e5995ebfc..201ad0e77 100644 --- a/Makefile +++ b/Makefile @@ -1692,6 +1692,34 @@ M5329BFEE_config : unconfig fi @$(MKCONFIG) -a M5329EVB m68k mcf532x m5329evb freescale +M54455EVB_config \ +M54455EVB_atmel_config \ +M54455EVB_intel_config \ +M54455EVB_a33_config \ +M54455EVB_a66_config \ +M54455EVB_i33_config \ +M54455EVB_i66_config : unconfig + @case "$@" in \ + M54455EVB_config) FLASH=ATMEL; FREQ=33333333;; \ + M54455EVB_atmel_config) FLASH=ATMEL; FREQ=33333333;; \ + M54455EVB_intel_config) FLASH=INTEL; FREQ=33333333;; \ + M54455EVB_a33_config) FLASH=ATMEL; FREQ=33333333;; \ + M54455EVB_a66_config) FLASH=ATMEL; FREQ=66666666;; \ + M54455EVB_i33_config) FLASH=INTEL; FREQ=33333333;; \ + M54455EVB_i66_config) FLASH=INTEL; FREQ=66666666;; \ + esac; \ + >include/config.h ; \ + if [ "$${FLASH}" == "INTEL" ] ; then \ + echo "#undef CFG_ATMEL_BOOT" >> include/config.h ; \ + echo "... with INTEL boot..." ; \ + else \ + echo "#define CFG_ATMEL_BOOT" >> include/config.h ; \ + echo "... with ATMEL boot..." ; \ + fi; \ + echo "#define CFG_INPUT_CLKSRC $${FREQ}" >>include/config.h ; \ + echo "... with $${FREQ}Hz input clock" + @$(MKCONFIG) -a M54455EVB m68k mcf5445x m54455evb freescale + ######################################################################### ## MPC83xx Systems ######################################################################### diff --git a/README b/README index 4f2acb40d..4b1982b22 100644 --- a/README +++ b/README @@ -137,6 +137,7 @@ Directory Hierarchy: - ixp Files specific to Intel XScale IXP CPUs - mcf52x2 Files specific to Freescale ColdFire MCF52x2 CPUs - mcf532x Files specific to Freescale ColdFire MCF5329 CPUs + - mcf5445x Files specific to Freescale ColdFire MCF5445x CPUs - mips Files specific to MIPS CPUs - mpc5xx Files specific to Freescale MPC5xx CPUs - mpc5xxx Files specific to Freescale MPC5xxx CPUs diff --git a/board/freescale/m54455evb/Makefile b/board/freescale/m54455evb/Makefile new file mode 100644 index 000000000..ca9a7729e --- /dev/null +++ b/board/freescale/m54455evb/Makefile @@ -0,0 +1,44 @@ +# +# (C) Copyright 2000-2003 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS = $(BOARD).o flash.o mii.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### \ No newline at end of file diff --git a/board/freescale/m54455evb/config.mk b/board/freescale/m54455evb/config.mk new file mode 100644 index 000000000..ce014edca --- /dev/null +++ b/board/freescale/m54455evb/config.mk @@ -0,0 +1,25 @@ +# +# (C) Copyright 2000-2003 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# Coldfire contribution by Bernhard Kuhn +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +TEXT_BASE = 0 diff --git a/board/freescale/m54455evb/flash.c b/board/freescale/m54455evb/flash.c new file mode 100644 index 000000000..de2cca863 --- /dev/null +++ b/board/freescale/m54455evb/flash.c @@ -0,0 +1,974 @@ +/* + * (C) Copyright 2000-2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +#include + +#ifndef CFG_FLASH_CFI +typedef unsigned char FLASH_PORT_WIDTH; +typedef volatile unsigned char FLASH_PORT_WIDTHV; + +#define FPW FLASH_PORT_WIDTH +#define FPWV FLASH_PORT_WIDTHV + +#define CFG_FLASH_CFI_WIDTH FLASH_CFI_8BIT +#define CFG_FLASH_NONCFI_WIDTH FLASH_CFI_8BIT + +/* Intel-compatible flash commands */ +#define INTEL_PROGRAM 0x00100010 +#define INTEL_ERASE 0x00200020 +#define INTEL_WRSETUP 0x00400040 +#define INTEL_CLEAR 0x00500050 +#define INTEL_LOCKBIT 0x00600060 +#define INTEL_PROTECT 0x00010001 +#define INTEL_STATUS 0x00700070 +#define INTEL_READID 0x00900090 +#define INTEL_CFIQRY 0x00980098 +#define INTEL_SUSERASE 0x00B000B0 +#define INTEL_PROTPROG 0x00C000C0 +#define INTEL_CONFIRM 0x00D000D0 +#define INTEL_WRBLK 0x00e800e8 +#define INTEL_RESET 0x00FF00FF + +/* Intel-compatible flash status bits */ +#define INTEL_FINISHED 0x00800080 +#define INTEL_OK 0x00800080 +#define INTEL_ERASESUS 0x00600060 +#define INTEL_WSM_SUS (INTEL_FINISHED | INTEL_ERASESUS) + +/* 28F160C3B CFI Data offset - This could vary */ +#define INTEL_CFI_MFG 0x00 /* Manufacturer ID */ +#define INTEL_CFI_PART 0x01 /* Product ID */ +#define INTEL_CFI_LOCK 0x02 /* */ +#define INTEL_CFI_TWPRG 0x1F /* Typical Single Word Program Timeout 2^n us */ +#define INTEL_CFI_MBUFW 0x20 /* Typical Max Buffer Write Timeout 2^n us */ +#define INTEL_CFI_TERB 0x21 /* Typical Block Erase Timeout 2^n ms */ +#define INTEL_CFI_MWPRG 0x23 /* Maximum Word program timeout 2^n us */ +#define INTEL_CFI_MERB 0x25 /* Maximum Block Erase Timeout 2^n s */ +#define INTEL_CFI_SIZE 0x27 /* Device size 2^n bytes */ +#define INTEL_CFI_CAP 0x28 +#define INTEL_CFI_WRBUF 0x2A +#define INTEL_CFI_BANK 0x2C /* Number of Bank */ +#define INTEL_CFI_BLK1A 0x2D /* Number of Blocks */ +#define INTEL_CFI_BLK1B 0x2E /* Number of Blocks */ +#define INTEL_CFI_SZ1A 0x2F /* Block Region Size */ +#define INTEL_CFI_SZ1B 0x30 +#define INTEL_CFI_BLK2A 0x31 +#define INTEL_CFI_BLK2B 0x32 +#define INTEL_CFI_SZ2A 0x33 +#define INTEL_CFI_SZ2B 0x34 + +#define FLASH_CYCLE1 0x0555 +#define FLASH_CYCLE2 0x0aaa + +#define WR_BLOCK 0x20 + +/* not in the flash.h yet */ +#define FLASH_28F64P30T 0x00B9 /* Intel 28F64P30T ( 64M) */ +#define FLASH_28F64P30B 0x00BA /* Intel 28F64P30B ( 64M) */ +#define FLASH_28F128P30T 0x00BB /* Intel 28F128P30T ( 128M = 8M x 16 ) */ +#define FLASH_28F128P30B 0x00BC /* Intel 28F128P30B ( 128M = 8M x 16 ) */ +#define FLASH_28F256P30T 0x00BD /* Intel 28F256P30T ( 256M = 16M x 16 ) */ +#define FLASH_28F256P30B 0x00BE /* Intel 28F256P30B ( 256M = 16M x 16 ) */ + +#define SYNC __asm__("nop") + +/*----------------------------------------------------------------------- + * Functions + */ + +ulong flash_get_size(FPWV * addr, flash_info_t * info); +int flash_get_offsets(ulong base, flash_info_t * info); +int flash_cmd_rd(volatile u16 * addr, int index); +int write_data(flash_info_t * info, ulong dest, FPW data); +int write_data_block(flash_info_t * info, ulong src, ulong dest); +int write_word_atm(flash_info_t * info, volatile u8 * dest, u16 data); +void inline spin_wheel(void); +void flash_sync_real_protect(flash_info_t * info); +uchar intel_sector_protected(flash_info_t * info, ushort sector); + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; + +ulong flash_init(void) +{ + int i; + ulong size = 0; + ulong fbase = 0; + + for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) { + memset(&flash_info[i], 0, sizeof(flash_info_t)); + + switch (i) { + case 0: + fbase = (ulong) CFG_FLASH0_BASE; + break; + case 1: + fbase = (ulong) CFG_FLASH1_BASE; + break; + } + + flash_get_size((FPWV *) fbase, &flash_info[i]); + flash_get_offsets((ulong) fbase, &flash_info[i]); + fbase += flash_info[i].size; + size += flash_info[i].size; + + /* get the h/w and s/w protection status in sync */ + flash_sync_real_protect(&flash_info[i]); + } + + /* Protect monitor and environment sectors */ + flash_protect(FLAG_PROTECT_SET, + CFG_MONITOR_BASE, + CFG_MONITOR_BASE + monitor_flash_len - 1, &flash_info[0]); + + return size; +} + +int flash_get_offsets(ulong base, flash_info_t * info) +{ + int i, j, k; + int sectors, bs, banks; + ulong start; + + if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_ATM) { + int sect[] = CFG_ATMEL_SECT; + int sectsz[] = CFG_ATMEL_SECTSZ; + + info->start[0] = base; + for (k = 0, i = 0; i < CFG_ATMEL_REGION; i++) { + for (j = 0; j < sect[i]; j++, k++) { + info->start[k + 1] = info->start[k] + sectsz[i]; + info->protect[k] = 0; + } + } + } + + if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) { + volatile u16 *addr16 = (volatile u16 *)base; + + *addr16 = (FPW) INTEL_RESET; /* restore read mode */ + *addr16 = (FPW) INTEL_READID; + + banks = addr16[INTEL_CFI_BANK] & 0xff; + + sectors = 0; + info->start[0] = base; + + for (k = 0, i = 0; i < banks; i++) { + /* Geometry y1 = y1 + 1, y2 = y2 + 1, CFI spec. + * To be exact, Z = [0x2f 0x30] (LE) * 256 bytes * [0x2D 0x2E] block count + * Z = [0x33 0x34] (LE) * 256 bytes * [0x31 0x32] block count + */ + bs = ((((addr16[INTEL_CFI_SZ1B + (i * 4)] & 0xff) << 8) + | (addr16[INTEL_CFI_SZ1A + (i * 4)] & 0xff)) * + 0x100); + sectors = + (addr16[INTEL_CFI_BLK1A + (i * 4)] & 0xff) + 1; + + for (j = 0; j < sectors; j++, k++) { + info->start[k + 1] = info->start[k] + bs; + } + } + + *addr16 = (FPW) INTEL_RESET; /* restore read mode */ + } + + return ERR_OK; +} + +void flash_print_info(flash_info_t * info) +{ + int i; + + switch (info->flash_id & FLASH_VENDMASK) { + case FLASH_MAN_INTEL: + printf("INTEL "); + break; + case FLASH_MAN_ATM: + printf("ATMEL "); + break; + default: + printf("Unknown Vendor "); + break; + } + + switch (info->flash_id & FLASH_TYPEMASK) { + case FLASH_AT040: + printf("AT49BV040A\n"); + break; + case FLASH_28F128J3A: + printf("Intel 28F128J3A\n"); + break; + default: + printf("Unknown Chip Type\n"); + return; + } + + if (info->size > 0x100000) { + int remainder; + + printf(" Size: %ld", info->size >> 20); + + remainder = (info->size % 0x100000); + if (remainder) { + remainder >>= 10; + remainder = (int)((float) + (((float)remainder / (float)1024) * + 10000)); + printf(".%d ", remainder); + } + + printf("MB in %d Sectors\n", info->sector_count); + } else + printf(" Size: %ld KB in %d Sectors\n", + info->size >> 10, info->sector_count); + + printf(" Sector Start Addresses:"); + for (i = 0; i < info->sector_count; ++i) { + if ((i % 5) == 0) + printf("\n "); + printf(" %08lX%s", + info->start[i], info->protect[i] ? " (RO)" : " "); + } + printf("\n"); +} + +/* + * The following code cannot be run from FLASH! + */ +ulong flash_get_size(FPWV * addr, flash_info_t * info) +{ + volatile u16 *addr16 = (volatile u16 *)addr; + int intel = 0, banks = 0; + u16 value; + int i; + + addr[FLASH_CYCLE1] = (FPWV) 0x00AA00AA; /* for Atmel, Intel ignores this */ + addr[FLASH_CYCLE2] = (FPWV) 0x00550055; /* for Atmel, Intel ignores this */ + addr[FLASH_CYCLE1] = (FPWV) 0x00900090; /* selects Intel or Atmel */ + + switch (addr[0] & 0xff) { + case (u8) ATM_MANUFACT: + info->flash_id = FLASH_MAN_ATM; + value = addr[1]; + break; + case (u8) INTEL_MANUFACT: + /* Terminate Atmel ID read */ + addr[0] = (FPWV) 0x00F000F0; + /* Write auto select command: read Manufacturer ID */ + /* Write auto select command sequence and test FLASH answer */ + *addr16 = (FPW) INTEL_RESET; /* restore read mode */ + *addr16 = (FPW) INTEL_READID; + + info->flash_id = FLASH_MAN_INTEL; + value = (addr16[INTEL_CFI_MFG] << 8); + value |= addr16[INTEL_CFI_PART] & 0xff; + intel = 1; + break; + default: + printf("Unknown Flash\n"); + info->flash_id = FLASH_UNKNOWN; + info->sector_count = 0; + info->size = 0; + + *addr = (FPW) 0x00F000F0; + *addr = (FPW) INTEL_RESET; /* restore read mode */ + return (0); /* no or unknown flash */ + } + + switch (value) { + case (u8) ATM_ID_LV040: + info->flash_id += FLASH_AT040; + break; + case (u16) INTEL_ID_28F128J3: + info->flash_id += FLASH_28F128J3A; + break; + case (u16) INTEL_ID_28F64P30T: + info->flash_id += FLASH_28F64P30T; + break; + case (u16) INTEL_ID_28F64P30B: + info->flash_id += FLASH_28F64P30B; + break; + case (u16) INTEL_ID_28F128P30T: + info->flash_id += FLASH_28F128P30T; + break; + case (u16) INTEL_ID_28F128P30B: + info->flash_id += FLASH_28F128P30B; + break; + case (u16) INTEL_ID_28F256P30T: + info->flash_id += FLASH_28F256P30T; + break; + case (u16) INTEL_ID_28F256P30B: + info->flash_id += FLASH_28F256P30B; + break; + default: + info->flash_id = FLASH_UNKNOWN; + break; + } + + if (intel) { + /* Intel spec. under CFI section */ + u32 sz; + int sectors, bs; + + banks = addr16[INTEL_CFI_BANK] & 0xff; + + sectors = sz = 0; + for (i = 0; i < banks; i++) { + /* Geometry y1 = y1 + 1, y2 = y2 + 1, CFI spec. + * To be exact, Z = [0x2f 0x30] (LE) * 256 bytes * [0x2D 0x2E] block count + * Z = [0x33 0x34] (LE) * 256 bytes * [0x31 0x32] block count + */ + bs = ((((addr16[INTEL_CFI_SZ1B + (i * 4)] & 0xff) << 8) + | (addr16[INTEL_CFI_SZ1A + (i * 4)] & 0xff)) * + 0x100); + sectors += + (addr16[INTEL_CFI_BLK1A + (i * 4)] & 0xff) + 1; + sz += (bs * sectors); + } + + info->sector_count = sectors; + info->size = sz; + *addr = (FPW) INTEL_RESET; /* restore read mode */ + } else { + int sect[] = CFG_ATMEL_SECT; + int sectsz[] = CFG_ATMEL_SECTSZ; + + info->sector_count = 0; + info->size = 0; + for (i = 0; i < CFG_ATMEL_REGION; i++) { + info->sector_count += sect[i]; + info->size += sect[i] * sectsz[i]; + } + + /* reset ID mode */ + addr[0] = (FPWV) 0x00F000F0; + } + + if (info->sector_count > CFG_MAX_FLASH_SECT) { + printf("** ERROR: sector count %d > max (%d) **\n", + info->sector_count, CFG_MAX_FLASH_SECT); + info->sector_count = CFG_MAX_FLASH_SECT; + } + + return (info->size); +} + +int flash_cmd_rd(volatile u16 * addr, int index) +{ + return (int)addr[index]; +} + +/* + * This function gets the u-boot flash sector protection status + * (flash_info_t.protect[]) in sync with the sector protection + * status stored in hardware. + */ +void flash_sync_real_protect(flash_info_t * info) +{ + int i; + + switch (info->flash_id & FLASH_TYPEMASK) { + case FLASH_28F160C3B: + case FLASH_28F160C3T: + case FLASH_28F320C3B: + case FLASH_28F320C3T: + case FLASH_28F640C3B: + case FLASH_28F640C3T: + for (i = 0; i < info->sector_count; ++i) { + info->protect[i] = intel_sector_protected(info, i); + } + break; + default: + /* no h/w protect support */ + break; + } +} + +/* + * checks if "sector" in bank "info" is protected. Should work on intel + * strata flash chips 28FxxxJ3x in 8-bit mode. + * Returns 1 if sector is protected (or timed-out while trying to read + * protection status), 0 if it is not. + */ +uchar intel_sector_protected(flash_info_t * info, ushort sector) +{ + FPWV *addr; + FPWV *lock_conf_addr; + ulong start; + unsigned char ret; + + /* + * first, wait for the WSM to be finished. The rationale for + * waiting for the WSM to become idle for at most + * CFG_FLASH_ERASE_TOUT is as follows. The WSM can be busy + * because of: (1) erase, (2) program or (3) lock bit + * configuration. So we just wait for the longest timeout of + * the (1)-(3), i.e. the erase timeout. + */ + + /* wait at least 35ns (W12) before issuing Read Status Register */ + /*udelay(1); */ + addr = (FPWV *) info->start[sector]; + *addr = (FPW) INTEL_STATUS; + + start = get_timer(0); + while ((*addr & (FPW) INTEL_FINISHED) != (FPW) INTEL_FINISHED) { + if (get_timer(start) > CFG_FLASH_UNLOCK_TOUT) { + *addr = (FPW) INTEL_RESET; /* restore read mode */ + printf("WSM busy too long, can't get prot status\n"); + return 1; + } + } + + /* issue the Read Identifier Codes command */ + *addr = (FPW) INTEL_READID; + + /* Intel example code uses offset of 4 for 8-bit flash */ + lock_conf_addr = (FPWV *) info->start[sector]; + ret = (lock_conf_addr[INTEL_CFI_LOCK] & (FPW) INTEL_PROTECT) ? 1 : 0; + + /* put flash back in read mode */ + *addr = (FPW) INTEL_RESET; + + return ret; +} + +int flash_erase(flash_info_t * info, int s_first, int s_last) +{ + int flag, prot, sect; + ulong type, start, last; + int rcode = 0, intel = 0; + + if ((s_first < 0) || (s_first > s_last)) { + if (info->flash_id == FLASH_UNKNOWN) + printf("- missing\n"); + else + printf("- no sectors to erase\n"); + return 1; + } + + type = (info->flash_id & FLASH_VENDMASK); + + if (type != (FLASH_MAN_INTEL & FLASH_VENDMASK)) { + if (type != (FLASH_MAN_ATM & FLASH_VENDMASK)) { + type = (info->flash_id & FLASH_VENDMASK); + printf + ("Can't erase unknown flash type %08lx - aborted\n", + info->flash_id); + return 1; + } + } + + if (type == FLASH_MAN_INTEL) + intel = 1; + + prot = 0; + for (sect = s_first; sect <= s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + + if (prot) + printf("- Warning: %d protected sectors will not be erased!\n", + prot); + else + printf("\n"); + + start = get_timer(0); + last = start; + + /* Start erase on unprotected sectors */ + for (sect = s_first; sect <= s_last; sect++) { + if (info->protect[sect] == 0) { /* not protected */ + + FPWV *addr = (FPWV *) (info->start[sect]); + int min = 0; + + printf("."); + + /* arm simple, non interrupt dependent timer */ + start = get_timer(0); + + if (intel) { + *addr = (FPW) INTEL_READID; + min = addr[INTEL_CFI_TERB] & 0xff; + min = 1 << min; /* ms */ + min = (min / info->sector_count) * 1000; + + /* start erase block */ + *addr = (FPW) INTEL_CLEAR; /* clear status register */ + *addr = (FPW) INTEL_ERASE; /* erase setup */ + *addr = (FPW) INTEL_CONFIRM; /* erase confirm */ + + while ((*addr & (FPW) INTEL_FINISHED) != + (FPW) INTEL_FINISHED) { + + if (get_timer(start) > + CFG_FLASH_ERASE_TOUT) { + printf("Timeout\n"); + *addr = (FPW) INTEL_SUSERASE; /* suspend erase */ + *addr = (FPW) INTEL_RESET; /* reset to read mode */ + + rcode = 1; + break; + } + } + + *addr = (FPW) INTEL_RESET; /* resest to read mode */ + } else { + FPWV *base; /* first address in bank */ + FPWV *atmeladdr; + + flag = disable_interrupts(); + + atmeladdr = (FPWV *) addr; /* concatenate to 8 bit */ + base = (FPWV *) (CFG_ATMEL_BASE); /* First sector */ + + base[FLASH_CYCLE1] = (u8) 0x00AA00AA; /* unlock */ + base[FLASH_CYCLE2] = (u8) 0x00550055; /* unlock */ + base[FLASH_CYCLE1] = (u8) 0x00800080; /* erase mode */ + base[FLASH_CYCLE1] = (u8) 0x00AA00AA; /* unlock */ + base[FLASH_CYCLE2] = (u8) 0x00550055; /* unlock */ + *atmeladdr = (u8) 0x00300030; /* erase sector */ + + if (flag) + enable_interrupts(); + + while ((*atmeladdr & (u8) 0x00800080) != + (u8) 0x00800080) { + if (get_timer(start) > + CFG_FLASH_ERASE_TOUT) { + printf("Timeout\n"); + *atmeladdr = (u8) 0x00F000F0; /* reset to read mode */ + + rcode = 1; + break; + } + } + + *atmeladdr = (u8) 0x00F000F0; /* reset to read mode */ + } /* Atmel or Intel */ + } + } + printf(" done\n"); + + return rcode; +} + +int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt) +{ + if (info->flash_id == FLASH_UNKNOWN) + return 4; + + switch (info->flash_id & FLASH_VENDMASK) { + case FLASH_MAN_ATM: + { + u16 data = 0; + int bytes; /* number of bytes to program in current word */ + int left; /* number of bytes left to program */ + int i, res; + + for (left = cnt, res = 0; + left > 0 && res == 0; + addr += sizeof(data), left -= + sizeof(data) - bytes) { + + bytes = addr & (sizeof(data) - 1); + addr &= ~(sizeof(data) - 1); + + /* combine source and destination data so can program + * an entire word of 16 or 32 bits + */ + for (i = 0; i < sizeof(data); i++) { + data <<= 8; + if (i < bytes || i - bytes >= left) + data += *((uchar *) addr + i); + else + data += *src++; + } + + data = (data >> 8) | (data << 8); + res = write_word_atm(info, (FPWV *) addr, data); + } + return res; + } /* case FLASH_MAN_ATM */ + + case FLASH_MAN_INTEL: + { + ulong cp, wp; + u16 data; + int count, i, l, rc, port_width; + + /* get lower word aligned address */ + wp = addr; + port_width = sizeof(FPW); + + /* + * handle unaligned start bytes + */ + if ((l = addr - wp) != 0) { + data = 0; + for (i = 0, cp = wp; i < l; ++i, ++cp) { + data = (data << 8) | (*(uchar *) cp); + } + + for (; i < port_width && cnt > 0; ++i) { + data = (data << 8) | *src++; + --cnt; + ++cp; + } + + for (; cnt == 0 && i < port_width; ++i, ++cp) + data = (data << 8) | (*(uchar *) cp); + + if ((rc = write_data(info, wp, data)) != 0) + return (rc); + + wp += port_width; + } + + if (cnt > WR_BLOCK) { + /* + * handle word aligned part + */ + count = 0; + while (cnt >= WR_BLOCK) { + + if ((rc = + write_data_block(info, + (ulong) src, + wp)) != 0) + return (rc); + + wp += WR_BLOCK; + src += WR_BLOCK; + cnt -= WR_BLOCK; + + if (count++ > 0x800) { + spin_wheel(); + count = 0; + } + } + } + + /* handle word aligned part */ + if (cnt < WR_BLOCK) { + /* + * handle word aligned part + */ + count = 0; + while (cnt >= port_width) { + data = 0; + for (i = 0; i < port_width; ++i) + data = (data << 8) | *src++; + + if ((rc = + write_data(info, + (ulong) ((FPWV *) wp), + (FPW) (data))) != 0) + return (rc); + + wp += port_width; + cnt -= port_width; + if (count++ > 0x800) { + spin_wheel(); + count = 0; + } + } + } + + if (cnt == 0) + return ERR_OK; + + /* + * handle unaligned tail bytes + */ + data = 0; + for (i = 0, cp = wp; i < port_width && cnt > 0; + ++i, ++cp) { + data = (data << 8) | (*src++); + --cnt; + } + for (; i < port_width; ++i, ++cp) { + data = (data << 8) | (*(uchar *) cp); + } + + return write_data(info, (ulong) ((FPWV *) wp), + (FPW) data); + + } /* case FLASH_MAN_INTEL */ + + } /* switch */ + + return ERR_OK; +} + +/*----------------------------------------------------------------------- + * Write a word or halfword to Flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +int write_data_block(flash_info_t * info, ulong src, ulong dest) +{ + FPWV *srcaddr = (FPWV *) src; + FPWV *dstaddr = (FPWV *) dest; + ulong start; + int flag, i; + + /* Check if Flash is (sufficiently) erased */ + for (i = 0; i < WR_BLOCK; i++) + if ((*dstaddr++ & 0xff) != 0xff) { + printf("not erased at %08lx (%lx)\n", + (ulong) dstaddr, *dstaddr); + return (2); + } + + dstaddr = (FPWV *) dest; + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + *dstaddr = (FPW) INTEL_WRBLK; /* write block setup */ + + if (flag) + enable_interrupts(); + + /* arm simple, non interrupt dependent timer */ + start = get_timer(0); + + /* wait while polling the status register */ + while ((*dstaddr & (FPW) INTEL_FINISHED) != (FPW) INTEL_OK) { + if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + *dstaddr = (FPW) INTEL_RESET; /* restore read mode */ + return (1); + } + } + + *dstaddr = (FPW) WR_BLOCK - 1; /* write 32 to buffer */ + for (i = 0; i < WR_BLOCK; i++) + *dstaddr++ = *srcaddr++; + + dstaddr -= 1; + *dstaddr = (FPW) INTEL_CONFIRM; /* write 32 to buffer */ + + /* arm simple, non interrupt dependent timer */ + start = get_timer(0); + + /* wait while polling the status register */ + while ((*dstaddr & (FPW) INTEL_FINISHED) != (FPW) INTEL_OK) { + if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + *dstaddr = (FPW) INTEL_RESET; /* restore read mode */ + return (1); + } + } + + *dstaddr = (FPW) INTEL_RESET; /* restore read mode */ + + return (0); +} + +/*----------------------------------------------------------------------- + * Write a word or halfword to Flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +int write_data(flash_info_t * info, ulong dest, FPW data) +{ + FPWV *addr = (FPWV *) dest; + ulong start; + int flag; + + /* Check if Flash is (sufficiently) erased */ + if ((*addr & data) != data) { + printf("not erased at %08lx (%lx)\n", (ulong) addr, + (ulong) * addr); + return (2); + } + + /* Disable interrupts which might cause a timeout here */ + flag = (int)disable_interrupts(); + + *addr = (FPW) INTEL_CLEAR; + *addr = (FPW) INTEL_RESET; + + *addr = (FPW) INTEL_WRSETUP; /* write setup */ + *addr = data; + + if (flag) + enable_interrupts(); + + /* arm simple, non interrupt dependent timer */ + start = get_timer(0); + + /* wait while polling the status register */ + while ((*addr & (FPW) INTEL_OK) != (FPW) INTEL_OK) { + if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + *addr = (FPW) INTEL_SUSERASE; /* suspend mode */ + *addr = (FPW) INTEL_CLEAR; /* clear status */ + *addr = (FPW) INTEL_RESET; /* reset */ + return (1); + } + } + + *addr = (FPW) INTEL_CLEAR; /* clear status */ + *addr = (FPW) INTEL_RESET; /* restore read mode */ + + return (0); +} + +/*----------------------------------------------------------------------- + * Write a word to Flash for ATMEL FLASH + * A word is 16 bits, whichever the bus width of the flash bank + * (not an individual chip) is. + * + * returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +int write_word_atm(flash_info_t * info, volatile u8 * dest, u16 data) +{ + ulong start; + int flag, i; + int res = 0; /* result, assume success */ + FPWV *base; /* first address in flash bank */ + + /* Check if Flash is (sufficiently) erased */ + if ((*((volatile u16 *)dest) & data) != data) { + return (2); + } + + base = (FPWV *) (CFG_ATMEL_BASE); + + for (i = 0; i < sizeof(u16); i++) { + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + base[FLASH_CYCLE1] = (u8) 0x00AA00AA; /* unlock */ + base[FLASH_CYCLE2] = (u8) 0x00550055; /* unlock */ + base[FLASH_CYCLE1] = (u8) 0x00A000A0; /* selects program mode */ + + *dest = data; /* start programming the data */ + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + start = get_timer(0); + + /* data polling for D7 */ + while (res == 0 + && (*dest & (u8) 0x00800080) != + (data & (u8) 0x00800080)) { + if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + *dest = (u8) 0x00F000F0; /* reset bank */ + res = 1; + } + } + + *dest++ = (u8) 0x00F000F0; /* reset bank */ + data >>= 8; + } + + return (res); +} + +void inline spin_wheel(void) +{ + static int p = 0; + static char w[] = "\\/-"; + + printf("\010%c", w[p]); + (++p == 3) ? (p = 0) : 0; +} + +#ifdef CFG_FLASH_PROTECTION +/*----------------------------------------------------------------------- + */ +int flash_real_protect(flash_info_t * info, long sector, int prot) +{ + int rcode = 0; /* assume success */ + FPWV *addr; /* address of sector */ + FPW value; + + addr = (FPWV *) (info->start[sector]); + + switch (info->flash_id & FLASH_TYPEMASK) { + case FLASH_28F160C3B: + case FLASH_28F160C3T: + case FLASH_28F320C3B: + case FLASH_28F320C3T: + case FLASH_28F640C3B: + case FLASH_28F640C3T: + *addr = (FPW) INTEL_RESET; /* make sure in read mode */ + *addr = (FPW) INTEL_LOCKBIT; /* lock command setup */ + + if (prot) + *addr = (FPW) INTEL_PROTECT; /* lock sector */ + else + *addr = (FPW) INTEL_CONFIRM; /* unlock sector */ + + /* now see if it really is locked/unlocked as requested */ + *addr = (FPW) INTEL_READID; + + /* read sector protection at sector address, (A7 .. A0) = 0x02. + * D0 = 1 for each device if protected. + * If at least one device is protected the sector is marked + * protected, but return failure. Mixed protected and + * unprotected devices within a sector should never happen. + */ + value = addr[2] & (FPW) INTEL_PROTECT; + if (value == 0) + info->protect[sector] = 0; + else if (value == (FPW) INTEL_PROTECT) + info->protect[sector] = 1; + else { + /* error, mixed protected and unprotected */ + rcode = 1; + info->protect[sector] = 1; + } + if (info->protect[sector] != prot) + rcode = 1; /* failed to protect/unprotect as requested */ + + /* reload all protection bits from hardware for now */ + flash_sync_real_protect(info); + break; + + default: + /* no hardware protect that we support */ + info->protect[sector] = prot; + break; + } + + return rcode; +} +#endif +#endif diff --git a/board/freescale/m54455evb/m54455evb.c b/board/freescale/m54455evb/m54455evb.c new file mode 100644 index 000000000..1411a1a4c --- /dev/null +++ b/board/freescale/m54455evb/m54455evb.c @@ -0,0 +1,165 @@ +/* + * (C) Copyright 2000-2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +int checkboard(void) +{ + puts("Board: "); + puts("Freescale M54455 EVB\n"); + return 0; +}; + +long int initdram(int board_type) +{ + volatile sdramc_t *sdram = (volatile sdramc_t *)(MMAP_SDRAM); + volatile gpio_t *gpio = (volatile gpio_t *)(MMAP_GPIO); + u32 dramsize, i; + + dramsize = CFG_SDRAM_SIZE * 0x100000 >> 1; + + for (i = 0x13; i < 0x20; i++) { + if (dramsize == (1 << i)) + break; + } + i--; + + gpio->mscr_sdram = 0xAA; + + sdram->sdcs0 = (CFG_SDRAM_BASE | i); + sdram->sdcs1 = (CFG_SDRAM_BASE1 | i); + + sdram->sdcfg1 = CFG_SDRAM_CFG1; + sdram->sdcfg2 = CFG_SDRAM_CFG2; + + /* Issue PALL */ + sdram->sdcr = CFG_SDRAM_CTRL | 2; + + /* Issue LEMR */ + sdram->sdmr = CFG_SDRAM_EMOD | 0x408; + sdram->sdmr = CFG_SDRAM_MODE | 0x300; + + udelay(500); + + /* Issue PALL */ + sdram->sdcr = CFG_SDRAM_CTRL | 2; + + /* Perform two refresh cycles */ + sdram->sdcr = CFG_SDRAM_CTRL | 4; + sdram->sdcr = CFG_SDRAM_CTRL | 4; + + sdram->sdmr = CFG_SDRAM_MODE | 0x200; + + sdram->sdcr = (CFG_SDRAM_CTRL & ~0x80000000) | 0x10000c00; + + udelay(100); + + return (dramsize << 1); +}; + +int testdram(void) +{ + /* TODO: XXX XXX XXX */ + printf("DRAM test not implemented!\n"); + + return (0); +} + +#if defined(CONFIG_CMD_IDE) +#include + +int ide_preinit(void) +{ + volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; + + gpio->par_fec |= (gpio->par_fec & GPIO_PAR_FEC_FEC1_MASK) | 0x10; + gpio->par_feci2c |= + (gpio->par_feci2c & 0xF0FF) | (GPIO_PAR_FECI2C_MDC1_ATA_DIOR | + GPIO_PAR_FECI2C_MDIO1_ATA_DIOW); + gpio->par_ata |= + (GPIO_PAR_ATA_BUFEN | GPIO_PAR_ATA_CS1 | GPIO_PAR_ATA_CS0 | + GPIO_PAR_ATA_DA2 | GPIO_PAR_ATA_DA1 | GPIO_PAR_ATA_DA0 + | GPIO_PAR_ATA_RESET_RESET | GPIO_PAR_ATA_DMARQ_DMARQ | + GPIO_PAR_ATA_IORDY_IORDY); + gpio->par_pci |= + (GPIO_PAR_PCI_GNT3_ATA_DMACK | GPIO_PAR_PCI_REQ3_ATA_INTRQ); + + return (0); +} + +void ide_set_reset(int idereset) +{ + volatile atac_t *ata = (atac_t *) MMAP_ATA; + long period; + /* t1, t2, t3, t4, t5, t6, t9, tRD, tA */ + int piotms[5][9] = { + {70, 165, 60, 30, 50, 5, 20, 0, 35}, /* PIO 0 */ + {50, 125, 45, 20, 35, 5, 15, 0, 35}, /* PIO 1 */ + {30, 100, 30, 15, 20, 5, 10, 0, 35}, /* PIO 2 */ + {30, 80, 30, 10, 20, 5, 10, 0, 35}, /* PIO 3 */ + {25, 70, 20, 10, 20, 5, 10, 0, 35} + }; /* PIO 4 */ + + if (idereset) { + ata->cr = 0; /* control reset */ + udelay(10000); + } else { +#define CALC_TIMING(t) (t + period - 1) / period + period = 1000000000 / gd->bus_clk; /* period in ns */ + + /*ata->ton = CALC_TIMING (180); */ + ata->t1 = CALC_TIMING(piotms[2][0]); + ata->t2w = CALC_TIMING(piotms[2][1]); + ata->t2r = CALC_TIMING(piotms[2][1]); + ata->ta = CALC_TIMING(piotms[2][8]); + ata->trd = CALC_TIMING(piotms[2][7]); + ata->t4 = CALC_TIMING(piotms[2][3]); + ata->t9 = CALC_TIMING(piotms[2][6]); + + ata->cr = 0x40; /* IORDY enable */ + udelay(200000); + ata->cr |= 0x01; /* IORDY enable */ + } +} +#endif + +#if defined(CONFIG_PCI) +/* + * Initialize PCI devices, report devices found. + */ +static struct pci_controller hose; +extern void pci_mcf5445x_init(struct pci_controller *hose); + +void pci_init_board(void) +{ + pci_mcf5445x_init(&hose); +} +#endif /* CONFIG_PCI */ + diff --git a/board/freescale/m54455evb/mii.c b/board/freescale/m54455evb/mii.c new file mode 100644 index 000000000..c067183aa --- /dev/null +++ b/board/freescale/m54455evb/mii.c @@ -0,0 +1,320 @@ +/* + * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI) +#undef MII_DEBUG +#undef ET_DEBUG + +int fecpin_setclear(struct eth_device *dev, int setclear) +{ + volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; + struct fec_info_s *info = (struct fec_info_s *)dev->priv; + + if (setclear) { + gpio->par_feci2c |= + (GPIO_PAR_FECI2C_MDC0_MDC0 | GPIO_PAR_FECI2C_MDIO0_MDIO0); + + if (info->iobase == CFG_FEC0_IOBASE) + gpio->par_fec |= GPIO_PAR_FEC_FEC0_RMII_GPIO; + else + gpio->par_fec |= GPIO_PAR_FEC_FEC1_RMII_ATA; + } else { + gpio->par_feci2c &= + ~(GPIO_PAR_FECI2C_MDC0_MDC0 | GPIO_PAR_FECI2C_MDIO0_MDIO0); + + if (info->iobase == CFG_FEC0_IOBASE) + gpio->par_fec &= GPIO_PAR_FEC_FEC0_MASK; + else + gpio->par_fec &= GPIO_PAR_FEC_FEC1_MASK; + } + return 0; +} + +#if defined(CFG_DISCOVER_PHY) || defined(CONFIG_CMD_MII) +#include + +/* Make MII read/write commands for the FEC. */ +#define mk_mii_read(ADDR, REG) (0x60020000 | ((ADDR << 23) | (REG & 0x1f) << 18)) + +#define mk_mii_write(ADDR, REG, VAL) (0x50020000 | ((ADDR << 23) | (REG & 0x1f) << 18) | (VAL & 0xffff)) + +/* PHY identification */ +#define PHY_ID_LXT970 0x78100000 /* LXT970 */ +#define PHY_ID_LXT971 0x001378e0 /* LXT971 and 972 */ +#define PHY_ID_82555 0x02a80150 /* Intel 82555 */ +#define PHY_ID_QS6612 0x01814400 /* QS6612 */ +#define PHY_ID_AMD79C784 0x00225610 /* AMD 79C784 */ +#define PHY_ID_LSI80225 0x0016f870 /* LSI 80225 */ +#define PHY_ID_LSI80225B 0x0016f880 /* LSI 80225/B */ +#define PHY_ID_DP83848VV 0x20005C90 /* National 83848 */ +#define PHY_ID_DP83849 0x20005CA2 /* National 82849 */ + +#define STR_ID_LXT970 "LXT970" +#define STR_ID_LXT971 "LXT971" +#define STR_ID_82555 "Intel82555" +#define STR_ID_QS6612 "QS6612" +#define STR_ID_AMD79C784 "AMD79C784" +#define STR_ID_LSI80225 "LSI80225" +#define STR_ID_LSI80225B "LSI80225/B" +#define STR_ID_DP83848VV "N83848" +#define STR_ID_DP83849 "N83849" + +/**************************************************************************** + * mii_init -- Initialize the MII for MII command without ethernet + * This function is a subset of eth_init + **************************************************************************** + */ +void mii_reset(struct fec_info_s *info) +{ + volatile fec_t *fecp = (fec_t *) (info->miibase); + struct eth_device *dev; + int i, miispd; + u16 rst = 0; + + dev = eth_get_dev(); + + miispd = (gd->bus_clk / 1000000) / 5; + fecp->mscr = miispd << 1; + + miiphy_write(dev->name, info->phy_addr, PHY_BMCR, PHY_BMCR_RESET); + for (i = 0; i < FEC_RESET_DELAY; ++i) { + udelay(500); + miiphy_read(dev->name, info->phy_addr, PHY_BMCR, &rst); + if ((rst & PHY_BMCR_RESET) == 0) + break; + } + if (i == FEC_RESET_DELAY) + printf("Mii reset timeout %d\n", i); +} + +/* send command to phy using mii, wait for result */ +uint mii_send(uint mii_cmd) +{ + struct fec_info_s *info; + struct eth_device *dev; + volatile fec_t *ep; + uint mii_reply; + int j = 0; + + /* retrieve from register structure */ + dev = eth_get_dev(); + info = dev->priv; + + ep = (fec_t *) info->miibase; + + ep->mmfr = mii_cmd; /* command to phy */ + + /* wait for mii complete */ + while (!(ep->eir & FEC_EIR_MII) && (j < MCFFEC_TOUT_LOOP)) { + udelay(1); + j++; + } + if (j >= MCFFEC_TOUT_LOOP) { + printf("MII not complete\n"); + return -1; + } + + mii_reply = ep->mmfr; /* result from phy */ + ep->eir = FEC_EIR_MII; /* clear MII complete */ +#ifdef ET_DEBUG + printf("%s[%d] %s: sent=0x%8.8x, reply=0x%8.8x\n", + __FILE__, __LINE__, __FUNCTION__, mii_cmd, mii_reply); +#endif + + return (mii_reply & 0xffff); /* data read from phy */ +} +#endif /* CFG_DISCOVER_PHY || (CONFIG_MII) */ + +#if defined(CFG_DISCOVER_PHY) +int mii_discover_phy(struct eth_device *dev) +{ +#define MAX_PHY_PASSES 11 + struct fec_info_s *info = dev->priv; + int phyaddr, pass; + uint phyno, phytype; + + if (info->phyname_init) + return info->phy_addr; + + phyaddr = -1; /* didn't find a PHY yet */ + for (pass = 1; pass <= MAX_PHY_PASSES && phyaddr < 0; ++pass) { + if (pass > 1) { + /* PHY may need more time to recover from reset. + * The LXT970 needs 50ms typical, no maximum is + * specified, so wait 10ms before try again. + * With 11 passes this gives it 100ms to wake up. + */ + udelay(10000); /* wait 10ms */ + } + + for (phyno = 0; phyno < 32 && phyaddr < 0; ++phyno) { + + phytype = mii_send(mk_mii_read(phyno, PHY_PHYIDR1)); +#ifdef ET_DEBUG + printf("PHY type 0x%x pass %d type\n", phytype, pass); +#endif + if (phytype != 0xffff) { + phyaddr = phyno; + phytype <<= 16; + phytype |= + mii_send(mk_mii_read(phyno, PHY_PHYIDR2)); + + switch (phytype & 0xffffffff) { + case PHY_ID_DP83848VV: + strcpy(info->phy_name, + STR_ID_DP83848VV); + info->phyname_init = 1; + break; + default: + strcpy(info->phy_name, "unknown"); + info->phyname_init = 1; + break; + } + +#ifdef ET_DEBUG + printf("PHY @ 0x%x pass %d type ", phyno, pass); + switch (phytype & 0xffffffff) { + case PHY_ID_DP83848VV: + printf(STR_ID_DP83848VV); + break; + default: + printf("0x%08x\n", phytype); + break; + } +#endif + } + } + } + if (phyaddr < 0) + printf("No PHY device found.\n"); + + return phyaddr; +} +#endif /* CFG_DISCOVER_PHY */ + +int mii_init(void) __attribute__((weak,alias("__mii_init"))); + +void __mii_init(void) +{ + volatile fec_t *fecp; + struct fec_info_s *info; + struct eth_device *dev; + int miispd = 0, i = 0; + u16 autoneg = 0; + + /* retrieve from register structure */ + dev = eth_get_dev(); + info = dev->priv; + + fecp = (fec_t *) info->miibase; + + /* We use strictly polling mode only */ + fecp->eimr = 0; + + /* Clear any pending interrupt */ + fecp->eir = 0xffffffff; + + /* Set MII speed */ + miispd = (gd->bus_clk / 1000000) / 5; + fecp->mscr = miispd << 1; + + info->phy_addr = mii_discover_phy(dev); + +#define AUTONEGLINK (PHY_BMSR_AUTN_COMP | PHY_BMSR_LS) + while (i < MCFFEC_TOUT_LOOP) { + autoneg = 0; + miiphy_read(dev->name, info->phy_addr, PHY_BMSR, &autoneg); + i++; + + if ((autoneg & AUTONEGLINK) == AUTONEGLINK) + break; + + udelay(500); + } + if (i >= MCFFEC_TOUT_LOOP) { + printf("Auto Negotiation not complete\n"); + } + + /* adapt to the half/full speed settings */ + info->dup_spd = miiphy_duplex(dev->name, info->phy_addr) << 16; + info->dup_spd |= miiphy_speed(dev->name, info->phy_addr); +} + +/***************************************************************************** + * Read and write a MII PHY register, routines used by MII Utilities + * + * FIXME: These routines are expected to return 0 on success, but mii_send + * does _not_ return an error code. Maybe 0xFFFF means error, i.e. + * no PHY connected... + * For now always return 0. + * FIXME: These routines only work after calling eth_init() at least once! + * Otherwise they hang in mii_send() !!! Sorry! + *****************************************************************************/ + +int mcffec_miiphy_read(char *devname, unsigned char addr, unsigned char reg, + unsigned short *value) +{ + short rdreg; /* register working value */ + +#ifdef MII_DEBUG + printf("miiphy_read(0x%x) @ 0x%x = ", reg, addr); +#endif + rdreg = mii_send(mk_mii_read(addr, reg)); + + *value = rdreg; + +#ifdef MII_DEBUG + printf("0x%04x\n", *value); +#endif + + return 0; +} + +int mcffec_miiphy_write(char *devname, unsigned char addr, unsigned char reg, + unsigned short value) +{ + short rdreg; /* register working value */ + +#ifdef MII_DEBUG + printf("miiphy_write(0x%x) @ 0x%x = ", reg, addr); +#endif + + rdreg = mii_send(mk_mii_write(addr, reg, value)); + +#ifdef MII_DEBUG + printf("0x%04x\n", value); +#endif + + return 0; +} + +#endif /* CONFIG_CMD_NET, FEC_ENET & NET_MULTI */ diff --git a/board/freescale/m54455evb/u-boot.lds b/board/freescale/m54455evb/u-boot.lds new file mode 100644 index 000000000..bda68e4f8 --- /dev/null +++ b/board/freescale/m54455evb/u-boot.lds @@ -0,0 +1,144 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(m68k) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/mcf5445x/start.o (.text) + lib_m68k/traps.o (.text) + lib_m68k/interrupts.o (.text) + common/dlmalloc.o (.text) + lib_generic/zlib.o (.text) + + . = DEFINED(env_offset) ? env_offset : .; + common/environment.o (.text) + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + + .reloc : + { + __got_start = .; + *(.got) + __got_end = .; + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + _sbss = .; + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + . = ALIGN(4); + _ebss = .; + } + _end = . ; + PROVIDE (end = .); +} diff --git a/common/cmd_bdinfo.c b/common/cmd_bdinfo.c index 889cff841..7686080f3 100644 --- a/common/cmd_bdinfo.c +++ b/common/cmd_bdinfo.c @@ -208,24 +208,36 @@ int do_bdinfo ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) } #elif defined(CONFIG_M68K) /* M68K */ +static void print_str(const char *, const char *); int do_bdinfo ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { int i; bd_t *bd = gd->bd; + char buf[32]; + print_num ("memstart", (ulong)bd->bi_memstart); print_num ("memsize", (ulong)bd->bi_memsize); print_num ("flashstart", (ulong)bd->bi_flashstart); print_num ("flashsize", (ulong)bd->bi_flashsize); print_num ("flashoffset", (ulong)bd->bi_flashoffset); #if defined(CFG_INIT_RAM_ADDR) - print_num ("sramstart", (ulong)bd->bi_sramstart); - print_num ("sramsize", (ulong)bd->bi_sramsize); + print_num ("sramstart", (ulong)bd->bi_sramstart); + print_num ("sramsize", (ulong)bd->bi_sramsize); #endif #if defined(CFG_MBAR) - print_num ("mbar", bd->bi_mbar_base ); + print_num ("mbar", bd->bi_mbar_base); #endif -#if defined(CONFIG_CMD_NET) + print_str ("busfreq", strmhz(buf, bd->bi_busfreq)); +#ifdef CONFIG_PCI + print_str ("pcifreq", strmhz(buf, bd->bi_pcifreq)); +#endif +#ifdef CONFIG_EXTRA_CLOCK + print_str ("flbfreq", strmhz(buf, bd->bi_flbfreq)); + print_str ("inpfreq", strmhz(buf, bd->bi_inpfreq)); + print_str ("vcofreq", strmhz(buf, bd->bi_vcofreq)); +#endif +#if defined(CFG_CMD_NET) puts ("ethaddr ="); for (i=0; i<6; ++i) { printf ("%c%02X", i ? ':' : ' ', bd->bi_enetaddr[i]); @@ -323,7 +335,7 @@ static void print_num(const char *name, ulong value) printf ("%-12s= 0x%08lX\n", name, value); } -#ifdef CONFIG_PPC +#if defined(CONFIG_PPC) || defined(CONFIG_M68K) static void print_str(const char *name, const char *str) { printf ("%-12s= %6s MHz\n", name, str); diff --git a/cpu/mcf5445x/Makefile b/cpu/mcf5445x/Makefile new file mode 100644 index 000000000..26ec29895 --- /dev/null +++ b/cpu/mcf5445x/Makefile @@ -0,0 +1,48 @@ +# +# (C) Copyright 2000-2004 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +# CFLAGS += -DET_DEBUG + +LIB = lib$(CPU).a + +START = start.o +COBJS = cpu.o speed.o cpu_init.o interrupts.o pci.o + +SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) +START := $(addprefix $(obj),$(START)) + +all: $(obj).depend $(START) $(LIB) + +$(LIB): $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +######################################################################### + +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/cpu/mcf5445x/config.mk b/cpu/mcf5445x/config.mk new file mode 100644 index 000000000..d0c72fb6b --- /dev/null +++ b/cpu/mcf5445x/config.mk @@ -0,0 +1,27 @@ +# +# (C) Copyright 2003 Josef Baumgartner +# +# (C) Copyright 2000-2004 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +PLATFORM_RELFLAGS += -ffixed-d7 -msep-data +PLATFORM_CPPFLAGS += -m5407 -fPIC diff --git a/cpu/mcf5445x/cpu.c b/cpu/mcf5445x/cpu.c new file mode 100644 index 000000000..e601b8949 --- /dev/null +++ b/cpu/mcf5445x/cpu.c @@ -0,0 +1,97 @@ +/* + * + * (C) Copyright 2000-2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +#include + +DECLARE_GLOBAL_DATA_PTR; + +int do_reset(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char *argv[]) +{ + volatile rcm_t *rcm = (rcm_t *) (MMAP_RCM); + udelay(1000); + rcm->rcr |= RCM_RCR_SOFTRST; + + /* we don't return! */ + return 0; +}; + +int checkcpu(void) +{ + volatile ccm_t *ccm = (ccm_t *) MMAP_CCM; + u16 msk; + u16 id = 0; + u8 ver; + + puts("CPU: "); + msk = (ccm->cir >> 6); + ver = (ccm->cir & 0x003f); + switch (msk) { + case 0x48: + id = 54455; + break; + case 0x49: + id = 54454; + break; + case 0x4a: + id = 54453; + break; + case 0x4b: + id = 54452; + break; + case 0x4d: + id = 54451; + break; + case 0x4f: + id = 54450; + break; + } + + if (id) { + printf("Freescale MCF%d (Mask:%01x Version:%x)\n", id, msk, + ver); + printf(" CPU CLK %d Mhz BUS CLK %d Mhz FLB CLK %d Mhz\n", + (int)(gd->cpu_clk / 1000000), + (int)(gd->bus_clk / 1000000), + (int)(gd->flb_clk / 1000000)); +#ifdef CONFIG_PCI + printf(" PCI CLK %d Mhz INP CLK %d Mhz VCO CLK %d Mhz\n", + (int)(gd->pci_clk / 1000000), + (int)(gd->inp_clk / 1000000), + (int)(gd->vco_clk / 1000000)); +#else + printf(" INP CLK %d Mhz VCO CLK %d Mhz\n", + (int)(gd->inp_clk / 1000000), + (int)(gd->vco_clk / 1000000)); +#endif + } + + return 0; +} diff --git a/cpu/mcf5445x/cpu_init.c b/cpu/mcf5445x/cpu_init.c new file mode 100644 index 000000000..6622eeea9 --- /dev/null +++ b/cpu/mcf5445x/cpu_init.c @@ -0,0 +1,140 @@ +/* + * + * (C) Copyright 2000-2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * (C) Copyright 2004-2007 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +#include +#include + +/* + * Breath some life into the CPU... + * + * Set up the memory map, + * initialize a bunch of registers, + * initialize the UPM's + */ +void cpu_init_f(void) +{ + volatile scm1_t *scm1 = (scm1_t *) MMAP_SCM1; + volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; + volatile fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS; + + scm1->mpr = 0x77777777; + scm1->pacra = 0; + scm1->pacrb = 0; + scm1->pacrc = 0; + scm1->pacrd = 0; + scm1->pacre = 0; + scm1->pacrf = 0; + scm1->pacrg = 0; + + /* FlexBus */ + gpio->par_be = + GPIO_PAR_BE_BE3_BE3 | GPIO_PAR_BE_BE2_BE2 | GPIO_PAR_BE_BE1_BE1 | + GPIO_PAR_BE_BE0_BE0; + gpio->par_fbctl = + GPIO_PAR_FBCTL_OE | GPIO_PAR_FBCTL_TA_TA | GPIO_PAR_FBCTL_RW_RW | + GPIO_PAR_FBCTL_TS_TS; + +#if (defined(CFG_CS0_BASE) && defined(CFG_CS0_MASK) && defined(CFG_CS0_CTRL)) + fbcs->csar0 = CFG_CS0_BASE; + fbcs->cscr0 = CFG_CS0_CTRL; + fbcs->csmr0 = CFG_CS0_MASK; +#endif + +#if (defined(CFG_CS1_BASE) && defined(CFG_CS1_MASK) && defined(CFG_CS1_CTRL)) + /* Latch chipselect */ + fbcs->csar1 = CFG_CS1_BASE; + fbcs->cscr1 = CFG_CS1_CTRL; + fbcs->csmr1 = CFG_CS1_MASK; +#endif + +#if (defined(CFG_CS2_BASE) && defined(CFG_CS2_MASK) && defined(CFG_CS2_CTRL)) + fbcs->csar2 = CFG_CS2_BASE; + fbcs->cscr2 = CFG_CS2_CTRL; + fbcs->csmr2 = CFG_CS2_MASK; +#endif + +#if (defined(CFG_CS3_BASE) && defined(CFG_CS3_MASK) && defined(CFG_CS3_CTRL)) + fbcs->csar3 = CFG_CS3_BASE; + fbcs->cscr3 = CFG_CS3_CTRL; + fbcs->csmr3 = CFG_CS3_MASK; +#endif + +#if (defined(CFG_CS4_BASE) && defined(CFG_CS4_MASK) && defined(CFG_CS4_CTRL)) + fbcs->csar4 = CFG_CS4_BASE; + fbcs->cscr4 = CFG_CS4_CTRL; + fbcs->csmr4 = CFG_CS4_MASK; +#endif + +#if (defined(CFG_CS5_BASE) && defined(CFG_CS5_MASK) && defined(CFG_CS5_CTRL)) + fbcs->csar5 = CFG_CS5_BASE; + fbcs->cscr5 = CFG_CS5_CTRL; + fbcs->csmr5 = CFG_CS5_MASK; +#endif + +#ifdef CONFIG_FSL_I2C + gpio->par_feci2c = GPIO_PAR_FECI2C_SCL_SCL | GPIO_PAR_FECI2C_SDA_SDA; +#endif + + icache_enable(); +} + +/* + * initialize higher level parts of CPU like timers + */ +int cpu_init_r(void) +{ +#ifdef CONFIG_MCFTMR + volatile rtc_t *rtc = (volatile rtc_t *)(CFG_MCFRTC_BASE); + volatile rtcex_t *rtcex = (volatile rtcex_t *)&rtc->extended; + u32 oscillator = CFG_RTC_OSCILLATOR; + + rtcex->gocu = (CFG_RTC_OSCILLATOR >> 16) & 0xFFFF; + rtcex->gocl = CFG_RTC_OSCILLATOR & 0xFFFF; +#endif + + return (0); +} + +void uart_port_conf(void) +{ + volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; + + /* Setup Ports: */ + switch (CFG_UART_PORT) { + case 0: + gpio->par_uart = + (GPIO_PAR_UART_U0TXD_U0TXD | GPIO_PAR_UART_U0RXD_U0RXD); + break; + case 1: + gpio->par_uart = + (GPIO_PAR_UART_U1TXD_U1TXD | GPIO_PAR_UART_U1RXD_U1RXD); + break; + } +} diff --git a/cpu/mcf5445x/interrupts.c b/cpu/mcf5445x/interrupts.c new file mode 100644 index 000000000..9572a7bc3 --- /dev/null +++ b/cpu/mcf5445x/interrupts.c @@ -0,0 +1,52 @@ +/* + * + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* CPU specific interrupt routine */ +#include +#include + +int interrupt_init(void) +{ + volatile int0_t *intp = (int0_t *) (CFG_INTR_BASE); + + /* Make sure all interrupts are disabled */ + intp->imrh0 |= 0xFFFFFFFF; + intp->imrl0 |= 0xFFFFFFFF; + + enable_interrupts(); + return 0; +} + +#if defined(CONFIG_MCFTMR) +void dtimer_intr_setup(void) +{ + volatile int0_t *intp = (int0_t *) (CFG_INTR_BASE); + + intp->icr0[CFG_TMRINTR_NO] = CFG_TMRINTR_PRI; + intp->imrh0 &= ~CFG_TMRINTR_MASK; +} +#endif diff --git a/cpu/mcf5445x/pci.c b/cpu/mcf5445x/pci.c new file mode 100644 index 000000000..8ace53630 --- /dev/null +++ b/cpu/mcf5445x/pci.c @@ -0,0 +1,189 @@ +/* + * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * PCI Configuration space access support + */ +#include +#include +#include +#include + +#if defined(CONFIG_PCI) +/* System RAM mapped over PCI */ +#define CFG_PCI_SYS_MEM_BUS CFG_SDRAM_BASE +#define CFG_PCI_SYS_MEM_PHYS CFG_SDRAM_BASE +#define CFG_PCI_SYS_MEM_SIZE (1024 * 1024 * 1024) + +#define cfg_read(val, addr, type, op) *val = op((type)(addr)); +#define cfg_write(val, addr, type, op) op((type *)(addr), (val)); + +#define PCI_OP(rw, size, type, op, mask) \ +int pci_##rw##_cfg_##size(struct pci_controller *hose, \ + pci_dev_t dev, int offset, type val) \ +{ \ + u32 addr = 0; \ + u16 cfg_type = 0; \ + addr = ((offset & 0xfc) | cfg_type | (dev) | 0x80000000); \ + out_be32(hose->cfg_addr, addr); \ + __asm__ __volatile__("nop"); \ + cfg_##rw(val, hose->cfg_data + (offset & mask), type, op); \ + out_be32(hose->cfg_addr, addr & 0x7fffffff); \ + __asm__ __volatile__("nop"); \ + return 0; \ +} + +PCI_OP(read, byte, u8 *, in_8, 3) +PCI_OP(read, word, u16 *, in_le16, 2) +PCI_OP(write, byte, u8, out_8, 3) +PCI_OP(write, word, u16, out_le16, 2) +PCI_OP(write, dword, u32, out_le32, 0) + +int pci_read_cfg_dword(struct pci_controller *hose, pci_dev_t dev, + int offset, u32 * val) +{ + u32 addr; + u32 tmpv; + u32 mask = 2; /* word access */ + /* Read lower 16 bits */ + addr = ((offset & 0xfc) | (dev) | 0x80000000); + out_be32(hose->cfg_addr, addr); + __asm__ __volatile__("nop"); + *val = (u32) in_le16((u16 *) (hose->cfg_data + (offset & mask))); + out_be32(hose->cfg_addr, addr & 0x7fffffff); + __asm__ __volatile__("nop"); + + /* Read upper 16 bits */ + offset += 2; + addr = ((offset & 0xfc) | 1 | (dev) | 0x80000000); + out_be32(hose->cfg_addr, addr); + __asm__ __volatile__("nop"); + tmpv = (u32) in_le16((u16 *) (hose->cfg_data + (offset & mask))); + out_be32(hose->cfg_addr, addr & 0x7fffffff); + __asm__ __volatile__("nop"); + + /* combine results into dword value */ + *val = (tmpv << 16) | *val; + + return 0; +} + +void pci_mcf5445x_init(struct pci_controller *hose) +{ + volatile pci_t *pci = (volatile pci_t *)MMAP_PCI; + volatile pciarb_t *pciarb = (volatile pciarb_t *)MMAP_PCIARB; + volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; + u32 barEn = 0; + + pciarb->acr = 0x001f001f; + + /* Set PCIGNT1, PCIREQ1, PCIREQ0/PCIGNTIN, PCIGNT0/PCIREQOUT, + PCIREQ2, PCIGNT2 */ + gpio->par_pci = + GPIO_PAR_PCI_GNT3_GNT3 | GPIO_PAR_PCI_GNT2 | GPIO_PAR_PCI_GNT1 | + GPIO_PAR_PCI_GNT0 | GPIO_PAR_PCI_REQ3_REQ3 | GPIO_PAR_PCI_REQ2 | + GPIO_PAR_PCI_REQ1 | GPIO_PAR_PCI_REQ0; + + pci->tcr1 |= PCI_TCR1_P; + + /* Initiator windows */ + pci->iw0btar = CFG_PCI_MEM_PHYS; + pci->iw1btar = CFG_PCI_IO_PHYS; + pci->iw2btar = CFG_PCI_CFG_PHYS; + + pci->iwcr = + PCI_IWCR_W0C_EN | PCI_IWCR_W1C_EN | PCI_IWCR_W1C_IO | + PCI_IWCR_W2C_EN | PCI_IWCR_W2C_IO; + + /* Enable bus master and mem access */ + pci->scr = PCI_SCR_MW | PCI_SCR_B | PCI_SCR_M; + + /* Cache line size and master latency */ + pci->cr1 = PCI_CR1_CLS(8) | PCI_CR1_LTMR(0xFF); + pci->cr2 = 0; + +#ifdef CFG_PCI_BAR0 + pci->bar0 = PCI_BAR_BAR0(CFG_PCI_BAR0); + pci->tbatr0 = CFG_PCI_TBATR0 | PCI_TBATR_EN; + barEn |= PCI_TCR1_B0E; +#endif +#ifdef CFG_PCI_BAR1 + pci->bar1 = PCI_BAR_BAR1(CFG_PCI_BAR1); + pci->tbatr1 = CFG_PCI_TBATR1 | PCI_TBATR_EN; + barEn |= PCI_TCR1_B1E; +#endif +#ifdef CFG_PCI_BAR2 + pci->bar2 = PCI_BAR_BAR2(CFG_PCI_BAR2); + pci->tbatr2 = CFG_PCI_TBATR2 | PCI_TBATR_EN; + barEn |= PCI_TCR1_B2E; +#endif +#ifdef CFG_PCI_BAR3 + pci->bar3 = PCI_BAR_BAR3(CFG_PCI_BAR3); + pci->tbatr3 = CFG_PCI_TBATR3 | PCI_TBATR_EN; + barEn |= PCI_TCR1_B3E; +#endif +#ifdef CFG_PCI_BAR4 + pci->bar4 = PCI_BAR_BAR4(CFG_PCI_BAR4); + pci->tbatr4 = CFG_PCI_TBATR4 | PCI_TBATR_EN; + barEn |= PCI_TCR1_B4E; +#endif +#ifdef CFG_PCI_BAR5 + pci->bar5 = PCI_BAR_BAR5(CFG_PCI_BAR5); + pci->tbatr5 = CFG_PCI_TBATR5 | PCI_TBATR_EN; + barEn |= PCI_TCR1_B5E; +#endif + + pci->tcr2 = barEn; + + /* Deassert reset bit */ + pci->gscr &= ~PCI_GSCR_PR; + udelay(1000); + + /* Enable PCI bus master support */ + hose->first_busno = 0; + hose->last_busno = 0xff; + + pci_set_region(hose->regions + 0, CFG_PCI_MEM_BUS, CFG_PCI_MEM_PHYS, + CFG_PCI_MEM_SIZE, PCI_REGION_MEM); + + pci_set_region(hose->regions + 1, CFG_PCI_IO_BUS, CFG_PCI_IO_PHYS, + CFG_PCI_IO_SIZE, PCI_REGION_IO); + + pci_set_region(hose->regions + 2, CFG_PCI_SYS_MEM_BUS, + CFG_PCI_SYS_MEM_PHYS, CFG_PCI_SYS_MEM_SIZE, + PCI_REGION_MEM | PCI_REGION_MEMORY); + + hose->region_count = 3; + + hose->cfg_addr = &(pci->car); + hose->cfg_data = (volatile unsigned char *)CFG_PCI_CFG_BUS; + + pci_set_ops(hose, pci_read_cfg_byte, pci_read_cfg_word, + pci_read_cfg_dword, pci_write_cfg_byte, pci_write_cfg_word, + pci_write_cfg_dword); + + /* Hose scan */ + pci_register_hose(hose); + hose->last_busno = pci_hose_scan(hose); +} +#endif /* CONFIG_PCI */ diff --git a/cpu/mcf5445x/speed.c b/cpu/mcf5445x/speed.c new file mode 100644 index 000000000..967becfdd --- /dev/null +++ b/cpu/mcf5445x/speed.c @@ -0,0 +1,186 @@ +/* + * + * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +#include + +DECLARE_GLOBAL_DATA_PTR; + +/* + * Low Power Divider specifications + */ +#define CLOCK_LPD_MIN (1 << 0) /* Divider (decoded) */ +#define CLOCK_LPD_MAX (1 << 15) /* Divider (decoded) */ + +#define CLOCK_PLL_FVCO_MAX 540000000 +#define CLOCK_PLL_FVCO_MIN 300000000 + +#define CLOCK_PLL_FSYS_MAX 266666666 +#define CLOCK_PLL_FSYS_MIN 100000000 +#define MHZ 1000000 + +void clock_enter_limp(int lpdiv) +{ + volatile ccm_t *ccm = (volatile ccm_t *)MMAP_CCM; + int i, j; + + /* Check bounds of divider */ + if (lpdiv < CLOCK_LPD_MIN) + lpdiv = CLOCK_LPD_MIN; + if (lpdiv > CLOCK_LPD_MAX) + lpdiv = CLOCK_LPD_MAX; + + /* Round divider down to nearest power of two */ + for (i = 0, j = lpdiv; j != 1; j >>= 1, i++) ; + + /* Apply the divider to the system clock */ + ccm->cdr = (ccm->cdr & 0xF0FF) | CCM_CDR_LPDIV(i); + + /* Enable Limp Mode */ + ccm->misccr |= CCM_MISCCR_LIMP; +} + +/* + * brief Exit Limp mode + * warning The PLL should be set and locked prior to exiting Limp mode + */ +void clock_exit_limp(void) +{ + volatile ccm_t *ccm = (volatile ccm_t *)MMAP_CCM; + volatile pll_t *pll = (volatile pll_t *)MMAP_PLL; + + /* Exit Limp mode */ + ccm->misccr &= ~CCM_MISCCR_LIMP; + + /* Wait for the PLL to lock */ + while (!(pll->psr & PLL_PSR_LOCK)) ; +} + +/* + * get_clocks() fills in gd->cpu_clock and gd->bus_clk + */ +int get_clocks(void) +{ + volatile ccm_t *ccm = (volatile ccm_t *)MMAP_CCM; + volatile pll_t *pll = (volatile pll_t *)MMAP_PLL; + volatile u8 *cpld = (volatile u8 *)(CFG_CS2_BASE + 3); + volatile u8 *fpga = (volatile u8 *)(CFG_CS3_BASE + 14); + int pllmult_nopci[] = { 20, 10, 24, 18, 12, 6, 16, 8 }; + int pllmult_pci[] = { 12, 6, 16, 8 }; + int vco, bPci, temp, fbtemp, pcrvalue; + int *pPllmult = NULL; + u16 fbpll_mask; + u8 cpldmode; + + /* To determine PCI is present or not */ + if (((ccm->ccr & CCM_CCR_360_FBCONFIG_MASK) == 0x00e0) || + ((ccm->ccr & CCM_CCR_360_FBCONFIG_MASK) == 0x0060)) { + pPllmult = &pllmult_pci[0]; + fbpll_mask = 3; + bPci = 1; + } else { + pPllmult = &pllmult_nopci[0]; + fbpll_mask = 7; +#ifdef CONFIG_PCI + gd->pci_clk = 0; +#endif + bPci = 0; + } + +#ifdef CONFIG_M54455EVB + /* Temporary place here, belongs in board/freescale/... */ + /* Temporary read from CCR- fixed fb issue, must be the same clock + as pci or input clock, causing cpld/fpga read inconsistancy */ + fbtemp = pPllmult[ccm->ccr & fbpll_mask]; + + /* Break down into small pieces, code still in flex bus */ + pcrvalue = pll->pcr & 0xFFFFF0FF; + temp = fbtemp - 1; + pcrvalue |= PLL_PCR_OUTDIV3(temp); + + pll->pcr = pcrvalue; + + cpldmode = *cpld & 0x03; + if (cpldmode == 0) { + /* RCON mode */ + vco = pPllmult[ccm->rcon & fbpll_mask] * CFG_INPUT_CLKSRC; + + if ((vco < CLOCK_PLL_FVCO_MIN) || (vco > CLOCK_PLL_FVCO_MAX)) { + /* invaild range, re-set in PCR */ + int temp = ((pll->pcr & PLL_PCR_OUTDIV2_MASK) >> 4) + 1; + int i, j, bus; + + j = (pll->pcr & 0xFF000000) >> 24; + for (i = j; i < 0xFF; i++) { + vco = i * CFG_INPUT_CLKSRC; + if (vco >= CLOCK_PLL_FVCO_MIN) { + bus = vco / temp; + if (bus <= CLOCK_PLL_FSYS_MIN - MHZ) + continue; + else + break; + } + } + pcrvalue = pll->pcr & 0x00FF00FF; + fbtemp = ((i - 1) << 8) | ((i - 1) << 12); + pcrvalue |= ((i << 24) | fbtemp); + + pll->pcr = pcrvalue; + } + gd->vco_clk = vco; /* Vco clock */ + } else if (cpldmode == 2) { + /* Normal mode */ + vco = pPllmult[ccm->ccr & fbpll_mask] * CFG_INPUT_CLKSRC; + gd->vco_clk = vco; /* Vco clock */ + } else if (cpldmode == 3) { + /* serial mode */ + } +#endif /* CONFIG_M54455EVB */ + + if ((ccm->ccr & CCM_MISCCR_LIMP) == CCM_MISCCR_LIMP) { + /* Limp mode */ + } else { + gd->inp_clk = CFG_INPUT_CLKSRC; /* Input clock */ + + temp = (pll->pcr & PLL_PCR_OUTDIV1_MASK) + 1; + gd->cpu_clk = vco / temp; /* cpu clock */ + + temp = ((pll->pcr & PLL_PCR_OUTDIV2_MASK) >> 4) + 1; + gd->bus_clk = vco / temp; /* bus clock */ + + temp = ((pll->pcr & PLL_PCR_OUTDIV3_MASK) >> 8) + 1; + gd->flb_clk = vco / temp; /* FlexBus clock */ + +#ifdef CONFIG_PCI + if (bPci) { + temp = ((pll->pcr & PLL_PCR_OUTDIV4_MASK) >> 12) + 1; + gd->pci_clk = vco / temp; /* PCI clock */ + } +#endif + } + + return (0); +} diff --git a/cpu/mcf5445x/start.S b/cpu/mcf5445x/start.S new file mode 100644 index 000000000..cd989ab62 --- /dev/null +++ b/cpu/mcf5445x/start.S @@ -0,0 +1,388 @@ +/* + * Copyright (C) 2003 Josef Baumgartner + * Based on code from Bernhard Kuhn + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include "version.h" + +#ifndef CONFIG_IDENT_STRING +#define CONFIG_IDENT_STRING "" +#endif + +/* last three long word reserved for cache status */ +#define CACR_STATUS (CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END-12) +#define ICACHE_STATUS (CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END- 8) +#define DCACHE_STATUS (CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END- 4) + +#define _START _start +#define _FAULT _fault + +#define SAVE_ALL \ + move.w #0x2700,%sr; /* disable intrs */ \ + subl #60,%sp; /* space for 15 regs */ \ + moveml %d0-%d7/%a0-%a6,%sp@; + +#define RESTORE_ALL \ + moveml %sp@,%d0-%d7/%a0-%a6; \ + addl #60,%sp; /* space for 15 regs */ \ + rte; + +.text +/* + * Vector table. This is used for initial platform startup. + * These vectors are to catch any un-intended traps. + */ +_vectors: + +INITSP: .long 0x00000000 /* Initial SP */ +INITPC: .long _START /* Initial PC */ +vector02: .long _FAULT /* Access Error */ +vector03: .long _FAULT /* Address Error */ +vector04: .long _FAULT /* Illegal Instruction */ +vector05: .long _FAULT /* Reserved */ +vector06: .long _FAULT /* Reserved */ +vector07: .long _FAULT /* Reserved */ +vector08: .long _FAULT /* Privilege Violation */ +vector09: .long _FAULT /* Trace */ +vector0A: .long _FAULT /* Unimplemented A-Line */ +vector0B: .long _FAULT /* Unimplemented F-Line */ +vector0C: .long _FAULT /* Debug Interrupt */ +vector0D: .long _FAULT /* Reserved */ +vector0E: .long _FAULT /* Format Error */ +vector0F: .long _FAULT /* Unitialized Int. */ + +/* Reserved */ +vector10_17: +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT + +vector18: .long _FAULT /* Spurious Interrupt */ +vector19: .long _FAULT /* Autovector Level 1 */ +vector1A: .long _FAULT /* Autovector Level 2 */ +vector1B: .long _FAULT /* Autovector Level 3 */ +vector1C: .long _FAULT /* Autovector Level 4 */ +vector1D: .long _FAULT /* Autovector Level 5 */ +vector1E: .long _FAULT /* Autovector Level 6 */ +vector1F: .long _FAULT /* Autovector Level 7 */ + +/* TRAP #0 - #15 */ +vector20_2F: +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT + +/* Reserved */ +vector30_3F: +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT + +vector64_127: +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT + +vector128_191: +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT + +vector192_255: +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT + + .text + + .globl _start +_start: + nop + nop + move.w #0x2700,%sr /* Mask off Interrupt */ + + /* Set vector base register at the beginning of the Flash */ + move.l #CFG_FLASH_BASE, %d0 + movec %d0, %VBR + + move.l #(CFG_INIT_RAM_ADDR + CFG_INIT_RAM_CTRL), %d0 + movec %d0, %RAMBAR0 + + /* initialize general use internal ram */ + move.l #0, %d0 + move.l #(CACR_STATUS), %a1 /* CACR */ + move.l #(ICACHE_STATUS), %a2 /* icache */ + move.l #(DCACHE_STATUS), %a3 /* dcache */ + move.l %d0, (%a1) + move.l %d0, (%a2) + move.l %d0, (%a3) + + /* invalidate and disable cache */ + move.l #0x01004100, %d0 /* Invalidate cache cmd */ + movec %d0, %CACR /* Invalidate cache */ + move.l #0, %d0 + movec %d0, %ACR0 + movec %d0, %ACR1 + movec %d0, %ACR2 + movec %d0, %ACR3 + + /* set stackpointer to end of internal ram to get some stackspace for + the first c-code */ + move.l #(CFG_INIT_RAM_ADDR + CFG_INIT_SP_OFFSET), %sp + clr.l %sp@- + + move.l #__got_start, %a5 /* put relocation table address to a5 */ + + bsr cpu_init_f /* run low-level CPU init code (from flash) */ + bsr board_init_f /* run low-level board init code (from flash) */ + + /* board_init_f() does not return */ + +/*------------------------------------------------------------------------------*/ + +/* + * void relocate_code (addr_sp, gd, addr_moni) + * + * This "function" does not return, instead it continues in RAM + * after relocating the monitor code. + * + * r3 = dest + * r4 = src + * r5 = length in bytes + * r6 = cachelinesize + */ + .globl relocate_code +relocate_code: + link.w %a6,#0 + move.l 8(%a6), %sp /* set new stack pointer */ + + move.l 12(%a6), %d0 /* Save copy of Global Data pointer */ + move.l 16(%a6), %a0 /* Save copy of Destination Address */ + + move.l #CFG_MONITOR_BASE, %a1 + move.l #__init_end, %a2 + move.l %a0, %a3 + + /* copy the code to RAM */ +1: + move.l (%a1)+, (%a3)+ + cmp.l %a1,%a2 + bgt.s 1b + +/* + * We are done. Do not return, instead branch to second part of board + * initialization, now running from RAM. + */ + move.l %a0, %a1 + add.l #(in_ram - CFG_MONITOR_BASE), %a1 + jmp (%a1) + +in_ram: + +clear_bss: + /* + * Now clear BSS segment + */ + move.l %a0, %a1 + add.l #(_sbss - CFG_MONITOR_BASE),%a1 + move.l %a0, %d1 + add.l #(_ebss - CFG_MONITOR_BASE),%d1 +6: + clr.l (%a1)+ + cmp.l %a1,%d1 + bgt.s 6b + + /* + * fix got table in RAM + */ + move.l %a0, %a1 + add.l #(__got_start - CFG_MONITOR_BASE),%a1 + move.l %a1,%a5 /* * fix got pointer register a5 */ + + move.l %a0, %a2 + add.l #(__got_end - CFG_MONITOR_BASE),%a2 + +7: + move.l (%a1),%d1 + sub.l #_start,%d1 + add.l %a0,%d1 + move.l %d1,(%a1)+ + cmp.l %a2, %a1 + bne 7b + + /* calculate relative jump to board_init_r in ram */ + move.l %a0, %a1 + add.l #(board_init_r - CFG_MONITOR_BASE), %a1 + + /* set parameters for board_init_r */ + move.l %a0,-(%sp) /* dest_addr */ + move.l %d0,-(%sp) /* gd */ + jsr (%a1) + +/*------------------------------------------------------------------------------*/ +/* exception code */ + .globl _fault +_fault: + jmp _fault + .globl _exc_handler + +_exc_handler: + SAVE_ALL + movel %sp,%sp@- + bsr exc_handler + addql #4,%sp + RESTORE_ALL + + .globl _int_handler +_int_handler: + SAVE_ALL + movel %sp,%sp@- + bsr int_handler + addql #4,%sp + RESTORE_ALL + +/*------------------------------------------------------------------------------*/ +/* cache functions */ + .globl icache_enable +icache_enable: + move.l #(CACR_STATUS), %a1 /* read CACR Status */ + move.l (%a1), %d1 + + move.l #0x00040100, %d0 /* Invalidate icache */ + or.l %d1, %d0 + movec %d0, %CACR + + move.l #(CFG_SDRAM_BASE + 0xc000), %d0 /* Setup icache */ + movec %d0, %ACR2 + + or.l #0x00088400, %d1 /* Enable bcache and icache */ + movec %d1, %CACR + + move.l #(ICACHE_STATUS), %a1 + moveq #1, %d0 + move.l %d0, (%a1) + rts + + .globl icache_disable +icache_disable: + move.l #(CACR_STATUS), %a1 /* read CACR Status */ + move.l (%a1), %d0 + + and.l #0xFFF77BFF, %d0 + or.l #0x00040100, %d0 /* Setup cache mask */ + movec %d0, %CACR /* Invalidate icache */ + clr.l %d0 + movec %d0, %ACR2 + movec %d0, %ACR3 + + move.l #(ICACHE_STATUS), %a1 + moveq #0, %d0 + move.l %d0, (%a1) + rts + + .globl icache_status +icache_status: + move.l #(ICACHE_STATUS), %a1 + move.l (%a1), %d0 + rts + + .globl icache_invalid +icache_invalid: + move.l #(CACR_STATUS), %a1 /* read CACR Status */ + move.l (%a1), %d0 + + or.l #0x00040100, %d0 /* Invalidate icache */ + movec %d0, %CACR /* Enable and invalidate cache */ + rts + + .globl dcache_enable +dcache_enable: + move.l #(CACR_STATUS), %a1 /* read CACR Status */ + move.l (%a1), %d1 + + move.l #0x01000000, %d0 + or.l %d1, %d0 + movec %d0, %CACR /* Invalidate dcache */ + + move.l #(CFG_SDRAM_BASE + 0xc000), %d0 + movec %d0, %ACR0 + move.l #0, %d0 + movec %d0, %ACR1 + + or.l #0x80000000, %d1 /* Enable bcache and icache */ + movec %d1, %CACR + + move.l #(DCACHE_STATUS), %a1 + moveq #1, %d0 + move.l %d0, (%a1) + rts + + .globl dcache_disable +dcache_disable: + move.l #(CACR_STATUS), %a1 /* read CACR Status */ + move.l (%a1), %d0 + + and.l #0x7FFFFFFF, %d0 + or.l #0x01000000, %d0 /* Setup cache mask */ + movec %d0, %CACR /* Disable dcache */ + clr.l %d0 + movec %d0, %ACR0 + movec %d0, %ACR1 + + move.l #(DCACHE_STATUS), %a1 + moveq #0, %d0 + move.l %d0, (%a1) + rts + + .globl dcache_invalid +dcache_invalid: + move.l #(CACR_STATUS), %a1 /* read CACR Status */ + move.l (%a1), %d0 + + or.l #0x01000000, %d0 /* Setup cache mask */ + movec %d0, %CACR /* Enable and invalidate cache */ + rts + + .globl dcache_status +dcache_status: + move.l #(DCACHE_STATUS), %a1 + move.l (%a1), %d0 + rts + +/*------------------------------------------------------------------------------*/ + + .globl version_string +version_string: + .ascii U_BOOT_VERSION + .ascii " (", __DATE__, " - ", __TIME__, ")" + .ascii CONFIG_IDENT_STRING, "\0" diff --git a/doc/README.m54455evb b/doc/README.m54455evb new file mode 100644 index 000000000..c768fc8a4 --- /dev/null +++ b/doc/README.m54455evb @@ -0,0 +1,416 @@ +Freescale MCF54455EVB ColdFire Development Board +================================================ + +TsiChung Liew(Tsi-Chung.Liew@freescale.com) +Created 4/08/07 +=========================================== + + +Changed files: +============== + +- board/freescale/m54455evb/m54455evb.c Dram setup, IDE pre init, and PCI init +- board/freescale/m54455evb/flash.c Atmel and INTEL flash support +- board/freescale/m54455evb/Makefile Makefile +- board/freescale/m54455evb/config.mk config make +- board/freescale/m54455evb/u-boot.lds Linker description + +- common/cmd_bdinfo.c Clock frequencies output +- common/cmd_mii.c mii support + +- cpu/mcf5445x/cpu.c cpu specific code +- cpu/mcf5445x/cpu_init.c Flexbus ChipSelect, Mux pins setup, icache and RTC extra regs +- cpu/mcf5445x/interrupts.c cpu specific interrupt support +- cpu/mcf5445x/speed.c system, pci, flexbus, and cpu clock +- cpu/mcf5445x/Makefile Makefile +- cpu/mcf5445x/config.mk config make +- cpu/mcf5445x/start.S start up assembly code + +- doc/README.m54455evb This readme file + +- drivers/net/mcffec.c ColdFire common FEC driver +- drivers/serial/mcfuart.c ColdFire common UART driver + +- include/asm-m68k/bitops.h Bit operation function export +- include/asm-m68k/byteorder.h Byte order functions +- include/asm-m68k/fec.h FEC structure and definition +- include/asm-m68k/fsl_i2c.h I2C structure and definition +- include/asm-m68k/global_data.h Global data structure +- include/asm-m68k/immap.h ColdFire specific header file and driver macros +- include/asm-m68k/immap_5445x.h mcf5445x specific header file +- include/asm-m68k/io.h io functions +- include/asm-m68k/m5445x.h mcf5445x specific header file +- include/asm-m68k/posix_types.h Posix +- include/asm-m68k/processor.h header file +- include/asm-m68k/ptrace.h Exception structure +- include/asm-m68k/rtc.h Realtime clock header file +- include/asm-m68k/string.h String function export +- include/asm-m68k/timer.h Timer structure and definition +- include/asm-m68k/types.h Data types definition +- include/asm-m68k/uart.h Uart structure and definition +- include/asm-m68k/u-boot.h u-boot structure + +- include/configs/M54455EVB.h Board specific configuration file + +- lib_m68k/board.c board init function +- lib_m68k/cache.c +- lib_m68k/interrupts Coldfire common interrupt functions +- lib_m68k/m68k_linux.c +- lib_m68k/time.c Timer functions (Dma timer and PIT) +- lib_m68k/traps.c Exception init code + +- rtc/mcfrtc.c Realtime clock Driver + +1 MCF5445x specific Options/Settings +==================================== +1.1 pre-loader is no longer suppoer in thie coldfire family + +1.2 Configuration settings for M54455EVB Development Board +CONFIG_MCF5445x -- define for all MCF5445x CPUs +CONFIG_M54455 -- define for all Freescale MCF54455 CPUs +CONFIG_M54455EVB -- define for M54455EVB board + +CONFIG_MCFUART -- define to use common CF Uart driver +CFG_UART_PORT -- define UART port number, start with 0, 1 and 2 +CONFIG_BAUDRATE -- define UART baudrate + +CONFIG_MCFRTC -- define to use common CF RTC driver +CFG_MCFRTC_BASE -- provide base address for RTC in immap.h +CFG_RTC_OSCILLATOR -- define RTC clock frequency +RTC_DEBUG -- define to show RTC debug message +CFG_CMD_DATE -- enable to use date feature in u-boot + +CONFIG_MCFFEC -- define to use common CF FEC driver +CONFIG_NET_MULTI -- define to use multi FEC in u-boot +CONFIG_MII -- enable to use MII driver +CONFIG_CF_DOMII -- enable to use MII feature in cmd_mii.c +CFG_DISCOVER_PHY -- enable PHY discovery +CFG_RX_ETH_BUFFER -- Set FEC Receive buffer +CFG_FAULT_ECHO_LINK_DOWN-- +CFG_FEC0_PINMUX -- Set FEC0 Pin configuration +CFG_FEC1_PINMUX -- Set FEC1 Pin configuration +CFG_FEC0_MIIBASE -- Set FEC0 MII base register +CFG_FEC1_MIIBASE -- Set FEC0 MII base register +MCFFEC_TOUT_LOOP -- set FEC timeout loop +CONFIG_HAS_ETH1 -- define to enable second FEC in u-boot + +CONFIG_ISO_PARTITION -- enable ISO read/write +CONFIG_DOS_PARTITION -- enable DOS read/write +CONFIG_IDE_RESET -- define ide_reset() +CONFIG_IDE_PREINIT -- define ide_preinit() +CONFIG_ATAPI -- define ATAPI support +CONFIG_LBA48 -- define LBA48 (larger than 120GB) support +CFG_IDE_MAXBUS -- define max channel +CFG_IDE_MAXDEVICE -- define max devices per channel +CFG_ATA_BASE_ADDR -- define ATA base address +CFG_ATA_IDE0_OFFSET -- define ATA IDE0 offset +CFG_ATA_DATA_OFFSET -- define ATA data IO +CFG_ATA_REG_OFFSET -- define for normal register accesses +CFG_ATA_ALT_OFFSET -- define for alternate registers +CFG_ATA_STRIDE -- define for Interval between registers +_IO_BASE -- define for IO base address + +CONFIG_MCFTMR -- define to use DMA timer +CONFIG_MCFPIT -- define to use PIT timer + +CONFIG_FSL_I2C -- define to use FSL common I2C driver +CONFIG_HARD_I2C -- define for I2C hardware support +CONFIG_SOFT_I2C -- define for I2C bit-banged +CFG_I2C_SPEED -- define for I2C speed +CFG_I2C_SLAVE -- define for I2C slave address +CFG_I2C_OFFSET -- define for I2C base address offset +CFG_IMMR -- define for MBAR offset + +CONFIG_PCI -- define for PCI support +CONFIG_PCI_PNP -- define for Plug n play support +CFG_PCI_MEM_BUS -- PCI memory logical offset +CFG_PCI_MEM_PHYS -- PCI memory physical offset +CFG_PCI_MEM_SIZE -- PCI memory size +CFG_PCI_IO_BUS -- PCI IO logical offset +CFG_PCI_IO_PHYS -- PCI IO physical offset +CFG_PCI_IO_SIZE -- PCI IO size +CFG_PCI_CFG_BUS -- PCI Configuration logical offset +CFG_PCI_CFG_PHYS -- PCI Configuration physical offset +CFG_PCI_CFG_SIZE -- PCI Configuration size + +CONFIG_EXTRA_CLOCK -- Enable extra clock such as vco, flexbus, pci, etc + +CFG_MBAR -- define MBAR offset + +CFG_ATMEL_BOOT -- To determine the u-boot is booted from Atmel or Intel + +CONFIG_MONITOR_IS_IN_RAM -- Not support + +CFG_INIT_RAM_ADDR -- defines the base address of the MCF54455 internal SRAM + +CFG_CSn_BASE -- defines the Chip Select Base register +CFG_CSn_MASK -- defines the Chip Select Mask register +CFG_CSn_CTRL -- defines the Chip Select Control register + +CFG_ATMEL_BASE -- defines the Atmel Flash base +CFG_INTEL_BASE -- defines the Intel Flash base + +CFG_SDRAM_BASE -- defines the DRAM Base +CFG_SDRAM_BASE1 -- defines the DRAM Base 1 + +2. MEMORY MAP UNDER U-BOOT AND LINUX KERNEL +=========================================== +2.1. System memory map: + Flash: 0x00000000-0x3FFFFFFF (1024MB) + DDR: 0x40000000-0x7FFFFFFF (1024MB) + SRAM: 0x80000000-0x8FFFFFFF (256MB) + ATA: 0x90000000-0x9FFFFFFF (256MB) + PCI: 0xA0000000-0xBFFFFFFF (512MB) + FlexBus: 0xC0000000-0xDFFFFFFF (512MB) + IP: 0xF0000000-0xFFFFFFFF (256MB) + +2.2. For the initial bringup, we adopted a consistent memory scheme between u-boot and + linux kernel, you can customize it based on your system requirements: + Atmel boot: + Flash0: 0x00000000-0x0007FFFF (512KB) + Flash1: 0x04000000-0x05FFFFFF (32MB) + Intel boot: + Flash0: 0x00000000-0x01FFFFFF (32MB) + Flash1: 0x04000000-0x0407FFFF (512KB) + + CPLD: 0x08000000-0x08FFFFFF (16MB) + FPGA: 0x09000000-0x09FFFFFF (16MB) + DDR: 0x40000000-0x4FFFFFFF (256MB) + SRAM: 0x80000000-0x80007FFF (32KB) + IP: 0xFC000000-0xFC0FFFFF (64KB) + +3. SWITCH SETTINGS +================== +3.1 SW1 Pin3: 0 - Boot from Atmel or 1 - INTEL + SW1 Pin4: 0 - ULPI chip not in reset state or 1 - ULPI chip in reset state + SW1 Pin5: 0 - Full ATA Bus enabled, FEC Phy1 powered down + 1 - Upper 8 bits ATA data bus disabled, FEC PHY1 active + SW1 Pin6: 0 - FEC Phy0 active or 1 - FEC Phy0 powered down + SW1 Pin3: 0 - Boot from Atmel or 1 - INTEL + +4. COMPILATION +============== +4.1 To create U-Boot the gcc-4.1-32 compiler set (ColdFire ELF version) +from codesourcery.com was used. Download it from: +http://www.codesourcery.com/gnu_toolchains/coldfire/download.html + +4.2 Compilation + export CROSS_COMPILE=cross-compile-prefix + cd u-boot-1.x.x + make distclean + make M54455EVB_config, or - default to atmel 33Mhz input clock + make M54455EVB_atmel_config, or - default to atmel 33Mhz input clock + make M54455EVB_a33_config, or - default to atmel 33Mhz input clock + make M54455EVB_a66_config, or - default to atmel 66Mhz input clock + make M54455EVB_intel_config, or - default to intel 33Mhz input clock + make M54455EVB_i33_config, or - default to intel 33Mhz input clock + make M54455EVB_i66_config, or - default to intel 66Mhz input clock + make + +5. SCREEN DUMP +============== +5.1 M54455EVB Development board + Boot from Atmel (NOTE: May not show exactly the same) + +U-Boot 1.2.0-g98c80b46-dirty (Jul 26 2007 - 12:44:08) + +CPU: Freescale MCF54455 (Mask:48 Version:1) + CPU CLK 266 Mhz BUS CLK 133 Mhz FLB CLK 66 Mhz + PCI CLK 33 Mhz INP CLK 33 Mhz VCO CLK 533 Mhz +Board: Freescale M54455 EVB +I2C: ready +DRAM: 256 MB +FLASH: 16.5 MB +In: serial +Out: serial +Err: serial +Net: FEC0, FEC1 +IDE: Bus 0: not available +-> print +bootargs=root=/dev/ram rw +bootdelay=1 +baudrate=115200 +ethaddr=00:e0:0c:bc:e5:60 +eth1addr=00:e0:0c:bc:e5:61 +hostname=M54455EVB +netdev=eth0 +inpclk=33333333 +loadaddr=40010000 +load=tftp ${loadaddr) ${u-boot} +upd=run load; run prog +prog=prot off 0 2ffff;era 0 2ffff;cp.b ${loadaddr} 0 ${filesize};save +ethact=FEC0 +mtdids=nor0=M54455EVB-1 +mtdparts=M54455EVB-1:16m(user) +u-boot=u-boot54455.bin +filesize=292b4 +fileaddr=40010000 +gatewayip=192.168.1.1 +netmask=255.255.255.0 +ipaddr=192.168.1.3 +serverip=192.168.1.2 +stdin=serial +stdout=serial +stderr=serial +mem=261632k + +Environment size: 563/8188 bytes +-> bdinfo +memstart = 0x40000000 +memsize = 0x10000000 +flashstart = 0x00000000 +flashsize = 0x01080000 +flashoffset = 0x00000000 +sramstart = 0x80000000 +sramsize = 0x00008000 +mbar = 0xFC000000 +busfreq = 133.333 MHz +pcifreq = 33.333 MHz +flbfreq = 66.666 MHz +inpfreq = 33.333 MHz +vcofreq = 533.333 MHz +ethaddr = 00:E0:0C:BC:E5:60 +eth1addr = 00:E0:0C:BC:E5:61 +ip_addr = 192.168.1.3 +baudrate = 115200 bps +-> +-> help +? - alias for 'help' +autoscr - run script from memory +base - print or set address offset +bdinfo - print Board Info structure +boot - boot default, i.e., run 'bootcmd' +bootd - boot default, i.e., run 'bootcmd' +bootelf - Boot from an ELF image in memory +bootm - boot application image from memory +bootp - boot image via network using BootP/TFTP protocol +bootvx - Boot vxWorks from an ELF image +cmp - memory compare +coninfo - print console devices and information +cp - memory copy +crc32 - checksum calculation +date - get/set/reset date & time +dcache - enable or disable data cache +diskboot- boot from IDE device +echo - echo args to console +erase - erase FLASH memory +ext2load- load binary file from a Ext2 filesystem +ext2ls - list files in a directory (default /) +fatinfo - print information about filesystem +fatload - load binary file from a dos filesystem +fatls - list files in a directory (default /) +flinfo - print FLASH memory information +fsinfo - print information about filesystems +fsload - load binary file from a filesystem image +go - start application at address 'addr' +help - print online help +icache - enable or disable instruction cache +icrc32 - checksum calculation +ide - IDE sub-system +iloop - infinite loop on address range +imd - i2c memory display +iminfo - print header information for application image +imls - list all images found in flash +imm - i2c memory modify (auto-incrementing) +imw - memory write (fill) +inm - memory modify (constant address) +iprobe - probe to discover valid I2C chip addresses +itest - return true/false on integer compare +loadb - load binary file over serial line (kermit mode) +loads - load S-Record file over serial line +loady - load binary file over serial line (ymodem mode) +loop - infinite loop on address range +ls - list files in a directory (default /) +md - memory display +mii - MII utility commands +mm - memory modify (auto-incrementing) +mtest - simple RAM test +mw - memory write (fill) +nfs - boot image via network using NFS protocol +nm - memory modify (constant address) +pci - list and access PCI Configuration Space +ping - send ICMP ECHO_REQUEST to network host +printenv- print environment variables +protect - enable or disable FLASH write protection +rarpboot- boot image via network using RARP/TFTP protocol +reset - Perform RESET of the CPU +run - run commands in an environment variable +saveenv - save environment variables to persistent storage +setenv - set environment variables +sleep - delay execution for some time +tftpboot- boot image via network using TFTP protocol +version - print monitor version +->bootm 4000000 + +## Booting image at 04000000 ... + Image Name: Linux Kernel Image + Created: 2007-08-14 15:13:00 UTC + Image Type: M68K Linux Kernel Image (uncompressed) + Data Size: 2301952 Bytes = 2.2 MB + Load Address: 40020000 + Entry Point: 40020000 + Verifying Checksum ... OK +OK +Linux version 2.6.20-gfe5136d6-dirty (mattw@kea) (gcc version 4.2.0 20070318 (pr +erelease) (Sourcery G++ Lite 4.2-20)) #108 Mon Aug 13 13:00:13 MDT 2007 +starting up linux startmem 0xc0254000, endmem 0xcfffffff, size 253MB +Built 1 zonelists. Total pages: 32624 +Kernel command line: root=/dev/mtdblock1 rw rootfstype=jffs2 ip=none mtdparts=ph +ysmap-flash.0:5M(kernel)ro,-(jffs2) +PID hash table entries: 1024 (order: 10, 4096 bytes) +Console: colour dummy device 80x25 +Dentry cache hash table entries: 32768 (order: 4, 131072 bytes) +Inode-cache hash table entries: 16384 (order: 3, 65536 bytes) +Memory: 257496k/262136k available (1864k kernel code, 2440k data, 88k init) +Mount-cache hash table entries: 1024 +NET: Registered protocol family 16 +SCSI subsystem initialized +NET: Registered protocol family 2 +IP route cache hash table entries: 2048 (order: 0, 8192 bytes) +TCP established hash table entries: 8192 (order: 2, 32768 bytes) +TCP bind hash table entries: 4096 (order: 1, 16384 bytes) +TCP: Hash tables configured (established 8192 bind 4096) +TCP reno registered +JFFS2 version 2.2. (NAND) (C) 2001-2006 Red Hat, Inc. +io scheduler noop registered +io scheduler anticipatory registered +io scheduler deadline registered +io scheduler cfq registered (default) +ColdFire internal UART serial driver version 1.00 +ttyS0 at 0xfc060000 (irq = 90) is a builtin ColdFire UART +ttyS1 at 0xfc064000 (irq = 91) is a builtin ColdFire UART +ttyS2 at 0xfc068000 (irq = 92) is a builtin ColdFire UART +RAMDISK driver initialized: 16 RAM disks of 64000K size 1024 blocksize +loop: loaded (max 8 devices) +FEC ENET Version 0.2 +fec: PHY @ 0x0, ID 0x20005ca2 -- DP83849 +eth0: ethernet 00:08:ee:00:e4:19 +physmap platform flash device: 01000000 at 04000000 +physmap-flash.0: Found 1 x16 devices at 0x0 in 8-bit bank + Intel/Sharp Extended Query Table at 0x0031 +Using buffer write method +cfi_cmdset_0001: Erase suspend on write enabled +2 cmdlinepart partitions found on MTD device physmap-flash.0 +Creating 2 MTD partitions on "physmap-flash.0": +0x00000000-0x00500000 : "kernel" +mtd: Giving out device 0 to kernel +0x00500000-0x01000000 : "jffs2" +mtd: Giving out device 1 to jffs2 +mice: PS/2 mouse device common for all mice +i2c /dev entries driver +TCP cubic registered +NET: Registered protocol family 1 +NET: Registered protocol family 17 +NET: Registered protocol family 15 +VFS: Mounted root (jffs2 filesystem). +Setting the hostname to freescale +Mounting filesystems +mount: Mounting usbfs on /proc/bus/usb failed: No such file or directory +Starting syslogd and klogd +Setting up networking on loopback device: +Setting up networking on eth0: +eth0: config: auto-negotiation on, 100FDX, 100HDX, 10FDX, 10HDX. +Adding static route for default gateway to 172.27.255.254: +Setting nameserver to 172.27.0.1 in /etc/resolv.conf: +Starting inetd: +/ # diff --git a/drivers/net/mcffec.c b/drivers/net/mcffec.c index 68a0ee640..2e0ddeb77 100644 --- a/drivers/net/mcffec.c +++ b/drivers/net/mcffec.c @@ -430,20 +430,33 @@ int fec_init(struct eth_device *dev, bd_t * bd) /* Set station address */ if ((u32) fecp == CFG_FEC0_IOBASE) { +#ifdef CFG_FEC1_IOBASE + volatile fec_t *fecp1 = (fec_t *) (CFG_FEC1_IOBASE); + ea = &bd->bi_enet1addr[0]; + fecp1->palr = + (ea[0] << 24) | (ea[1] << 16) | (ea[2] << 8) | (ea[3]); + fecp1->paur = (ea[4] << 24) | (ea[5] << 16); +#endif ea = &bd->bi_enetaddr[0]; + fecp->palr = + (ea[0] << 24) | (ea[1] << 16) | (ea[2] << 8) | (ea[3]); + fecp->paur = (ea[4] << 24) | (ea[5] << 16); } else { +#ifdef CFG_FEC0_IOBASE + volatile fec_t *fecp0 = (fec_t *) (CFG_FEC0_IOBASE); + ea = &bd->bi_enetaddr[0]; + fecp0->palr = + (ea[0] << 24) | (ea[1] << 16) | (ea[2] << 8) | (ea[3]); + fecp0->paur = (ea[4] << 24) | (ea[5] << 16); +#endif #ifdef CFG_FEC1_IOBASE ea = &bd->bi_enet1addr[0]; + fecp->palr = + (ea[0] << 24) | (ea[1] << 16) | (ea[2] << 8) | (ea[3]); + fecp->paur = (ea[4] << 24) | (ea[5] << 16); #endif } - fecp->palr = (ea[0] << 24) | (ea[1] << 16) | (ea[2] << 8) | (ea[3]); - fecp->paur = (ea[4] << 24) | (ea[5] << 16); -#ifdef ET_DEBUG - printf("Eth Addrs: %02x:%02x:%02x:%02x:%02x:%02x\n", - ea[0], ea[1], ea[2], ea[3], ea[4], ea[5]); -#endif - /* Clear unicast address hash table */ fecp->iaur = 0; fecp->ialr = 0; diff --git a/include/asm-m68k/global_data.h b/include/asm-m68k/global_data.h index f68352f12..9d9894b1a 100644 --- a/include/asm-m68k/global_data.h +++ b/include/asm-m68k/global_data.h @@ -39,6 +39,14 @@ typedef struct global_data { unsigned long baudrate; unsigned long cpu_clk; /* CPU clock in Hz! */ unsigned long bus_clk; +#ifdef CONFIG_PCI + unsigned long pci_clk; +#endif +#ifdef CONFIG_EXTRA_CLOCK + unsigned long inp_clk; + unsigned long vco_clk; + unsigned long flb_clk; +#endif unsigned long ram_size; /* RAM size */ unsigned long reloc_off; /* Relocation Offset */ unsigned long reset_status; /* reset status register at boot */ diff --git a/include/asm-m68k/immap.h b/include/asm-m68k/immap.h index bf7b51bec..d66c1619b 100644 --- a/include/asm-m68k/immap.h +++ b/include/asm-m68k/immap.h @@ -170,4 +170,44 @@ #define CFG_NUM_IRQS (128) #endif /* CONFIG_M5329 */ +#ifdef CONFIG_M54455 +#include +#include + +#define CFG_FEC0_IOBASE (MMAP_FEC0) +#define CFG_FEC1_IOBASE (MMAP_FEC1) + +#define CFG_UART_BASE (MMAP_UART0 + (CFG_UART_PORT * 0x4000)) + +#define CFG_MCFRTC_BASE (MMAP_RTC) + +/* Timer */ +#ifdef CONFIG_MCFTMR +#define CFG_UDELAY_BASE (MMAP_DTMR0) +#define CFG_TMR_BASE (MMAP_DTMR1) +#define CFG_TMRPND_REG (((volatile int0_t *)(CFG_INTR_BASE))->iprh0) +#define CFG_TMRINTR_NO (INT0_HI_DTMR1) +#define CFG_TMRINTR_MASK (INTC_IPRH_INT33) +#define CFG_TMRINTR_PEND (CFG_TMRINTR_MASK) +#define CFG_TMRINTR_PRI (6) +#define CFG_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8) +#endif + +#ifdef CONFIG_MCFPIT +#define CFG_UDELAY_BASE (MMAP_PIT0) +#define CFG_PIT_BASE (MMAP_PIT1) +#define CFG_PIT_PRESCALE (6) +#endif + +#define CFG_INTR_BASE (MMAP_INTC0) +#define CFG_NUM_IRQS (128) + +#ifdef CONFIG_PCI +#define CFG_PCI_BAR0 CFG_SDRAM_BASE +#define CFG_PCI_BAR4 CFG_SDRAM_BASE +#define CFG_PCI_TBATR0 (CFG_SDRAM_BASE) +#define CFG_PCI_TBATR4 (CFG_SDRAM_BASE) +#endif +#endif /* CONFIG_M54455 */ + #endif /* __IMMAP_H */ diff --git a/include/asm-m68k/immap_5445x.h b/include/asm-m68k/immap_5445x.h new file mode 100644 index 000000000..d091d7b73 --- /dev/null +++ b/include/asm-m68k/immap_5445x.h @@ -0,0 +1,937 @@ +/* + * MCF5445x Internal Memory Map + * + * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __IMMAP_5445X__ +#define __IMMAP_5445X__ + +/* Module Base Addresses */ +#define MMAP_SCM1 0xFC000000 +#define MMAP_XBS 0xFC004000 +#define MMAP_FBCS 0xFC008000 +#define MMAP_FEC0 0xFC030000 +#define MMAP_FEC1 0xFC034000 +#define MMAP_RTC 0xFC03C000 +#define MMAP_EDMA 0xFC044000 +#define MMAP_INTC0 0xFC048000 +#define MMAP_INTC1 0xFC04C000 +#define MMAP_IACK 0xFC054000 +#define MMAP_I2C 0xFC058000 +#define MMAP_DSPI 0xFC05C000 +#define MMAP_UART0 0xFC060000 +#define MMAP_UART1 0xFC064000 +#define MMAP_UART2 0xFC068000 +#define MMAP_DTMR0 0xFC070000 +#define MMAP_DTMR1 0xFC074000 +#define MMAP_DTMR2 0xFC078000 +#define MMAP_DTMR3 0xFC07C000 +#define MMAP_PIT0 0xFC080000 +#define MMAP_PIT1 0xFC084000 +#define MMAP_PIT2 0xFC088000 +#define MMAP_PIT3 0xFC08C000 +#define MMAP_EPORT 0xFC094000 +#define MMAP_WTM 0xFC098000 +#define MMAP_SBF 0xFC0A0000 +#define MMAP_RCM 0xFC0A0000 +#define MMAP_CCM 0xFC0A0000 +#define MMAP_GPIO 0xFC0A4000 +#define MMAP_PCI 0xFC0A8000 +#define MMAP_PCIARB 0xFC0AC000 +#define MMAP_RNG 0xFC0B4000 +#define MMAP_SDRAM 0xFC0B8000 +#define MMAP_SSI 0xFC0BC000 +#define MMAP_PLL 0xFC0C4000 +#define MMAP_ATA 0x90000000 + +/********************************************************************* +* ATA +*********************************************************************/ + +typedef struct atac { + /* PIO */ + u8 toff; /* 0x00 */ + u8 ton; /* 0x01 */ + u8 t1; /* 0x02 */ + u8 t2w; /* 0x03 */ + u8 t2r; /* 0x04 */ + u8 ta; /* 0x05 */ + u8 trd; /* 0x06 */ + u8 t4; /* 0x07 */ + u8 t9; /* 0x08 */ + + /* DMA */ + u8 tm; /* 0x09 */ + u8 tn; /* 0x0A */ + u8 td; /* 0x0B */ + u8 tk; /* 0x0C */ + u8 tack; /* 0x0D */ + u8 tenv; /* 0x0E */ + u8 trp; /* 0x0F */ + u8 tzah; /* 0x10 */ + u8 tmli; /* 0x11 */ + u8 tdvh; /* 0x12 */ + u8 tdzfs; /* 0x13 */ + u8 tdvs; /* 0x14 */ + u8 tcvh; /* 0x15 */ + u8 tss; /* 0x16 */ + u8 tcyc; /* 0x17 */ + + /* FIFO */ + u32 fifo32; /* 0x18 */ + u16 fifo16; /* 0x1C */ + u8 rsvd0[2]; + u8 ffill; /* 0x20 */ + u8 rsvd1[3]; + + /* ATA */ + u8 cr; /* 0x24 */ + u8 rsvd2[3]; + u8 isr; /* 0x28 */ + u8 rsvd3[3]; + u8 ier; /* 0x2C */ + u8 rsvd4[3]; + u8 icr; /* 0x30 */ + u8 rsvd5[3]; + u8 falarm; /* 0x34 */ + u8 rsvd6[106]; +} atac_t; + +/********************************************************************* +* Cross-bar switch (XBS) +*********************************************************************/ + +typedef struct xbs { + u8 resv0[0x100]; + u32 prs1; /* XBS Priority Register */ + u8 resv1[0xC]; + u32 crs1; /* XBS Control Register */ + u8 resv2[0xEC]; + u32 prs2; /* XBS Priority Register */ + u8 resv3[0xC]; + u32 crs2; /* XBS Control Register */ + u8 resv4[0xEC]; + u32 prs3; /* XBS Priority Register */ + u8 resv5[0xC]; + u32 crs3; /* XBS Control Register */ + u8 resv6[0xEC]; + u32 prs4; /* XBS Priority Register */ + u8 resv7[0xC]; + u32 crs4; /* XBS Control Register */ + u8 resv8[0xEC]; + u32 prs5; /* XBS Priority Register */ + u8 resv9[0xC]; + u32 crs5; /* XBS Control Register */ + u8 resv10[0xEC]; + u32 prs6; /* XBS Priority Register */ + u8 resv11[0xC]; + u32 crs6; /* XBS Control Register */ + u8 resv12[0xEC]; + u32 prs7; /* XBS Priority Register */ + u8 resv13[0xC]; + u32 crs7; /* XBS Control Register */ +} xbs_t; + +/********************************************************************* +* FlexBus Chip Selects (FBCS) +*********************************************************************/ + +typedef struct fbcs { + u32 csar0; /* Chip-select Address Register */ + u32 csmr0; /* Chip-select Mask Register */ + u32 cscr0; /* Chip-select Control Register */ + u32 csar1; /* Chip-select Address Register */ + u32 csmr1; /* Chip-select Mask Register */ + u32 cscr1; /* Chip-select Control Register */ + u32 csar2; /* Chip-select Address Register */ + u32 csmr2; /* Chip-select Mask Register */ + u32 cscr2; /* Chip-select Control Register */ + u32 csar3; /* Chip-select Address Register */ + u32 csmr3; /* Chip-select Mask Register */ + u32 cscr3; /* Chip-select Control Register */ +} fbcs_t; + +/********************************************************************* +* Enhanced DMA (EDMA) +*********************************************************************/ + +typedef struct edma { + u32 cr; + u32 es; + u8 resv0[0x6]; + u16 erq; + u8 resv1[0x6]; + u16 eei; + u8 serq; + u8 cerq; + u8 seei; + u8 ceei; + u8 cint; + u8 cerr; + u8 ssrt; + u8 cdne; + u8 resv2[0x6]; + u16 intr; + u8 resv3[0x6]; + u16 err; + u8 resv4[0xD0]; + u8 dchpri0; + u8 dchpri1; + u8 dchpri2; + u8 dchpri3; + u8 dchpri4; + u8 dchpri5; + u8 dchpri6; + u8 dchpri7; + u8 dchpri8; + u8 dchpri9; + u8 dchpri10; + u8 dchpri11; + u8 dchpri12; + u8 dchpri13; + u8 dchpri14; + u8 dchpri15; + u8 resv5[0xEF0]; + u32 tcd0_saddr; + u16 tcd0_attr; + u16 tcd0_soff; + u32 tcd0_nbytes; + u32 tcd0_slast; + u32 tcd0_daddr; + union { + u16 tcd0_citer_elink; + u16 tcd0_citer; + }; + u16 tcd0_doff; + u32 tcd0_dlast_sga; + union { + u16 tcd0_biter_elink; + u16 tcd0_biter; + }; + u16 tcd0_csr; + u32 tcd1_saddr; + u16 tcd1_attr; + u16 tcd1_soff; + u32 tcd1_nbytes; + u32 tcd1_slast; + u32 tcd1_daddr; + union { + u16 tcd1_citer_elink; + u16 tcd1_citer; + }; + u16 tcd1_doff; + u32 tcd1_dlast_sga; + union { + u16 tcd1_biter; + u16 tcd1_biter_elink; + }; + u16 tcd1_csr; + u32 tcd2_saddr; + u16 tcd2_attr; + u16 tcd2_soff; + u32 tcd2_nbytes; + u32 tcd2_slast; + u32 tcd2_daddr; + union { + u16 tcd2_citer; + u16 tcd2_citer_elink; + }; + u16 tcd2_doff; + u32 tcd2_dlast_sga; + union { + u16 tcd2_biter_elink; + u16 tcd2_biter; + }; + u16 tcd2_csr; + u32 tcd3_saddr; + u16 tcd3_attr; + u16 tcd3_soff; + u32 tcd3_nbytes; + u32 tcd3_slast; + u32 tcd3_daddr; + union { + u16 tcd3_citer; + u16 tcd3_citer_elink; + }; + u16 tcd3_doff; + u32 tcd3_dlast_sga; + union { + u16 tcd3_biter_elink; + u16 tcd3_biter; + }; + u16 tcd3_csr; + u32 tcd4_saddr; + u16 tcd4_attr; + u16 tcd4_soff; + u32 tcd4_nbytes; + u32 tcd4_slast; + u32 tcd4_daddr; + union { + u16 tcd4_citer; + u16 tcd4_citer_elink; + }; + u16 tcd4_doff; + u32 tcd4_dlast_sga; + union { + u16 tcd4_biter; + u16 tcd4_biter_elink; + }; + u16 tcd4_csr; + u32 tcd5_saddr; + u16 tcd5_attr; + u16 tcd5_soff; + u32 tcd5_nbytes; + u32 tcd5_slast; + u32 tcd5_daddr; + union { + u16 tcd5_citer; + u16 tcd5_citer_elink; + }; + u16 tcd5_doff; + u32 tcd5_dlast_sga; + union { + u16 tcd5_biter_elink; + u16 tcd5_biter; + }; + u16 tcd5_csr; + u32 tcd6_saddr; + u16 tcd6_attr; + u16 tcd6_soff; + u32 tcd6_nbytes; + u32 tcd6_slast; + u32 tcd6_daddr; + union { + u16 tcd6_citer; + u16 tcd6_citer_elink; + }; + u16 tcd6_doff; + u32 tcd6_dlast_sga; + union { + u16 tcd6_biter_elink; + u16 tcd6_biter; + }; + u16 tcd6_csr; + u32 tcd7_saddr; + u16 tcd7_attr; + u16 tcd7_soff; + u32 tcd7_nbytes; + u32 tcd7_slast; + u32 tcd7_daddr; + union { + u16 tcd7_citer; + u16 tcd7_citer_elink; + }; + u16 tcd7_doff; + u32 tcd7_dlast_sga; + union { + u16 tcd7_biter_elink; + u16 tcd7_biter; + }; + u16 tcd7_csr; + u32 tcd8_saddr; + u16 tcd8_attr; + u16 tcd8_soff; + u32 tcd8_nbytes; + u32 tcd8_slast; + u32 tcd8_daddr; + union { + u16 tcd8_citer; + u16 tcd8_citer_elink; + }; + u16 tcd8_doff; + u32 tcd8_dlast_sga; + union { + u16 tcd8_biter_elink; + u16 tcd8_biter; + }; + u16 tcd8_csr; + u32 tcd9_saddr; + u16 tcd9_attr; + u16 tcd9_soff; + u32 tcd9_nbytes; + u32 tcd9_slast; + u32 tcd9_daddr; + union { + u16 tcd9_citer_elink; + u16 tcd9_citer; + }; + u16 tcd9_doff; + u32 tcd9_dlast_sga; + union { + u16 tcd9_biter_elink; + u16 tcd9_biter; + }; + u16 tcd9_csr; + u32 tcd10_saddr; + u16 tcd10_attr; + u16 tcd10_soff; + u32 tcd10_nbytes; + u32 tcd10_slast; + u32 tcd10_daddr; + union { + u16 tcd10_citer_elink; + u16 tcd10_citer; + }; + u16 tcd10_doff; + u32 tcd10_dlast_sga; + union { + u16 tcd10_biter; + u16 tcd10_biter_elink; + }; + u16 tcd10_csr; + u32 tcd11_saddr; + u16 tcd11_attr; + u16 tcd11_soff; + u32 tcd11_nbytes; + u32 tcd11_slast; + u32 tcd11_daddr; + union { + u16 tcd11_citer; + u16 tcd11_citer_elink; + }; + u16 tcd11_doff; + u32 tcd11_dlast_sga; + union { + u16 tcd11_biter; + u16 tcd11_biter_elink; + }; + u16 tcd11_csr; + u32 tcd12_saddr; + u16 tcd12_attr; + u16 tcd12_soff; + u32 tcd12_nbytes; + u32 tcd12_slast; + u32 tcd12_daddr; + union { + u16 tcd12_citer; + u16 tcd12_citer_elink; + }; + u16 tcd12_doff; + u32 tcd12_dlast_sga; + union { + u16 tcd12_biter; + u16 tcd12_biter_elink; + }; + u16 tcd12_csr; + u32 tcd13_saddr; + u16 tcd13_attr; + u16 tcd13_soff; + u32 tcd13_nbytes; + u32 tcd13_slast; + u32 tcd13_daddr; + union { + u16 tcd13_citer_elink; + u16 tcd13_citer; + }; + u16 tcd13_doff; + u32 tcd13_dlast_sga; + union { + u16 tcd13_biter_elink; + u16 tcd13_biter; + }; + u16 tcd13_csr; + u32 tcd14_saddr; + u16 tcd14_attr; + u16 tcd14_soff; + u32 tcd14_nbytes; + u32 tcd14_slast; + u32 tcd14_daddr; + union { + u16 tcd14_citer; + u16 tcd14_citer_elink; + }; + u16 tcd14_doff; + u32 tcd14_dlast_sga; + union { + u16 tcd14_biter_elink; + u16 tcd14_biter; + }; + u16 tcd14_csr; + u32 tcd15_saddr; + u16 tcd15_attr; + u16 tcd15_soff; + u32 tcd15_nbytes; + u32 tcd15_slast; + u32 tcd15_daddr; + union { + u16 tcd15_citer_elink; + u16 tcd15_citer; + }; + u16 tcd15_doff; + u32 tcd15_dlast_sga; + union { + u16 tcd15_biter; + u16 tcd15_biter_elink; + }; + u16 tcd15_csr; +} edma_t; + +/********************************************************************* +* Interrupt Controller (INTC) +*********************************************************************/ + +typedef struct int0_ctrl { + u32 iprh0; /* 0x00 Pending Register High */ + u32 iprl0; /* 0x04 Pending Register Low */ + u32 imrh0; /* 0x08 Mask Register High */ + u32 imrl0; /* 0x0C Mask Register Low */ + u32 frch0; /* 0x10 Force Register High */ + u32 frcl0; /* 0x14 Force Register Low */ + u16 res1; /* 0x18 - 0x19 */ + u16 icfg0; /* 0x1A Configuration Register */ + u8 simr0; /* 0x1C Set Interrupt Mask */ + u8 cimr0; /* 0x1D Clear Interrupt Mask */ + u8 clmask0; /* 0x1E Current Level Mask */ + u8 slmask; /* 0x1F Saved Level Mask */ + u32 res2[8]; /* 0x20 - 0x3F */ + u8 icr0[64]; /* 0x40 - 0x7F Control registers */ + u32 res3[24]; /* 0x80 - 0xDF */ + u8 swiack0; /* 0xE0 Software Interrupt Acknowledge */ + u8 res4[3]; /* 0xE1 - 0xE3 */ + u8 Lniack0_1; /* 0xE4 Level n interrupt acknowledge resister */ + u8 res5[3]; /* 0xE5 - 0xE7 */ + u8 Lniack0_2; /* 0xE8 Level n interrupt acknowledge resister */ + u8 res6[3]; /* 0xE9 - 0xEB */ + u8 Lniack0_3; /* 0xEC Level n interrupt acknowledge resister */ + u8 res7[3]; /* 0xED - 0xEF */ + u8 Lniack0_4; /* 0xF0 Level n interrupt acknowledge resister */ + u8 res8[3]; /* 0xF1 - 0xF3 */ + u8 Lniack0_5; /* 0xF4 Level n interrupt acknowledge resister */ + u8 res9[3]; /* 0xF5 - 0xF7 */ + u8 Lniack0_6; /* 0xF8 Level n interrupt acknowledge resister */ + u8 resa[3]; /* 0xF9 - 0xFB */ + u8 Lniack0_7; /* 0xFC Level n interrupt acknowledge resister */ + u8 resb[3]; /* 0xFD - 0xFF */ +} int0_t; + +typedef struct int1_ctrl { + /* Interrupt Controller 1 */ + u32 iprh1; /* 0x00 Pending Register High */ + u32 iprl1; /* 0x04 Pending Register Low */ + u32 imrh1; /* 0x08 Mask Register High */ + u32 imrl1; /* 0x0C Mask Register Low */ + u32 frch1; /* 0x10 Force Register High */ + u32 frcl1; /* 0x14 Force Register Low */ + u16 res1; /* 0x18 */ + u16 icfg1; /* 0x1A Configuration Register */ + u8 simr1; /* 0x1C Set Interrupt Mask */ + u8 cimr1; /* 0x1D Clear Interrupt Mask */ + u16 res2; /* 0x1E - 0x1F */ + u32 res3[8]; /* 0x20 - 0x3F */ + u8 icr1[64]; /* 0x40 - 0x7F */ + u32 res4[24]; /* 0x80 - 0xDF */ + u8 swiack1; /* 0xE0 Software Interrupt Acknowledge */ + u8 res5[3]; /* 0xE1 - 0xE3 */ + u8 Lniack1_1; /* 0xE4 Level n interrupt acknowledge resister */ + u8 res6[3]; /* 0xE5 - 0xE7 */ + u8 Lniack1_2; /* 0xE8 Level n interrupt acknowledge resister */ + u8 res7[3]; /* 0xE9 - 0xEB */ + u8 Lniack1_3; /* 0xEC Level n interrupt acknowledge resister */ + u8 res8[3]; /* 0xED - 0xEF */ + u8 Lniack1_4; /* 0xF0 Level n interrupt acknowledge resister */ + u8 res9[3]; /* 0xF1 - 0xF3 */ + u8 Lniack1_5; /* 0xF4 Level n interrupt acknowledge resister */ + u8 resa[3]; /* 0xF5 - 0xF7 */ + u8 Lniack1_6; /* 0xF8 Level n interrupt acknowledge resister */ + u8 resb[3]; /* 0xF9 - 0xFB */ + u8 Lniack1_7; /* 0xFC Level n interrupt acknowledge resister */ + u8 resc[3]; /* 0xFD - 0xFF */ +} int1_t; + +/********************************************************************* +* Global Interrupt Acknowledge (IACK) +*********************************************************************/ + +typedef struct iack { + u8 resv0[0xE0]; + u8 gswiack; + u8 resv1[0x3]; + u8 gl1iack; + u8 resv2[0x3]; + u8 gl2iack; + u8 resv3[0x3]; + u8 gl3iack; + u8 resv4[0x3]; + u8 gl4iack; + u8 resv5[0x3]; + u8 gl5iack; + u8 resv6[0x3]; + u8 gl6iack; + u8 resv7[0x3]; + u8 gl7iack; +} iack_t; + +/********************************************************************* +* DMA Serial Peripheral Interface (DSPI) +*********************************************************************/ + +typedef struct dspi { + u32 dmcr; + u8 resv0[0x4]; + u32 dtcr; + u32 dctar0; + u32 dctar1; + u32 dctar2; + u32 dctar3; + u32 dctar4; + u32 dctar5; + u32 dctar6; + u32 dctar7; + u32 dsr; + u32 dirsr; + u32 dtfr; + u32 drfr; + u32 dtfdr0; + u32 dtfdr1; + u32 dtfdr2; + u32 dtfdr3; + u8 resv1[0x30]; + u32 drfdr0; + u32 drfdr1; + u32 drfdr2; + u32 drfdr3; +} dspi_t; + +/********************************************************************* +* Edge Port Module (EPORT) +*********************************************************************/ + +typedef struct eport { + u16 eppar; + u8 epddr; + u8 epier; + u8 epdr; + u8 eppdr; + u8 epfr; +} eport_t; + +/********************************************************************* +* Watchdog Timer Modules (WTM) +*********************************************************************/ + +typedef struct wtm { + u16 wcr; + u16 wmr; + u16 wcntr; + u16 wsr; +} wtm_t; + +/********************************************************************* +* Serial Boot Facility (SBF) +*********************************************************************/ + +typedef struct sbf { + u8 resv0[0x18]; + u16 sbfsr; /* Serial Boot Facility Status Register */ + u8 resv1[0x6]; + u16 sbfcr; /* Serial Boot Facility Control Register */ +} sbf_t; + +/********************************************************************* +* Reset Controller Module (RCM) +*********************************************************************/ + +typedef struct rcm { + u8 rcr; + u8 rsr; +} rcm_t; + +/********************************************************************* +* Chip Configuration Module (CCM) +*********************************************************************/ + +typedef struct ccm { + u8 ccm_resv0[0x4]; + u16 ccr; /* Chip Configuration Register (256 TEPBGA, Read-only) */ + u8 resv1[0x2]; + u16 rcon; /* Reset Configuration (256 TEPBGA, Read-only) */ + u16 cir; /* Chip Identification Register (Read-only) */ + u8 resv2[0x4]; + u16 misccr; /* Miscellaneous Control Register */ + u16 cdr; /* Clock Divider Register */ + u16 uocsr; /* USB On-the-Go Controller Status Register */ +} ccm_t; + +/********************************************************************* +* General Purpose I/O Module (GPIO) +*********************************************************************/ + +typedef struct gpio { + u8 podr_fec0h; /* FEC0 High Port Output Data Register */ + u8 podr_fec0l; /* FEC0 Low Port Output Data Register */ + u8 podr_ssi; /* SSI Port Output Data Register */ + u8 podr_fbctl; /* Flexbus Control Port Output Data Register */ + u8 podr_be; /* Flexbus Byte Enable Port Output Data Register */ + u8 podr_cs; /* Flexbus Chip-Select Port Output Data Register */ + u8 podr_dma; /* DMA Port Output Data Register */ + u8 podr_feci2c; /* FEC1 / I2C Port Output Data Register */ + u8 resv0[0x1]; + u8 podr_uart; /* UART Port Output Data Register */ + u8 podr_dspi; /* DSPI Port Output Data Register */ + u8 podr_timer; /* Timer Port Output Data Register */ + u8 podr_pci; /* PCI Port Output Data Register */ + u8 podr_usb; /* USB Port Output Data Register */ + u8 podr_atah; /* ATA High Port Output Data Register */ + u8 podr_atal; /* ATA Low Port Output Data Register */ + u8 podr_fec1h; /* FEC1 High Port Output Data Register */ + u8 podr_fec1l; /* FEC1 Low Port Output Data Register */ + u8 resv1[0x2]; + u8 podr_fbadh; /* Flexbus AD High Port Output Data Register */ + u8 podr_fbadmh; /* Flexbus AD Med-High Port Output Data Register */ + u8 podr_fbadml; /* Flexbus AD Med-Low Port Output Data Register */ + u8 podr_fbadl; /* Flexbus AD Low Port Output Data Register */ + u8 pddr_fec0h; /* FEC0 High Port Data Direction Register */ + u8 pddr_fec0l; /* FEC0 Low Port Data Direction Register */ + u8 pddr_ssi; /* SSI Port Data Direction Register */ + u8 pddr_fbctl; /* Flexbus Control Port Data Direction Register */ + u8 pddr_be; /* Flexbus Byte Enable Port Data Direction Register */ + u8 pddr_cs; /* Flexbus Chip-Select Port Data Direction Register */ + u8 pddr_dma; /* DMA Port Data Direction Register */ + u8 pddr_feci2c; /* FEC1 / I2C Port Data Direction Register */ + u8 resv2[0x1]; + u8 pddr_uart; /* UART Port Data Direction Register */ + u8 pddr_dspi; /* DSPI Port Data Direction Register */ + u8 pddr_timer; /* Timer Port Data Direction Register */ + u8 pddr_pci; /* PCI Port Data Direction Register */ + u8 pddr_usb; /* USB Port Data Direction Register */ + u8 pddr_atah; /* ATA High Port Data Direction Register */ + u8 pddr_atal; /* ATA Low Port Data Direction Register */ + u8 pddr_fec1h; /* FEC1 High Port Data Direction Register */ + u8 pddr_fec1l; /* FEC1 Low Port Data Direction Register */ + u8 resv3[0x2]; + u8 pddr_fbadh; /* Flexbus AD High Port Data Direction Register */ + u8 pddr_fbadmh; /* Flexbus AD Med-High Port Data Direction Register */ + u8 pddr_fbadml; /* Flexbus AD Med-Low Port Data Direction Register */ + u8 pddr_fbadl; /* Flexbus AD Low Port Data Direction Register */ + u8 ppdsdr_fec0h; /* FEC0 High Port Pin Data/Set Data Register */ + u8 ppdsdr_fec0l; /* FEC0 Low Port Clear Output Data Register */ + u8 ppdsdr_ssi; /* SSI Port Pin Data/Set Data Register */ + u8 ppdsdr_fbctl; /* Flexbus Control Port Pin Data/Set Data Register */ + u8 ppdsdr_be; /* Flexbus Byte Enable Port Pin Data/Set Data Register */ + u8 ppdsdr_cs; /* Flexbus Chip-Select Port Pin Data/Set Data Register */ + u8 ppdsdr_dma; /* DMA Port Pin Data/Set Data Register */ + u8 ppdsdr_feci2c; /* FEC1 / I2C Port Pin Data/Set Data Register */ + u8 resv4[0x1]; + u8 ppdsdr_uart; /* UART Port Pin Data/Set Data Register */ + u8 ppdsdr_dspi; /* DSPI Port Pin Data/Set Data Register */ + u8 ppdsdr_timer; /* FTimer Port Pin Data/Set Data Register */ + u8 ppdsdr_pci; /* PCI Port Pin Data/Set Data Register */ + u8 ppdsdr_usb; /* USB Port Pin Data/Set Data Register */ + u8 ppdsdr_atah; /* ATA High Port Pin Data/Set Data Register */ + u8 ppdsdr_atal; /* ATA Low Port Pin Data/Set Data Register */ + u8 ppdsdr_fec1h; /* FEC1 High Port Pin Data/Set Data Register */ + u8 ppdsdr_fec1l; /* FEC1 Low Port Pin Data/Set Data Register */ + u8 resv5[0x2]; + u8 ppdsdr_fbadh; /* Flexbus AD High Port Pin Data/Set Data Register */ + u8 ppdsdr_fbadmh; /* Flexbus AD Med-High Port Pin Data/Set Data Register */ + u8 ppdsdr_fbadml; /* Flexbus AD Med-Low Port Pin Data/Set Data Register */ + u8 ppdsdr_fbadl; /* Flexbus AD Low Port Pin Data/Set Data Register */ + u8 pclrr_fec0h; /* FEC0 High Port Clear Output Data Register */ + u8 pclrr_fec0l; /* FEC0 Low Port Pin Data/Set Data Register */ + u8 pclrr_ssi; /* SSI Port Clear Output Data Register */ + u8 pclrr_fbctl; /* Flexbus Control Port Clear Output Data Register */ + u8 pclrr_be; /* Flexbus Byte Enable Port Clear Output Data Register */ + u8 pclrr_cs; /* Flexbus Chip-Select Port Clear Output Data Register */ + u8 pclrr_dma; /* DMA Port Clear Output Data Register */ + u8 pclrr_feci2c; /* FEC1 / I2C Port Clear Output Data Register */ + u8 resv6[0x1]; + u8 pclrr_uart; /* UART Port Clear Output Data Register */ + u8 pclrr_dspi; /* DSPI Port Clear Output Data Register */ + u8 pclrr_timer; /* Timer Port Clear Output Data Register */ + u8 pclrr_pci; /* PCI Port Clear Output Data Register */ + u8 pclrr_usb; /* USB Port Clear Output Data Register */ + u8 pclrr_atah; /* ATA High Port Clear Output Data Register */ + u8 pclrr_atal; /* ATA Low Port Clear Output Data Register */ + u8 pclrr_fec1h; /* FEC1 High Port Clear Output Data Register */ + u8 pclrr_fec1l; /* FEC1 Low Port Clear Output Data Register */ + u8 resv7[0x2]; + u8 pclrr_fbadh; /* Flexbus AD High Port Clear Output Data Register */ + u8 pclrr_fbadmh; /* Flexbus AD Med-High Port Clear Output Data Register */ + u8 pclrr_fbadml; /* Flexbus AD Med-Low Port Clear Output Data Register */ + u8 pclrr_fbadl; /* Flexbus AD Low Port Clear Output Data Register */ + u8 par_fec; /* FEC Pin Assignment Register */ + u8 par_dma; /* DMA Pin Assignment Register */ + u8 par_fbctl; /* Flexbus Control Pin Assignment Register */ + u8 par_dspi; /* DSPI Pin Assignment Register */ + u8 par_be; /* Flexbus Byte-Enable Pin Assignment Register */ + u8 par_cs; /* Flexbus Chip-Select Pin Assignment Register */ + u8 par_timer; /* Time Pin Assignment Register */ + u8 par_usb; /* USB Pin Assignment Register */ + u8 resv8[0x1]; + u8 par_uart; /* UART Pin Assignment Register */ + u16 par_feci2c; /* FEC / I2C Pin Assignment Register */ + u16 par_ssi; /* SSI Pin Assignment Register */ + u16 par_ata; /* ATA Pin Assignment Register */ + u8 par_irq; /* IRQ Pin Assignment Register */ + u8 resv9[0x1]; + u16 par_pci; /* PCI Pin Assignment Register */ + u8 mscr_sdram; /* SDRAM Mode Select Control Register */ + u8 mscr_pci; /* PCI Mode Select Control Register */ + u8 resv10[0x2]; + u8 dscr_i2c; /* I2C Drive Strength Control Register */ + u8 dscr_flexbus; /* FLEXBUS Drive Strength Control Register */ + u8 dscr_fec; /* FEC Drive Strength Control Register */ + u8 dscr_uart; /* UART Drive Strength Control Register */ + u8 dscr_dspi; /* DSPI Drive Strength Control Register */ + u8 dscr_timer; /* TIMER Drive Strength Control Register */ + u8 dscr_ssi; /* SSI Drive Strength Control Register */ + u8 dscr_dma; /* DMA Drive Strength Control Register */ + u8 dscr_debug; /* DEBUG Drive Strength Control Register */ + u8 dscr_reset; /* RESET Drive Strength Control Register */ + u8 dscr_irq; /* IRQ Drive Strength Control Register */ + u8 dscr_usb; /* USB Drive Strength Control Register */ + u8 dscr_ata; /* ATA Drive Strength Control Register */ +} gpio_t; + +/********************************************************************* +* Random Number Generator (RNG) +*********************************************************************/ + +typedef struct rng { + u32 rngcr; + u32 rngsr; + u32 rnger; + u32 rngout; +} rng_t; + +/********************************************************************* +* SDRAM Controller (SDRAMC) +*********************************************************************/ + +typedef struct sdramc { + u32 sdmr; /* SDRAM Mode/Extended Mode Register */ + u32 sdcr; /* SDRAM Control Register */ + u32 sdcfg1; /* SDRAM Configuration Register 1 */ + u32 sdcfg2; /* SDRAM Chip Select Register */ + u8 resv0[0x100]; + u32 sdcs0; /* SDRAM Mode/Extended Mode Register */ + u32 sdcs1; /* SDRAM Mode/Extended Mode Register */ +} sdramc_t; + +/********************************************************************* +* Synchronous Serial Interface (SSI) +*********************************************************************/ + +typedef struct ssi { + u32 tx0; + u32 tx1; + u32 rx0; + u32 rx1; + u32 cr; + u32 isr; + u32 ier; + u32 tcr; + u32 rcr; + u32 ccr; + u8 resv0[0x4]; + u32 fcsr; + u8 resv1[0x8]; + u32 acr; + u32 acadd; + u32 acdat; + u32 atag; + u32 tmask; + u32 rmask; +} ssi_t; + +/********************************************************************* +* Phase Locked Loop (PLL) +*********************************************************************/ + +typedef struct pll { + u32 pcr; /* PLL Control Register */ + u32 psr; /* PLL Status Register */ +} pll_t; + +typedef struct pci { + u32 idr; /* 0x00 Device Id / Vendor Id Register */ + u32 scr; /* 0x04 Status / command Register */ + u32 ccrir; /* 0x08 Class Code / Revision Id Register */ + u32 cr1; /* 0x0c Configuration 1 Register */ + u32 bar0; /* 0x10 Base address register 0 Register */ + u32 bar1; /* 0x14 Base address register 1 Register */ + u32 bar2; /* 0x18 Base address register 2 Register */ + u32 bar3; /* 0x1c Base address register 3 Register */ + u32 bar4; /* 0x20 Base address register 4 Register */ + u32 bar5; /* 0x24 Base address register 5 Register */ + u32 ccpr; /* 0x28 Cardbus CIS Pointer Register */ + u32 sid; /* 0x2c Subsystem ID / Subsystem Vendor ID Register */ + u32 erbar; /* 0x30 Expansion ROM Base Address Register */ + u32 cpr; /* 0x34 Capabilities Pointer Register */ + u32 rsvd1; /* 0x38 */ + u32 cr2; /* 0x3c Configuration Register 2 */ + u32 rsvd2[8]; /* 0x40 - 0x5f */ + + /* General control / status registers */ + u32 gscr; /* 0x60 Global Status / Control Register */ + u32 tbatr0a; /* 0x64 Target Base Address Translation Register 0 */ + u32 tbatr1a; /* 0x68 Target Base Address Translation Register 1 */ + u32 tcr1; /* 0x6c Target Control 1 Register */ + u32 iw0btar; /* 0x70 Initiator Window 0 Base/Translation addr */ + u32 iw1btar; /* 0x74 Initiator Window 1 Base/Translation addr */ + u32 iw2btar; /* 0x78 Initiator Window 2 Base/Translation addr */ + u32 rsvd3; /* 0x7c */ + u32 iwcr; /* 0x80 Initiator Window Configuration Register */ + u32 icr; /* 0x84 Initiator Control Register */ + u32 isr; /* 0x88 Initiator Status Register */ + u32 tcr2; /* 0x8c Target Control 2 Register */ + u32 tbatr0; /* 0x90 Target Base Address Translation Register 0 */ + u32 tbatr1; /* 0x94 Target Base Address Translation Register 1 */ + u32 tbatr2; /* 0x98 Target Base Address Translation Register 2 */ + u32 tbatr3; /* 0x9c Target Base Address Translation Register 3 */ + u32 tbatr4; /* 0xa0 Target Base Address Translation Register 4 */ + u32 tbatr5; /* 0xa4 Target Base Address Translation Register 5 */ + u32 intr; /* 0xa8 Interrupt Register */ + u32 rsvd4[19]; /* 0xac - 0xf7 */ + u32 car; /* 0xf8 Configuration Address Register */ +} pci_t; + +typedef struct pci_arbiter { + /* Pci Arbiter Registers */ + union { + u32 acr; /* Arbiter Control Register */ + u32 asr; /* Arbiter Status Register */ + }; +} pciarb_t; + +/* Register read/write struct */ +typedef struct scm1 { + u32 mpr; /* 0x00 Master Privilege Register */ + u32 rsvd1[7]; + u32 pacra; /* 0x20 Peripheral Access Control Register A */ + u32 pacrb; /* 0x24 Peripheral Access Control Register B */ + u32 pacrc; /* 0x28 Peripheral Access Control Register C */ + u32 pacrd; /* 0x2C Peripheral Access Control Register D */ + u32 rsvd2[4]; + u32 pacre; /* 0x40 Peripheral Access Control Register E */ + u32 pacrf; /* 0x44 Peripheral Access Control Register F */ + u32 pacrg; /* 0x48 Peripheral Access Control Register G */ +} scm1_t; +/********************************************************************/ + +typedef struct rtcex { + u32 rsvd1[3]; + u32 gocu; + u32 gocl; +} rtcex_t; +#endif /* __IMMAP_5445X__ */ diff --git a/include/asm-m68k/m5445x.h b/include/asm-m68k/m5445x.h new file mode 100644 index 000000000..8b886b0b6 --- /dev/null +++ b/include/asm-m68k/m5445x.h @@ -0,0 +1,1541 @@ +/* + * MCF5445x Internal Memory Map + * + * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __MCF5445X__ +#define __MCF5445X__ + +/********************************************************************* +* Cross-bar switch (XBS) +*********************************************************************/ + +/* Bit definitions and macros for PRS group */ +#define XBS_PRS_M0(x) (((x)&0x00000007)) /* Core */ +#define XBS_PRS_M1(x) (((x)&0x00000007)<<4) /* eDMA */ +#define XBS_PRS_M2(x) (((x)&0x00000007)<<8) /* FEC0 */ +#define XBS_PRS_M3(x) (((x)&0x00000007)<<12) /* FEC1 */ +#define XBS_PRS_M5(x) (((x)&0x00000007)<<20) /* PCI controller */ +#define XBS_PRS_M6(x) (((x)&0x00000007)<<24) /* USB OTG */ +#define XBS_PRS_M7(x) (((x)&0x00000007)<<28) /* Serial Boot */ + +/* Bit definitions and macros for CRS group */ +#define XBS_CRS_PARK(x) (((x)&0x00000007)) /* Master parking ctrl */ +#define XBS_CRS_PCTL(x) (((x)&0x00000003)<<4) /* Parking mode ctrl */ +#define XBS_CRS_ARB (0x00000100) /* Arbitration Mode */ +#define XBS_CRS_RO (0x80000000) /* Read Only */ + +#define XBS_CRS_PCTL_PARK_FIELD (0) +#define XBS_CRS_PCTL_PARK_ON_LAST (1) +#define XBS_CRS_PCTL_PARK_NONE (2) +#define XBS_CRS_PCTL_PARK_CORE (0) +#define XBS_CRS_PCTL_PARK_EDMA (1) +#define XBS_CRS_PCTL_PARK_FEC0 (2) +#define XBS_CRS_PCTL_PARK_FEC1 (3) +#define XBS_CRS_PCTL_PARK_PCI (5) +#define XBS_CRS_PCTL_PARK_USB (6) +#define XBS_CRS_PCTL_PARK_SBF (7) + +/********************************************************************* +* FlexBus Chip Selects (FBCS) +*********************************************************************/ + +/* Bit definitions and macros for CSAR group */ +#define FBCS_CSAR_BA(x) ((x)&0xFFFF0000) + +/* Bit definitions and macros for CSMR group */ +#define FBCS_CSMR_V (0x00000001) /* Valid bit */ +#define FBCS_CSMR_WP (0x00000100) /* Write protect */ +#define FBCS_CSMR_BAM(x) (((x)&0x0000FFFF)<<16) /* Base address mask */ +#define FBCS_CSMR_BAM_4G (0xFFFF0000) +#define FBCS_CSMR_BAM_2G (0x7FFF0000) +#define FBCS_CSMR_BAM_1G (0x3FFF0000) +#define FBCS_CSMR_BAM_1024M (0x3FFF0000) +#define FBCS_CSMR_BAM_512M (0x1FFF0000) +#define FBCS_CSMR_BAM_256M (0x0FFF0000) +#define FBCS_CSMR_BAM_128M (0x07FF0000) +#define FBCS_CSMR_BAM_64M (0x03FF0000) +#define FBCS_CSMR_BAM_32M (0x01FF0000) +#define FBCS_CSMR_BAM_16M (0x00FF0000) +#define FBCS_CSMR_BAM_8M (0x007F0000) +#define FBCS_CSMR_BAM_4M (0x003F0000) +#define FBCS_CSMR_BAM_2M (0x001F0000) +#define FBCS_CSMR_BAM_1M (0x000F0000) +#define FBCS_CSMR_BAM_1024K (0x000F0000) +#define FBCS_CSMR_BAM_512K (0x00070000) +#define FBCS_CSMR_BAM_256K (0x00030000) +#define FBCS_CSMR_BAM_128K (0x00010000) +#define FBCS_CSMR_BAM_64K (0x00000000) + +/* Bit definitions and macros for CSCR group */ +#define FBCS_CSCR_BSTW (0x00000008) /* Burst-write enable */ +#define FBCS_CSCR_BSTR (0x00000010) /* Burst-read enable */ +#define FBCS_CSCR_BEM (0x00000020) /* Byte-enable mode */ +#define FBCS_CSCR_PS(x) (((x)&0x00000003)<<6) /* Port size */ +#define FBCS_CSCR_AA (0x00000100) /* Auto-acknowledge */ +#define FBCS_CSCR_WS(x) (((x)&0x0000003F)<<10) /* Wait states */ +#define FBCS_CSCR_WRAH(x) (((x)&0x00000003)<<16) /* Write address hold or deselect */ +#define FBCS_CSCR_RDAH(x) (((x)&0x00000003)<<18) /* Read address hold or deselect */ +#define FBCS_CSCR_ASET(x) (((x)&0x00000003)<<20) /* Address setup */ +#define FBCS_CSCR_SWSEN (0x00800000) /* Secondary wait state enable */ +#define FBCS_CSCR_SWS(x) (((x)&0x0000003F)<<26) /* Secondary wait states */ + +#define FBCS_CSCR_PS_8 (0x00000040) +#define FBCS_CSCR_PS_16 (0x00000080) +#define FBCS_CSCR_PS_32 (0x00000000) + +/********************************************************************* +* Interrupt Controller (INTC) +*********************************************************************/ +#define INT0_LO_RSVD0 (0) +#define INT0_LO_EPORT1 (1) +#define INT0_LO_EPORT2 (2) +#define INT0_LO_EPORT3 (3) +#define INT0_LO_EPORT4 (4) +#define INT0_LO_EPORT5 (5) +#define INT0_LO_EPORT6 (6) +#define INT0_LO_EPORT7 (7) +#define INT0_LO_EDMA_00 (8) +#define INT0_LO_EDMA_01 (9) +#define INT0_LO_EDMA_02 (10) +#define INT0_LO_EDMA_03 (11) +#define INT0_LO_EDMA_04 (12) +#define INT0_LO_EDMA_05 (13) +#define INT0_LO_EDMA_06 (14) +#define INT0_LO_EDMA_07 (15) +#define INT0_LO_EDMA_08 (16) +#define INT0_LO_EDMA_09 (17) +#define INT0_LO_EDMA_10 (18) +#define INT0_LO_EDMA_11 (19) +#define INT0_LO_EDMA_12 (20) +#define INT0_LO_EDMA_13 (21) +#define INT0_LO_EDMA_14 (22) +#define INT0_LO_EDMA_15 (23) +#define INT0_LO_EDMA_ERR (24) +#define INT0_LO_SCM (25) +#define INT0_LO_UART0 (26) +#define INT0_LO_UART1 (27) +#define INT0_LO_UART2 (28) +#define INT0_LO_RSVD1 (29) +#define INT0_LO_I2C (30) +#define INT0_LO_QSPI (31) +#define INT0_HI_DTMR0 (32) +#define INT0_HI_DTMR1 (33) +#define INT0_HI_DTMR2 (34) +#define INT0_HI_DTMR3 (35) +#define INT0_HI_FEC0_TXF (36) +#define INT0_HI_FEC0_TXB (37) +#define INT0_HI_FEC0_UN (38) +#define INT0_HI_FEC0_RL (39) +#define INT0_HI_FEC0_RXF (40) +#define INT0_HI_FEC0_RXB (41) +#define INT0_HI_FEC0_MII (42) +#define INT0_HI_FEC0_LC (43) +#define INT0_HI_FEC0_HBERR (44) +#define INT0_HI_FEC0_GRA (45) +#define INT0_HI_FEC0_EBERR (46) +#define INT0_HI_FEC0_BABT (47) +#define INT0_HI_FEC0_BABR (48) +#define INT0_HI_FEC1_TXF (49) +#define INT0_HI_FEC1_TXB (50) +#define INT0_HI_FEC1_UN (51) +#define INT0_HI_FEC1_RL (52) +#define INT0_HI_FEC1_RXF (53) +#define INT0_HI_FEC1_RXB (54) +#define INT0_HI_FEC1_MII (55) +#define INT0_HI_FEC1_LC (56) +#define INT0_HI_FEC1_HBERR (57) +#define INT0_HI_FEC1_GRA (58) +#define INT0_HI_FEC1_EBERR (59) +#define INT0_HI_FEC1_BABT (60) +#define INT0_HI_FEC1_BABR (61) +#define INT0_HI_SCMIR (62) +#define INT0_HI_RTC_ISR (63) + +#define INT1_HI_DSPI_EOQF (33) +#define INT1_HI_DSPI_TFFF (34) +#define INT1_HI_DSPI_TCF (35) +#define INT1_HI_DSPI_TFUF (36) +#define INT1_HI_DSPI_RFDF (37) +#define INT1_HI_DSPI_RFOF (38) +#define INT1_HI_DSPI_RFOF_TFUF (39) +#define INT1_HI_RNG_EI (40) +#define INT1_HI_PIT0_PIF (43) +#define INT1_HI_PIT1_PIF (44) +#define INT1_HI_PIT2_PIF (45) +#define INT1_HI_PIT3_PIF (46) +#define INT1_HI_USBOTG_USBSTS (47) +#define INT1_HI_SSI_ISR (49) +#define INT1_HI_CCM_UOCSR (53) +#define INT1_HI_ATA_ISR (54) +#define INT1_HI_PCI_SCR (55) +#define INT1_HI_PCI_ASR (56) +#define INT1_HI_PLL_LOCKS (57) + +/* Bit definitions and macros for IPRH */ +#define INTC_IPRH_INT32 (0x00000001) +#define INTC_IPRH_INT33 (0x00000002) +#define INTC_IPRH_INT34 (0x00000004) +#define INTC_IPRH_INT35 (0x00000008) +#define INTC_IPRH_INT36 (0x00000010) +#define INTC_IPRH_INT37 (0x00000020) +#define INTC_IPRH_INT38 (0x00000040) +#define INTC_IPRH_INT39 (0x00000080) +#define INTC_IPRH_INT40 (0x00000100) +#define INTC_IPRH_INT41 (0x00000200) +#define INTC_IPRH_INT42 (0x00000400) +#define INTC_IPRH_INT43 (0x00000800) +#define INTC_IPRH_INT44 (0x00001000) +#define INTC_IPRH_INT45 (0x00002000) +#define INTC_IPRH_INT46 (0x00004000) +#define INTC_IPRH_INT47 (0x00008000) +#define INTC_IPRH_INT48 (0x00010000) +#define INTC_IPRH_INT49 (0x00020000) +#define INTC_IPRH_INT50 (0x00040000) +#define INTC_IPRH_INT51 (0x00080000) +#define INTC_IPRH_INT52 (0x00100000) +#define INTC_IPRH_INT53 (0x00200000) +#define INTC_IPRH_INT54 (0x00400000) +#define INTC_IPRH_INT55 (0x00800000) +#define INTC_IPRH_INT56 (0x01000000) +#define INTC_IPRH_INT57 (0x02000000) +#define INTC_IPRH_INT58 (0x04000000) +#define INTC_IPRH_INT59 (0x08000000) +#define INTC_IPRH_INT60 (0x10000000) +#define INTC_IPRH_INT61 (0x20000000) +#define INTC_IPRH_INT62 (0x40000000) +#define INTC_IPRH_INT63 (0x80000000) + +/* Bit definitions and macros for IPRL */ +#define INTC_IPRL_INT0 (0x00000001) +#define INTC_IPRL_INT1 (0x00000002) +#define INTC_IPRL_INT2 (0x00000004) +#define INTC_IPRL_INT3 (0x00000008) +#define INTC_IPRL_INT4 (0x00000010) +#define INTC_IPRL_INT5 (0x00000020) +#define INTC_IPRL_INT6 (0x00000040) +#define INTC_IPRL_INT7 (0x00000080) +#define INTC_IPRL_INT8 (0x00000100) +#define INTC_IPRL_INT9 (0x00000200) +#define INTC_IPRL_INT10 (0x00000400) +#define INTC_IPRL_INT11 (0x00000800) +#define INTC_IPRL_INT12 (0x00001000) +#define INTC_IPRL_INT13 (0x00002000) +#define INTC_IPRL_INT14 (0x00004000) +#define INTC_IPRL_INT15 (0x00008000) +#define INTC_IPRL_INT16 (0x00010000) +#define INTC_IPRL_INT17 (0x00020000) +#define INTC_IPRL_INT18 (0x00040000) +#define INTC_IPRL_INT19 (0x00080000) +#define INTC_IPRL_INT20 (0x00100000) +#define INTC_IPRL_INT21 (0x00200000) +#define INTC_IPRL_INT22 (0x00400000) +#define INTC_IPRL_INT23 (0x00800000) +#define INTC_IPRL_INT24 (0x01000000) +#define INTC_IPRL_INT25 (0x02000000) +#define INTC_IPRL_INT26 (0x04000000) +#define INTC_IPRL_INT27 (0x08000000) +#define INTC_IPRL_INT28 (0x10000000) +#define INTC_IPRL_INT29 (0x20000000) +#define INTC_IPRL_INT30 (0x40000000) +#define INTC_IPRL_INT31 (0x80000000) + +/* Bit definitions and macros for IMRH */ +#define INTC_IMRH_INT_MASK32 (0x00000001) +#define INTC_IMRH_INT_MASK33 (0x00000002) +#define INTC_IMRH_INT_MASK34 (0x00000004) +#define INTC_IMRH_INT_MASK35 (0x00000008) +#define INTC_IMRH_INT_MASK36 (0x00000010) +#define INTC_IMRH_INT_MASK37 (0x00000020) +#define INTC_IMRH_INT_MASK38 (0x00000040) +#define INTC_IMRH_INT_MASK39 (0x00000080) +#define INTC_IMRH_INT_MASK40 (0x00000100) +#define INTC_IMRH_INT_MASK41 (0x00000200) +#define INTC_IMRH_INT_MASK42 (0x00000400) +#define INTC_IMRH_INT_MASK43 (0x00000800) +#define INTC_IMRH_INT_MASK44 (0x00001000) +#define INTC_IMRH_INT_MASK45 (0x00002000) +#define INTC_IMRH_INT_MASK46 (0x00004000) +#define INTC_IMRH_INT_MASK47 (0x00008000) +#define INTC_IMRH_INT_MASK48 (0x00010000) +#define INTC_IMRH_INT_MASK49 (0x00020000) +#define INTC_IMRH_INT_MASK50 (0x00040000) +#define INTC_IMRH_INT_MASK51 (0x00080000) +#define INTC_IMRH_INT_MASK52 (0x00100000) +#define INTC_IMRH_INT_MASK53 (0x00200000) +#define INTC_IMRH_INT_MASK54 (0x00400000) +#define INTC_IMRH_INT_MASK55 (0x00800000) +#define INTC_IMRH_INT_MASK56 (0x01000000) +#define INTC_IMRH_INT_MASK57 (0x02000000) +#define INTC_IMRH_INT_MASK58 (0x04000000) +#define INTC_IMRH_INT_MASK59 (0x08000000) +#define INTC_IMRH_INT_MASK60 (0x10000000) +#define INTC_IMRH_INT_MASK61 (0x20000000) +#define INTC_IMRH_INT_MASK62 (0x40000000) +#define INTC_IMRH_INT_MASK63 (0x80000000) + +/* Bit definitions and macros for IMRL */ +#define INTC_IMRL_INT_MASK0 (0x00000001) +#define INTC_IMRL_INT_MASK1 (0x00000002) +#define INTC_IMRL_INT_MASK2 (0x00000004) +#define INTC_IMRL_INT_MASK3 (0x00000008) +#define INTC_IMRL_INT_MASK4 (0x00000010) +#define INTC_IMRL_INT_MASK5 (0x00000020) +#define INTC_IMRL_INT_MASK6 (0x00000040) +#define INTC_IMRL_INT_MASK7 (0x00000080) +#define INTC_IMRL_INT_MASK8 (0x00000100) +#define INTC_IMRL_INT_MASK9 (0x00000200) +#define INTC_IMRL_INT_MASK10 (0x00000400) +#define INTC_IMRL_INT_MASK11 (0x00000800) +#define INTC_IMRL_INT_MASK12 (0x00001000) +#define INTC_IMRL_INT_MASK13 (0x00002000) +#define INTC_IMRL_INT_MASK14 (0x00004000) +#define INTC_IMRL_INT_MASK15 (0x00008000) +#define INTC_IMRL_INT_MASK16 (0x00010000) +#define INTC_IMRL_INT_MASK17 (0x00020000) +#define INTC_IMRL_INT_MASK18 (0x00040000) +#define INTC_IMRL_INT_MASK19 (0x00080000) +#define INTC_IMRL_INT_MASK20 (0x00100000) +#define INTC_IMRL_INT_MASK21 (0x00200000) +#define INTC_IMRL_INT_MASK22 (0x00400000) +#define INTC_IMRL_INT_MASK23 (0x00800000) +#define INTC_IMRL_INT_MASK24 (0x01000000) +#define INTC_IMRL_INT_MASK25 (0x02000000) +#define INTC_IMRL_INT_MASK26 (0x04000000) +#define INTC_IMRL_INT_MASK27 (0x08000000) +#define INTC_IMRL_INT_MASK28 (0x10000000) +#define INTC_IMRL_INT_MASK29 (0x20000000) +#define INTC_IMRL_INT_MASK30 (0x40000000) +#define INTC_IMRL_INT_MASK31 (0x80000000) + +/* Bit definitions and macros for INTFRCH */ +#define INTC_INTFRCH_INTFRC32 (0x00000001) +#define INTC_INTFRCH_INTFRC33 (0x00000002) +#define INTC_INTFRCH_INTFRC34 (0x00000004) +#define INTC_INTFRCH_INTFRC35 (0x00000008) +#define INTC_INTFRCH_INTFRC36 (0x00000010) +#define INTC_INTFRCH_INTFRC37 (0x00000020) +#define INTC_INTFRCH_INTFRC38 (0x00000040) +#define INTC_INTFRCH_INTFRC39 (0x00000080) +#define INTC_INTFRCH_INTFRC40 (0x00000100) +#define INTC_INTFRCH_INTFRC41 (0x00000200) +#define INTC_INTFRCH_INTFRC42 (0x00000400) +#define INTC_INTFRCH_INTFRC43 (0x00000800) +#define INTC_INTFRCH_INTFRC44 (0x00001000) +#define INTC_INTFRCH_INTFRC45 (0x00002000) +#define INTC_INTFRCH_INTFRC46 (0x00004000) +#define INTC_INTFRCH_INTFRC47 (0x00008000) +#define INTC_INTFRCH_INTFRC48 (0x00010000) +#define INTC_INTFRCH_INTFRC49 (0x00020000) +#define INTC_INTFRCH_INTFRC50 (0x00040000) +#define INTC_INTFRCH_INTFRC51 (0x00080000) +#define INTC_INTFRCH_INTFRC52 (0x00100000) +#define INTC_INTFRCH_INTFRC53 (0x00200000) +#define INTC_INTFRCH_INTFRC54 (0x00400000) +#define INTC_INTFRCH_INTFRC55 (0x00800000) +#define INTC_INTFRCH_INTFRC56 (0x01000000) +#define INTC_INTFRCH_INTFRC57 (0x02000000) +#define INTC_INTFRCH_INTFRC58 (0x04000000) +#define INTC_INTFRCH_INTFRC59 (0x08000000) +#define INTC_INTFRCH_INTFRC60 (0x10000000) +#define INTC_INTFRCH_INTFRC61 (0x20000000) +#define INTC_INTFRCH_INTFRC62 (0x40000000) +#define INTC_INTFRCH_INTFRC63 (0x80000000) + +/* Bit definitions and macros for INTFRCL */ +#define INTC_INTFRCL_INTFRC0 (0x00000001) +#define INTC_INTFRCL_INTFRC1 (0x00000002) +#define INTC_INTFRCL_INTFRC2 (0x00000004) +#define INTC_INTFRCL_INTFRC3 (0x00000008) +#define INTC_INTFRCL_INTFRC4 (0x00000010) +#define INTC_INTFRCL_INTFRC5 (0x00000020) +#define INTC_INTFRCL_INTFRC6 (0x00000040) +#define INTC_INTFRCL_INTFRC7 (0x00000080) +#define INTC_INTFRCL_INTFRC8 (0x00000100) +#define INTC_INTFRCL_INTFRC9 (0x00000200) +#define INTC_INTFRCL_INTFRC10 (0x00000400) +#define INTC_INTFRCL_INTFRC11 (0x00000800) +#define INTC_INTFRCL_INTFRC12 (0x00001000) +#define INTC_INTFRCL_INTFRC13 (0x00002000) +#define INTC_INTFRCL_INTFRC14 (0x00004000) +#define INTC_INTFRCL_INTFRC15 (0x00008000) +#define INTC_INTFRCL_INTFRC16 (0x00010000) +#define INTC_INTFRCL_INTFRC17 (0x00020000) +#define INTC_INTFRCL_INTFRC18 (0x00040000) +#define INTC_INTFRCL_INTFRC19 (0x00080000) +#define INTC_INTFRCL_INTFRC20 (0x00100000) +#define INTC_INTFRCL_INTFRC21 (0x00200000) +#define INTC_INTFRCL_INTFRC22 (0x00400000) +#define INTC_INTFRCL_INTFRC23 (0x00800000) +#define INTC_INTFRCL_INTFRC24 (0x01000000) +#define INTC_INTFRCL_INTFRC25 (0x02000000) +#define INTC_INTFRCL_INTFRC26 (0x04000000) +#define INTC_INTFRCL_INTFRC27 (0x08000000) +#define INTC_INTFRCL_INTFRC28 (0x10000000) +#define INTC_INTFRCL_INTFRC29 (0x20000000) +#define INTC_INTFRCL_INTFRC30 (0x40000000) +#define INTC_INTFRCL_INTFRC31 (0x80000000) + +/* Bit definitions and macros for ICONFIG */ +#define INTC_ICONFIG_EMASK (0x0020) +#define INTC_ICONFIG_ELVLPRI1 (0x0200) +#define INTC_ICONFIG_ELVLPRI2 (0x0400) +#define INTC_ICONFIG_ELVLPRI3 (0x0800) +#define INTC_ICONFIG_ELVLPRI4 (0x1000) +#define INTC_ICONFIG_ELVLPRI5 (0x2000) +#define INTC_ICONFIG_ELVLPRI6 (0x4000) +#define INTC_ICONFIG_ELVLPRI7 (0x8000) + +/* Bit definitions and macros for SIMR */ +#define INTC_SIMR_SIMR(x) (((x)&0x7F)) + +/* Bit definitions and macros for CIMR */ +#define INTC_CIMR_CIMR(x) (((x)&0x7F)) + +/* Bit definitions and macros for CLMASK */ +#define INTC_CLMASK_CLMASK(x) (((x)&0x0F)) + +/* Bit definitions and macros for SLMASK */ +#define INTC_SLMASK_SLMASK(x) (((x)&0x0F)) + +/* Bit definitions and macros for ICR group */ +#define INTC_ICR_IL(x) (((x)&0x07)) + +/********************************************************************* +* DMA Serial Peripheral Interface (DSPI) +*********************************************************************/ + +/* Bit definitions and macros for DMCR */ +#define DSPI_DMCR_HALT (0x00000001) +#define DSPI_DMCR_SMPL_PT(x) (((x)&0x00000003)<<8) +#define DSPI_DMCR_CRXF (0x00000400) +#define DSPI_DMCR_CTXF (0x00000800) +#define DSPI_DMCR_DRXF (0x00001000) +#define DSPI_DMCR_DTXF (0x00002000) +#define DSPI_DMCR_CSIS0 (0x00010000) +#define DSPI_DMCR_CSIS2 (0x00040000) +#define DSPI_DMCR_CSIS3 (0x00080000) +#define DSPI_DMCR_CSIS5 (0x00200000) +#define DSPI_DMCR_ROOE (0x01000000) +#define DSPI_DMCR_PCSSE (0x02000000) +#define DSPI_DMCR_MTFE (0x04000000) +#define DSPI_DMCR_FRZ (0x08000000) +#define DSPI_DMCR_DCONF(x) (((x)&0x00000003)<<28) +#define DSPI_DMCR_CSCK (0x40000000) +#define DSPI_DMCR_MSTR (0x80000000) + +/* Bit definitions and macros for DTCR */ +#define DSPI_DTCR_SPI_TCNT(x) (((x)&0x0000FFFF)<<16) + +/* Bit definitions and macros for DCTAR group */ +#define DSPI_DCTAR_BR(x) (((x)&0x0000000F)) +#define DSPI_DCTAR_DT(x) (((x)&0x0000000F)<<4) +#define DSPI_DCTAR_ASC(x) (((x)&0x0000000F)<<8) +#define DSPI_DCTAR_CSSCK(x) (((x)&0x0000000F)<<12) +#define DSPI_DCTAR_PBR(x) (((x)&0x00000003)<<16) +#define DSPI_DCTAR_PDT(x) (((x)&0x00000003)<<18) +#define DSPI_DCTAR_PASC(x) (((x)&0x00000003)<<20) +#define DSPI_DCTAR_PCSSCK(x) (((x)&0x00000003)<<22) +#define DSPI_DCTAR_LSBFE (0x01000000) +#define DSPI_DCTAR_CPHA (0x02000000) +#define DSPI_DCTAR_CPOL (0x04000000) +#define DSPI_DCTAR_TRSZ(x) (((x)&0x0000000F)<<27) +#define DSPI_DCTAR_PCSSCK_1CLK (0x00000000) +#define DSPI_DCTAR_PCSSCK_3CLK (0x00400000) +#define DSPI_DCTAR_PCSSCK_5CLK (0x00800000) +#define DSPI_DCTAR_PCSSCK_7CLK (0x00A00000) +#define DSPI_DCTAR_PASC_1CLK (0x00000000) +#define DSPI_DCTAR_PASC_3CLK (0x00100000) +#define DSPI_DCTAR_PASC_5CLK (0x00200000) +#define DSPI_DCTAR_PASC_7CLK (0x00300000) +#define DSPI_DCTAR_PDT_1CLK (0x00000000) +#define DSPI_DCTAR_PDT_3CLK (0x00040000) +#define DSPI_DCTAR_PDT_5CLK (0x00080000) +#define DSPI_DCTAR_PDT_7CLK (0x000A0000) +#define DSPI_DCTAR_PBR_1CLK (0x00000000) +#define DSPI_DCTAR_PBR_3CLK (0x00010000) +#define DSPI_DCTAR_PBR_5CLK (0x00020000) +#define DSPI_DCTAR_PBR_7CLK (0x00030000) + +/* Bit definitions and macros for DSR */ +#define DSPI_DSR_RXPTR(x) (((x)&0x0000000F)) +#define DSPI_DSR_RXCTR(x) (((x)&0x0000000F)<<4) +#define DSPI_DSR_TXPTR(x) (((x)&0x0000000F)<<8) +#define DSPI_DSR_TXCTR(x) (((x)&0x0000000F)<<12) +#define DSPI_DSR_RFDF (0x00020000) +#define DSPI_DSR_RFOF (0x00080000) +#define DSPI_DSR_TFFF (0x02000000) +#define DSPI_DSR_TFUF (0x08000000) +#define DSPI_DSR_EOQF (0x10000000) +#define DSPI_DSR_TXRXS (0x40000000) +#define DSPI_DSR_TCF (0x80000000) + +/* Bit definitions and macros for DIRSR */ +#define DSPI_DIRSR_RFDFS (0x00010000) +#define DSPI_DIRSR_RFDFE (0x00020000) +#define DSPI_DIRSR_RFOFE (0x00080000) +#define DSPI_DIRSR_TFFFS (0x01000000) +#define DSPI_DIRSR_TFFFE (0x02000000) +#define DSPI_DIRSR_TFUFE (0x08000000) +#define DSPI_DIRSR_EOQFE (0x10000000) +#define DSPI_DIRSR_TCFE (0x80000000) + +/* Bit definitions and macros for DTFR */ +#define DSPI_DTFR_TXDATA(x) (((x)&0x0000FFFF)) +#define DSPI_DTFR_CS0 (0x00010000) +#define DSPI_DTFR_CS2 (0x00040000) +#define DSPI_DTFR_CS3 (0x00080000) +#define DSPI_DTFR_CS5 (0x00200000) +#define DSPI_DTFR_CTCNT (0x04000000) +#define DSPI_DTFR_EOQ (0x08000000) +#define DSPI_DTFR_CTAS(x) (((x)&0x00000007)<<28) +#define DSPI_DTFR_CONT (0x80000000) + +/* Bit definitions and macros for DRFR */ +#define DSPI_DRFR_RXDATA(x) (((x)&0x0000FFFF)) + +/* Bit definitions and macros for DTFDR group */ +#define DSPI_DTFDR_TXDATA(x) (((x)&0x0000FFFF)) +#define DSPI_DTFDR_TXCMD(x) (((x)&0x0000FFFF)<<16) + +/* Bit definitions and macros for DRFDR group */ +#define DSPI_DRFDR_RXDATA(x) (((x)&0x0000FFFF)) + +/********************************************************************* +* Edge Port Module (EPORT) +*********************************************************************/ + +/* Bit definitions and macros for EPPAR */ +#define EPORT_EPPAR_EPPA1(x) (((x)&0x0003)<<2) +#define EPORT_EPPAR_EPPA2(x) (((x)&0x0003)<<4) +#define EPORT_EPPAR_EPPA3(x) (((x)&0x0003)<<6) +#define EPORT_EPPAR_EPPA4(x) (((x)&0x0003)<<8) +#define EPORT_EPPAR_EPPA5(x) (((x)&0x0003)<<10) +#define EPORT_EPPAR_EPPA6(x) (((x)&0x0003)<<12) +#define EPORT_EPPAR_EPPA7(x) (((x)&0x0003)<<14) +#define EPORT_EPPAR_LEVEL (0) +#define EPORT_EPPAR_RISING (1) +#define EPORT_EPPAR_FALLING (2) +#define EPORT_EPPAR_BOTH (3) +#define EPORT_EPPAR_EPPA7_LEVEL (0x0000) +#define EPORT_EPPAR_EPPA7_RISING (0x4000) +#define EPORT_EPPAR_EPPA7_FALLING (0x8000) +#define EPORT_EPPAR_EPPA7_BOTH (0xC000) +#define EPORT_EPPAR_EPPA6_LEVEL (0x0000) +#define EPORT_EPPAR_EPPA6_RISING (0x1000) +#define EPORT_EPPAR_EPPA6_FALLING (0x2000) +#define EPORT_EPPAR_EPPA6_BOTH (0x3000) +#define EPORT_EPPAR_EPPA5_LEVEL (0x0000) +#define EPORT_EPPAR_EPPA5_RISING (0x0400) +#define EPORT_EPPAR_EPPA5_FALLING (0x0800) +#define EPORT_EPPAR_EPPA5_BOTH (0x0C00) +#define EPORT_EPPAR_EPPA4_LEVEL (0x0000) +#define EPORT_EPPAR_EPPA4_RISING (0x0100) +#define EPORT_EPPAR_EPPA4_FALLING (0x0200) +#define EPORT_EPPAR_EPPA4_BOTH (0x0300) +#define EPORT_EPPAR_EPPA3_LEVEL (0x0000) +#define EPORT_EPPAR_EPPA3_RISING (0x0040) +#define EPORT_EPPAR_EPPA3_FALLING (0x0080) +#define EPORT_EPPAR_EPPA3_BOTH (0x00C0) +#define EPORT_EPPAR_EPPA2_LEVEL (0x0000) +#define EPORT_EPPAR_EPPA2_RISING (0x0010) +#define EPORT_EPPAR_EPPA2_FALLING (0x0020) +#define EPORT_EPPAR_EPPA2_BOTH (0x0030) +#define EPORT_EPPAR_EPPA1_LEVEL (0x0000) +#define EPORT_EPPAR_EPPA1_RISING (0x0004) +#define EPORT_EPPAR_EPPA1_FALLING (0x0008) +#define EPORT_EPPAR_EPPA1_BOTH (0x000C) + +/* Bit definitions and macros for EPDDR */ +#define EPORT_EPDDR_EPDD1 (0x02) +#define EPORT_EPDDR_EPDD2 (0x04) +#define EPORT_EPDDR_EPDD3 (0x08) +#define EPORT_EPDDR_EPDD4 (0x10) +#define EPORT_EPDDR_EPDD5 (0x20) +#define EPORT_EPDDR_EPDD6 (0x40) +#define EPORT_EPDDR_EPDD7 (0x80) + +/* Bit definitions and macros for EPIER */ +#define EPORT_EPIER_EPIE1 (0x02) +#define EPORT_EPIER_EPIE2 (0x04) +#define EPORT_EPIER_EPIE3 (0x08) +#define EPORT_EPIER_EPIE4 (0x10) +#define EPORT_EPIER_EPIE5 (0x20) +#define EPORT_EPIER_EPIE6 (0x40) +#define EPORT_EPIER_EPIE7 (0x80) + +/* Bit definitions and macros for EPDR */ +#define EPORT_EPDR_EPD1 (0x02) +#define EPORT_EPDR_EPD2 (0x04) +#define EPORT_EPDR_EPD3 (0x08) +#define EPORT_EPDR_EPD4 (0x10) +#define EPORT_EPDR_EPD5 (0x20) +#define EPORT_EPDR_EPD6 (0x40) +#define EPORT_EPDR_EPD7 (0x80) + +/* Bit definitions and macros for EPPDR */ +#define EPORT_EPPDR_EPPD1 (0x02) +#define EPORT_EPPDR_EPPD2 (0x04) +#define EPORT_EPPDR_EPPD3 (0x08) +#define EPORT_EPPDR_EPPD4 (0x10) +#define EPORT_EPPDR_EPPD5 (0x20) +#define EPORT_EPPDR_EPPD6 (0x40) +#define EPORT_EPPDR_EPPD7 (0x80) + +/* Bit definitions and macros for EPFR */ +#define EPORT_EPFR_EPF1 (0x02) +#define EPORT_EPFR_EPF2 (0x04) +#define EPORT_EPFR_EPF3 (0x08) +#define EPORT_EPFR_EPF4 (0x10) +#define EPORT_EPFR_EPF5 (0x20) +#define EPORT_EPFR_EPF6 (0x40) +#define EPORT_EPFR_EPF7 (0x80) + +/********************************************************************* +* Watchdog Timer Modules (WTM) +*********************************************************************/ + +/* Bit definitions and macros for WCR */ +#define WTM_WCR_EN (0x0001) +#define WTM_WCR_HALTED (0x0002) +#define WTM_WCR_DOZE (0x0004) +#define WTM_WCR_WAIT (0x0008) + +/********************************************************************* +* Serial Boot Facility (SBF) +*********************************************************************/ + +/* Bit definitions and macros for SBFCR */ +#define SBF_SBFCR_BLDIV(x) (((x)&0x000F)) /* Boot loader clock divider */ +#define SBF_SBFCR_FR (0x0010) /* Fast read */ + +/********************************************************************* +* Reset Controller Module (RCM) +*********************************************************************/ + +/* Bit definitions and macros for RCR */ +#define RCM_RCR_FRCRSTOUT (0x40) +#define RCM_RCR_SOFTRST (0x80) + +/* Bit definitions and macros for RSR */ +#define RCM_RSR_LOL (0x01) +#define RCM_RSR_WDR_CORE (0x02) +#define RCM_RSR_EXT (0x04) +#define RCM_RSR_POR (0x08) +#define RCM_RSR_SOFT (0x20) + +/********************************************************************* +* Chip Configuration Module (CCM) +*********************************************************************/ + +/* Bit definitions and macros for CCR_360 */ +#define CCM_CCR_360_PLLMULT2(x) (((x)&0x0003)) /* 2-Bit PLL clock mode */ +#define CCM_CCR_360_PCISLEW (0x0004) /* PCI pad slew rate mode */ +#define CCM_CCR_360_PCIMODE (0x0008) /* PCI host/agent mode */ +#define CCM_CCR_360_PLLMODE (0x0010) /* PLL Mode */ +#define CCM_CCR_360_FBCONFIG(x) (((x)&0x0007)<<5) /* Flexbus/PCI port size configuration */ +#define CCM_CCR_360_PLLMULT3(x) (((x)&0x0007)) /* 3-Bit PLL Clock Mode */ +#define CCM_CCR_360_OSCMODE (0x0008) /* Oscillator Clock Mode */ +#define CCM_CCR_360_FBCONFIG_MASK (0x00E0) +#define CCM_CCR_360_PLLMULT2_MASK (0x0003) +#define CCM_CCR_360_PLLMULT3_MASK (0x0007) +#define CCM_CCR_360_FBCONFIG_NM_NP_32 (0x0000) +#define CCM_CCR_360_FBCONFIG_NM_NP_8 (0x0020) +#define CCM_CCR_360_FBCONFIG_NM_NP_16 (0x0040) +#define CCM_CCR_360_FBCONFIG_M_P_16 (0x0060) +#define CCM_CCR_360_FBCONFIG_M_NP_32 (0x0080) +#define CCM_CCR_360_FBCONFIG_M_NP_8 (0x00A0) +#define CCM_CCR_360_FBCONFIG_M_NP_16 (0x00C0) +#define CCM_CCR_360_FBCONFIG_M_P_8 (0x00E0) +#define CCM_CCR_360_PLLMULT2_12X (0x0000) +#define CCM_CCR_360_PLLMULT2_6X (0x0001) +#define CCM_CCR_360_PLLMULT2_16X (0x0002) +#define CCM_CCR_360_PLLMULT2_8X (0x0003) +#define CCM_CCR_360_PLLMULT3_20X (0x0000) +#define CCM_CCR_360_PLLMULT3_10X (0x0001) +#define CCM_CCR_360_PLLMULT3_24X (0x0002) +#define CCM_CCR_360_PLLMULT3_18X (0x0003) +#define CCM_CCR_360_PLLMULT3_12X (0x0004) +#define CCM_CCR_360_PLLMULT3_6X (0x0005) +#define CCM_CCR_360_PLLMULT3_16X (0x0006) +#define CCM_CCR_360_PLLMULT3_8X (0x0007) + +/* Bit definitions and macros for CCR_256 */ +#define CCM_CCR_256_PLLMULT3(x) (((x)&0x0007)) /* 3-Bit PLL clock mode */ +#define CCM_CCR_256_OSCMODE (0x0008) /* Oscillator clock mode */ +#define CCM_CCR_256_PLLMODE (0x0010) /* PLL Mode */ +#define CCM_CCR_256_FBCONFIG(x) (((x)&0x0007)<<5) /* Flexbus/PCI port size configuration */ +#define CCM_CCR_256_FBCONFIG_MASK (0x00E0) +#define CCM_CCR_256_FBCONFIG_NM_32 (0x0000) +#define CCM_CCR_256_FBCONFIG_NM_8 (0x0020) +#define CCM_CCR_256_FBCONFIG_NM_16 (0x0040) +#define CCM_CCR_256_FBCONFIG_M_32 (0x0080) +#define CCM_CCR_256_FBCONFIG_M_8 (0x00A0) +#define CCM_CCR_256_FBCONFIG_M_16 (0x00C0) +#define CCM_CCR_256_PLLMULT3_MASK (0x0007) +#define CCM_CCR_256_PLLMULT3_20X (0x0000) +#define CCM_CCR_256_PLLMULT3_10X (0x0001) +#define CCM_CCR_256_PLLMULT3_24X (0x0002) +#define CCM_CCR_256_PLLMULT3_18X (0x0003) +#define CCM_CCR_256_PLLMULT3_12X (0x0004) +#define CCM_CCR_256_PLLMULT3_6X (0x0005) +#define CCM_CCR_256_PLLMULT3_16X (0x0006) +#define CCM_CCR_256_PLLMULT3_8X (0x0007) + +/* Bit definitions and macros for RCON_360 */ +#define CCM_RCON_360_PLLMULT(x) (((x)&0x0003)) /* PLL clock mode */ +#define CCM_RCON_360_PCISLEW (0x0004) /* PCI pad slew rate mode */ +#define CCM_RCON_360_PCIMODE (0x0008) /* PCI host/agent mode */ +#define CCM_RCON_360_PLLMODE (0x0010) /* PLL Mode */ +#define CCM_RCON_360_FBCONFIG(x) (((x)&0x0007)<<5) /* Flexbus/PCI port size configuration */ + +/* Bit definitions and macros for RCON_256 */ +#define CCM_RCON_256_PLLMULT(x) (((x)&0x0007)) /* PLL clock mode */ +#define CCM_RCON_256_OSCMODE (0x0008) /* Oscillator clock mode */ +#define CCM_RCON_256_PLLMODE (0x0010) /* PLL Mode */ +#define CCM_RCON_256_FBCONFIG(x) (((x)&0x0007)<<5) /* Flexbus/PCI port size configuration */ + +/* Bit definitions and macros for CIR */ +#define CCM_CIR_PRN(x) (((x)&0x003F)) /* Part revision number */ +#define CCM_CIR_PIN(x) (((x)&0x03FF)<<6) /* Part identification number */ +#define CCM_CIR_PIN_MASK (0xFFC0) +#define CCM_CIR_PRN_MASK (0x003F) +#define CCM_CIR_PIN_MCF54450 (0x4F<<6) +#define CCM_CIR_PIN_MCF54451 (0x4D<<6) +#define CCM_CIR_PIN_MCF54452 (0x4B<<6) +#define CCM_CIR_PIN_MCF54453 (0x49<<6) +#define CCM_CIR_PIN_MCF54454 (0x4A<<6) +#define CCM_CIR_PIN_MCF54455 (0x48<<6) + +/* Bit definitions and macros for MISCCR */ +#define CCM_MISCCR_USBSRC (0x0001) /* USB clock source */ +#define CCM_MISCCR_USBOC (0x0002) /* USB VBUS over-current sense polarity */ +#define CCM_MISCCR_USBPUE (0x0004) /* USB transceiver pull-up enable */ +#define CCM_MISCCR_SSISRC (0x0010) /* SSI clock source */ +#define CCM_MISCCR_TIMDMA (0x0020) /* Timer DMA mux selection */ +#define CCM_MISCCR_SSIPUS (0x0040) /* SSI RXD/TXD pull select */ +#define CCM_MISCCR_SSIPUE (0x0080) /* SSI RXD/TXD pull enable */ +#define CCM_MISCCR_BMT(x) (((x)&0x0007)<<8) /* Bus monitor timing field */ +#define CCM_MISCCR_BME (0x0800) /* Bus monitor external enable bit */ +#define CCM_MISCCR_LIMP (0x1000) /* Limp mode enable */ +#define CCM_MISCCR_BMT_65536 (0) +#define CCM_MISCCR_BMT_32768 (1) +#define CCM_MISCCR_BMT_16384 (2) +#define CCM_MISCCR_BMT_8192 (3) +#define CCM_MISCCR_BMT_4096 (4) +#define CCM_MISCCR_BMT_2048 (5) +#define CCM_MISCCR_BMT_1024 (6) +#define CCM_MISCCR_BMT_512 (7) +#define CCM_MISCCR_SSIPUS_UP (1) +#define CCM_MISCCR_SSIPUS_DOWN (0) +#define CCM_MISCCR_TIMDMA_TIM (1) +#define CCM_MISCCR_TIMDMA_SSI (0) +#define CCM_MISCCR_SSISRC_CLKIN (0) +#define CCM_MISCCR_SSISRC_PLL (1) +#define CCM_MISCCR_USBOC_ACTHI (0) +#define CCM_MISCCR_USBOV_ACTLO (1) +#define CCM_MISCCR_USBSRC_CLKIN (0) +#define CCM_MISCCR_USBSRC_PLL (1) + +/* Bit definitions and macros for CDR */ +#define CCM_CDR_SSIDIV(x) (((x)&0x00FF)) /* SSI oversampling clock divider */ +#define CCM_CDR_LPDIV(x) (((x)&0x000F)<<8) /* Low power clock divider */ + +/* Bit definitions and macros for UOCSR */ +#define CCM_UOCSR_XPDE (0x0001) /* On-chip transceiver pull-down enable */ +#define CCM_UOCSR_UOMIE (0x0002) /* USB OTG misc interrupt enable */ +#define CCM_UOCSR_WKUP (0x0004) /* USB OTG controller wake-up event */ +#define CCM_UOCSR_PWRFLT (0x0008) /* VBUS power fault */ +#define CCM_UOCSR_SEND (0x0010) /* Session end */ +#define CCM_UOCSR_VVLD (0x0020) /* VBUS valid indicator */ +#define CCM_UOCSR_BVLD (0x0040) /* B-peripheral valid indicator */ +#define CCM_UOCSR_AVLD (0x0080) /* A-peripheral valid indicator */ +#define CCM_UOCSR_DPPU (0x0100) /* D+ pull-up for FS enabled (read-only) */ +#define CCM_UOCSR_DCR_VBUS (0x0200) /* VBUS discharge resistor enabled (read-only) */ +#define CCM_UOCSR_CRG_VBUS (0x0400) /* VBUS charge resistor enabled (read-only) */ +#define CCM_UOCSR_DMPD (0x1000) /* D- 15Kohm pull-down (read-only) */ +#define CCM_UOCSR_DPPD (0x2000) /* D+ 15Kohm pull-down (read-only) */ + +/********************************************************************* +* General Purpose I/O Module (GPIO) +*********************************************************************/ + +/* Bit definitions and macros for PAR_FEC */ +#define GPIO_PAR_FEC_FEC0(x) (((x)&0x07)) +#define GPIO_PAR_FEC_FEC1(x) (((x)&0x07)<<4) +#define GPIO_PAR_FEC_FEC1_MASK (0x8F) +#define GPIO_PAR_FEC_FEC1_MII (0x70) +#define GPIO_PAR_FEC_FEC1_RMII_GPIO (0x30) +#define GPIO_PAR_FEC_FEC1_RMII_ATA (0x20) +#define GPIO_PAR_FEC_FEC1_ATA (0x10) +#define GPIO_PAR_FEC_FEC1_GPIO (0x00) +#define GPIO_PAR_FEC_FEC0_MASK (0xF8) +#define GPIO_PAR_FEC_FEC0_MII (0x07) +#define GPIO_PAR_FEC_FEC0_RMII_GPIO (0x03) +#define GPIO_PAR_FEC_FEC0_RMII_ATA (0x02) +#define GPIO_PAR_FEC_FEC0_ATA (0x01) +#define GPIO_PAR_FEC_FEC0_GPIO (0x00) + +/* Bit definitions and macros for PAR_DMA */ +#define GPIO_PAR_DMA_DREQ0 (0x01) +#define GPIO_PAR_DMA_DACK0(x) (((x)&0x03)<<2) +#define GPIO_PAR_DMA_DREQ1(x) (((x)&0x03)<<4) +#define GPIO_PAR_DMA_DACK1(x) (((x)&0x03)<<6) +#define GPIO_PAR_DMA_DACK1_MASK (0x3F) +#define GPIO_PAR_DMA_DACK1_DACK1 (0xC0) +#define GPIO_PAR_DMA_DACK1_ULPI_DIR (0x40) +#define GPIO_PAR_DMA_DACK1_GPIO (0x00) +#define GPIO_PAR_DMA_DREQ1_MASK (0xCF) +#define GPIO_PAR_DMA_DREQ1_DREQ1 (0x30) +#define GPIO_PAR_DMA_DREQ1_USB_CLKIN (0x10) +#define GPIO_PAR_DMA_DREQ1_GPIO (0x00) +#define GPIO_PAR_DMA_DACK0_MASK (0xF3) +#define GPIO_PAR_DMA_DACK0_DACK1 (0x0C) +#define GPIO_PAR_DMA_DACK0_ULPI_DIR (0x04) +#define GPIO_PAR_DMA_DACK0_GPIO (0x00) +#define GPIO_PAR_DMA_DREQ0_DREQ0 (0x01) +#define GPIO_PAR_DMA_DREQ0_GPIO (0x00) + +/* Bit definitions and macros for PAR_FBCTL */ +#define GPIO_PAR_FBCTL_TS(x) (((x)&0x03)<<3) +#define GPIO_PAR_FBCTL_RW (0x20) +#define GPIO_PAR_FBCTL_TA (0x40) +#define GPIO_PAR_FBCTL_OE (0x80) +#define GPIO_PAR_FBCTL_OE_OE (0x80) +#define GPIO_PAR_FBCTL_OE_GPIO (0x00) +#define GPIO_PAR_FBCTL_TA_TA (0x40) +#define GPIO_PAR_FBCTL_TA_GPIO (0x00) +#define GPIO_PAR_FBCTL_RW_RW (0x20) +#define GPIO_PAR_FBCTL_RW_GPIO (0x00) +#define GPIO_PAR_FBCTL_TS_MASK (0xE7) +#define GPIO_PAR_FBCTL_TS_TS (0x18) +#define GPIO_PAR_FBCTL_TS_ALE (0x10) +#define GPIO_PAR_FBCTL_TS_TBST (0x08) +#define GPIO_PAR_FBCTL_TS_GPIO (0x80) + +/* Bit definitions and macros for PAR_DSPI */ +#define GPIO_PAR_DSPI_SCK (0x01) +#define GPIO_PAR_DSPI_SOUT (0x02) +#define GPIO_PAR_DSPI_SIN (0x04) +#define GPIO_PAR_DSPI_PCS0 (0x08) +#define GPIO_PAR_DSPI_PCS1 (0x10) +#define GPIO_PAR_DSPI_PCS2 (0x20) +#define GPIO_PAR_DSPI_PCS5 (0x40) +#define GPIO_PAR_DSPI_PCS5_PCS5 (0x40) +#define GPIO_PAR_DSPI_PCS5_GPIO (0x00) +#define GPIO_PAR_DSPI_PCS2_PCS2 (0x20) +#define GPIO_PAR_DSPI_PCS2_GPIO (0x00) +#define GPIO_PAR_DSPI_PCS1_PCS1 (0x10) +#define GPIO_PAR_DSPI_PCS1_GPIO (0x00) +#define GPIO_PAR_DSPI_PCS0_PCS0 (0x08) +#define GPIO_PAR_DSPI_PCS0_GPIO (0x00) +#define GPIO_PAR_DSPI_SIN_SIN (0x04) +#define GPIO_PAR_DSPI_SIN_GPIO (0x00) +#define GPIO_PAR_DSPI_SOUT_SOUT (0x02) +#define GPIO_PAR_DSPI_SOUT_GPIO (0x00) +#define GPIO_PAR_DSPI_SCK_SCK (0x01) +#define GPIO_PAR_DSPI_SCK_GPIO (0x00) + +/* Bit definitions and macros for PAR_BE */ +#define GPIO_PAR_BE_BS0 (0x01) +#define GPIO_PAR_BE_BS1 (0x04) +#define GPIO_PAR_BE_BS2(x) (((x)&0x03)<<4) +#define GPIO_PAR_BE_BS3(x) (((x)&0x03)<<6) +#define GPIO_PAR_BE_BE3_MASK (0x3F) +#define GPIO_PAR_BE_BE3_BE3 (0xC0) +#define GPIO_PAR_BE_BE3_TSIZ1 (0x80) +#define GPIO_PAR_BE_BE3_GPIO (0x00) +#define GPIO_PAR_BE_BE2_MASK (0xCF) +#define GPIO_PAR_BE_BE2_BE2 (0x30) +#define GPIO_PAR_BE_BE2_TSIZ0 (0x20) +#define GPIO_PAR_BE_BE2_GPIO (0x00) +#define GPIO_PAR_BE_BE1_BE1 (0x04) +#define GPIO_PAR_BE_BE1_GPIO (0x00) +#define GPIO_PAR_BE_BE0_BE0 (0x01) +#define GPIO_PAR_BE_BE0_GPIO (0x00) + +/* Bit definitions and macros for PAR_CS */ +#define GPIO_PAR_CS_CS1 (0x02) +#define GPIO_PAR_CS_CS2 (0x04) +#define GPIO_PAR_CS_CS3 (0x08) +#define GPIO_PAR_CS_CS3_CS3 (0x08) +#define GPIO_PAR_CS_CS3_GPIO (0x00) +#define GPIO_PAR_CS_CS2_CS2 (0x04) +#define GPIO_PAR_CS_CS2_GPIO (0x00) +#define GPIO_PAR_CS_CS1_CS1 (0x02) +#define GPIO_PAR_CS_CS1_GPIO (0x00) + +/* Bit definitions and macros for PAR_TIMER */ +#define GPIO_PAR_TIMER_T0IN(x) (((x)&0x03)) +#define GPIO_PAR_TIMER_T1IN(x) (((x)&0x03)<<2) +#define GPIO_PAR_TIMER_T2IN(x) (((x)&0x03)<<4) +#define GPIO_PAR_TIMER_T3IN(x) (((x)&0x03)<<6) +#define GPIO_PAR_TIMER_T3IN_MASK (0x3F) +#define GPIO_PAR_TIMER_T3IN_T3IN (0xC0) +#define GPIO_PAR_TIMER_T3IN_T3OUT (0x80) +#define GPIO_PAR_TIMER_T3IN_U2RXD (0x40) +#define GPIO_PAR_TIMER_T3IN_GPIO (0x00) +#define GPIO_PAR_TIMER_T2IN_MASK (0xCF) +#define GPIO_PAR_TIMER_T2IN_T2IN (0x30) +#define GPIO_PAR_TIMER_T2IN_T2OUT (0x20) +#define GPIO_PAR_TIMER_T2IN_U2TXD (0x10) +#define GPIO_PAR_TIMER_T2IN_GPIO (0x00) +#define GPIO_PAR_TIMER_T1IN_MASK (0xF3) +#define GPIO_PAR_TIMER_T1IN_T1IN (0x0C) +#define GPIO_PAR_TIMER_T1IN_T1OUT (0x08) +#define GPIO_PAR_TIMER_T1IN_U2CTS (0x04) +#define GPIO_PAR_TIMER_T1IN_GPIO (0x00) +#define GPIO_PAR_TIMER_T0IN_MASK (0xFC) +#define GPIO_PAR_TIMER_T0IN_T0IN (0x03) +#define GPIO_PAR_TIMER_T0IN_T0OUT (0x02) +#define GPIO_PAR_TIMER_T0IN_U2RTS (0x01) +#define GPIO_PAR_TIMER_T0IN_GPIO (0x00) + +/* Bit definitions and macros for PAR_USB */ +#define GPIO_PAR_USB_VBUSOC(x) (((x)&0x03)) +#define GPIO_PAR_USB_VBUSEN(x) (((x)&0x03)<<2) +#define GPIO_PAR_USB_VBUSEN_MASK (0xF3) +#define GPIO_PAR_USB_VBUSEN_VBUSEN (0x0C) +#define GPIO_PAR_USB_VBUSEN_USBPULLUP (0x08) +#define GPIO_PAR_USB_VBUSEN_ULPI_NXT (0x04) +#define GPIO_PAR_USB_VBUSEN_GPIO (0x00) +#define GPIO_PAR_USB_VBUSOC_MASK (0xFC) +#define GPIO_PAR_USB_VBUSOC_VBUSOC (0x03) +#define GPIO_PAR_USB_VBUSOC_ULPI_STP (0x01) +#define GPIO_PAR_USB_VBUSOC_GPIO (0x00) + +/* Bit definitions and macros for PAR_UART */ +#define GPIO_PAR_UART_U0TXD (0x01) +#define GPIO_PAR_UART_U0RXD (0x02) +#define GPIO_PAR_UART_U0RTS (0x04) +#define GPIO_PAR_UART_U0CTS (0x08) +#define GPIO_PAR_UART_U1TXD (0x10) +#define GPIO_PAR_UART_U1RXD (0x20) +#define GPIO_PAR_UART_U1RTS (0x40) +#define GPIO_PAR_UART_U1CTS (0x80) +#define GPIO_PAR_UART_U1CTS_U1CTS (0x80) +#define GPIO_PAR_UART_U1CTS_GPIO (0x00) +#define GPIO_PAR_UART_U1RTS_U1RTS (0x40) +#define GPIO_PAR_UART_U1RTS_GPIO (0x00) +#define GPIO_PAR_UART_U1RXD_U1RXD (0x20) +#define GPIO_PAR_UART_U1RXD_GPIO (0x00) +#define GPIO_PAR_UART_U1TXD_U1TXD (0x10) +#define GPIO_PAR_UART_U1TXD_GPIO (0x00) +#define GPIO_PAR_UART_U0CTS_U0CTS (0x08) +#define GPIO_PAR_UART_U0CTS_GPIO (0x00) +#define GPIO_PAR_UART_U0RTS_U0RTS (0x04) +#define GPIO_PAR_UART_U0RTS_GPIO (0x00) +#define GPIO_PAR_UART_U0RXD_U0RXD (0x02) +#define GPIO_PAR_UART_U0RXD_GPIO (0x00) +#define GPIO_PAR_UART_U0TXD_U0TXD (0x01) +#define GPIO_PAR_UART_U0TXD_GPIO (0x00) + +/* Bit definitions and macros for PAR_FECI2C */ +#define GPIO_PAR_FECI2C_SDA(x) (((x)&0x0003)) +#define GPIO_PAR_FECI2C_SCL(x) (((x)&0x0003)<<2) +#define GPIO_PAR_FECI2C_MDIO0 (0x0010) +#define GPIO_PAR_FECI2C_MDC0 (0x0040) +#define GPIO_PAR_FECI2C_MDIO1(x) (((x)&0x0003)<<8) +#define GPIO_PAR_FECI2C_MDC1(x) (((x)&0x0003)<<10) +#define GPIO_PAR_FECI2C_MDC1_MASK (0xF3FF) +#define GPIO_PAR_FECI2C_MDC1_MDC1 (0x0C00) +#define GPIO_PAR_FECI2C_MDC1_ATA_DIOR (0x0800) +#define GPIO_PAR_FECI2C_MDC1_GPIO (0x0000) +#define GPIO_PAR_FECI2C_MDIO1_MASK (0xFCFF) +#define GPIO_PAR_FECI2C_MDIO1_MDIO1 (0x0300) +#define GPIO_PAR_FECI2C_MDIO1_ATA_DIOW (0x0200) +#define GPIO_PAR_FECI2C_MDIO1_GPIO (0x0000) +#define GPIO_PAR_FECI2C_MDC0_MDC0 (0x0040) +#define GPIO_PAR_FECI2C_MDC0_GPIO (0x0000) +#define GPIO_PAR_FECI2C_MDIO0_MDIO0 (0x0010) +#define GPIO_PAR_FECI2C_MDIO0_GPIO (0x0000) +#define GPIO_PAR_FECI2C_SCL_MASK (0xFFF3) +#define GPIO_PAR_FECI2C_SCL_SCL (0x000C) +#define GPIO_PAR_FECI2C_SCL_U2TXD (0x0004) +#define GPIO_PAR_FECI2C_SCL_GPIO (0x0000) +#define GPIO_PAR_FECI2C_SDA_MASK (0xFFFC) +#define GPIO_PAR_FECI2C_SDA_SDA (0x0003) +#define GPIO_PAR_FECI2C_SDA_U2RXD (0x0001) +#define GPIO_PAR_FECI2C_SDA_GPIO (0x0000) + +/* Bit definitions and macros for PAR_SSI */ +#define GPIO_PAR_SSI_MCLK (0x0001) +#define GPIO_PAR_SSI_STXD(x) (((x)&0x0003)<<2) +#define GPIO_PAR_SSI_SRXD(x) (((x)&0x0003)<<4) +#define GPIO_PAR_SSI_FS(x) (((x)&0x0003)<<6) +#define GPIO_PAR_SSI_BCLK(x) (((x)&0x0003)<<8) +#define GPIO_PAR_SSI_BCLK_MASK (0xFCFF) +#define GPIO_PAR_SSI_BCLK_BCLK (0x0300) +#define GPIO_PAR_SSI_BCLK_U1CTS (0x0200) +#define GPIO_PAR_SSI_BCLK_GPIO (0x0000) +#define GPIO_PAR_SSI_FS_MASK (0xFF3F) +#define GPIO_PAR_SSI_FS_FS (0x00C0) +#define GPIO_PAR_SSI_FS_U1RTS (0x0080) +#define GPIO_PAR_SSI_FS_GPIO (0x0000) +#define GPIO_PAR_SSI_SRXD_MASK (0xFFCF) +#define GPIO_PAR_SSI_SRXD_SRXD (0x0030) +#define GPIO_PAR_SSI_SRXD_U1RXD (0x0020) +#define GPIO_PAR_SSI_SRXD_GPIO (0x0000) +#define GPIO_PAR_SSI_STXD_MASK (0xFFF3) +#define GPIO_PAR_SSI_STXD_STXD (0x000C) +#define GPIO_PAR_SSI_STXD_U1TXD (0x0008) +#define GPIO_PAR_SSI_STXD_GPIO (0x0000) +#define GPIO_PAR_SSI_MCLK_MCLK (0x0001) +#define GPIO_PAR_SSI_MCLK_GPIO (0x0000) + +/* Bit definitions and macros for PAR_ATA */ +#define GPIO_PAR_ATA_IORDY (0x0001) +#define GPIO_PAR_ATA_DMARQ (0x0002) +#define GPIO_PAR_ATA_RESET (0x0004) +#define GPIO_PAR_ATA_DA0 (0x0020) +#define GPIO_PAR_ATA_DA1 (0x0040) +#define GPIO_PAR_ATA_DA2 (0x0080) +#define GPIO_PAR_ATA_CS0 (0x0100) +#define GPIO_PAR_ATA_CS1 (0x0200) +#define GPIO_PAR_ATA_BUFEN (0x0400) +#define GPIO_PAR_ATA_BUFEN_BUFEN (0x0400) +#define GPIO_PAR_ATA_BUFEN_GPIO (0x0000) +#define GPIO_PAR_ATA_CS1_CS1 (0x0200) +#define GPIO_PAR_ATA_CS1_GPIO (0x0000) +#define GPIO_PAR_ATA_CS0_CS0 (0x0100) +#define GPIO_PAR_ATA_CS0_GPIO (0x0000) +#define GPIO_PAR_ATA_DA2_DA2 (0x0080) +#define GPIO_PAR_ATA_DA2_GPIO (0x0000) +#define GPIO_PAR_ATA_DA1_DA1 (0x0040) +#define GPIO_PAR_ATA_DA1_GPIO (0x0000) +#define GPIO_PAR_ATA_DA0_DA0 (0x0020) +#define GPIO_PAR_ATA_DA0_GPIO (0x0000) +#define GPIO_PAR_ATA_RESET_RESET (0x0004) +#define GPIO_PAR_ATA_RESET_GPIO (0x0000) +#define GPIO_PAR_ATA_DMARQ_DMARQ (0x0002) +#define GPIO_PAR_ATA_DMARQ_GPIO (0x0000) +#define GPIO_PAR_ATA_IORDY_IORDY (0x0001) +#define GPIO_PAR_ATA_IORDY_GPIO (0x0000) + +/* Bit definitions and macros for PAR_IRQ */ +#define GPIO_PAR_IRQ_IRQ1 (0x02) +#define GPIO_PAR_IRQ_IRQ4 (0x10) +#define GPIO_PAR_IRQ_IRQ4_IRQ4 (0x10) +#define GPIO_PAR_IRQ_IRQ4_GPIO (0x00) +#define GPIO_PAR_IRQ_IRQ1_IRQ1 (0x02) +#define GPIO_PAR_IRQ_IRQ1_GPIO (0x00) + +/* Bit definitions and macros for PAR_PCI */ +#define GPIO_PAR_PCI_REQ0 (0x0001) +#define GPIO_PAR_PCI_REQ1 (0x0004) +#define GPIO_PAR_PCI_REQ2 (0x0010) +#define GPIO_PAR_PCI_REQ3(x) (((x)&0x0003)<<6) +#define GPIO_PAR_PCI_GNT0 (0x0100) +#define GPIO_PAR_PCI_GNT1 (0x0400) +#define GPIO_PAR_PCI_GNT2 (0x1000) +#define GPIO_PAR_PCI_GNT3(x) (((x)&0x0003)<<14) +#define GPIO_PAR_PCI_GNT3_MASK (0x3FFF) +#define GPIO_PAR_PCI_GNT3_GNT3 (0xC000) +#define GPIO_PAR_PCI_GNT3_ATA_DMACK (0x8000) +#define GPIO_PAR_PCI_GNT3_GPIO (0x0000) +#define GPIO_PAR_PCI_GNT2_GNT2 (0x1000) +#define GPIO_PAR_PCI_GNT2_GPIO (0x0000) +#define GPIO_PAR_PCI_GNT1_GNT1 (0x0400) +#define GPIO_PAR_PCI_GNT1_GPIO (0x0000) +#define GPIO_PAR_PCI_GNT0_GNT0 (0x0100) +#define GPIO_PAR_PCI_GNT0_GPIO (0x0000) +#define GPIO_PAR_PCI_REQ3_MASK (0xFF3F) +#define GPIO_PAR_PCI_REQ3_REQ3 (0x00C0) +#define GPIO_PAR_PCI_REQ3_ATA_INTRQ (0x0080) +#define GPIO_PAR_PCI_REQ3_GPIO (0x0000) +#define GPIO_PAR_PCI_REQ2_REQ2 (0x0010) +#define GPIO_PAR_PCI_REQ2_GPIO (0x0000) +#define GPIO_PAR_PCI_REQ1_REQ1 (0x0040) +#define GPIO_PAR_PCI_REQ1_GPIO (0x0000) +#define GPIO_PAR_PCI_REQ0_REQ0 (0x0001) +#define GPIO_PAR_PCI_REQ0_GPIO (0x0000) + +/* Bit definitions and macros for MSCR_SDRAM */ +#define GPIO_MSCR_SDRAM_SDCTL(x) (((x)&0x03)) +#define GPIO_MSCR_SDRAM_SDCLK(x) (((x)&0x03)<<2) +#define GPIO_MSCR_SDRAM_SDDQS(x) (((x)&0x03)<<4) +#define GPIO_MSCR_SDRAM_SDDATA(x) (((x)&0x03)<<6) +#define GPIO_MSCR_SDRAM_SDDATA_MASK (0x3F) +#define GPIO_MSCR_SDRAM_SDDATA_DDR1 (0xC0) +#define GPIO_MSCR_SDRAM_SDDATA_DDR2 (0x80) +#define GPIO_MSCR_SDRAM_SDDATA_FS_LPDDR (0x40) +#define GPIO_MSCR_SDRAM_SDDATA_HS_LPDDR (0x00) +#define GPIO_MSCR_SDRAM_SDDQS_MASK (0xCF) +#define GPIO_MSCR_SDRAM_SDDQS_DDR1 (0x30) +#define GPIO_MSCR_SDRAM_SDDQS_DDR2 (0x20) +#define GPIO_MSCR_SDRAM_SDDQS_FS_LPDDR (0x10) +#define GPIO_MSCR_SDRAM_SDDQS_HS_LPDDR (0x00) +#define GPIO_MSCR_SDRAM_SDCLK_MASK (0xF3) +#define GPIO_MSCR_SDRAM_SDCLK_DDR1 (0x0C) +#define GPIO_MSCR_SDRAM_SDCLK_DDR2 (0x08) +#define GPIO_MSCR_SDRAM_SDCLK_FS_LPDDR (0x04) +#define GPIO_MSCR_SDRAM_SDCLK_HS_LPDDR (0x00) +#define GPIO_MSCR_SDRAM_SDCTL_MASK (0xFC) +#define GPIO_MSCR_SDRAM_SDCTL_DDR1 (0x03) +#define GPIO_MSCR_SDRAM_SDCTL_DDR2 (0x02) +#define GPIO_MSCR_SDRAM_SDCTL_FS_LPDDR (0x01) +#define GPIO_MSCR_SDRAM_SDCTL_HS_LPDDR (0x00) + +/* Bit definitions and macros for MSCR_PCI */ +#define GPIO_MSCR_PCI_PCI (0x01) +#define GPIO_MSCR_PCI_PCI_HI_66MHZ (0x01) +#define GPIO_MSCR_PCI_PCI_LO_33MHZ (0x00) + +/* Bit definitions and macros for DSCR_I2C */ +#define GPIO_DSCR_I2C_I2C(x) (((x)&0x03)) +#define GPIO_DSCR_I2C_I2C_LOAD_50PF (0x03) +#define GPIO_DSCR_I2C_I2C_LOAD_30PF (0x02) +#define GPIO_DSCR_I2C_I2C_LOAD_20PF (0x01) +#define GPIO_DSCR_I2C_I2C_LOAD_10PF (0x00) + +/* Bit definitions and macros for DSCR_FLEXBUS */ +#define GPIO_DSCR_FLEXBUS_FBADL(x) (((x)&0x03)) +#define GPIO_DSCR_FLEXBUS_FBADH(x) (((x)&0x03)<<2) +#define GPIO_DSCR_FLEXBUS_FBCTL(x) (((x)&0x03)<<4) +#define GPIO_DSCR_FLEXBUS_FBCLK(x) (((x)&0x03)<<6) +#define GPIO_DSCR_FLEXBUS_FBCLK_LOAD_50PF (0xC0) +#define GPIO_DSCR_FLEXBUS_FBCLK_LOAD_30PF (0x80) +#define GPIO_DSCR_FLEXBUS_FBCLK_LOAD_20PF (0x40) +#define GPIO_DSCR_FLEXBUS_FBCLK_LOAD_10PF (0x00) +#define GPIO_DSCR_FLEXBUS_FBCTL_LOAD_50PF (0x30) +#define GPIO_DSCR_FLEXBUS_FBCTL_LOAD_30PF (0x20) +#define GPIO_DSCR_FLEXBUS_FBCTL_LOAD_20PF (0x10) +#define GPIO_DSCR_FLEXBUS_FBCTL_LOAD_10PF (0x00) +#define GPIO_DSCR_FLEXBUS_FBADH_LOAD_50PF (0x0C) +#define GPIO_DSCR_FLEXBUS_FBADH_LOAD_30PF (0x08) +#define GPIO_DSCR_FLEXBUS_FBADH_LOAD_20PF (0x04) +#define GPIO_DSCR_FLEXBUS_FBADH_LOAD_10PF (0x00) +#define GPIO_DSCR_FLEXBUS_FBADL_LOAD_50PF (0x03) +#define GPIO_DSCR_FLEXBUS_FBADL_LOAD_30PF (0x02) +#define GPIO_DSCR_FLEXBUS_FBADL_LOAD_20PF (0x01) +#define GPIO_DSCR_FLEXBUS_FBADL_LOAD_10PF (0x00) + +/* Bit definitions and macros for DSCR_FEC */ +#define GPIO_DSCR_FEC_FEC0(x) (((x)&0x03)) +#define GPIO_DSCR_FEC_FEC1(x) (((x)&0x03)<<2) +#define GPIO_DSCR_FEC_FEC1_LOAD_50PF (0x0C) +#define GPIO_DSCR_FEC_FEC1_LOAD_30PF (0x08) +#define GPIO_DSCR_FEC_FEC1_LOAD_20PF (0x04) +#define GPIO_DSCR_FEC_FEC1_LOAD_10PF (0x00) +#define GPIO_DSCR_FEC_FEC0_LOAD_50PF (0x03) +#define GPIO_DSCR_FEC_FEC0_LOAD_30PF (0x02) +#define GPIO_DSCR_FEC_FEC0_LOAD_20PF (0x01) +#define GPIO_DSCR_FEC_FEC0_LOAD_10PF (0x00) + +/* Bit definitions and macros for DSCR_UART */ +#define GPIO_DSCR_UART_UART0(x) (((x)&0x03)) +#define GPIO_DSCR_UART_UART1(x) (((x)&0x03)<<2) +#define GPIO_DSCR_UART_UART1_LOAD_50PF (0x0C) +#define GPIO_DSCR_UART_UART1_LOAD_30PF (0x08) +#define GPIO_DSCR_UART_UART1_LOAD_20PF (0x04) +#define GPIO_DSCR_UART_UART1_LOAD_10PF (0x00) +#define GPIO_DSCR_UART_UART0_LOAD_50PF (0x03) +#define GPIO_DSCR_UART_UART0_LOAD_30PF (0x02) +#define GPIO_DSCR_UART_UART0_LOAD_20PF (0x01) +#define GPIO_DSCR_UART_UART0_LOAD_10PF (0x00) + +/* Bit definitions and macros for DSCR_DSPI */ +#define GPIO_DSCR_DSPI_DSPI(x) (((x)&0x03)) +#define GPIO_DSCR_DSPI_DSPI_LOAD_50PF (0x03) +#define GPIO_DSCR_DSPI_DSPI_LOAD_30PF (0x02) +#define GPIO_DSCR_DSPI_DSPI_LOAD_20PF (0x01) +#define GPIO_DSCR_DSPI_DSPI_LOAD_10PF (0x00) + +/* Bit definitions and macros for DSCR_TIMER */ +#define GPIO_DSCR_TIMER_TIMER(x) (((x)&0x03)) +#define GPIO_DSCR_TIMER_TIMER_LOAD_50PF (0x03) +#define GPIO_DSCR_TIMER_TIMER_LOAD_30PF (0x02) +#define GPIO_DSCR_TIMER_TIMER_LOAD_20PF (0x01) +#define GPIO_DSCR_TIMER_TIMER_LOAD_10PF (0x00) + +/* Bit definitions and macros for DSCR_SSI */ +#define GPIO_DSCR_SSI_SSI(x) (((x)&0x03)) +#define GPIO_DSCR_SSI_SSI_LOAD_50PF (0x03) +#define GPIO_DSCR_SSI_SSI_LOAD_30PF (0x02) +#define GPIO_DSCR_SSI_SSI_LOAD_20PF (0x01) +#define GPIO_DSCR_SSI_SSI_LOAD_10PF (0x00) + +/* Bit definitions and macros for DSCR_DMA */ +#define GPIO_DSCR_DMA_DMA(x) (((x)&0x03)) +#define GPIO_DSCR_DMA_DMA_LOAD_50PF (0x03) +#define GPIO_DSCR_DMA_DMA_LOAD_30PF (0x02) +#define GPIO_DSCR_DMA_DMA_LOAD_20PF (0x01) +#define GPIO_DSCR_DMA_DMA_LOAD_10PF (0x00) + +/* Bit definitions and macros for DSCR_DEBUG */ +#define GPIO_DSCR_DEBUG_DEBUG(x) (((x)&0x03)) +#define GPIO_DSCR_DEBUG_DEBUG_LOAD_50PF (0x03) +#define GPIO_DSCR_DEBUG_DEBUG_LOAD_30PF (0x02) +#define GPIO_DSCR_DEBUG_DEBUG_LOAD_20PF (0x01) +#define GPIO_DSCR_DEBUG_DEBUG_LOAD_10PF (0x00) + +/* Bit definitions and macros for DSCR_RESET */ +#define GPIO_DSCR_RESET_RESET(x) (((x)&0x03)) +#define GPIO_DSCR_RESET_RESET_LOAD_50PF (0x03) +#define GPIO_DSCR_RESET_RESET_LOAD_30PF (0x02) +#define GPIO_DSCR_RESET_RESET_LOAD_20PF (0x01) +#define GPIO_DSCR_RESET_RESET_LOAD_10PF (0x00) + +/* Bit definitions and macros for DSCR_IRQ */ +#define GPIO_DSCR_IRQ_IRQ(x) (((x)&0x03)) +#define GPIO_DSCR_IRQ_IRQ_LOAD_50PF (0x03) +#define GPIO_DSCR_IRQ_IRQ_LOAD_30PF (0x02) +#define GPIO_DSCR_IRQ_IRQ_LOAD_20PF (0x01) +#define GPIO_DSCR_IRQ_IRQ_LOAD_10PF (0x00) + +/* Bit definitions and macros for DSCR_USB */ +#define GPIO_DSCR_USB_USB(x) (((x)&0x03)) +#define GPIO_DSCR_USB_USB_LOAD_50PF (0x03) +#define GPIO_DSCR_USB_USB_LOAD_30PF (0x02) +#define GPIO_DSCR_USB_USB_LOAD_20PF (0x01) +#define GPIO_DSCR_USB_USB_LOAD_10PF (0x00) + +/* Bit definitions and macros for DSCR_ATA */ +#define GPIO_DSCR_ATA_ATA(x) (((x)&0x03)) +#define GPIO_DSCR_ATA_ATA_LOAD_50PF (0x03) +#define GPIO_DSCR_ATA_ATA_LOAD_30PF (0x02) +#define GPIO_DSCR_ATA_ATA_LOAD_20PF (0x01) +#define GPIO_DSCR_ATA_ATA_LOAD_10PF (0x00) + +/********************************************************************* +* Random Number Generator (RNG) +*********************************************************************/ + +/* Bit definitions and macros for RNGCR */ +#define RNG_RNGCR_GO (0x00000001) +#define RNG_RNGCR_HA (0x00000002) +#define RNG_RNGCR_IM (0x00000004) +#define RNG_RNGCR_CI (0x00000008) + +/* Bit definitions and macros for RNGSR */ +#define RNG_RNGSR_SV (0x00000001) +#define RNG_RNGSR_LRS (0x00000002) +#define RNG_RNGSR_FUF (0x00000004) +#define RNG_RNGSR_EI (0x00000008) +#define RNG_RNGSR_OFL(x) (((x)&0x000000FF)<<8) +#define RNG_RNGSR_OFS(x) (((x)&0x000000FF)<<16) + +/********************************************************************* +* SDRAM Controller (SDRAMC) +*********************************************************************/ + +/* Bit definitions and macros for SDMR */ +#define SDRAMC_SDMR_DDR2_AD(x) (((x)&0x00003FFF)) /* Address for DDR2 */ +#define SDRAMC_SDMR_CMD (0x00010000) /* Command */ +#define SDRAMC_SDMR_AD(x) (((x)&0x00000FFF)<<18) /* Address */ +#define SDRAMC_SDMR_BK(x) (((x)&0x00000003)<<30) /* Bank Address */ +#define SDRAMC_SDMR_BK_LMR (0x00000000) +#define SDRAMC_SDMR_BK_LEMR (0x40000000) + +/* Bit definitions and macros for SDCR */ +#define SDRAMC_SDCR_DPD (0x00000001) /* Deep Power-Down Mode */ +#define SDRAMC_SDCR_IPALL (0x00000002) /* Initiate Precharge All */ +#define SDRAMC_SDCR_IREF (0x00000004) /* Initiate Refresh */ +#define SDRAMC_SDCR_DQS_OE(x) (((x)&0x00000003)<<10) /* DQS Output Enable */ +#define SDRAMC_SDCR_MEM_PS (0x00002000) /* Data Port Size */ +#define SDRAMC_SDCR_REF_CNT(x) (((x)&0x0000003F)<<16) /* Periodic Refresh Counter */ +#define SDRAMC_SDCR_OE_RULE (0x00400000) /* Drive Rule Selection */ +#define SDRAMC_SDCR_ADDR_MUX(x) (((x)&0x00000003)<<24) /* Internal Address Mux Select */ +#define SDRAMC_SDCR_DDR2_MODE (0x08000000) /* DDR2 Mode Select */ +#define SDRAMC_SDCR_REF_EN (0x10000000) /* Refresh Enable */ +#define SDRAMC_SDCR_DDR_MODE (0x20000000) /* DDR Mode Select */ +#define SDRAMC_SDCR_CKE (0x40000000) /* Clock Enable */ +#define SDRAMC_SDCR_MODE_EN (0x80000000) /* SDRAM Mode Register Programming Enable */ +#define SDRAMC_SDCR_DQS_OE_BOTH (0x00000C000) + +/* Bit definitions and macros for SDCFG1 */ +#define SDRAMC_SDCFG1_WT_LAT(x) (((x)&0x00000007)<<4) /* Write Latency */ +#define SDRAMC_SDCFG1_REF2ACT(x) (((x)&0x0000000F)<<8) /* Refresh to active delay */ +#define SDRAMC_SDCFG1_PRE2ACT(x) (((x)&0x00000007)<<12) /* Precharge to active delay */ +#define SDRAMC_SDCFG1_ACT2RW(x) (((x)&0x00000007)<<16) /* Active to read/write delay */ +#define SDRAMC_SDCFG1_RD_LAT(x) (((x)&0x0000000F)<<20) /* Read CAS Latency */ +#define SDRAMC_SDCFG1_SWT2RWP(x) (((x)&0x00000007)<<24) /* Single write to read/write/precharge delay */ +#define SDRAMC_SDCFG1_SRD2RWP(x) (((x)&0x0000000F)<<28) /* Single read to read/write/precharge delay */ + +/* Bit definitions and macros for SDCFG2 */ +#define SDRAMC_SDCFG2_BL(x) (((x)&0x0000000F)<<16) /* Burst Length */ +#define SDRAMC_SDCFG2_BRD2W(x) (((x)&0x0000000F)<<20) /* Burst read to write delay */ +#define SDRAMC_SDCFG2_BWT2RWP(x) (((x)&0x0000000F)<<24) /* Burst write to read/write/precharge delay */ +#define SDRAMC_SDCFG2_BRD2RP(x) (((x)&0x0000000F)<<28) /* Burst read to read/precharge delay */ + +/* Bit definitions and macros for SDCS group */ +#define SDRAMC_SDCS_CSSZ(x) (((x)&0x0000001F)) /* Chip-Select Size */ +#define SDRAMC_SDCS_CSBA(x) (((x)&0x00000FFF)<<20) /* Chip-Select Base Address */ +#define SDRAMC_SDCS_BA(x) ((x)&0xFFF00000) +#define SDRAMC_SDCS_CSSZ_DISABLE (0x00000000) +#define SDRAMC_SDCS_CSSZ_1MBYTE (0x00000013) +#define SDRAMC_SDCS_CSSZ_2MBYTE (0x00000014) +#define SDRAMC_SDCS_CSSZ_4MBYTE (0x00000015) +#define SDRAMC_SDCS_CSSZ_8MBYTE (0x00000016) +#define SDRAMC_SDCS_CSSZ_16MBYTE (0x00000017) +#define SDRAMC_SDCS_CSSZ_32MBYTE (0x00000018) +#define SDRAMC_SDCS_CSSZ_64MBYTE (0x00000019) +#define SDRAMC_SDCS_CSSZ_128MBYTE (0x0000001A) +#define SDRAMC_SDCS_CSSZ_256MBYTE (0x0000001B) +#define SDRAMC_SDCS_CSSZ_512MBYTE (0x0000001C) +#define SDRAMC_SDCS_CSSZ_1GBYTE (0x0000001D) +#define SDRAMC_SDCS_CSSZ_2GBYTE (0x0000001E) +#define SDRAMC_SDCS_CSSZ_4GBYTE (0x0000001F) + +/********************************************************************* +* Synchronous Serial Interface (SSI) +*********************************************************************/ + +/* Bit definitions and macros for CR */ +#define SSI_CR_SSI_EN (0x00000001) +#define SSI_CR_TE (0x00000002) +#define SSI_CR_RE (0x00000004) +#define SSI_CR_NET (0x00000008) +#define SSI_CR_SYN (0x00000010) +#define SSI_CR_I2S(x) (((x)&0x00000003)<<5) +#define SSI_CR_MCE (0x00000080) +#define SSI_CR_TCH (0x00000100) +#define SSI_CR_CIS (0x00000200) +#define SSI_CR_I2S_NORMAL (0x00000000) +#define SSI_CR_I2S_MASTER (0x00000020) +#define SSI_CR_I2S_SLAVE (0x00000040) + +/* Bit definitions and macros for ISR */ +#define SSI_ISR_TFE0 (0x00000001) +#define SSI_ISR_TFE1 (0x00000002) +#define SSI_ISR_RFF0 (0x00000004) +#define SSI_ISR_RFF1 (0x00000008) +#define SSI_ISR_RLS (0x00000010) +#define SSI_ISR_TLS (0x00000020) +#define SSI_ISR_RFS (0x00000040) +#define SSI_ISR_TFS (0x00000080) +#define SSI_ISR_TUE0 (0x00000100) +#define SSI_ISR_TUE1 (0x00000200) +#define SSI_ISR_ROE0 (0x00000400) +#define SSI_ISR_ROE1 (0x00000800) +#define SSI_ISR_TDE0 (0x00001000) +#define SSI_ISR_TDE1 (0x00002000) +#define SSI_ISR_RDR0 (0x00004000) +#define SSI_ISR_RDR1 (0x00008000) +#define SSI_ISR_RXT (0x00010000) +#define SSI_ISR_CMDDU (0x00020000) +#define SSI_ISR_CMDAU (0x00040000) + +/* Bit definitions and macros for IER */ +#define SSI_IER_TFE0 (0x00000001) +#define SSI_IER_TFE1 (0x00000002) +#define SSI_IER_RFF0 (0x00000004) +#define SSI_IER_RFF1 (0x00000008) +#define SSI_IER_RLS (0x00000010) +#define SSI_IER_TLS (0x00000020) +#define SSI_IER_RFS (0x00000040) +#define SSI_IER_TFS (0x00000080) +#define SSI_IER_TUE0 (0x00000100) +#define SSI_IER_TUE1 (0x00000200) +#define SSI_IER_ROE0 (0x00000400) +#define SSI_IER_ROE1 (0x00000800) +#define SSI_IER_TDE0 (0x00001000) +#define SSI_IER_TDE1 (0x00002000) +#define SSI_IER_RDR0 (0x00004000) +#define SSI_IER_RDR1 (0x00008000) +#define SSI_IER_RXT (0x00010000) +#define SSI_IER_CMDU (0x00020000) +#define SSI_IER_CMDAU (0x00040000) +#define SSI_IER_TIE (0x00080000) +#define SSI_IER_TDMAE (0x00100000) +#define SSI_IER_RIE (0x00200000) +#define SSI_IER_RDMAE (0x00400000) + +/* Bit definitions and macros for TCR */ +#define SSI_TCR_TEFS (0x00000001) +#define SSI_TCR_TFSL (0x00000002) +#define SSI_TCR_TFSI (0x00000004) +#define SSI_TCR_TSCKP (0x00000008) +#define SSI_TCR_TSHFD (0x00000010) +#define SSI_TCR_TXDIR (0x00000020) +#define SSI_TCR_TFDIR (0x00000040) +#define SSI_TCR_TFEN0 (0x00000080) +#define SSI_TCR_TFEN1 (0x00000100) +#define SSI_TCR_TXBIT0 (0x00000200) + +/* Bit definitions and macros for RCR */ +#define SSI_RCR_REFS (0x00000001) +#define SSI_RCR_RFSL (0x00000002) +#define SSI_RCR_RFSI (0x00000004) +#define SSI_RCR_RSCKP (0x00000008) +#define SSI_RCR_RSHFD (0x00000010) +#define SSI_RCR_RFEN0 (0x00000080) +#define SSI_RCR_RFEN1 (0x00000100) +#define SSI_RCR_RXBIT0 (0x00000200) +#define SSI_RCR_RXEXT (0x00000400) + +/* Bit definitions and macros for CCR */ +#define SSI_CCR_PM(x) (((x)&0x000000FF)) +#define SSI_CCR_DC(x) (((x)&0x0000001F)<<8) +#define SSI_CCR_WL(x) (((x)&0x0000000F)<<13) +#define SSI_CCR_PSR (0x00020000) +#define SSI_CCR_DIV2 (0x00040000) + +/* Bit definitions and macros for FCSR */ +#define SSI_FCSR_TFWM0(x) (((x)&0x0000000F)) +#define SSI_FCSR_RFWM0(x) (((x)&0x0000000F)<<4) +#define SSI_FCSR_TFCNT0(x) (((x)&0x0000000F)<<8) +#define SSI_FCSR_RFCNT0(x) (((x)&0x0000000F)<<12) +#define SSI_FCSR_TFWM1(x) (((x)&0x0000000F)<<16) +#define SSI_FCSR_RFWM1(x) (((x)&0x0000000F)<<20) +#define SSI_FCSR_TFCNT1(x) (((x)&0x0000000F)<<24) +#define SSI_FCSR_RFCNT1(x) (((x)&0x0000000F)<<28) + +/* Bit definitions and macros for ACR */ +#define SSI_ACR_AC97EN (0x00000001) +#define SSI_ACR_FV (0x00000002) +#define SSI_ACR_TIF (0x00000004) +#define SSI_ACR_RD (0x00000008) +#define SSI_ACR_WR (0x00000010) +#define SSI_ACR_FRDIV(x) (((x)&0x0000003F)<<5) + +/* Bit definitions and macros for ACADD */ +#define SSI_ACADD_SSI_ACADD(x) (((x)&0x0007FFFF)) + +/* Bit definitions and macros for ACDAT */ +#define SSI_ACDAT_SSI_ACDAT(x) (((x)&0x0007FFFF)) + +/* Bit definitions and macros for ATAG */ +#define SSI_ATAG_DDI_ATAG(x) (((x)&0x0000FFFF)) + +/********************************************************************* +* Phase Locked Loop (PLL) +*********************************************************************/ + +/* Bit definitions and macros for PCR */ +#define PLL_PCR_OUTDIV1(x) (((x)&0x0000000F)) /* Output divider for CPU clock frequency */ +#define PLL_PCR_OUTDIV2(x) (((x)&0x0000000F)<<4) /* Output divider for internal bus clock frequency */ +#define PLL_PCR_OUTDIV3(x) (((x)&0x0000000F)<<8) /* Output divider for Flexbus clock frequency */ +#define PLL_PCR_OUTDIV4(x) (((x)&0x0000000F)<<12) /* Output divider for PCI clock frequency */ +#define PLL_PCR_OUTDIV5(x) (((x)&0x0000000F)<<16) /* Output divider for USB clock frequency */ +#define PLL_PCR_PFDR(x) (((x)&0x000000FF)<<24) /* Feedback divider for VCO frequency */ +#define PLL_PCR_PFDR_MASK (0x000F0000) +#define PLL_PCR_OUTDIV5_MASK (0x000F0000) +#define PLL_PCR_OUTDIV4_MASK (0x0000F000) +#define PLL_PCR_OUTDIV3_MASK (0x00000F00) +#define PLL_PCR_OUTDIV2_MASK (0x000000F0) +#define PLL_PCR_OUTDIV1_MASK (0x0000000F) + +/* Bit definitions and macros for PSR */ +#define PLL_PSR_LOCKS (0x00000001) /* PLL lost lock - sticky */ +#define PLL_PSR_LOCK (0x00000002) /* PLL lock status */ +#define PLL_PSR_LOLIRQ (0x00000004) /* PLL loss-of-lock interrupt enable */ +#define PLL_PSR_LOLRE (0x00000008) /* PLL loss-of-lock reset enable */ + +/********************************************************************* +* PCI +*********************************************************************/ + +/* Bit definitions and macros for SCR */ +#define PCI_SCR_PE (0x80000000) /* Parity Error detected */ +#define PCI_SCR_SE (0x40000000) /* System error signalled */ +#define PCI_SCR_MA (0x20000000) /* Master aboart received */ +#define PCI_SCR_TR (0x10000000) /* Target abort received */ +#define PCI_SCR_TS (0x08000000) /* Target abort signalled */ +#define PCI_SCR_DT (0x06000000) /* PCI_DEVSEL timing */ +#define PCI_SCR_DP (0x01000000) /* Master data parity err */ +#define PCI_SCR_FC (0x00800000) /* Fast back-to-back */ +#define PCI_SCR_R (0x00400000) /* Reserved */ +#define PCI_SCR_66M (0x00200000) /* 66Mhz */ +#define PCI_SCR_C (0x00100000) /* Capabilities list */ +#define PCI_SCR_F (0x00000200) /* Fast back-to-back enable */ +#define PCI_SCR_S (0x00000100) /* SERR enable */ +#define PCI_SCR_ST (0x00000080) /* Addr and Data stepping */ +#define PCI_SCR_PER (0x00000040) /* Parity error response */ +#define PCI_SCR_V (0x00000020) /* VGA palette snoop enable */ +#define PCI_SCR_MW (0x00000010) /* Memory write and invalidate enable */ +#define PCI_SCR_SP (0x00000008) /* Special cycle monitor or ignore */ +#define PCI_SCR_B (0x00000004) /* Bus master enable */ +#define PCI_SCR_M (0x00000002) /* Memory access control */ +#define PCI_SCR_IO (0x00000001) /* I/O access control */ + +#define PCI_CR1_BIST(x) ((x & 0xFF) << 24) /* Built in self test */ +#define PCI_CR1_HDR(x) ((x & 0xFF) << 16) /* Header type */ +#define PCI_CR1_LTMR(x) ((x & 0xF8) << 8) /* Latency timer */ +#define PCI_CR1_CLS(x) (x & 0x0F) /* Cache line size */ + +#define PCI_BAR_BAR0(x) (x & 0xFFFC0000) +#define PCI_BAR_BAR1(x) (x & 0xFFF00000) +#define PCI_BAR_BAR2(x) (x & 0xFFC00000) +#define PCI_BAR_BAR3(x) (x & 0xFF000000) +#define PCI_BAR_BAR4(x) (x & 0xF8000000) +#define PCI_BAR_BAR5(x) (x & 0xE0000000) +#define PCI_BAR_PREF (0x00000004) /* Prefetchable access */ +#define PCI_BAR_RANGE (0x00000002) /* Fixed to 00 */ +#define PCI_BAR_IO_M (0x00000001) /* IO / memory space */ + +#define PCI_CR2_MAXLAT(x) ((x & 0xFF) << 24) /* Maximum latency */ +#define PCI_CR2_MINGNT(x) ((x & 0xFF) << 16) /* Minimum grant */ +#define PCI_CR2_INTPIN(x) ((x & 0xFF) << 8) /* Interrupt Pin */ +#define PCI_CR2_INTLIN(x) (x & 0xFF) /* Interrupt Line */ + +#define PCI_GSCR_DRD (0x80000000) /* Delayed read discarded */ +#define PCI_GSCR_PE (0x20000000) /* PCI_PERR detected */ +#define PCI_GSCR_SE (0x10000000) /* SERR detected */ +#define PCI_GSCR_ER (0x08000000) /* Error response detected */ +#define PCI_GSCR_DRDE (0x00008000) /* Delayed read discarded enable */ +#define PCI_GSCR_PEE (0x00002000) /* PERR detected interrupt enable */ +#define PCI_GSCR_SEE (0x00001000) /* SERR detected interrupt enable */ +#define PCI_GSCR_PR (0x00000001) /* PCI reset */ + +#define PCI_TCR1_LD (0x01000000) /* Latency rule disable */ +#define PCI_TCR1_PID (0x00020000) /* Prefetch invalidate and disable */ +#define PCI_TCR1_P (0x00010000) /* Prefetch reads */ +#define PCI_TCR1_WCD (0x00000100) /* Write combine disable */ + +#define PCI_TCR1_B5E (0x00002000) /* */ +#define PCI_TCR1_B4E (0x00001000) /* */ +#define PCI_TCR1_B3E (0x00000800) /* */ +#define PCI_TCR1_B2E (0x00000400) /* */ +#define PCI_TCR1_B1E (0x00000200) /* */ +#define PCI_TCR1_B0E (0x00000100) /* */ +#define PCI_TCR1_CR (0x00000001) /* */ + +#define PCI_TBATR_BAT(x) ((x & 0xFFF) << 20) +#define PCI_TBATR_EN (0x00000001) /* Enable */ + +#define PCI_IWCR_W0C_IO (0x08000000) /* Windows Maps to PCI I/O */ +#define PCI_IWCR_W0C_PRC_RDMUL (0x04000000) /* PCI Memory Read multiple */ +#define PCI_IWCR_W0C_PRC_RDLN (0x02000000) /* PCI Memory Read line */ +#define PCI_IWCR_W0C_PRC_RD (0x00000000) /* PCI Memory Read */ +#define PCI_IWCR_W0C_EN (0x01000000) /* Enable - Register initialize */ +#define PCI_IWCR_W1C_IO (0x00080000) /* Windows Maps to PCI I/O */ +#define PCI_IWCR_W1C_PRC_RDMUL (0x00040000) /* PCI Memory Read multiple */ +#define PCI_IWCR_W1C_PRC_RDLN (0x00020000) /* PCI Memory Read line */ +#define PCI_IWCR_W1C_PRC_RD (0x00000000) /* PCI Memory Read */ +#define PCI_IWCR_W1C_EN (0x00010000) /* Enable - Register initialize */ +#define PCI_IWCR_W2C_IO (0x00000800) /* Windows Maps to PCI I/O */ +#define PCI_IWCR_W2C_PRC_RDMUL (0x00000400) /* PCI Memory Read multiple */ +#define PCI_IWCR_W2C_PRC_RDLN (0x00000200) /* PCI Memory Read line */ +#define PCI_IWCR_W2C_PRC_RD (0x00000000) /* PCI Memory Read */ +#define PCI_IWCR_W2C_EN (0x00000100) /* Enable - Register initialize */ + +#define PCI_ICR_REE (0x04000000) /* Retry error enable */ +#define PCI_ICR_IAE (0x02000000) /* Initiator abort enable */ +#define PCI_ICR_TAE (0x01000000) /* Target abort enable */ + +#define PCI_IDR_DEVID ( + +/********************************************************************/ + +#endif /* __MCF5445X__ */ diff --git a/include/asm-m68k/rtc.h b/include/asm-m68k/rtc.h index f955bc5fe..7651ca932 100644 --- a/include/asm-m68k/rtc.h +++ b/include/asm-m68k/rtc.h @@ -35,9 +35,10 @@ typedef struct rtc_ctrl { u32 cr; /* 0x10 Control Register */ u32 isr; /* 0x14 Interrupt Status Register */ u32 ier; /* 0x18 Interrupt Enable Register */ - u32 stpwach; /* 0x1C Stopwatch Minutes Register */ + u32 stpwatch; /* 0x1C Stopwatch Minutes Register */ u32 days; /* 0x20 Days Counter Register */ u32 alrm_day; /* 0x24 Days Alarm Register */ + void *extended; } rtc_t; /* Bit definitions and macros for HOURMIN */ diff --git a/include/asm-m68k/u-boot.h b/include/asm-m68k/u-boot.h index 70dbda464..93a6959ff 100644 --- a/include/asm-m68k/u-boot.h +++ b/include/asm-m68k/u-boot.h @@ -52,6 +52,14 @@ typedef struct bd_info { unsigned short bi_ethspeed; /* Ethernet speed in Mbps */ unsigned long bi_intfreq; /* Internal Freq, in MHz */ unsigned long bi_busfreq; /* Bus Freq, in MHz */ +#ifdef CONFIG_PCI + unsigned long bi_pcifreq; /* pci Freq in MHz */ +#endif +#ifdef CONFIG_EXTRA_CLOCK + unsigned long bi_inpfreq; /* input Freq in MHz */ + unsigned long bi_vcofreq; /* vco Freq in MHz */ + unsigned long bi_flbfreq; /* Flexbus Freq in MHz */ +#endif unsigned long bi_baudrate; /* Console Baudrate */ #ifdef CONFIG_HAS_ETH1 diff --git a/include/configs/M54455EVB.h b/include/configs/M54455EVB.h new file mode 100644 index 000000000..6f4859c23 --- /dev/null +++ b/include/configs/M54455EVB.h @@ -0,0 +1,391 @@ +/* + * Configuation settings for the Freescale MCF54455 EVB board. + * + * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef _JAMICA54455_H +#define _JAMICA54455_H + +/* + * High Level Configuration Options + * (easy to change) + */ +#define CONFIG_MCF5445x /* define processor family */ +#define CONFIG_M54455 /* define processor type */ +#define CONFIG_M54455EVB /* M54455EVB board */ + +#undef DEBUG + +#define CONFIG_MCFUART +#define CFG_UART_PORT (0) +#define CONFIG_BAUDRATE 115200 +#define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 } + +#undef CONFIG_WATCHDOG + +#define CONFIG_TIMESTAMP /* Print image info with timestamp */ + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + +/* Command line configuration */ +#include + +#define CONFIG_CMD_BOOTD +#define CONFIG_CMD_CACHE +#define CONFIG_CMD_DATE +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_ELF +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT +#define CONFIG_CMD_FLASH +#define CONFIG_CMD_I2C +#define CONFIG_CMD_IDE +#define CONFIG_CMD_JFFS2 +#define CONFIG_CMD_MEMORY +#define CONFIG_CMD_MISC +#define CONFIG_CMD_MII +#define CONFIG_CMD_NET +#define CONFIG_CMD_PCI +#define CONFIG_CMD_PING +#define CONFIG_CMD_REGINFO + +#undef CONFIG_CMD_LOADB +#undef CONFIG_CMD_LOADS + +/* Network configuration */ +#define CONFIG_MCFFEC +#ifdef CONFIG_MCFFEC +# define CONFIG_NET_MULTI 1 +# define CONFIG_MII 1 +# define CONFIG_CF_DOMII +# define CFG_DISCOVER_PHY +# define CFG_RX_ETH_BUFFER 8 +# define CFG_FAULT_ECHO_LINK_DOWN + +# define CFG_FEC0_PINMUX 0 +# define CFG_FEC1_PINMUX 0 +# define CFG_FEC0_MIIBASE CFG_FEC0_IOBASE +# define CFG_FEC1_MIIBASE CFG_FEC0_IOBASE +# define MCFFEC_TOUT_LOOP 50000 +# define CONFIG_HAS_ETH1 + +# define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */ +# define CONFIG_BOOTARGS "root=/dev/mtdblock1 rw rootfstype=jffs2 ip=none mtdparts=physmap-flash.0:5M(kernel)ro,-(jffs2)" +# define CONFIG_ETHADDR 00:e0:0c:bc:e5:60 +# define CONFIG_ETH1ADDR 00:e0:0c:bc:e5:61 +# define CONFIG_ETHPRIME "FEC0" +# define CONFIG_IPADDR 192.162.1.2 +# define CONFIG_NETMASK 255.255.255.0 +# define CONFIG_SERVERIP 192.162.1.1 +# define CONFIG_GATEWAYIP 192.162.1.1 +# define CONFIG_OVERWRITE_ETHADDR_ONCE + +/* If CFG_DISCOVER_PHY is not defined - hardcoded */ +# ifndef CFG_DISCOVER_PHY +# define FECDUPLEX FULL +# define FECSPEED _100BASET +# else +# ifndef CFG_FAULT_ECHO_LINK_DOWN +# define CFG_FAULT_ECHO_LINK_DOWN +# endif +# endif /* CFG_DISCOVER_PHY */ +#endif + +#define CONFIG_HOSTNAME M54455EVB +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "inpclk=" MK_STR(CFG_INPUT_CLKSRC) "\0" \ + "loadaddr=40010000\0" \ + "u-boot=u-boot.bin\0" \ + "load=tftp ${loadaddr) ${u-boot}\0" \ + "upd=run load; run prog\0" \ + "prog=prot off 0 2ffff;" \ + "era 0 2ffff;" \ + "cp.b ${loadaddr} 0 ${filesize};" \ + "save\0" \ + "" + +/* ATA configuration */ +#define CONFIG_ISO_PARTITION +#define CONFIG_DOS_PARTITION +#define CONFIG_IDE_RESET 1 +#define CONFIG_IDE_PREINIT 1 +#define CONFIG_ATAPI +#undef CONFIG_LBA48 + +#define CFG_IDE_MAXBUS 1 +#define CFG_IDE_MAXDEVICE 2 + +#define CFG_ATA_BASE_ADDR 0x90000000 +#define CFG_ATA_IDE0_OFFSET 0 + +#define CFG_ATA_DATA_OFFSET 0xA0 /* Offset for data I/O */ +#define CFG_ATA_REG_OFFSET 0xA0 /* Offset for normal register accesses */ +#define CFG_ATA_ALT_OFFSET 0xC0 /* Offset for alternate registers */ +#define CFG_ATA_STRIDE 4 /* Interval between registers */ +#define _IO_BASE 0 + +/* Realtime clock */ +#define CONFIG_MCFRTC +#undef RTC_DEBUG +#define CFG_RTC_OSCILLATOR (32 * CFG_HZ) + +/* Timer */ +#define CONFIG_MCFTMR +#undef CONFIG_MCFPIT + +/* I2c */ +#define CONFIG_FSL_I2C +#define CONFIG_HARD_I2C /* I2C with hardware support */ +#undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CFG_I2C_SPEED 80000 /* I2C speed and slave address */ +#define CFG_I2C_SLAVE 0x7F +#define CFG_I2C_OFFSET 0x58000 +#define CFG_IMMR CFG_MBAR + +/* PCI */ +#define CONFIG_PCI 1 + +#define CFG_PCI_MEM_BUS 0xA0000000 +#define CFG_PCI_MEM_PHYS CFG_PCI_MEM_BUS +#define CFG_PCI_MEM_SIZE 0x10000000 + +#define CFG_PCI_IO_BUS 0xB1000000 +#define CFG_PCI_IO_PHYS CFG_PCI_IO_BUS +#define CFG_PCI_IO_SIZE 0x01000000 + +#define CFG_PCI_CFG_BUS 0xB0000000 +#define CFG_PCI_CFG_PHYS CFG_PCI_CFG_BUS +#define CFG_PCI_CFG_SIZE 0x01000000 + +/* FPGA - Spartan 2 */ +/* experiment +#define CONFIG_FPGA CFG_SPARTAN3 +#define CONFIG_FPGA_COUNT 1 +#define CFG_FPGA_PROG_FEEDBACK +#define CFG_FPGA_CHECK_CTRLC +*/ + +/* Input, PCI, Flexbus, and VCO */ +#define CONFIG_EXTRA_CLOCK + +#define CONFIG_PRAM 512 /* 512 KB */ + +#define CFG_PROMPT "-> " +#define CFG_LONGHELP /* undef to save memory */ + +#if defined(CONFIG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_LOAD_ADDR (CFG_SDRAM_BASE + 0x10000) + +#define CFG_HZ 1000 + +#define CFG_MBAR 0xFC000000 + +/* + * Low Level Configuration Settings + * (address mappings, register initial values, etc.) + * You should know what you are doing if you make changes here. + */ + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area (in DPRAM) + */ +#define CFG_INIT_RAM_ADDR 0x80000000 +#define CFG_INIT_RAM_END 0x8000 /* End of used area in internal SRAM */ +#define CFG_INIT_RAM_CTRL 0x221 +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET ((CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) - 16) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + */ +#define CFG_SDRAM_BASE 0x40000000 +#define CFG_SDRAM_BASE1 0x48000000 +#define CFG_SDRAM_SIZE 256 /* SDRAM size in MB */ +#define CFG_SDRAM_CFG1 0x65311610 +#define CFG_SDRAM_CFG2 0x59670000 +#define CFG_SDRAM_CTRL 0xEA0B2000 +#define CFG_SDRAM_EMOD 0x40010000 +#define CFG_SDRAM_MODE 0x00010033 + +#define CFG_MEMTEST_START CFG_SDRAM_BASE + 0x400 +#define CFG_MEMTEST_END ((CFG_SDRAM_SIZE - 3) << 20) + +#define CFG_MONITOR_BASE (CFG_FLASH_BASE + 0x400) +#define CFG_BOOTPARAMS_LEN 64*1024 +#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ +#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization ?? + */ +/* Initial Memory map for Linux */ +#define CFG_BOOTMAPSZ (CFG_SDRAM_BASE + (CFG_SDRAM_SIZE << 20)) + +/* Configuration for environment + * Environment is embedded in u-boot in the second sector of the flash + */ +#define CFG_ENV_OFFSET 0x4000 +#define CFG_ENV_SECT_SIZE 0x2000 +#define CFG_ENV_IS_IN_FLASH 1 +#define CONFIG_ENV_OVERWRITE 1 +#undef CFG_ENV_IS_EMBEDDED + +/*----------------------------------------------------------------------- + * FLASH organization + */ +#ifdef CFG_ATMEL_BOOT +# define CFG_FLASH_BASE 0 +# define CFG_FLASH0_BASE CFG_CS0_BASE +# define CFG_FLASH1_BASE CFG_CS1_BASE +#else +# define CFG_FLASH_BASE CFG_FLASH0_BASE +# define CFG_FLASH0_BASE CFG_CS1_BASE +# define CFG_FLASH1_BASE CFG_CS0_BASE +#endif + +/* M54455EVB has one non CFI flash, defined CFG_FLASH_CFI will cause the system +/* M54455EVB has one non CFI flash, defined CFG_FLASH_CFI will cause the system + keep reset. */ +#undef CFG_FLASH_CFI +#ifdef CFG_FLASH_CFI + +# define CFG_FLASH_CFI_DRIVER 1 +# define CFG_FLASH_SIZE 0x1000000 /* Max size that the board might have */ +# define CFG_FLASH_CFI_WIDTH FLASH_CFI_8BIT +# define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ +# define CFG_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ +# define CFG_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ +# define CFG_FLASH_CHECKSUM +# define CFG_FLASH_BANKS_LIST { CFG_CS0_BASE, CFG_CS1_BASE } + +#else + +# define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ + +# define CFG_ATMEL_REGION 4 +# define CFG_ATMEL_TOTALSECT 11 +# define CFG_ATMEL_SECT {1, 2, 1, 7} +# define CFG_ATMEL_SECTSZ {0x4000, 0x2000, 0x8000, 0x10000} +# define CFG_INTEL_SECT 137 + +/* max number of sectors on one chip */ +# define CFG_MAX_FLASH_SECT (CFG_ATMEL_TOTALSECT + CFG_INTEL_SECT) +# define CFG_FLASH_ERASE_TOUT 2000 /* Atmel needs longer timeout */ +# define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ +# define CFG_FLASH_LOCK_TOUT 5 /* Timeout for Flash Set Lock Bit (in ms) */ +# define CFG_FLASH_UNLOCK_TOUT 100 /* Timeout for Flash Clear Lock Bits (in ms) */ +# define CFG_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ +# define CFG_FLASH_CHECKSUM + +#endif + +/* + * This is setting for JFFS2 support in u-boot. + * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support. + */ +#ifdef CFG_ATMEL_BOOT +# define CONFIG_JFFS2_DEV "nor0" +# define CONFIG_JFFS2_PART_SIZE 0x01000000 +# define CONFIG_JFFS2_PART_OFFSET CFG_FLASH1_BASE +#else +# define CONFIG_JFFS2_DEV "nor0" +# define CONFIG_JFFS2_PART_SIZE (0x01000000 - 0x500000) +# define CONFIG_JFFS2_PART_OFFSET (CFG_FLASH0_BASE + 0x500000) +#endif + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_CACHELINE_SIZE 16 + +/*----------------------------------------------------------------------- + * Memory bank definitions + */ +/* + * CS0 - NOR Flash 1, 2, 4, or 8MB + * CS1 - CompactFlash and registers + * CS2 - CPLD + * CS3 - FPGA + * CS4 - Available + * CS5 - Available + */ + +#ifdef CFG_ATMEL_BOOT + /* Atmel Flash */ +#define CFG_CS0_BASE 0 +#define CFG_CS0_MASK 0x00070001 +#define CFG_CS0_CTRL 0x00001140 +/* Intel Flash */ +#define CFG_CS1_BASE 0x04000000 +#define CFG_CS1_MASK 0x01FF0001 +#define CFG_CS1_CTRL 0x003F3D60 + +#define CFG_ATMEL_BASE CFG_CS0_BASE +#else +/* Intel Flash */ +#define CFG_CS0_BASE 0 +#define CFG_CS0_MASK 0x01FF0001 +#define CFG_CS0_CTRL 0x003F3D60 + /* Atmel Flash */ +#define CFG_CS1_BASE 0x04000000 +#define CFG_CS1_MASK 0x00070001 +#define CFG_CS1_CTRL 0x00001140 + +#define CFG_ATMEL_BASE CFG_CS1_BASE +#endif + +/* CPLD */ +#define CFG_CS2_BASE 0x08000000 +#define CFG_CS2_MASK 0x00070001 +#define CFG_CS2_CTRL 0x003f1140 + +/* FPGA */ +#define CFG_CS3_BASE 0x09000000 +#define CFG_CS3_MASK 0x00070001 +#define CFG_CS3_CTRL 0x00000020 + +#endif /* _JAMICA54455_H */ diff --git a/lib_m68k/board.c b/lib_m68k/board.c index 778ec788a..43f97c404 100644 --- a/lib_m68k/board.c +++ b/lib_m68k/board.c @@ -30,9 +30,7 @@ #include #include -#ifdef CONFIG_M5272 -#include -#endif +#include #if defined(CONFIG_CMD_IDE) #include @@ -139,19 +137,19 @@ void *sbrk (ptrdiff_t increment) char *strmhz(char *buf, long hz) { - long l, n; - long m; + long l, n; + long m; - n = hz / 1000000L; + n = hz / 1000000L; - l = sprintf (buf, "%ld", n); + l = sprintf (buf, "%ld", n); - m = (hz % 1000000L) / 1000L; + m = (hz % 1000000L) / 1000L; - if (m != 0) - sprintf (buf+l, ".%03ld", m); + if (m != 0) + sprintf (buf+l, ".%03ld", m); - return (buf); + return (buf); } /* @@ -169,7 +167,7 @@ char *strmhz(char *buf, long hz) typedef int (init_fnc_t) (void); /************************************************************************ - * Init Utilities * + * Init Utilities ************************************************************************ * Some of this code should be moved into the core functions, * but let's get it working (again) first... @@ -383,6 +381,14 @@ board_init_f (ulong bootflag) WATCHDOG_RESET (); bd->bi_intfreq = gd->cpu_clk; /* Internal Freq, in Hz */ bd->bi_busfreq = gd->bus_clk; /* Bus Freq, in Hz */ +#ifdef CONFIG_PCI + bd->bi_pcifreq = gd->pci_clk; /* PCI Freq in Hz */ +#endif +#ifdef CONFIG_EXTRA_CLOCK + bd->bi_inpfreq = gd->inp_clk; /* input Freq in Hz */ + bd->bi_vcofreq = gd->vco_clk; /* vco Freq in Hz */ + bd->bi_flbfreq = gd->flb_clk; /* flexbus Freq in Hz */ +#endif bd->bi_baudrate = gd->baudrate; /* Console Baudrate */ #ifdef CFG_EXTBDINFO diff --git a/lib_m68k/interrupts.c b/lib_m68k/interrupts.c old mode 100755 new mode 100644 diff --git a/lib_m68k/m68k_linux.c b/lib_m68k/m68k_linux.c index 6c194f80a..fde1744e4 100644 --- a/lib_m68k/m68k_linux.c +++ b/lib_m68k/m68k_linux.c @@ -25,6 +25,8 @@ #include #include #include +#include +#include #include DECLARE_GLOBAL_DATA_PTR; @@ -34,103 +36,189 @@ DECLARE_GLOBAL_DATA_PTR; #define LINUX_MAX_ENVS 256 #define LINUX_MAX_ARGS 256 -extern image_header_t header; /* from cmd_bootm.c */ +#ifdef CONFIG_SHOW_BOOT_PROGRESS +# include +# define SHOW_BOOT_PROGRESS(arg) show_boot_progress(arg) +#else +# define SHOW_BOOT_PROGRESS(arg) +#endif -extern int do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]); +extern image_header_t header; -static int linux_argc; -static char **linux_argv; - -static char **linux_env; -static char *linux_env_p; -static int linux_env_idx; - -static void linux_params_init (ulong start, char *commandline); -static void linux_env_set (char *env_name, char *env_val); - -void do_bootm_linux (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[], - ulong addr, ulong * len_ptr, int verify) +void do_bootm_linux(cmd_tbl_t * cmdtp, int flag, + int argc, char *argv[], + ulong addr, ulong * len_ptr, int verify) { - ulong len = 0, checksum; + ulong sp; + ulong len, checksum; ulong initrd_start, initrd_end; + ulong cmd_start, cmd_end; + ulong initrd_high; ulong data; - void (*theKernel) (int, char **, char **, int *); + int initrd_copy_to_ram = 1; + char *cmdline; + char *s; + bd_t *kbd; + void (*kernel) (bd_t *, ulong, ulong, ulong, ulong); image_header_t *hdr = &header; - char *commandline = getenv ("bootargs"); - char env_buf[12]; - theKernel = - (void (*)(int, char **, char **, int *)) ntohl (hdr->ih_ep); + if ((s = getenv("initrd_high")) != NULL) { + /* a value of "no" or a similar string will act like 0, + * turning the "load high" feature off. This is intentional. + */ + initrd_high = simple_strtoul(s, NULL, 16); + if (initrd_high == ~0) + initrd_copy_to_ram = 0; + } else { /* not set, no restrictions to load high */ + initrd_high = ~0; + } + +#ifdef CONFIG_LOGBUFFER + kbd = gd->bd; + /* Prevent initrd from overwriting logbuffer */ + if (initrd_high < (kbd->bi_memsize - LOGBUFF_LEN - LOGBUFF_OVERHEAD)) + initrd_high = kbd->bi_memsize - LOGBUFF_LEN - LOGBUFF_OVERHEAD; + debug("## Logbuffer at 0x%08lX ", kbd->bi_memsize - LOGBUFF_LEN); +#endif + + /* + * Booting a (Linux) kernel image + * + * Allocate space for command line and board info - the + * address should be as high as possible within the reach of + * the kernel (see CFG_BOOTMAPSZ settings), but in unused + * memory, which means far enough below the current stack + * pointer. + */ + asm("movel %%a7, %%d0\n" + "movel %%d0, %0\n": "=d"(sp): :"%d0"); + debug("## Current stack ends at 0x%08lX ", sp); + + sp -= 2048; /* just to be sure */ + if (sp > CFG_BOOTMAPSZ) + sp = CFG_BOOTMAPSZ; + sp &= ~0xF; + + debug("=> set upper limit to 0x%08lX\n", sp); + + cmdline = (char *)((sp - CFG_BARGSIZE) & ~0xF); + kbd = (bd_t *) (((ulong) cmdline - sizeof(bd_t)) & ~0xF); + + if ((s = getenv("bootargs")) == NULL) + s = ""; + + strcpy(cmdline, s); + + cmd_start = (ulong) & cmdline[0]; + cmd_end = cmd_start + strlen(cmdline); + + *kbd = *(gd->bd); + +#ifdef DEBUG + printf("## cmdline at 0x%08lX ... 0x%08lX\n", cmd_start, cmd_end); + + do_bdinfo(NULL, 0, 0, NULL); +#endif + + if ((s = getenv("clocks_in_mhz")) != NULL) { + /* convert all clock information to MHz */ + kbd->bi_intfreq /= 1000000L; + kbd->bi_busfreq /= 1000000L; + } + + kernel = + (void (*)(bd_t *, ulong, ulong, ulong, ulong))ntohl(hdr->ih_ep); /* * Check if there is an initrd image */ + if (argc >= 3) { - show_boot_progress (9); + debug("Not skipping initrd\n"); + SHOW_BOOT_PROGRESS(9); - addr = simple_strtoul (argv[2], NULL, 16); + addr = simple_strtoul(argv[2], NULL, 16); - printf ("## Loading Ramdisk Image at %08lx ...\n", addr); + printf("## Loading RAMDisk Image at %08lx ...\n", addr); /* Copy header so we can blank CRC field for re-calculation */ - memcpy (&header, (char *) addr, sizeof (image_header_t)); + memmove(&header, (char *)addr, sizeof(image_header_t)); - if (ntohl (hdr->ih_magic) != IH_MAGIC) { - printf ("Bad Magic Number\n"); - show_boot_progress (-10); - do_reset (cmdtp, flag, argc, argv); + if (ntohl(hdr->ih_magic) != IH_MAGIC) { + puts("Bad Magic Number\n"); + SHOW_BOOT_PROGRESS(-10); + do_reset(cmdtp, flag, argc, argv); } data = (ulong) & header; - len = sizeof (image_header_t); + len = sizeof(image_header_t); - checksum = ntohl (hdr->ih_hcrc); + checksum = ntohl(hdr->ih_hcrc); hdr->ih_hcrc = 0; - if (crc32 (0, (char *) data, len) != checksum) { - printf ("Bad Header Checksum\n"); - show_boot_progress (-11); - do_reset (cmdtp, flag, argc, argv); + if (crc32(0, (uchar *) data, len) != checksum) { + puts("Bad Header Checksum\n"); + SHOW_BOOT_PROGRESS(-11); + do_reset(cmdtp, flag, argc, argv); } - show_boot_progress (10); + SHOW_BOOT_PROGRESS(10); - print_image_hdr (hdr); + print_image_hdr(hdr); - data = addr + sizeof (image_header_t); - len = ntohl (hdr->ih_size); + data = addr + sizeof(image_header_t); + len = ntohl(hdr->ih_size); if (verify) { ulong csum = 0; +#if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG) + ulong cdata = data, edata = cdata + len; +#endif /* CONFIG_HW_WATCHDOG || CONFIG_WATCHDOG */ - printf (" Verifying Checksum ... "); - csum = crc32 (0, (char *) data, len); - if (csum != ntohl (hdr->ih_dcrc)) { - printf ("Bad Data CRC\n"); - show_boot_progress (-12); - do_reset (cmdtp, flag, argc, argv); + puts(" Verifying Checksum ... "); + +#if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG) + + while (cdata < edata) { + ulong chunk = edata - cdata; + + if (chunk > CHUNKSZ) + chunk = CHUNKSZ; + csum = crc32(csum, (uchar *) cdata, chunk); + cdata += chunk; + + WATCHDOG_RESET(); } - printf ("OK\n"); +#else /* !(CONFIG_HW_WATCHDOG || CONFIG_WATCHDOG) */ + csum = crc32(0, (uchar *) data, len); +#endif /* CONFIG_HW_WATCHDOG || CONFIG_WATCHDOG */ + + if (csum != ntohl(hdr->ih_dcrc)) { + puts("Bad Data CRC\n"); + SHOW_BOOT_PROGRESS(-12); + do_reset(cmdtp, flag, argc, argv); + } + puts("OK\n"); } - show_boot_progress (11); + SHOW_BOOT_PROGRESS(11); if ((hdr->ih_os != IH_OS_LINUX) || (hdr->ih_arch != IH_CPU_M68K) || (hdr->ih_type != IH_TYPE_RAMDISK)) { - printf ("No Linux M68K Ramdisk Image\n"); - show_boot_progress (-13); - do_reset (cmdtp, flag, argc, argv); + puts("No Linux ColdFire Ramdisk Image\n"); + SHOW_BOOT_PROGRESS(-13); + do_reset(cmdtp, flag, argc, argv); } /* * Now check if we have a multifile image */ } else if ((hdr->ih_type == IH_TYPE_MULTI) && (len_ptr[1])) { - ulong tail = ntohl (len_ptr[0]) % 4; + u_long tail = ntohl(len_ptr[0]) % 4; int i; - show_boot_progress (13); + SHOW_BOOT_PROGRESS(13); /* skip kernel length and terminator */ data = (ulong) (&len_ptr[2]); @@ -138,130 +226,110 @@ void do_bootm_linux (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[], for (i = 1; len_ptr[i]; ++i) data += 4; /* add kernel length, and align */ - data += ntohl (len_ptr[0]); + data += ntohl(len_ptr[0]); if (tail) { data += 4 - tail; } - len = ntohl (len_ptr[1]); + len = ntohl(len_ptr[1]); } else { /* * no initrd image */ - show_boot_progress (14); + SHOW_BOOT_PROGRESS(14); - data = 0; + len = data = 0; } -#ifdef DEBUG if (!data) { - printf ("No initrd\n"); + debug("No initrd\n"); } -#endif if (data) { - initrd_start = data; - initrd_end = initrd_start + len; + if (!initrd_copy_to_ram) { /* zero-copy ramdisk support */ + initrd_start = data; + initrd_end = initrd_start + len; + } else { + initrd_start = (ulong) kbd - len; + initrd_start &= ~(4096 - 1); /* align on page */ + + if (initrd_high) { + ulong nsp; + + /* + * the inital ramdisk does not need to be within + * CFG_BOOTMAPSZ as it is not accessed until after + * the mm system is initialised. + * + * do the stack bottom calculation again and see if + * the initrd will fit just below the monitor stack + * bottom without overwriting the area allocated + * above for command line args and board info. + */ + asm("movel %%a7, %%d0\n" + "movel %%d0, %0\n": "=d"(nsp): :"%d0"); + nsp -= 2048; /* just to be sure */ + nsp &= ~0xF; + + if (nsp > initrd_high) /* limit as specified */ + nsp = initrd_high; + + nsp -= len; + nsp &= ~(4096 - 1); /* align on page */ + + if (nsp >= sp) + initrd_start = nsp; + } + + SHOW_BOOT_PROGRESS(12); + + debug + ("## initrd at 0x%08lX ... 0x%08lX (len=%ld=0x%lX)\n", + data, data + len - 1, len, len); + + initrd_end = initrd_start + len; + printf(" Loading Ramdisk to %08lx, end %08lx ... ", + initrd_start, initrd_end); +#if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG) + { + size_t l = len; + void *to = (void *)initrd_start; + void *from = (void *)data; + + while (l > 0) { + size_t tail = + (l > CHUNKSZ) ? CHUNKSZ : l; + WATCHDOG_RESET(); + memmove(to, from, tail); + to += tail; + from += tail; + l -= tail; + } + } +#else /* !(CONFIG_HW_WATCHDOG || CONFIG_WATCHDOG) */ + memmove((void *)initrd_start, (void *)data, len); +#endif /* CONFIG_HW_WATCHDOG || CONFIG_WATCHDOG */ + puts("OK\n"); + } } else { initrd_start = 0; initrd_end = 0; } - show_boot_progress (15); + debug("## Transferring control to Linux (at address %08lx) ...\n", + (ulong) kernel); -#ifdef DEBUG - printf ("## Transferring control to Linux (at address %08lx) ...\n", - (ulong) theKernel); -#endif + SHOW_BOOT_PROGRESS(15); - linux_params_init (PHYSADDR (gd->bd->bi_boot_params), commandline); - - sprintf (env_buf, "%lu", gd->ram_size >> 20); - linux_env_set ("memsize", env_buf); - - sprintf (env_buf, "0x%08X", (uint) PHYSADDR (initrd_start)); - linux_env_set ("initrd_start", env_buf); - - sprintf (env_buf, "0x%X", (uint) (initrd_end - initrd_start)); - linux_env_set ("initrd_size", env_buf); - - sprintf (env_buf, "0x%08X", (uint) (gd->bd->bi_flashstart)); - linux_env_set ("flash_start", env_buf); - - sprintf (env_buf, "0x%X", (uint) (gd->bd->bi_flashsize)); - linux_env_set ("flash_size", env_buf); - - /* we assume that the kernel is in place */ - printf ("\nStarting kernel ...\n\n"); - - theKernel (linux_argc, linux_argv, linux_env, 0); -} - -static void linux_params_init (ulong start, char *line) -{ - char *next, *quote, *argp; - - linux_argc = 1; - linux_argv = (char **) start; - linux_argv[0] = 0; - argp = (char *) (linux_argv + LINUX_MAX_ARGS); - - next = line; - - while (line && *line && linux_argc < LINUX_MAX_ARGS) { - quote = strchr (line, '"'); - next = strchr (line, ' '); - - while (next != NULL && quote != NULL && quote < next) { - /* we found a left quote before the next blank - * now we have to find the matching right quote - */ - next = strchr (quote + 1, '"'); - if (next != NULL) { - quote = strchr (next + 1, '"'); - next = strchr (next + 1, ' '); - } - } - - if (next == NULL) { - next = line + strlen (line); - } - - linux_argv[linux_argc] = argp; - memcpy (argp, line, next - line); - argp[next - line] = 0; - - argp += next - line + 1; - linux_argc++; - - if (*next) - next++; - - line = next; - } - - linux_env = (char **) (((ulong) argp + 15) & ~15); - linux_env[0] = 0; - linux_env_p = (char *) (linux_env + LINUX_MAX_ENVS); - linux_env_idx = 0; -} - -static void linux_env_set (char *env_name, char *env_val) -{ - if (linux_env_idx < LINUX_MAX_ENVS - 1) { - linux_env[linux_env_idx] = linux_env_p; - - strcpy (linux_env_p, env_name); - linux_env_p += strlen (env_name); - - strcpy (linux_env_p, "="); - linux_env_p += 1; - - strcpy (linux_env_p, env_val); - linux_env_p += strlen (env_val); - - linux_env_p++; - linux_env[++linux_env_idx] = 0; - } + /* + * Linux Kernel Parameters (passing board info data): + * r3: ptr to board info data + * r4: initrd_start or 0 if no initrd + * r5: initrd_end - unused if r4 is 0 + * r6: Start of command line string + * r7: End of command line string + */ + (*kernel) (kbd, initrd_start, initrd_end, cmd_start, cmd_end); + /* does not return */ } From 14778585d1389d86d5846efec29e5fce892680ce Mon Sep 17 00:00:00 2001 From: Tony Li Date: Fri, 17 Aug 2007 10:35:59 +0800 Subject: [PATCH 167/259] mpc83xx: Split PIB init code from pci.c and add Qoc3 ATM card support The patch split the PIB init code from pci.c to a single file board/freescale/common/pq-mds-pib.c And add Qoc3 ATM card support for MPC8360EMDS and MPC832XEMDS board. Signed-off-by Tony Li --- board/freescale/common/pq-mds-pib.c | 101 ++++++++++++++++++++++++++++ board/freescale/common/pq-mds-pib.h | 9 +++ board/mpc832xemds/Makefile | 2 +- board/mpc832xemds/mpc832xemds.c | 11 +++ board/mpc832xemds/pci.c | 40 ----------- board/mpc8360emds/Makefile | 2 +- board/mpc8360emds/mpc8360emds.c | 11 +++ board/mpc8360emds/pci.c | 40 ----------- include/configs/MPC832XEMDS.h | 3 + include/configs/MPC8360EMDS.h | 7 +- 10 files changed, 142 insertions(+), 84 deletions(-) create mode 100644 board/freescale/common/pq-mds-pib.c create mode 100644 board/freescale/common/pq-mds-pib.h diff --git a/board/freescale/common/pq-mds-pib.c b/board/freescale/common/pq-mds-pib.c new file mode 100644 index 000000000..9799117a9 --- /dev/null +++ b/board/freescale/common/pq-mds-pib.c @@ -0,0 +1,101 @@ +/* + * Copyright (C) 2007 Freescale Semiconductor, Inc. + * + * Tony Li + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation; + */ + +#include +#include +#include + +#include "pq-mds-pib.h" + +int pib_init(void) +{ + u8 val8; + u8 orig_i2c_bus; + + /* Switch temporarily to I2C bus #2 */ + orig_i2c_bus = i2c_get_bus_num(); + i2c_set_bus_num(1); +#if defined(CONFIG_PCI) && !defined(CONFIG_PCISLAVE) + /* Assign PIB PMC slot to desired PCI bus */ + val8 = 0; + i2c_write(0x23, 0x6, 1, &val8, 1); + i2c_write(0x23, 0x7, 1, &val8, 1); + val8 = 0xff; + i2c_write(0x23, 0x2, 1, &val8, 1); + i2c_write(0x23, 0x3, 1, &val8, 1); + + val8 = 0; + i2c_write(0x26, 0x6, 1, &val8, 1); + val8 = 0x34; + i2c_write(0x26, 0x7, 1, &val8, 1); +#if defined(CONFIG_MPC832XEMDS) + val8 = 0xf9; /* PMC2, PMC3 slot to PCI bus */ +#else + val8 = 0xf3; /* PMC1, PMC2, PMC3 slot to PCI bus */ +#endif + i2c_write(0x26, 0x2, 1, &val8, 1); + val8 = 0xff; + i2c_write(0x26, 0x3, 1, &val8, 1); + + val8 = 0; + i2c_write(0x27, 0x6, 1, &val8, 1); + i2c_write(0x27, 0x7, 1, &val8, 1); + val8 = 0xff; + i2c_write(0x27, 0x2, 1, &val8, 1); + val8 = 0xef; + i2c_write(0x27, 0x3, 1, &val8, 1); + + eieio(); + +#if defined(CONFIG_MPC832XEMDS) + printf("PCI 32bit bus on PMC2 &PMC3\n"); +#else + printf("PCI 32bit bus on PMC1 & PMC2 &PMC3\n"); +#endif +#endif + +#if defined(CONFIG_PQ_MDS_PIB_ATM) +#if defined(CONFIG_MPC8360EMDS) + val8 = 0; + i2c_write(0x20, 0x6, 1, &val8, 1); + i2c_write(0x20, 0x7, 1, &val8, 1); + + val8 = 0xdf; + i2c_write(0x20, 0x2, 1, &val8, 1); + val8 = 0xf7; + i2c_write(0x20, 0x3, 1, &val8, 1); + + eieio(); + + printf("QOC3 ATM card on PMC0\n"); +#elif defined(CONFIG_MPC832XEMDS) + val = 0; + i2c_write(0x26, 0x7, 1, &val, 1); + val = 0xf7; + i2c_write(0x26, 0x3, 1, &val, 1); + + val = 0; + i2c_write(0x21, 0x6, 1, &val, 1); + i2c_write(0x21, 0x7, 1, &val, 1); + + val = 0xdf; + i2c_write(0x21, 0x2, 1, &val, 1); + val = 0xef; + i2c_write(0x21, 0x3, 1, &val, 1); + + eieio(); + + printf("QOC3 ATM card on PMC1\n"); +#endif +#endif + /* Reset to original I2C bus */ + i2c_set_bus_num(orig_i2c_bus); + return 0; +} diff --git a/board/freescale/common/pq-mds-pib.h b/board/freescale/common/pq-mds-pib.h new file mode 100644 index 000000000..67066fd11 --- /dev/null +++ b/board/freescale/common/pq-mds-pib.h @@ -0,0 +1,9 @@ +/* + * Copyright (C) 2007 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation; + */ + +extern int pib_init(void); diff --git a/board/mpc832xemds/Makefile b/board/mpc832xemds/Makefile index 5ec7a871d..4da74b827 100644 --- a/board/mpc832xemds/Makefile +++ b/board/mpc832xemds/Makefile @@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a -COBJS := $(BOARD).o pci.o +COBJS := $(BOARD).o pci.o ../freescale/common/pq-mds-pib.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/board/mpc832xemds/mpc832xemds.c b/board/mpc832xemds/mpc832xemds.c index f70783e73..207fcdf8b 100644 --- a/board/mpc832xemds/mpc832xemds.c +++ b/board/mpc832xemds/mpc832xemds.c @@ -32,6 +32,9 @@ #elif defined(CONFIG_OF_LIBFDT) #include #endif +#if defined(CONFIG_PQ_MDS_PIB) +#include "../freescale/common/pq-mds-pib.h" +#endif const qe_iop_conf_t qe_iop_conf_tab[] = { /* ETH3 */ @@ -88,6 +91,14 @@ int board_early_init_f(void) return 0; } +int board_early_init_r(void) +{ +#ifdef CONFIG_PQ_MDS_PIB + pib_init(); +#endif + return 0; +} + int fixed_sdram(void); long int initdram(int board_type) diff --git a/board/mpc832xemds/pci.c b/board/mpc832xemds/pci.c index c2f61ea6a..6bc35c70f 100644 --- a/board/mpc832xemds/pci.c +++ b/board/mpc832xemds/pci.c @@ -131,7 +131,6 @@ void pci_init_board(void) volatile pcictrl83xx_t *pci_ctrl; volatile pciconf83xx_t *pci_conf; - u8 val8, orig_i2c_bus; u16 reg16; u32 val32; u32 dev; @@ -199,43 +198,6 @@ void pci_init_board(void) PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | PIWAR_WTT_SNOOP | PIWAR_IWS_2G; - /* - * Assign PIB PMC slot to desired PCI bus - */ - - /* Switch temporarily to I2C bus #2 */ - orig_i2c_bus = i2c_get_bus_num(); - i2c_set_bus_num(1); - - val8 = 0; - i2c_write(0x23, 0x6, 1, &val8, 1); - i2c_write(0x23, 0x7, 1, &val8, 1); - val8 = 0xff; - i2c_write(0x23, 0x2, 1, &val8, 1); - i2c_write(0x23, 0x3, 1, &val8, 1); - - val8 = 0; - i2c_write(0x26, 0x6, 1, &val8, 1); - val8 = 0x34; - i2c_write(0x26, 0x7, 1, &val8, 1); - - val8 = 0xf9; /* PMC2, PMC3 slot to PCI bus */ - i2c_write(0x26, 0x2, 1, &val8, 1); - val8 = 0xff; - i2c_write(0x26, 0x3, 1, &val8, 1); - - val8 = 0; - i2c_write(0x27, 0x6, 1, &val8, 1); - i2c_write(0x27, 0x7, 1, &val8, 1); - val8 = 0xff; - i2c_write(0x27, 0x2, 1, &val8, 1); - val8 = 0xef; - i2c_write(0x27, 0x3, 1, &val8, 1); - asm("eieio"); - - /* Reset to original I2C bus */ - i2c_set_bus_num(orig_i2c_bus); - /* * Release PCI RST Output signal */ @@ -292,8 +254,6 @@ void pci_init_board(void) pci_hose_write_config_byte(&hose[0], dev, PCI_LATENCY_TIMER, 0x80); pci_hose_write_config_byte(&hose[0], dev, PCI_CACHE_LINE_SIZE, 0x08); - printf("PCI 32bit bus on PMC2 & PMC3\n"); - /* * Hose scan. */ diff --git a/board/mpc8360emds/Makefile b/board/mpc8360emds/Makefile index 5ec7a871d..4da74b827 100644 --- a/board/mpc8360emds/Makefile +++ b/board/mpc8360emds/Makefile @@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a -COBJS := $(BOARD).o pci.o +COBJS := $(BOARD).o pci.o ../freescale/common/pq-mds-pib.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/board/mpc8360emds/mpc8360emds.c b/board/mpc8360emds/mpc8360emds.c index 386173351..d6d0f4e25 100644 --- a/board/mpc8360emds/mpc8360emds.c +++ b/board/mpc8360emds/mpc8360emds.c @@ -30,6 +30,9 @@ #elif defined(CONFIG_OF_LIBFDT) #include #endif +#if defined(CONFIG_PQ_MDS_PIB) +#include "../freescale/common/pq-mds-pib.h" +#endif const qe_iop_conf_t qe_iop_conf_tab[] = { /* GETH1 */ @@ -106,6 +109,14 @@ int board_early_init_f(void) return 0; } +int board_early_init_r(void) +{ +#ifdef CONFIG_PQ_MDS_PIB + pib_init(); +#endif + return 0; +} + #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC) extern void ddr_enable_ecc(unsigned int dram_size); #endif diff --git a/board/mpc8360emds/pci.c b/board/mpc8360emds/pci.c index 79812853e..cf7ef9044 100644 --- a/board/mpc8360emds/pci.c +++ b/board/mpc8360emds/pci.c @@ -131,7 +131,6 @@ void pci_init_board(void) volatile pcictrl83xx_t *pci_ctrl; volatile pciconf83xx_t *pci_conf; - u8 val8, orig_i2c_bus; u16 reg16; u32 val32; u32 dev; @@ -199,43 +198,6 @@ void pci_init_board(void) PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | PIWAR_WTT_SNOOP | PIWAR_IWS_2G; - /* - * Assign PIB PMC slot to desired PCI bus - */ - - /* Switch temporarily to I2C bus #2 */ - orig_i2c_bus = i2c_get_bus_num(); - i2c_set_bus_num(1); - - val8 = 0; - i2c_write(0x23, 0x6, 1, &val8, 1); - i2c_write(0x23, 0x7, 1, &val8, 1); - val8 = 0xff; - i2c_write(0x23, 0x2, 1, &val8, 1); - i2c_write(0x23, 0x3, 1, &val8, 1); - - val8 = 0; - i2c_write(0x26, 0x6, 1, &val8, 1); - val8 = 0x34; - i2c_write(0x26, 0x7, 1, &val8, 1); - - val8 = 0xf3; /*PMC1, PMC2, PMC3 slot to PCI bus */ - i2c_write(0x26, 0x2, 1, &val8, 1); - val8 = 0xff; - i2c_write(0x26, 0x3, 1, &val8, 1); - - val8 = 0; - i2c_write(0x27, 0x6, 1, &val8, 1); - i2c_write(0x27, 0x7, 1, &val8, 1); - val8 = 0xff; - i2c_write(0x27, 0x2, 1, &val8, 1); - val8 = 0xef; - i2c_write(0x27, 0x3, 1, &val8, 1); - asm("eieio"); - - /* Reset to original I2C bus */ - i2c_set_bus_num(orig_i2c_bus); - /* * Release PCI RST Output signal */ @@ -292,8 +254,6 @@ void pci_init_board(void) pci_hose_write_config_byte(&hose[0], dev, PCI_LATENCY_TIMER, 0x80); pci_hose_write_config_byte(&hose[0], dev, PCI_CACHE_LINE_SIZE, 0x08); - printf("PCI 32bit bus on PMC1 & PMC2 & PMC3\n"); - /* * Hose scan. */ diff --git a/include/configs/MPC832XEMDS.h b/include/configs/MPC832XEMDS.h index e8c6b7502..efc317288 100644 --- a/include/configs/MPC832XEMDS.h +++ b/include/configs/MPC832XEMDS.h @@ -30,6 +30,8 @@ #define CONFIG_MPC83XX 1 /* MPC83xx family */ #define CONFIG_MPC832X 1 /* MPC832x CPU specific */ #define CONFIG_MPC832XEMDS 1 /* MPC832XEMDS board specific */ +#undef CONFIG_PQ_MDS_PIB /* POWERQUICC MDS Platform IO Board */ +#undef CONFIG_PQ_MDS_PIB_ATM /* QOC3 ATM card */ /* * System Clock Setup @@ -87,6 +89,7 @@ #define CFG_SICRL 0x00000000 #define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */ +#define CONFIG_BOARD_EARLY_INIT_R /* * IMMR new address diff --git a/include/configs/MPC8360EMDS.h b/include/configs/MPC8360EMDS.h index 4b32a140e..094b66e7c 100644 --- a/include/configs/MPC8360EMDS.h +++ b/include/configs/MPC8360EMDS.h @@ -32,6 +32,8 @@ #define CONFIG_MPC83XX 1 /* MPC83XX family */ #define CONFIG_MPC8360 1 /* MPC8360 CPU specific */ #define CONFIG_MPC8360EMDS 1 /* MPC8360EMDS board specific */ +#undef CONFIG_PQ_MDS_PIB /* POWERQUICC MDS Platform IO Board */ +#undef CONFIG_PQ_MDS_PIB_ATM /* QOC3 ATM card */ /* * System Clock Setup @@ -88,6 +90,7 @@ #define CFG_SICRL 0x40000000 #define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */ +#define CONFIG_BOARD_EARLY_INIT_R /* * IMMR new address @@ -309,13 +312,13 @@ /* * CS4 on Local Bus, to PIB */ -#define CFG_BR4_PRELIM 0xf8008801 /* CS4 base address at 0xf8008000 */ +#define CFG_BR4_PRELIM 0xf8010801 /* CS4 base address at 0xf8010000 */ #define CFG_OR4_PRELIM 0xffffe9f7 /* size 32KB, port size 8bit, GPCM */ /* * CS5 on Local Bus, to PIB */ -#define CFG_BR5_PRELIM 0xf8010801 /* CS5 base address at 0xf8010000 */ +#define CFG_BR5_PRELIM 0xf8008801 /* CS5 base address at 0xf8008000 */ #define CFG_OR5_PRELIM 0xffffe9f7 /* size 32KB, port size 8bit, GPCM */ /* From bbea46f76f767b919070b4829bf34c86bd223248 Mon Sep 17 00:00:00 2001 From: Kim Phillips Date: Thu, 16 Aug 2007 22:52:48 -0500 Subject: [PATCH 168/259] mpc83xx: implement board_add_ram_info add board_add_ram_info, to make memory diagnostic output more consistent. u-boot banner output now looks like: DRAM: 256 MB (DDR1, 64-bit, ECC on) and for boards with SDRAM on the local bus, a line such as this is added: SDRAM: 64 MB (local bus) also replaced some magic numbers with their equivalent define names. Signed-off-by: Kim Phillips --- board/freescale/mpc8323erdb/mpc8323erdb.c | 2 - board/mpc8313erdb/sdram.c | 3 -- board/mpc832xemds/mpc832xemds.c | 2 - board/mpc8349emds/mpc8349emds.c | 8 +--- board/mpc8349itx/mpc8349itx.c | 3 +- board/mpc8360emds/mpc8360emds.c | 5 +-- board/sbc8349/sbc8349.c | 5 +-- board/tqm834x/tqm834x.c | 4 +- cpu/mpc83xx/spd_sdram.c | 54 ++++++++++++++++------- include/configs/MPC8313ERDB.h | 4 +- include/mpc83xx.h | 5 ++- 11 files changed, 50 insertions(+), 45 deletions(-) diff --git a/board/freescale/mpc8323erdb/mpc8323erdb.c b/board/freescale/mpc8323erdb/mpc8323erdb.c index 850d1c370..e73861300 100644 --- a/board/freescale/mpc8323erdb/mpc8323erdb.c +++ b/board/freescale/mpc8323erdb/mpc8323erdb.c @@ -91,8 +91,6 @@ long int initdram(int board_type) msize = fixed_sdram(); - puts("\n DDR RAM: "); - /* return total bus SDRAM size(bytes) -- DDR */ return (msize * 1024 * 1024); } diff --git a/board/mpc8313erdb/sdram.c b/board/mpc8313erdb/sdram.c index 4b6778837..e6e84107e 100644 --- a/board/mpc8313erdb/sdram.c +++ b/board/mpc8313erdb/sdram.c @@ -112,8 +112,6 @@ long int initdram(int board_type) if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im) return -1; - puts("Initializing\n"); - /* DDR SDRAM - Main SODIMM */ msize = fixed_sdram(); @@ -127,7 +125,6 @@ long int initdram(int board_type) resume_from_sleep(); #endif - puts(" DDR RAM: "); /* return total bus SDRAM size(bytes) -- DDR */ return msize; } diff --git a/board/mpc832xemds/mpc832xemds.c b/board/mpc832xemds/mpc832xemds.c index 207fcdf8b..7a45ded76 100644 --- a/board/mpc832xemds/mpc832xemds.c +++ b/board/mpc832xemds/mpc832xemds.c @@ -114,8 +114,6 @@ long int initdram(int board_type) msize = fixed_sdram(); - puts("\n DDR RAM: "); - /* return total bus SDRAM size(bytes) -- DDR */ return (msize * 1024 * 1024); } diff --git a/board/mpc8349emds/mpc8349emds.c b/board/mpc8349emds/mpc8349emds.c index 2ad25ec50..39c091627 100644 --- a/board/mpc8349emds/mpc8349emds.c +++ b/board/mpc8349emds/mpc8349emds.c @@ -70,8 +70,6 @@ long int initdram (int board_type) if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im) return -1; - puts("Initializing\n"); - /* DDR SDRAM - Main SODIMM */ im->sysconf.ddrlaw[0].bar = CFG_DDR_BASE & LAWBAR_BAR; #if defined(CONFIG_SPD_EEPROM) @@ -90,7 +88,7 @@ long int initdram (int board_type) */ ddr_enable_ecc(msize * 1024 * 1024); #endif - puts(" DDR RAM: "); + /* return total bus SDRAM size(bytes) -- DDR */ return (msize * 1024 * 1024); } @@ -191,9 +189,6 @@ void sdram_init(void) volatile lbus83xx_t *lbc= &immap->lbus; uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE; - puts("\n SDRAM on Local Bus: "); - print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n"); - /* * Setup SDRAM Base and Option Registers, already done in cpu_init.c */ @@ -255,7 +250,6 @@ void sdram_init(void) #else void sdram_init(void) { - puts(" SDRAM on Local Bus is NOT available!\n"); } #endif diff --git a/board/mpc8349itx/mpc8349itx.c b/board/mpc8349itx/mpc8349itx.c index 125e6c086..c82f7847a 100644 --- a/board/mpc8349itx/mpc8349itx.c +++ b/board/mpc8349itx/mpc8349itx.c @@ -76,7 +76,7 @@ int fixed_sdram(void) im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1; im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2;/* Was "2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT" */ - im->ddr.sdram_cfg = SDRAM_CFG_SREN | SDRAM_CFG_SDRAM_TYPE_DDR; + im->ddr.sdram_cfg = SDRAM_CFG_SREN | SDRAM_CFG_SDRAM_TYPE_DDR1; im->ddr.sdram_mode = (0x0000 << SDRAM_MODE_ESD_SHIFT) | (0x0032 << SDRAM_MODE_SD_SHIFT); im->ddr.sdram_interval = @@ -162,7 +162,6 @@ long int initdram(int board_type) ddr_enable_ecc(msize * 1048576); #endif - puts(" DDR RAM: "); /* return total bus RAM size(bytes) */ return msize * 1024 * 1024; } diff --git a/board/mpc8360emds/mpc8360emds.c b/board/mpc8360emds/mpc8360emds.c index d6d0f4e25..0751c6faf 100644 --- a/board/mpc8360emds/mpc8360emds.c +++ b/board/mpc8360emds/mpc8360emds.c @@ -149,7 +149,7 @@ long int initdram(int board_type) * Initialize SDRAM if it is on local bus. */ sdram_init(); - puts(" DDR RAM: "); + /* return total bus SDRAM size(bytes) -- DDR */ return (msize * 1024 * 1024); } @@ -234,8 +234,6 @@ void sdram_init(void) volatile lbus83xx_t *lbc = &immap->lbus; uint *sdram_addr = (uint *) CFG_LBC_SDRAM_BASE; - puts("\n SDRAM on Local Bus: "); - print_size(CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n"); /* * Setup SDRAM Base and Option Registers, already done in cpu_init.c */ @@ -291,7 +289,6 @@ void sdram_init(void) #else void sdram_init(void) { - puts("SDRAM on Local Bus is NOT available!\n"); } #endif diff --git a/board/sbc8349/sbc8349.c b/board/sbc8349/sbc8349.c index 4cd447e09..86166ea44 100644 --- a/board/sbc8349/sbc8349.c +++ b/board/sbc8349/sbc8349.c @@ -64,8 +64,6 @@ long int initdram (int board_type) if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im) return -1; - puts("Initializing\n"); - /* DDR SDRAM - Main SODIMM */ im->sysconf.ddrlaw[0].bar = CFG_DDR_BASE & LAWBAR_BAR; #if defined(CONFIG_SPD_EEPROM) @@ -84,7 +82,6 @@ long int initdram (int board_type) */ ddr_enable_ecc(msize * 1024 * 1024); #endif - puts(" DDR RAM: "); /* return total bus SDRAM size(bytes) -- DDR */ return (msize * 1024 * 1024); } @@ -130,7 +127,7 @@ int fixed_sdram(void) #if defined(CONFIG_DDR_2T_TIMING) | SDRAM_CFG_2T_EN #endif - | 2 << SDRAM_CFG_SDRAM_TYPE_SHIFT; + | SDRAM_CFG_SDRAM_TYPE_DDR1; #if defined (CONFIG_DDR_32BIT) /* for 32-bit mode burst length is 8 */ im->ddr.sdram_cfg |= (SDRAM_CFG_32_BE | SDRAM_CFG_8_BE); diff --git a/board/tqm834x/tqm834x.c b/board/tqm834x/tqm834x.c index 9c35e22c8..7d0b05548 100644 --- a/board/tqm834x/tqm834x.c +++ b/board/tqm834x/tqm834x.c @@ -114,7 +114,7 @@ long int initdram (int board_type) /* enable DDR controller */ im->ddr.sdram_cfg = (SDRAM_CFG_MEM_EN | SDRAM_CFG_SREN | - SDRAM_CFG_SDRAM_TYPE_DDR); + SDRAM_CFG_SDRAM_TYPE_DDR1); SYNC; /* size detection */ @@ -388,7 +388,7 @@ static void set_ddr_config(void) { /* don't enable DDR controller yet */ im->ddr.sdram_cfg = SDRAM_CFG_SREN | - SDRAM_CFG_SDRAM_TYPE_DDR; + SDRAM_CFG_SDRAM_TYPE_DDR1; SYNC; /* Set SDRAM mode */ diff --git a/cpu/mpc83xx/spd_sdram.c b/cpu/mpc83xx/spd_sdram.c index 54f0c83d4..040836c42 100644 --- a/cpu/mpc83xx/spd_sdram.c +++ b/cpu/mpc83xx/spd_sdram.c @@ -34,6 +34,30 @@ #include #include +void board_add_ram_info(int use_default) +{ + volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile ddr83xx_t *ddr = &immap->ddr; + + printf(" (DDR%d", ((ddr->sdram_cfg & SDRAM_CFG_SDRAM_TYPE_MASK) + >> SDRAM_CFG_SDRAM_TYPE_SHIFT) - 1); + + if (ddr->sdram_cfg & SDRAM_CFG_32_BE) + puts(", 32-bit"); + else + puts(", 64-bit"); + + if (ddr->sdram_cfg & SDRAM_CFG_ECC_EN) + puts(", ECC on)"); + else + puts(", ECC off)"); + +#if defined(CFG_LB_SDRAM) && defined(CFG_LBC_SDRAM_SIZE) + puts("\nSDRAM: "); + print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, " (local bus)"); +#endif +} + #ifdef CONFIG_SPD_EEPROM DECLARE_GLOBAL_DATA_PTR; @@ -109,7 +133,7 @@ long int spd_sdram() unsigned int n_ranks; unsigned int odt_rd_cfg, odt_wr_cfg; unsigned char twr_clk, twtr_clk; - unsigned char sdram_type; + unsigned int sdram_type; unsigned int memsize; unsigned int law_size; unsigned char caslat, caslat_ctrl; @@ -137,7 +161,7 @@ long int spd_sdram() #endif /* Check the memory type */ if (spd.mem_type != SPD_MEMTYPE_DDR && spd.mem_type != SPD_MEMTYPE_DDR2) { - printf("DDR: Module mem type is %02X\n", spd.mem_type); + debug("DDR: Module mem type is %02X\n", spd.mem_type); return 0; } @@ -578,17 +602,17 @@ long int spd_sdram() burstlen = 0x03; /* 32 bit data bus, burst len is 8 */ else burstlen = 0x02; /* 32 bit data bus, burst len is 4 */ - printf("\n DDR DIMM: data bus width is 32 bit"); + debug("\n DDR DIMM: data bus width is 32 bit"); } else { burstlen = 0x02; /* Others act as 64 bit bus, burst len is 4 */ - printf("\n DDR DIMM: data bus width is 64 bit"); + debug("\n DDR DIMM: data bus width is 64 bit"); } /* Is this an ECC DDR chip? */ if (spd.config == 0x02) - printf(" with ECC\n"); + debug(" with ECC\n"); else - printf(" without ECC\n"); + debug(" without ECC\n"); /* Burst length is always 4 for 64 bit data bus, 8 for 32 bit data bus, Burst type is sequential @@ -718,26 +742,26 @@ long int spd_sdram() * sdram_cfg[13] = 0 (8_BE =0, 4-beat bursts) */ if (spd.mem_type == SPD_MEMTYPE_DDR) - sdram_type = 2; + sdram_type = SDRAM_CFG_SDRAM_TYPE_DDR1; else - sdram_type = 3; + sdram_type = SDRAM_CFG_SDRAM_TYPE_DDR1; sdram_cfg = (0 - | (1 << 31) /* DDR enable */ - | (1 << 30) /* Self refresh */ - | (sdram_type << 24) /* SDRAM type */ + | SDRAM_CFG_MEM_EN /* DDR enable */ + | SDRAM_CFG_SREN /* Self refresh */ + | sdram_type /* SDRAM type */ ); /* sdram_cfg[3] = RD_EN - registered DIMM enable */ if (spd.mod_attr & 0x02) - sdram_cfg |= 0x10000000; + sdram_cfg |= SDRAM_CFG_RD_EN; /* The DIMM is 32bit width */ if (spd.dataw_lsb == 0x20) { if (spd.mem_type == SPD_MEMTYPE_DDR) - sdram_cfg |= 0x000C0000; + sdram_cfg |= SDRAM_CFG_32_BE | SDRAM_CFG_8_BE; if (spd.mem_type == SPD_MEMTYPE_DDR2) - sdram_cfg |= 0x00080000; + sdram_cfg |= SDRAM_CFG_32_BE; } ddrc_ecc_enable = 0; @@ -758,7 +782,7 @@ long int spd_sdram() debug("DDR:err_disable=0x%08x\n", ddr->err_disable); debug("DDR:err_sbe=0x%08x\n", ddr->err_sbe); #endif - printf(" DDRC ECC mode: %s\n", ddrc_ecc_enable ? "ON":"OFF"); + debug(" DDRC ECC mode: %s\n", ddrc_ecc_enable ? "ON":"OFF"); #if defined(CONFIG_DDR_2T_TIMING) /* diff --git a/include/configs/MPC8313ERDB.h b/include/configs/MPC8313ERDB.h index e2ec0bc22..db79ce28f 100644 --- a/include/configs/MPC8313ERDB.h +++ b/include/configs/MPC8313ERDB.h @@ -113,12 +113,12 @@ /* 0x03200064 */ #if defined(CONFIG_DDR_2T_TIMING) #define CFG_SDRAM_CFG ( SDRAM_CFG_SREN \ - | 3 << SDRAM_CFG_SDRAM_TYPE_SHIFT \ + | SDRAM_CFG_SDRAM_TYPE_DDR2 \ | SDRAM_CFG_2T_EN \ | SDRAM_CFG_DBW_32 ) #else #define CFG_SDRAM_CFG ( SDRAM_CFG_SREN \ - | 3 << SDRAM_CFG_SDRAM_TYPE_SHIFT \ + | SDRAM_CFG_SDRAM_TYPE_DDR2 \ | SDRAM_CFG_32_BE ) /* 0x43080000 */ #endif diff --git a/include/mpc83xx.h b/include/mpc83xx.h index 829dbf938..4d32c6a37 100644 --- a/include/mpc83xx.h +++ b/include/mpc83xx.h @@ -705,8 +705,9 @@ #define SDRAM_CFG_SREN 0x40000000 #define SDRAM_CFG_ECC_EN 0x20000000 #define SDRAM_CFG_RD_EN 0x10000000 -#define SDRAM_CFG_SDRAM_TYPE 0x03000000 -#define SDRAM_CFG_SDRAM_TYPE_DDR 0x02000000 +#define SDRAM_CFG_SDRAM_TYPE_DDR1 0x02000000 +#define SDRAM_CFG_SDRAM_TYPE_DDR2 0x03000000 +#define SDRAM_CFG_SDRAM_TYPE_MASK 0x07000000 #define SDRAM_CFG_SDRAM_TYPE_SHIFT 24 #define SDRAM_CFG_DYN_PWR 0x00200000 #define SDRAM_CFG_32_BE 0x00080000 From 5aa4ad8d8e7e9468219990c7875d5fdc9e962f47 Mon Sep 17 00:00:00 2001 From: Kim Phillips Date: Thu, 16 Aug 2007 22:52:59 -0500 Subject: [PATCH 169/259] mpc83xx: suppress unused variable 'val8' warning Signed-off-by: Kim Phillips --- board/freescale/common/pq-mds-pib.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/board/freescale/common/pq-mds-pib.c b/board/freescale/common/pq-mds-pib.c index 9799117a9..8c013c72f 100644 --- a/board/freescale/common/pq-mds-pib.c +++ b/board/freescale/common/pq-mds-pib.c @@ -22,9 +22,10 @@ int pib_init(void) /* Switch temporarily to I2C bus #2 */ orig_i2c_bus = i2c_get_bus_num(); i2c_set_bus_num(1); + + val8 = 0; #if defined(CONFIG_PCI) && !defined(CONFIG_PCISLAVE) /* Assign PIB PMC slot to desired PCI bus */ - val8 = 0; i2c_write(0x23, 0x6, 1, &val8, 1); i2c_write(0x23, 0x7, 1, &val8, 1); val8 = 0xff; From e58fe95784d2514fc9c21028dc59f2b319a35d80 Mon Sep 17 00:00:00 2001 From: Kim Phillips Date: Thu, 16 Aug 2007 22:53:09 -0500 Subject: [PATCH 170/259] mpc83xx: move freescale boards to boards/freescale includes build fixes. Signed-off-by: Kim Phillips --- Makefile | 10 +++++----- board/{ => freescale}/mpc8313erdb/Makefile | 0 board/{ => freescale}/mpc8313erdb/config.mk | 0 board/{ => freescale}/mpc8313erdb/mpc8313erdb.c | 0 board/{ => freescale}/mpc8313erdb/sdram.c | 0 board/{ => freescale}/mpc832xemds/Makefile | 2 +- board/{ => freescale}/mpc832xemds/config.mk | 0 board/{ => freescale}/mpc832xemds/mpc832xemds.c | 2 +- board/{ => freescale}/mpc832xemds/pci.c | 0 board/{ => freescale}/mpc8349emds/Makefile | 0 board/{ => freescale}/mpc8349emds/config.mk | 0 board/{ => freescale}/mpc8349emds/mpc8349emds.c | 0 board/{ => freescale}/mpc8349emds/pci.c | 0 board/{ => freescale}/mpc8349itx/Makefile | 0 board/{ => freescale}/mpc8349itx/config.mk | 0 board/{ => freescale}/mpc8349itx/mpc8349itx.c | 0 board/{ => freescale}/mpc8349itx/pci.c | 0 board/{ => freescale}/mpc8360emds/Makefile | 2 +- board/{ => freescale}/mpc8360emds/config.mk | 0 board/{ => freescale}/mpc8360emds/mpc8360emds.c | 2 +- board/{ => freescale}/mpc8360emds/pci.c | 0 21 files changed, 9 insertions(+), 9 deletions(-) rename board/{ => freescale}/mpc8313erdb/Makefile (100%) rename board/{ => freescale}/mpc8313erdb/config.mk (100%) rename board/{ => freescale}/mpc8313erdb/mpc8313erdb.c (100%) rename board/{ => freescale}/mpc8313erdb/sdram.c (100%) rename board/{ => freescale}/mpc832xemds/Makefile (95%) rename board/{ => freescale}/mpc832xemds/config.mk (100%) rename board/{ => freescale}/mpc832xemds/mpc832xemds.c (99%) rename board/{ => freescale}/mpc832xemds/pci.c (100%) rename board/{ => freescale}/mpc8349emds/Makefile (100%) rename board/{ => freescale}/mpc8349emds/config.mk (100%) rename board/{ => freescale}/mpc8349emds/mpc8349emds.c (100%) rename board/{ => freescale}/mpc8349emds/pci.c (100%) rename board/{ => freescale}/mpc8349itx/Makefile (100%) rename board/{ => freescale}/mpc8349itx/config.mk (100%) rename board/{ => freescale}/mpc8349itx/mpc8349itx.c (100%) rename board/{ => freescale}/mpc8349itx/pci.c (100%) rename board/{ => freescale}/mpc8360emds/Makefile (95%) rename board/{ => freescale}/mpc8360emds/config.mk (100%) rename board/{ => freescale}/mpc8360emds/mpc8360emds.c (99%) rename board/{ => freescale}/mpc8360emds/pci.c (100%) diff --git a/Makefile b/Makefile index 65efd3f5e..62531a5f5 100644 --- a/Makefile +++ b/Makefile @@ -1688,7 +1688,7 @@ MPC8313ERDB_66_config: unconfig echo -n "...66M..." ; \ echo "#define CFG_66MHZ" >>$(obj)include/config.h ; \ fi ; - @$(MKCONFIG) -a MPC8313ERDB ppc mpc83xx mpc8313erdb + @$(MKCONFIG) -a MPC8313ERDB ppc mpc83xx mpc8313erdb freescale MPC8323ERDB_config: unconfig @$(MKCONFIG) -a MPC8323ERDB ppc mpc83xx mpc8323erdb freescale @@ -1716,10 +1716,10 @@ MPC832XEMDS_SLAVE_config: unconfig echo -n "...66M..." ; \ echo "#define PCI_66M" >>$(obj)include/config.h ; \ fi ; - @$(MKCONFIG) -a MPC832XEMDS ppc mpc83xx mpc832xemds + @$(MKCONFIG) -a MPC832XEMDS ppc mpc83xx mpc832xemds freescale MPC8349EMDS_config: unconfig - @$(MKCONFIG) $(@:_config=) ppc mpc83xx mpc8349emds + @$(MKCONFIG) $(@:_config=) ppc mpc83xx mpc8349emds freescale MPC8349ITX_config \ MPC8349ITX_LOWBOOT_config \ @@ -1733,7 +1733,7 @@ MPC8349ITXGP_config: unconfig @if [ "$(findstring LOWBOOT,$@)" ] ; then \ echo "TEXT_BASE = 0xFE000000" >$(obj)board/mpc8349itx/config.tmp ; \ fi - @$(MKCONFIG) -a -n $(@:_config=) MPC8349ITX ppc mpc83xx mpc8349itx + @$(MKCONFIG) -a -n $(@:_config=) MPC8349ITX ppc mpc83xx mpc8349itx freescale MPC8360EMDS_config \ MPC8360EMDS_HOST_33_config \ @@ -1758,7 +1758,7 @@ MPC8360EMDS_SLAVE_config: unconfig echo -n "...66M..." ; \ echo "#define PCI_66M" >>$(obj)include/config.h ; \ fi ; - @$(MKCONFIG) -a MPC8360EMDS ppc mpc83xx mpc8360emds + @$(MKCONFIG) -a MPC8360EMDS ppc mpc83xx mpc8360emds freescale sbc8349_config: unconfig @$(MKCONFIG) $(@:_config=) ppc mpc83xx sbc8349 diff --git a/board/mpc8313erdb/Makefile b/board/freescale/mpc8313erdb/Makefile similarity index 100% rename from board/mpc8313erdb/Makefile rename to board/freescale/mpc8313erdb/Makefile diff --git a/board/mpc8313erdb/config.mk b/board/freescale/mpc8313erdb/config.mk similarity index 100% rename from board/mpc8313erdb/config.mk rename to board/freescale/mpc8313erdb/config.mk diff --git a/board/mpc8313erdb/mpc8313erdb.c b/board/freescale/mpc8313erdb/mpc8313erdb.c similarity index 100% rename from board/mpc8313erdb/mpc8313erdb.c rename to board/freescale/mpc8313erdb/mpc8313erdb.c diff --git a/board/mpc8313erdb/sdram.c b/board/freescale/mpc8313erdb/sdram.c similarity index 100% rename from board/mpc8313erdb/sdram.c rename to board/freescale/mpc8313erdb/sdram.c diff --git a/board/mpc832xemds/Makefile b/board/freescale/mpc832xemds/Makefile similarity index 95% rename from board/mpc832xemds/Makefile rename to board/freescale/mpc832xemds/Makefile index 4da74b827..ea52484c0 100644 --- a/board/mpc832xemds/Makefile +++ b/board/freescale/mpc832xemds/Makefile @@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a -COBJS := $(BOARD).o pci.o ../freescale/common/pq-mds-pib.o +COBJS := $(BOARD).o pci.o ../common/pq-mds-pib.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/board/mpc832xemds/config.mk b/board/freescale/mpc832xemds/config.mk similarity index 100% rename from board/mpc832xemds/config.mk rename to board/freescale/mpc832xemds/config.mk diff --git a/board/mpc832xemds/mpc832xemds.c b/board/freescale/mpc832xemds/mpc832xemds.c similarity index 99% rename from board/mpc832xemds/mpc832xemds.c rename to board/freescale/mpc832xemds/mpc832xemds.c index 7a45ded76..6ba25d464 100644 --- a/board/mpc832xemds/mpc832xemds.c +++ b/board/freescale/mpc832xemds/mpc832xemds.c @@ -33,7 +33,7 @@ #include #endif #if defined(CONFIG_PQ_MDS_PIB) -#include "../freescale/common/pq-mds-pib.h" +#include "../common/pq-mds-pib.h" #endif const qe_iop_conf_t qe_iop_conf_tab[] = { diff --git a/board/mpc832xemds/pci.c b/board/freescale/mpc832xemds/pci.c similarity index 100% rename from board/mpc832xemds/pci.c rename to board/freescale/mpc832xemds/pci.c diff --git a/board/mpc8349emds/Makefile b/board/freescale/mpc8349emds/Makefile similarity index 100% rename from board/mpc8349emds/Makefile rename to board/freescale/mpc8349emds/Makefile diff --git a/board/mpc8349emds/config.mk b/board/freescale/mpc8349emds/config.mk similarity index 100% rename from board/mpc8349emds/config.mk rename to board/freescale/mpc8349emds/config.mk diff --git a/board/mpc8349emds/mpc8349emds.c b/board/freescale/mpc8349emds/mpc8349emds.c similarity index 100% rename from board/mpc8349emds/mpc8349emds.c rename to board/freescale/mpc8349emds/mpc8349emds.c diff --git a/board/mpc8349emds/pci.c b/board/freescale/mpc8349emds/pci.c similarity index 100% rename from board/mpc8349emds/pci.c rename to board/freescale/mpc8349emds/pci.c diff --git a/board/mpc8349itx/Makefile b/board/freescale/mpc8349itx/Makefile similarity index 100% rename from board/mpc8349itx/Makefile rename to board/freescale/mpc8349itx/Makefile diff --git a/board/mpc8349itx/config.mk b/board/freescale/mpc8349itx/config.mk similarity index 100% rename from board/mpc8349itx/config.mk rename to board/freescale/mpc8349itx/config.mk diff --git a/board/mpc8349itx/mpc8349itx.c b/board/freescale/mpc8349itx/mpc8349itx.c similarity index 100% rename from board/mpc8349itx/mpc8349itx.c rename to board/freescale/mpc8349itx/mpc8349itx.c diff --git a/board/mpc8349itx/pci.c b/board/freescale/mpc8349itx/pci.c similarity index 100% rename from board/mpc8349itx/pci.c rename to board/freescale/mpc8349itx/pci.c diff --git a/board/mpc8360emds/Makefile b/board/freescale/mpc8360emds/Makefile similarity index 95% rename from board/mpc8360emds/Makefile rename to board/freescale/mpc8360emds/Makefile index 4da74b827..ea52484c0 100644 --- a/board/mpc8360emds/Makefile +++ b/board/freescale/mpc8360emds/Makefile @@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a -COBJS := $(BOARD).o pci.o ../freescale/common/pq-mds-pib.o +COBJS := $(BOARD).o pci.o ../common/pq-mds-pib.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/board/mpc8360emds/config.mk b/board/freescale/mpc8360emds/config.mk similarity index 100% rename from board/mpc8360emds/config.mk rename to board/freescale/mpc8360emds/config.mk diff --git a/board/mpc8360emds/mpc8360emds.c b/board/freescale/mpc8360emds/mpc8360emds.c similarity index 99% rename from board/mpc8360emds/mpc8360emds.c rename to board/freescale/mpc8360emds/mpc8360emds.c index 0751c6faf..e050cd439 100644 --- a/board/mpc8360emds/mpc8360emds.c +++ b/board/freescale/mpc8360emds/mpc8360emds.c @@ -31,7 +31,7 @@ #include #endif #if defined(CONFIG_PQ_MDS_PIB) -#include "../freescale/common/pq-mds-pib.h" +#include "../common/pq-mds-pib.h" #endif const qe_iop_conf_t qe_iop_conf_tab[] = { diff --git a/board/mpc8360emds/pci.c b/board/freescale/mpc8360emds/pci.c similarity index 100% rename from board/mpc8360emds/pci.c rename to board/freescale/mpc8360emds/pci.c From 4cc1cd5941827a04cf5c51a07fcc42e8945894aa Mon Sep 17 00:00:00 2001 From: Kim Phillips Date: Fri, 17 Aug 2007 09:30:00 -0500 Subject: [PATCH 171/259] mpc83xx: fix typo in DDR2 programming introduced in the implement board_add_ram_info patch as I was cleaning out the magic numbers. sorry. Signed-off-by: Kim Phillips --- cpu/mpc83xx/spd_sdram.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/cpu/mpc83xx/spd_sdram.c b/cpu/mpc83xx/spd_sdram.c index 040836c42..ee2d0385e 100644 --- a/cpu/mpc83xx/spd_sdram.c +++ b/cpu/mpc83xx/spd_sdram.c @@ -744,7 +744,7 @@ long int spd_sdram() if (spd.mem_type == SPD_MEMTYPE_DDR) sdram_type = SDRAM_CFG_SDRAM_TYPE_DDR1; else - sdram_type = SDRAM_CFG_SDRAM_TYPE_DDR1; + sdram_type = SDRAM_CFG_SDRAM_TYPE_DDR2; sdram_cfg = (0 | SDRAM_CFG_MEM_EN /* DDR enable */ From 4a442d3186b31893b4f77c6e82f63c4517a5224b Mon Sep 17 00:00:00 2001 From: TsiChungLiew Date: Thu, 16 Aug 2007 19:23:50 -0500 Subject: [PATCH 172/259] ColdFire: Add M5235EVB Platform for MCF523x Signed-off-by: TsiChungLiew --- CREDITS | 2 +- MAINTAINERS | 1 + MAKEALL | 1 + Makefile | 25 +- board/freescale/m5235evb/Makefile | 44 ++ board/freescale/m5235evb/config.mk | 28 + board/freescale/m5235evb/m5235evb.c | 117 ++++ board/freescale/m5235evb/mii.c | 307 ++++++++++ board/freescale/m5235evb/u-boot.16 | 145 +++++ board/freescale/m5235evb/u-boot.32 | 153 +++++ board/freescale/m5235evb/u-boot.lds | 145 +++++ cpu/mcf523x/Makefile | 48 ++ cpu/mcf523x/config.mk | 27 + cpu/mcf523x/cpu.c | 109 ++++ cpu/mcf523x/cpu_init.c | 145 +++++ cpu/mcf523x/interrupts.c | 49 ++ cpu/mcf523x/speed.c | 48 ++ cpu/mcf523x/start.S | 340 +++++++++++ include/asm-m68k/immap.h | 29 + include/asm-m68k/immap_5235.h | 378 ++++++++++++ include/asm-m68k/m5235.h | 905 ++++++++++++++++++++++++++++ include/configs/M5235EVB.h | 261 ++++++++ 22 files changed, 3303 insertions(+), 4 deletions(-) create mode 100644 board/freescale/m5235evb/Makefile create mode 100644 board/freescale/m5235evb/config.mk create mode 100644 board/freescale/m5235evb/m5235evb.c create mode 100644 board/freescale/m5235evb/mii.c create mode 100644 board/freescale/m5235evb/u-boot.16 create mode 100644 board/freescale/m5235evb/u-boot.32 create mode 100644 board/freescale/m5235evb/u-boot.lds create mode 100644 cpu/mcf523x/Makefile create mode 100644 cpu/mcf523x/config.mk create mode 100644 cpu/mcf523x/cpu.c create mode 100644 cpu/mcf523x/cpu_init.c create mode 100644 cpu/mcf523x/interrupts.c create mode 100644 cpu/mcf523x/speed.c create mode 100644 cpu/mcf523x/start.S create mode 100644 include/asm-m68k/immap_5235.h create mode 100644 include/asm-m68k/m5235.h create mode 100644 include/configs/M5235EVB.h diff --git a/CREDITS b/CREDITS index f30b2228f..6e44db470 100644 --- a/CREDITS +++ b/CREDITS @@ -491,7 +491,7 @@ W: www.monstr.eu N: TsiChung Liew E: Tsi-Chung.Liew@freescale.com -D: Support for ColdFire MCF532x, MCF5445x +D: Support for ColdFire MCF523x, MCF532x, MCF5445x W: www.freescale.com N: Hayden Fraser diff --git a/MAINTAINERS b/MAINTAINERS index 7fde6d99e..d15028665 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -608,6 +608,7 @@ Zachary P. Landau TsiChung Liew + M5235EVB mcf52x2 M5329EVB mcf532x M54455EVB mcf5445x diff --git a/MAKEALL b/MAKEALL index b7ed0f430..125c78275 100755 --- a/MAKEALL +++ b/MAKEALL @@ -618,6 +618,7 @@ LIST_coldfire=" \ EB+MCF-EV123 \ EB+MCF-EV123_internal \ idmr \ + M5235EVB \ M5249EVB \ M5253EVB \ M5271EVB \ diff --git a/Makefile b/Makefile index 201ad0e77..7b2b0252d 100644 --- a/Makefile +++ b/Makefile @@ -1639,6 +1639,25 @@ ZPC1900_config: unconfig ## Coldfire ######################################################################### +M5235EVB_config \ +M5235EVB_Flash16_config \ +M5235EVB_Flash32_config: unconfig + @case "$@" in \ + M5235EVB_config) FLASH=16;; \ + M5235EVB_Flash16_config) FLASH=16;; \ + M5235EVB_Flash32_config) FLASH=32;; \ + esac; \ + >include/config.h ; \ + if [ "$${FLASH}" != "16" ] ; then \ + echo "#define NORFLASH_PS32BIT 1" >> include/config.h ; \ + echo "TEXT_BASE = 0xFFC00000" > $(obj)board/freescale/m5235evb/config.tmp ; \ + cp $(obj)board/freescale/m5235evb/u-boot.32 $(obj)board/freescale/m5235evb/u-boot.lds ; \ + else \ + echo "TEXT_BASE = 0xFFE00000" > $(obj)board/freescale/m5235evb/config.tmp ; \ + cp $(obj)board/freescale/m5235evb/u-boot.16 $(obj)board/freescale/m5235evb/u-boot.lds ; \ + fi + @$(MKCONFIG) -a M5235EVB m68k mcf523x m5235evb freescale + M5249EVB_config : unconfig @$(MKCONFIG) $(@:_config=) m68k mcf52x2 m5249evb freescale @@ -1710,13 +1729,13 @@ M54455EVB_i66_config : unconfig esac; \ >include/config.h ; \ if [ "$${FLASH}" == "INTEL" ] ; then \ - echo "#undef CFG_ATMEL_BOOT" >> include/config.h ; \ + echo "#undef CFG_ATMEL_BOOT" >> $(obj)include/config.h ; \ echo "... with INTEL boot..." ; \ else \ - echo "#define CFG_ATMEL_BOOT" >> include/config.h ; \ + echo "#define CFG_ATMEL_BOOT" >> $(obj)include/config.h ; \ echo "... with ATMEL boot..." ; \ fi; \ - echo "#define CFG_INPUT_CLKSRC $${FREQ}" >>include/config.h ; \ + echo "#define CFG_INPUT_CLKSRC $${FREQ}" >> $(obj)include/config.h ; \ echo "... with $${FREQ}Hz input clock" @$(MKCONFIG) -a M54455EVB m68k mcf5445x m54455evb freescale diff --git a/board/freescale/m5235evb/Makefile b/board/freescale/m5235evb/Makefile new file mode 100644 index 000000000..74c252869 --- /dev/null +++ b/board/freescale/m5235evb/Makefile @@ -0,0 +1,44 @@ +# +# (C) Copyright 2000-2003 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS = $(BOARD).o mii.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/freescale/m5235evb/config.mk b/board/freescale/m5235evb/config.mk new file mode 100644 index 000000000..ada38dd95 --- /dev/null +++ b/board/freescale/m5235evb/config.mk @@ -0,0 +1,28 @@ +# +# (C) Copyright 2000-2003 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# Coldfire contribution by Bernhard Kuhn +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +/*TEXT_BASE = 0xFFC00000*/ +sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp + +PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) \ No newline at end of file diff --git a/board/freescale/m5235evb/m5235evb.c b/board/freescale/m5235evb/m5235evb.c new file mode 100644 index 000000000..585854cd9 --- /dev/null +++ b/board/freescale/m5235evb/m5235evb.c @@ -0,0 +1,117 @@ +/* + * (C) Copyright 2000-2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +int checkboard(void) +{ + puts("Board: "); + puts("Freescale M5235 EVB\n"); + return 0; +}; + +long int initdram(int board_type) +{ + volatile sdram_t *sdram = (volatile sdram_t *)(MMAP_SDRAM); + volatile gpio_t *gpio = (volatile gpio_t *)(MMAP_GPIO); + u32 dramsize, i, dramclk; + + /* + * When booting from external Flash, the port-size is less than + * the port-size of SDRAM. In this case it is necessary to enable + * Data[15:0] on Port Address/Data. + */ + gpio->par_ad = + GPIO_PAR_AD_ADDR23 | GPIO_PAR_AD_ADDR22 | GPIO_PAR_AD_ADDR21 | + GPIO_PAR_AD_DATAL; + + /* Initialize PAR to enable SDRAM signals */ + gpio->par_sdram = + GPIO_PAR_SDRAM_SDWE | GPIO_PAR_SDRAM_SCAS | GPIO_PAR_SDRAM_SRAS | + GPIO_PAR_SDRAM_SCKE | GPIO_PAR_SDRAM_SDCS(3); + + dramsize = CFG_SDRAM_SIZE * 0x100000; + for (i = 0x13; i < 0x20; i++) { + if (dramsize == (1 << i)) + break; + } + i--; + + if (!(sdram->dacr0 & SDRAMC_DARCn_RE)) { + dramclk = gd->bus_clk / (CFG_HZ * CFG_HZ); + + /* Initialize DRAM Control Register: DCR */ + sdram->dcr = SDRAMC_DCR_RTIM_9CLKS | + SDRAMC_DCR_RTIM_6CLKS | SDRAMC_DCR_RC((15 * dramclk) >> 4); + + /* Initialize DACR0 */ + sdram->dacr0 = + SDRAMC_DARCn_BA(CFG_SDRAM_BASE) | SDRAMC_DARCn_CASL_C1 | + SDRAMC_DARCn_CBM_CMD20 | SDRAMC_DARCn_PS_32; + + /* Initialize DMR0 */ + sdram->dmr0 = ((dramsize - 1) & 0xFFFC0000) | SDRAMC_DMRn_V; + + /* Set IP (bit 3) in DACR */ + sdram->dacr0 |= SDRAMC_DARCn_IP; + + /* Wait 30ns to allow banks to precharge */ + for (i = 0; i < 5; i++) { + asm("nop"); + } + + /* Write to this block to initiate precharge */ + *(u32 *) (CFG_SDRAM_BASE) = 0xA5A59696; + + /* Set RE (bit 15) in DACR */ + sdram->dacr0 |= SDRAMC_DARCn_RE; + + /* Wait for at least 8 auto refresh cycles to occur */ + for (i = 0; i < 0x2000; i++) { + asm("nop"); + } + + /* Finish the configuration by issuing the MRS. */ + sdram->dacr0 |= SDRAMC_DARCn_IMRS; + + /* Write to the SDRAM Mode Register */ + *(u32 *) (CFG_SDRAM_BASE + 0x400) = 0xA5A59696; + } + + return dramsize; +}; + +int testdram(void) +{ + /* TODO: XXX XXX XXX */ + printf("DRAM test not implemented!\n"); + + return (0); +} diff --git a/board/freescale/m5235evb/mii.c b/board/freescale/m5235evb/mii.c new file mode 100644 index 000000000..58fabdf32 --- /dev/null +++ b/board/freescale/m5235evb/mii.c @@ -0,0 +1,307 @@ +/* + * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI) +#undef MII_DEBUG +#undef ET_DEBUG + +int fecpin_setclear(struct eth_device *dev, int setclear) +{ + volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; + + if (setclear) { + gpio->par_feci2c |= + (GPIO_PAR_FECI2C_EMDC_FECEMDC | GPIO_PAR_FECI2C_EMDIO_FECEMDIO); + } else { + gpio->par_feci2c &= + ~(GPIO_PAR_FECI2C_EMDC_MASK | GPIO_PAR_FECI2C_EMDIO_MASK); + } + + return 0; +} + +#if defined(CFG_DISCOVER_PHY) || defined(CONFIG_MII) +#include + +/* Make MII read/write commands for the FEC. */ +#define mk_mii_read(ADDR, REG) (0x60020000 | ((ADDR << 23) | (REG & 0x1f) << 18)) + +#define mk_mii_write(ADDR, REG, VAL) (0x50020000 | ((ADDR << 23) | (REG & 0x1f) << 18) | (VAL & 0xffff)) + +/* PHY identification */ +#define PHY_ID_LXT970 0x78100000 /* LXT970 */ +#define PHY_ID_LXT971 0x001378e0 /* LXT971 and 972 */ +#define PHY_ID_82555 0x02a80150 /* Intel 82555 */ +#define PHY_ID_QS6612 0x01814400 /* QS6612 */ +#define PHY_ID_AMD79C784 0x00225610 /* AMD 79C784 */ +#define PHY_ID_LSI80225 0x0016f870 /* LSI 80225 */ +#define PHY_ID_LSI80225B 0x0016f880 /* LSI 80225/B */ +#define PHY_ID_DP83848VV 0x20005C90 /* National 83848 */ +#define PHY_ID_DP83849 0x20005CA2 /* National 82849 */ +#define PHY_ID_KS8721BL 0x00221619 /* Micrel KS8721BL/SL */ + +#define STR_ID_LXT970 "LXT970" +#define STR_ID_LXT971 "LXT971" +#define STR_ID_82555 "Intel82555" +#define STR_ID_QS6612 "QS6612" +#define STR_ID_AMD79C784 "AMD79C784" +#define STR_ID_LSI80225 "LSI80225" +#define STR_ID_LSI80225B "LSI80225/B" +#define STR_ID_DP83848VV "N83848" +#define STR_ID_DP83849 "N83849" +#define STR_ID_KS8721BL "KS8721BL" + +/**************************************************************************** + * mii_init -- Initialize the MII for MII command without ethernet + * This function is a subset of eth_init + **************************************************************************** + */ +void mii_reset(struct fec_info_s *info) +{ + volatile fec_t *fecp = (fec_t *) (info->miibase); + int i; + + fecp->ecr = FEC_ECR_RESET; + for (i = 0; (fecp->ecr & FEC_ECR_RESET) && (i < FEC_RESET_DELAY); ++i) { + udelay(1); + } + if (i == FEC_RESET_DELAY) { + printf("FEC_RESET_DELAY timeout\n"); + } +} + +/* send command to phy using mii, wait for result */ +uint mii_send(uint mii_cmd) +{ + struct fec_info_s *info; + struct eth_device *dev; + volatile fec_t *ep; + uint mii_reply; + int j = 0; + + /* retrieve from register structure */ + dev = eth_get_dev(); + info = dev->priv; + + ep = (fec_t *) info->miibase; + + ep->mmfr = mii_cmd; /* command to phy */ + + /* wait for mii complete */ + while (!(ep->eir & FEC_EIR_MII) && (j < MCFFEC_TOUT_LOOP)) { + udelay(1); + j++; + } + if (j >= MCFFEC_TOUT_LOOP) { + printf("MII not complete\n"); + return -1; + } + + mii_reply = ep->mmfr; /* result from phy */ + ep->eir = FEC_EIR_MII; /* clear MII complete */ +#ifdef ET_DEBUG + printf("%s[%d] %s: sent=0x%8.8x, reply=0x%8.8x\n", + __FILE__, __LINE__, __FUNCTION__, mii_cmd, mii_reply); +#endif + + return (mii_reply & 0xffff); /* data read from phy */ +} +#endif /* CFG_DISCOVER_PHY || (CONFIG_MII) */ + +#if defined(CFG_DISCOVER_PHY) +int mii_discover_phy(struct eth_device *dev) +{ +#define MAX_PHY_PASSES 11 + struct fec_info_s *info = dev->priv; + int phyaddr, pass; + uint phyno, phytype; + + if (info->phyname_init) + return info->phy_addr; + + phyaddr = -1; /* didn't find a PHY yet */ + for (pass = 1; pass <= MAX_PHY_PASSES && phyaddr < 0; ++pass) { + if (pass > 1) { + /* PHY may need more time to recover from reset. + * The LXT970 needs 50ms typical, no maximum is + * specified, so wait 10ms before try again. + * With 11 passes this gives it 100ms to wake up. + */ + udelay(10000); /* wait 10ms */ + } + + for (phyno = 0; phyno < 32 && phyaddr < 0; ++phyno) { + + phytype = mii_send(mk_mii_read(phyno, PHY_PHYIDR1)); +#ifdef ET_DEBUG + printf("PHY type 0x%x pass %d type\n", phytype, pass); +#endif + if (phytype != 0xffff) { + phyaddr = phyno; + phytype <<= 16; + phytype |= + mii_send(mk_mii_read(phyno, PHY_PHYIDR2)); + + switch (phytype & 0xffffffff) { + case PHY_ID_KS8721BL: + strcpy(info->phy_name, + STR_ID_KS8721BL); + info->phyname_init = 1; + break; + default: + strcpy(info->phy_name, "unknown"); + info->phyname_init = 1; + break; + } + +#ifdef ET_DEBUG + printf("PHY @ 0x%x pass %d type ", phyno, pass); + switch (phytype & 0xffffffff) { + case PHY_ID_KS8721BL: + printf(STR_ID_KS8721BL); + break; + default: + printf("0x%08x\n", phytype); + break; + } +#endif + } + } + } + if (phyaddr < 0) + printf("No PHY device found.\n"); + + return phyaddr; +} +#endif /* CFG_DISCOVER_PHY */ + +int mii_init(void) __attribute__((weak,alias("__mii_init"))); + +void __mii_init(void) +{ + volatile fec_t *fecp; + struct fec_info_s *info; + struct eth_device *dev; + int miispd = 0, i = 0; + u16 autoneg = 0; + + /* retrieve from register structure */ + dev = eth_get_dev(); + info = dev->priv; + + fecp = (fec_t *) info->miibase; + + fecpin_setclear(dev, 1); + + mii_reset(info); + + /* We use strictly polling mode only */ + fecp->eimr = 0; + + /* Clear any pending interrupt */ + fecp->eir = 0xffffffff; + + /* Set MII speed */ + miispd = (gd->bus_clk / 1000000) / 5; + fecp->mscr = miispd << 1; + + info->phy_addr = mii_discover_phy(dev); + +#define AUTONEGLINK (PHY_BMSR_AUTN_COMP | PHY_BMSR_LS) + while (i < MCFFEC_TOUT_LOOP) { + autoneg = 0; + miiphy_read(dev->name, info->phy_addr, PHY_BMSR, &autoneg); + i++; + + if ((autoneg & AUTONEGLINK) == AUTONEGLINK) + break; + + udelay(500); + } + if (i >= MCFFEC_TOUT_LOOP) { + printf("Auto Negotiation not complete\n"); + } + + /* adapt to the half/full speed settings */ + info->dup_spd = miiphy_duplex(dev->name, info->phy_addr) << 16; + info->dup_spd |= miiphy_speed(dev->name, info->phy_addr); +} + +/***************************************************************************** + * Read and write a MII PHY register, routines used by MII Utilities + * + * FIXME: These routines are expected to return 0 on success, but mii_send + * does _not_ return an error code. Maybe 0xFFFF means error, i.e. + * no PHY connected... + * For now always return 0. + * FIXME: These routines only work after calling eth_init() at least once! + * Otherwise they hang in mii_send() !!! Sorry! + *****************************************************************************/ + +int mcffec_miiphy_read(char *devname, unsigned char addr, unsigned char reg, + unsigned short *value) +{ + short rdreg; /* register working value */ + +#ifdef MII_DEBUG + printf("miiphy_read(0x%x) @ 0x%x = ", reg, addr); +#endif + rdreg = mii_send(mk_mii_read(addr, reg)); + + *value = rdreg; + +#ifdef MII_DEBUG + printf("0x%04x\n", *value); +#endif + + return 0; +} + +int mcffec_miiphy_write(char *devname, unsigned char addr, unsigned char reg, + unsigned short value) +{ + short rdreg; /* register working value */ + +#ifdef MII_DEBUG + printf("miiphy_write(0x%x) @ 0x%x = ", reg, addr); +#endif + + rdreg = mii_send(mk_mii_write(addr, reg, value)); + +#ifdef MII_DEBUG + printf("0x%04x\n", value); +#endif + + return 0; +} + +#endif /* CONFIG_CMD_NET, FEC_ENET & NET_MULTI */ diff --git a/board/freescale/m5235evb/u-boot.16 b/board/freescale/m5235evb/u-boot.16 new file mode 100644 index 000000000..8ffd32607 --- /dev/null +++ b/board/freescale/m5235evb/u-boot.16 @@ -0,0 +1,145 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(m68k) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/mcf523x/start.o (.text) + cpu/mcf523x/cpu_init.o (.text) + lib_m68k/traps.o (.text) + lib_m68k/interrupts.o (.text) + common/dlmalloc.o (.text) + lib_generic/zlib.o (.text) + + . = DEFINED(env_offset) ? env_offset : .; + common/environment.o (.text) + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + + .reloc : + { + __got_start = .; + *(.got) + __got_end = .; + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + _sbss = .; + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + . = ALIGN(4); + _ebss = .; + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/freescale/m5235evb/u-boot.32 b/board/freescale/m5235evb/u-boot.32 new file mode 100644 index 000000000..9b72f66c6 --- /dev/null +++ b/board/freescale/m5235evb/u-boot.32 @@ -0,0 +1,153 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(m68k) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/mcf523x/start.o (.text) + cpu/mcf523x/cpu.o (.text) + cpu/mcf523x/cpu_init.o (.text) + cpu/mcf523x/interrupts.o (.text) + cpu/mcf523x/speed.o (.text) + lib_m68k/libm68k.a (.text) + common/dlmalloc.o (.text) + common/cmd_bootm.o (.text) + common/cmd_flash.o (.text) + common/cmd_elf.o (.text) + common/cmd_mem.o (.text) + common/console.o (.text) + common/main.o (.text) + lib_generic/libgeneric.a (.text) + + . = DEFINED(env_offset) ? env_offset : .; + common/environment.o (.text) + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + + .reloc : + { + __got_start = .; + *(.got) + __got_end = .; + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + _sbss = .; + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + . = ALIGN(4); + _ebss = .; + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/freescale/m5235evb/u-boot.lds b/board/freescale/m5235evb/u-boot.lds new file mode 100644 index 000000000..8ffd32607 --- /dev/null +++ b/board/freescale/m5235evb/u-boot.lds @@ -0,0 +1,145 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(m68k) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/mcf523x/start.o (.text) + cpu/mcf523x/cpu_init.o (.text) + lib_m68k/traps.o (.text) + lib_m68k/interrupts.o (.text) + common/dlmalloc.o (.text) + lib_generic/zlib.o (.text) + + . = DEFINED(env_offset) ? env_offset : .; + common/environment.o (.text) + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + + .reloc : + { + __got_start = .; + *(.got) + __got_end = .; + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + _sbss = .; + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + . = ALIGN(4); + _ebss = .; + } + _end = . ; + PROVIDE (end = .); +} diff --git a/cpu/mcf523x/Makefile b/cpu/mcf523x/Makefile new file mode 100644 index 000000000..d0e9b4550 --- /dev/null +++ b/cpu/mcf523x/Makefile @@ -0,0 +1,48 @@ +# +# (C) Copyright 2000-2004 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +# CFLAGS += -DET_DEBUG + +LIB = lib$(CPU).a + +START = start.o +COBJS = cpu.o speed.o cpu_init.o interrupts.o + +SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) +START := $(addprefix $(obj),$(START)) + +all: $(obj).depend $(START) $(LIB) + +$(LIB): $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +######################################################################### + +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/cpu/mcf523x/config.mk b/cpu/mcf523x/config.mk new file mode 100644 index 000000000..ba324a894 --- /dev/null +++ b/cpu/mcf523x/config.mk @@ -0,0 +1,27 @@ +# +# (C) Copyright 2003 Josef Baumgartner +# +# (C) Copyright 2000-2004 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +PLATFORM_RELFLAGS += -ffixed-d7 -msep-data +PLATFORM_CPPFLAGS += -m5307 -fPIC diff --git a/cpu/mcf523x/cpu.c b/cpu/mcf523x/cpu.c new file mode 100644 index 000000000..f0d954b3f --- /dev/null +++ b/cpu/mcf523x/cpu.c @@ -0,0 +1,109 @@ +/* + * + * (C) Copyright 2000-2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +#include + +DECLARE_GLOBAL_DATA_PTR; + +int do_reset(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char *argv[]) +{ + volatile ccm_t *ccm = (ccm_t *) MMAP_CCM; + + ccm->rcr = CCM_RCR_SOFTRST; + /* we don't return! */ + return 0; +}; + +int checkcpu(void) +{ + volatile ccm_t *ccm = (ccm_t *) MMAP_CCM; + u16 msk; + u16 id = 0; + u8 ver; + + puts("CPU: "); + msk = (ccm->cir >> 6); + ver = (ccm->cir & 0x003f); + switch (msk) { + case 0x31: + id = 5235; + break; + } + + if (id) { + printf("Freescale MCF%d (Mask:%01x Version:%x)\n", id, msk, + ver); + printf(" CPU CLK %d Mhz BUS CLK %d Mhz\n", + (int)(gd->cpu_clk / 1000000), + (int)(gd->bus_clk / 1000000)); + } + + return 0; +}; + +#if defined(CONFIG_WATCHDOG) +/* Called by macro WATCHDOG_RESET */ +void watchdog_reset(void) +{ + volatile wdog_t *wdp = (wdog_t *) (MMAP_WDOG); + + wdp->sr = 0x5555; /* Count register */ + asm("nop"); + wdp->sr = 0xAAAA; /* Count register */ +} + +int watchdog_disable(void) +{ + volatile wdog_t *wdp = (wdog_t *) (MMAP_WDOG); + + /* UserManual, once the wdog is disabled, wdog cannot be re-enabled */ + wdp->cr |= WTM_WCR_HALTED; /* halted watchdog timer */ + + puts("WATCHDOG:disabled\n"); + return (0); +} + +int watchdog_init(void) +{ + volatile wdog_t *wdp = (wdog_t *) (MMAP_WDOG); + u32 wdog_module = 0; + + /* set timeout and enable watchdog */ + wdog_module = ((CFG_CLK / CFG_HZ) * CONFIG_WATCHDOG_TIMEOUT); + wdog_module |= (wdog_module / 8192); + wdp->mr = wdog_module; + + wdp->cr = WTM_WCR_EN; + puts("WATCHDOG:enabled\n"); + + return (0); +} +#endif /* CONFIG_WATCHDOG */ diff --git a/cpu/mcf523x/cpu_init.c b/cpu/mcf523x/cpu_init.c new file mode 100644 index 000000000..a31054d9a --- /dev/null +++ b/cpu/mcf523x/cpu_init.c @@ -0,0 +1,145 @@ +/* + * + * (C) Copyright 2000-2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * (C) Copyright 2007 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +#include + +/* + * Breath some life into the CPU... + * + * Set up the memory map, + * initialize a bunch of registers, + * initialize the UPM's + */ +void cpu_init_f(void) +{ + volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; + volatile fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS; + volatile wdog_t *wdog = (wdog_t *) MMAP_WDOG; + volatile scm_t *scm = (scm_t *) MMAP_SCM; + + /* watchdog is enabled by default - disable the watchdog */ +#ifndef CONFIG_WATCHDOG + wdog->cr = 0; +#endif + + scm->rambar = (CFG_INIT_RAM_ADDR | SCM_RAMBAR_BDE); + + /* Port configuration */ + gpio->par_cs = 0; + +#if (defined(CFG_CS0_BASE) && defined(CFG_CS0_MASK) && defined(CFG_CS0_CTRL)) + fbcs->csar0 = CFG_CS0_BASE; + fbcs->cscr0 = CFG_CS0_CTRL; + fbcs->csmr0 = CFG_CS0_MASK; +#endif + +#if (defined(CFG_CS1_BASE) && defined(CFG_CS1_MASK) && defined(CFG_CS1_CTRL)) + gpio->par_cs |= GPIO_PAR_CS_CS1; + fbcs->csar1 = CFG_CS1_BASE; + fbcs->cscr1 = CFG_CS1_CTRL; + fbcs->csmr1 = CFG_CS1_MASK; +#endif + +#if (defined(CFG_CS2_BASE) && defined(CFG_CS2_MASK) && defined(CFG_CS2_CTRL)) + gpio->par_cs |= GPIO_PAR_CS_CS2; + fbcs->csar2 = CFG_CS2_BASE; + fbcs->cscr2 = CFG_CS2_CTRL; + fbcs->csmr2 = CFG_CS2_MASK; +#endif + +#if (defined(CFG_CS3_BASE) && defined(CFG_CS3_MASK) && defined(CFG_CS3_CTRL)) + gpio->par_cs |= GPIO_PAR_CS_CS3; + fbcs->csar3 = CFG_CS3_BASE; + fbcs->cscr3 = CFG_CS3_CTRL; + fbcs->csmr3 = CFG_CS3_MASK; +#endif + +#if (defined(CFG_CS4_BASE) && defined(CFG_CS4_MASK) && defined(CFG_CS4_CTRL)) + gpio->par_cs |= GPIO_PAR_CS_CS4; + fbcs->csar4 = CFG_CS4_BASE; + fbcs->cscr4 = CFG_CS4_CTRL; + fbcs->csmr4 = CFG_CS4_MASK; +#endif + +#if (defined(CFG_CS5_BASE) && defined(CFG_CS5_MASK) && defined(CFG_CS5_CTRL)) + gpio->par_cs |= GPIO_PAR_CS_CS5; + fbcs->csar5 = CFG_CS5_BASE; + fbcs->cscr5 = CFG_CS5_CTRL; + fbcs->csmr5 = CFG_CS5_MASK; +#endif + +#if (defined(CFG_CS6_BASE) && defined(CFG_CS6_MASK) && defined(CFG_CS6_CTRL)) + gpio->par_cs |= GPIO_PAR_CS_CS6; + fbcs->csar6 = CFG_CS6_BASE; + fbcs->cscr6 = CFG_CS6_CTRL; + fbcs->csmr6 = CFG_CS6_MASK; +#endif + +#if (defined(CFG_CS7_BASE) && defined(CFG_CS7_MASK) && defined(CFG_CS7_CTRL)) + gpio->par_cs |= GPIO_PAR_CS_CS7; + fbcs->csar7 = CFG_CS7_BASE; + fbcs->cscr7 = CFG_CS7_CTRL; + fbcs->csmr7 = CFG_CS7_MASK; +#endif + +#ifdef CONFIG_FSL_I2C + gpio->par_feci2c &= ~(GPIO_PAR_FECI2C_SCL_MASK | GPIO_PAR_FECI2C_SDA_MASK); + gpio->par_feci2c |= (GPIO_PAR_FECI2C_SCL_I2CSCL | GPIO_PAR_FECI2C_SDA_I2CSDA); +#endif + + icache_enable(); +} + +/* + * initialize higher level parts of CPU like timers + */ +int cpu_init_r(void) +{ + return (0); +} + +void uart_port_conf(void) +{ + volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; + + /* Setup Ports: */ + switch (CFG_UART_PORT) { + case 0: + gpio->par_uart = (GPIO_PAR_UART_U0RXD | GPIO_PAR_UART_U0TXD); + break; + case 1: + gpio->par_uart = + (GPIO_PAR_UART_U1RXD_U1RXD | GPIO_PAR_UART_U1TXD_U1TXD); + break; + case 2: + gpio->par_timer = (GPIO_PAR_UART_U2RXD | GPIO_PAR_UART_U2TXD); + break; + } +} diff --git a/cpu/mcf523x/interrupts.c b/cpu/mcf523x/interrupts.c new file mode 100644 index 000000000..125c53b1b --- /dev/null +++ b/cpu/mcf523x/interrupts.c @@ -0,0 +1,49 @@ +/* + * + * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* CPU specific interrupt routine */ +#include +#include + +int interrupt_init(void) +{ + volatile int0_t *intp = (int0_t *) (CFG_INTR_BASE); + + /* Make sure all interrupts are disabled */ + intp->imrl0 |= 0x1; + + enable_interrupts(); + return 0; +} + +#if defined(CONFIG_MCFTMR) +void dtimer_intr_setup(void) +{ + volatile int0_t *intp = (int0_t *) (CFG_INTR_BASE); + + intp->icr0[CFG_TMRINTR_NO] = CFG_TMRINTR_PRI; + intp->imrl0 &= ~INTC_IPRL_INT0; + intp->imrl0 &= ~CFG_TMRINTR_MASK; +} +#endif diff --git a/cpu/mcf523x/speed.c b/cpu/mcf523x/speed.c new file mode 100644 index 000000000..509109d0e --- /dev/null +++ b/cpu/mcf523x/speed.c @@ -0,0 +1,48 @@ +/* + * + * (C) Copyright 2000-2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +#include + +DECLARE_GLOBAL_DATA_PTR; +/* + * get_clocks() fills in gd->cpu_clock and gd->bus_clk + */ +int get_clocks(void) +{ + volatile pll_t *pll = (volatile pll_t *)(MMAP_PLL); + + pll->syncr = PLL_SYNCR_MFD(1); + + while (!(pll->synsr & PLL_SYNSR_LOCK)); + + gd->bus_clk = CFG_CLK; + gd->cpu_clk = (gd->bus_clk * 2); + return (0); +} diff --git a/cpu/mcf523x/start.S b/cpu/mcf523x/start.S new file mode 100644 index 000000000..2bd603db6 --- /dev/null +++ b/cpu/mcf523x/start.S @@ -0,0 +1,340 @@ +/* + * Copyright (C) 2003 Josef Baumgartner + * Based on code from Bernhard Kuhn + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include "version.h" + +#ifndef CONFIG_IDENT_STRING +#define CONFIG_IDENT_STRING "" +#endif + +#define _START _start +#define _FAULT _fault + +#define SAVE_ALL \ + move.w #0x2700,%sr; /* disable intrs */ \ + subl #60,%sp; /* space for 15 regs */ \ + moveml %d0-%d7/%a0-%a6,%sp@; + +#define RESTORE_ALL \ + moveml %sp@,%d0-%d7/%a0-%a6; \ + addl #60,%sp; /* space for 15 regs */ \ + rte; + +.text +/* + * Vector table. This is used for initial platform startup. + * These vectors are to catch any un-intended traps. + */ +_vectors: + +INITSP: .long 0x00000000 /* Initial SP */ +INITPC: .long _START /* Initial PC */ +vector02: .long _FAULT /* Access Error */ +vector03: .long _FAULT /* Address Error */ +vector04: .long _FAULT /* Illegal Instruction */ +vector05: .long _FAULT /* Reserved */ +vector06: .long _FAULT /* Reserved */ +vector07: .long _FAULT /* Reserved */ +vector08: .long _FAULT /* Privilege Violation */ +vector09: .long _FAULT /* Trace */ +vector0A: .long _FAULT /* Unimplemented A-Line */ +vector0B: .long _FAULT /* Unimplemented F-Line */ +vector0C: .long _FAULT /* Debug Interrupt */ +vector0D: .long _FAULT /* Reserved */ +vector0E: .long _FAULT /* Format Error */ +vector0F: .long _FAULT /* Unitialized Int. */ + +/* Reserved */ +vector10_17: +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT + +vector18: .long _FAULT /* Spurious Interrupt */ +vector19: .long _FAULT /* Autovector Level 1 */ +vector1A: .long _FAULT /* Autovector Level 2 */ +vector1B: .long _FAULT /* Autovector Level 3 */ +vector1C: .long _FAULT /* Autovector Level 4 */ +vector1D: .long _FAULT /* Autovector Level 5 */ +vector1E: .long _FAULT /* Autovector Level 6 */ +vector1F: .long _FAULT /* Autovector Level 7 */ + +/* TRAP #0 - #15 */ +vector20_2F: +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT + +/* Reserved */ +vector30_3F: +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT + +vector64_127: +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT + +vector128_191: +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT + +vector192_255: +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT + + .text + + .globl _start +_start: + nop + nop + move.w #0x2700,%sr /* Mask off Interrupt */ + + /* Set vector base register at the beginning of the Flash */ + move.l #CFG_FLASH_BASE, %d0 + movec %d0, %VBR + + move.l #(CFG_INIT_RAM_ADDR + CFG_INIT_RAM_CTRL), %d0 + movec %d0, %RAMBAR1 + + /* invalidate and disable cache */ + move.l #0x01000000, %d0 /* Invalidate cache cmd */ + movec %d0, %CACR /* Invalidate cache */ + nop + move.l #0, %d0 + movec %d0, %ACR0 + movec %d0, %ACR1 + + /* initialize general use internal ram */ + move.l #0, %d0 + move.l #(CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END-8), %a1 + move.l #(CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END-4), %a2 + move.l %d0, (%a1) + move.l %d0, (%a2) + + /* set stackpointer to end of internal ram to get some stackspace for the + first c-code */ + move.l #(CFG_INIT_RAM_ADDR + CFG_INIT_SP_OFFSET), %sp + clr.l %sp@- + + move.l #__got_start, %a5 /* put relocation table address to a5 */ + + bsr cpu_init_f /* run low-level CPU init code (from flash) */ + bsr board_init_f /* run low-level board init code (from flash) */ + + /* board_init_f() does not return */ + +/*------------------------------------------------------------------------------*/ + +/* + * void relocate_code (addr_sp, gd, addr_moni) + * + * This "function" does not return, instead it continues in RAM + * after relocating the monitor code. + * + * r3 = dest + * r4 = src + * r5 = length in bytes + * r6 = cachelinesize + */ + .globl relocate_code +relocate_code: + link.w %a6,#0 + move.l 8(%a6), %sp /* set new stack pointer */ + + move.l 12(%a6), %d0 /* Save copy of Global Data pointer */ + move.l 16(%a6), %a0 /* Save copy of Destination Address */ + + move.l #CFG_MONITOR_BASE, %a1 + move.l #__init_end, %a2 + move.l %a0, %a3 + + /* copy the code to RAM */ +1: + move.l (%a1)+, (%a3)+ + cmp.l %a1,%a2 + bgt.s 1b + +/* + * We are done. Do not return, instead branch to second part of board + * initialization, now running from RAM. + */ + move.l %a0, %a1 + add.l #(in_ram - CFG_MONITOR_BASE), %a1 + jmp (%a1) + +in_ram: + +clear_bss: + /* + * Now clear BSS segment + */ + move.l %a0, %a1 + add.l #(_sbss - CFG_MONITOR_BASE),%a1 + move.l %a0, %d1 + add.l #(_ebss - CFG_MONITOR_BASE),%d1 +6: + clr.l (%a1)+ + cmp.l %a1,%d1 + bgt.s 6b + + /* + * fix got table in RAM + */ + move.l %a0, %a1 + add.l #(__got_start - CFG_MONITOR_BASE),%a1 + move.l %a1,%a5 /* * fix got pointer register a5 */ + + move.l %a0, %a2 + add.l #(__got_end - CFG_MONITOR_BASE),%a2 + +7: + move.l (%a1),%d1 + sub.l #_start,%d1 + add.l %a0,%d1 + move.l %d1,(%a1)+ + cmp.l %a2, %a1 + bne 7b + + /* calculate relative jump to board_init_r in ram */ + move.l %a0, %a1 + add.l #(board_init_r - CFG_MONITOR_BASE), %a1 + + /* set parameters for board_init_r */ + move.l %a0,-(%sp) /* dest_addr */ + move.l %d0,-(%sp) /* gd */ + jsr (%a1) + +/*------------------------------------------------------------------------------*/ +/* exception code */ + .globl _fault +_fault: + jmp _fault + .globl _exc_handler + +_exc_handler: + SAVE_ALL + movel %sp,%sp@- + bsr exc_handler + addql #4,%sp + RESTORE_ALL + + .globl _int_handler +_int_handler: + SAVE_ALL + movel %sp,%sp@- + bsr int_handler + addql #4,%sp + RESTORE_ALL + +/*------------------------------------------------------------------------------*/ +/* cache functions */ + .globl icache_enable +icache_enable: + move.l #0x01000000, %d0 /* Invalidate cache cmd */ + movec %d0, %CACR /* Invalidate cache */ + nop + move.l #(CFG_SDRAM_BASE + 0xc000), %d0 /* Setup cache mask */ + movec %d0, %ACR0 /* Enable cache */ + move.l #(CFG_FLASH_BASE + 0xc000), %d0 /* Setup cache mask */ + movec %d0, %ACR1 /* Enable cache */ + + move.l #0x80400100, %d0 /* Setup cache mask */ + movec %d0, %CACR /* Enable cache */ + nop + + move.l #(CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END-8), %a1 + moveq #1, %d0 + move.l %d0, (%a1) + rts + + .globl icache_disable +icache_disable: + move.l #0x00000100, %d0 /* Setup cache mask */ + movec %d0, %CACR /* Disable cache */ + clr.l %d0 /* Setup cache mask */ + movec %d0, %ACR0 + movec %d0, %ACR1 + + move.l #(CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END-8), %a1 + moveq #0, %d0 + move.l %d0, (%a1) + rts + + .globl icache_status +icache_status: + move.l #(CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END-8), %a1 + move.l (%a1), %d0 + rts + + .globl icache_invalid +icache_invalid: + move.l #0x80600100, %d0 /* Setup cache mask */ + movec %d0, %CACR /* Enable cache */ + nop + rts + + .globl dcache_enable +dcache_enable: + move.l #(CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END-4), %a1 + moveq #1, %d0 + move.l %d0, (%a1) + rts + + /* No dcache, just a dummy function */ + .globl dcache_disable +dcache_disable: + move.l #(CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END-4), %a1 + moveq #0, %d0 + move.l %d0, (%a1) + rts + + .globl dcache_status +dcache_status: + move.l #(CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END-4), %a1 + move.l (%a1), %d0 + rts + +/*------------------------------------------------------------------------------*/ + + .globl version_string +version_string: + .ascii U_BOOT_VERSION + .ascii " (", __DATE__, " - ", __TIME__, ")" + .ascii CONFIG_IDENT_STRING, "\0" diff --git a/include/asm-m68k/immap.h b/include/asm-m68k/immap.h index d66c1619b..ffb9a377b 100644 --- a/include/asm-m68k/immap.h +++ b/include/asm-m68k/immap.h @@ -26,6 +26,35 @@ #ifndef __IMMAP_H #define __IMMAP_H +#ifdef CONFIG_M5235 +#include +#include + +#define CFG_FEC0_IOBASE (MMAP_FEC) +#define CFG_UART_BASE (MMAP_UART0 + (CFG_UART_PORT * 0x40)) + +/* Timer */ +#ifdef CONFIG_MCFTMR +#define CFG_UDELAY_BASE (MMAP_DTMR0) +#define CFG_TMR_BASE (MMAP_DTMR3) +#define CFG_TMRPND_REG (((volatile int0_t *)(CFG_INTR_BASE))->iprl0) +#define CFG_TMRINTR_NO (INT0_LO_DTMR3) +#define CFG_TMRINTR_MASK (INTC_IPRL_INT22) +#define CFG_TMRINTR_PEND (CFG_TMRINTR_MASK) +#define CFG_TMRINTR_PRI (0x1E) /* Level must include inorder to work */ +#define CFG_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8) +#endif + +#ifdef CONFIG_MCFPIT +#define CFG_UDELAY_BASE (MMAP_PIT0) +#define CFG_PIT_BASE (MMAP_PIT1) +#define CFG_PIT_PRESCALE (6) +#endif + +#define CFG_INTR_BASE (MMAP_INTC0) +#define CFG_NUM_IRQS (128) +#endif /* CONFIG_M5235 */ + #ifdef CONFIG_M5249 #include #include diff --git a/include/asm-m68k/immap_5235.h b/include/asm-m68k/immap_5235.h new file mode 100644 index 000000000..4a034501d --- /dev/null +++ b/include/asm-m68k/immap_5235.h @@ -0,0 +1,378 @@ +/* + * MCF5329 Internal Memory Map + * + * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __IMMAP_5235__ +#define __IMMAP_5235__ + +#define MMAP_SCM (CFG_MBAR + 0x00000000) +#define MMAP_SDRAM (CFG_MBAR + 0x00000040) +#define MMAP_FBCS (CFG_MBAR + 0x00000080) +#define MMAP_DMA0 (CFG_MBAR + 0x00000100) +#define MMAP_DMA1 (CFG_MBAR + 0x00000110) +#define MMAP_DMA2 (CFG_MBAR + 0x00000120) +#define MMAP_DMA3 (CFG_MBAR + 0x00000130) +#define MMAP_UART0 (CFG_MBAR + 0x00000200) +#define MMAP_UART1 (CFG_MBAR + 0x00000240) +#define MMAP_UART2 (CFG_MBAR + 0x00000280) +#define MMAP_I2C (CFG_MBAR + 0x00000300) +#define MMAP_QSPI (CFG_MBAR + 0x00000340) +#define MMAP_DTMR0 (CFG_MBAR + 0x00000400) +#define MMAP_DTMR1 (CFG_MBAR + 0x00000440) +#define MMAP_DTMR2 (CFG_MBAR + 0x00000480) +#define MMAP_DTMR3 (CFG_MBAR + 0x000004C0) +#define MMAP_INTC0 (CFG_MBAR + 0x00000C00) +#define MMAP_INTC1 (CFG_MBAR + 0x00000D00) +#define MMAP_INTCACK (CFG_MBAR + 0x00000F00) +#define MMAP_FEC (CFG_MBAR + 0x00001000) +#define MMAP_FECFIFO (CFG_MBAR + 0x00001400) +#define MMAP_GPIO (CFG_MBAR + 0x00100000) +#define MMAP_CCM (CFG_MBAR + 0x00110000) +#define MMAP_PLL (CFG_MBAR + 0x00120000) +#define MMAP_EPORT (CFG_MBAR + 0x00130000) +#define MMAP_WDOG (CFG_MBAR + 0x00140000) +#define MMAP_PIT0 (CFG_MBAR + 0x00150000) +#define MMAP_PIT1 (CFG_MBAR + 0x00160000) +#define MMAP_PIT2 (CFG_MBAR + 0x00170000) +#define MMAP_PIT3 (CFG_MBAR + 0x00180000) +#define MMAP_MDHA (CFG_MBAR + 0x00190000) +#define MMAP_RNG (CFG_MBAR + 0x001A0000) +#define MMAP_SKHA (CFG_MBAR + 0x001B0000) +#define MMAP_CAN1 (CFG_MBAR + 0x001C0000) +#define MMAP_ETPU (CFG_MBAR + 0x001D0000) +#define MMAP_CAN2 (CFG_MBAR + 0x001F0000) + +/* System Control Module register */ +typedef struct scm_ctrl { + u32 ipsbar; /* 0x00 - MBAR */ + u32 res1; /* 0x04 */ + u32 rambar; /* 0x08 - RAMBAR */ + u32 res2; /* 0x0C */ + u8 crsr; /* 0x10 Core Reset Status Register */ + u8 cwcr; /* 0x11 Core Watchdog Control Register */ + u8 lpicr; /* 0x12 Low-Power Interrupt Control Register */ + u8 cwsr; /* 0x13 Core Watchdog Service Register */ + u32 dmareqc; /* 0x14 */ + u32 res3; /* 0x18 */ + u32 mpark; /* 0x1C */ + u8 mpr; /* 0x20 */ + u8 res4[3]; /* 0x21 - 0x23 */ + u8 pacr0; /* 0x24 */ + u8 pacr1; /* 0x25 */ + u8 pacr2; /* 0x26 */ + u8 pacr3; /* 0x27 */ + u8 pacr4; /* 0x28 */ + u32 res5; /* 0x29 */ + u8 pacr5; /* 0x2a */ + u8 pacr6; /* 0x2b */ + u8 pacr7; /* 0x2c */ + u32 res6; /* 0x2d */ + u8 pacr8; /* 0x2e */ + u32 res7; /* 0x2f */ + u8 gpacr; /* 0x30 */ + u8 res8[3]; /* 0x31 - 0x33 */ +} scm_t; + +/* SDRAM controller registers */ +typedef struct sdram_ctrl { + u16 dcr; /* 0x00 Control register */ + u16 res1[3]; /* 0x02 - 0x07 */ + u32 dacr0; /* 0x08 address and control register 0 */ + u32 dmr0; /* 0x0C mask register block 0 */ + u32 dacr1; /* 0x10 address and control register 1 */ + u32 dmr1; /* 0x14 mask register block 1 */ +} sdram_t; + +/* Flexbus module Chip select registers */ +typedef struct fbcs_ctrl { + u16 csar0; /* 0x00 Chip-Select Address Register 0 */ + u16 res0; + u32 csmr0; /* 0x04 Chip-Select Mask Register 0 */ + u16 res1; /* 0x08 */ + u16 cscr0; /* 0x0A Chip-Select Control Register 0 */ + + u16 csar1; /* 0x0C Chip-Select Address Register 1 */ + u16 res2; + u32 csmr1; /* 0x10 Chip-Select Mask Register 1 */ + u16 res3; /* 0x14 */ + u16 cscr1; /* 0x16 Chip-Select Control Register 1 */ + + u16 csar2; /* 0x18 Chip-Select Address Register 2 */ + u16 res4; + u32 csmr2; /* 0x1C Chip-Select Mask Register 2 */ + u16 res5; /* 0x20 */ + u16 cscr2; /* 0x22 Chip-Select Control Register 2 */ + + u16 csar3; /* 0x24 Chip-Select Address Register 3 */ + u16 res6; + u32 csmr3; /* 0x28 Chip-Select Mask Register 3 */ + u16 res7; /* 0x2C */ + u16 cscr3; /* 0x2E Chip-Select Control Register 3 */ + + u16 csar4; /* 0x30 Chip-Select Address Register 4 */ + u16 res8; + u32 csmr4; /* 0x34 Chip-Select Mask Register 4 */ + u16 res9; /* 0x38 */ + u16 cscr4; /* 0x3A Chip-Select Control Register 4 */ + + u16 csar5; /* 0x3C Chip-Select Address Register 5 */ + u16 res10; + u32 csmr5; /* 0x40 Chip-Select Mask Register 5 */ + u16 res11; /* 0x44 */ + u16 cscr5; /* 0x46 Chip-Select Control Register 5 */ + + u16 csar6; /* 0x48 Chip-Select Address Register 5 */ + u16 res12; + u32 csmr6; /* 0x4C Chip-Select Mask Register 5 */ + u16 res13; /* 0x50 */ + u16 cscr6; /* 0x52 Chip-Select Control Register 5 */ + + u16 csar7; /* 0x54 Chip-Select Address Register 5 */ + u16 res14; + u32 csmr7; /* 0x58 Chip-Select Mask Register 5 */ + u16 res15; /* 0x5C */ + u16 cscr7; /* 0x5E Chip-Select Control Register 5 */ +} fbcs_t; + +/* QSPI module registers */ +typedef struct qspi_ctrl { + u16 qmr; /* Mode register */ + u16 res1; + u16 qdlyr; /* Delay register */ + u16 res2; + u16 qwr; /* Wrap register */ + u16 res3; + u16 qir; /* Interrupt register */ + u16 res4; + u16 qar; /* Address register */ + u16 res5; + u16 qdr; /* Data register */ + u16 res6; +} qspi_t; + +/* Interrupt module registers */ +typedef struct int0_ctrl { + /* Interrupt Controller 0 */ + u32 iprh0; /* 0x00 Pending Register High */ + u32 iprl0; /* 0x04 Pending Register Low */ + u32 imrh0; /* 0x08 Mask Register High */ + u32 imrl0; /* 0x0C Mask Register Low */ + u32 frch0; /* 0x10 Force Register High */ + u32 frcl0; /* 0x14 Force Register Low */ + u8 irlr; /* 0x18 */ + u8 iacklpr; /* 0x19 */ + u16 res1[19]; /* 0x1a - 0x3c */ + u8 icr0[64]; /* 0x40 - 0x7F Control registers */ + u32 res3[24]; /* 0x80 - 0xDF */ + u8 swiack0; /* 0xE0 Software Interrupt Acknowledge */ + u8 res4[3]; /* 0xE1 - 0xE3 */ + u8 Lniack0_1; /* 0xE4 Level n interrupt acknowledge resister */ + u8 res5[3]; /* 0xE5 - 0xE7 */ + u8 Lniack0_2; /* 0xE8 Level n interrupt acknowledge resister */ + u8 res6[3]; /* 0xE9 - 0xEB */ + u8 Lniack0_3; /* 0xEC Level n interrupt acknowledge resister */ + u8 res7[3]; /* 0xED - 0xEF */ + u8 Lniack0_4; /* 0xF0 Level n interrupt acknowledge resister */ + u8 res8[3]; /* 0xF1 - 0xF3 */ + u8 Lniack0_5; /* 0xF4 Level n interrupt acknowledge resister */ + u8 res9[3]; /* 0xF5 - 0xF7 */ + u8 Lniack0_6; /* 0xF8 Level n interrupt acknowledge resister */ + u8 resa[3]; /* 0xF9 - 0xFB */ + u8 Lniack0_7; /* 0xFC Level n interrupt acknowledge resister */ + u8 resb[3]; /* 0xFD - 0xFF */ +} int0_t; + +typedef struct int1_ctrl { + /* Interrupt Controller 1 */ + u32 iprh1; /* 0x00 Pending Register High */ + u32 iprl1; /* 0x04 Pending Register Low */ + u32 imrh1; /* 0x08 Mask Register High */ + u32 imrl1; /* 0x0C Mask Register Low */ + u32 frch1; /* 0x10 Force Register High */ + u32 frcl1; /* 0x14 Force Register Low */ + u8 irlr; /* 0x18 */ + u8 iacklpr; /* 0x19 */ + u16 res1[19]; /* 0x1a - 0x3c */ + u8 icr1[64]; /* 0x40 - 0x7F */ + u32 res4[24]; /* 0x80 - 0xDF */ + u8 swiack1; /* 0xE0 Software Interrupt Acknowledge */ + u8 res5[3]; /* 0xE1 - 0xE3 */ + u8 Lniack1_1; /* 0xE4 Level n interrupt acknowledge resister */ + u8 res6[3]; /* 0xE5 - 0xE7 */ + u8 Lniack1_2; /* 0xE8 Level n interrupt acknowledge resister */ + u8 res7[3]; /* 0xE9 - 0xEB */ + u8 Lniack1_3; /* 0xEC Level n interrupt acknowledge resister */ + u8 res8[3]; /* 0xED - 0xEF */ + u8 Lniack1_4; /* 0xF0 Level n interrupt acknowledge resister */ + u8 res9[3]; /* 0xF1 - 0xF3 */ + u8 Lniack1_5; /* 0xF4 Level n interrupt acknowledge resister */ + u8 resa[3]; /* 0xF5 - 0xF7 */ + u8 Lniack1_6; /* 0xF8 Level n interrupt acknowledge resister */ + u8 resb[3]; /* 0xF9 - 0xFB */ + u8 Lniack1_7; /* 0xFC Level n interrupt acknowledge resister */ + u8 resc[3]; /* 0xFD - 0xFF */ +} int1_t; + +typedef struct intgack_ctrl1 { + /* Global IACK Registers */ + u8 swiack; /* 0xE0 Global Software Interrupt Acknowledge */ + u8 Lniack[7]; /* 0xE1 - 0xE7 Global Level 0 Interrupt Acknowledge */ +} intgack_t; + +/* GPIO port registers */ +typedef struct gpio_ctrl { + /* Port Output Data Registers */ + u8 podr_addr; /* 0x00 */ + u8 podr_datah; /* 0x01 */ + u8 podr_datal; /* 0x02 */ + u8 podr_busctl; /* 0x03 */ + u8 podr_bs; /* 0x04 */ + u8 podr_cs; /* 0x05 */ + u8 podr_sdram; /* 0x06 */ + u8 podr_feci2c; /* 0x07 */ + u8 podr_uarth; /* 0x08 */ + u8 podr_uartl; /* 0x09 */ + u8 podr_qspi; /* 0x0A */ + u8 podr_timer; /* 0x0B */ + u8 podr_etpu; /* 0x0C */ + u8 res1[3]; /* 0x0D - 0x0F */ + + /* Port Data Direction Registers */ + u8 pddr_addr; /* 0x10 */ + u8 pddr_datah; /* 0x11 */ + u8 pddr_datal; /* 0x12 */ + u8 pddr_busctl; /* 0x13 */ + u8 pddr_bs; /* 0x14 */ + u8 pddr_cs; /* 0x15 */ + u8 pddr_sdram; /* 0x16 */ + u8 pddr_feci2c; /* 0x17 */ + u8 pddr_uarth; /* 0x18 */ + u8 pddr_uartl; /* 0x19 */ + u8 pddr_qspi; /* 0x1A */ + u8 pddr_timer; /* 0x1B */ + u8 pddr_etpu; /* 0x1C */ + u8 res2[3]; /* 0x1D - 0x1F */ + + /* Port Data Direction Registers */ + u8 ppdsdr_addr; /* 0x20 */ + u8 ppdsdr_datah; /* 0x21 */ + u8 ppdsdr_datal; /* 0x22 */ + u8 ppdsdr_busctl; /* 0x23 */ + u8 ppdsdr_bs; /* 0x24 */ + u8 ppdsdr_cs; /* 0x25 */ + u8 ppdsdr_sdram; /* 0x26 */ + u8 ppdsdr_feci2c; /* 0x27 */ + u8 ppdsdr_uarth; /* 0x28 */ + u8 ppdsdr_uartl; /* 0x29 */ + u8 ppdsdr_qspi; /* 0x2A */ + u8 ppdsdr_timer; /* 0x2B */ + u8 ppdsdr_etpu; /* 0x2C */ + u8 res3[3]; /* 0x2D - 0x2F */ + + /* Port Clear Output Data Registers */ + u8 pclrr_addr; /* 0x30 */ + u8 pclrr_datah; /* 0x31 */ + u8 pclrr_datal; /* 0x32 */ + u8 pclrr_busctl; /* 0x33 */ + u8 pclrr_bs; /* 0x34 */ + u8 pclrr_cs; /* 0x35 */ + u8 pclrr_sdram; /* 0x36 */ + u8 pclrr_feci2c; /* 0x37 */ + u8 pclrr_uarth; /* 0x38 */ + u8 pclrr_uartl; /* 0x39 */ + u8 pclrr_qspi; /* 0x3A */ + u8 pclrr_timer; /* 0x3B */ + u8 pclrr_etpu; /* 0x3C */ + u8 res4[3]; /* 0x3D - 0x3F */ + + /* Pin Assignment Registers */ + u8 par_ad; /* 0x40 */ + u8 res5; /* 0x41 */ + u16 par_busctl; /* 0x42 */ + u8 par_bs; /* 0x44 */ + u8 par_cs; /* 0x45 */ + u8 par_sdram; /* 0x46 */ + u8 par_feci2c; /* 0x47 */ + u16 par_uart; /* 0x48 */ + u8 par_qspi; /* 0x4A */ + u8 res6; /* 0x4B */ + u16 par_timer; /* 0x4C */ + u8 par_etpu; /* 0x4E */ + u8 res7; /* 0x4F */ + + /* Drive Strength Control Registers */ + u8 dscr_eim; /* 0x50 */ + u8 dscr_etpu; /* 0x51 */ + u8 dscr_feci2c; /* 0x52 */ + u8 dscr_uart; /* 0x53 */ + u8 dscr_qspi; /* 0x54 */ + u8 dscr_timer; /* 0x55 */ + u16 res8; /* 0x56 */ +} gpio_t; + +/*Chip configuration module registers */ +typedef struct ccm_ctrl { + u8 rcr; /* 0x01 */ + u8 rsr; /* 0x02 */ + u16 res1; /* 0x03 */ + u16 ccr; /* 0x04 Chip configuration register */ + u16 lpcr; /* 0x06 Low-power Control register */ + u16 rcon; /* 0x08 Rreset configuration register */ + u16 cir; /* 0x0a Chip identification register */ +} ccm_t; + +/* Clock Module registers */ +typedef struct pll_ctrl { + u32 syncr; /* 0x00 synthesizer control register */ + u32 synsr; /* 0x04 synthesizer status register */ +} pll_t; + +/* Watchdog registers */ +typedef struct wdog_ctrl { + u16 cr; /* 0x00 Control register */ + u16 mr; /* 0x02 Modulus register */ + u16 cntr; /* 0x04 Count register */ + u16 sr; /* 0x06 Service register */ +} wdog_t; + +/* FlexCan module registers */ +typedef struct can_ctrl { + u32 mcr; /* 0x00 Module Configuration register */ + u32 ctrl; /* 0x04 Control register */ + u32 timer; /* 0x08 Free Running Timer */ + u32 res1; /* 0x0C */ + u32 rxgmask; /* 0x10 Rx Global Mask */ + u32 rx14mask; /* 0x14 RxBuffer 14 Mask */ + u32 rx15mask; /* 0x18 RxBuffer 15 Mask */ + u32 errcnt; /* 0x1C Error Counter Register */ + u32 errstat; /* 0x20 Error and status Register */ + u32 res2; /* 0x24 */ + u32 imask; /* 0x28 Interrupt Mask Register */ + u32 res3; /* 0x2C */ + u32 iflag; /* 0x30 Interrupt Flag Register */ + u32 res4[19]; /* 0x34 - 0x7F */ + u32 MB0_15[2048]; /* 0x80 Message Buffer 0-15 */ +} can_t; + +#endif /* __IMMAP_5235__ */ diff --git a/include/asm-m68k/m5235.h b/include/asm-m68k/m5235.h new file mode 100644 index 000000000..b98b452ca --- /dev/null +++ b/include/asm-m68k/m5235.h @@ -0,0 +1,905 @@ +/* + * mcf5329.h -- Definitions for Freescale Coldfire 5329 + * + * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef mcf5235_h +#define mcf5235_h +/****************************************************************************/ + +/********************************************************************* +* System Control Module (SCM) +*********************************************************************/ + +/* Bit definition and macros for SCM_IPSBAR */ +#define SCM_IPSBAR_BA(x) (((x)&0x03)<<30) +#define SCM_IPSBAR_V (0x00000001) + +/* Bit definition and macros for SCM_RAMBAR */ +#define SCM_RAMBAR_BA(x) (((x)&0xFFFF)<<16) +#define SCM_RAMBAR_BDE (0x00000200) + +/* Bit definition and macros for SCM_CRSR */ +#define SCM_CRSR_EXT (0x80) + +/* Bit definitions and macros for SCM_CWCR */ +#define SCM_CWCR_CWE (0x80) +#define SCM_CWCR_CWRI (0x40) +#define SCM_CWCR_CWT(x) (((x)&0x07)<<3) +#define SCM_CWCR_CWTA (0x04) +#define SCM_CWCR_CWTAVAL (0x02) +#define SCM_CWCR_CWTIC (0x01) + +/* Bit definitions and macros for SCM_LPICR */ +#define SCM_LPICR_ENBSTOP (0x80) +#define SCM_LPICR_XLPM_IPL(x) (((x)&0x07)<<4) +#define SCM_LPICR_XLPM_IPL_ANY (0x00) +#define SCM_LPICR_XLPM_IPL_L2_7 (0x10) +#define SCM_LPICR_XLPM_IPL_L3_7 (0x20) +#define SCM_LPICR_XLPM_IPL_L4_7 (0x30) +#define SCM_LPICR_XLPM_IPL_L5_7 (0x40) +#define SCM_LPICR_XLPM_IPL_L6_7 (0x50) +#define SCM_LPICR_XLPM_IPL_L7 (0x70) + +/* Bit definitions and macros for SCM_DMAREQC */ +#define SCM_DMAREQC_EXT(x) (((x)&0x0F)<<16) +#define SCM_DMAREQC_EXT_ETPU (0x00080000) +#define SCM_DMAREQC_EXT_EXTDREQ2 (0x00040000) +#define SCM_DMAREQC_EXT_EXTDREQ1 (0x00020000) +#define SCM_DMAREQC_EXT_EXTDREQ0 (0x00010000) +#define SCM_DMAREQC_DMAC3(x) (((x)&0x0F)<<12) +#define SCM_DMAREQC_DMAC2(x) (((x)&0x0F)<<8) +#define SCM_DMAREQC_DMAC1(x) (((x)&0x0F)<<4) +#define SCM_DMAREQC_DMAC0(x) (((x)&0x0F)) +#define SCM_DMAREQC_DMACn_DTMR0 (0x04) +#define SCM_DMAREQC_DMACn_DTMR1 (0x05) +#define SCM_DMAREQC_DMACn_DTMR2 (0x06) +#define SCM_DMAREQC_DMACn_DTMR3 (0x07) +#define SCM_DMAREQC_DMACn_UART0RX (0x08) +#define SCM_DMAREQC_DMACn_UART1RX (0x09) +#define SCM_DMAREQC_DMACn_UART2RX (0x0A) +#define SCM_DMAREQC_DMACn_UART0TX (0x0C) +#define SCM_DMAREQC_DMACn_UART1TX (0x0D) +#define SCM_DMAREQC_DMACn_UART3TX (0x0E) + +/* Bit definitions and macros for SCM_MPARK */ +#define SCM_MPARK_M2_P_EN (0x02000000) +#define SCM_MPARK_M3_PRTY_MSK (0x00C00000) +#define SCM_MPARK_M3_PRTY_4TH (0x00000000) +#define SCM_MPARK_M3_PRTY_3RD (0x00400000) +#define SCM_MPARK_M3_PRTY_2ND (0x00800000) +#define SCM_MPARK_M3_PRTY_1ST (0x00C00000) +#define SCM_MPARK_M2_PRTY_MSK (0x00300000) +#define SCM_MPARK_M2_PRTY_4TH (0x00000000) +#define SCM_MPARK_M2_PRTY_3RD (0x00100000) +#define SCM_MPARK_M2_PRTY_2ND (0x00200000) +#define SCM_MPARK_M2_PRTY_1ST (0x00300000) +#define SCM_MPARK_M0_PRTY_MSK (0x000C0000) +#define SCM_MPARK_M0_PRTY_4TH (0x00000000) +#define SCM_MPARK_M0_PRTY_3RD (0x00040000) +#define SCM_MPARK_M0_PRTY_2ND (0x00080000) +#define SCM_MPARK_M0_PRTY_1ST (0x000C0000) +#define SCM_MPARK_FIXED (0x00004000) +#define SCM_MPARK_TIMEOUT (0x00002000) +#define SCM_MPARK_PRKLAST (0x00001000) +#define SCM_MPARK_LCKOUT_TIME(x) (((x)&0x0F)<<8) + +/* Bit definitions and macros for SCM_MPR */ +#define SCM_MPR_MPR3 (0x08) +#define SCM_MPR_MPR2 (0x04) +#define SCM_MPR_MPR1 (0x02) +#define SCM_MPR_MPR0 (0x01) + +/* Bit definitions and macros for SCM_PACRn */ +#define SCM_PACRn_LOCK1 (0x80) +#define SCM_PACRn_ACCESSCTRL1(x) (((x)&0x07)<<4) +#define SCM_PACRn_LOCK0 (0x08) +#define SCM_PACRn_ACCESSCTRL0(x) (((x)&0x07)) + +/* Bit definitions and macros for SCM_GPACR */ +#define SCM_PACRn_LOCK (0x80) +#define SCM_PACRn_ACCESSCTRL0(x) (((x)&0x07)) + +/********************************************************************* +* SDRAM Controller (SDRAMC) +*********************************************************************/ +/* Bit definitions and macros for SDRAMC_DCR */ +#define SDRAMC_DCR_NAM (0x2000) +#define SDRAMC_DCR_COC (0x1000) +#define SDRAMC_DCR_IS (0x0800) +#define SDRAMC_DCR_RTIM_MASK (0x0C00) +#define SDRAMC_DCR_RTIM_3CLKS (0x0000) +#define SDRAMC_DCR_RTIM_6CLKS (0x0200) +#define SDRAMC_DCR_RTIM_9CLKS (0x0400) +#define SDRAMC_DCR_RC(x) (((x)&0xFF)<<8) + +/* Bit definitions and macros for SDRAMC_DARCn */ +#define SDRAMC_DARCn_BA(x) (((x)&0xFFFC)<<18) +#define SDRAMC_DARCn_RE (0x00008000) +#define SDRAMC_DARCn_CASL_MASK (0x00003000) +#define SDRAMC_DARCn_CASL_C0 (0x00000000) +#define SDRAMC_DARCn_CASL_C1 (0x00001000) +#define SDRAMC_DARCn_CASL_C2 (0x00002000) +#define SDRAMC_DARCn_CASL_C3 (0x00003000) +#define SDRAMC_DARCn_CBM_MASK (0x00000700) +#define SDRAMC_DARCn_CBM_CMD17 (0x00000000) +#define SDRAMC_DARCn_CBM_CMD18 (0x00000100) +#define SDRAMC_DARCn_CBM_CMD19 (0x00000200) +#define SDRAMC_DARCn_CBM_CMD20 (0x00000300) +#define SDRAMC_DARCn_CBM_CMD21 (0x00000400) +#define SDRAMC_DARCn_CBM_CMD22 (0x00000500) +#define SDRAMC_DARCn_CBM_CMD23 (0x00000600) +#define SDRAMC_DARCn_CBM_CMD24 (0x00000700) +#define SDRAMC_DARCn_IMRS (0x00000040) +#define SDRAMC_DARCn_PS_MASK (0x00000030) +#define SDRAMC_DARCn_PS_32 (0x00000000) +#define SDRAMC_DARCn_PS_16 (0x00000010) +#define SDRAMC_DARCn_PS_8 (0x00000020) +#define SDRAMC_DARCn_IP (0x00000008) + +/* Bit definitions and macros for SDRAMC_DMRn */ +#define SDRAMC_DMRn_BAM(x) (((x)&0x3FFF)<<18) +#define SDRAMC_DMRn_WP (0x00000100) +#define SDRAMC_DMRn_V (0x00000001) + +/********************************************************************* +* FlexBus Chip Selects (FBCS) +*********************************************************************/ +/* Bit definitions and macros for FBCS_CSMR */ +#define FBCS_CSMR_BAM(x) (((x)&0xFFFF)<<16) +#define FBCS_CSMR_BAM_4G (0xFFFF0000) +#define FBCS_CSMR_BAM_2G (0x7FFF0000) +#define FBCS_CSMR_BAM_1G (0x3FFF0000) +#define FBCS_CSMR_BAM_1024M (0x3FFF0000) +#define FBCS_CSMR_BAM_512M (0x1FFF0000) +#define FBCS_CSMR_BAM_256M (0x0FFF0000) +#define FBCS_CSMR_BAM_128M (0x07FF0000) +#define FBCS_CSMR_BAM_64M (0x03FF0000) +#define FBCS_CSMR_BAM_32M (0x01FF0000) +#define FBCS_CSMR_BAM_16M (0x00FF0000) +#define FBCS_CSMR_BAM_8M (0x007F0000) +#define FBCS_CSMR_BAM_4M (0x003F0000) +#define FBCS_CSMR_BAM_2M (0x001F0000) +#define FBCS_CSMR_BAM_1M (0x000F0000) +#define FBCS_CSMR_BAM_1024K (0x000F0000) +#define FBCS_CSMR_BAM_512K (0x00070000) +#define FBCS_CSMR_BAM_256K (0x00030000) +#define FBCS_CSMR_BAM_128K (0x00010000) +#define FBCS_CSMR_BAM_64K (0x00000000) +#define FBCS_CSMR_WP (0x00000100) +#define FBCS_CSMR_V (0x00000001) + +/* Bit definitions and macros for FBCS_CSCR */ +#define FBCS_CSCR_SRWS(x) (((x)&0x03)<<14) +#define FBCS_CSCR_IWS(x) (((x)&0x0F)<<10) +#define FBCS_CSCR_AA (0x0100) +#define FBCS_CSCR_PS_MASK (0x00C0) +#define FBCS_CSCR_PS_32 (0x0000) +#define FBCS_CSCR_PS_16 (0x0080) +#define FBCS_CSCR_PS_8 (0x0040) +#define FBCS_CSCR_BEM (0x0020) +#define FBCS_CSCR_BSTR (0x0010) +#define FBCS_CSCR_BSTW (0x0008) +#define FBCS_CSCR_SWWS(x) ((x)&0x07) + +/********************************************************************* +* Queued Serial Peripheral Interface (QSPI) +*********************************************************************/ +/* Bit definitions and macros for QSPI_QMR */ +#define QSPI_QMR_MSTR (0x8000) +#define QSPI_QMR_DOHIE (0x4000) +#define QSPI_QMR_BITS(x) (((x)&0x000F)<<10) +#define QSPI_QMR_CPOL (0x0200) +#define QSPI_QMR_CPHA (0x0100) +#define QSPI_QMR_BAUD(x) ((x)&0x00FF) + +/* Bit definitions and macros for QSPI_QDLYR */ +#define QSPI_QDLYR_SPE (0x8000) +#define QSPI_QDLYR_QCD(x) (((x)&0x007F)<<8) +#define QSPI_QDLYR_DTL(x) ((x)&0x00FF) + +/* Bit definitions and macros for QSPI_QWR */ +#define QSPI_QWR_HALT (0x8000) +#define QSPI_QWR_WREN (0x4000) +#define QSPI_QWR_WRTO (0x2000) +#define QSPI_QWR_CSIV (0x1000) +#define QSPI_QWR_ENDQP(x) (((x)&0x000F)<<8) +#define QSPI_QWR_NEWQP(x) ((x)&0x000F) + +/* Bit definitions and macros for QSPI_QIR */ +#define QSPI_QIR_WCEFB (0x8000) +#define QSPI_QIR_ABRTB (0x4000) +#define QSPI_QIR_ABRTL (0x1000) +#define QSPI_QIR_WCEFE (0x0800) +#define QSPI_QIR_ABRTE (0x0400) +#define QSPI_QIR_SPIFE (0x0100) +#define QSPI_QIR_WCEF (0x0008) +#define QSPI_QIR_ABRT (0x0004) +#define QSPI_QIR_SPIF (0x0001) + +/* Bit definitions and macros for QSPI_QAR */ +#define QSPI_QAR_ADDR(x) ((x)&0x003F) + +/* Bit definitions and macros for QSPI_QDR */ +#define QSPI_QDR_CONT (0x8000) +#define QSPI_QDR_BITSE (0x4000) +#define QSPI_QDR_DT (0x2000) +#define QSPI_QDR_DSCK (0x1000) +#define QSPI_QDR_QSPI_CS3 (0x0800) +#define QSPI_QDR_QSPI_CS2 (0x0400) +#define QSPI_QDR_QSPI_CS1 (0x0200) +#define QSPI_QDR_QSPI_CS0 (0x0100) + +/********************************************************************* +* Interrupt Controller (INTC) +*********************************************************************/ +#define INT0_LO_RSVD0 (0) +#define INT0_LO_EPORT1 (1) +#define INT0_LO_EPORT2 (2) +#define INT0_LO_EPORT3 (3) +#define INT0_LO_EPORT4 (4) +#define INT0_LO_EPORT5 (5) +#define INT0_LO_EPORT6 (6) +#define INT0_LO_EPORT7 (7) +#define INT0_LO_SCM (8) +#define INT0_LO_DMA0 (9) +#define INT0_LO_DMA1 (10) +#define INT0_LO_DMA2 (11) +#define INT0_LO_DMA3 (12) +#define INT0_LO_UART0 (13) +#define INT0_LO_UART1 (14) +#define INT0_LO_UART2 (15) +#define INT0_LO_RSVD1 (16) +#define INT0_LO_I2C (17) +#define INT0_LO_QSPI (18) +#define INT0_LO_DTMR0 (19) +#define INT0_LO_DTMR1 (20) +#define INT0_LO_DTMR2 (21) +#define INT0_LO_DTMR3 (22) +#define INT0_LO_FEC_TXF (23) +#define INT0_LO_FEC_TXB (24) +#define INT0_LO_FEC_UN (25) +#define INT0_LO_FEC_RL (26) +#define INT0_LO_FEC_RXF (27) +#define INT0_LO_FEC_RXB (28) +#define INT0_LO_FEC_MII (29) +#define INT0_LO_FEC_LC (30) +#define INT0_LO_FEC_HBERR (31) +#define INT0_HI_FEC_GRA (32) +#define INT0_HI_FEC_EBERR (33) +#define INT0_HI_FEC_BABT (34) +#define INT0_HI_FEC_BABR (35) +#define INT0_HI_PIT0 (36) +#define INT0_HI_PIT1 (37) +#define INT0_HI_PIT2 (38) +#define INT0_HI_PIT3 (39) +#define INT0_HI_RNG (40) +#define INT0_HI_SKHA (41) +#define INT0_HI_MDHA (42) +#define INT0_HI_CAN1_BUF0I (43) +#define INT0_HI_CAN1_BUF1I (44) +#define INT0_HI_CAN1_BUF2I (45) +#define INT0_HI_CAN1_BUF3I (46) +#define INT0_HI_CAN1_BUF4I (47) +#define INT0_HI_CAN1_BUF5I (48) +#define INT0_HI_CAN1_BUF6I (49) +#define INT0_HI_CAN1_BUF7I (50) +#define INT0_HI_CAN1_BUF8I (51) +#define INT0_HI_CAN1_BUF9I (52) +#define INT0_HI_CAN1_BUF10I (53) +#define INT0_HI_CAN1_BUF11I (54) +#define INT0_HI_CAN1_BUF12I (55) +#define INT0_HI_CAN1_BUF13I (56) +#define INT0_HI_CAN1_BUF14I (57) +#define INT0_HI_CAN1_BUF15I (58) +#define INT0_HI_CAN1_ERRINT (59) +#define INT0_HI_CAN1_BOFFINT (60) +/* 60-63 Reserved */ + +/* 0 - 7 Reserved */ +#define INT1_LO_CAN1_BUF0I (8) +#define INT1_LO_CAN1_BUF1I (9) +#define INT1_LO_CAN1_BUF2I (10) +#define INT1_LO_CAN1_BUF3I (11) +#define INT1_LO_CAN1_BUF4I (12) +#define INT1_LO_CAN1_BUF5I (13) +#define INT1_LO_CAN1_BUF6I (14) +#define INT1_LO_CAN1_BUF7I (15) +#define INT1_LO_CAN1_BUF8I (16) +#define INT1_LO_CAN1_BUF9I (17) +#define INT1_LO_CAN1_BUF10I (18) +#define INT1_LO_CAN1_BUF11I (19) +#define INT1_LO_CAN1_BUF12I (20) +#define INT1_LO_CAN1_BUF13I (21) +#define INT1_LO_CAN1_BUF14I (22) +#define INT1_LO_CAN1_BUF15I (23) +#define INT1_LO_CAN1_ERRINT (24) +#define INT1_LO_CAN1_BOFFINT (25) +/* 26 Reserved */ +#define INT1_LO_ETPU_TC0F (27) +#define INT1_LO_ETPU_TC1F (28) +#define INT1_LO_ETPU_TC2F (29) +#define INT1_LO_ETPU_TC3F (30) +#define INT1_LO_ETPU_TC4F (31) +#define INT1_HI_ETPU_TC5F (32) +#define INT1_HI_ETPU_TC6F (33) +#define INT1_HI_ETPU_TC7F (34) +#define INT1_HI_ETPU_TC8F (35) +#define INT1_HI_ETPU_TC9F (36) +#define INT1_HI_ETPU_TC10F (37) +#define INT1_HI_ETPU_TC11F (38) +#define INT1_HI_ETPU_TC12F (39) +#define INT1_HI_ETPU_TC13F (40) +#define INT1_HI_ETPU_TC14F (41) +#define INT1_HI_ETPU_TC15F (42) +#define INT1_HI_ETPU_TC16F (43) +#define INT1_HI_ETPU_TC17F (44) +#define INT1_HI_ETPU_TC18F (45) +#define INT1_HI_ETPU_TC19F (46) +#define INT1_HI_ETPU_TC20F (47) +#define INT1_HI_ETPU_TC21F (48) +#define INT1_HI_ETPU_TC22F (49) +#define INT1_HI_ETPU_TC23F (50) +#define INT1_HI_ETPU_TC24F (51) +#define INT1_HI_ETPU_TC25F (52) +#define INT1_HI_ETPU_TC26F (53) +#define INT1_HI_ETPU_TC27F (54) +#define INT1_HI_ETPU_TC28F (55) +#define INT1_HI_ETPU_TC29F (56) +#define INT1_HI_ETPU_TC30F (57) +#define INT1_HI_ETPU_TC31F (58) +#define INT1_HI_ETPU_TGIF (59) + +/* Bit definitions and macros for INTC_IPRH */ +#define INTC_IPRH_INT63 (0x80000000) +#define INTC_IPRH_INT62 (0x40000000) +#define INTC_IPRH_INT61 (0x20000000) +#define INTC_IPRH_INT60 (0x10000000) +#define INTC_IPRH_INT59 (0x08000000) +#define INTC_IPRH_INT58 (0x04000000) +#define INTC_IPRH_INT57 (0x02000000) +#define INTC_IPRH_INT56 (0x01000000) +#define INTC_IPRH_INT55 (0x00800000) +#define INTC_IPRH_INT54 (0x00400000) +#define INTC_IPRH_INT53 (0x00200000) +#define INTC_IPRH_INT52 (0x00100000) +#define INTC_IPRH_INT51 (0x00080000) +#define INTC_IPRH_INT50 (0x00040000) +#define INTC_IPRH_INT49 (0x00020000) +#define INTC_IPRH_INT48 (0x00010000) +#define INTC_IPRH_INT47 (0x00008000) +#define INTC_IPRH_INT46 (0x00004000) +#define INTC_IPRH_INT45 (0x00002000) +#define INTC_IPRH_INT44 (0x00001000) +#define INTC_IPRH_INT43 (0x00000800) +#define INTC_IPRH_INT42 (0x00000400) +#define INTC_IPRH_INT41 (0x00000200) +#define INTC_IPRH_INT40 (0x00000100) +#define INTC_IPRH_INT39 (0x00000080) +#define INTC_IPRH_INT38 (0x00000040) +#define INTC_IPRH_INT37 (0x00000020) +#define INTC_IPRH_INT36 (0x00000010) +#define INTC_IPRH_INT35 (0x00000008) +#define INTC_IPRH_INT34 (0x00000004) +#define INTC_IPRH_INT33 (0x00000002) +#define INTC_IPRH_INT32 (0x00000001) + +/* Bit definitions and macros for INTC_IPRL */ +#define INTC_IPRL_INT31 (0x80000000) +#define INTC_IPRL_INT30 (0x40000000) +#define INTC_IPRL_INT29 (0x20000000) +#define INTC_IPRL_INT28 (0x10000000) +#define INTC_IPRL_INT27 (0x08000000) +#define INTC_IPRL_INT26 (0x04000000) +#define INTC_IPRL_INT25 (0x02000000) +#define INTC_IPRL_INT24 (0x01000000) +#define INTC_IPRL_INT23 (0x00800000) +#define INTC_IPRL_INT22 (0x00400000) +#define INTC_IPRL_INT21 (0x00200000) +#define INTC_IPRL_INT20 (0x00100000) +#define INTC_IPRL_INT19 (0x00080000) +#define INTC_IPRL_INT18 (0x00040000) +#define INTC_IPRL_INT17 (0x00020000) +#define INTC_IPRL_INT16 (0x00010000) +#define INTC_IPRL_INT15 (0x00008000) +#define INTC_IPRL_INT14 (0x00004000) +#define INTC_IPRL_INT13 (0x00002000) +#define INTC_IPRL_INT12 (0x00001000) +#define INTC_IPRL_INT11 (0x00000800) +#define INTC_IPRL_INT10 (0x00000400) +#define INTC_IPRL_INT9 (0x00000200) +#define INTC_IPRL_INT8 (0x00000100) +#define INTC_IPRL_INT7 (0x00000080) +#define INTC_IPRL_INT6 (0x00000040) +#define INTC_IPRL_INT5 (0x00000020) +#define INTC_IPRL_INT4 (0x00000010) +#define INTC_IPRL_INT3 (0x00000008) +#define INTC_IPRL_INT2 (0x00000004) +#define INTC_IPRL_INT1 (0x00000002) +#define INTC_IPRL_INT0 (0x00000001) + +/* Bit definitions and macros for INTC_IRLR */ +#define INTC_IRLRn(x) (((x)&0x7F)<<1) + +/* Bit definitions and macros for INTC_IACKLPRn */ +#define INTC_IACKLPRn_LEVEL(x) (((x)&0x07)<<4) +#define INTC_IACKLPRn_PRI(x) ((x)&0x0F) + +/* Bit definitions and macros for INTC_ICRnx */ +#define INTC_ICRnx_IL(x) (((x)&0x07)<<3) +#define INTC_ICRnx_IP(x) ((x)&0x07) + +/********************************************************************* +* General Purpose I/O (GPIO) +*********************************************************************/ +/* Bit definitions and macros for GPIO_PODR */ +#define GPIO_PODR_ADDR(x) (((x)&0x07)<<5) +#define GPIO_PODR_ADDR_MASK (0xE0) +#define GPIO_PODR_BS(x) ((x)&0x0F) +#define GPIO_PODR_BS_MASK (0x0F) +#define GPIO_PODR_CS(x) (((x)&0x7F)<<1) +#define GPIO_PODR_CS_MASK (0xFE) +#define GPIO_PODR_SDRAM(X) ((x)&0x3F) +#define GPIO_PODR_SDRAM_MASK (0x3F) +#define GPIO_PODR_FECI2C(x) GPIO_PODR_BS(x) +#define GPIO_PODR_FECI2C_MASK GPIO_PODR_BS_MASK +#define GPIO_PODR_UARTH(x) ((x)&0x03) +#define GPIO_PODR_UARTH_MASK (0x03) +#define GPIO_PODR_QSPI(x) ((x)&0x1F) +#define GPIO_PODR_QSPI_MASK (0x1F) +#define GPIO_PODR_ETPU(x) ((x)&0x07) +#define GPIO_PODR_ETPU_MASK (0x07) + +/* Bit definitions and macros for GPIO_PDDR */ +#define GPIO_PDDR_ADDR(x) GPIO_PODR_ADDR(x) +#define GPIO_PDDR_ADDR_MASK GPIO_PODR_ADDR_MASK +#define GPIO_PDDR_BS(x) GPIO_PODR_BS(x) +#define GPIO_PDDR_BS_MASK GPIO_PODR_BS_MASK +#define GPIO_PDDR_CS(x) GPIO_PODR_CS(x) +#define GPIO_PDDR_CS_MASK GPIO_PODR_CS_MASK +#define GPIO_PDDR_SDRAM(X) GPIO_PODR_SDRAM(X) +#define GPIO_PDDR_SDRAM_MASK GPIO_PODR_SDRAM_MASK +#define GPIO_PDDR_FECI2C(x) GPIO_PDDR_BS(x) +#define GPIO_PDDR_FECI2C_MASK GPIO_PDDR_BS_MASK +#define GPIO_PDDR_UARTH(x) GPIO_PODR_UARTH(x) +#define GPIO_PDDR_UARTH_MASK GPIO_PODR_UARTH_MASK +#define GPIO_PDDR_QSPI(x) GPIO_PODR_QSPI(x) +#define GPIO_PDDR_QSPI_MASK GPIO_PODR_QSPI_MASK +#define GPIO_PDDR_ETPU(x) GPIO_PODR_ETPU(x) +#define GPIO_PDDR_ETPU_MASK GPIO_PODR_ETPU_MASK + +/* Bit definitions and macros for GPIO_PPDSDR */ +#define GPIO_PPDSDR_ADDR(x) GPIO_PODR_ADDR(x) +#define GPIO_PPDSDR_ADDR_MASK GPIO_PODR_ADDR_MASK +#define GPIO_PPDSDR_BS(x) GPIO_PODR_BS(x) +#define GPIO_PPDSDR_BS_MASK GPIO_PODR_BS_MASK +#define GPIO_PPDSDR_CS(x) GPIO_PODR_CS(x) +#define GPIO_PPDSDR_CS_MASK GPIO_PODR_CS_MASK +#define GPIO_PPDSDR_SDRAM(X) GPIO_PODR_SDRAM(X) +#define GPIO_PPDSDR_SDRAM_MASK GPIO_PODR_SDRAM_MASK +#define GPIO_PPDSDR_FECI2C(x) GPIO_PPDSDR_BS(x) +#define GPIO_PPDSDR_FECI2C_MASK GPIO_PPDSDR_BS_MASK +#define GPIO_PPDSDR_UARTH(x) GPIO_PODR_UARTH(x) +#define GPIO_PPDSDR_UARTH_MASK GPIO_PODR_UARTH_MASK +#define GPIO_PPDSDR_QSPI(x) GPIO_PODR_QSPI(x) +#define GPIO_PPDSDR_QSPI_MASK GPIO_PODR_QSPI_MASK +#define GPIO_PPDSDR_ETPU(x) GPIO_PODR_ETPU(x) +#define GPIO_PPDSDR_ETPU_MASK GPIO_PODR_ETPU_MASK + +/* Bit definitions and macros for GPIO_PCLRR */ +#define GPIO_PCLRR_ADDR(x) GPIO_PODR_ADDR(x) +#define GPIO_PCLRR_ADDR_MASK GPIO_PODR_ADDR_MASK +#define GPIO_PCLRR_BS(x) GPIO_PODR_BS(x) +#define GPIO_PCLRR_BS_MASK GPIO_PODR_BS_MASK +#define GPIO_PCLRR_CS(x) GPIO_PODR_CS(x) +#define GPIO_PCLRR_CS_MASK GPIO_PODR_CS_MASK +#define GPIO_PCLRR_SDRAM(X) GPIO_PODR_SDRAM(X) +#define GPIO_PCLRR_SDRAM_MASK GPIO_PODR_SDRAM_MASK +#define GPIO_PCLRR_FECI2C(x) GPIO_PCLRR_BS(x) +#define GPIO_PCLRR_FECI2C_MASK GPIO_PCLRR_BS_MASK +#define GPIO_PCLRR_UARTH(x) GPIO_PODR_UARTH(x) +#define GPIO_PCLRR_UARTH_MASK GPIO_PODR_UARTH_MASK +#define GPIO_PCLRR_QSPI(x) GPIO_PODR_QSPI(x) +#define GPIO_PCLRR_QSPI_MASK GPIO_PODR_QSPI_MASK +#define GPIO_PCLRR_ETPU(x) GPIO_PODR_ETPU(x) +#define GPIO_PCLRR_ETPU_MASK GPIO_PODR_ETPU_MASK + +/* Bit definitions and macros for GPIO_PAR */ +#define GPIO_PAR_AD_ADDR23 (0x80) +#define GPIO_PAR_AD_ADDR22 (0x40) +#define GPIO_PAR_AD_ADDR21 (0x20) +#define GPIO_PAR_AD_DATAL (0x01) +#define GPIO_PAR_BUSCTL_OE (0x4000) +#define GPIO_PAR_BUSCTL_TA (0x1000) +#define GPIO_PAR_BUSCTL_TEA(x) (((x)&0x03)<<10) +#define GPIO_PAR_BUSCTL_TEA_MASK (0x0C00) +#define GPIO_PAR_BUSCTL_TEA_GPIO (0x0400) +#define GPIO_PAR_BUSCTL_TEA_DREQ1 (0x0800) +#define GPIO_PAR_BUSCTL_TEA_EXTBUS (0x0C00) +#define GPIO_PAR_BUSCTL_RWB (0x0100) +#define GPIO_PAR_BUSCTL_TSIZ1 (0x0040) +#define GPIO_PAR_BUSCTL_TSIZ0 (0x0010) +#define GPIO_PAR_BUSCTL_TS(x) (((x)&0x03)<<2) +#define GPIO_PAR_BUSCTL_TS_MASK (0x0C) +#define GPIO_PAR_BUSCTL_TS_GPIO (0x04) +#define GPIO_PAR_BUSCTL_TS_DACK2 (0x08) +#define GPIO_PAR_BUSCTL_TS_EXTBUS (0x0C) +#define GPIO_PAR_BUSCTL_TIP(x) ((x)&0x03) +#define GPIO_PAR_BUSCTL_TIP_MASK (0x03) +#define GPIO_PAR_BUSCTL_TIP_GPIO (0x01) +#define GPIO_PAR_BUSCTL_TIP_DREQ0 (0x02) +#define GPIO_PAR_BUSCTL_TIP_EXTBUS (0x03) +#define GPIO_PAR_BS(x) ((x)&0x0F) +#define GPIO_PAR_BS_MASK (0x0F) +#define GPIO_PAR_CS(x) (((x)&0x7F)<<1) +#define GPIO_PAR_CS_MASK (0xFE) +#define GPIO_PAR_CS_CS7 (0x80) +#define GPIO_PAR_CS_CS6 (0x40) +#define GPIO_PAR_CS_CS5 (0x20) +#define GPIO_PAR_CS_CS4 (0x10) +#define GPIO_PAR_CS_CS3 (0x08) +#define GPIO_PAR_CS_CS2 (0x04) +#define GPIO_PAR_CS_CS1 (0x02) +#define GPIO_PAR_CS_SD3 GPIO_PAR_CS_CS3 +#define GPIO_PAR_CS_SD2 GPIO_PAR_CS_CS2 +#define GPIO_PAR_SDRAM_CSSDCS(x) (((x)&0x03)<<6) +#define GPIO_PAR_SDRAM_CSSDCS_MASK (0xC0) +#define GPIO_PAR_SDRAM_SDWE (0x20) +#define GPIO_PAR_SDRAM_SCAS (0x10) +#define GPIO_PAR_SDRAM_SRAS (0x08) +#define GPIO_PAR_SDRAM_SCKE (0x04) +#define GPIO_PAR_SDRAM_SDCS(x) ((x)&0x03) +#define GPIO_PAR_SDRAM_SDCS_MASK (0x03) +#define GPIO_PAR_FECI2C_EMDC(x) (((x)&0x03)<<6) +#define GPIO_PAR_FECI2C_EMDC_MASK (0xC0) +#define GPIO_PAR_FECI2C_EMDC_U2TXD (0x40) +#define GPIO_PAR_FECI2C_EMDC_I2CSCL (0x80) +#define GPIO_PAR_FECI2C_EMDC_FECEMDC (0xC0) +#define GPIO_PAR_FECI2C_EMDIO(x) (((x)&0x03)<<4) +#define GPIO_PAR_FECI2C_EMDIO_MASK (0x30) +#define GPIO_PAR_FECI2C_EMDIO_U2RXD (0x10) +#define GPIO_PAR_FECI2C_EMDIO_I2CSDA (0x20) +#define GPIO_PAR_FECI2C_EMDIO_FECEMDIO (0x30) +#define GPIO_PAR_FECI2C_SCL(x) (((x)&0x03)<<2) +#define GPIO_PAR_FECI2C_SCL_MASK (0x0C) +#define GPIO_PAR_FECI2C_SCL_CAN0RX (0x08) +#define GPIO_PAR_FECI2C_SCL_I2CSCL (0x0C) +#define GPIO_PAR_FECI2C_SDA(x) ((x)&0x03) +#define GPIO_PAR_FECI2C_SDA_MASK (0x03) +#define GPIO_PAR_FECI2C_SDA_CAN0TX (0x02) +#define GPIO_PAR_FECI2C_SDA_I2CSDA (0x03) +#define GPIO_PAR_UART_DREQ2 (0x8000) +#define GPIO_PAR_UART_CAN1EN (0x4000) +#define GPIO_PAR_UART_U2RXD (0x2000) +#define GPIO_PAR_UART_U2TXD (0x1000) +#define GPIO_PAR_UART_U1RXD(x) (((x)&0x03)<<10) +#define GPIO_PAR_UART_U1RXD_MASK (0x0C00) +#define GPIO_PAR_UART_U1RXD_CAN0RX (0x0800) +#define GPIO_PAR_UART_U1RXD_U1RXD (0x0C00) +#define GPIO_PAR_UART_U1TXD(x) (((x)&0x03)<<8) +#define GPIO_PAR_UART_U1TXD_MASK (0x0300) +#define GPIO_PAR_UART_U1TXD_CAN0TX (0x0200) +#define GPIO_PAR_UART_U1TXD_U1TXD (0x0300) +#define GPIO_PAR_UART_U1CTS(x) (((x)&0x03)<<6) +#define GPIO_PAR_UART_U1CTS_MASK (0x00C0) +#define GPIO_PAR_UART_U1CTS_U2CTS (0x0080) +#define GPIO_PAR_UART_U1CTS_U1CTS (0x00C0) +#define GPIO_PAR_UART_U1RTS(x) (((x)&0x03)<<4) +#define GPIO_PAR_UART_U1RTS_MASK (0x0030) +#define GPIO_PAR_UART_U1RTS_U2RTS (0x0020) +#define GPIO_PAR_UART_U1RTS_U1RTS (0x0030) +#define GPIO_PAR_UART_U0RXD (0x0008) +#define GPIO_PAR_UART_U0TXD (0x0004) +#define GPIO_PAR_UART_U0CTS (0x0002) +#define GPIO_PAR_UART_U0RTS (0x0001) +#define GPIO_PAR_QSPI_CS1(x) (((x)&0x03)<<6) +#define GPIO_PAR_QSPI_CS1_MASK (0xC0) +#define GPIO_PAR_QSPI_CS1_SDRAMSCKE (0x80) +#define GPIO_PAR_QSPI_CS1_QSPICS1 (0xC0) +#define GPIO_PAR_QSPI_CS0 (0x20) +#define GPIO_PAR_QSPI_DIN(x) (((x)&0x03)<<3) +#define GPIO_PAR_QSPI_DIN_MASK (0x18) +#define GPIO_PAR_QSPI_DIN_I2CSDA (0x10) +#define GPIO_PAR_QSPI_DIN_QSPIDIN (0x18) +#define GPIO_PAR_QSPI_DOUT (0x04) +#define GPIO_PAR_QSPI_SCK(x) ((x)&0x03) +#define GPIO_PAR_QSPI_SCK_MASK (0x03) +#define GPIO_PAR_QSPI_SCK_I2CSCL (0x02) +#define GPIO_PAR_QSPI_SCK_QSPISCK (0x03) +#define GPIO_PAR_DT3IN(x) (((x)&0x03)<<14) +#define GPIO_PAR_DT3IN_MASK (0xC000) +#define GPIO_PAR_DT3IN_QSPICS2 (0x4000) +#define GPIO_PAR_DT3IN_U2CTS (0x8000) +#define GPIO_PAR_DT3IN_DT3IN (0xC000) +#define GPIO_PAR_DT2IN(x) (((x)&0x03)<<12) +#define GPIO_PAR_DT2IN_MASK (0x3000) +#define GPIO_PAR_DT2IN_DT2OUT (0x1000) +#define GPIO_PAR_DT2IN_DREQ2 (0x2000) +#define GPIO_PAR_DT2IN_DT2IN (0x3000) +#define GPIO_PAR_DT1IN(x) (((x)&0x03)<<10) +#define GPIO_PAR_DT1IN_MASK (0x0C00) +#define GPIO_PAR_DT1IN_DT1OUT (0x0400) +#define GPIO_PAR_DT1IN_DREQ1 (0x0800) +#define GPIO_PAR_DT1IN_DT1IN (0x0C00) +#define GPIO_PAR_DT0IN(x) (((x)&0x03)<<8) +#define GPIO_PAR_DT0IN_MASK (0x0300) +#define GPIO_PAR_DT0IN_DREQ0 (0x0200) +#define GPIO_PAR_DT0IN_DT0IN (0x0300) +#define GPIO_PAR_DT3OUT(x) (((x)&0x03)<<6) +#define GPIO_PAR_DT3OUT_MASK (0x00C0) +#define GPIO_PAR_DT3OUT_QSPICS3 (0x0040) +#define GPIO_PAR_DT3OUT_U2RTS (0x0080) +#define GPIO_PAR_DT3OUT_DT3OUT (0x00C0) +#define GPIO_PAR_DT2OUT(x) (((x)&0x03)<<4) +#define GPIO_PAR_DT2OUT_MASK (0x0030) +#define GPIO_PAR_DT2OUT_DACK2 (0x0020) +#define GPIO_PAR_DT2OUT_DT2OUT (0x0030) +#define GPIO_PAR_DT1OUT(x) (((x)&0x03)<<2) +#define GPIO_PAR_DT1OUT_MASK (0x000C) +#define GPIO_PAR_DT1OUT_DACK1 (0x0008) +#define GPIO_PAR_DT1OUT_DT1OUT (0x000C) +#define GPIO_PAR_DT0OUT(x) ((x)&0x03) +#define GPIO_PAR_DT0OUT_MASK (0x0003) +#define GPIO_PAR_DT0OUT_DACK0 (0x0002) +#define GPIO_PAR_DT0OUT_DT0OUT (0x0003) +#define GPIO_PAR_ETPU_TCRCLK (0x04) +#define GPIO_PAR_ETPU_UTPU_ODIS (0x02) +#define GPIO_PAR_ETPU_LTPU_ODIS (0x01) + +/* Bit definitions and macros for GPIO_DSCR */ +#define GPIO_DSCR_EIM_EIM1 (0x10) +#define GPIO_DSCR_EIM_EIM0 (0x01) +#define GPIO_DSCR_ETPU_ETPU31_24 (0x40) +#define GPIO_DSCR_ETPU_ETPU23_16 (0x10) +#define GPIO_DSCR_ETPU_ETPU15_8 (0x04) +#define GPIO_DSCR_ETPU_ETPU7_0 (0x01) +#define GPIO_DSCR_FECI2C_FEC (0x10) +#define GPIO_DSCR_FECI2C_I2C (0x01) +#define GPIO_DSCR_UART_IRQ (0x40) +#define GPIO_DSCR_UART_UART2 (0x10) +#define GPIO_DSCR_UART_UART1 (0x04) +#define GPIO_DSCR_UART_UART0 (0x01) +#define GPIO_DSCR_QSPI_QSPI (0x01) +#define GPIO_DSCR_TIMER (0x01) + +/********************************************************************* +* Chip Configuration Module (CCM) +*********************************************************************/ +/* Bit definitions and macros for CCM_RCR */ +#define CCM_RCR_SOFTRST (0x80) +#define CCM_RCR_FRCRSTOUT (0x40) + +/* Bit definitions and macros for CCM_RSR */ +#define CCM_RSR_SOFT (0x20) +#define CCM_RSR_WDR (0x10) +#define CCM_RSR_POR (0x08) +#define CCM_RSR_EXT (0x04) +#define CCM_RSR_LOC (0x02) +#define CCM_RSR_LOL (0x01) + +/* Bit definitions and macros for CCM_CCR */ +#define CCM_CCR_LOAD (0x8000) +#define CCM_CCR_SZEN (0x0040) +#define CCM_CCR_PSTEN (0x0020) +#define CCM_CCR_BME (0x0008) +#define CCM_CCR_BMT(x) ((x)&0x07) +#define CCM_CCR_BMT_MASK (0x0007) +#define CCM_CCR_BMT_64K (0x0000) +#define CCM_CCR_BMT_32K (0x0001) +#define CCM_CCR_BMT_16K (0x0002) +#define CCM_CCR_BMT_8K (0x0003) +#define CCM_CCR_BMT_4K (0x0004) +#define CCM_CCR_BMT_2K (0x0005) +#define CCM_CCR_BMT_1K (0x0006) +#define CCM_CCR_BMT_512 (0x0007) + +/* Bit definitions and macros for CCM_RCON */ +#define CCM_RCON_RCSC(x) (((x)&0x0003)<<8) +#define CCM_RCON_RLOAD (0x0020) +#define CCM_RCON_BOOTPS(x) (((x)&0x0003)<<3) +#define CCM_RCON_BOOTPS_MASK (0x0018) +#define CCM_RCON_BOOTPS_32 (0x0018) +#define CCM_RCON_BOOTPS_16 (0x0008) +#define CCM_RCON_BOOTPS_8 (0x0010) +#define CCM_RCON_MODE (0x0001) + +/* Bit definitions and macros for CCM_CIR */ +#define CCM_CIR_PIN(x) (((x)&0x03FF)<<6) +#define CCM_CIR_PRN(x) ((x)&0x003F) + +/********************************************************************* +* PLL Clock Module +*********************************************************************/ +/* Bit definitions and macros for PLL_SYNCR */ +#define PLL_SYNCR_MFD(x) (((x)&0x07)<<24) +#define PLL_SYNCR_MFD_MASK (0x07000000) +#define PLL_SYNCR_RFC(x) (((x)&0x07)<<19) +#define PLL_SYNCR_RFC_MASK (0x00380000) +#define PLL_SYNCR_LOCEN (0x00040000) +#define PLL_SYNCR_LOLRE (0x00020000) +#define PLL_SYNCR_LOCRE (0x00010000) +#define PLL_SYNCR_DISCLK (0x00008000) +#define PLL_SYNCR_LOLIRQ (0x00004000) +#define PLL_SYNCR_LOCIRQ (0x00002000) +#define PLL_SYNCR_RATE (0x00001000) +#define PLL_SYNCR_DEPTH(x) (((x)&0x03)<<10) +#define PLL_SYNCR_EXP(x) ((x)&0x03FF) + +/* Bit definitions and macros for PLL_SYNSR */ +#define PLL_SYNSR_LOLF (0x00000200) +#define PLL_SYNSR_LOC (0x00000100) +#define PLL_SYNSR_MODE (0x00000080) +#define PLL_SYNSR_PLLSEL (0x00000040) +#define PLL_SYNSR_PLLREF (0x00000020) +#define PLL_SYNSR_LOCKS (0x00000010) +#define PLL_SYNSR_LOCK (0x00000008) +#define PLL_SYNSR_LOCF (0x00000004) +#define PLL_SYNSR_CALDONE (0x00000002) +#define PLL_SYNSR_CALPASS (0x00000001) + +/********************************************************************* + * Edge Port +*********************************************************************/ +#define EPORT_EPPAR_EPPA7(x) (((x)&0x03)<<14) +#define EPORT_EPPAR_EPPA6(x) (((x)&0x03)<<12) +#define EPORT_EPPAR_EPPA5(x) (((x)&0x03)<<10) +#define EPORT_EPPAR_EPPA4(x) (((x)&0x03)<<8) +#define EPORT_EPPAR_EPPA3(x) (((x)&0x03)<<6) +#define EPORT_EPPAR_EPPA2(x) (((x)&0x03)<<4) +#define EPORT_EPPAR_EPPA1(x) (((x)&0x03)<<2) + +#define EPORT_EPDDR_EPDD7(x) EPORT_EPPAR_EPPA7(x) +#define EPORT_EPDDR_EPDD6(x) EPORT_EPPAR_EPPA6(x) +#define EPORT_EPDDR_EPDD5(x) EPORT_EPPAR_EPPA5(x) +#define EPORT_EPDDR_EPDD4(x) EPORT_EPPAR_EPPA4(x) +#define EPORT_EPDDR_EPDD3(x) EPORT_EPPAR_EPPA3(x) +#define EPORT_EPDDR_EPDD2(x) EPORT_EPPAR_EPPA2(x) +#define EPORT_EPDDR_EPDD1(x) EPORT_EPPAR_EPPA1(x) + +#define EPORT_EPIER_EPIE7 (0x80) +#define EPORT_EPIER_EPIE6 (0x40) +#define EPORT_EPIER_EPIE5 (0x20) +#define EPORT_EPIER_EPIE4 (0x10) +#define EPORT_EPIER_EPIE3 (0x08) +#define EPORT_EPIER_EPIE2 (0x04) +#define EPORT_EPIER_EPIE1 (0x02) + +#define EPORT_EPDR_EPDR7 EPORT_EPIER_EPIE7 +#define EPORT_EPDR_EPDR6 EPORT_EPIER_EPIE6 +#define EPORT_EPDR_EPDR5 EPORT_EPIER_EPIE5 +#define EPORT_EPDR_EPDR4 EPORT_EPIER_EPIE4 +#define EPORT_EPDR_EPDR3 EPORT_EPIER_EPIE3 +#define EPORT_EPDR_EPDR2 EPORT_EPIER_EPIE2 +#define EPORT_EPDR_EPDR1 EPORT_EPIER_EPIE1 + +#define EPORT_EPPDR_EPPDR7 EPORT_EPIER_EPIE7 +#define EPORT_EPPDR_EPPDR6 EPORT_EPIER_EPIE6 +#define EPORT_EPPDR_EPPDR5 EPORT_EPIER_EPIE5 +#define EPORT_EPPDR_EPPDR4 EPORT_EPIER_EPIE4 +#define EPORT_EPPDR_EPPDR3 EPORT_EPIER_EPIE3 +#define EPORT_EPPDR_EPPDR2 EPORT_EPIER_EPIE2 +#define EPORT_EPPDR_EPPDR1 EPORT_EPIER_EPIE1 + +/********************************************************************* +* Watchdog Timer Modules (WTM) +*********************************************************************/ +/* Bit definitions and macros for WTM_WCR */ +#define WTM_WCR_WAIT (0x0008) +#define WTM_WCR_DOZE (0x0004) +#define WTM_WCR_HALTED (0x0002) +#define WTM_WCR_EN (0x0001) + +/********************************************************************* +* FlexCAN Module (CAN) +*********************************************************************/ +/* Bit definitions and macros for CAN_CANMCR */ +#define CANMCR_MDIS (0x80000000) +#define CANMCR_FRZ (0x40000000) +#define CANMCR_HALT (0x10000000) +#define CANMCR_NORDY (0x08000000) +#define CANMCR_SOFTRST (0x02000000) +#define CANMCR_FRZACK (0x01000000) +#define CANMCR_SUPV (0x00800000) +#define CANMCR_LPMACK (0x00100000) +#define CANMCR_MAXMB(x) (((x)&0x0F)) + +/* Bit definitions and macros for CAN_CANCTRL */ +#define CANCTRL_PRESDIV(x) (((x)&0xFF)<<24) +#define CANCTRL_RJW(x) (((x)&0x03)<<22) +#define CANCTRL_PSEG1(x) (((x)&0x07)<<19) +#define CANCTRL_PSEG2(x) (((x)&0x07)<<16) +#define CANCTRL_BOFFMSK (0x00008000) +#define CANCTRL_ERRMSK (0x00004000) +#define CANCTRL_CLKSRC (0x00002000) +#define CANCTRL_LPB (0x00001000) +#define CANCTRL_SMP (0x00000080) +#define CANCTRL_BOFFREC (0x00000040) +#define CANCTRL_TSYNC (0x00000020) +#define CANCTRL_LBUF (0x00000010) +#define CANCTRL_LOM (0x00000008) +#define CANCTRL_PROPSEG(x) (((x)&0x07)) + +/* Bit definitions and macros for CAN_TIMER */ +#define TIMER_TIMER(x) ((x)&0xFFFF) + +/* Bit definitions and macros for CAN_RXGMASK */ +#define RXGMASK_MI(x) ((x)&0x1FFFFFFF) + +/* Bit definitions and macros for CAN_ERRCNT */ +#define ERRCNT_TXECTR(x) (((x)&0xFF)) +#define ERRCNT_RXECTR(x) (((x)&0xFF)<<8) + +/* Bit definitions and macros for CAN_ERRSTAT */ +#define ERRSTAT_BITERR1 (0x00008000) +#define ERRSTAT_BITERR0 (0x00004000) +#define ERRSTAT_ACKERR (0x00002000) +#define ERRSTAT_CRCERR (0x00001000) +#define ERRSTAT_FRMERR (0x00000800) +#define ERRSTAT_STFERR (0x00000400) +#define ERRSTAT_TXWRN (0x00000200) +#define ERRSTAT_RXWRN (0x00000100) +#define ERRSTAT_IDLE (0x00000080) +#define ERRSTAT_TXRX (0x00000040) +#define ERRSTAT_FLT_BUSOFF (0x00000020) +#define ERRSTAT_FLT_PASSIVE (0x00000010) +#define ERRSTAT_FLT_ACTIVE (0x00000000) +#define ERRSTAT_BOFFINT (0x00000004) +#define ERRSTAT_ERRINT (0x00000002) + +/* Bit definitions and macros for CAN_IMASK */ +#define IMASK_BUF15M (0x00008000) +#define IMASK_BUF14M (0x00004000) +#define IMASK_BUF13M (0x00002000) +#define IMASK_BUF12M (0x00001000) +#define IMASK_BUF11M (0x00000800) +#define IMASK_BUF10M (0x00000400) +#define IMASK_BUF9M (0x00000200) +#define IMASK_BUF8M (0x00000100) +#define IMASK_BUF7M (0x00000080) +#define IMASK_BUF6M (0x00000040) +#define IMASK_BUF5M (0x00000020) +#define IMASK_BUF4M (0x00000010) +#define IMASK_BUF3M (0x00000008) +#define IMASK_BUF2M (0x00000004) +#define IMASK_BUF1M (0x00000002) +#define IMASK_BUF0M (0x00000001) + +/* Bit definitions and macros for CAN_IFLAG */ +#define IFLAG_BUF15I (0x00008000) +#define IFLAG_BUF14I (0x00004000) +#define IFLAG_BUF13I (0x00002000) +#define IFLAG_BUF12I (0x00001000) +#define IFLAG_BUF11I (0x00000800) +#define IFLAG_BUF10I (0x00000400) +#define IFLAG_BUF9I (0x00000200) +#define IFLAG_BUF8I (0x00000100) +#define IFLAG_BUF7I (0x00000080) +#define IFLAG_BUF6I (0x00000040) +#define IFLAG_BUF5I (0x00000020) +#define IFLAG_BUF4I (0x00000010) +#define IFLAG_BUF3I (0x00000008) +#define IFLAG_BUF2I (0x00000004) +#define IFLAG_BUF1I (0x00000002) +#define IFLAG_BUF0I (0x00000001) + +#endif /* mcf5235_h */ diff --git a/include/configs/M5235EVB.h b/include/configs/M5235EVB.h new file mode 100644 index 000000000..7f544c839 --- /dev/null +++ b/include/configs/M5235EVB.h @@ -0,0 +1,261 @@ +/* + * Configuation settings for the Freescale MCF5329 FireEngine board. + * + * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef _M5235EVB_H +#define _M5235EVB_H + +/* + * High Level Configuration Options + * (easy to change) + */ +#define CONFIG_MCF523x /* define processor family */ +#define CONFIG_M5235 /* define processor type */ + +#undef DEBUG + +#define CONFIG_MCFUART +#define CFG_UART_PORT (0) +#define CONFIG_BAUDRATE 115200 +#define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 } + +#undef CONFIG_WATCHDOG +#define CONFIG_WATCHDOG_TIMEOUT 5000 /* timeout in milliseconds, max timeout is 6.71sec */ + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + +/* Command line configuration */ +#include + +#define CONFIG_CMD_BOOTD +#define CONFIG_CMD_CACHE +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_ELF +#define CONFIG_CMD_FLASH +#define CONFIG_CMD_I2C +#define CONFIG_CMD_MEMORY +#define CONFIG_CMD_MISC +#define CONFIG_CMD_MII +#define CONFIG_CMD_NET +#define CONFIG_CMD_PCI +#define CONFIG_CMD_PING +#define CONFIG_CMD_REGINFO + +#undef CONFIG_CMD_LOADB +#undef CONFIG_CMD_LOADS + +#define CONFIG_MCFFEC +#ifdef CONFIG_MCFFEC +# define CONFIG_NET_MULTI 1 +# define CONFIG_MII 1 +# define CFG_DISCOVER_PHY +# define CFG_RX_ETH_BUFFER 8 +# define CFG_FAULT_ECHO_LINK_DOWN + +# define CFG_FEC0_PINMUX 0 +# define CFG_FEC0_MIIBASE CFG_FEC0_IOBASE +# define MCFFEC_TOUT_LOOP 50000 +/* If CFG_DISCOVER_PHY is not defined - hardcoded */ +# ifndef CFG_DISCOVER_PHY +# define FECDUPLEX FULL +# define FECSPEED _100BASET +# else +# ifndef CFG_FAULT_ECHO_LINK_DOWN +# define CFG_FAULT_ECHO_LINK_DOWN +# endif +# endif /* CFG_DISCOVER_PHY */ +#endif + +/* Timer */ +#define CONFIG_MCFTMR +#undef CONFIG_MCFPIT + +/* I2C */ +#define CONFIG_FSL_I2C +#define CONFIG_HARD_I2C /* I2C with hw support */ +#undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CFG_I2C_SPEED 80000 +#define CFG_I2C_SLAVE 0x7F +#define CFG_I2C_OFFSET 0x00000300 +#define CFG_IMMR CFG_MBAR + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */ +#define CONFIG_BOOTFILE "u-boot.bin" +#ifdef CONFIG_MCFFEC +# define CONFIG_ETHADDR 00:e0:0c:bc:e5:60 +# define CONFIG_IPADDR 192.162.1.2 +# define CONFIG_NETMASK 255.255.255.0 +# define CONFIG_SERVERIP 192.162.1.1 +# define CONFIG_GATEWAYIP 192.162.1.1 +# define CONFIG_OVERWRITE_ETHADDR_ONCE +#endif /* FEC_ENET */ + +#define CONFIG_HOSTNAME M5235EVB +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "loadaddr=10000\0" \ + "u-boot=u-boot.bin\0" \ + "load=tftp ${loadaddr) ${u-boot}\0" \ + "upd=run load; run prog\0" \ + "prog=prot off ffe00000 ffe3ffff;" \ + "era ffe00000 ffe3ffff;" \ + "cp.b ${loadaddr} ffe00000 ${filesize};"\ + "save\0" \ + "" + +#define CONFIG_PRAM 512 /* 512 KB */ +#define CFG_PROMPT "-> " +#define CFG_LONGHELP /* undef to save memory */ + +#if defined(CONFIG_KGDB) +# define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +# define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif + +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ +#define CFG_LOAD_ADDR (CFG_SDRAM_BASE+0x20000) + +#define CFG_HZ 1000 +#define CFG_CLK 75000000 +#define CFG_CPU_CLK CFG_CLK * 2 + +#define CFG_MBAR 0x40000000 + +/* + * Low Level Configuration Settings + * (address mappings, register initial values, etc.) + * You should know what you are doing if you make changes here. + */ +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area (in DPRAM) + */ +#define CFG_INIT_RAM_ADDR 0x20000000 +#define CFG_INIT_RAM_END 0x10000 /* End of used area in internal SRAM */ +#define CFG_INIT_RAM_CTRL 0x21 +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE - 0x10) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + */ +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_SDRAM_SIZE 16 /* SDRAM size in MB */ + +#define CFG_MEMTEST_START CFG_SDRAM_BASE + 0x400 +#define CFG_MEMTEST_END ((CFG_SDRAM_SIZE - 3) << 20) + +#define CFG_MONITOR_BASE (CFG_FLASH_BASE + 0x400) +#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ + +#define CFG_BOOTPARAMS_LEN 64*1024 +#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization ?? + */ +/* Initial Memory map for Linux */ +#define CFG_BOOTMAPSZ (CFG_SDRAM_BASE + (CFG_SDRAM_SIZE << 20)) + +/*----------------------------------------------------------------------- + * FLASH organization + */ +#define CFG_FLASH_CFI +#ifdef CFG_FLASH_CFI +# define CFG_FLASH_CFI_DRIVER 1 +# define CFG_FLASH_SIZE 0x800000 /* Max size that the board might have */ +#ifdef NORFLASH_PS32BIT +# define CFG_FLASH_CFI_WIDTH FLASH_CFI_32BIT +#else +# define CFG_FLASH_CFI_WIDTH FLASH_CFI_16BIT +#endif +# define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +# define CFG_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ +# define CFG_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ +#endif + +#define CFG_FLASH_BASE (CFG_CS0_BASE << 16) + +/* Configuration for environment + * Environment is embedded in u-boot in the second sector of the flash + */ +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_IS_EMBEDDED 1 +#ifdef NORFLASH_PS32BIT +# define CFG_ENV_OFFSET (0x8000) +# define CFG_ENV_SIZE 0x4000 +# define CFG_ENV_SECT_SIZE 0x4000 +#else +# define CFG_ENV_OFFSET (0x4000) +# define CFG_ENV_SIZE 0x2000 +# define CFG_ENV_SECT_SIZE 0x2000 +#endif + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_CACHELINE_SIZE 16 + +/*----------------------------------------------------------------------- + * Chipselect bank definitions + */ +/* + * CS0 - NOR Flash 1, 2, 4, or 8MB + * CS1 - Available + * CS2 - Available + * CS3 - Available + * CS4 - Available + * CS5 - Available + * CS6 - Available + * CS7 - Available + */ +#ifdef NORFLASH_PS32BIT +# define CFG_CS0_BASE 0xFFC0 +# define CFG_CS0_MASK 0x003f0001 +# define CFG_CS0_CTRL 0x1D00 +#else +# define CFG_CS0_BASE 0xFFE0 +# define CFG_CS0_MASK 0x001f0001 +# define CFG_CS0_CTRL 0x1D80 +#endif + +#endif /* _M5329EVB_H */ From 8280f6a1c43247616b68224675188e5ccd124650 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Sat, 18 Aug 2007 14:33:02 +0200 Subject: [PATCH 173/259] Coding style cleanup Signed-off-by: Stefan Roese --- CREDITS | 56 +++++++++++++-------------- board/freescale/m5249evb/m5249evb.c | 1 - board/freescale/m5253evbe/m5253evbe.c | 1 - board/freescale/m54455evb/m54455evb.c | 1 - cpu/mcf523x/cpu_init.c | 28 +++++++------- cpu/mcf523x/speed.c | 3 +- cpu/mcf52x2/cpu_init.c | 2 +- doc/README.m5253evbe | 6 +-- include/configs/M5249EVB.h | 1 - include/configs/M5253EVBE.h | 1 - lib_m68k/m68k_linux.c | 6 ++- 11 files changed, 52 insertions(+), 54 deletions(-) diff --git a/CREDITS b/CREDITS index 6e44db470..0953e7b95 100644 --- a/CREDITS +++ b/CREDITS @@ -147,6 +147,11 @@ N: Daniel Engstr E: daniel@omicron.se D: x86 port, Support for sc520_cdp board +N: Hayden Fraser +E: Hayden.Fraser@freescale.com +D: Support for ColdFire MCF5253 +W: www.freescale.com + N: Dr. Wolfgang Grandegger E: wg@denx.de D: Support for Interphase 4539 T1/E1/J1 PMC, PN62, CCM, SCM boards @@ -283,6 +288,11 @@ E: team@leox.org D: Support for LEOX boards, DS164x RTC W: http://www.leox.org +N: TsiChung Liew +E: Tsi-Chung.Liew@freescale.com +D: Support for ColdFire MCF523x, MCF532x, MCF5445x +W: www.freescale.com + N: Leif Lindholm E: leif.lindholm@i3micro.com D: Support for AMD dbau1550 board. @@ -297,6 +307,11 @@ N: Raymond Lo E: lo@routefree.com D: Support for DOS partitions +N: James MacAulay +E: james.macaulay@amirix.com +D: Suppport for Amirix AP1000 +W: www.amirix.com + N: Dan Malek E: dan@embeddedalley.com D: FADSROM, the grandfather of all of this @@ -372,8 +387,9 @@ D: Support for the Wind River sbc405, sbc8240 board W: http://www.windriver.com N: Stefan Roese -E: stefan.roese@esd-electronics.com -D: AMCC PPC401/403/405GP Support; Windows environment support +E: sr@denx.de +D: AMCC PPC4xx Support +W: http://www.denx.de N: Erwin Rol E: erwin@muffin.org @@ -407,6 +423,11 @@ N: Art Shipkowski E: art@videon-central.com D: Support for NetSilicon NS7520 +N: Michal Simek +E: monstr@monstr.eu +D: Support for Microblaze, ML401, XUPV2P board +W: www.monstr.eu + N: Yasushi Shoji E: yashi@atmark-techno.com D: Support for Xilinx MicroBlaze, for Atmark Techno SUZAKU FPGA board @@ -420,6 +441,11 @@ E: andrea.scian@dave-tech.it D: Port to B2 board W: www.dave-tech.it +N: Timur Tabi +E: timur@freescale.com +D: Support for MPC8349E-mITX +W: www.freescale.com + N: Rob Taylor E: robt@flyingpig.com D: Port to MBX860T and Sandpoint8240 @@ -473,29 +499,3 @@ N: Alex Zuepke E: azu@sysgo.de D: Overall improvements on StrongARM, ARM720TDMI; Support for Tuxscreen; initial PCMCIA support for ARM W: www.elinos.com - -N: James MacAulay -E: james.macaulay@amirix.com -D: Suppport for Amirix AP1000 -W: www.amirix.com - -N: Timur Tabi -E: timur@freescale.com -D: Support for MPC8349E-mITX -W: www.freescale.com - -N: Michal Simek -E: monstr@monstr.eu -D: Support for Microblaze, ML401, XUPV2P board -W: www.monstr.eu - -N: TsiChung Liew -E: Tsi-Chung.Liew@freescale.com -D: Support for ColdFire MCF523x, MCF532x, MCF5445x -W: www.freescale.com - -N: Hayden Fraser -E: Hayden.Fraser@freescale.com -D: Support for ColdFire MCF5253 -W: www.freescale.com - diff --git a/board/freescale/m5249evb/m5249evb.c b/board/freescale/m5249evb/m5249evb.c index b0bf41394..e8f621ba3 100644 --- a/board/freescale/m5249evb/m5249evb.c +++ b/board/freescale/m5249evb/m5249evb.c @@ -111,4 +111,3 @@ int testdram (void) { return (0); } - diff --git a/board/freescale/m5253evbe/m5253evbe.c b/board/freescale/m5253evbe/m5253evbe.c index 67fab5b02..43aa84de2 100644 --- a/board/freescale/m5253evbe/m5253evbe.c +++ b/board/freescale/m5253evbe/m5253evbe.c @@ -130,4 +130,3 @@ void ide_set_reset(int idereset) } } #endif /* CONFIG_CMD_IDE */ - diff --git a/board/freescale/m54455evb/m54455evb.c b/board/freescale/m54455evb/m54455evb.c index 1411a1a4c..6a0278252 100644 --- a/board/freescale/m54455evb/m54455evb.c +++ b/board/freescale/m54455evb/m54455evb.c @@ -162,4 +162,3 @@ void pci_init_board(void) pci_mcf5445x_init(&hose); } #endif /* CONFIG_PCI */ - diff --git a/cpu/mcf523x/cpu_init.c b/cpu/mcf523x/cpu_init.c index a31054d9a..55c9cd356 100644 --- a/cpu/mcf523x/cpu_init.c +++ b/cpu/mcf523x/cpu_init.c @@ -127,19 +127,19 @@ int cpu_init_r(void) void uart_port_conf(void) { - volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; + volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; - /* Setup Ports: */ - switch (CFG_UART_PORT) { - case 0: - gpio->par_uart = (GPIO_PAR_UART_U0RXD | GPIO_PAR_UART_U0TXD); - break; - case 1: - gpio->par_uart = - (GPIO_PAR_UART_U1RXD_U1RXD | GPIO_PAR_UART_U1TXD_U1TXD); - break; - case 2: - gpio->par_timer = (GPIO_PAR_UART_U2RXD | GPIO_PAR_UART_U2TXD); - break; - } + /* Setup Ports: */ + switch (CFG_UART_PORT) { + case 0: + gpio->par_uart = (GPIO_PAR_UART_U0RXD | GPIO_PAR_UART_U0TXD); + break; + case 1: + gpio->par_uart = + (GPIO_PAR_UART_U1RXD_U1RXD | GPIO_PAR_UART_U1TXD_U1TXD); + break; + case 2: + gpio->par_timer = (GPIO_PAR_UART_U2RXD | GPIO_PAR_UART_U2TXD); + break; + } } diff --git a/cpu/mcf523x/speed.c b/cpu/mcf523x/speed.c index 509109d0e..247d3188b 100644 --- a/cpu/mcf523x/speed.c +++ b/cpu/mcf523x/speed.c @@ -41,8 +41,9 @@ int get_clocks(void) pll->syncr = PLL_SYNCR_MFD(1); while (!(pll->synsr & PLL_SYNSR_LOCK)); - + gd->bus_clk = CFG_CLK; gd->cpu_clk = (gd->bus_clk * 2); + return (0); } diff --git a/cpu/mcf52x2/cpu_init.c b/cpu/mcf52x2/cpu_init.c index f41d77bc5..458b85ef1 100644 --- a/cpu/mcf52x2/cpu_init.c +++ b/cpu/mcf52x2/cpu_init.c @@ -63,7 +63,7 @@ void cpu_init_f(void) mbar2_writeByte(MCFSIM_INTBASE, 0x40); /* Base interrupts at 64 */ mbar2_writeByte(MCFSIM_SPURVEC, 0x00); - /*mbar2_writeLong(MCFSIM_IDECONFIG1, 0x00000020); *//* Enable a 1 cycle pre-drive cycle on CS1 */ + /*mbar2_writeLong(MCFSIM_IDECONFIG1, 0x00000020); */ /* Enable a 1 cycle pre-drive cycle on CS1 */ /* * Setup chip selects... diff --git a/doc/README.m5253evbe b/doc/README.m5253evbe index 7f2afcf15..0426cb1d4 100644 --- a/doc/README.m5253evbe +++ b/doc/README.m5253evbe @@ -18,14 +18,14 @@ Created 06/05/2007 SDR: 0x00000000-0x00ffffff SRAM0: 0x20010000-0x20017fff SRAM1: 0x20000000-0x2000ffff - MBAR1: 0x10000000-0x4fffffff + MBAR1: 0x10000000-0x4fffffff MBAR2: 0x80000000-0xCfffffff - Flash: 0xffe00000-0xffffffff + Flash: 0xffe00000-0xffffffff 3. DEFINITIONS AND COMPILATION ============================== 3.1 Explanation on NEW definitions in include/configs/M5253EVBE.h - CONFIG_MCF52x2 Processor family + CONFIG_MCF52x2 Processor family CONFIG_MCF5253 MCF5253 specific CONFIG_M5253EVBE Amadeus Plus board specific CFG_CLK Define Amadeus Plus CPU Clock diff --git a/include/configs/M5249EVB.h b/include/configs/M5249EVB.h index b300b68bc..de7ea4293 100644 --- a/include/configs/M5249EVB.h +++ b/include/configs/M5249EVB.h @@ -192,4 +192,3 @@ #define CFG_GPIO1_LED 0x00400000 /* user led */ #endif /* M5249 */ - diff --git a/include/configs/M5253EVBE.h b/include/configs/M5253EVBE.h index 9ad74e2bc..48170e7a3 100644 --- a/include/configs/M5253EVBE.h +++ b/include/configs/M5253EVBE.h @@ -210,4 +210,3 @@ #define CFG_GPIO1_LED 0x00400000 /* user led */ #endif /* _M5253EVB_H */ - diff --git a/lib_m68k/m68k_linux.c b/lib_m68k/m68k_linux.c index fde1744e4..bea97441b 100644 --- a/lib_m68k/m68k_linux.c +++ b/lib_m68k/m68k_linux.c @@ -92,7 +92,8 @@ void do_bootm_linux(cmd_tbl_t * cmdtp, int flag, */ asm("movel %%a7, %%d0\n" "movel %%d0, %0\n": "=d"(sp): :"%d0"); - debug("## Current stack ends at 0x%08lX ", sp); + + debug("## Current stack ends at 0x%08lX ", sp); sp -= 2048; /* just to be sure */ if (sp > CFG_BOOTMAPSZ) @@ -269,7 +270,8 @@ void do_bootm_linux(cmd_tbl_t * cmdtp, int flag, */ asm("movel %%a7, %%d0\n" "movel %%d0, %0\n": "=d"(nsp): :"%d0"); - nsp -= 2048; /* just to be sure */ + + nsp -= 2048; /* just to be sure */ nsp &= ~0xF; if (nsp > initrd_high) /* limit as specified */ From 26667b7fa05a8bf2fc65fb9f3230b02b1a10c367 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Sat, 18 Aug 2007 14:37:52 +0200 Subject: [PATCH 174/259] ColdFire: Fix some remaining problems with CFG_CMD_ Signed-off-by: Stefan Roese --- common/cmd_bdinfo.c | 4 ++-- doc/README.m54455evb | 2 +- include/configs/idmr.h | 6 +++--- 3 files changed, 6 insertions(+), 6 deletions(-) diff --git a/common/cmd_bdinfo.c b/common/cmd_bdinfo.c index 7686080f3..ef15a006c 100644 --- a/common/cmd_bdinfo.c +++ b/common/cmd_bdinfo.c @@ -237,7 +237,7 @@ int do_bdinfo ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) print_str ("inpfreq", strmhz(buf, bd->bi_inpfreq)); print_str ("vcofreq", strmhz(buf, bd->bi_vcofreq)); #endif -#if defined(CFG_CMD_NET) +#if defined(CONFIG_CMD_NET) puts ("ethaddr ="); for (i=0; i<6; ++i) { printf ("%c%02X", i ? ':' : ' ', bd->bi_enetaddr[i]); @@ -266,7 +266,7 @@ int do_bdinfo ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) puts ("\nip_addr = "); print_IPaddr (bd->bi_ip_addr); -#endif /* CONFIG_CMD_NET */ +#endif printf ("\nbaudrate = %d bps\n", bd->bi_baudrate); return 0; diff --git a/doc/README.m54455evb b/doc/README.m54455evb index c768fc8a4..119a19d89 100644 --- a/doc/README.m54455evb +++ b/doc/README.m54455evb @@ -78,7 +78,7 @@ CONFIG_MCFRTC -- define to use common CF RTC driver CFG_MCFRTC_BASE -- provide base address for RTC in immap.h CFG_RTC_OSCILLATOR -- define RTC clock frequency RTC_DEBUG -- define to show RTC debug message -CFG_CMD_DATE -- enable to use date feature in u-boot +CONFIG_CMD_DATE -- enable to use date feature in u-boot CONFIG_MCFFEC -- define to use common CF FEC driver CONFIG_NET_MULTI -- define to use multi FEC in u-boot diff --git a/include/configs/idmr.h b/include/configs/idmr.h index 3ec4a7944..404e88a4f 100644 --- a/include/configs/idmr.h +++ b/include/configs/idmr.h @@ -235,8 +235,8 @@ "2m(rootfs)," \ "-(user)"; -#if (CONFIG_COMMANDS & CFG_CMD_MII) -#error MII commands don't work on iDMR board and sholud not be enabled. -#endif /* (CONFIG_COMMANDS & CFG_CMD_MII) */ +#if defined(CONFIG_CMD_MII) +#error "MII commands don't work on iDMR board and should not be enabled." +#endif #endif /* _IDMR_H */ From 815b5bd5b18569917c3e04b9757511e6ed23b9f6 Mon Sep 17 00:00:00 2001 From: Shinya Kuribayashi Date: Fri, 17 Aug 2007 12:43:44 +0900 Subject: [PATCH 175/259] PCI_READ_VIA_DWORD_OP: Fix *val uninitialized bug This patch has been sent on: - 6 Jun 2007 Many users of PCI config read routines tend to ignore the function ret value, and are only concerned about the contents of *val. Based on this, pci_hose_read_config_{byte,word}_via_dword should initialize the *val on dword read error. Without this fix, for example, we'll go on scanning bus with vendor or header_type uninitialized. This brings many unnecessary config trials. Signed-off-by: Shinya Kuribayashi --- drivers/pci.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/pci.c b/drivers/pci.c index 41589192c..50ca6b0ba 100644 --- a/drivers/pci.c +++ b/drivers/pci.c @@ -82,8 +82,10 @@ int pci_hose_read_config_##size##_via_dword(struct pci_controller *hose,\ { \ u32 val32; \ \ - if (pci_hose_read_config_dword(hose, dev, offset & 0xfc, &val32) < 0)\ + if (pci_hose_read_config_dword(hose, dev, offset & 0xfc, &val32) < 0) { \ + *val = -1; \ return -1; \ + } \ \ *val = (val32 >> ((offset & (int)off_mask) * 8)); \ \ From 79f240f7ecc0506b43ac50d1ea405ff6540d4d57 Mon Sep 17 00:00:00 2001 From: Kim Phillips Date: Thu, 16 Aug 2007 22:52:39 -0500 Subject: [PATCH 176/259] lib_ppc: make board_add_ram_info weak platforms wishing to display RAM diagnostics in addition to size, can do so, on one line, in their own board_add_ram_info() implementation. this consequently eliminates CONFIG_ADD_RAM_INFO. Thanks to Stefan for the hint. Signed-off-by: Kim Phillips --- board/lwmon5/sdram.c | 2 -- board/netstal/hcu5/sdram.c | 2 -- cpu/ppc4xx/44x_spd_ddr2.c | 2 -- include/configs/TQM85xx.h | 1 - include/configs/hcu5.h | 1 - include/configs/katmai.h | 1 - include/configs/luan.h | 1 - include/configs/lwmon5.h | 1 - include/configs/p3mx.h | 1 - include/configs/yucca.h | 1 - lib_ppc/board.c | 11 ++++++----- 11 files changed, 6 insertions(+), 18 deletions(-) diff --git a/board/lwmon5/sdram.c b/board/lwmon5/sdram.c index f906b859a..d4547e24c 100644 --- a/board/lwmon5/sdram.c +++ b/board/lwmon5/sdram.c @@ -57,7 +57,6 @@ void dcbz_area(u32 start_address, u32 num_bytes); void dflush(void); -#ifdef CONFIG_ADD_RAM_INFO static u32 is_ecc_enabled(void) { u32 val; @@ -87,7 +86,6 @@ void board_add_ram_info(int use_default) val = DDR0_03_CASLAT_DECODE(val); printf(", CL%d)", val); } -#endif static int wait_for_dlllock(void) { diff --git a/board/netstal/hcu5/sdram.c b/board/netstal/hcu5/sdram.c index 40391958d..c5be8b925 100644 --- a/board/netstal/hcu5/sdram.c +++ b/board/netstal/hcu5/sdram.c @@ -70,7 +70,6 @@ void dflush(void); void program_tlb(u32 phys_addr, u32 virt_addr, u32 size, u32 tlb_word2_i_value); -#ifdef CONFIG_ADD_RAM_INFO void board_add_ram_info(int use_default) { PPC440_SYS_INFO board_cfg; @@ -99,7 +98,6 @@ void board_add_ram_info(int use_default) val = DDR0_03_CASLAT_DECODE(val); printf(", CL%d)", val); } -#endif /*-------------------------------------------------------------------- * wait_for_dlllock. diff --git a/cpu/ppc4xx/44x_spd_ddr2.c b/cpu/ppc4xx/44x_spd_ddr2.c index 18b90ba5a..67ba5bdef 100644 --- a/cpu/ppc4xx/44x_spd_ddr2.c +++ b/cpu/ppc4xx/44x_spd_ddr2.c @@ -621,7 +621,6 @@ static void get_spd_info(unsigned long *dimm_populated, } } -#ifdef CONFIG_ADD_RAM_INFO void board_add_ram_info(int use_default) { PPC440_SYS_INFO board_cfg; @@ -642,7 +641,6 @@ void board_add_ram_info(int use_default) val = (val & SDRAM_MMODE_DCL_MASK) >> 4; printf(", CL%d)", val); } -#endif /*------------------------------------------------------------------ * For the memory DIMMs installed, this routine verifies that they diff --git a/include/configs/TQM85xx.h b/include/configs/TQM85xx.h index cb9bf5492..9beb0bacf 100644 --- a/include/configs/TQM85xx.h +++ b/include/configs/TQM85xx.h @@ -94,7 +94,6 @@ */ #define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory */ #define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE -#define CONFIG_ADD_RAM_INFO 1 /* print additional info*/ #if defined(CONFIG_TQM8540) || defined(CONFIG_TQM8560) /* TQM8540 & 8560 need DLL-override */ diff --git a/include/configs/hcu5.h b/include/configs/hcu5.h index d0bf2516e..f95d78ec1 100644 --- a/include/configs/hcu5.h +++ b/include/configs/hcu5.h @@ -43,7 +43,6 @@ #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ #define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */ -#define CONFIG_ADD_RAM_INFO 1 /* Print additional info */ /*----------------------------------------------------------------------- * Base addresses -- Note these are effective addresses where the diff --git a/include/configs/katmai.h b/include/configs/katmai.h index 110ad44ee..b6d0f519a 100644 --- a/include/configs/katmai.h +++ b/include/configs/katmai.h @@ -42,7 +42,6 @@ #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ #define CONFIG_MISC_INIT_F 1 /* Use misc_init_f() */ -#define CONFIG_ADD_RAM_INFO 1 /* Print additional info */ #undef CONFIG_SHOW_BOOT_PROGRESS /*----------------------------------------------------------------------- diff --git a/include/configs/luan.h b/include/configs/luan.h index 26dbec92e..a09dd7473 100644 --- a/include/configs/luan.h +++ b/include/configs/luan.h @@ -39,7 +39,6 @@ #define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */ #define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */ -#define CONFIG_ADD_RAM_INFO 1 /* Print additional info */ /*----------------------------------------------------------------------- * Base addresses -- Note these are effective addresses where the diff --git a/include/configs/lwmon5.h b/include/configs/lwmon5.h index 604b7d12f..7116c49c7 100644 --- a/include/configs/lwmon5.h +++ b/include/configs/lwmon5.h @@ -35,7 +35,6 @@ #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ #define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */ -#define CONFIG_ADD_RAM_INFO 1 /* Print additional info */ /*----------------------------------------------------------------------- * Base addresses -- Note these are effective addresses where the diff --git a/include/configs/p3mx.h b/include/configs/p3mx.h index 8ae38cb27..bec442d98 100644 --- a/include/configs/p3mx.h +++ b/include/configs/p3mx.h @@ -60,7 +60,6 @@ #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ #define CONFIG_BOARD_EARLY_INIT_R 1 /* Call board_early_init_f */ #define CONFIG_MISC_INIT_R 1 /* Call misc_init_r() */ -#define CONFIG_ADD_RAM_INFO 1 /* Print additional info */ /*----------------------------------------------------------------------- * Base addresses -- Note these are effective addresses where the diff --git a/include/configs/yucca.h b/include/configs/yucca.h index 9c536fd12..906f046fa 100644 --- a/include/configs/yucca.h +++ b/include/configs/yucca.h @@ -46,7 +46,6 @@ #define EXTCLK_83 83333333 #define CONFIG_MISC_INIT_F 1 /* Use misc_init_f() */ -#define CONFIG_ADD_RAM_INFO 1 /* Print additional info */ #undef CONFIG_SHOW_BOOT_PROGRESS #undef CONFIG_STRESS diff --git a/lib_ppc/board.c b/lib_ppc/board.c index c87d46c3d..9aa67f93c 100644 --- a/lib_ppc/board.c +++ b/lib_ppc/board.c @@ -209,9 +209,12 @@ static int init_baudrate (void) /***********************************************************************/ -#ifdef CONFIG_ADD_RAM_INFO -void board_add_ram_info(int); -#endif +void __board_add_ram_info(int use_default) +{ + /* please define platform specific board_add_ram_info() */ +} +void board_add_ram_info(int) __attribute__((weak, alias("__board_add_ram_info"))); + static int init_func_ram (void) { @@ -224,9 +227,7 @@ static int init_func_ram (void) if ((gd->ram_size = initdram (board_type)) > 0) { print_size (gd->ram_size, ""); -#ifdef CONFIG_ADD_RAM_INFO board_add_ram_info(0); -#endif putc('\n'); return (0); } From 05675735ef77dc23b5e0eb782bad1ff477b55e86 Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Sat, 18 Aug 2007 22:00:38 +0200 Subject: [PATCH 177/259] Update CHANGELOG. --- CHANGELOG | 878 ++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 878 insertions(+) diff --git a/CHANGELOG b/CHANGELOG index da67d366c..2749d69c7 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -1,3 +1,432 @@ +commit 79f240f7ecc0506b43ac50d1ea405ff6540d4d57 +Author: Kim Phillips +Date: Thu Aug 16 22:52:39 2007 -0500 + + lib_ppc: make board_add_ram_info weak + + platforms wishing to display RAM diagnostics in addition to size, + can do so, on one line, in their own board_add_ram_info() + implementation. + + this consequently eliminates CONFIG_ADD_RAM_INFO. + + Thanks to Stefan for the hint. + + Signed-off-by: Kim Phillips + +commit 815b5bd5b18569917c3e04b9757511e6ed23b9f6 +Author: Shinya Kuribayashi +Date: Fri Aug 17 12:43:44 2007 +0900 + + PCI_READ_VIA_DWORD_OP: Fix *val uninitialized bug + + This patch has been sent on: + - 6 Jun 2007 + + Many users of PCI config read routines tend to ignore the function + ret value, and are only concerned about the contents of *val. Based + on this, pci_hose_read_config_{byte,word}_via_dword should initialize + the *val on dword read error. + + Without this fix, for example, we'll go on scanning bus with vendor or + header_type uninitialized. This brings many unnecessary config trials. + + Signed-off-by: Shinya Kuribayashi + +commit 26667b7fa05a8bf2fc65fb9f3230b02b1a10c367 +Author: Stefan Roese +Date: Sat Aug 18 14:37:52 2007 +0200 + + ColdFire: Fix some remaining problems with CFG_CMD_ + + Signed-off-by: Stefan Roese + +commit 8280f6a1c43247616b68224675188e5ccd124650 +Author: Stefan Roese +Date: Sat Aug 18 14:33:02 2007 +0200 + + Coding style cleanup + + Signed-off-by: Stefan Roese + +commit 4a442d3186b31893b4f77c6e82f63c4517a5224b +Author: TsiChungLiew +Date: Thu Aug 16 19:23:50 2007 -0500 + + ColdFire: Add M5235EVB Platform for MCF523x + + Signed-off-by: TsiChungLiew + +commit 4cc1cd5941827a04cf5c51a07fcc42e8945894aa +Author: Kim Phillips +Date: Fri Aug 17 09:30:00 2007 -0500 + + mpc83xx: fix typo in DDR2 programming + + introduced in the implement board_add_ram_info patch as I was cleaning out the + magic numbers. sorry. + + Signed-off-by: Kim Phillips + +commit e58fe95784d2514fc9c21028dc59f2b319a35d80 +Author: Kim Phillips +Date: Thu Aug 16 22:53:09 2007 -0500 + + mpc83xx: move freescale boards to boards/freescale + + includes build fixes. + + Signed-off-by: Kim Phillips + +commit 5aa4ad8d8e7e9468219990c7875d5fdc9e962f47 +Author: Kim Phillips +Date: Thu Aug 16 22:52:59 2007 -0500 + + mpc83xx: suppress unused variable 'val8' warning + + Signed-off-by: Kim Phillips + +commit bbea46f76f767b919070b4829bf34c86bd223248 +Author: Kim Phillips +Date: Thu Aug 16 22:52:48 2007 -0500 + + mpc83xx: implement board_add_ram_info + + add board_add_ram_info, to make memory diagnostic output more + consistent. u-boot banner output now looks like: + + DRAM: 256 MB (DDR1, 64-bit, ECC on) + + and for boards with SDRAM on the local bus, a line such as this is + added: + + SDRAM: 64 MB (local bus) + + also replaced some magic numbers with their equivalent define names. + + Signed-off-by: Kim Phillips + +commit 14778585d1389d86d5846efec29e5fce892680ce +Author: Tony Li +Date: Fri Aug 17 10:35:59 2007 +0800 + + mpc83xx: Split PIB init code from pci.c and add Qoc3 ATM card support + + The patch split the PIB init code from pci.c to a single file board/freescale/common/pq-mds-pib.c + And add Qoc3 ATM card support for MPC8360EMDS and MPC832XEMDS board. + + Signed-off-by Tony Li + +commit 8ae158cd87a4a25722b27835261b6ff0fa2aa6a7 +Author: TsiChungLiew +Date: Thu Aug 16 15:05:11 2007 -0500 + + ColdFire: Add M54455EVB for MCF5445x + + Signed-off-by: TsiChungLiew + +commit a1436a842654a8d3927d082a8ae9ee0a10da62d7 +Author: TsiChungLiew +Date: Thu Aug 16 13:20:50 2007 -0500 + + ColdFire: Add M5253EVBE platform for MCF52x2 + + Signed-off-by: TsiChungLiew + +commit a605aacd8324094199402816cc6d9124aba57b8d +Author: TsiChungLiew +Date: Thu Aug 16 05:04:31 2007 -0500 + + ColdFire: Add M5249EVB platform for MCF52x2 + + Signed-off-by: TsiChungLiew + +commit f28e1bd9daa6de5eb33ae4822bda6b008ccb4e9e +Author: TsiChungLiew +Date: Wed Aug 15 20:32:06 2007 -0500 + + ColdFire: Update Freescale MCF52x2 platforms + + Signed-off-by: TsiChungLiew + +commit 870470dbf6f4bb9864e0d97aeedbc17c167c6d1c +Author: TsiChungLiew +Date: Wed Aug 15 19:55:10 2007 -0500 + + ColdFire: Update EB+MCF-EV123 platform + + Signed-off-by: TsiChungLiew + +commit aa93d859d9b1fcd8eea52d51b06e86c38f72111b +Author: TsiChungLiew +Date: Wed Aug 15 19:46:38 2007 -0500 + + ColdFire: update TASREG platform for MCF52x2 + + Signed-off-by: TsiChungLiew + +commit a9505510bf56a9b5558248dd8b73ec9d9a1556a2 +Author: TsiChungLiew +Date: Wed Aug 15 19:45:51 2007 -0500 + + ColdFire: update r5200 platform for MCF52x2 + + Signed-off-by: TsiChungLiew + +commit 6cfd3c7bc813fb317ab7c0781f0d1874b1c0877c +Author: TsiChungLiew +Date: Wed Aug 15 19:43:20 2007 -0500 + + ColdFire: idmr platform MCF52x2 update + + Signed-off-by: TsiChungLiew + +commit 6706424d0bb851fb52af00cd1c3301e91ee7f2b0 +Author: TsiChungLiew +Date: Wed Aug 15 19:41:06 2007 -0500 + + ColdFire: cobra5272 platform for MCF52x2 update + + Signed-off-by: TsiChungLiew + +commit 56115665b4a64c10c01440c57749b265e0908fa4 +Author: TsiChungLiew +Date: Wed Aug 15 19:38:15 2007 -0500 + + ColdFire: MCF52x2 Header files update + + Signed-off-by: TsiChungLiew + +commit 83ec20bc4380eebddfde45da6e3a69a92d4db21d +Author: TsiChungLiew +Date: Wed Aug 15 19:21:21 2007 -0500 + + ColdFire: MCF52x2 update + + Signed-off-by: TsiChungLiew + +commit f52e78304dcc0ac459c0ea1fa5be275c7d1642cf +Author: TsiChungLiew +Date: Wed Aug 15 18:46:11 2007 -0500 + + ColdFire: MCF5329 update cache + + Signed-off-by: TsiChungLiew + +commit 7171977fb8fd77cfb6676953fa9a05789c450513 +Author: TsiChungLiew +Date: Wed Aug 15 15:40:20 2007 -0500 + + ColdFire: MCF5329 header file clean up + + Signed-off-by: TsiChungLiew + +commit ab77bc547ba561c25ea34457ed17aa0b2f7c2723 +Author: TsiChungLiew +Date: Wed Aug 15 15:39:17 2007 -0500 + + ColdFire: MCF5329 Update and cleanup + + Signed-off-by: TsiChungLiew + +commit 10327dc5541f947c0cf7e31fef86c4706169607a +Author: Andy Fleming +Date: Thu Aug 16 16:35:02 2007 -0500 + + Add CONFIG_HAS_ETH0 to all boards with TSEC + + The 85xx code now relies on CONFIG_HAS_ETH0 to determine whether + to update TSEC1's device-tree node, so we need to add it + to all the boards with TSECs. Do this for 83xx and 86xx, too, + since they will eventually do something similar. + + Signed-off-by: Andy Fleming + +commit d64ee908a1b525e5bb2b4cbeb5c449ad6a469666 +Author: Kumar Gala +Date: Thu Aug 16 15:05:04 2007 -0500 + + Update MPC8544 DS PCI memory map + + The PCIe bus that the ULI M1575 is connected to has no possible way of + needing more than the fixed amount of IO & Memory space needed by the ULI. + + So make it use far less IO & memory space and have it use the shared LAW. This + free's up a LAW for PCIe1 IO space. Also reduce the amount of IO space needed + by each bus. + + Signed-off-by: Kumar Gala + +commit ea5877e31ed63ade948fd1293895ec23fe01472e +Author: Kumar Gala +Date: Thu Aug 16 11:01:21 2007 -0500 + + Fix up some fdt issues on 8544DS + + It looks like we had a merge issue that duplicated a bit of code + in ft_board_setup. Also, we need to set CONFIG_HAS_ETH0 to get + the MAC address properly set in the device tree on boot for TSEC1 + + Signed-off-by: Kumar Gala + +commit 07bc20560cb9d3d186cca268c05c82762e8c55ad +Author: Niklaus Giger +Date: Thu Aug 16 15:16:03 2007 +0200 + + PPC4xx:HCU4/5 cleanup + + Minor cleanups to confirm to the u-boot coding style. + Some german expressions -> english. + HCU5 enforces a unique IP adress for a given slot in the rack. + + Signed-off-by: Niklaus Giger + +commit 1e6b07c64967c1eb2cd84faa4c32bf2a769bc8eb +Author: Niklaus Giger +Date: Thu Aug 16 15:16:02 2007 +0200 + + PPC4xx:HCU4/5 cleanup ecc/sdram init + + Make ecc initialisation robust, as DDR2-ECC errors may be generated + while zeroing the RAM. + + Return 16 bytes (a cacheline) less than the available memory, as the + board and/or PPC440EPx might have problems accessing the last bytes. + + Signed-off-by: Niklaus Giger + +commit d35b508a55508535b6e8445b718585d27df733d3 +Author: Kim Phillips +Date: Wed Aug 15 22:29:56 2007 -0500 + + fdt: suppress unused variable 'bd' warning + + Signed-off-by: Kim Phillips + +commit 82bd9ee77490588d4da785d75829ca63d0176baf +Author: Andy Fleming +Date: Wed Aug 15 20:06:50 2007 -0500 + + Fix warnings from of_data copy fix + + Forgot to cast of_flat_tree to ulong. + + Signed-off-by: Andy Fleming + +commit 7613afda77d5eec0f47d303025b0c661b70e4c73 +Author: Andy Fleming +Date: Wed Aug 15 20:03:44 2007 -0500 + + Don't wait for disconnected TSECs + + The TSEC driver's PHY code waits a long time for autonegotiation to + complete, even if the link is down. The PHY knows the link is + down or up before autonegotiation completes, so we can short-circuit + the process if the link is down. + + Signed-off-by: Andy Fleming + +commit b96c83d4ae475a70ef2635cd0e748174c44c8601 +Author: Andy Fleming +Date: Wed Aug 15 20:03:34 2007 -0500 + + Fix numerous bugs in the 8568 UEC support + + Actually, fixed a large bug in the UEC for *all* platforms. + How did this ever work? + + uec_init() did not follow the spec for eth_init(), and returned + 0 on success. Switch it to return the link like tsec_init() + (and 0 on error) + + The immap for the 8568 was defined based on MPC8568, rather than + CONFIG_MPC8568 + + CONFIG_QE was off + + CONFIG_ETHPRIME was set to "Freescale GETH". Now is "FSL UEC0" + + Fixed a comment about the ranges for CONFIG_ETHPRIME if TSEC_ENET is + enabled + + Signed-off-by: Andy Fleming + +commit 3a79013e2adda53332dfd0b511066a805e929a9d +Author: Andy Fleming +Date: Wed Aug 15 20:03:25 2007 -0500 + + Define tsec flag values in config files + + The tsec_info structure and array has a "flags" field for each + ethernet controller. This field is the only reason there are + settings. Switch to defining TSECn_FLAGS for each controller + in the config header, and we can greatly simplify the array, and + also simplify the addition of future boards. + + Signed-off-by: Andy Fleming + +commit ec7238229507e7f47533a611ea8c53319d234cf3 +Author: Andy Fleming +Date: Wed Aug 15 20:03:13 2007 -0500 + + Add support for building all boards with a TSEC + + Changes to the TSEC driver affect almost all 83xx, 85xx, and 86xx boards. + Now we can do a MAKEALL test on all of them! + + Signed-off-by: Andy Fleming + +commit 10aaf716cb0dc6614df54ef78bed5144afd23ef8 +Author: Andy Fleming +Date: Wed Aug 15 17:30:56 2007 -0500 + + Fix of_data copying for CONFIG_OF_FLAT_TREE-using boards + + The fix, "Fix where the #ifdef CFG_BOOTMAPSZ is placed" + neglected to *also* put the code inside the similar #ifdef + for CONFIG_OF_FLAT_TREE. + + Signed-off-by: Andy Fleming + +commit 78f9fef7f406078c8bf7191e665a73f795157746 +Author: Scott Wood +Date: Wed Aug 15 15:46:46 2007 -0500 + + mpc885ads: Don't define CONFIG_BZIP2. + + bzip2 requires a significant chunk of malloc space, and there isn't + enough room on mpc885ads (with only 8MB RAM) for both bzip2's malloc area + and a downloaded image at 0x400000. + + Signed-off-by: Scott Wood + +commit 002275a3ed8b114885f6702d6d544d0780dfe689 +Author: Michal Simek +Date: Thu Aug 16 08:54:10 2007 +0200 + + Bios emulator - fix microblaze toolchain problem + + microblaze CPU have problem with bios_emulator code. + Microblaze toolchain doesn't support PRAGMA PACK. + + Signed-off-by: Michal Simek + +commit a5a38f4fd7e5366d706ff6a985f9b6715ddbc98b +Author: Wolfgang Denk +Date: Thu Aug 16 11:51:04 2007 +0200 + + Minor Coding Style fix; Update CHANGELOG file. + + Signed-off-by: Wolfgang Denk + +commit 8fb6e80c06849e3013ac5c9350d8ed9e52967991 +Author: Stefan Roese +Date: Thu Aug 16 11:21:49 2007 +0200 + + ppc4xx: Remove #warning in esd auto_update.c + + Signed-off-by: Stefan Roese + commit 2d78074d2e806edc380c1464eb9e5df335ece65e Author: Stefan Roese Date: Fri Jun 22 17:32:28 2007 +0200 @@ -11,6 +440,101 @@ Date: Fri Jun 22 17:32:28 2007 +0200 Signed-off-by: Reinhard Arlt Signed-off-by: Stefan Roese +commit 9de469bd960cc1870bb40d6672ed42726b8b50d7 +Author: Stefan Roese +Date: Thu Aug 16 10:18:33 2007 +0200 + + ppc4xx: Only enable POST FPU test on Sequoia and not Rainier + + Signed-off-by: Stefan Roese + +commit 6da0c5bd4a53e40eb4f7eb72a4c051ecabad783c +Author: Stefan Roese +Date: Thu Aug 16 09:54:51 2007 +0200 + + Add missing rainier (PPC440GRx) target to MAKEALL and MAINTAINERs files + + Signed-off-by: Stefan Roese + +commit 02ba7022f62bb75908296c58c63866e1d294b69a +Author: Stefan Roese +Date: Thu Aug 16 09:52:29 2007 +0200 + + ppc4xx: Update Sequoia/Rainier bootstrap command + + As suggested by David Mitchell, here an update for the Sequoia/Rainier + bootstrap command. + + Signed-off-by: Stefan Roese + +commit 35cc4e4823668e8745854899cfaedd4489beb0ef +Author: Kim Phillips +Date: Wed Aug 15 22:30:39 2007 -0500 + + mpc83xx: enable libfdt by default on freescale boards + + this enables libfdt code by default for the + freescale mpc8313erdb, mpc832xemds, mpc8349emds, + mpc8349itx and gp boards. + + Signed-off-by: Kim Phillips + +commit 3fde9e8b22cfbd7af489214758f9839a206576cb +Author: Kim Phillips +Date: Wed Aug 15 22:30:33 2007 -0500 + + mpc83xx: migrate remaining freescale boards to libfdt + + this adds libfdt support code for the freescale + mpc8313erdb, mpc832xemds, mpc8349emds, mpc8349itx, + and gp boards. + + Boards remain compatible with OF_FLAT_TREE. + + Signed-off-by: Kim Phillips + +commit 6a16e0dfcc4119b46adb1dce2d6c8fb3c5d108e1 +Author: Kim Phillips +Date: Wed Aug 15 22:30:26 2007 -0500 + + mpc83xx: move common /memory node update mechanism to cpu.c + + also adds common prototypes to include/common.h. + + Signed-off-by: Kim Phillips + +commit 8f9e0e9f339aee4ce31a338d5f27356eb5457f85 +Author: Kim Phillips +Date: Wed Aug 15 22:30:19 2007 -0500 + + mpc83xx: remaining 8360 libfdt fixes + + PCI clocks and QE frequencies weren't being updated, and the core clock + was being updated incorrectly. This patch also adds a /memory node if + it doesn't already exist prior to update. + + plus some cosmetic trimming to single line comments. + + Signed-off-by: Kim Phillips + +commit f4b2ac5ed9aaff9920d487bff8a59696c083a524 +Author: Kim Phillips +Date: Wed Aug 15 22:30:12 2007 -0500 + + mpc83xx: fix UEC2->1 typo in libfdt setup code + + Signed-off-by: Kim Phillips + +commit 19fa1c35368484d4ed10ddce8a7793c21862e3a3 +Author: Kim Phillips +Date: Wed Aug 15 22:30:05 2007 -0500 + + mpc83xx: add MAINTAINER and MAKEALL entries for the mpc8323erdb + + and reorder the existing 83xx maintainers alpha. + + Signed-off-by: Kim Phillips + commit 30b52df9e906bf0e465916c2c6bb5192b438e0b8 Author: Jon Loeliger Date: Wed Aug 15 11:55:35 2007 -0500 @@ -56,6 +580,14 @@ Date: Wed Aug 15 11:13:15 2007 -0400 Signed-off-by: Gerald Van Baren +commit 0e19209767194a97cec6d93dba9e64d1da8d548e +Author: Niklaus Giger +Date: Wed Aug 15 12:14:23 2007 +0200 + + PPC4xx:HCU4/5-Board fix compile warning + + Signed-off-by: Niklaus Giger + commit 594e79838ce5078a90d0c27abb2b2d61d5f8e8a7 Author: Ed Swarthout Date: Tue Aug 14 14:06:45 2007 -0500 @@ -1394,6 +1926,78 @@ Date: Thu Aug 9 09:08:18 2007 -0500 Signed-off by: Joe Hamman +commit 3ba4c2d68f6541db4677b4aea12071f56e6ff6e6 +Author: Stefan Roese +Date: Wed Aug 8 09:54:26 2007 +0200 + + Coding style cleanup + + Signed-off-by: Stefan Roese + +commit a41de1f0d373e09c782dea558385a06247111ba5 +Author: TsiChungLiew +Date: Sun Aug 5 05:15:18 2007 -0500 + + Port enabled for I2C signals and chipselects port configuration. + + Signed-off-by: TsiChungLiew + +commit 1a33ce65a4c51a69190dd8c408f9e1c62a66e94f +Author: TsiChungLiew +Date: Sun Aug 5 04:31:18 2007 -0500 + + Added NAND support + + Signed-off-by: TsiChungLiew + +commit eaf9e447beb3e498818ef8ad0b8c1597cd506149 +Author: TsiChungLiew +Date: Sun Aug 5 04:11:20 2007 -0500 + + Added I2C support + + Signed-off-by: TsiChungLiew + +commit 99c03c175d2689093176facf17c58ce2cb320001 +Author: TsiChungLiew +Date: Sun Aug 5 03:58:52 2007 -0500 + + Changed CFG_CLK to gd->bus_clk for CFG_TIMER_PRESCALER. Added DECLARE_GLOBAL_DATA_PTR for time.c + + Signed-off-by: TsiChungLiew + +commit 8d1d66af54d305de29d0bbf4aa8c9e6375f7f731 +Author: TsiChungLiew +Date: Sun Aug 5 03:55:21 2007 -0500 + + Added uart_gpio_conf() in serial_init(), seperated uart port configuration from cpu_init() to uart_gpio_conf() + + Signed-off-by: TsiChungLiew + +commit 6fde84a44b7e575ea80fe0e2d5be3b6f73d1e630 +Author: TsiChungLiew +Date: Sun Aug 5 03:43:30 2007 -0500 + + Moved sync() from board file to include/asm-m68k/io.h + + Signed-off-by: TsiChungLiew + +commit 9e737d8476e7d6a596d16caaf6a3853a9a1190a2 +Author: TsiChungLiew +Date: Sun Aug 5 03:30:44 2007 -0500 + + Declared attributes of void __mii_init(void) as an alias for int mii_init(void) + + Signed-off-by: TsiChungLiew + +commit 9998bd37ead85e93953559720710d3b0685c81e6 +Author: TsiChungLiew +Date: Sun Aug 5 03:19:10 2007 -0500 + + Renamed CONFIG_MCFSERIAL to CONFIG_MCFUART + + Signed-off-by: TsiChungLiew + commit 7c4c3722a38d40b0cf537ddae72b04f4088b190c Author: Jason Jin Date: Tue Aug 7 16:17:06 2007 +0800 @@ -1775,6 +2379,14 @@ Date: Thu Jul 19 17:12:28 2007 +0200 Signed-off-by: Rafal Jaworowski +commit c883f6ea32dce91f07670b3aafecf6c99b1e5341 +Author: Stefan Roese +Date: Mon Jul 16 13:11:12 2007 +0200 + + Coding style cleanup + + Signed-off-by: Stefan Roese + commit 8848ec858f74ed6dab06fb6d5ddc933e0a1328bf Author: Stefan Roese Date: Mon Jul 16 10:02:12 2007 +0200 @@ -2057,6 +2669,252 @@ Date: Sun Jul 8 13:44:27 2007 +0200 Signed-off-by: Stefan Roese +commit 0dca874db62718e41253659e60f3a1de7eb418ce +Author: TsiChung +Date: Tue Jul 10 15:45:43 2007 -0500 + + Cache update and added CFG_UNIFY_CACHE + + Enabled cache in cpu_init_f() for faster flash to mem allocation. Updated cache handling in start.S. Applied cache invalidate in fec_send() and fec_recv(). Added CFG_UNIFY_CACHE for CF V3 only. + + Signed-off-by: TsiChung + +commit 52b017604a8f4d4a795880ef6e7861d7f2f1b005 +Author: TsiChungLiew +Date: Thu Jul 5 23:36:16 2007 -0500 + + Update header file. Include dtimer_intr_setup(). Changed timer divider to global define. + + Include immap.h and timer.h. Moved dtimer interrupt setup to dtimer_intr_setup() from cpu/mcf532x/interrupts.c. Changed (CFG_CLK /1000000) -1 << 8 to CFG_TIMER_PRESCALER + + Signed-off-by: TsiChungLiew + +commit 5cdc07c7ef8f08ea55d3c47ed9221d91aa6d5fac +Author: TsiChungLiew +Date: Thu Jul 5 23:31:25 2007 -0500 + + Update header files + + Include immap.h and renamed mcfrtc.h to rtc.h + + Signed-off-by: TsiChungLiew + +commit 2870e98ac8e5553e9187b12a47e5f46babb53990 +Author: TsiChungLiew +Date: Thu Jul 5 23:29:21 2007 -0500 + + Add mcffec_initialize() + + Added mcffec_initialize() in eth_initialize() + + Signed-off-by: TsiChungLiew + +commit 45a25bfd0c52f8a3fa137216bc94d32f90bedc5d +Author: TsiChungLiew +Date: Thu Jul 5 23:27:40 2007 -0500 + + Update header file and clean up + + Include immap.h + + Signed-off-by: TsiChungLiew + +commit 0cee9c66318602c856a899ae5fa7579ccba6443a +Author: TsiChungLiew +Date: Thu Jul 5 23:23:15 2007 -0500 + + New uart structure and defines + + Seperated from mcfuart.h + + Signed-off-by: TsiChungLiew + +commit a90e79de8d99e9c9d69d60bfff9f24c337165900 +Author: TsiChungLiew +Date: Thu Jul 5 23:22:31 2007 -0500 + + New timer structure and defines + + Seperated from mcftimer.h + + Signed-off-by: TsiChungLiew + +commit e04acb2eba4782489417240eff76e20e176aec10 +Author: TsiChungLiew +Date: Thu Jul 5 23:21:09 2007 -0500 + + Rename mcfrtc to rtc + + Since it is already in m68k folder, un-necessary to pad mcf. Replaced immap_5329.h and m5329.h to immap.h + + Signed-off-by: TsiChungLiew + +commit 2bd806fe4fc23958b8f78778199e7a6e3f8f6ad5 +Author: TsiChungLiew +Date: Thu Jul 5 23:17:36 2007 -0500 + + Rename mcfserial.c. Update include header + + Renamed mcfserial.c to mcfuart.c. Modified Makefile for mcfuart.o from mcfserial.o. Replace immap_5329.h and m5329.h to immap.h + + Signed-off-by: TsiChungLiew + +commit f2208fbc2eb9de3f4285bfaa021c6ebae16c9b0e +Author: TsiChungLiew +Date: Thu Jul 5 23:13:58 2007 -0500 + + Header file update, clean up and cache handling + + Replaced immap_5329.h and m5329.h with immap.h. Included cache_invalid. + + Signed-off-by: TsiChungLiew + +commit 2e3f25ae9082daa9f5d181db45dfbc2e52ce0f97 +Author: TsiChungLiew +Date: Thu Jul 5 23:10:40 2007 -0500 + + Create interrupts.c and modify Makefile + + interrupt_init() and dtimer_intr_setup() are placed in interrupts.c. Added interrupts.o to Makefile + + Signed-off-by: TsiChungLiew + +commit ddd104f1ed655eda50c06ba636237a83ed943f34 +Author: TsiChungLiew +Date: Thu Jul 5 23:06:55 2007 -0500 + + Enable Icache + + Signed-off-by: TsiChungLiew + +commit b9bf3de377b2bae70c983c9b97feae914999e735 +Author: TsiChungLiew +Date: Thu Jul 5 23:05:31 2007 -0500 + + Update header file and some clean up + + Replaced immap_5329.h and m5329.h with immap.h. Removed whitespaces. + + Signed-off-by: TsiChungLiew + +commit 84a015b52ec820a5ae173717d78516de731c89c2 +Author: TsiChungLiew +Date: Thu Jul 5 23:03:28 2007 -0500 + + Update header file and enable icache + + Replaced immap_5329.h and m5329.h with immap.h. Enabled icache_enable() in cpu_init_r(). + + Signed-off-by: TsiChungLiew + +commit 7a17e759c7a8b58e910daf54df611e94fc8ca074 +Author: TsiChungLiew +Date: Thu Jul 5 23:01:22 2007 -0500 + + Update header file and removed interrupt_init() + + Replace immap_5329.h and m5329.h with immap.h. Removed interrupt_init() and placed it in interrupts.c + + Signed-off-by: TsiChungLiew + +commit 3b635492c95bd0d6e08f93f699821cba1f602a64 +Author: TsiChungLiew +Date: Thu Jul 5 22:57:46 2007 -0500 + + Update for flash.o and mii.o + + Removed flash.o and added mii.o + + Signed-off-by: TsiChungLiew + +commit c5ded275d839e4ff79f41718d50a835d989f57bc +Author: TsiChungLiew +Date: Thu Jul 5 22:56:19 2007 -0500 + + MII functions calls. + + Signed-off-by: TsiChungLiew + +commit 427c814104560e29bda14955c67703245aaaa5b4 +Author: TsiChungLiew +Date: Thu Jul 5 22:54:42 2007 -0500 + + Removed MII functions and replaced immap_5329.h and m5329.h with immap.h. + + The removed MII routines will be placed in mii.c. + + Signed-off-by: TsiChungLiew + +commit 01a793fda09c63df5a496f09dc1c7cb26e6751a2 +Author: TsiChungLiew +Date: Thu Jul 5 22:51:05 2007 -0500 + + Duplicate code + + There is a Common Flash Interface Driver existed. To use the CFI driver, define CFG_FLASH_CFI in configuration file. + + Signed-off-by: TsiChungLiew + +commit 2744354a8437b8f78db178e30660215688bff570 +Author: TsiChungLiew +Date: Thu Jul 5 22:46:38 2007 -0500 + + Seperate old structure defines and new structure defines + + Removed new uart structure and defines to uart.h + + Signed-off-by: TsiChungLiew + +commit 2bd58608dbcff8890ca9a0c59e861ac24f8bb230 +Author: TsiChungLiew +Date: Thu Jul 5 22:45:01 2007 -0500 + + Seperate old structure defines and new structure defines + + New timer structure and defines will move to new timer.h + + Signed-off-by: TsiChungLiew + +commit 8cd5cd6de4ff92e03978338ed7aeb3ce7b7b9784 +Author: TsiChungLiew +Date: Thu Jul 5 22:42:23 2007 -0500 + + Clean up + + Removed whitespace + + Signed-off-by: TsiChungLiew + +commit 514871f565dd8bd1121e4a3ac1665a790e20b8f2 +Author: TsiChungLiew +Date: Thu Jul 5 22:41:24 2007 -0500 + + Clean up + + Replaced whitespace with tabs + + Signed-off-by: TsiChungLiew + +commit 48dbfeabc7afffe30609a4489f10c22cb67ef7dd +Author: TsiChungLiew +Date: Thu Jul 5 22:39:07 2007 -0500 + + Create new header file and move peripherals base address from configs file to new header file. + + Create new header file to include immap_5xxx.h and m5xxx.h and to share among drivers without update in driver file each processor is added. Moved peripherals base address and defines from configs file to immap.h. + + Signed-off-by: TsiChungLiew + +commit be296e31c4411f96d9cb3d2afc8fcb006867abfa +Author: TsiChungLiew +Date: Thu Jul 5 22:24:58 2007 -0500 + + Revert file mode + + Changed MAKEALL file mode to executable, removed executable file mode from Makefile + + Signed-off-by: TsiChungLiew + commit b3aff0cb9ecf236d7e8c93761dd1dadf6837a582 Author: Jon Loeliger Date: Tue Jul 10 11:19:50 2007 -0500 @@ -3759,6 +4617,26 @@ Date: Tue Jun 19 16:40:58 2007 +0200 Signed-off-by: Stefan Roese +commit 8e585f02f82c17cc66cd229dbf0fd3066bbbf658 +Author: TsiChung Liew +Date: Mon Jun 18 13:50:13 2007 -0500 + + Added M5329AFEE and M5329BFEE Platforms + + Added board/freescale/m5329evb, cpu/mcf532x, drivers/net, + drivers/serial, immap_5329.h, m5329.h, mcfrtc.h, + include/configs/M5329EVB.h, lib_m68k/interrupts.c, and + rtc/mcfrtc.c + + Modified CREDITS, MAKEFILE, Makefile, README, common/cmd_bdinfo.c, + common/cmd_mii.c, include/asm-m68k/byteorder.h, include/asm-m68k/fec.h, + include/asm-m68k/io.h, include/asm-m68k/mcftimer.h, + include/asm-m68k/mcfuart.h, include/asm-m68k/ptrace.h, + include/asm-m68k/u-boot.h, lib_m68k/Makefile, lib_m68k/board.c, + lib_m68k/time.c, net/eth.c and rtc/Makefile + + Signed-off-by: TsiChung Liew + commit e73846b7cf1e29ae635bf9bb5570269663df2ee5 Author: Stefan Roese Date: Fri Jun 15 11:33:41 2007 +0200 From 3e66c078003607a7d1d214c15a5f262bc1b4032f Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Sun, 19 Aug 2007 10:27:34 +0200 Subject: [PATCH 178/259] Fix some build errors. Signed-off-by: Wolfgang Denk --- drivers/net/mcffec.c | 4 ++-- drivers/serial/mcfuart.c | 4 +++- rtc/mcfrtc.c | 10 +++++----- 3 files changed, 10 insertions(+), 8 deletions(-) diff --git a/drivers/net/mcffec.c b/drivers/net/mcffec.c index 2e0ddeb77..3b812585b 100644 --- a/drivers/net/mcffec.c +++ b/drivers/net/mcffec.c @@ -27,15 +27,15 @@ #include #include +#ifdef CONFIG_MCFFEC + #include #include #include -#include #include #include -#ifdef CONFIG_MCFFEC #undef ET_DEBUG #undef MII_DEBUG diff --git a/drivers/serial/mcfuart.c b/drivers/serial/mcfuart.c index bc7077de7..88f3eb10a 100644 --- a/drivers/serial/mcfuart.c +++ b/drivers/serial/mcfuart.c @@ -28,12 +28,14 @@ */ #include + +#ifdef CONFIG_MCFUART + #include #include DECLARE_GLOBAL_DATA_PTR; -#ifdef CONFIG_MCFUART extern void uart_port_conf(void); int serial_init(void) diff --git a/rtc/mcfrtc.c b/rtc/mcfrtc.c index 76bb5107f..27386e586 100644 --- a/rtc/mcfrtc.c +++ b/rtc/mcfrtc.c @@ -22,14 +22,14 @@ */ #include -#include -#include - -#include -#include #if defined(CONFIG_MCFRTC) && defined(CONFIG_CMD_DATE) +#include +#include +#include +#include + #undef RTC_DEBUG #ifndef CFG_MCFRTC_BASE From 3ad63878737a5a2b1e60825bf0a7d601d7a695e7 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Tue, 21 Aug 2007 16:27:57 +0200 Subject: [PATCH 179/259] ppc4xx: Add matrix kbd support to lwmon5 board (440EPx based) This patch adds support for the matrix keyboard on the lwmon5 board. Since the implementation in the dsPCI is kind of compatible with the "old" lwmon board, most of the code is copied from the lwmon board directory. Signed-off-by: Stefan Roese --- board/lwmon5/Makefile | 2 +- board/lwmon5/kbd.c | 458 ++++++++++++++++++++++++++++++++++ board/lwmon5/lwmon5.c | 19 +- include/asm-ppc/global_data.h | 2 +- include/configs/lwmon5.h | 14 +- 5 files changed, 478 insertions(+), 17 deletions(-) create mode 100644 board/lwmon5/kbd.c diff --git a/board/lwmon5/Makefile b/board/lwmon5/Makefile index 06ef7f933..2a9357146 100644 --- a/board/lwmon5/Makefile +++ b/board/lwmon5/Makefile @@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a -COBJS = $(BOARD).o sdram.o +COBJS = $(BOARD).o kbd.o sdram.o SOBJS = init.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) diff --git a/board/lwmon5/kbd.c b/board/lwmon5/kbd.c new file mode 100644 index 000000000..1e5349a6e --- /dev/null +++ b/board/lwmon5/kbd.c @@ -0,0 +1,458 @@ +/* + * (C) Copyright 2007 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * (C) Copyright 2001, 2002 + * DENX Software Engineering + * Wolfgang Denk, wd@denx.de + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* define DEBUG for debugging output (obviously ;-)) */ +#if 0 +#define DEBUG +#endif + +#include +#include +#include +#include +#include +#include + +#include +#include /* for strdup */ + +DECLARE_GLOBAL_DATA_PTR; + +static void kbd_init (void); +static int compare_magic (uchar *kbd_data, uchar *str); + +/*--------------------- Local macros and constants --------------------*/ +#define _NOT_USED_ 0xFFFFFFFF + +/*------------------------- Keyboard controller -----------------------*/ +/* command codes */ +#define KEYBD_CMD_READ_KEYS 0x01 +#define KEYBD_CMD_READ_VERSION 0x02 +#define KEYBD_CMD_READ_STATUS 0x03 +#define KEYBD_CMD_RESET_ERRORS 0x10 + +/* status codes */ +#define KEYBD_STATUS_MASK 0x3F +#define KEYBD_STATUS_H_RESET 0x20 +#define KEYBD_STATUS_BROWNOUT 0x10 +#define KEYBD_STATUS_WD_RESET 0x08 +#define KEYBD_STATUS_OVERLOAD 0x04 +#define KEYBD_STATUS_ILLEGAL_WR 0x02 +#define KEYBD_STATUS_ILLEGAL_RD 0x01 + +/* Number of bytes returned from Keyboard Controller */ +#define KEYBD_VERSIONLEN 2 /* version information */ + +/* + * This is different from the "old" lwmon dsPIC kbd controller + * implementation. Now the controller still answers with 9 bytes, + * but the last 3 bytes are always "0x06 0x07 0x08". So we just + * set the length to compare to 6 instead of 9. + */ +#define KEYBD_DATALEN 6 /* normal key scan data */ + +/* maximum number of "magic" key codes that can be assigned */ + +static uchar kbd_addr = CFG_I2C_KEYBD_ADDR; + +static uchar *key_match (uchar *); + +#define KEYBD_SET_DEBUGMODE '#' /* Magic key to enable debug output */ + +/*********************************************************************** +F* Function: int board_postclk_init (void) P*A*Z* + * +P* Parameters: none +P* +P* Returnvalue: int +P* - 0 is always returned. + * +Z* Intention: This function is the board_postclk_init() method implementation +Z* for the lwmon board. + * + ***********************************************************************/ +int board_postclk_init (void) +{ + kbd_init(); + + return (0); +} + +static void kbd_init (void) +{ + uchar kbd_data[KEYBD_DATALEN]; + uchar tmp_data[KEYBD_DATALEN]; + uchar val, errcd; + int i; + + i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE); + + gd->kbd_status = 0; + + /* Forced by PIC. Delays <= 175us loose */ + udelay(1000); + + /* Read initial keyboard error code */ + val = KEYBD_CMD_READ_STATUS; + i2c_write (kbd_addr, 0, 0, &val, 1); + i2c_read (kbd_addr, 0, 0, &errcd, 1); + /* clear unused bits */ + errcd &= KEYBD_STATUS_MASK; + /* clear "irrelevant" bits. Recommended by Martin Rajek, LWN */ + errcd &= ~(KEYBD_STATUS_H_RESET|KEYBD_STATUS_BROWNOUT); + if (errcd) { + gd->kbd_status |= errcd << 8; + } + /* Reset error code and verify */ + val = KEYBD_CMD_RESET_ERRORS; + i2c_write (kbd_addr, 0, 0, &val, 1); + udelay(1000); /* delay NEEDED by keyboard PIC !!! */ + + val = KEYBD_CMD_READ_STATUS; + i2c_write (kbd_addr, 0, 0, &val, 1); + i2c_read (kbd_addr, 0, 0, &val, 1); + + val &= KEYBD_STATUS_MASK; /* clear unused bits */ + if (val) { /* permanent error, report it */ + gd->kbd_status |= val; + return; + } + + /* + * Read current keyboard state. + * + * After the error reset it may take some time before the + * keyboard PIC picks up a valid keyboard scan - the total + * scan time is approx. 1.6 ms (information by Martin Rajek, + * 28 Sep 2002). We read a couple of times for the keyboard + * to stabilize, using a big enough delay. + * 10 times should be enough. If the data is still changing, + * we use what we get :-( + */ + + memset (tmp_data, 0xFF, KEYBD_DATALEN); /* impossible value */ + for (i=0; i<10; ++i) { + val = KEYBD_CMD_READ_KEYS; + i2c_write (kbd_addr, 0, 0, &val, 1); + i2c_read (kbd_addr, 0, 0, kbd_data, KEYBD_DATALEN); + + if (memcmp(kbd_data, tmp_data, KEYBD_DATALEN) == 0) { + /* consistent state, done */ + break; + } + /* remeber last state, delay, and retry */ + memcpy (tmp_data, kbd_data, KEYBD_DATALEN); + udelay (5000); + } +} + +/*********************************************************************** +F* Function: int misc_init_r (void) P*A*Z* + * +P* Parameters: none +P* +P* Returnvalue: int +P* - 0 is always returned, even in the case of a keyboard +P* error. + * +Z* Intention: This function is the misc_init_r() method implementation +Z* for the lwmon board. +Z* The keyboard controller is initialized and the result +Z* of a read copied to the environment variable "keybd". +Z* If KEYBD_SET_DEBUGMODE is defined, a check is made for +Z* this key, and if found display to the LCD will be enabled. +Z* The keys in "keybd" are checked against the magic +Z* keycommands defined in the environment. +Z* See also key_match(). + * +D* Design: wd@denx.de +C* Coding: wd@denx.de +V* Verification: dzu@denx.de + ***********************************************************************/ +int misc_init_r_kbd (void) +{ + uchar kbd_data[KEYBD_DATALEN]; + char keybd_env[2 * KEYBD_DATALEN + 1]; + uchar kbd_init_status = gd->kbd_status >> 8; + uchar kbd_status = gd->kbd_status; + uchar val; + char *str; + int i; + + if (kbd_init_status) { + printf ("KEYBD: Error %02X\n", kbd_init_status); + } + if (kbd_status) { /* permanent error, report it */ + printf ("*** Keyboard error code %02X ***\n", kbd_status); + sprintf (keybd_env, "%02X", kbd_status); + setenv ("keybd", keybd_env); + return 0; + } + + /* + * Now we know that we have a working keyboard, so disable + * all output to the LCD except when a key press is detected. + */ + + if ((console_assign (stdout, "serial") < 0) || + (console_assign (stderr, "serial") < 0)) { + printf ("Can't assign serial port as output device\n"); + } + + /* Read Version */ + val = KEYBD_CMD_READ_VERSION; + i2c_write (kbd_addr, 0, 0, &val, 1); + i2c_read (kbd_addr, 0, 0, kbd_data, KEYBD_VERSIONLEN); + printf ("KEYBD: Version %d.%d\n", kbd_data[0], kbd_data[1]); + + /* Read current keyboard state */ + val = KEYBD_CMD_READ_KEYS; + i2c_write (kbd_addr, 0, 0, &val, 1); + i2c_read (kbd_addr, 0, 0, kbd_data, KEYBD_DATALEN); + + for (i = 0; i < KEYBD_DATALEN; ++i) { + sprintf (keybd_env + i + i, "%02X", kbd_data[i]); + } + setenv ("keybd", keybd_env); + + str = strdup ((char *)key_match (kbd_data)); /* decode keys */ +#ifdef KEYBD_SET_DEBUGMODE + if (kbd_data[0] == KEYBD_SET_DEBUGMODE) { /* set debug mode */ + if ((console_assign (stdout, "lcd") < 0) || + (console_assign (stderr, "lcd") < 0)) { + printf ("Can't assign LCD display as output device\n"); + } + } +#endif /* KEYBD_SET_DEBUGMODE */ +#ifdef CONFIG_PREBOOT /* automatically configure "preboot" command on key match */ + setenv ("preboot", str); /* set or delete definition */ +#endif /* CONFIG_PREBOOT */ + if (str != NULL) { + free (str); + } + return (0); +} + +#ifdef CONFIG_PREBOOT + +static uchar kbd_magic_prefix[] = "key_magic"; +static uchar kbd_command_prefix[] = "key_cmd"; + +static int compare_magic (uchar *kbd_data, uchar *str) +{ + uchar compare[KEYBD_DATALEN-1]; + char *nxt; + int i; + + /* Don't include modifier byte */ + memcpy (compare, kbd_data+1, KEYBD_DATALEN-1); + + for (; str != NULL; str = (*nxt) ? (uchar *)(nxt+1) : (uchar *)nxt) { + uchar c; + int k; + + c = (uchar) simple_strtoul ((char *)str, (char **) (&nxt), 16); + + if (str == (uchar *)nxt) { /* invalid character */ + break; + } + + /* + * Check if this key matches the input. + * Set matches to zero, so they match only once + * and we can find duplicates or extra keys + */ + for (k = 0; k < sizeof(compare); ++k) { + if (compare[k] == '\0') /* only non-zero entries */ + continue; + if (c == compare[k]) { /* found matching key */ + compare[k] = '\0'; + break; + } + } + if (k == sizeof(compare)) { + return -1; /* unmatched key */ + } + } + + /* + * A full match leaves no keys in the `compare' array, + */ + for (i = 0; i < sizeof(compare); ++i) { + if (compare[i]) + { + return -1; + } + } + + return 0; +} + +/*********************************************************************** +F* Function: static uchar *key_match (uchar *kbd_data) P*A*Z* + * +P* Parameters: uchar *kbd_data +P* - The keys to match against our magic definitions +P* +P* Returnvalue: uchar * +P* - != NULL: Pointer to the corresponding command(s) +P* NULL: No magic is about to happen + * +Z* Intention: Check if pressed key(s) match magic sequence, +Z* and return the command string associated with that key(s). +Z* +Z* If no key press was decoded, NULL is returned. +Z* +Z* Note: the first character of the argument will be +Z* overwritten with the "magic charcter code" of the +Z* decoded key(s), or '\0'. +Z* +Z* Note: the string points to static environment data +Z* and must be saved before you call any function that +Z* modifies the environment. + * +D* Design: wd@denx.de +C* Coding: wd@denx.de +V* Verification: dzu@denx.de + ***********************************************************************/ +static uchar *key_match (uchar *kbd_data) +{ + char magic[sizeof (kbd_magic_prefix) + 1]; + uchar *suffix; + char *kbd_magic_keys; + + /* + * The following string defines the characters that can pe appended + * to "key_magic" to form the names of environment variables that + * hold "magic" key codes, i. e. such key codes that can cause + * pre-boot actions. If the string is empty (""), then only + * "key_magic" is checked (old behaviour); the string "125" causes + * checks for "key_magic1", "key_magic2" and "key_magic5", etc. + */ + if ((kbd_magic_keys = getenv ("magic_keys")) == NULL) + kbd_magic_keys = ""; + + /* loop over all magic keys; + * use '\0' suffix in case of empty string + */ + for (suffix=(uchar *)kbd_magic_keys; *suffix || suffix==(uchar *)kbd_magic_keys; ++suffix) { + sprintf (magic, "%s%c", kbd_magic_prefix, *suffix); + debug ("### Check magic \"%s\"\n", magic); + if (compare_magic(kbd_data, (uchar *)getenv(magic)) == 0) { + char cmd_name[sizeof (kbd_command_prefix) + 1]; + char *cmd; + + sprintf (cmd_name, "%s%c", kbd_command_prefix, *suffix); + + cmd = getenv (cmd_name); + debug ("### Set PREBOOT to $(%s): \"%s\"\n", + cmd_name, cmd ? cmd : "<>"); + *kbd_data = *suffix; + return ((uchar *)cmd); + } + } + debug ("### Delete PREBOOT\n"); + *kbd_data = '\0'; + return (NULL); +} +#endif /* CONFIG_PREBOOT */ + +/*********************************************************************** +F* Function: int do_kbd (cmd_tbl_t *cmdtp, int flag, +F* int argc, char *argv[]) P*A*Z* + * +P* Parameters: cmd_tbl_t *cmdtp +P* - Pointer to our command table entry +P* int flag +P* - If the CMD_FLAG_REPEAT bit is set, then this call is +P* a repetition +P* int argc +P* - Argument count +P* char *argv[] +P* - Array of the actual arguments +P* +P* Returnvalue: int +P* - 0 is always returned. + * +Z* Intention: Implement the "kbd" command. +Z* The keyboard status is read. The result is printed on +Z* the console and written into the "keybd" environment +Z* variable. + * +D* Design: wd@denx.de +C* Coding: wd@denx.de +V* Verification: dzu@denx.de + ***********************************************************************/ +int do_kbd (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + uchar kbd_data[KEYBD_DATALEN]; + char keybd_env[2 * KEYBD_DATALEN + 1]; + uchar val; + int i; + +#if 0 /* Done in kbd_init */ + i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE); +#endif + + /* Read keys */ + val = KEYBD_CMD_READ_KEYS; + i2c_write (kbd_addr, 0, 0, &val, 1); + i2c_read (kbd_addr, 0, 0, kbd_data, KEYBD_DATALEN); + + puts ("Keys:"); + for (i = 0; i < KEYBD_DATALEN; ++i) { + sprintf (keybd_env + i + i, "%02X", kbd_data[i]); + printf (" %02x", kbd_data[i]); + } + putc ('\n'); + setenv ("keybd", keybd_env); + return 0; +} + +U_BOOT_CMD( + kbd, 1, 1, do_kbd, + "kbd - read keyboard status\n", + NULL +); + +/*----------------------------- Utilities -----------------------------*/ + +#ifdef CONFIG_POST +/* + * Returns 1 if keys pressed to start the power-on long-running tests + * Called from board_init_f(). + */ +int post_hotkeys_pressed(void) +{ + uchar kbd_data[KEYBD_DATALEN]; + uchar val; + + /* Read keys */ + val = KEYBD_CMD_READ_KEYS; + i2c_write (kbd_addr, 0, 0, &val, 1); + i2c_read (kbd_addr, 0, 0, kbd_data, KEYBD_DATALEN); + + return (compare_magic(kbd_data, (uchar *)CONFIG_POST_KEY_MAGIC) == 0); +} +#endif diff --git a/board/lwmon5/lwmon5.c b/board/lwmon5/lwmon5.c index 830ec1911..0958194ec 100644 --- a/board/lwmon5/lwmon5.c +++ b/board/lwmon5/lwmon5.c @@ -28,7 +28,8 @@ DECLARE_GLOBAL_DATA_PTR; extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ -ulong flash_get_size (ulong base, int banknum); +ulong flash_get_size(ulong base, int banknum); +int misc_init_r_kbd(void); int board_early_init_f(void) { @@ -295,6 +296,11 @@ int misc_init_r(void) out_be32((void *)0xc4000024, 0x64); out_be32((void *)0xc4000020, 0x701); + /* + * Init matrix keyboard + */ + misc_init_r_kbd(); + return 0; } @@ -521,14 +527,3 @@ void hw_watchdog_reset(void) val = gpio_read_out_bit(CFG_GPIO_WATCHDOG) == 0 ? 1 : 0; gpio_write_bit(CFG_GPIO_WATCHDOG, val); } - -#ifdef CONFIG_POST -/* - * Returns 1 if keys pressed to start the power-on long-running tests - * Called from board_init_f(). - */ -int post_hotkeys_pressed(void) -{ - return (ctrlc()); -} -#endif diff --git a/include/asm-ppc/global_data.h b/include/asm-ppc/global_data.h index cd2463643..a35013d56 100644 --- a/include/asm-ppc/global_data.h +++ b/include/asm-ppc/global_data.h @@ -129,7 +129,7 @@ typedef struct global_data { unsigned long do_mdm_init; unsigned long be_quiet; #endif -#ifdef CONFIG_LWMON +#if defined(CONFIG_LWMON) || defined(CONFIG_LWMON5) unsigned long kbd_status; #endif void **jt; /* jump table */ diff --git a/include/configs/lwmon5.h b/include/configs/lwmon5.h index 5ebe4404d..14a200d3e 100644 --- a/include/configs/lwmon5.h +++ b/include/configs/lwmon5.h @@ -34,6 +34,7 @@ #define CONFIG_SYS_CLK_FREQ 33300000 /* external freq to pll */ #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ +#define CONFIG_BOARD_POSTCLK_INIT 1 /* Call board_postclk_init */ #define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */ #define CONFIG_ADD_RAM_INFO 1 /* Print additional info */ @@ -159,10 +160,16 @@ #define CONFIG_RTC_PCF8563 1 /* enable Philips PCF8563 RTC */ #define CFG_I2C_RTC_ADDR 0x51 /* Philips PCF8563 RTC address */ +#define CFG_I2C_KEYBD_ADDR 0x56 /* PIC LWE keyboard */ -#define CONFIG_PREBOOT "echo;" \ - "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ - "echo" +#define CONFIG_POST_KEY_MAGIC "3C+3E" /* press F3 + F5 keys to force POST */ +#if 0 +#define CONFIG_AUTOBOOT_KEYED /* Enable "password" protection */ +#define CONFIG_AUTOBOOT_PROMPT "\nEnter password - autoboot in %d sec...\n" +#define CONFIG_AUTOBOOT_DELAY_STR " " /* "password" */ +#endif + +#define CONFIG_PREBOOT "setenv bootdelay 15" #undef CONFIG_BOOTARGS @@ -210,6 +217,7 @@ #define CONFIG_PHY_ADDR 3 /* PHY address, See schematics */ #define CONFIG_PHY_RESET 1 /* reset phy upon startup */ +#define CONFIG_PHY_RESET_DELAY 300 #define CONFIG_HAS_ETH0 #define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */ From c64fb30e4c5976007d56fc1789c7a0666082b536 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Wed, 22 Aug 2007 08:56:09 +0200 Subject: [PATCH 180/259] ppc4xx: Remove unused option CFG_INIT_RAM_OCM Signed-off-by: Stefan Roese --- include/configs/hcu5.h | 1 - include/configs/lwmon5.h | 1 - 2 files changed, 2 deletions(-) diff --git a/include/configs/hcu5.h b/include/configs/hcu5.h index f95d78ec1..90858819b 100644 --- a/include/configs/hcu5.h +++ b/include/configs/hcu5.h @@ -73,7 +73,6 @@ * Initial RAM & stack pointer *----------------------------------------------------------------------*/ /* 440EPx/440GRx have 16KB of internal SRAM, so no need for D-Cache */ -#define CFG_INIT_RAM_OCM 1 /* OCM as init ram */ #define CFG_INIT_RAM_ADDR CFG_OCM_BASE /* OCM */ #define CFG_INIT_RAM_END (4 << 10) diff --git a/include/configs/lwmon5.h b/include/configs/lwmon5.h index cf8ff4520..23b19ba89 100644 --- a/include/configs/lwmon5.h +++ b/include/configs/lwmon5.h @@ -72,7 +72,6 @@ * Initial RAM & stack pointer *----------------------------------------------------------------------*/ /* 440EPx/440GRx have 16KB of internal SRAM, so no need for D-Cache */ -#define CFG_INIT_RAM_OCM 1 /* OCM as init ram */ #define CFG_INIT_RAM_ADDR CFG_OCM_BASE /* OCM */ #define CFG_OCM_DATA_ADDR CFG_OCM_BASE From c25dd8fc25e9ca3695db996a257d9ba4dab414db Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Thu, 23 Aug 2007 11:02:37 +0200 Subject: [PATCH 181/259] ppc4xx: Add support for 2nd I2C EEPROM on lwmon5 board This patch adds support for the 2nd EEPROM (AT24C128) on the lwmon5 board. Now the "eeprom" command can be used to read/write from/to this device. Additionally a new command was added "eepromwp" to en-/disable the write-protect of this 2nd EEPROM. The 1st EEPROM is not affected by this write-protect command. Signed-off-by: Stefan Roese --- board/lwmon5/lwmon5.c | 27 +++++++++++++++++++++++++++ include/configs/lwmon5.h | 15 +++++++++------ 2 files changed, 36 insertions(+), 6 deletions(-) diff --git a/board/lwmon5/lwmon5.c b/board/lwmon5/lwmon5.c index 0958194ec..77f998971 100644 --- a/board/lwmon5/lwmon5.c +++ b/board/lwmon5/lwmon5.c @@ -19,6 +19,7 @@ */ #include +#include #include #include #include @@ -527,3 +528,29 @@ void hw_watchdog_reset(void) val = gpio_read_out_bit(CFG_GPIO_WATCHDOG) == 0 ? 1 : 0; gpio_write_bit(CFG_GPIO_WATCHDOG, val); } + +int do_eeprom_wp(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + if (argc < 2) { + printf("Usage:\n%s\n", cmdtp->usage); + return 1; + } + + if ((strcmp(argv[1], "on") == 0)) { + gpio_write_bit(CFG_GPIO_EEPROM_EXT_WP, 1); + } else if ((strcmp(argv[1], "off") == 0)) { + gpio_write_bit(CFG_GPIO_EEPROM_EXT_WP, 0); + } else { + printf("Usage:\n%s\n", cmdtp->usage); + return 1; + } + + + return 0; +} + +U_BOOT_CMD( + eepromwp, 2, 0, do_eeprom_wp, + "eepromwp- eeprom write protect off/on\n", + " - enable (on) or disable (off) I2C EEPROM write protect\n" +); diff --git a/include/configs/lwmon5.h b/include/configs/lwmon5.h index 23b19ba89..7b2def3d2 100644 --- a/include/configs/lwmon5.h +++ b/include/configs/lwmon5.h @@ -161,15 +161,16 @@ *----------------------------------------------------------------------*/ #define CONFIG_HARD_I2C 1 /* I2C with hardware support */ #undef CONFIG_SOFT_I2C /* I2C bit-banged */ -#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CFG_I2C_SPEED 100000 /* I2C speed and slave address */ #define CFG_I2C_SLAVE 0x7F -#define CFG_I2C_MULTI_EEPROMS -#define CFG_I2C_EEPROM_ADDR (0xa8>>1) -#define CFG_I2C_EEPROM_ADDR_LEN 1 +#define CFG_I2C_EEPROM_ADDR 0x53 /* EEPROM AT24C128 */ +#define CFG_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */ +#define CFG_EEPROM_PAGE_WRITE_BITS 6 /* The Atmel AT24C128 has */ + /* 64 byte page write mode using*/ + /* last 6 bits of the address */ +#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ #define CFG_EEPROM_PAGE_WRITE_ENABLE -#define CFG_EEPROM_PAGE_WRITE_BITS 3 -#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 #define CONFIG_RTC_PCF8563 1 /* enable Philips PCF8563 RTC */ #define CFG_I2C_RTC_ADDR 0x51 /* Philips PCF8563 RTC address */ @@ -397,6 +398,8 @@ #define CFG_GPIO_PHY1_RST 12 #define CFG_GPIO_FLASH_WP 14 #define CFG_GPIO_PHY0_RST 22 +#define CFG_GPIO_EEPROM_EXT_WP 55 +#define CFG_GPIO_EEPROM_INT_WP 57 #define CFG_GPIO_WATCHDOG 58 #define CFG_GPIO_LIME_S 59 #define CFG_GPIO_LIME_RST 60 From d7bfa620037a6d2210159387571bdf93aa32c162 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Fri, 24 Aug 2007 15:19:10 +0200 Subject: [PATCH 182/259] ppc4xx: Change GPIO signal for watchdog triggering on lwmon5 Signed-off-by: Stefan Roese --- include/configs/lwmon5.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/configs/lwmon5.h b/include/configs/lwmon5.h index 7b2def3d2..ecca577aa 100644 --- a/include/configs/lwmon5.h +++ b/include/configs/lwmon5.h @@ -400,9 +400,9 @@ #define CFG_GPIO_PHY0_RST 22 #define CFG_GPIO_EEPROM_EXT_WP 55 #define CFG_GPIO_EEPROM_INT_WP 57 -#define CFG_GPIO_WATCHDOG 58 #define CFG_GPIO_LIME_S 59 #define CFG_GPIO_LIME_RST 60 +#define CFG_GPIO_WATCHDOG 63 /*----------------------------------------------------------------------- * PPC440 GPIO Configuration From 75e1a84d483e36be10e206e539b028c4889e1158 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Fri, 24 Aug 2007 15:41:42 +0200 Subject: [PATCH 183/259] ppc4xx: Add RTC POST test to lwmon5 board configuration Since this RTC POST test is taking quite a while to complete it's only initiated upon special keypress same as the complete memory POST. Signed-off-by: Stefan Roese --- include/configs/lwmon5.h | 15 ++++++++------- 1 file changed, 8 insertions(+), 7 deletions(-) diff --git a/include/configs/lwmon5.h b/include/configs/lwmon5.h index ecca577aa..be483245b 100644 --- a/include/configs/lwmon5.h +++ b/include/configs/lwmon5.h @@ -142,15 +142,16 @@ #endif /* POST support */ -#define CONFIG_POST (CFG_POST_MEMORY | \ - CFG_POST_ECC_ON | \ +#define CONFIG_POST (CFG_POST_CACHE | \ CFG_POST_CPU | \ - CFG_POST_UART | \ - CFG_POST_I2C | \ - CFG_POST_CACHE | \ - CFG_POST_FPU | \ + CFG_POST_ECC_ON | \ CFG_POST_ETHER | \ - CFG_POST_SPR) + CFG_POST_FPU | \ + CFG_POST_I2C | \ + CFG_POST_MEMORY | \ + CFG_POST_RTC | \ + CFG_POST_SPR | \ + CFG_POST_UART) #define CFG_POST_CACHE_ADDR 0x10000000 /* free virtual address */ #define CONFIG_LOGBUFFER From 9c02defc29b57945b600714cf61ddfd02b02fb14 Mon Sep 17 00:00:00 2001 From: Yuri Tikhonov Date: Sat, 25 Aug 2007 05:07:16 +0200 Subject: [PATCH 184/259] POST: limit memory test area to not touch global data anymore As experienced on lwmon5, on some boards the POST memory test can corrupt the global data buffer (bd). This patch fixes this issue by checking and limiting this area. Signed-off-by: Yuri Tikhonov Signed-off-by: Stefan Roese --- post/drivers/memory.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/post/drivers/memory.c b/post/drivers/memory.c index a2c088bad..fbc349a85 100644 --- a/post/drivers/memory.c +++ b/post/drivers/memory.c @@ -461,6 +461,9 @@ int memory_post_test (int flags) unsigned long memsize = (bd->bi_memsize >= 256 << 20 ? 256 << 20 : bd->bi_memsize) - (1 << 20); + /* Limit area to be tested with the board info struct */ + if (CFG_SDRAM_BASE + memsize > (ulong)bd) + memsize = (ulong)bd - CFG_SDRAM_BASE; if (flags & POST_SLOWTEST) { ret = memory_post_tests (CFG_SDRAM_BASE, memsize); From f98984cb194bb34dbe1db9429d3b51133af30d07 Mon Sep 17 00:00:00 2001 From: Heiko Schocher Date: Tue, 28 Aug 2007 17:39:14 +0200 Subject: [PATCH 185/259] IDE: - make ide_inb () and ide_outb () "weak", so boards can define there own I/O functions. (Needed for the pcs440ep board). - The default I/O Functions are again 8 Bit accesses. - Added CONFIG_CMD_IDE for the pcs440ep Board. Signed-off-by: Heiko Schocher --- board/pcs440ep/pcs440ep.c | 24 ++++++++++++++++++ common/cmd_ide.c | 51 ++++++++++++-------------------------- include/asm-ppc/io.h | 3 +++ include/configs/pcs440ep.h | 13 +++------- include/ide.h | 2 ++ 5 files changed, 49 insertions(+), 44 deletions(-) diff --git a/board/pcs440ep/pcs440ep.c b/board/pcs440ep/pcs440ep.c index e247fee0c..90e99d3dc 100644 --- a/board/pcs440ep/pcs440ep.c +++ b/board/pcs440ep/pcs440ep.c @@ -30,6 +30,7 @@ #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; @@ -867,6 +868,29 @@ U_BOOT_CMD( ); #endif +#if defined (CONFIG_CMD_IDE) +/* These addresses need to be shifted one place to the left + * ( bus per_addr 20 -30 is connectsd on CF bus A10-A0) + * These values are shifted + */ +extern ulong *ide_bus_offset; +void inline ide_outb(int dev, int port, unsigned char val) +{ + debug ("ide_outb (dev= %d, port= 0x%x, val= 0x%02x) : @ 0x%08lx\n", + dev, port, val, (ATA_CURR_BASE(dev)+port)); + + out_be16((u16 *)(ATA_CURR_BASE(dev)+(port << 1)), val); +} +unsigned char inline ide_inb(int dev, int port) +{ + uchar val; + val = in_be16((u16 *)(ATA_CURR_BASE(dev)+(port << 1))); + debug ("ide_inb (dev= %d, port= 0x%x) : @ 0x%08lx -> 0x%02x\n", + dev, port, (ATA_CURR_BASE(dev)+port), val); + return (val); +} +#endif + #ifdef CONFIG_IDE_PREINIT int ide_preinit (void) { diff --git a/common/cmd_ide.c b/common/cmd_ide.c index 89fefed33..bb064eaa0 100644 --- a/common/cmd_ide.c +++ b/common/cmd_ide.c @@ -31,6 +31,7 @@ #include #include #include +#include #if defined(CONFIG_IDE_8xx_DIRECT) || defined(CONFIG_IDE_PCMCIA) # include @@ -128,8 +129,6 @@ ulong ide_bus_offset[CFG_IDE_MAXBUS] = { }; -#define ATA_CURR_BASE(dev) (CFG_ATA_BASE_ADDR+ide_bus_offset[IDE_BUS(dev)]) - #ifndef CONFIG_AMIGAONEG3SE static int ide_bus_ok[CFG_IDE_MAXBUS]; #else @@ -172,8 +171,8 @@ static uchar ide_wait (int dev, ulong t); #define IDE_SPIN_UP_TIME_OUT 5000 /* 5 sec spin-up timeout */ -static void __inline__ ide_outb(int dev, int port, unsigned char val); -static unsigned char __inline__ ide_inb(int dev, int port); +void inline ide_outb(int dev, int port, unsigned char val); +unsigned char inline ide_inb(int dev, int port); static void input_data(int dev, ulong *sect_buf, int words); static void output_data(int dev, ulong *sect_buf, int words); static void ident_cpy (unsigned char *dest, unsigned char *src, unsigned int len); @@ -805,45 +804,27 @@ set_pcmcia_timing (int pmode) /* ------------------------------------------------------------------------- */ -#if defined(__PPC__) || defined(CONFIG_PXA_PCMCIA) -static void __inline__ -ide_outb(int dev, int port, unsigned char val) +void inline +__ide_outb(int dev, int port, unsigned char val) { debug ("ide_outb (dev= %d, port= 0x%x, val= 0x%02x) : @ 0x%08lx\n", - dev, port, val, (ATA_CURR_BASE(dev)+port)); - - /* Ensure I/O operations complete */ - EIEIO; - *((u16 *)(ATA_CURR_BASE(dev)+CFG_ATA_PORT_ADDR(port))) = val; + dev, port, val, (ATA_CURR_BASE(dev)+CFG_ATA_PORT_ADDR(port))); + outb(val, (ATA_CURR_BASE(dev)+CFG_ATA_PORT_ADDR(port))); } -#else /* ! __PPC__ */ -static void __inline__ -ide_outb(int dev, int port, unsigned char val) -{ - outb(val, ATA_CURR_BASE(dev)+CFG_ATA_PORT_ADDR(port)); -} -#endif /* __PPC__ */ +void inline ide_outb (int dev, int port, unsigned char val) + __attribute__((weak, alias("__ide_outb"))); - -#if defined(__PPC__) || defined(CONFIG_PXA_PCMCIA) -static unsigned char __inline__ -ide_inb(int dev, int port) +unsigned char inline +__ide_inb(int dev, int port) { uchar val; - /* Ensure I/O operations complete */ - EIEIO; - val = *((u16 *)(ATA_CURR_BASE(dev)+CFG_ATA_PORT_ADDR(port))); + val = inb((ATA_CURR_BASE(dev)+CFG_ATA_PORT_ADDR(port))); debug ("ide_inb (dev= %d, port= 0x%x) : @ 0x%08lx -> 0x%02x\n", - dev, port, (ATA_CURR_BASE(dev)+port), val); - return (val); + dev, port, (ATA_CURR_BASE(dev)+CFG_ATA_PORT_ADDR(port)), val); + return val; } -#else /* ! __PPC__ */ -static unsigned char __inline__ -ide_inb(int dev, int port) -{ - return inb(ATA_CURR_BASE(dev)+CFG_ATA_PORT_ADDR(port)); -} -#endif /* __PPC__ */ +unsigned char inline ide_inb(int dev, int port) + __attribute__((weak, alias("__ide_inb"))); #ifdef __PPC__ # ifdef CONFIG_AMIGAONEG3SE diff --git a/include/asm-ppc/io.h b/include/asm-ppc/io.h index 03289bcc2..11dfa1c57 100644 --- a/include/asm-ppc/io.h +++ b/include/asm-ppc/io.h @@ -13,6 +13,9 @@ #define SIO_CONFIG_RA 0x398 #define SIO_CONFIG_RD 0x399 +#ifndef _IO_BASE +#define _IO_BASE 0 +#endif #define readb(addr) in_8((volatile u8 *)(addr)) #define writeb(b,addr) out_8((volatile u8 *)(addr), (b)) diff --git a/include/configs/pcs440ep.h b/include/configs/pcs440ep.h index 8e51d2d3c..7653ba1d2 100644 --- a/include/configs/pcs440ep.h +++ b/include/configs/pcs440ep.h @@ -266,7 +266,10 @@ #define CONFIG_CMD_DIAG #define CONFIG_CMD_EEPROM #define CONFIG_CMD_ELF +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT #define CONFIG_CMD_I2C +#define CONFIG_CMD_IDE #define CONFIG_CMD_IRQ #define CONFIG_CMD_MII #define CONFIG_CMD_NET @@ -274,12 +277,10 @@ #define CONFIG_CMD_PCI #define CONFIG_CMD_PING #define CONFIG_CMD_REGINFO +#define CONFIG_CMD_REISER #define CONFIG_CMD_SDRAM -#define CONFIG_CMD_EXT2 -#define CONFIG_CMD_FAT #define CONFIG_CMD_USB - #define CONFIG_SUPPORT_VFAT /* @@ -488,10 +489,4 @@ /* Offset for alternate registers */ #define CFG_ATA_ALT_OFFSET (0x0000) -/* These addresses need to be shifted one place to the left - * ( bus per_addr 20 -30 is connectsd on CF bus A10-A0) - * These values are shifted - */ -#define CFG_ATA_PORT_ADDR(port) ((port) << 1) - #endif /* __CONFIG_H */ diff --git a/include/ide.h b/include/ide.h index 6976a6c31..222f4f84e 100644 --- a/include/ide.h +++ b/include/ide.h @@ -26,6 +26,8 @@ #define IDE_BUS(dev) (dev >> 1) +#define ATA_CURR_BASE(dev) (CFG_ATA_BASE_ADDR+ide_bus_offset[IDE_BUS(dev)]) + #ifdef CONFIG_IDE_LED /* From a861558c65f65f1cf1302f3a35e9db7686b9e1a3 Mon Sep 17 00:00:00 2001 From: Heiko Schocher Date: Tue, 28 Aug 2007 17:40:33 +0200 Subject: [PATCH 186/259] [UC101] Fix: if no CF in the board, U-Boot resets sometimes. Signed-off-by: Heiko Schocher --- cpu/mpc5xxx/ide.c | 8 ++++++++ include/configs/uc101.h | 1 - 2 files changed, 8 insertions(+), 1 deletion(-) diff --git a/cpu/mpc5xxx/ide.c b/cpu/mpc5xxx/ide.c index 087ddac10..344e6f202 100644 --- a/cpu/mpc5xxx/ide.c +++ b/cpu/mpc5xxx/ide.c @@ -54,11 +54,19 @@ int ide_preinit (void) /* All sample codes do that... */ *(vu_long *) MPC5XXX_ATA_SHARE_COUNT = 0; +#if defined(CONFIG_UC101) + /* Configure and reset host */ + *(vu_long *) MPC5XXX_ATA_HOST_CONFIG = + MPC5xxx_ATA_HOSTCONF_SMR | MPC5xxx_ATA_HOSTCONF_FR; + udelay (10); + *(vu_long *) MPC5XXX_ATA_HOST_CONFIG = 0; +#else /* Configure and reset host */ *(vu_long *) MPC5XXX_ATA_HOST_CONFIG = MPC5xxx_ATA_HOSTCONF_IORDY | MPC5xxx_ATA_HOSTCONF_SMR | MPC5xxx_ATA_HOSTCONF_FR; udelay (10); *(vu_long *) MPC5XXX_ATA_HOST_CONFIG = MPC5xxx_ATA_HOSTCONF_IORDY; +#endif /* Disable prefetch on Commbus */ psdma->PtdCntrl |= 1; diff --git a/include/configs/uc101.h b/include/configs/uc101.h index 3b471d0a9..aed80ec1e 100644 --- a/include/configs/uc101.h +++ b/include/configs/uc101.h @@ -332,7 +332,6 @@ #define CFG_IDE_MAXDEVICE 2 /* max. 2 drives per IDE bus */ #define CONFIG_IDE_PREINIT 1 -/* #define CONFIG_IDE_RESET 1 beispile siehe tqm5200.c */ #define CFG_ATA_IDE0_OFFSET 0x0000 From 6af2eeb1e99c2dcc584d4c5ab7fcae30a325f4de Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Wed, 29 Aug 2007 01:32:05 +0200 Subject: [PATCH 187/259] Minor coding style cleanup. Signed-off-by: Wolfgang Denk --- cpu/mpc5xxx/ide.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/cpu/mpc5xxx/ide.c b/cpu/mpc5xxx/ide.c index 344e6f202..df5b4acd0 100644 --- a/cpu/mpc5xxx/ide.c +++ b/cpu/mpc5xxx/ide.c @@ -56,7 +56,7 @@ int ide_preinit (void) #if defined(CONFIG_UC101) /* Configure and reset host */ - *(vu_long *) MPC5XXX_ATA_HOST_CONFIG = + *(vu_long *) MPC5XXX_ATA_HOST_CONFIG = MPC5xxx_ATA_HOSTCONF_SMR | MPC5xxx_ATA_HOSTCONF_FR; udelay (10); *(vu_long *) MPC5XXX_ATA_HOST_CONFIG = 0; From 3bb342fc85d79dbb6b8c2039e7cdcddc82b8d90f Mon Sep 17 00:00:00 2001 From: Kim Phillips Date: Fri, 10 Aug 2007 14:34:14 -0500 Subject: [PATCH 188/259] fdt: remove unused OF_FLAT_TREE_MAX_SIZE references and make some minor corrections to the FDT part of the README. Signed-off-by: Kim Phillips --- README | 10 ++++------ include/configs/IceCube.h | 3 --- include/configs/MPC8313ERDB.h | 3 --- include/configs/MPC832XEMDS.h | 3 --- include/configs/MPC8349EMDS.h | 3 --- include/configs/MPC8349ITX.h | 3 --- include/configs/MPC8360EMDS.h | 4 ---- include/configs/MPC8540ADS.h | 3 --- include/configs/MPC8541CDS.h | 3 --- include/configs/MPC8544DS.h | 3 --- include/configs/MPC8548CDS.h | 3 --- include/configs/MPC8555CDS.h | 3 --- include/configs/MPC8560ADS.h | 3 --- include/configs/MPC8568MDS.h | 3 --- include/configs/MPC8641HPCN.h | 3 --- include/configs/TQM5200.h | 2 -- include/configs/jupiter.h | 3 --- include/configs/motionpro.h | 2 -- include/configs/mpc7448hpc2.h | 3 --- include/configs/sbc8349.h | 3 --- include/configs/stxxtc.h | 3 --- 21 files changed, 4 insertions(+), 65 deletions(-) diff --git a/README b/README index 4b1982b22..09eb76fe4 100644 --- a/README +++ b/README @@ -338,7 +338,7 @@ The following options need to be configured: CONFIG_OF_LIBFDT * New libfdt-based support * Adds the "fdt" command - * The bootm command does _not_ modify the fdt + * The bootm command automatically updates the fdt CONFIG_OF_FLAT_TREE * Deprecated, see CONFIG_OF_LIBFDT @@ -347,15 +347,13 @@ The following options need to be configured: * The environment variable "disable_of", when set, disables this functionality. - CONFIG_OF_FLAT_TREE_MAX_SIZE - - The maximum size of the constructed OF tree. - OF_CPU - The proper name of the cpus node. OF_SOC - The proper name of the soc node. OF_TBCLK - The timebase frequency. OF_STDOUT_PATH - The path to the console device + boards with QUICC Engines require OF_QE to set UCC mac addresses + CONFIG_OF_HAS_BD_T * CONFIG_OF_LIBFDT - enables the "fdt bd_t" command @@ -365,7 +363,7 @@ The following options need to be configured: CONFIG_OF_HAS_UBOOT_ENV - * CONFIG_OF_LIBFDT - enables the "fdt bd_t" command + * CONFIG_OF_LIBFDT - enables the "fdt env" command * CONFIG_OF_FLAT_TREE - The resulting flat device tree will have a copy of u-boot's environment variables diff --git a/include/configs/IceCube.h b/include/configs/IceCube.h index 532615485..bdd92bae3 100644 --- a/include/configs/IceCube.h +++ b/include/configs/IceCube.h @@ -181,9 +181,6 @@ #define CONFIG_OF_FLAT_TREE 1 #define CONFIG_OF_BOARD_SETUP 1 -/* maximum size of the flat tree (8K) */ -#define OF_FLAT_TREE_MAX_SIZE 8192 - #define OF_CPU "PowerPC,5200@0" #define OF_SOC "soc5200@f0000000" #define OF_TBCLK (bd->bi_busfreq / 4) diff --git a/include/configs/MPC8313ERDB.h b/include/configs/MPC8313ERDB.h index 36b0f160b..6568fe13b 100644 --- a/include/configs/MPC8313ERDB.h +++ b/include/configs/MPC8313ERDB.h @@ -231,9 +231,6 @@ #define CONFIG_OF_LIBFDT 1 #define CONFIG_OF_BOARD_SETUP 1 -/* maximum size of the flat tree (8K) */ -#define OF_FLAT_TREE_MAX_SIZE 8192 - #define OF_CPU "PowerPC,8313@0" #define OF_SOC "soc8313@e0000000" #define OF_TBCLK (bd->bi_busfreq / 4) diff --git a/include/configs/MPC832XEMDS.h b/include/configs/MPC832XEMDS.h index efc317288..c9c6d88cf 100644 --- a/include/configs/MPC832XEMDS.h +++ b/include/configs/MPC832XEMDS.h @@ -321,9 +321,6 @@ #define CONFIG_OF_LIBFDT 1 #define CONFIG_OF_BOARD_SETUP 1 -/* maximum size of the flat tree (8K) */ -#define OF_FLAT_TREE_MAX_SIZE 8192 - #define OF_CPU "PowerPC,8323@0" #define OF_SOC "soc8323@e0000000" #define OF_QE "qe@e0100000" diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h index c1f1c747c..92555bac4 100644 --- a/include/configs/MPC8349EMDS.h +++ b/include/configs/MPC8349EMDS.h @@ -342,9 +342,6 @@ #define CONFIG_OF_LIBFDT 1 #define CONFIG_OF_BOARD_SETUP 1 -/* maximum size of the flat tree (8K) */ -#define OF_FLAT_TREE_MAX_SIZE 8192 - #define OF_CPU "PowerPC,8349@0" #define OF_SOC "soc8349@e0000000" #define OF_TBCLK (bd->bi_busfreq / 4) diff --git a/include/configs/MPC8349ITX.h b/include/configs/MPC8349ITX.h index 3311d5c1f..54cab528b 100644 --- a/include/configs/MPC8349ITX.h +++ b/include/configs/MPC8349ITX.h @@ -299,9 +299,6 @@ boards, we say we have two, but don't display a message if we find only one. */ #define CONFIG_OF_LIBFDT 1 #define CONFIG_OF_BOARD_SETUP -/* maximum size of the flat tree (8K) */ -#define OF_FLAT_TREE_MAX_SIZE 8192 - #define OF_CPU "PowerPC,8349@0" #define OF_SOC "soc8349@e0000000" #define OF_TBCLK (bd->bi_busfreq / 4) diff --git a/include/configs/MPC8360EMDS.h b/include/configs/MPC8360EMDS.h index 094b66e7c..41f062ce7 100644 --- a/include/configs/MPC8360EMDS.h +++ b/include/configs/MPC8360EMDS.h @@ -351,10 +351,6 @@ #define CONFIG_OF_HAS_BD_T 1 #define CONFIG_OF_HAS_UBOOT_ENV 1 - -/* maximum size of the flat tree (8K) */ -#define OF_FLAT_TREE_MAX_SIZE 8192 - #define OF_CPU "PowerPC,8360@0" #define OF_SOC "soc8360@e0000000" #define OF_QE "qe@e0100000" diff --git a/include/configs/MPC8540ADS.h b/include/configs/MPC8540ADS.h index 22de2fb2c..be603ac11 100644 --- a/include/configs/MPC8540ADS.h +++ b/include/configs/MPC8540ADS.h @@ -301,9 +301,6 @@ #define CONFIG_OF_FLAT_TREE 1 #define CONFIG_OF_BOARD_SETUP 1 -/* maximum size of the flat tree (8K) */ -#define OF_FLAT_TREE_MAX_SIZE 8192 - #define OF_CPU "PowerPC,8540@0" #define OF_SOC "soc8540@e0000000" #define OF_TBCLK (bd->bi_busfreq / 8) diff --git a/include/configs/MPC8541CDS.h b/include/configs/MPC8541CDS.h index a4727b29b..4e061bd9f 100644 --- a/include/configs/MPC8541CDS.h +++ b/include/configs/MPC8541CDS.h @@ -312,9 +312,6 @@ extern unsigned long get_clock_freq(void); #define CONFIG_OF_FLAT_TREE 1 #define CONFIG_OF_BOARD_SETUP 1 -/* maximum size of the flat tree (8K) */ -#define OF_FLAT_TREE_MAX_SIZE 8192 - #define OF_CPU "PowerPC,8541@0" #define OF_SOC "soc8541@e0000000" #define OF_TBCLK (bd->bi_busfreq / 8) diff --git a/include/configs/MPC8544DS.h b/include/configs/MPC8544DS.h index 746f360f9..07631b921 100644 --- a/include/configs/MPC8544DS.h +++ b/include/configs/MPC8544DS.h @@ -252,9 +252,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_OF_FLAT_TREE 1 #define CONFIG_OF_BOARD_SETUP 1 -/* maximum size of the flat tree (8K) */ -#define OF_FLAT_TREE_MAX_SIZE 8192 - #define OF_CPU "PowerPC,8544@0" #define OF_SOC "soc8544@e0000000" #define OF_TBCLK (bd->bi_busfreq / 8) diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h index 58a8ea55c..682f0c057 100644 --- a/include/configs/MPC8548CDS.h +++ b/include/configs/MPC8548CDS.h @@ -336,9 +336,6 @@ extern unsigned long get_clock_freq(void); #define CONFIG_OF_FLAT_TREE 1 #define CONFIG_OF_BOARD_SETUP 1 -/* maximum size of the flat tree (8K) */ -#define OF_FLAT_TREE_MAX_SIZE 8192 - #define OF_CPU "PowerPC,8548@0" #define OF_SOC "soc8548@e0000000" #define OF_TBCLK (bd->bi_busfreq / 8) diff --git a/include/configs/MPC8555CDS.h b/include/configs/MPC8555CDS.h index 8d7d6579d..1d1b7c907 100644 --- a/include/configs/MPC8555CDS.h +++ b/include/configs/MPC8555CDS.h @@ -312,9 +312,6 @@ extern unsigned long get_clock_freq(void); #define CONFIG_OF_FLAT_TREE 1 #define CONFIG_OF_BOARD_SETUP 1 -/* maximum size of the flat tree (8K) */ -#define OF_FLAT_TREE_MAX_SIZE 8192 - #define OF_CPU "PowerPC,8555@0" #define OF_SOC "soc8555@e0000000" #define OF_TBCLK (bd->bi_busfreq / 8) diff --git a/include/configs/MPC8560ADS.h b/include/configs/MPC8560ADS.h index b3c33d9f7..a8f362fa1 100644 --- a/include/configs/MPC8560ADS.h +++ b/include/configs/MPC8560ADS.h @@ -292,9 +292,6 @@ #define CONFIG_OF_FLAT_TREE 1 #define CONFIG_OF_BOARD_SETUP 1 -/* maximum size of the flat tree (8K) */ -#define OF_FLAT_TREE_MAX_SIZE 8192 - #define OF_CPU "PowerPC,8560@0" #define OF_SOC "soc8560@e0000000" #define OF_TBCLK (bd->bi_busfreq / 8) diff --git a/include/configs/MPC8568MDS.h b/include/configs/MPC8568MDS.h index 80ccda51f..d5a14fc39 100644 --- a/include/configs/MPC8568MDS.h +++ b/include/configs/MPC8568MDS.h @@ -293,9 +293,6 @@ extern unsigned long get_clock_freq(void); #define CONFIG_OF_FLAT_TREE 1 #define CONFIG_OF_BOARD_SETUP 1 -/* maximum size of the flat tree (8K) */ -#define OF_FLAT_TREE_MAX_SIZE 8192 - #define OF_CPU "PowerPC,8568@0" #define OF_SOC "soc8568@e0000000" #define OF_QE "qe@e0080000" diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h index 03e815d87..bf25f7f4f 100644 --- a/include/configs/MPC8641HPCN.h +++ b/include/configs/MPC8641HPCN.h @@ -268,9 +268,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_OF_FLAT_TREE 1 #define CONFIG_OF_BOARD_SETUP 1 -/* maximum size of the flat tree (8K) */ -#define OF_FLAT_TREE_MAX_SIZE 8192 - #define OF_CPU "PowerPC,8641@0" #define OF_SOC "soc8641@f8000000" #define OF_TBCLK (bd->bi_busfreq / 4) diff --git a/include/configs/TQM5200.h b/include/configs/TQM5200.h index 3d9850023..c08173b07 100644 --- a/include/configs/TQM5200.h +++ b/include/configs/TQM5200.h @@ -704,8 +704,6 @@ #define CONFIG_OF_FLAT_TREE 1 #define CONFIG_OF_BOARD_SETUP 1 -/* maximum size of the flat tree (8K) */ -#define OF_FLAT_TREE_MAX_SIZE 8192 #define OF_CPU "PowerPC,5200@0" #define OF_SOC "soc5200@f0000000" #define OF_TBCLK (bd->bi_busfreq / 4) diff --git a/include/configs/jupiter.h b/include/configs/jupiter.h index b68c5aa46..4070ab971 100644 --- a/include/configs/jupiter.h +++ b/include/configs/jupiter.h @@ -148,9 +148,6 @@ #define CONFIG_OF_FLAT_TREE 1 #define CONFIG_OF_BOARD_SETUP 1 -/* maximum size of the flat tree (8K) */ -#define OF_FLAT_TREE_MAX_SIZE 8192 - #define OF_CPU "PowerPC,5200@0" #define OF_SOC "soc5200@f0000000" #define OF_TBCLK (bd->bi_busfreq / 8) diff --git a/include/configs/motionpro.h b/include/configs/motionpro.h index e0a827fdd..82827c692 100644 --- a/include/configs/motionpro.h +++ b/include/configs/motionpro.h @@ -420,8 +420,6 @@ extern void __led_set(led_id_t id, int state); #define CONFIG_OF_FLAT_TREE 1 #define CONFIG_OF_BOARD_SETUP 1 -/* maximum size of the flat tree (8K) */ -#define OF_FLAT_TREE_MAX_SIZE 8192 #define OF_CPU "PowerPC,5200@0" #define OF_SOC "soc5200@f0000000" #define OF_TBCLK (bd->bi_busfreq / 4) diff --git a/include/configs/mpc7448hpc2.h b/include/configs/mpc7448hpc2.h index f4f33f3e0..bd3107ab2 100644 --- a/include/configs/mpc7448hpc2.h +++ b/include/configs/mpc7448hpc2.h @@ -80,9 +80,6 @@ #define CONFIG_OF_FLAT_TREE 1 #define CONFIG_OF_BOARD_SETUP 1 -/* maximum size of the flat tree (8K) */ -#define OF_FLAT_TREE_MAX_SIZE 8192 - #define OF_CPU "PowerPC,7448@0" #define OF_TSI "tsi108@c0000000" #define OF_TBCLK (bd->bi_busfreq / 8) diff --git a/include/configs/sbc8349.h b/include/configs/sbc8349.h index 37a8f8705..e7d8a5a66 100644 --- a/include/configs/sbc8349.h +++ b/include/configs/sbc8349.h @@ -313,9 +313,6 @@ #define CONFIG_OF_FLAT_TREE 1 #define CONFIG_OF_BOARD_SETUP 1 -/* maximum size of the flat tree (8K) */ -#define OF_FLAT_TREE_MAX_SIZE 8192 - #define OF_CPU "PowerPC,8349@0" #define OF_SOC "soc8349@e0000000" #define OF_TBCLK (bd->bi_busfreq / 4) diff --git a/include/configs/stxxtc.h b/include/configs/stxxtc.h index 0dbf4b7fe..b035857dc 100644 --- a/include/configs/stxxtc.h +++ b/include/configs/stxxtc.h @@ -592,9 +592,6 @@ typedef unsigned int led_id_t; /* pass open firmware flat tree */ #define CONFIG_OF_FLAT_TREE 1 -/* maximum size of the flat tree (8K) */ -#define OF_FLAT_TREE_MAX_SIZE 8192 - #define OF_CPU "PowerPC,MPC870@0" #define OF_TBCLK (MPC8XX_HZ / 16) #define CONFIG_OF_HAS_BD_T 1 From 9bb8b209ed2058a5756ecbeb544c067e44a42aea Mon Sep 17 00:00:00 2001 From: Dirk Behme Date: Mon, 20 Aug 2007 07:09:05 +0200 Subject: [PATCH 189/259] Fix compilation error for omap2420h4_config. omap2420h4 switched to cfi, so remove old (already disabled) flash.c and flash_probe() calls in env_flash.c. Signed-off-by: Dirk Behme --- board/omap2420h4/flash.c | 537 --------------------------------------- common/env_flash.c | 20 +- 2 files changed, 1 insertion(+), 556 deletions(-) delete mode 100644 board/omap2420h4/flash.c diff --git a/board/omap2420h4/flash.c b/board/omap2420h4/flash.c deleted file mode 100644 index d5e106a5e..000000000 --- a/board/omap2420h4/flash.c +++ /dev/null @@ -1,537 +0,0 @@ -/* - * (C) Copyright 2001 - * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net - * - * (C) Copyright 2001-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2003 - * Texas Instruments, - * Kshitij Gupta - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include - -#define PHYS_FLASH_SECT_SIZE SZ_128K -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/* Board support for 1 or 2 flash devices */ -#undef FLASH_PORT_WIDTH32 -#define FLASH_PORT_WIDTH16 - -#ifdef FLASH_PORT_WIDTH16 -# define FLASH_PORT_WIDTH ushort -# define FLASH_PORT_WIDTHV vu_short -# define SWAP(x) __swab16(x) -#else -# define FLASH_PORT_WIDTH ulong -# define FLASH_PORT_WIDTHV vu_long -# define SWAP(x) __swab32(x) -#endif - -#define FPW FLASH_PORT_WIDTH -#define FPWV FLASH_PORT_WIDTHV - -#define mb() __asm__ __volatile__ ("" : : : "memory") - - -/* Flash Organization Structure */ -typedef struct OrgDef { - unsigned int sector_number; - unsigned int sector_size; -} OrgDef; - - -/* Flash Organizations */ -OrgDef OrgIntel_28F256L18T[] = { - {4, SZ_32K}, /* 4 * 32kBytes sectors */ - {255, SZ_128K}, /* 255 * 128kBytes sectors */ -}; - - -/*----------------------------------------------------------------------- - * Functions - */ -unsigned long flash_init (void); -static ulong flash_get_size (FPW * addr, flash_info_t * info); -static int write_data (flash_info_t * info, ulong dest, FPW data); -static void flash_get_offsets (ulong base, flash_info_t * info); -void inline spin_wheel (void); -void flash_print_info (flash_info_t * info); -void flash_unprotect_sectors (FPWV * addr); -int flash_erase (flash_info_t * info, int s_first, int s_last); -int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt); -void flash_unlock(flash_info_t * info, int bank); -int flash_probe(void); - -/*----------------------------------------------------------------------- - */ - -/* see if flash is ok */ -int flash_probe(void) -{ - return(flash_get_size ((FPW *) PHYS_FLASH_1, &flash_info[0])); -} - -unsigned long flash_init (void) -{ - int i; - ulong size = 0; - for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) { - switch (i) { - case 0: - flash_get_size ((FPW *) PHYS_FLASH_1, &flash_info[i]); - flash_get_offsets (PHYS_FLASH_1, &flash_info[i]); - /* to reset the lock bit */ - flash_unlock(&flash_info[i],i); - break; - case 1: - flash_get_size ((FPW *) PHYS_FLASH_2, &flash_info[i]); - flash_get_offsets (PHYS_FLASH_2, &flash_info[i]); - /* to reset the lock bit */ - flash_unlock(&flash_info[i],i); - break; - - default: - panic ("configured too many flash banks!\n"); - break; - } - size += flash_info[i].size; - } - -#ifdef CFG_ENV_IS_IN_FLASH - /* Protect monitor and environment sectors - */ - flash_protect (FLAG_PROTECT_SET, - CFG_FLASH_BASE, - CFG_FLASH_BASE + monitor_flash_len - 1, &flash_info[0]); - - flash_protect (FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0]); -#endif - return size; -} - -/*----------------------------------------------------------------------- - */ -void flash_unlock(flash_info_t * info, int bank) -{ - int j; - if (!bank) - j=2; /* leave 0,1 locked for boot bank */ - else - j=0; /* get the whole bank for #2 */ - - for (;jstart[j]); - if (addr == NULL) { - printf("Warning Flash probe failed\n"); - break; - } - flash_unprotect_sectors (addr); - *addr = (FPW) 0x00500050;/* clear status register */ - *addr = (FPW) 0x00FF00FF;/* resest to read mode */ - } -} - -/*----------------------------------------------------------------------- - */ -static void flash_get_offsets (ulong base, flash_info_t * info) -{ - int i; - volatile int r; /* gcc 3.4.0-1 strangeness, need to follow up.*/ - - if (info->flash_id == FLASH_UNKNOWN) { - return; - } - - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) { - for (i = 0; i < info->sector_count; i++) { - if (i > 254) { /* 255,256,257,258 */ - r=i; - info->start[i] = base + (((r-(int)255) * SZ_32K) + (255*PHYS_FLASH_SECT_SIZE)); - info->protect[i] = 0; - } else { - info->start[i] = base + (i * PHYS_FLASH_SECT_SIZE); - info->protect[i] = 0; - } - } - } -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t * info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_INTEL: - printf ("INTEL "); - break; - default: - printf ("Unknown Vendor "); - break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_28F256L18T: - printf ("FLASH 28F256L18T\n"); - break; - default: - printf ("Unknown Chip Type\n"); - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i = 0; i < info->sector_count; ++i) { - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[i], info->protect[i] ? " (RO)" : " "); - } - printf ("\n"); - return; -} - -/* - * The following code cannot be run from FLASH! - */ -static ulong flash_get_size (FPW * addr, flash_info_t * info) -{ - volatile FPW value; - /* mb(); this one makes ARM11 err go away, but I want it :) as a guide to problems */ - - /* Write auto select command: read Manufacturer ID */ - addr[0x5555] = (FPW) 0x00AA00AA; - addr[0x2AAA] = (FPW) 0x00550055; - addr[0x5555] = (FPW) 0x00900090; - - mb (); - value = addr[0] & 0xFF; /* just looking for 89 (8989 is hw pat)*/ - - switch (value) { - - case (FPW) INTEL_MANUFACT: - info->flash_id = FLASH_MAN_INTEL; - break; - - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - addr[0] = (FPW) 0x00FF00FF; /* restore read mode */ - return(0); /* no or unknown flash */ - } - - mb (); - value = addr[1]; /* device ID */ - switch (value) { - - case (FPW) (INTEL_ID_28F256L18T): /* 880D */ - info->flash_id += FLASH_28F256L18T; - info->sector_count = 259; /*0-258*/ - info->size = SZ_32M; - break; /* => 32 MB */ - - default: - info->flash_id = FLASH_UNKNOWN; - break; - } - - if (info->sector_count > CFG_MAX_FLASH_SECT) { - printf ("** ERROR: sector count %d > max (%d) **\n", - info->sector_count, CFG_MAX_FLASH_SECT); - info->sector_count = CFG_MAX_FLASH_SECT; - } - - addr[0] = (FPW) 0x00FF00FF; /* restore read mode */ - - return(info->size); -} - - -/* unprotects a sector for write and erase - * on some intel parts, this unprotects the entire chip, but it - * wont hurt to call this additional times per sector... - */ -void flash_unprotect_sectors (FPWV * addr) -{ -#define PD_FINTEL_WSMS_READY_MASK 0x0080 - - *addr = (FPW) 0x00500050; /* clear status register */ - - /* this sends the clear lock bit command */ - *addr = (FPW) 0x00600060; - *addr = (FPW) 0x00D000D0; -} - - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t * info, int s_first, int s_last) -{ - int prot, sect; - ulong type, start, last; - int rcode = 0; -#ifdef CONFIG_USE_IRQ - int iflag; -#endif - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - type = (info->flash_id & FLASH_VENDMASK); - if ((type != FLASH_MAN_INTEL)) { - printf ("Can't erase unknown flash type %08lx - aborted\n", - info->flash_id); - return 1; - } - - prot = 0; - for (sect = s_first; sect <= s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - - start = get_timer (0); - last = start; - -#ifdef CONFIG_USE_IRQ - /* Disable interrupts which might cause a timeout here */ - iflag = disable_interrupts (); -#endif - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - FPWV *addr = (FPWV *) (info->start[sect]); - FPW status; - - printf ("Erasing sector %2d ... ", sect); - - flash_unprotect_sectors (addr); - - /* arm simple, non interrupt dependent timer */ - reset_timer_masked (); - - *addr = (FPW) 0x00500050;/* clear status register */ - *addr = (FPW) 0x00200020;/* erase setup */ - *addr = (FPW) 0x00D000D0;/* erase confirm */ - - while (((status = - *addr) & (FPW) 0x00800080) != - (FPW) 0x00800080) { - if (get_timer_masked () > - CFG_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - /* suspend erase */ - *addr = (FPW) 0x00B000B0; - /* reset to read mode */ - *addr = (FPW) 0x00FF00FF; - rcode = 1; - break; - } - } - - /* clear status register cmd. */ - *addr = (FPW) 0x00500050; - *addr = (FPW) 0x00FF00FF;/* resest to read mode */ - printf (" done\n"); - } - } -#ifdef CONFIG_USE_IRQ - if (iflag) - enable_interrupts(); -#endif - - return rcode; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - * 4 - Flash not identified - */ - -int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) -{ - ulong cp, wp; - FPW data; - int count, i, l, rc, port_width; - - if (info->flash_id == FLASH_UNKNOWN) { - return 4; - } -/* get lower word aligned address */ -#ifdef FLASH_PORT_WIDTH16 - wp = (addr & ~1); - port_width = 2; -#else - wp = (addr & ~3); - port_width = 4; -#endif - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i = 0, cp = wp; i < l; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - for (; i < port_width && cnt > 0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt == 0 && i < port_width; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - - if ((rc = write_data (info, wp, SWAP (data))) != 0) { - return(rc); - } - wp += port_width; - } - - /* - * handle word aligned part - */ - count = 0; - while (cnt >= port_width) { - data = 0; - for (i = 0; i < port_width; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_data (info, wp, SWAP (data))) != 0) { - return(rc); - } - wp += port_width; - cnt -= port_width; - if (count++ > 0x800) { - spin_wheel (); - count = 0; - } - } - - if (cnt == 0) { - return(0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i < port_width; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - - return(write_data (info, wp, SWAP (data))); -} - -/*----------------------------------------------------------------------- - * Write a word or halfword to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_data (flash_info_t * info, ulong dest, FPW data) -{ - FPWV *addr = (FPWV *) dest; - ulong status; -#ifdef CONFIG_USE_IRQ - int iflag; -#endif - - /* Check if Flash is (sufficiently) erased */ - if ((*addr & data) != data) { - printf ("not erased at %08lx (%x)\n", (ulong) addr, *addr); - return(2); - } - /* Disable interrupts which might cause a timeout here */ -#ifdef CONFIG_USE_IRQ - iflag = disable_interrupts (); -#endif - *addr = (FPW) 0x00400040; /* write setup */ - *addr = data; - - /* arm simple, non interrupt dependent timer */ - reset_timer_masked (); - - /* wait while polling the status register */ - while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) { - if (get_timer_masked () > CFG_FLASH_WRITE_TOUT) { - *addr = (FPW) 0x00FF00FF; /* restore read mode */ - return(1); - } - } - *addr = (FPW) 0x00FF00FF; /* restore read mode */ - -#ifdef CONFIG_USE_IRQ - if (iflag) - enable_interrupts(); -#endif - - return(0); -} - -void inline spin_wheel (void) -{ - static int p = 0; - static char w[] = "\\/-"; - - printf ("\010%c", w[p]); - (++p == 3) ? (p = 0) : 0; -} diff --git a/common/env_flash.c b/common/env_flash.c index 7a37e550d..eccfb62a3 100644 --- a/common/env_flash.c +++ b/common/env_flash.c @@ -107,13 +107,6 @@ int env_init(void) ulong addr1 = (ulong)&(flash_addr->data); ulong addr2 = (ulong)&(flash_addr_new->data); -#ifdef CONFIG_OMAP2420H4 - int flash_probe(void); - - if(flash_probe() == 0) - goto bad_flash; -#endif - crc1_ok = (crc32(0, flash_addr->data, ENV_SIZE) == flash_addr->crc); crc2_ok = (crc32(0, flash_addr_new->data, ENV_SIZE) == flash_addr_new->crc); @@ -143,9 +136,6 @@ int env_init(void) gd->env_valid = 2; } -#ifdef CONFIG_OMAP2420H4 -bad_flash: -#endif return (0); } @@ -259,20 +249,12 @@ Done: int env_init(void) { -#ifdef CONFIG_OMAP2420H4 - int flash_probe(void); - - if(flash_probe() == 0) - goto bad_flash; -#endif if (crc32(0, env_ptr->data, ENV_SIZE) == env_ptr->crc) { gd->env_addr = (ulong)&(env_ptr->data); gd->env_valid = 1; return(0); } -#ifdef CONFIG_OMAP2420H4 -bad_flash: -#endif + gd->env_addr = (ulong)&default_environment[0]; gd->env_valid = 0; return (0); From 0e700ce03a23bb1921149bc77008ace7103d5289 Mon Sep 17 00:00:00 2001 From: Martin Krause Date: Mon, 20 Aug 2007 13:56:47 +0200 Subject: [PATCH 190/259] Fix compiler warning in include/s3c2410.h This patch fixes the "type qualifiers ignored on fuction return tpye" warning for include/s3c2410.h Signed-off-by: Martin Krause --- include/s3c2410.h | 36 ++++++++++++++++++------------------ 1 file changed, 18 insertions(+), 18 deletions(-) diff --git a/include/s3c2410.h b/include/s3c2410.h index 86495f628..87135b45d 100644 --- a/include/s3c2410.h +++ b/include/s3c2410.h @@ -69,75 +69,75 @@ typedef enum { #include -static inline S3C24X0_MEMCTL * const S3C24X0_GetBase_MEMCTL(void) +static inline S3C24X0_MEMCTL * S3C24X0_GetBase_MEMCTL(void) { return (S3C24X0_MEMCTL * const)S3C24X0_MEMCTL_BASE; } -static inline S3C24X0_USB_HOST * const S3C24X0_GetBase_USB_HOST(void) +static inline S3C24X0_USB_HOST * S3C24X0_GetBase_USB_HOST(void) { return (S3C24X0_USB_HOST * const)S3C24X0_USB_HOST_BASE; } -static inline S3C24X0_INTERRUPT * const S3C24X0_GetBase_INTERRUPT(void) +static inline S3C24X0_INTERRUPT * S3C24X0_GetBase_INTERRUPT(void) { return (S3C24X0_INTERRUPT * const)S3C24X0_INTERRUPT_BASE; } -static inline S3C24X0_DMAS * const S3C24X0_GetBase_DMAS(void) +static inline S3C24X0_DMAS * S3C24X0_GetBase_DMAS(void) { return (S3C24X0_DMAS * const)S3C24X0_DMA_BASE; } -static inline S3C24X0_CLOCK_POWER * const S3C24X0_GetBase_CLOCK_POWER(void) +static inline S3C24X0_CLOCK_POWER * S3C24X0_GetBase_CLOCK_POWER(void) { return (S3C24X0_CLOCK_POWER * const)S3C24X0_CLOCK_POWER_BASE; } -static inline S3C24X0_LCD * const S3C24X0_GetBase_LCD(void) +static inline S3C24X0_LCD * S3C24X0_GetBase_LCD(void) { return (S3C24X0_LCD * const)S3C24X0_LCD_BASE; } -static inline S3C2410_NAND * const S3C2410_GetBase_NAND(void) +static inline S3C2410_NAND * S3C2410_GetBase_NAND(void) { return (S3C2410_NAND * const)S3C2410_NAND_BASE; } -static inline S3C24X0_UART * const S3C24X0_GetBase_UART(S3C24X0_UARTS_NR nr) +static inline S3C24X0_UART * S3C24X0_GetBase_UART(S3C24X0_UARTS_NR nr) { return (S3C24X0_UART * const)(S3C24X0_UART_BASE + (nr * 0x4000)); } -static inline S3C24X0_TIMERS * const S3C24X0_GetBase_TIMERS(void) +static inline S3C24X0_TIMERS * S3C24X0_GetBase_TIMERS(void) { return (S3C24X0_TIMERS * const)S3C24X0_TIMER_BASE; } -static inline S3C24X0_USB_DEVICE * const S3C24X0_GetBase_USB_DEVICE(void) +static inline S3C24X0_USB_DEVICE * S3C24X0_GetBase_USB_DEVICE(void) { return (S3C24X0_USB_DEVICE * const)S3C24X0_USB_DEVICE_BASE; } -static inline S3C24X0_WATCHDOG * const S3C24X0_GetBase_WATCHDOG(void) +static inline S3C24X0_WATCHDOG * S3C24X0_GetBase_WATCHDOG(void) { return (S3C24X0_WATCHDOG * const)S3C24X0_WATCHDOG_BASE; } -static inline S3C24X0_I2C * const S3C24X0_GetBase_I2C(void) +static inline S3C24X0_I2C * S3C24X0_GetBase_I2C(void) { return (S3C24X0_I2C * const)S3C24X0_I2C_BASE; } -static inline S3C24X0_I2S * const S3C24X0_GetBase_I2S(void) +static inline S3C24X0_I2S * S3C24X0_GetBase_I2S(void) { return (S3C24X0_I2S * const)S3C24X0_I2S_BASE; } -static inline S3C24X0_GPIO * const S3C24X0_GetBase_GPIO(void) +static inline S3C24X0_GPIO * S3C24X0_GetBase_GPIO(void) { return (S3C24X0_GPIO * const)S3C24X0_GPIO_BASE; } -static inline S3C24X0_RTC * const S3C24X0_GetBase_RTC(void) +static inline S3C24X0_RTC * S3C24X0_GetBase_RTC(void) { return (S3C24X0_RTC * const)S3C24X0_RTC_BASE; } -static inline S3C2410_ADC * const S3C2410_GetBase_ADC(void) +static inline S3C2410_ADC * S3C2410_GetBase_ADC(void) { return (S3C2410_ADC * const)S3C2410_ADC_BASE; } -static inline S3C24X0_SPI * const S3C24X0_GetBase_SPI(void) +static inline S3C24X0_SPI * S3C24X0_GetBase_SPI(void) { return (S3C24X0_SPI * const)S3C24X0_SPI_BASE; } -static inline S3C2410_SDI * const S3C2410_GetBase_SDI(void) +static inline S3C2410_SDI * S3C2410_GetBase_SDI(void) { return (S3C2410_SDI * const)S3C2410_SDI_BASE; } From 16e23c3f5dab6937f5109365416808c7f15c122b Mon Sep 17 00:00:00 2001 From: Ed Swarthout Date: Mon, 20 Aug 2007 23:55:33 -0500 Subject: [PATCH 191/259] fsl_pci_init - Remove self PCSRBAR allocation CPU physical address space was being wasted by allocating a PCSRBAR PCI inbound region to it's memory space. As a rule, PCSRBAR should be left alone since it does not affect transactions from self and other masters may have changed it. Signed-off-by: Ed Swarthout --- drivers/fsl_pci_init.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/drivers/fsl_pci_init.c b/drivers/fsl_pci_init.c index 1084dc6b7..3a13eea1f 100644 --- a/drivers/fsl_pci_init.c +++ b/drivers/fsl_pci_init.c @@ -130,9 +130,14 @@ fsl_pci_init(struct pci_controller *hose) } - /* Call setup to allocate PCSRBAR window */ - pciauto_setup_device(hose, dev, 1, hose->pci_mem, + /* Use generic setup_device to initialize standard pci regs, + * but do not allocate any windows since any BAR found (such + * as PCSRBAR) is not in this cpu's memory space. + */ + + pciauto_setup_device(hose, dev, 0, hose->pci_mem, hose->pci_prefetch, hose->pci_io); + #ifndef CONFIG_PCI_NOSCAN printf (" Scanning PCI bus %02x\n", hose->current_busno); hose->last_busno = pci_hose_scan_bus(hose,hose->current_busno); From 4a8527ef086ec7c89f40674ef024ae6f988a614a Mon Sep 17 00:00:00 2001 From: Martin Krause Date: Tue, 21 Aug 2007 12:40:34 +0200 Subject: [PATCH 192/259] MPC5xxx: fix some compiler warnings in USB code Fix the following warnings: - usb.c:xx: warning: function declaration isn't a prototype - usb_ohci.c:xxx: warning: passing argument 1 of '__fswab32' makes integer from pointer wihtout a cast Signed-off-by: Martin Krause --- cpu/mpc5xxx/usb.c | 6 +++--- drivers/usb_ohci.c | 6 +++--- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/cpu/mpc5xxx/usb.c b/cpu/mpc5xxx/usb.c index ce709fc65..ed467ab3b 100644 --- a/cpu/mpc5xxx/usb.c +++ b/cpu/mpc5xxx/usb.c @@ -27,7 +27,7 @@ #include -int usb_cpu_init() +int usb_cpu_init(void) { /* Set the USB Clock */ *(vu_long *)MPC5XXX_CDM_48_FDC = CONFIG_USB_CLOCK; @@ -41,12 +41,12 @@ int usb_cpu_init() return 0; } -int usb_cpu_stop() +int usb_cpu_stop(void) { return 0; } -int usb_cpu_init_fail() +int usb_cpu_init_fail(void) { return 0; } diff --git a/drivers/usb_ohci.c b/drivers/usb_ohci.c index f0a37b20a..14984a5f3 100644 --- a/drivers/usb_ohci.c +++ b/drivers/usb_ohci.c @@ -669,7 +669,7 @@ static int ep_link (ohci_t *ohci, ed_t *edi) ed_p = &(((ed_t *)ed_p)->hwNextED)) inter = ep_rev (6, ((ed_t *)ed_p)->int_interval); ed->hwNextED = *ed_p; - *ed_p = m32_swap(ed); + *ed_p = m32_swap((unsigned long)ed); } break; } @@ -687,11 +687,11 @@ static void periodic_unlink ( struct ohci *ohci, volatile struct ed *ed, /* ED might have been unlinked through another path */ while (*ed_p != 0) { - if (((struct ed *)m32_swap (ed_p)) == ed) { + if (((struct ed *)m32_swap ((unsigned long)ed_p)) == ed) { *ed_p = ed->hwNextED; break; } - ed_p = & (((struct ed *)m32_swap (ed_p))->hwNextED); + ed_p = & (((struct ed *)m32_swap ((unsigned long)ed_p))->hwNextED); } } } From 5f470948570526e9186f053a3003da7719604e90 Mon Sep 17 00:00:00 2001 From: stefano babic Date: Tue, 21 Aug 2007 15:50:33 +0200 Subject: [PATCH 193/259] Fix MAC address setting in DM9000 driver. The logic to check if there is a correct MAC address in the DM9000 EEPROM, added in the last patch, is wrong. Now the MAC address is always taken from the environment, even if a suitable MAC is present in the EEPROM. Signed-off-by: Stefano Babic --- drivers/dm9000x.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/dm9000x.c b/drivers/dm9000x.c index 78acb097e..e0d531bd9 100644 --- a/drivers/dm9000x.c +++ b/drivers/dm9000x.c @@ -303,8 +303,8 @@ eth_init(bd_t * bd) for (i = 0; i < 6; i++) ((u16 *) bd->bi_enetaddr)[i] = read_srom_word(i); - if (!is_zero_ether_addr(bd->bi_enetaddr) && - !is_mutlicast_ether_addr(bd->bi_enetaddr)) { + if (is_zero_ether_addr(bd->bi_enetaddr) || + is_multicast_ether_addr(bd->bi_enetaddr)) { /* try reading from environment */ u8 i; char *s, *e; @@ -542,7 +542,7 @@ read_srom_word(int offset) { DM9000_iow(DM9000_EPAR, offset); DM9000_iow(DM9000_EPCR, 0x4); - udelay(200); + udelay(8000); DM9000_iow(DM9000_EPCR, 0x0); return (DM9000_ior(DM9000_EPDRL) + (DM9000_ior(DM9000_EPDRH) << 8)); } From ef8f20752712dc1cdbd86f47e3bd6e35f81c83fd Mon Sep 17 00:00:00 2001 From: stefano babic Date: Tue, 21 Aug 2007 15:52:33 +0200 Subject: [PATCH 194/259] Fix: TFTP is not working on little endian systems TFTP does not work anymore after multicast tftp patch was applied on little endian systems. This patch fix it. Signed-off-by: Stefano Babic --- net/tftp.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/net/tftp.c b/net/tftp.c index d6db91c05..fb2f50564 100644 --- a/net/tftp.c +++ b/net/tftp.c @@ -178,7 +178,7 @@ TftpSend (void) pkt += strlen((char *)pkt) + 1; /* try for more effic. blk size */ pkt += sprintf((char *)pkt,"blksize%c%d%c", - 0,htons(TftpBlkSizeOption),0); + 0,TftpBlkSizeOption,0); #ifdef CONFIG_MCAST_TFTP /* Check all preconditions before even trying the option */ if (!ProhibitMcast From 7608d75f9c87c9eb5b3a43219d0506d3e979a13f Mon Sep 17 00:00:00 2001 From: Kim Phillips Date: Tue, 21 Aug 2007 17:00:17 -0500 Subject: [PATCH 195/259] support board vendor-common makefiles if a board/$(VENDOR)/common/Makefile exists, build it. also add the first such case, board/freescale/common/Makefile, to handle building board-shared EEPROM, PIXIS, and MDS-PIB code, as dictated by board configuration. thusly get rid of alternate build dir errors such as: FATAL: can't create /work/wd/tmp/u-boot-ppc/board/freescale/mpc8360emds/../common/pq-mds-pib.o: No such file or directory by putting the common/ mkdir command in its proper place (the common Makefile). Common bits from existing individual board Makefiles have been removed. Signed-off-by: Kim Phillips --- Makefile | 2 + board/freescale/common/Makefile | 56 ++++++++++++++++++++++++++++ board/freescale/common/pixis.c | 3 ++ board/freescale/common/pq-mds-pib.c | 3 ++ board/freescale/mpc832xemds/Makefile | 2 +- board/freescale/mpc8360emds/Makefile | 2 +- board/freescale/mpc8544ds/Makefile | 7 +--- board/freescale/mpc8641hpcn/Makefile | 8 +--- include/configs/MPC8544DS.h | 1 + include/configs/MPC8641HPCN.h | 1 + 10 files changed, 70 insertions(+), 15 deletions(-) create mode 100644 board/freescale/common/Makefile diff --git a/Makefile b/Makefile index 2e15ceaf0..0477cd3dc 100644 --- a/Makefile +++ b/Makefile @@ -190,6 +190,8 @@ endif OBJS := $(addprefix $(obj),$(OBJS)) LIBS = lib_generic/libgeneric.a +LIBS += $(shell if [ -f board/$(VENDOR)/common/Makefile ]; then echo \ + "board/$(VENDOR)/common/lib$(VENDOR).a"; fi) LIBS += board/$(BOARDDIR)/lib$(BOARD).a LIBS += cpu/$(CPU)/lib$(CPU).a ifdef SOC diff --git a/board/freescale/common/Makefile b/board/freescale/common/Makefile new file mode 100644 index 000000000..44f613e41 --- /dev/null +++ b/board/freescale/common/Makefile @@ -0,0 +1,56 @@ +# +# (C) Copyright 2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +ifneq ($(OBJTREE),$(SRCTREE)) +$(shell mkdir -p $(obj)board/$(VENDOR)/common) +endif + +LIB = $(obj)lib$(VENDOR).a + +COBJS := sys_eeprom.o \ + pixis.o \ + pq-mds-pib.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/freescale/common/pixis.c b/board/freescale/common/pixis.c index 99cc2ee19..ae4bef187 100644 --- a/board/freescale/common/pixis.c +++ b/board/freescale/common/pixis.c @@ -27,6 +27,8 @@ #include #include +#ifdef CONFIG_FSL_PIXIS + #include "pixis.h" @@ -470,3 +472,4 @@ U_BOOT_CMD( " pixis_reset altbank cf \n" " pixis_reset cf \n" ); +#endif /* CONFIG_FSL_PIXIS */ diff --git a/board/freescale/common/pq-mds-pib.c b/board/freescale/common/pq-mds-pib.c index 8c013c72f..d79f2eb2e 100644 --- a/board/freescale/common/pq-mds-pib.c +++ b/board/freescale/common/pq-mds-pib.c @@ -12,6 +12,8 @@ #include #include +#ifdef CONFIG_PQ_MDS_PIB + #include "pq-mds-pib.h" int pib_init(void) @@ -100,3 +102,4 @@ int pib_init(void) i2c_set_bus_num(orig_i2c_bus); return 0; } +#endif /* CONFIG_PQ_MDS_PIB */ diff --git a/board/freescale/mpc832xemds/Makefile b/board/freescale/mpc832xemds/Makefile index ea52484c0..5ec7a871d 100644 --- a/board/freescale/mpc832xemds/Makefile +++ b/board/freescale/mpc832xemds/Makefile @@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a -COBJS := $(BOARD).o pci.o ../common/pq-mds-pib.o +COBJS := $(BOARD).o pci.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/board/freescale/mpc8360emds/Makefile b/board/freescale/mpc8360emds/Makefile index ea52484c0..5ec7a871d 100644 --- a/board/freescale/mpc8360emds/Makefile +++ b/board/freescale/mpc8360emds/Makefile @@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a -COBJS := $(BOARD).o pci.o ../common/pq-mds-pib.o +COBJS := $(BOARD).o pci.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/board/freescale/mpc8544ds/Makefile b/board/freescale/mpc8544ds/Makefile index 308f707de..006fdc95e 100644 --- a/board/freescale/mpc8544ds/Makefile +++ b/board/freescale/mpc8544ds/Makefile @@ -24,14 +24,9 @@ include $(TOPDIR)/config.mk -ifneq ($(OBJTREE),$(SRCTREE)) -$(shell mkdir -p $(obj)../common) -endif - LIB = $(obj)lib$(BOARD).a -COBJS := $(BOARD).o \ - ../common/pixis.o +COBJS := $(BOARD).o SOBJS := init.o diff --git a/board/freescale/mpc8641hpcn/Makefile b/board/freescale/mpc8641hpcn/Makefile index 93b015d47..201da3ebe 100644 --- a/board/freescale/mpc8641hpcn/Makefile +++ b/board/freescale/mpc8641hpcn/Makefile @@ -23,15 +23,9 @@ include $(TOPDIR)/config.mk -ifneq ($(OBJTREE),$(SRCTREE)) -$(shell mkdir -p $(obj)../common) -endif - LIB = $(obj)lib$(BOARD).a -COBJS := $(BOARD).o \ - ../common/sys_eeprom.o \ - ../common/pixis.o +COBJS := $(BOARD).o SOBJS := init.o diff --git a/include/configs/MPC8544DS.h b/include/configs/MPC8544DS.h index 07631b921..9743f031e 100644 --- a/include/configs/MPC8544DS.h +++ b/include/configs/MPC8544DS.h @@ -181,6 +181,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CFG_BR3_PRELIM 0xf8100801 /* port size 8bit */ #define CFG_OR3_PRELIM 0xfff06ff7 /* 1MB PIXIS area*/ +#define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */ #define PIXIS_BASE 0xf8100000 /* PIXIS registers */ #define PIXIS_ID 0x0 /* Board ID at offset 0 */ #define PIXIS_VER 0x1 /* Board version at offset 1 */ diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h index bf25f7f4f..7d8a380dc 100644 --- a/include/configs/MPC8641HPCN.h +++ b/include/configs/MPC8641HPCN.h @@ -185,6 +185,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CFG_OR3_PRELIM 0xfff06ff7 /* 1MB PIXIS area*/ +#define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */ #define PIXIS_BASE 0xf8100000 /* PIXIS registers */ #define PIXIS_ID 0x0 /* Board ID at offset 0 */ #define PIXIS_VER 0x1 /* Board version at offset 1 */ From 94c47fdaf14cb29fa3fb4d4da2efdd96c803b46b Mon Sep 17 00:00:00 2001 From: Jason Jin Date: Wed, 22 Aug 2007 17:54:49 +0800 Subject: [PATCH 196/259] Remove the bios emulator binary files from MAI board Signed-off-by: Jason Jin --- .../scitech/bin-linux/glibc/dmake | Bin 70812 -> 0 bytes .../bios_emulator/scitech/bin-linux/glibc/k_cp | Bin 37612 -> 0 bytes .../scitech/bin-linux/glibc/k_echo | Bin 11924 -> 0 bytes .../bios_emulator/scitech/bin-linux/glibc/k_rm | Bin 38300 -> 0 bytes .../scitech/bin-linux/glibc/makedep | Bin 58623 -> 0 bytes .../bios_emulator/scitech/bin-linux/glibc/nasm | Bin 263498 -> 0 bytes .../scitech/bin-linux/glibc/ndisasm | Bin 100192 -> 0 bytes .../scitech/bin-linux/glibc/trans | Bin 9244 -> 0 bytes .../bios_emulator/scitech/bin-linux/libc/dmake | Bin 71264 -> 0 bytes .../bios_emulator/scitech/bin-linux/libc/nasm | Bin 168228 -> 0 bytes .../scitech/bin-linux/libc/ndisasm | Bin 66888 -> 0 bytes .../bios_emulator/scitech/bin-linux/libc/trans | Bin 8984 -> 0 bytes .../scitech/makedefs/makedefs.prj | Bin 9025 -> 0 bytes .../scitech/src/pm/os2/dossctl.obj | Bin 59 -> 0 bytes 14 files changed, 0 insertions(+), 0 deletions(-) delete mode 100755 board/MAI/bios_emulator/scitech/bin-linux/glibc/dmake delete mode 100755 board/MAI/bios_emulator/scitech/bin-linux/glibc/k_cp delete mode 100755 board/MAI/bios_emulator/scitech/bin-linux/glibc/k_echo delete mode 100755 board/MAI/bios_emulator/scitech/bin-linux/glibc/k_rm delete mode 100755 board/MAI/bios_emulator/scitech/bin-linux/glibc/makedep delete mode 100755 board/MAI/bios_emulator/scitech/bin-linux/glibc/nasm delete mode 100755 board/MAI/bios_emulator/scitech/bin-linux/glibc/ndisasm delete mode 100755 board/MAI/bios_emulator/scitech/bin-linux/glibc/trans delete mode 100755 board/MAI/bios_emulator/scitech/bin-linux/libc/dmake delete mode 100755 board/MAI/bios_emulator/scitech/bin-linux/libc/nasm delete mode 100755 board/MAI/bios_emulator/scitech/bin-linux/libc/ndisasm delete mode 100755 board/MAI/bios_emulator/scitech/bin-linux/libc/trans delete mode 100644 board/MAI/bios_emulator/scitech/makedefs/makedefs.prj delete mode 100644 board/MAI/bios_emulator/scitech/src/pm/os2/dossctl.obj diff --git a/board/MAI/bios_emulator/scitech/bin-linux/glibc/dmake b/board/MAI/bios_emulator/scitech/bin-linux/glibc/dmake deleted file mode 100755 index 4d6ccb3f46ee6c0e2ca1e75884595e043b3ec097..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 70812 zcmd?SeRx#W)i-=5nMo!vVS)sV8Z>H9P*9?v1c(j^6CxiHnUJ7{uWIm+B1AX`K?n?; zq~>slOmLVq^k64$oK~Ruw2|5{ zZK#%kaK?>`A`QML;OFPV=f#(f?@fM)<2M9;evD&jPKod!j^BA%9*rOKYdKDQF5uj6 z`TYELrfHf!Op|&U4^XQZ=+P>^?ep_%0nCqhv5sq(E&al^%kCbtZ0T}y%{8l5TyveK zl_7i%zW)Cv0w7+6Zs3h@$Kqq!+4u_Z@n12%;rPxYfPWM4O%k7`-2itozDyTp+o$52 z?!qCsx8WP*!gR*tE5ete1KV>oz7hCH*IV%MUy0*r16;Slb+2{ZAlzyAO7UHW?^b+% zeEfG4zASt*@D0V6i|-127vUR&?-G3ccfRAu-*VS~q3h=LiyQ3vN4oA+{o>Fi+RZLZ z`ltR4bUpd0fd4~xX1{co!jJ9)-)UMlzKikkU!~({SGw-G&S*Da);SSV`oWjOe?dPu z;Q9x-ZrF9nSHhbvOy_#ne@(xzlsDC{gbVPIp5#+F+FG6lWe)1f7az4KNHm{$3PWWzowSbSh@KU%VAM^Q1 zGnQww0(>0! zZi37FFXKD#l|KCT0e%|z?RLxmFTnYzZ!BQee+XXy@@Fqx!hgi~7|Lsb%ktjEHyP!P zPjliw0K6XXdbmt~9A5zCahwtUC%z-d|Dp?@hWi-Ox4ZBexCapb5?q$=1s*-f|Gpa! zQKM}EJk^DB06&fNxnK&WzYK5yH+a>d(6XuSfnuH+?~T z9{@ZVa0Xn~_a(T?-1>-L3*dw3&r@(OMT)I(qy6~jalku~|LaK0^xp@(1^K`2!ao7r z1AN|c;b#FKL3>mE@dD$K{>zAG{Vy{=%A<@Vybthbz_ts&26!j(lTR6c5b*kb@qYq5 z6Yvr@{wUyO{mT0rVdVFvIrx4AxVB&Y3BXSSrp#vfp8?(pxEU_nmyUc#P~JoE6Al0# zjq;v!;atE60AJz47XY4#{G2D4{$j=>e+SBA`6B@D1btHRqX8dBe8^3I9pE+Ycq08L zo&%Qw-h%w(N0xUB;3KFnm46oCr-4rjjsPCrFa8d|sq!fg?gpIdZ^HKh=KPPMG2IT( z)&SlK`9zrVYa`S5lV@K(2mTu1^*`%NuPt17&%G;_FI;6TUTG{`s9}1(i_`KA+QO-~ z-#TU1EoIumX)|Y+PMNuIc6oUuT(z)jO6kn-LT%xarOTIUbt_jcU!g68*FZ_kEPh0; zTxDpBjk-06kUtA=nT<;BMuvsjl7^K_mm5p8B}t8{IZv2x{I`brdVm$9~?Zs8Yt zea4DqEAFrBi!oN14Gn6sA1wR9nT7tx)D`Is&g7@aN@uVr-0G_8Rylp}*Kl!P^Op=hnA3uPcm7Ya%f zT_|uZbfIW%p&QV&HoBK;+E%(yjvk>q5we~xl&>e~UaVO#6#p+D(D;U7&GO7vK|rO>(Q-h_FXE`;i2x)A0e zxt?SvNzyp!;L!j%HI6Fx{dB=A1MhY61rct7Ez zgbM^dKv)sZ5%?hC6NEK^-z3~k_{6{2{=Jl>&3b>6L^-0(0c) z^9YX>m?KbMM7Tg;jznE2oFgztq~1VS6PP1YUqkpr58KZXsz(VQ6__JcZy|h8V2)V5 zjc~ib9J%@ch{HNuA3# zbwJX6T#41GBLAOiYipyt_;m%y94p~p%@|}Q?DXWp*j{gJl4hQQsCad6>uL?@Uft`Y zj~&misgBsQ{L!`ZwBVMDyqeY-CKG9~wY6IC;r0N-{w*;hV{3A?VDoe7C^?ji=4xF}(I4(%E!N)Vc4G!`DoVuG zWJ+Nw1#^sBWersp!9C_O$c8r+#TDO)0{8{)NAS*%of1O zzO$hD9dk#lv0F2T+2Nj8$w;b&!RCp`*;Rr+ZAFRB@F~{HM8?E6dser7dqL-v0)|D` zj?s+4w8;;Gh%BBHM5A2c_r(fQebNgGlmoLNc154wgNj% zLes6esLi-_7m3#CJMxUrPhX1i`VsO$;X+OUAcr4Ghgpg0@_J81eOE{yaA6( z?=BEJC44hM7r!wIz2qT5S0b&oH?pmg{a2}vX4=>Pl}tv|JaA!bUx7=s&M<`yI_@~J zAPIv_AHZuRiV{MBJk7WzR;(F0$@}sY7dRxDH|}k-O@H*(Du1!*H*z=KTBU`U{kUdk z63AhTx}$4HYo<4P>%1t+XEmg6uxSR$2aWA4YnGxr#cPLht@6n>z$x=a-27b_p33JX z%BynF=jBy_9Q(Ga*!zW92d(ldd&*d=d@NGN)=tojD*M(6)~sX9xOPHw(wK_Atq;_D z)bG($Yp>AH^r;abQu0PMeG0Ho2llbXW12D0o^{N+-5bw99&5n_YyL5NqqjL}zT%(+ zwkF0>Q-x++6Wf5lm!P%gg~|IWlB+A!ip3nJpM+3oc?DQHJ^;Lj7E}Nfj79^aFSOa2 zww7Ey83QfV$I6ERiOx|kR%qI$3ZWK9S7o*O<1OsYf>d|rMxX(p2X&qOH>jIE7l^2b zAuu>N1mDMFjVClCmjxuv6V+-fiilSD{TNH=0t>usp0IBj365@lHQ0OwBuw1j+#YPE zyi&jPXyOogbNrbA>FkV81R`cBmhz}#(!>3%q)CxRX86JC? zf59a?um#T!TD^oVV6Kwi15@5`mQWb>AyS}S}wqD}#KtHYMs9HIC= zLPml6bDI;5X+?>odDzYK8|fHQwdp8$8xiVP%)Q4tffVUeazU@+J;AT+MP$9EKlT&o zbV#!rnxoac2-u)kAu%s#eVM4)4f#DU<^i{p-?tl|5P4OUjAwR+49Uj&`L2+bS8h^#%G%`=e;Ud@%+ zrnmW!Ilu`9j%dh%-l>Q@grVn!WDQkT+fpG0O!9e_Az0=npJy*7pC>aVpRdH9+mg?d zL)91AW5TTQThRBYB^-NMc-Nf#KNd!2IIA#wRv=lVEOPs{shC#7A#x8A41(SKIfQOo*reCg6LUUp1Ce z>Cx;9+Q2bmtd9|j{B~M#x{+zmVOO4PK9tfVfM2>5!NlZ6NB$1b2>SwLyQIxVU|D{s zSk#C{-o|FCOnip$8+e!A^Tnos~&9fqYv@WByI$%X|?78_?BsXb}RIgx>ZI$IG%|i8@ zc=N1PBT=apDcC%>pd~VT^W4!bkulryuz6*b6L~EylpKiN1nK_YV6J*k zeNx{Aj*h7G3FJry*cq5E8xV8?>u;uq;+2mKTgZ*&`Oyhb{-UYO?UK1eQrbfwfm|Ki zZvC<6MO2mi_!(>e>4O!O$<_ID)LkE^1`@P``Xs{Qmw;~ck8QV0n6rPb^zwXYr^{Uo zas<&mQr8{*!*;xeu-FDr)3;+EyvQ>#6)(YqlB@F~>Ic#|aA~X&NMXg zxfp=vhh$C@8XSj>MQ9*tSzAOMcEfUFjTkMLMv`WZE4~jPUZ=@P9Xr9Xu^fz9^iIEF zE^CQcNj~|;Jik7mYLSlRb2tuFXR0(UKFA)_7S%Z0V##La)F-iM8@`Lv4h7yzPNh=K<)CGHB6LU8JWqzU{t25u z1&o5UPQ~vPwfC35n~pz%y3uu=;jQpsb<*ZI6as)+9H+@~qT)2KM+Xq2&gM1naq{YH zHhO(jVI*CcMWc+z9OntgdD3y7a-65>w1!VX=fPy&8djC+2JsxJRAa<*uu>JmLmivk zg{fsc)Rf}sxyBeryUH;xvZv%qd)?8Qbq`uSW<5vnj(G!zQ?c3| z_r?C=!EC=Wq~FLaZJZy%&rQ~IFei|3-po5U3e<_UbM*+nvD~vI* z#wavy^zzqX&;gWzD!+LL3 zkRL1YGt{_b8{N%XpkVS^^SngqT(7~diQZC`6VD@#V1zVOr*C0JX|rWGN#9Mz!n$+H zHOxSWRbcPl5uuO+`$B-l!MI`SlR6ideI9a75LEw6j z7@;ngT{S_t%pnq4Cuyv}xVavZ=Q^EfYQP7Y?Fd?+ovhNiqXSi$PCQ!@wKAQeQy^un$`07LQ|19n=|yJ9T5CzSZTfyn^4qJcE`6SW)wt7c+yNG9eg#4r)w&EtC8Q0EvLIy5KalEw z7VF}0rCnZIJf(KSC63NI6?$nkiJntjUb|rc%b8PKYE{?T&`pG2fJSw#^)MlHgUlGC zu-LK}`eT2A5TjBQlnBfhIkJ{xdqFM~xG@L|m*2QLR)f=B#YTEnRJ6J)i*ZD>SFs8Jz;G)*(7yHf3D zve(c5N~uQlVryq=#s$gyW(qUvw=wqX5*vu0kMRgHh>V)ghzFc(XA6`6z8;Jjezrb< zw8@oI^}CpIzXU#6kGW-wUdNDMNyyW&eT58c)9+#6HVJ%+AzSsO4Ec(LJi(9_{fi7~ zl#oZ5(Gg;k^?Mm!C*h9~!_u+a58!}NeY(CM&K&h|13NMgBWi>#{e^~-ch3i(`eBlU zsBt?Y*mRQs^PXa_WOs&}*t=bsFzB?UNLYy6$@^-P&$H+IPopb{#*$+sWp1qG06R9= z^fuT|a0*%B1NI$L6FyG#7#*>aT2|sLXiy|(_mDXmy7&)*C z=7$3j{ZT~5v&8#jru+CWtTW)2XkM2pZB$V^hF8c)Zw())#9HBidNV>wP&dfdcQES< zlGXcptgfK+W38NTF94vw#qANx!BJx92i(u1#p_!nj*BpGCNuK<%Nvrt=Ub!w#d2M{D+<^I_-d$VH!Y3_9DKu*c}&>d{&)19ROh5$#g zBMAkoD$UD9hGitC%=Mb*vm1r^|42$Ko+cH=FJ!G1D1~{mL6c6gU=cNELJc`moY|nAuHZEqNU{$K+K)~9YTpfz2y)@j5SvI0-WXR?w%I^pn(8ofw1*{IK zkOX@jqnNt*D&iFq$sJ<5`pKT8`J~!|;lN&fN!+K@FT{O9{aD<`)c3@FL_I3*v+8Sb zQ_4j?lnbmqpj*JGGZ9NFF5}8!kjcW9dUBOtJ?}7mY#o-%FxdpulM;Xw-*!CAX?8ez z!wd0&ZO}^p4c!K4CTEc-N%QZq#x`a)+tfX7p2n>buvJy30$L=XMTJuVTO?qM8s`LX z+i3VdF~m)!hKhScWs7@I`QX~&rq=J*BEFyfJa!yRMb{xV9sN}#0Kqkd1g!-Nq?V%#~rK+vPBpf%mPbcb8vl6m#8)Hnh zx)L0SF^*l^A;oDaOXnxBbT>1EJk9UR@N4jO6+MLl6?#3P{ zLGYw2y|9dISw!XxK=v4mD%BpG{K3vbn9Cf9;lZ%WjzwJ|T2DX0_nTOw0wbbal%vJ3 zgnr3At>nAXCN>&ftSZZZ>Yd)`48PxQJZ`P?TGz*I;x+fw=5TjQn%#)ahd^<$ncYcz zw9YAhI(9hFT6d(+M&a6ShRR?IaY;1OlA-Zz^*ED=kHWS*2(Xy0RGT(Ys}W#qN1n zStnPHRJ*DDaZ9QYNLjZbETDdx3JbXWW0Zj3u9phFg9^Ao=n(iHQ&9S(-g477EvmYC zBMMAsVU@X#82$~)-?UgF#6oh8{i#BX80~0*W@mHON8W+c=UKB3bcXjaG&N!S61&r| z!VB}{Dml=egDuYjYwmtKn|h2j>rDo_T1~8RKjzRcA*D660pt6evM?1K=wDo_jy!I< zW2#DyuRTB0vUB-e-f0H#Ov#;JE9oR@G=7%4IrBvZL;SjR&}Dm~|K%hFP@QeX%Eq{C&*keEAf{Sn7qVUc;uFRIh{2oR7NTN1 zj1&nry@dLuC!3!oCMWevCDYc+B@<;uUI#coAmO1(^@Xa}}artjHMG~mP}l1qL!2=fMb81nMCqM5=KV74{8%~xZ7PYt8KzW@6~CYj zi+$fXn+5FE`gdHGaMl4rJv3ktb3&!u=9mdE3wxmT_D2)jzdh>F3PIG-gMkPzdDD_H zBtmH(=D>g0VOUn5K1)CGy6Oqgfqs=2(JP6{&;N)+NR$BTp2I{cux%MSWwX{2?&%2s zyS5{IMzh|g0Kr(0w)**g*`pQ>Cc_@ijqB*7E6q~ty|L}7-GS3@ zShISf>j$2>(!8q7n%@&q4VMt3&!y>@I`E7p2W{e`+PI(EDSn-`Hvy&4R*G_-AFAs48$45!Dni++Rq`{~%KxeXXq>OW+e8z5HH zHuSeU<2XAGpdqY}%&M6~VvYE_UjGS`|8b(UMT)nv9d%J}+XhASKQYC(B!!<6L@F3A zax3t;7WFW3%UjYSTd?Fdkzjkh($Khw`V`Eg!0kN2D*HRJ2+oPFpk01DY@*mce+^B9Am#pdyJkU0+u^+(coPzH?YvBsm^?v#zf_@Xu{x`S&R zwOYqHWJp?fIAlj^RCRAijrtJXoHUQ9*Yh1jWHyp?qusS>Eq(?v^tposORvr20zqY!O6Se3w!MR<~KnDBKeL{2;HyDTO95&gURcwRZlPWnf9GrTfC3&CK<1r ze&2t*{vOunYW1%RQQ2;5Aol$*Zi6q(?Y6xSvv90JtbFms)9iuP{?@wV(nV*>IcSn= zFmsNRA$x(_Y5E-`*_{~n+Zh2toG63+=1$N^)VEbrYt+3{P;Xf+v@aex`WHq_$}j~> zL{Ab)T+7}USk@okV3*|9s0A3g_7Eal>bE*K-8Ju(7rMu+Cf$4ObSjiu-|aJAfh$^3636Y1_qmdjiTIkaW-V4ZETFBtm>cg zt4NtBy8{-u2jN3fj8eAH4)wLroEa;b2N|ImW!vadGb)a)!@A;nq=mf{=vJzG#fmN^ zRM)5(sr)=U1AFsq#+FS*tNJLlsI5(k!Gy9-Oem{D>fhiIQ~?c-^fU%cl_c1|z%B~`v3OovD%YUocxF@2x`naU3!*csLW#0Fy+&|JY+aSM-mkvuwD7F` zX4m#GD?q)u8wAC9-$H1blR$D&q*y!lyr&dyFGLk&o&xqp>ICgJhPnspI9>ks5ZlAS zJP=nFm=Y5f_Pt;E6{z(h3~pM_Q`*TNn7KGiideUf27ml~j89N8qGn*|SE@J8M^-Qg zs3_+YtJP0#lGNC%bC{UtYH|7&2O4I$bTBjIJTJE9jS1(H=3&7LopVYvU3AZzoA~s$r+A*9%Ex>sAILsL$Wh#Y;A&Ow1UsoiUY9loPNW5!-amt3-)oGJ@k^Pb z?CSKYE9rTxxbdK_H7~zD=)nT5ehHluS24N#r zvgdIMXyP4ueK!(ER2~y!+7c9giI(X55MHA+hSQ29efKCLXrZZzsGAXiP^+U_fwRbj zkf5yN$FecoQ>_+53PjYM_zUAosIqlhTBXWjaWF)5kLvE2nsH_nEHRV-)p{pew}M&s z!X|<|tR|xV4Px{aJ=-Z7R(R}_uv{FN-koM)sShL0)osjD?`fUozb&F#GKn5m+=A0E zCnNaF8E@zd7=nY%hfus6p>Tv{O2#{9I08swLel!X4x`zK!>N(6?RH}zr4`C)ACQw0 z3A*!J>>C=TxJ&m0Nhn=bPMT98Xp1%G;aIOdwNG(fz0`?!!FP=qIB&%AC`7XL1YfD)&_Czb9ssQO2v^>2UoIdK0t`n7Y)@w;%2>*m4j$jFRu zM89-o_~ZAB8;GwEcR>6eakJwK#m$P>h&wPoTin_>&p~u#To%6>ZV}F81$R}aZ99m? zR$^+U$8TKBE^e(oe6Y1Vt+Expt%kfNEI2Ke^lUhkify^LH~!?S)cc&%n4sH((lhcDa&>UlH zFvDdg8$vj}nSf&a7Ooh|+9m#sg=5e-bNE|G$@zg;o&P-ytwh+LhhuK@xe1DcT`d0w zD-ql^thdQt;}R%e+1vOAz-Dh-oaZcqyE5#dyePTZ`=yqQa^x}(puoRjEt}XKGUk20 zN&Q=MMXEIr?w3}pg@R#9k0y$X4>%}dS(=5tG{;7Y@?UX8_Y904_%ee{Q{el2U0gr( z(QXHpP%@!WWfwzEwc@QgnIDT!;t){SpJtALzC3+DW!kAxhgLmq&?rD`o*?@dTTv z!dGmbf))S|=-iP}P!8BU-E|cLAa~3_(L3y;$yOqIQ-R^%oZ&q^*>nFusJ@q5C*_)`V2YO3DCfP4zCV)yYtXfr~f{407$|<6n6MwZW+IV7tIS8^E zvmmA_99jWQ8c$qpUgm^}T(8M?WIpUlgIqRW`x|L{p#|Yq*oxk~2(>o#0m=K*X(oCNc zzc@N!ota)59~PZ3%FM)p?etsX1ELceO&>NdJkvwek^{)oj=VdY-Z5d->%AuyJ5C)2 zS1Nd-ob$?9Hbi!(zz?Wjn_OtD*f@OhfQ{Lcvl>S=wHqV4{)%xixxmQpIsy-9Jb9fl zb8=&_i5Baw{Z1J2ih&-ilgFvkKk7uK?E72}V{F$SkcjdER=cl&>`;Tc)fEE}!RH&= zB>aAM2NfUWrImLHX4}@e{y8vzKEd2nBEf2xkl5hF1F$AZG4Ex$4akd+X8()sAxVBD z2B#dW6RXT_^=&|CXpNeKaf!~T?)n4_(T3WByF!>{|4M570SpWjpdL5>5V2f#5eFm! z8YZnqL?hPNqZ!pe=0YH{5cLZp)hR@B;zg7h^$UoL)P0GI33=jgJ?QvwH`dFjt48gU z8uNaQCTj8JE-yJv>;i$HVYv9e0|@!5)z>877AIePlC)Xqjr$X9=r5dv$Vp1B@vJj5 zW9@124C&vH6^1f7TQYmW1YLg7yqK;Ld#2E_PQ$|axiS|xWuib7g(66XoUQ{*+JAjJ z)=^vBn`NBt+}mI7h8AVbP)K`M+tNE+Y8yi-c8eU2{4R*q<$>A=TT7vNez_CX#qNnQ z>I1AktiJnk9uYuoG{2-T9yo- zh~EXe#6I(wcXF4`oGXi#*&@l%OzFTWZH%Af?hD4R1I^hmNdtbl%%zO=2U#a=p4Ef0 zeTeYPz^x>)0he>>L3u5AyRuu$la;Ndp31lnbyv?(w{dGjmH}d%%$DMz#&;d0otc}5 z!+86yxX>7Mo0_l|JT4Rln?8h1$hDOfwOc32KY7ucN{swA(r%zJ zu#ARin2bxzkMJkhY@xLnWLI&pV?|Uh2py?b^U?6uRi5B3j%e7b)fUVuY#SF~=HP1G z|3x(F*CRly1-Jp^M;RZG=TSx)%fQ~zg(w0e+Jg~&gvSH!Ao0Rz3n+U;_3Y(nPT;Tg zt{7)sF_ME8h^mkYk92sjsV5y?@bBT4{oc2r#Fxjqrw1QAgivVlwZHZH(O(CDhc|iN z`25%M`sc&WP1keqf1hTnTgDS`ci?-vUzrE{`Su9L!n-FB68~olbyVsxAwXxUl>sr<8_jKLU>-Trv+3PRpn%(Qq=_+&lVgkNUA4L{< z1e;ebM}mvHXzyxcUmh#BPEHtP1RcH%mTjJOY{EeEp8{gfd=B&0%Ep&h_6)#a&74od zN6M^s!7EHZ$jEW|+MmjgWDA%KXFZRoH8_@Sh2NyNbvN1V9tL#OsEvRy;dmhb5qnC# z!pj|G&Cv)@ixFF`?!;fzW4#Mq;iiefrtuJ1<-(BWKe{gA44aU44%62V*JojGcH7xi zidd(O(SH@1b=)bNbs9Bb_{c_3S%hLrJr9}90rLj$BZM*NR69ou#@t~{kTPaI{KQ49 zfQ{IXcoJ~~i0F>MVli|3**ql+H{?x%{(NMA2`p+xI!!v20ouL00!*Zb~o1lr?nYKumAbptoHfpV5YSE5N%P z(Mju!lJfY(=%hwtJXS_Ux0=_)$2#GVmyKpYePcv@uq!nmq*;5*;sGmxq!}_@&48}_ zUF$IH>*=j!NpxV3dJ}VuSgm-^<1%Wz2-WkKp@Ai7?0b7|PA5E~w#3I`tpyOgLxZ6D zHSRxH9b#swRv(G2Kj7{w7yMeVV5;YV5cS9lsT=pZPm{85`lH1l`wvklW{0u?5>1;kRv2Q6BWcH?X0+jIXAbR73pV2+78Hg#^Ri$w4RO)69{5fJ zZF^P^O6oceZ<`blQU7Eeoudw;yJFqg+Kf)R442`_iD}knFc_g+PdAo)4Qa*WC&TXD zI4)K)fmVL(?2e~L{r+WP`fBy|OUdMR1_4z$*0YwIkdn(bd#=Vi1;E$M^b9DpjcGf) z8JdL(I4QSp$icZzr_|pH2?LC>hccn(M29y=(=SHnxJf=lebh)DkYa-R4+thrt5J8b zX&BN47)!zC02tdPT93L}C`;ob&6~|nLo9L)<403yh&$Ea5QjVT9aBALWC-HSu+-?- zM)g=jbv4$?0LL28r_ZA3R=UGkaJ zELp3-0A4E$0&8_QR5HkKfV4UGx3|h3Aa-GRN`C};n6%=ZU?jho$>gur+2<5sFi&#GfGcUj-IK4a2rsRv9fF^7QYK@pf8=_O?y>6gU^wXqCuM|y1; zOb6+uWi&0niDU!x%RxW2`65k2x{fjrMp??r#`XeLEO1R4$9Qu&YX`eBj{9xaUXnkr zjeFA7>KhLEF`P4GUh3*4+W&bOb5dm(|NAm-M%PSosvpO>U_yp@Me7VtYqckeEjc3> zVIG{m$ebbhvXgg@tUFM8lftR_pHv=BP7sL?0aGa zLHKUIpu+=2-~`ry5d5h8f=vNP>#oc3 z2W89c6eGJtiz3N&T@>nVc6Gj8jzfc8y#I$ZfaSh?CPFuB@wBn+EoohUapIh-#(w~S zc@1~nc%^>-a~w=L*4|CHhm7qgiER z1}V;z`~wATXHZJiKLlC0jR75)Wy4TT1v9D3Oy*e*zY`?MV$}7;d5s&e7SGI=F zR6=0TKE@%R1JQM#tZl#Os9)CwcMa*a--b-cn*u6gS;mm)qyfgDIr;qmbso)__lQJP_2gm(Oy#hz^|mvaM+ zFofekL*namdWz3va;d6>ONw z812wZ+O%5Q?OyQQK;-Yb8$%ts`y~kA3_TkQdt{># zl&FPd#N(PnK;16w^rEC3<3c-}Gq61ODKC#G`1L}T_Ok4M$j0mIXf;mj2b*Y4vOWVJ z)YnGTj$Z;zhoOy&`k#AS_^i|!e;cwj{ucG##GV3kre20(Ym^5V;mw?GCo_%F#>jK0 zxz?%aXX3P9S41Zi7@tNbWEr1ygz!XQUCw)QW(VWbEx?Nc%v`*G0c>EtpOquKt`{P& zUXJ=AY8I&JP{1Sw{MLd1-jH#g1_4<&z3&Cjq5UJ)p{w|`5-x-cJz-oTXyb|s2{N4o zc?7$)*jZ0htCeU%-xC{<%kKSp(_cTbT0Ox|b?6dodIc1#9~DuPKoe^>d-_%9y`AEd z!7qQ0bX}J$3^qLiAC3YRzY+X0Cw?g1P%LBcVOHr#*R0=1Cyg{q#~!lYYdM(GlX_48 zjWS2}X-^U==lz@$feS=+iO!f8qWr^KAFe8c>-%N&c0#~Y9a)0PHqD;rg-DN;EF&+Q zx8SXmFm+ZrL{+VR$7aJO9f)nr*UXV}Qhe3VdK(K4{tb6^7v|&Hk7+#JVcm(xcG_$N zK<@O{5uGuUm^K%tMrxC|5RY9ozkWaIoGV+&u%A13hH)nj(sSTh^~`5Icw5A8-BB2? zqFlo1*gFd4ag^-hNyZeMNhe^Q1Tantc%rtTpA%J%jInCz8p+@p5}SHD#lNPjI~hp>7>aoj-KnEi?n}+Rr`2<5gQw96+;roll)E{-C9`bWN=K$<5!{~ngR2bd75Bk!i!rN6}*cRl=aq~`qJC*7Ghq6-n`@4@I{nJQa zfUoDTUjJisQT{TwjFx`&uXX)T!hI9pbNJRH-9EU-@a==2^`F8=#T0y&yrF)H+5)Ca z^6*!n>m-2Hxa^Q4L zb6^fziNDc-Id}!W(t#-)1U_Hj@G$`f0O<5_C=2)*{-SISSt&bC*pV-FUGD;L{Nb)c z@T={ZI&g8d@LFI&`vk^Tygdy1 z{yPW{Bn(k_4*)gs6zL!6szAlCsjN$m2{s)hJ$B@UVljLUqf@6f{i-}Im*3Y^JvToOJXIg2uJ%}>AF#i&tg8LFs`Z(w3cE2 z|31>@V(jUCPBpJhKLdKjFKW}*GtCn0QN{<>!+wCe-U5KSL?AYwfV$YlbImBbz656< zf9OhAn9{H3Gp?C`7ySvw^y6wTp60N^$5C=oJA~}jct{K^#q%%!#0hhViUNX(k% zas8WY%Qe`1AgJ{35xfMTT!T0+x1o=#E6@Ve?%Yb1yUf7G=i%3P zFyM~}5c3B2SFsQqTwfZh)L&xMPDG*29lohBQfu~jPPl!js!K6JIdLA`Xkn)r;nwhp zN_`(QPvZuJy8yd5qNc(Ys&65WnkSqD3#4@JCo||E^Spo^AnJQkQ?!ILei({7e|JM{ zqr+gKmJNyygs|{HT-H(_GxK@ihh#&cdZu5+VbwsWH zT_j4S?kCWJ4Y`Qg3L7OlLwMG09VX_%OfXom#ICqZ^?0A*N``(0fk;jktm}aF0`#Y9 z#GhD+XeD?$J~Eb&Xdy;sY{Y)F@87W!(PN%Z?VDks zK2WylvrhELh8I%Cusm1Qc;`uKU}PFZvsEdib5o*H-Wzgj+q+Kf6fB8ViUD~DjxpkFfoR1qg&DH z4cXr2u{f$Py7Z2hkg`($HPhdX^!EG{{cSWjm5DLWJCWQqGcS}ABYd0jIxvvl$z1N8 z8>gB9IP^R~e~;l`f;NY4-bIeaR?3T%OwNJ-AogR(_`CQ+7V+V2JAw`1mUke%vf+W4 zf*!t&U4!h-g^L1X#E$b*i3YogT)jOXpelNtUCy`UZb;?G)^A|U`4R*1gWCZcQ1p)Z zsd8>+IqDtkOU3Klw^<4>YF04UpT8?YOGpNawdOXH<9fBd+5G*FY+7a$GYrshggF0A-=TA7Siq^(e>+qRLzHE?;aM+=nF* z!Mu~o1wI*vT-(`H2_y3WH9N`*-1~XlZ{r!Q9ulbc;1A?CWS7`IAO{7h_ zfN=|{kY)rq3E?anjeV4vSZ#;d_gy^Qr+z2Nog^#VB)MP`oOCd^Y%v9!I?zU21SM{plL6-T z*h8u8VZ*M|*SBQrTgLS*?F!IgoJu==T*lES?;7TqC2XX;^{2i}6D`;tTW01Jm{P7+ zqhZ29kHxx^#!yL@?xd_urId#RXgxNbwH(am_TU;Xkh3W^h*RGcU#D(VE%w-cwsO8T z87-0d)Hpv@QVF)f9)$a-kLja=i5X%hgK5(VHa&^}^%F8Re`bWd_z-x}c|Y{Y$A~je zd|i+nPv(i}TYDoPlt^6sm%@xp{YgZ{vw;73`ZK+$7E3A&F5bp)N_`z{E`Xc6A{k&nxUTD1n#JpRHls@{xGpEYf8lW@P8yFybWSUua26?n!!5!09ci zB9-$Eq{HgEH&O_N$W&haB{V@j*jv8)0=vq_t4CyV8eR>aRqoIVc*xc~E%J4YOT$-t z39#tfnCR5~>VUVScdsO|JUO5eBW+ehD5=u6Po3?H`W z^+_uMtYPqa`j$&l`tGLhGy3kJ?}kgerSCoXSme(L9AfZE`u5W|WHo%d=o?Mn zbM!5u@5l6QrSA#)_R{wa`aY#^3w$hc{QUqnGWd4-O!^+6?~C;9q;D~OJ@nPkH*pPo zv*@d*uZ+Hj=qrYgMeZapS^!u^)I*nIbo0bC?V#X+5E#bowc||rrAII`d-MeS`ezKd z4*_~`Eqs52&mPX%9%>#gc4J={?;c*ksF{eOEO36hqf5Vh8-JPmGJB%vUoD3XyjQ^GQmCb3b3zEg3 z85i}tH~n|?B+x-Um(3{t%=~M=s6&XdK1HqRu+Liu=1<=L3Pt$k*J(bNpEN~1AD=77# zLgcdrk^`u}f~ZUN&{glTha8BjUv&WkU-Jt4JH4K9;YO5N$^L^o2Z`9mt+yxb`W?_a%(-LYzw|1buC zAPXeAW1a?xb6L+{v@=V z`n1;Yhn4yUpr#&!s;INm>$M#g0-}u{UW;+{AiR~j%@hwH1;qhhAE1GhuKqA%79pl1 z{2^Y#h-*5ZwWx>r3k5&U$TBAzTKNn>{bvlj6JhlQPQVKcn9cx?6YvTHiX~SemOhf} zRfdgVq8umS4F=>QK#!seoUlJJOmi~ocv{5`exJcz1o;ELPSTGU_LhX@q{6xxwi{uv z6YE+*D)=*OS0N(?<*KocLVEPnV)b>J21_reBCKJ)aRp zEDTF#hDz(MWavebyg<)&%8}&PF(Qr0?{*52!&+mzhKxm zAVGD_N%;Z-^cNY*GbVbWgP(+UGW5#`#YtbV(t+NT)yzN6$^QmJ-(t#I=0C=c3F&`j z=-(Jx?&R0`S}h_Z`NxbH!{j_Vqi3w+67_gQ4cm%xcS;EnJqw|V%wf+zmYSPzGyspI z;g#5MP5_VMb4l!RZOM3>9FZz&CBZy<&$ZhDO~1ophQgS)76*14yg!r{L<93 z%tQJ=%bbxY8yqryxR;Ojg4%m^fY|Zc8lF_+p$D!+VX|S%7l<7j=4k~I@Mc*qZe!2y zrr5<+=?+*{;; z>?6Tf4r&cQ1>+#?neuxs?X7i>@gQB_-1r}Ge918q0=XeTt{p~oLGE!PcSBo5J%f<{ zhkB)}zWWv4RNjHQg5tP(^i`C$H*!qy_1lrpfAgT^B4Ff%3wMR$@eYTBJv{qrZ;FL<~R_?Rq zcuAjnO4c@tzIdjU*hZ0Qd4FMhe}TWCgQwg{od0a+)MsIOfia%1ne3PdK9jt@9pm7w z)F+Yg{t7E?+(f^_>ddnuIEnQMHG>hULdt;$L!H|(gOJKR!2~$>sFf9uXY*GRuF8WWulbyKZ2w0OpwxBO2_#=We0vb9AFGiVT!nBLDex%uH|+ zMSHM$419P(7#u5hq=UezwVA(PTB$w+Dft#Q#VOvq79&ou=}DB8GEG(M38w!J(?`^F zX$2NtlF}HeYwIa`uSc-+iabvP>H!3%a^xW@q7OodLkDF^jd;)dD{>2^b{7!u8Y;C)E7imF5hhJI`>jwMrSx7m{t z)9}td25a*E5O8pxCpU8w)9_I1AOt4wpQ^4xMhY~pG=0|nwedoChX%g|$BWFW_<1J4 zS-4u*5!FD}Gp#nYi{r)CW5{7r`~XVw{#rTkUJ>;E=Hq;}SQ0NGl zFu+~>CYS_f+QWICpzp|0jru`^Qy4?-jfGZYH>BVd=v)4RsQd0Lg?kP}eTWLYX5Z$P zcO>t$Qy;(*rm4D1WrW2_Btx)iFp}w2?43y;Vndwk zJLo(tm)$fR6=Uq+%^!I52awDy{q5H&dL!!0Wh{<1gzG`Di`-&iVcy6hRTo?4zO^nW zvLQn2t|~B3D*3?Zr1^#k#`VPWWh{rRi2#wPBlNG#sd` z+zNF_*Zd&TrAiAnH36#6tkicBi*Glly7Xoz#hT0lT!LJanPpyshPeCf?MS|l$)A2r zsOdIuSBw&No{T^=+YN1j3XKs@(Rcx>(uu4(>D=&OpqGLDdT7FLi306c!6t=4tiR5h zs+IIe*B=mqHy*~b6#Y}iOqLjb*G|NwCLH0_0?0Ra-NYBWj)EH4p~#o6xvtYE9t3sz z?uJIn$dq7Np-%l3bBlg)BZ|*P@$vcSE16;z#K)$Nqz}Vy(%|?-)|UlcFw(H-qz!oY zlgiC=Ujj@112ZIL!BCdJjq0VH-eU7?<Y}fs43^u0U=)G`7Zbq49T|TqcR|m>kQgHNg;`0R~u5fj9F8hhg2Shyz*c;gCC zhrFne+Nll{k0&{UtzQ8H65I7f$pL0o2h62f`~t`l##R(};PAv`GQykS33P?717IJw z3Gb7$-!Wk^fJ)&GFFx>7pBd5bWv=O|jxsNau9LB}4r7VGdzx%5!!RDz%NuAn&Rh8+`ex?&3y38AU?PuC^7wl5_$u`_ z=J}432lafDd4ATLC%<1kcp;Ifp`OQ(D85Ya`X1A7>`h-N=>x<|u)|c=o9lbi|!0o-E#Hz<=D z$om4lJ(2M$r4VJtq-)GOt@$T5r?#*?8Ly7OIS*cX+NJ zW54fkI&c!%yG&&7Rum+62rk@Q>TOA%Twvm^gkw*@0YE$gwff`eq-^8woX`S0*iBvI zWFD9E@KMdF`w&incqK6pR75w|JTH0d%Kq{Y4b3dPpXyhE7hrk0L)_k0(rv-!(>e zJxrGQPdI-*J#T5BPt1ezyMU<#P4`e?Xv|47r$}VeH-NSEF4}Bd##d_4D76m^&Yo?@ z(+<1_Fd@xwUMPEab4Izqz$-ozbjP`c+hu14xgP4xRgOZS)BMJ5rgYEM`0FvVH{<67 zP#*IKaAzp6Ic-9DvbUAtt#LIyU^EboF77t-;sx@yTeX^o67V__2~gZ^ z3`m9_aetPP=ooFq@0vqWEq)9g4?^}Bavu)y*(0Ppw7Il>_rNJBOt?w3wnr?1DAA(R{B?hkPt zvr-lO1l$?!aiY;4O}`PjXk;nh>+mfe-O)_^@Hsj!)_xMA>;6k{Hx%O}L=z-*ZOj^F z@sH3p23}njFVrWZh-!5U3*ZERsklHdk+AXo!f;pyFL%q)W9U|?(pUR1Pn3Bu%nKl1 z@k&Ha8?VLrpu?NKisBRIKdBa&!Dp4f2eB?-fMWkp#_i7$Q!`XNtYUUs@6Y9PSr?|ES`mO$JbG` zpf83dee5>ryCt38@U!eaO~Bx;HufcxnVHeoyp-9|*E}r}inY&dd#LpImzZj-8Cqg{ z=l-wuzCJLj;_CY*Y;Y5U2^tkOv=;>dNkTwS5((yOLsIf(HeVH@gk-}eD^6+~NWZ66<7D{5;&EzxR~TH8{!mRg_ori(3Aim9dU`}>`_cXxx>kN5ra zZS=DD&YYP!bLPyMGiPSbd<(A~K}Q3#3F0VqEQhH$a-))tJ%To5Tl^^93ZT^mdJ}Vt z;V^b9LKUZIIBQ%;P6@&e36UGeX^BRPw~kT0h>8o(HBw_)g{P^!14~^*5T=dcMXII} zKD?7Pz`-C3hl9eyT4V|l+L+=snEzRJ{%Jo@REnQU7REa)lTo0)Sa>xm1ZWGT)(FN~QBm$l5pn4Vg;P0Of2mF88jjZ)xo zjcBI2Uql~GV)>NB!{zlbq|}-#_NGm)ycD?`@L zx*&!m@3ie2g3%3SdFA@`EE1mH#5eB&d~r;~weMzAqj^Ov4P|8)-0PWtB#70mlFY)_ z=-{X0Nrd50x&y1}H}0oe#?<4GJXkY~F(i+V_`&DVUFG)atCLo+}M?qe+L0~;) zF1+JQDY0+|J$0iHIlRQqaJLPOyNYyyha+$7Y8K^ z^WmR!W*B!Tk@E8rDA>$w(za)TNPz-U79Vs{WSq5!Uor(vlSp-c#tvCUE!ZxQJN^PX zjVAE}Aan_cP0vhbzR3j%wMQ>)JA283mqUUn4QjBH#oshhl=qV@iNPO*R$}L(|E<9L z=WI=S9J`IRI`5az$e=N5trC+muNkZ5+zSuWW6uvQROX@sLTC`S06}+2s#2t)6E&5` z74ntpy+`8a2pwleeCbxe`4W(-P}pN`{~1&~_@z{p@qUfGb{M>-stVL#)>YnA)E?EN znX!4cMMdKZBgLkmahYx4n*ohTncNN_&v=uYF&TFN?l6=I32jN6v zgVSH0m&CO$XezS^dmmsq{&3MNFbHe+`JvjGfX#!iC2uJq0ty0Qk^XuLV%}AWY6%iw zw~@F*A<;-A`k1WJMuP1d#bfqJ$ekG~#?`fRX!?b%$$wU40NK`=FM+Ujwy)aR{?OX3 zApJ|0IyqhZGC<{+X;-q@j@Cz2Pn6*BLYfLJG;5-Px*eEp=G%eEPCIa(IV&2NZU@dX z(^X*Ta@-YwIbEao7S`zfzDVTYq!cLJD6cD}(Yyd)_MmXM(R&+#eg>d;oH_3ua^i%x z)1MyL+6-%DU@Pwl_!5b@H3O^Ed0R8mc7*T=phWm`UOp4o0yNj-=(^KCY4~{@dV)0F zu%yWx0F0_&irEVmadRGuJ4Xqa7=$3$Fw@M(oN;U!0O>y+wkt9pSoFwFFuJ!GA7&Ejg9Hh$l>rvO>qiv|`DR%7 z0v#2;7ow!kH(!Yh#vKX@dWQLZ6|6pW^IQ0&PR##^_f0@dzJPUPLzdJv@Jy~<-K{D$ zD8xetl`XEAqDrMSh{y#+bz6g)QjSq*c8wj^uQaj%}h`s_h_Np5BW=}se zb$b1TSuHT|M}R3YJcg!v2O0VaJ0+T)n`kyMaIpflsc|W?vDj7BmHf(`HyI)SG+>-d z`(irGLUa_64FZQV0LPuSI7dJ^ce#nvI?`|Dg7Kf&lvC?!%D)({s85H(*x9rUKJ7Gy zMj*N`?$U8XhsHteWnnRj_GDRB0O-Y#uj-OKaUg1LRUlRhRlRlHLV;5t8x*9fpKg{} zc}Fm82!h*fC0A@ST=&By2u{*&iMu8Vx@i!!64&i{u=3DOwh=@Ox{fJ3+4q_#?lxxt zX^j7W2b+aq-V8e8Y!_;DTNT8gXcHo0*R) z?%t27*&tS)apWWwTc2EyNpM)_okRVprt4uKe-Lrlr7{GIa^B9J_AGg4d7{I@g7Pf>$u?BAdu! zzL;}>PH;M3MK!RO8`+nj4=s3ZIDdwJ@?$#cQ+!LJax5yr6#GQa{Jk4?RQL zs~V%OXZh82m9@AQS_k6EM`qksG#JJN#w$`=vvG@T5&CEXDS zbflXz5~?}^-#D-j98Az@ABeb)bgiPreVz>mN#*}#u;n;S>$Wd^nBreWQCNt9LX1ww z@fV4tqn^NWrp$q4SNIVQ9z(CdxOgGn;Imca!YkwmtN{KTNgK^nFek5r$vhVlfZie? zgy(OI$XNYxIXgPVdxT87=>wIWpYOt9+E*t;KKh~Zk) zk(nq2M<&7fQ(<@U)hFPprQy&@?pXS>q8t#=#-2g~`aqft$wDf84!+x@NJA&?ym9X^ z9c;`(c4o!%#0Q%~pC#3YabeTY4BQo^r|sB;Yy@#{Edg}_bdI$nn054DhSC$%GFY(X zXgC=-hN{fqCo_XB=4c5`7~0sC3U^!!=1ALd8B>b0kV34gM|0o8+~2_p7;qe$j9~h| z0f~X;vs}%9Uv1-zgGom@cVNT&r`nPpGX4lkAv`K{DIJi*W_LgH8<6~P5c4g~ILt+v zDWH4!Mc^p2juc=zS|m7zT8@ICsUv~5`VSN>|DtG|9z2095?j%bD)^m1!C~N_8L&y1 z7n2Kl&ir*5$;qs*n_NgkHwaa|5}a~;FWQPTym7n;m+|-)RKQ>&bb~#&mnD<3#|7TSg@!xRf4kI;p+Nn%6Zl7;X$Xi*}+XZ>Za{Kg)^`Z zYbII%<3hP}*t&lkcaveWWU}1q6^dSv?JpVrf4a7 z44*384MJf$_IrM-@)ZwB9^5Fl5P3Y73K*rkUNqrqX!DyWRUP0D*I=E^LiTFG1*4oX zt!qvU#Y~J`sDt!v`Un)-->>^)2rnbTtymeGh;Z5tXiE|L>l<4JMD1;54e8t71Y)?) z8+NYrGtZ@|>cAh8WJ@3JJT(!Abyxrm<0aT&-wZnHdYv(>Erym=Eb@=futc}Gr-xFi@2|?Mrc$y z{3{9wUe4uxe^RjJb@;AqI0CO{!ImS^8*nER#BdZ?~Ag}|`X>g)H?(JD3`N=E`BG{WKGjN12 z`2moj>pcwRt+X-1Royl0^OI?gaPp4AxohmqV3b}pqN)O;Iqp_@aa7IcYt3U%G9RYG z)Wo_BuvQW}#2$zxp@{K-T>N@1in=zmSd59NRAQ*Pd9)aej%rA=!L^x8()Hv+%Hl|% zZL6Dc*K(xJ48hnN91X^jL(F2=UUG9Y8VzNf-DKWzn42U_GBd)$m}?x>{O8Fy3k%)2 zcZ4l_23E&FA`XD}w{k*vB-rpevv@g8wuecg3xv=Z(oM3*H<<1vS+>9sifxJ2Sdyz-J`6R&=UgS+F>7aRdk z>hHrnpgqjR=!=@a6=#iph%&t|vEV<5C`yIz`OtLA$e5%YO`?orb?q`SPcp0V9cs|A zQCq+vr{OCj9f9aG^ytfm5=^FeUt|84+7-jbh7|8f2AzYTU7iG%;K5fYe9uDkx8gn3;^}Ll% z|3%Q{GxAnsV1z7$RY;41*98w+S!fp+kD zPz(L~y3Els(d5V^II{*>7QBwfwt{a!xjqv1ac{shi90ECg=rL*Ein5f_;Yx(qJNGQ zXFhzE)w7NBl?578Z|qCJIY*$6C8_XSqG?>xWOid=KlpT$nFTEX!>=2eXPCbQRM3?X z{I#&dIA-z)rXkz>)nukm6+>es@&KW1gB7WvlLY2++l*vO6+)3yb0TZ zTZV;OLwYDNuixpv%DaHUo(DwKF_cpy4m&gzRWlfukX;M*Rc%@-4Uidb2A?*Xk6Un; zN^-ZkkZ>51R4zyMA~iMznxD16B41b8oe3};TjVYQEt>Nm00fe9cQ@$HaqScJWKuL; zCYr;%7%gqpQE5A@BYkE<7~y0|-T~b6S(F)skK|v%w@mOyc}1B9?(D0}%q!0HkB5qJ z2vB0L%?v&pwNW;~7-661%ZfkG_wiHrR1I%V{9ubHOyja=LvC%W+ehj_1|;pf951!z z4R@o4Pa%Mg&?jsVkUd#&S~(PVpV~~w9o(npO2@TK7}suK-ya$eT^-us489ZmMf{3l z@L6o#e0_M?Z2#Qh&66Xu{TFitd;mQxH1ztx(q$2id!ic6bPOr%RMU_bBm~T#`G%zLo@q4sg6KvZ36({geEp>GEa&4dTYt$R0r%Sm^-< zINzRkAs~nL* zU^Ql=lHulxC(q3N8{p@ry!o~9^!`QY2A0tOt2 zf*fVy|BWaQOB>?pc`HoL){NE>ygVp*eQ4cd2-d0e_eN=E!!4}^Q4x4 zD%ZdRw1#;%k^y+vf>Kd8Pn&^TUFp1i5qUIhU!L*B~V5*JrF$lE*KNZU?pChx5~ z2YTHXk&pMw_-E{8gu)i|x5QZZeGHfJ0^xcr{F@BF$AWjp!XIJyEmn9s+>2THe;?st z|H!t#4I>VhDqF!nWH8RZVQCMYC>H)A!^q+|K_4whmr2hH+b#y$q)OZs6nnEk@UW$%rA97NK_=AkIGFXAs` zJj2xNcnTUYQ5!om8hAf6#kPmJfHNq zrX$T6(KO{u6Hh}#!{UH(MAf&3@swI0L8I>j61XR5W8aRZSsBISe(l|_`lmcT%sf9E zjc<#_pT2ILk|z?4T^~)ej%lQ=tUPJW8M`_f?`J$*p?nmc=SrSnhOslFX|_buSa~8w z8w=wfRri}2A5R-}DsAlfX#A~={|CIV2au0zg-F9G2J-AW!+QtPxXsa8*~@pv6OOKk0Ew ziQpkyNQ#VC{n+ZoUjRX(z4)xOn|ITrl0jn+rf?D#9v>?3cE{TctLHhY0E z!mldd-H1Wb!*=l4P8IOh#Db>mBkzpC)@bDuW_+CN*he}>_g%m7gLmx=!}&t%2)|?P z(7KQB^n-!IQ$B?_@-FpGd}r`G##f8?u^;n}x~|FIixB5Fzg8`>8e{2H$nc9L?6U~N zoc4@;Oi4c-r)jqZC%R_g{FiVS&iY+7+sK3}AG>c0{+@<6Px@fCp`7EL;@eSVKCiyX z@vl#N65f%NFCg==8Yy`VPIKfKt4i!!ae@ar0!wSPp{ek>kOQ9!*b$F_B5kwyT)2uS zU*-qjz_p^d`aMDJ(XmsUgSI+dn(5e{#q~>jQZprPQe*s<*hbIJ%V@JdZ#wr&(Iig; z4AyR-mnP$eKhYhPci_RV;Fv1(oNX(bX_k^nn3_S!UN7rj=m_Qy%7n7`7}Xn095|04 zo?9HSJUoLByy18?1$D%A67zZN$D`Nnon^F)EXBeUkDGO&aI?HJUg!A|OqR40(u)fe zCPyUK4Ez^0lnjKHr_U>Q2A|!PF}y2d1po7@C?{@)!cRJX-aC9?Jh3BK0%HTGY6Zb@ zj7>Nw+YwqZtpk_zjdWnMVMkv1v@OZOr$WU%miIQ;W^%9@iwB(8oJmWj+bL@@&}7%M zZaZdUD37>c(>@7%Wg^}~R<(_D4wgBz(0QTabR0JkX#d-%-qGU@O&21)W?W8NIQ6hp z^Ei|)rT(1{jj#|tAgG@JCZrM0dbdpRwy}n50foqeCAeFm zBspQ1I~C{F=`{hz0FOg>Y2hnzE(F&r(^!QzXgk&;f#=mA8?5Sm!zKo)fvk3M87|>)&_MBb^>)U^6{H^ULqZQ zO}`W7)1Lu74t8bX{t>J7bj%1Yz#hGlt}M5?lY!QHxdRs`EXTo{UyCYOpLX*kNIMK7 zlH^7BdaEF3YCD+ETcf9gvDcfJjWIR#;`ac3t6 z@3G&2x0#>A`xSxv({iiKv>lnqkGbt;xt6{O{pTKm8;!xSd#D_F5A@ih_#Ej<@;)GN zcgNsfh{Ama3^aC|z&X4R3ET!7&ccsgwtkNhd#n&(kWrJoj|f~%6fWKS7(&d;ZpBU~ z>YF2gd0b%T*)VB4npK(R9Z)F7a5bXTHOc#=z)iB@P$p}@GJP!b1&S_~`HaB5Ru-iR zmjnbB^eZRm9)Oa5iQZ=g_P=AW9DW4W+yYf%j2lvL?$!Iez};-askXhBdF{3GO7b2O zn6?;<*imLv`MnK5z%9x9bAh=!3WIy=x(x5@2xX(4v0mg^t+{XrJsH-JbUAO1bZQMVq4axsTTRdr&Wo#wQ3J2 zOcO->`mlF9l5l`{<`>KwQp~@=J`9t(huh$>Ojd~DZr>O%sP(>$f6Zs_$G%f(?|kI` z9Q;4N!fjsJ@&SA?j(BI>%&KF*^e#%evn5K#mv)RV3t;+BHUEsg??KmYEGLGlcHfc^ z+jWE*?HYQ4W1*BHyNz~YaxE0$!LW}tmU(BQfF|?DposSw@But%eEoJ-VOsdv5cWMb zjPDc&L*Chd!yKEVpm#3b%~yj2ORqJ5f|sBRhFY&6awiY_?haNRpNLAvuAzI`264EY zv{=%#G>vcHq}+tT79&37O7Y~yn8RP)PxbESH-P}fHD z$02<2TFq1HB{UQ2Hkmg7MOFt69b)vJCac7$*jZxC@lsvGS%`7~;&O0v35q}))napu zSt>-t2GVKa{Wkt?^QPNWt#g1qxGGlb=@NiiXW*sDJPZF4>B;!T?oNAWpyDCxu4ZoA z6_0Gkz+_mu!}cP#k{vdqro|W)%!E7YT*q@!du|dL2Ig#~P0_kx31Sf28`v#JO6kp_ zYk&lUYnKdGcDZ*MlGd7U6_ar65ht*fpI2;;o5zt3Aze7kH0~`VFI~ZU@`mNba%?Ot z0Mo)#xVD8mqLDx7gd8qVCt3)kI!+ZJW%Hb@`*0D5hYPV%jyr!<+clX}Z(-MY9{aX& z*IY`Ixvd0mXeW9=pDi7%#BCl0{o!e0Rw0W@=ShrfEih__zohC8>>IIWX0~)g_p&ez z3Z{CK`DsA21=?kMc-$SzTn7~&j2P~)KaN;nNzGg;FXI+_^|JLxyO592>uGlEagz2g zMZ`ykIKe7D*0)l4-blRx`$^Djn!*?2O_z*-KQltz#N{xS;eXbTZ*_L$q!&#E|?&d$Rh!Y@RlX(pP!m4jqSoQr3 zv`bulAMA_O7xI8oc~o5l7FYYxo1?Yo9y6)G1hM{jnNa^X?D_-SxcX!Lj#T*`L%9Kj zLq(D~1;G|s)*z$s#}rM@R=LO1q$IAKIGVgr5Ti*haN~x%MR%KzfcR2|abC!AH;y>r zI`E+5cC7sz4Q1SoO)wkk(o*ex{q3h{0X$ zc&8gmCG>c1?rvy)I5*d@d*5nggQ+FzWgOV6@R4 zgUF@^AiHpzIby1I@8S@5|ETLhiFZAuevSxC)g9Q_3gJ18NnPWKg7M(HZq4M8%5y#zWG& zNc%R@Mivv!ya}(hCiww{?$dOvf)&s~OXTCY1|~^-wd~aZSZkVBA#aD|?TC4?=m^ZJ z1b9O1Dn0nk0p`0}cDv30xsIa#C6pVP!oZLaI4H#K2nppog3=BlX_TNekcHX(3a1hE z8Cgs$B8!QDIUT3~T}=MUa5b3<`=x-he_ROhi|P@w(Ok0)4FHjr9)1)&0ZCy;Jcr4k z3^n1qFm5Pf>{u$?WzimYVkoL!i*p#D+M_4|#w3v3yc2-d>mCUe>VH>W1;cL$Hq*jY zxZ5_aeH=(-G2z?kp%;oEe16uAQW2xj4h;Iwb!@ zu3!}B~7SJj6urf2n1)hA^=1BiXpMu*saX1j7pY zH{{FraP9_QFfH!~+HP|RJ_66o;hNVT)NL0J3_OJPYclUb%-(7Dp@ETdX~h4K*)6ac z;>m6mfV-e>J>*TNY)O!))F(cUk8OWr&;ZtCuhRX=E7Yg&9bRuReARsTzMZ7ub~?h$ z$2P4gEFy4VX|QVFsOvk#+42GN9g-T;Ishi!kg<~dhL zYwyiKR$vA@_~c?0oX!%4_Gw1XuvKik0`X2I?mq(<*%xjaA3zZtIN?Ar;V@6V>7iyR933qE? zgXHvaj5t)y?LeFUod7hqvqM6 z4e+yravIIs(00K$P@B9B4*%N+m*WoK<*O4StvrFEV0g9QdmY-N(?ZxX{-bdJjW$CuZ^nBZ7=rBoV25 zh*7AP>jI;N(pGzjjf9NbA;d&Nj@uzbK|+q%AuL`(j@ltCIy9JSf3m<(zx@erk6dnk z8I$G^i5wWj&Y7u^{&KSv9V0Ypw6GkM)D(7DoTyDzXkl89SHY*@I9~;khGTpc4B*27 zuPiz^n7W5$2K!TYdDJ8YJf#MpP|GxIyKgdAfJxa0_Zv$wBh7%SgV786*v$wZ<4!x+ z&R~kNd=K#AFnF9;{K}WndiU-GCBt`6h&%UWp~3T#c$0(iQX_IoH~+d@aaF4M?FD!{ z82A9bw7JipKCt#M2V5g}=uZ4x?)?t4`W~`^U)NmZ1T4BD=DYVrA|g=3m2Qyg=t7=q zp(|!`*6DJ%5jk|FnctpI^>Qeem|>46&Ky8%k+WN|vHJRW-Ek-t^CRrINe(UMWD4?t zqrJHaIj~Yyxb-mFAi>1i4FlN*e~PWu ziOj}sQ_0-_u`WHbn3^ww zZTqKy(H`O!d>3erIyl>e3nvz8erpd=ddm-#Tqgx6Vob|4zky(tJt?{Q!VDZA8AU2w zeu`9(UtC2FAv{!ip;O!(MvM#TrrNj=9V6Ae9#)E21ts55=`<=JCkkROEArf&v{&5ZF8o z#~CgaDjg8^L$j$HGNuZYN++zQvX;IWi;KQ09Mcy zpP^k7oH1_uo#HxsfQws8CXZKTEU+2m64innx8r!EG7))2c|;uFd@@V*U`~CK%x{bk zVVq0xA#{?kF_;-_3}&7t%$x~kj%U8ji7+^x8C;b(4Npe+{E_%JES)-yUZhq{on~{h zHBaj&x-HQ0N6_k6d%ApFXa*VUgi}O0lZms2OVK0Dedv=x*B8KxbdPui5u?w_uX7dG zbw|X1r+FzMp5EoU7kUGIGX)Q(J$ewgOfI2dckNblpamhr(50n}T% zJ+>-W?G9DIX1^QTsDBw4+6@-xrX6)m*I{G;lUiWneS#u5?=q&tZDu26+%7D8nCHzS zDkw(@k+rwM{~{2`5Cpi&aZPG4RX*J2df2}ilmK*sMKH}5+-2dBwu49Ty@y#y1{(#| zP#!_rj5dVd78EOj7V1i?Yy;TM5GaSVnJ1a=Ufg*hlp%LOQ+!Q>4yjKWO zLUZGZ@+&Nd5#I!w(W5ju2iOy7p~-~mqg`%*oU-U(x4$l)n&5c>UTyqeuz2BBHdFQ- zRuFT@JI#lI8<4u#-u*N2ilV?4ObjL?hw!8k4tm>_IaKySJh2o4E>OUKBL?^OPl_B0 zJbf~76%43x{abWd)|c|b{iHHJxkyeSV+b+1ue6@btEM z^fqs6XRlB1=o`?D)`7JiL!Uj%H(ML<`1-ond-PUG(rIke*LVQq(fbGb+B}~2&fc{- z+ALqbu2(Rt0emA0dEVgf^cfzX-rC!)4|v)-`|e<=Lw7IH`Sqs}$i8;&bY8q;5 z>uM@%mTT(6Ra?OiZ8fT_cLLFV-RRTXTMds@Y_Y$yn|0N58fr_6>Rm;Zm8cae>hts( ztwtv(qzW&LtI(;4&hgESBS$>Oq+fk!k4N_ztv&sEUx(yIOlEbrrzo^~`wS%U_qJzA zCT*>~vkf$c-qYId(Pqvm%x_;aSF7k<-`d^TuDA7pkVa=;Z)-OI+6MY`&mgh&AxQGp zN;mel_H?%CRTA6l@fk$7+q2%&4OliUnuB%HN<9Wz1Yd2P18x59)&afUO55(~_w=@d zeKuaDul4kL20*ZO#W&K%%kYN+)-h)ddFAJCn$0zkIshIa&oksI#*Rqqf1+vqBXc(?s8XUrB+f?RaI17s%`Z6 zwB9~VPfnSaT{w%sT1i!PX;IyBx4cvrRk_d*7WiDeRu!#q0i$G1xEERWwyx>+uu$~2 z-nH_k_`Ppnqu`KbcRn;diJ<6GBGBzj7z0-{tZgdQN~Oy%3)Hf0o$l%BM?Ymx9`G3c zfnL31psz>Ial7hEE9$h8K0nAxB7GDR6AN9#EKgH%eO0N}G{F9cZjZ9SSO!Y&8)yY0 z9i82tEPaC)KT1-7^U$t}%tlEuvOv01HdSK{@w3HNk&u918x zlcZ)no}M+H0gF)#b{**{In@nlF=?Bn^R#)(&uXFu3Y6(f}2`ZGAoc-RJ`!(UDx}XnIdyduK-{5bE*!44rjCH)-we>jf1$ z*Y-kSwrlQ<5EX+KwK{us2v5klR>SZN^v0m-`__4SJ8wj3|3a1xy-3{C*(?3d=jm@n z4@6V=49a269SsnyAS+t+8~lCjqY6R??5Wa0tLX0btfknn%Ll3g6vJ_orh~>>X^-0& zDE0R*gxFpWwA=L!orbs14+0FV_4hzBQj&oWd-TDAjVTaLtSYj0kzpY6-2OGlLGNho z?DkP)`8Z@int+jfhE~fF#^=+!J9|JV$TdHRLh_;_%k%}ByC1^}h~BPW!g6Fl^7$~# zDDh<{6k*!lqE)woNl=I(;~d38Kd59#k3>%xXoZXeL*)+6%3V0vqA9sZhSecz*x6OfG>jXQ$Y>LN?Lce4S8p|xDAAJ(v**o1|L@;8(7D!Y=yTfU>I?Gn za()T@9d6U_GR-s~+!Vl|>N4Gco*1xcVdnFs!R@ zs71AVJD~KSgRl~mPa=&(5X!Ks`}EZuE0}aP+kr!W z6xAG8b*TuZoQg7ns`iT$witi=1`LQdZ2{v20gS*NNt8XSO{?kc-UuNIwD2YIvmrsc z`!;~v8f%N{%RxjDoO=Fs`ph{Jl<%9LKVP2@4X0hJs4gjW)dGxftcHw7H5j2;7J6HC zMWtlRQnmU%j(oi+5daeG%fV1Rs87@csDZTSXdAQvZ3AV!HsEP(SCX4K_u7NC)B<(W z=dd$Fe3z&`6U`kJ7Z{aG8Oe{3s7`}~K7Sj#dsOsy_sNiAl}>$ScI_oC_;*vs<`qLyXZhN&xoODmZ|DgK z6LGh4M$5{Tm$j^%*RnFdrKLd0AI5WRLN4n!wY7J2_81$6m`hP{Tf4`#*4w$RxBrF# zpWCSSHx4!<#_Gr_p^iTw!5{u*>ptk&J*2wgbjYeUjG66m!i>yMxelpJRc;-`3R6O^ zl7@VxtWjUBKHczgoKjq>N%V?;02$Yb1xlrWTBK$GM37q21}|jD#y-EkL3D@qKE1O; zpRIsq>l>i$>y-Myo+`7-q$w_w0nZxh&+Igi@1jQ=%rcq<*z7|Y#ORx?ulEeB>GN?c zMd~(`p-|d@5e;Rx_kj(eE@rRS3zq5G>#cU7F8HCpHiESKp%KJ1skYWOPz_U|KJ>rt zji*c29!+K`O{{BF?fQpFJEBRY#n>a}w}H9;Nr|1&WU)CK%NgiV66~We?TMxn#TIy4 zjrp%6Hkf#w$Ajt51Xa!ldP7XKLp+_1Ivbb_qXY(MQMWM)_ZpoT#WtvJiD_Pq3?7*0 z%)w~Np_HvCdJ7uWqi1(QO)V(EubvHI->cd#y9n)eX%QZFD8L^@9F>T4xcd#6uLGf;h-Rz03pk&meON*%IDZxLy{cAyVa z-3gWVN*@ z-R=zWbNn1#FYN<&um#&O!HfN2fHb^lYCzPTC7M=i2zHKf(E4aq?!!dXC=l3ACD5*WItA3fUA)fJUd$y4ZDFX^qO zKp%s4f`)>QF4hi8FhAu!+B9lIimRYsQY&ozm_o(O5f&=a1!-r}0I6p;3Vf_p?KV{d zqk-Xp2!VnSp5pR2wS8s>h@JXy=&)szDve(zQi73v#ta zi=P-$TM1nw1$F~ZN2|ZvfNC74M&@hDG-0J^wcVapv^13?VL_4f{Oa+{AMi+Ijxk94 z4XkTm(QY&bCNfqO8PDU(NrCn(vsc(5+)WkrCFMnR+A3|n1{K-us&&`b@vXRS1>bU9 z?vkQf*Y&k^P+6O`n4)bf-iRovsA+&IZW*_7Y>QWQO+|H?3t7bLeW=E0i{)1CJ5igo;7{lI<;se zGJO7is`gOR6_ubKO8u2US5n2AHMW!GU}UO+51kx)?$Wak=+{zXhn{WoBnIF?V}cgV z5m~8nt2rq>y=_JGnob6a0KHE7#DgCg1c#oVjUsj#dSS>SZo;`|)w zXhF3sGBSG|fM&hk(+-Z6@|NOHcSDnv*=kJ2h&iX*55BgnYH_v{iVADs!8DblP`hPj z#I$)zbpFuOIS9enyB5G4AL7R=)uFXAnnZPfFVrFkc~~D?W^0|jZQXuYMRPC{s%$8A zm|6%3>iRc-KnJF-tXsBLMUDH&p*J8ZItRA8RQk0V| zQi)UpDPT`%M;ru-bbHK#Dth}dT+2koz&s0PAgHH63K9WQVj_b|Z9j}~XNTto;9ust zM(gb8RqxgK@N{=}pi5U`mg(unh=W)34Jy?PhLsXVMw=93>p{6_2iTM}B$50o%9s&h z@gPugkQ^o7=)fSx2Fu2;b6Sf>m-0k|kQuK%TVyrcp*PazQBa`GC{Tz+^I~$_j=*d{ ze^r>ZnxLu?L!FtgtSDe0V0xJ#pCLCD~jui>QIzz=!uRyz#HSLti$BzYx&yp%9>(Ye`fhg zYQT5(5Zy(UZk>`vMo|J6=t!j{>zC+uHVB)Sf7y(yWmd12Drmj{-eSzI#xRObAFp4C zg-+H!D3A233s6K$)Cddy%+J1V#%8Swqj@Lny1JDWGy|yOP_v=1*#_HFCK{)jcCjLT zib;3YEDxyu(XoeRC}Tykf|cm?e3j5F*{3u zs@M&fGAWbZ^&+ryFv7+QkSfcv&09h0k3rg52VMw>yU)kQ!eDPIZeccSTmNF~5$78fcr$$y?qeEOg&jIZYy$_}w zpRo~rhv~8vCNRAEa%KS);1DG!sT&6)I)>f7vVdA+*3{K&u4bsYQmmDe zyjwM?s1g{fztL_?ZAtoF+;|%^i(7+_wSMOor5@Ju(<~527lz4!r;KPIu3C_YTD&18 zElam33`o+d&ziuMnp!B)pag1AhCFTFJ`H@~f#pt<1wO6U-`%bCc6MtT5 zZ$R@w6lp%M2LN36f|8>7{A(aP{k@$xXfTUM7sHjbQe}yGhSqG)shTqTTnaTED1uz( z#cRqbiu;DBO0Or+%br!JxmmpKf$gZ@1B|r|^E3lSb*^>h>-MU>y~>H2L5I@@=2`Jj za$rlqgn)}w5c_H^)LH_izAaOF96}JAkgK+)q+FY^v~{4(y9}ELpgeT@F^w$L>;?DB zu;k8Gwbn+k?t}#eYA|T}x%2(Lf%)BiZLQt&QPO--n&!)#+23#fibSz-30BJm@Qe5_o0a!!!c2>?BimqWim%& za5e%VCzFyAum%Lyq=kJ$2 zYIiNuB>X!GPl3I17{^EOT#Dyoc+SIf7M{s?{=PNI`3|1n;rSJwpW^v3o@elUAJ2F2 zd=1ZCcs`5gl&nAU^AL7++mW|o2h$*)>+vkYGXu{NE8fYCo^gNJM#Z}~wNrn~u|?Si z8`$M=-h}5fc<#aTFrKIIyo~2fJn!I1yw%}68_&gf7UC(!Q-@~_o&h{J;rR@nd+h8QM8~_fyrcxy_vO_MbM=KeSLQ6t!NIKmg#CvG|BrlN z^BDO&cR^0>f;hhWPnhce|Dnsj&l_3}46RtC!>=)*e!cdatf=&BIo?*ESIfa}M1ZPa z0~=FdRnJ)q9Z+7@_Cw3>^?eh4`_T?EH{u1sG;0^)q z!8k@`9RI$AC$4%L;hImwS9<|>1{2_q@pH~PJsfoymTCVDrzdD%w?FV}m-T-D>-PGA diff --git a/board/MAI/bios_emulator/scitech/bin-linux/glibc/k_cp b/board/MAI/bios_emulator/scitech/bin-linux/glibc/k_cp deleted file mode 100755 index d3729496cea1d2f1343461ba075008530d59f976..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 37612 zcmeHw3wTu3x%N&nfdLW{5ELugQNe=6+(;l0uz?URmCH!DwFSo^nPCPdnRI3kgjR6U zA(df_(o@^RIh7-bw)C{e(sLB!1sg6UXg!vywN$L4rFEx?$WabPjO2gcZ|^;`Cu0Bh zzdV2c=jqO~v%Yt&Z++`q-&*TiYwx{g?>npK&(6rmP|PD!$x?`-+imtzgnNT}N~z*d z1}Ni{Ym}=HDhks|qu{~W4w`2+P8-fFoacBVjpt>cc`}W%lcga|!TJ0b6@@4BEBSi* zDd1DD+Uz`EMuCqGQlwm_XM!!~R-A9z>^%1Z^Q2xZgQp#Z*qd#3o(^E1W?Esuzq&9` zcT>RM5NRq12MbE{G>8`6<}6$aN-swU{Hrof;$i%UgXIm!Nqu-w{^dBQ5#XR5%;N?S zBXQ>9oQiV{P99g`{G3pV@)?BJt#rX5FvF2*?tCy#PHKx?HA zw%2$APDw>8FsmFl8etj2fjBF0USq_~L^#x-Z!$tN$OCaDPPW~(X5=NpD=rbos4w6w z!dZ#aJjQ}3z&Y8B=od}|z7FTjIA`=rBP=xHaxRfJ!ic-t2<-@`Tlj{6{;YvNZ;2;~ zZt@o&X4^1>11H-Q624f@btl(!$}T%^;k#LwVtLptq9{BxY;zz-s1dB4NS!_?=G zpjROMy9mkOjq{kr-tPhXApbFh%>NnYy*!cM*8=ehO-d39Od6(;3>d9$e&^G-wZq#`R_+a z{@Dn7fK7XT5x5Qbc_aN+ge!oz8}e2G+acf7-vc}f>HlrW4*+ZEPh|!U10S*2>ucmk z{s#?t&A@Y^-&BOGUmRf@>T{Km{?EWokblgO_W!*&pfjdw^9V|K-5rz;D`nG%yePP3FG=cn8We$DiVIt*H+-xWcMCq`F)RrlfjK zMUzO?>Qq<_)i!Qa{J~l^pfra34XRfOt98MMs?>Yx>x1h(N`0iE-rcCI@u;4L^-3fh z@OT;(FJPD~%-!e-g@Pe+MErG1y*m&H)+(X;I)6wBdjg(X6`FYc4Sv<*RYD$j9TU9X zKqTx_>M6R`S0Ai{4vu2XB~C+ zHz;BMng(}3%0Nu0fy#x$weAM5;$^`sBcMP#cR=;mqiUY|ut!zAswWUo)LK-)t*RkK z(x6QP6|IX%-D@}0v4Xx}SZ#n3O4v}-TN?<5J&IfPH2GDk0b3~E4Ixw(IyS-ftOFt& zf-V-U`hyLM@WLi~vX@0Eu6c{lQmBP1686*~4;#s7yLvY&CtTjf2<#4}!?3gzEyk>E zK=Y}!h?fe~uVbvsbt%K?`kDQHu!JF;!U~2Zin5X+oc8SuM=DAkLkw~s zLoDn946%S}WO%Kjs0;_d*D=IG=?;dNq@oPr47V`E0&pwC!HRM>LoC*|Gn}F*_c4T1 z*})Kt!TTB76lE7fSo$G`Saj}XI89N0%y5XJ>|=<<+M^8f;CmUuc|FY#3&VDXScDv5 zh{eV+hFDlV&(NVL#~IF4l$RM|A$x-1jf(ObLrfB<7-FGxnjt0yjp2CAqYSZFJMvERk5%`|M$*uWSS)^^F~c|77eNI~tUaWap_q9Ah2COzS)@cnmSSTxYxBam28w z(z#FY1Y!sAF2O~_1-4{jkuEdcEOdzbBUdTXAwJzD+SLb zUO`+Wcs}v%#16quVpga#U+@y*Mq)+q3gRZ>vlkIDb|rC?_>|z=iMJ9T7hFfYow!}F zk9Y_1KEVOvUBtTtHxln9-Y!@r-bWl2+(g_)+$i`C;&$TO1xJaG5jzEMAwEuADR?XK z3F0EbcN3o?b_m{1tP$r6zK{4Uu_AZ}aS!p?k6HiwiQ$b*aT{@?;9lZ(;@bstg!_&WI|Xy3`;HS= z0;ApJD1PU*_?xlQJwN=)7Q$j3+02IWm1hsf&qL0$hg;Xv z@3e6p2i`p2^HfnX{O+T^J~REwK=kPxfyY?WIj92%>jzC7A4kN=>mV%6Eu(Uv}S5_2y%a(@6T=u8(PS2DMm@H*^iB&fFH z_AZAMHW#s?`p={e=bYMp5bPpKtLOArZgatsu%FKX^JupqX|1B2Lx8yE?s1qTVb;W| zoY*FNR$j|QWa|stT3gPttd`Rs_Vqy?Xjro^Y;WCp7CCFQhxC~E&QoBB?|hB_-zaYH zeS$vny+=OyRs2Ns4*SKG>J{;hPevC;u1*|aPHR%4g)v8G*)J*`EoWh;e5e9FKsog^ zr}p1ia>QFS@IjqePoKK(e9Jj7WU4iZ7AoP?p2NJ=dY~Kh^47~D*Jy%WiFMt*!1?37*u&JQKYR^e7CcW=CJ(_ zvxXn_MRI*n#!W`GpaZmBJACaxA6J0#Py3=6V-$=L$*<9#@9FE)GYmk6j%-S2N9f2t zVoS=lg84Aa68yus_wKRN;0t=AKhO8Za|Z(~t67_=l_5EP zNEmEnsP6Ud835vF=6@cYnSuU2>SsBC9D?H@`~4sNECAU1gk3;1Hvtsw$W{=rY>bpl z-}^N3URZL^*3-0oPD}fy%Oxe_C{pgRq^!;G@y;wP--D_V^}o(wI%@k&;n7*R&(rGZ`3hW} z%rWSPd(OgWW*^&4fVn2K?>OcTUk;S*E8{he_SAnkZ7|H&kxdL$ zOkHBrB_dMj+m8DC?#92qG7UUh2QEhTFj0&Wp?5Cw-S>}3`S2Xv^GGs5t9X85By%OI zb4XH3qB=jGF9qvm*f{4B{@@qAS z^;IHrZKe@312u~s8Piv`g|Rjx_UkaZUc!-_SWo6=)N}_F?8v4RI`58bDb!NuZf6aR zmJg$~uG&|l%|%gK4OnZm-58sRRX=|AFl-m=p0<3Mp>kf!7tm*XqV=qll8>Npv5%VT z8_y1N6N=^ll-d-h7+b)Y$YpHo&AfQ-^U$p$`#6n(L#k<1r<;9f(~)Ob^WGe{y{jsrLH!b+t$B0Jsvsw-*$~Tx*if)0&fXh89WEcFhkO?V@KHqJ24; zG(cMjTDQN9cF)u1+}+%LH>$S0rlX|^cBc_KTJA8Y*!0(E7`VVn>NZqnW}DFvk!;P4 zHfmiJeZqlUGDpAvqr^zIcKkakM8qEE|IZ%$Q+A?-RNjwl-)@y+oH98|XQ^~*FTO`t z*z#iD1MPYHkH?RzSlZymMHr=W2CYtmj7cbDg~N9X}uIajT!db8xJuTrKTn z--`9rsW*0(f!a=a(Xs3uA9Ri}p|&Jk(&jZT|^^Y)7ZvG&ukp1FB>8SeGxm@zc50y0I&^nP zhsfz#*M=J{Smxv3cEdi|Suo9$nfP}!oBtJ&yEjK2sN;;i4s~EOmr0q6eX~;oXclB{ z%eEnYt5npeZ`TcmKJ>>(G&=ZxT>~tN@2!<}jOjPqaLY&PKX>EDW*psdSE2UaSqxD$ z!w~iISdUE|<~z}WmS2fjxYO^Tv-r-=%T%*fYng5! zl>QPbrt7@O7#+S0RK_siuamkJC#u^MOOM14#$RfFQ^8P;{a$JQkkek|@|Kg4;bS>^ zV{a+(gM)sR*Rl=WQ4|r?WKj0dE8m5=wu&{H2Elt6k97{_+EKpS8T(D$%7sWY+S4cI zRiKemn`@hWg(<1CQ=TORdeU(Vm6y_@TJC2rLpX z;_p6A7lI2EUls~jti5g8BJb|~NXdJg7f@3{Va)Tw>JX|3$(&yAhUC67-c{6^g_KEm zJxDAJKFc6O8^s_~8z$+jtM&>CFjV`6l;tqc0ZE{YwHa#%`0l1LsIM`ZUjq@;CNYwA zhVoMmWgcFlXl*K>93+#u(((BJW7$Intd5h9>K!=%u_$d|0nsc zd+Wix{m;gpb!cc?T+{rc6ZAKk6v~;ZtZPco8;{uFgt$X zjG3#e)pJf3appMY8a}bfUVQS2myt#M^VSpb=gvI&YbnoGQ5E~>ip|}{Cp)TpS;^K7 zql}uzA${wK#M0g~+GdbX9+V6Nw66lpMy?T?UnxHM%nQu3=qAW~@640G6qbw`NVQYu zGqi8(qDgwHZedBaZSH>Zd10PY5$l+?Tsw`9q3yvxa}jFlpF{nzR;%vK+dsEr>#-*f zA=?=d+=fdgCH|iG-F+Enu%h1PoE&}5k+=WVCs>eF@+mG|krZn$k5``)EpQ2+x4%5z z0~7RBpM#>d&2P6U$RK^e`>vR2-!LRULkk&ZIvo4`om)?^wLXZS7txTKx4$$iewN0k z2|EpAJV7H!nKz+K`m;-yYv25K@yVajVI5gFxl&AG-AzK`$=S zbff=9WKVNyf55oV8u72yqnYb==_a^;(E8135bX5bj#;QiJKSyf%T2ky(;O=^|0F{Q z6VFs(c+kRdjttl849m1OkuM#Q*T|+XH$#-S%ASbi)M$&)cDQDyyk**Ak(UoAnd=jI zzv`3%TVuLfZsD4cEOoFi`&pFwBXAkL9%c3Aa)3v!*iC=Y(!P19Q}-FT-}GJ=FIg@6 z;C_@@b#FZKo;SYgY-{ydr*FiP}9M-!7(olWC;PwB6@mMyPNZnj1Ze zSAo1uvWL;xoD2>5DL>hV*#~#E2O|YG7Q?0z-$G*RHx*nkPR9)gWrHn#w##MS6S&g6 zCy);TDN5J%6TjyrgpjD&sdv;6xW0Q-FkTDlWuDDlX-^BMVSULsS9nbMK>jl~!l2F!rhK4gm>wBfdF&mGUR z59nS_=3jkMdxAI3k_I>lnZ+lYv8KyV)G>)N+Cs`UB_4#pswwa1ZTTrUr~ESVcIz}z zBzmvhacd1{R7j>xb6ayBqlV|3B|$Au+$Hun)cls1FfR6clXS*&dYs(E8+1G_jLWo5 z;@WJjRT%qsRJWG4h`4X+;>r@=OcQtSr;8KD8m$20%!xf&|A;;B@sT4?$;8#8@jw1X z-s4zsii5&Czm+lD4V>G>$oRI5zX z`asmWTGU$A8$Xez*%;jDM!6rq4`nJqXGR8o{5~}+`1pNjHBR&sp25BE*LRIFab^S< z8V+QAdfyKm^z_<3zo{3_#Zd8LTuR41IBL}DIV&?{(srAYN?tvR_If?<@$+f6J8IhQ zGqFBfB>UrFZ`X~nzD%g<1^L;J8+yAW#nv0_8peddz20EgK+&(af%baAwAcAT@5iN- z|Czm}iz*jIm2`V0wMp6wN~G)s0DD2DbbAH++Y1Wn_G%D&MS7dx*6nqE&4CDay?}3%~W%E9gC$%XC8bT=nt`C?#u$s`jE3eGF|7qZf}M*?BeHf zJ@X}^mw?ERCGGh`87l6>b?ql!o7wdUbZUs)ASs#1pP?yb@QXw?o$g=yfJCe4B_ec+OOHP1=t5cO#!S~<<$bs77r0-VoAKMYG_PFLr;Q(3^XV6PzFJOoOW+A>d?Ap=rQiE+z>k-) z9A9%P_IHSl9l_Nj?{xdNrxK0`JIAT-fmG}x5=;N)dn6URLxkW)D#wcNKq}!*VW-FO zJ)es8ORR&jCsVOCrV#dD-=9(mQ<0GOcsBdD)AwO2{yGsem)rxNOI9;S7lRD*CBx;Z zr2l$d1kvd^ePdGbzt!WN5?_*vKZtnThlHpVl2n;W`o5lJrNl2x#ovSYzOq?}_N`3C zHtB+l<_RJ}dn{Ec_+B_?*1EMcv-l)dp6suA`)w1QzOSW(OcWtGxU9+B{FWgqN>OVe zDs3%R!{^W1Z*WD(dkrsQfcV(D+CQDfg5$7$e+Bm*douG{evHI}U3OgEf`|-}e$}}b z^mcC|m(@s&q=93HF2;p0%nFsg@tjQXuvPwNJgnNE<;i>8wv!iy-aQmY1fc9;zUHyi zqVM7deVvnGTC4^0wpwy}RvT z^6p`GLpu&ea4BYwA`(<$<3mtVx~moY%`s?obylXzABZq_7T zHEK6&60aJuTV}2*+iq4Rp5@)m%6Q{d4s*)mwIl7e3aiHal-<7j`%l^}%P^bGFq_>l zTaID2eBEp?W4hfE3)q~kX{O_?WW90!pP23>W+~lt19Z#Hw&|9eZPzU~J4d(N?0nsF zvqucwXI{SEdvcI;)cC#+5 zS3JYJTWS+Wy>?4&;;7edsZAX9(*2y#wh1(C@_DO_4O~WzNR5rJ;WoklsaC+Ht?uw} z+4gCkMEAPh1e!!|oY~37nVoE$*+%31-*-C?;D(pp5?O}VF~&}nF?Onqu>)@;UZ-k= zS6adwhw=4hKn;v$Kn;v$Kn*O-aLcIl@zvbT8zSQ2b9^yOdA=6Tdxw6D5!JC=o|w1p zR4}Y-w3|<0SBu2dXeFSrw85Q;#lCMNLycC19A@eWq%QM4B=MsVkBNS{_5dQmpUBJ@ z(E9K>bUV2~p`SGGE135RmZ$oJ7ZY>8KG7k|z3fGNSVHg2@r&jbXK9^OvS%W}ob|FR z0Y0rG{NHce!?;zS*o4_szaC4!3G$8K{Y7<*U(LDaZ?%SR;!$}2mVu*H{r}rxgBj(L{ca%o9q#|=Q#E=W*9G)3f6HxCji*4;`(!@NNsQ$7nU)tf+1pV4 zzOM1xF??|69@W6jD{ctkRC>dk1u^WWwNI* z@g|mzSgd{XCHf9Njq8gHEN<`o2XuqxO*#1KrlMX?4j;+o+UA$_4A?p*F{0Ze-Q4}NNAS{@z44`|TdPkvTdPkyxlyVePlSF7uNjvNamj#Pk7ilJSr%Lp z3e$#*=$z%+KY=i=@Q#_!5Cj`z^Dm)Ie`SWI-+~!&Qx*s8+}zEF{f1xNPnY_}ub^p5 zFBX^DcJYZe?HF#EI+tm`7Uk^Aw7b#kV7Fzh2XIrTZ@Kogom&uw8}eFkM?;Anpj<^=lK2jZ#mls2Q)W42`VJw}GVK8JFVj9Jh2ZIdwkjpQM%$GV z{&O@S>`39;AbhQDnRXtxdzWe5Xkt8u?if%P@~`ihZS#b}c=qv%#M&S*Cnb>jE=Y+C znIa<<6!!xWw^J8~j4w&DofWOoE>C5vNM_@frXf!4%Sh9k?_qAuOx@$+%(5V-UyL7@>lppM4liYv;%;+(%X#&t^nG3Pru;T^Sq-fBA1LOi zZKBeZBljl|Qw&Yan*wZKv~{$puON~!ckZ_Q=!L23Rd){A@}hcG^g^L}dDk`33oF&U zt}BfDAQ<+A1-isGC+u&h@Ifrdc2rqeiE0d9=G1y%4nC$osb0SAGKhdu1!O3wtZ`~5 zk$4pMg5c`#fK~6G99jA>E|sRzQY=;Eqq zg`#G~Ua*^)@}1ga$xPd7`np!?`nUAuwUi^%95aW_%rU~L#q=Dvpd4wKanL=lWss#r zb!6uS6iq4bA&k9{(fKEY;EP-nJwPLh8u@E86Jks!8VdV@Avb=u_2F)$r^Z2Z_X?w3 zH{mg5e&Vw=YvF2N`lXmY{#k5C-V6R3&3#JJ7>D0`0d`1jdKnD} zwWFKblsjzEMYfFd)lXEaq%srLFURNDJLbTx;}!^8eOc=q*k>b3I(ipxS}Ls%-*2j> zU&}RjH|n|-pYLdSh}FW;(Xz{+@R+f+h1$hiw&TB3J0M!y6FUiOw1!upX?1?AeMr28 zlASeL*MCCaRotY5-P4k3ZIt-kdk(g}m0+QFLM_lj0&CBe62x zvI7{pa{GW~H~G9Nt<*NJ^@q%a$G@WdwwzI0pNoEYV`OgZ0IRT4{X$|V1+bO#w)`u3 zMW=1H0kg}GtD_UGEROe|wv8Sde`5IT%Cm7e3r;QM3nt!Di}37nEH$5l81p+PdW&Vw}s+lJcBBAsn4-=hnv* z2t@be%vO^)AXz(X%hxJ=Qn>CT3K~(9*va_j!<;*7v;$~JxU^;Qojr)f{KrB+itl70 zsVajb_Tj}yj$W9zqtaHOr2iTqddHB9g^^+LH&T^8I%~*9lu+?JyNaGOp3kbhs8)4d z1;^aNBAwc7{O7)H%q)2=SJSFerM@EV6tf;>mh+KcCSzZPiip!O#weKDkPBOMG)S`8 zlb&~zy{k;-mzvfMnDp;rt)1FSxY%NW?dm8lvT_z{V-ce_&?w#C^i9^>EFQb`ZP?b; z&S!=CCKy?t@$#Z?qP7sa)M$J0-?Gmwir-ntuQ#$qqRc~BfU(8?1)Rn_xdJ829X~h& z{CXry8~&Uqm8fnze>g+6jk&WcGbf6r%eH4xH_tB4DtbTh^`R1M(#B(Qi}b#BxhHCr zW7mENL0DKMqvdxBmu8bqDf#^Y&!5j<+ZZXVSMhV`LddPv$+6+V$`bs{ zTWZ#@#u03A=s((ajIC2{nKkE@nF|)pss>eKP|$$o-^dEw=-_Xl9d1W$upt}_cpR%e z-eAb%h=lzR>HeS?xhL z^EiSV8ayFK&?}%e5(;@5)MS&QJL326Y2C44urAeTbyI9IWT(Je0@k|>hN%wx;{S81 z-dSXDnEhq2a@AMnUiFnPCbJ5$5CZ~3pn;vp&+dgW(CG8mh9RfXy&C<@$UkAQyP?hz zX^=Q5igy~+p$B`Qpl*vf_znN;MGKdVH!!+!^%8byGs2lzrHcxsfX2oH+s}-2P^CA%O{N+ z@9?@YDC-8}1qf;+)Zm!zC~6wpG+6Ptn{>LUJV3ZQ9oDA9x^x)!r{%3nhpQXYQvGQV z7Bo^zS!_5hF`SlImxkb$EE&CNXiXaOcmwWKj8v~SJXO^AibEM&RMO;7R>2^q5AwkC z;O!9$JoQr@V{fd}&p@40v%%e%9 zE%0{>{M`co-&=rJ7Js%9+}db4O#c2M-=}A?y@21vzmD?^&WkvQ;{8U~;4Hv-GtPxL zZ^PMub2H9+aQ+L@sP5w1F3vk|yb0N;#a5muFjPo9x|AO-o zoX_BV0q5&D&)~d>b12@QbPdh|oHyfKi1Rj_4LCRBya(sM;Cuw?CO>G{2}1RdLKv+mSk3`2aJOa4}v!B@VG&bt5B3* zSa`;xW0`V-7W!VH$0$5L%?|%N@jr!p>Nax}#*ab&2EVy9ZF|CoL=2dy!aHo~I*gQf zhs56`^tD1)3w@o?UlICxp+iEC6*?jG4MIOCbg|G+3XN?_I9?KZqR?GJmkOPYA1X!_ zybuY;H9}7kx?JdTp>Gu$FL%PRPG}e$$2~$%7yA1`;{{hZo)P*BLcbz(rO;=Do+0!= zIH9OAQ)pasfUXj{Tq48T290{SnB=kc<>vu-}OX!fq+u?YlN<`@Eh5owG(}li6 z=r0R>r_dXOjtc!;HeU#7`Vb`Fei~39a)#Vxdo4=*uBDs3QRpV2Kg|!AV|f_*S6uk@Wy}LYkHTz{KCT~?czw+Nr_f_W{vUHym_y% zHXJEb*3{OP;66ruBQN9&6uggdsyeP{Lh<l4~cP6r7~WfRN5shc+0V#P&-0Lp z&eUznc%`7A(BDuSh}3y_U#<40@W%Sp!9cjc_h*OT>WClj?DkJApQOLIyHLLmhg|&x zq8|hhE2XFb7GaIi%k_HPxC`fDnHFur8^eXQbsnz~UGERq7Fy$yw*uh_pv3Az(FS+^ zd~VfH%Cn|6439CTxM0$xWG(UPP)JQLOI~#9(c^TwFc}p<)z(j4GOk#hOSrVW&QpuV z47eJD?Bt9`XSxyQEE%siHQs$13F8K6*cJ9P8VqQ0Hu_3sO(+;?#0^w4ep0FQjt14m z8@w*v{AS{mNqQ#z-f!*3e#z+lOy{d>FQwFk;z`o=Rx0GUq*ldKL@lQGSFEH&G+U`O z2E%?8xAj~ciKb>HWujVxXAK^_^iL}nwN}z8^G&q1t~&o3zZz!uhm9td6iq0vxKw;O z;!&QfHtcE)d1^g)vSa3%I0VZuC<0n&x3Tq#2O7;?TT%+Tp;_zl#zCag-Q$vwjm3?R;C#dkmNoEr2 zhdA^fw>fK7lvOYaPUuF4a5hb0Lrk4pbx%bXL!-e=E?2F(vC-pNEh6A^*afGIXDT~| znXCo_!3~~}Fu}W!sd)T^WaFmTB8_;fu)#LLXx<9GU01II{U-E*^I-tjBI*^31HrJY z^E8GFBMts0j?wiP=Xjfcp=%DGG~oWcKC(WIZ8iEvA?w1S9`=9D;EKHe_LMN$5!?K7j(}jFB;;z$6EkhI&CNser z4dWqt5~Cry+~lS~VA3LyV@-gGm>^mrzIc+EL-)PqW` zU?k&2#;>u&v!;+E@qWD4*^pDhdLmx5#tW^D_D1`$o@Ryy^r3ahEUc%Q67+hL@p?6- zgn%`kl?1<3p)sXWiQc%_f9j9TkGB58~gYo)z- z`Lro%qEYLK^Z?~9*LtoGSf#YlUtGaX!--^4DSQoH>TPYJiF$QK%i6RAsW06Zvhc0k z$x`(Si~ivas{=`kPSh(b33$_WZ7RW1V{aWEsD;-V<4Et(()viiE3}PxqsFDEU>H-9 z7ZV?cwA8K?wN3f9iKrf{T+Rv>7nSH$T<6(ns#~h}XMNB#*19ZBSE|=tMhEJF7kMW$ z={;JiqNk)o@Ex(sCe~xdZKO|$%xV3sHU>%#(_mSMbRy*KEB~S zOh+wVyHSrQ6gO-D(;Fj?$=2Vw3wyZMhpR6iI-O9iMmKgvaH1=xmkyU2u_1pD?|I+I z30C^HEPq`_SuU?Ttg;6(-(<;$;lcO8M`Ze+Xe_G`hlP_c>T=9=bW#x33$?tggB0-> zlZ|O~vObNb^O>`Yt8EE zYMCiw5ZxXa(wv!@%irMhz#@{_u!_FcV>UddH{y&19&@aTxI=aHSQu8E8O_BVGC;R= z;tV(>b<-G&08!9PM#jmUzhw!4g@UmLFa%gdCue`tG?>K=KQ@_DKLw$GW3XfSzy-oO zk!`vymRjrD;Kr&^*12pAqwW<+Yg44v;xhR`F6X*%Dg0ifzTUK`tYTAHll}tS`k+9+ zH&v~V-~$6@GZu4LP$&jLxCBz`@uvTcgY?Msa~=Y zI{P|*gDJ#py81L*u<^u+r>T}!XK_wYkNu3=QFn{ne)SGE)Ea&rS#&RrVQoqeZAf`> zq#MnIOFVR8v{Pt9nsPF~up)@3JHSJGqw0Dml?3@X1J{Jog673YGEe^|HhOC+>n9k@ z>k(nGR5ZC}g*J_0*}q|EV|3C~OH*mqJccdwFO6VAvVK%_Knvu!AhjlKZ&4pa4!Oaz(B$&&!Qe%P2*=-IMP}VG| z$xTm5<1Q>GM6EG{jaPp9t~CyB)c z#RVmf5WY3y4tvJ`J+tKo!QZ&S@K{3*-h?eGE+{HS__q|N6yVl{>Rydd4e22!Or1hc z_k$veQ3>z|>$#0guY%qXf5HE&z{B>+#3|q3Lx|hn$wO|a1MvQKL6&k?>0Q^`X=HihX=FpiKFi++K0f28JUm{Kkn%R;WSs`! zk%{Wl9AH+r+tOy6SVd(^^b2cP{@_@1)xanD6Q_YC1 z2eerg@=%XwjgWkNYiK+8UZ#)SpUK(>p1b9OpWgK;d}SF>9gk!O<}WFAk1R9n+KHn@LH`7F6V$s0_2@ zE1vqEARXfYE)I?#9pj-aF+Wp+L*Dg=kmEteY!w{nrwp>>3vsYV66+m<{a8;Q!9e<} zjzQ`B^+sVq$StNC2DWg*WR2F)LwViFsfA!Hq z=Ds6-N5Cq9>DO5#nEd;UeM;oN3F-WL3)%QZv0{X#Ju)zZarc9K_QgoQ1)-Tg6Zzf1 zrhPNeaoK%)4EapwP62-2g_g*`_cXU6RKBH`$MpLE9TxlmaJNMt`YW@&GSFU^s?T<# z{aGLSBNJ2puYhevdon-Ed(_}(I?GGxpRe#oY39CV*1sz)eb^=KPd^Vf9J%tnN}cA| z)!V1Ys2|g<0?hQY-%jP{cNK}*6RF=|Huy=K{l^H{KEr|Afw?J;_$pw29fBj3nBTMH z8;niNy<@Lg@MK`V-``BH0_JNlP0a6AY8JcepSH4zXpz4Fuxd5 z3Cw+W>~H+OBwy%n@}C3di_aM_o!^(_+tbbT47kLH@cR~e3hF-uxD9xzfj?kMdBsl)s7?FHVgjo%(plZ^8Azd}*q#U%s*t zc;8)$V>yk7vH1E!xKJ^@^Lz-FIi;8VaSerB`( zlY!3ytL=DKC))x17l7OL=zBef0}sQLbPV&sI`CtwiE=&g3E&FQ*WoM$)_`eWrq2d` z{-14j_6z1;1pL|qy8j{e0ylmi<45>&mG!{K9<BzL z-wAB}Uh*Trgl5F-f4R~J%-8dqco-Dh z_XF$$H}X4x+tI!?1}+8uG33+U)PFAUeMlc;;1$4gQQlOe{ni2VYcRTeye0wo81kF_ z^Df{O;Qy}VM_&LgI%KmiFzoR|U?0+F80k*{A4mIr#YlgF*dqTmU|#Qm9pfce`8{wG z@;?X6`kw;I3y^v?~3Jnp0AClyS4{S^37WBp2ha{!p%{JYKIKLk7< zxmrf&LD#hVU>mURk8_nQC^`=E zO#d?i*!sQealirCYmy<4_f77GKSMW?_FW7-7x~TaiF<&#e&i=_*#0W;3Z!obKlM)l zTfe{kJ>a^ZqJJCw4>7-`KRphdgZh~M>=5ucv`>jq{x5;|{=3c2dnzpNx4;3Uk2BKW z25v(6#{?_N2f)!s@h&5Sf8Y@GC(QR>H~23D-U@zwJmb~tz}EgZ0oc6W8iqSUGl6%2 z|2gDm{T2h?cUm8R?61p#_adF`$#ft2ciZemM)_X{J^}xB0BO{p`<~mtZ+?G$C-5=g z*^& zHUije-y&cQ{2LAa8NfZjW`A)4kFm6u8~8r-4^v(U*!n&8W?N??`h@sGcJ=Fg?& z_Bh^Hpnn~nYIy1t{0`l+U4Z^56jpPE+#6inp`&mo2;OqAth#2#%!t<&z<1b9 z8k-FiFEkHS^W*kac(l}jFTr#FE3=>&+?n?`;Hj(XTFqy3N*x|Qso1zCfbTtUdFzyF zd=-A#%xVZv3Jzg+L<)pGYm{K14zDiIH6o3z-(iWw^M!hUP^aaG&Pr`Tae0xl&V!&> zS--}O9g+d}MuktMUF%hsyO!G)u@BsXoiFl?7oVhehtxCG*~@0XQKJSYGZBVMkVa_%6`HI0{*Oi7M_Qo+3?6jolVFtgv}_P zdN$`9szSD1;WV#z2<5 z_JKk{ROx-ChMOX4urGnp`1SpgpcC(~@ZjML%Z3fDe1<+V-3{wz%p~9&2@D3sHS0?Y zXDpakWiZYDM3S47PnT^A8ZU*G5V=Hz)e-wNbK-kgZ>i;hSQ>5-bR;igMzJ; z7zb2$oyQg8jHHJG<-D#?My@5#BXXRmSLmrR* z5(KePaOS*4HO@sfONfkK+`mznWxjuP$PKfB3ucx!QoI$`eg+Z z`}_>-r8N4z_`Lc^LqA(VX?T*Q4XXnf0JHqzMtUTe-kl~9PP0C^KCM@=NjPF*Htf{+ z^Su}Q+u>ELDk28Pw#GmnTik36il>*TsYPVNa(^96Zm>9g8^eBde^!oh(&3XM*3|^3 znN}7XM!YgY+QpjP8}@kC^;ZKUbGAPe)`w>QK}KoV?Xx{^)XfKcTy~5uUl93~T~vSOY_0T8xP6oaJ0F z58X(`WC}eZvL7uqjP+VqEn48jk6_3EwPg6Eh5=$Q7O~q|OpNN!bk0&(r&?q3#boGm z;UTn9vwF9`fvo6DsX@Qyby~I3PMv?EnWh@oz!pv zW_ZyE&$=-j`Bi+@!(wOB z{6#Zo%y%uCJsYp&aV?oKbAB~evv3SnwOy#b{^}lUEYvZ^+_E_{WMRNExd=#Nm<9E* zWOK)AYZok#LR=JC1+j3Cnl}Dthdf`6cp7TWX)Z0% zbPnG1Rw`ENB589TL2NQwZsaI0l%u7{*zu!}o(x#+Iz*DZA$%vEdc4VGe*9jg3|4VC?C#~LY%zLzIn6r;+c8V zd2e=YsK|s3Esk+Ysu0@z1DLczRIO5)7DS}V;Ls`xmE2OL`G+c112~OaHByvYC}bI(2ZW8S?F>^r=FXlO{8uu2Up<}NLcj24mZy+u=s zDy810#?<@O4M>$Dt=Iz(;ss#F)rcdA!-%glg2wo6U`Em?J82Cxg?K$GGP1r}uj!kS z+5GvDQN}AM9zi9xOZqA#CqO>|8sk@yXC$3%Fph$M^udu)#uW05hL&mgvzbP9Tf=X4 zPo={ko!2yo7TpdUxf4jYBLM%{r*|My_ce&33sQ!+BT}bPM7BX*=?l`80%e$x0@#B1 zB9t?UhTCXUlb}`^p8$Q-k_u=AV*0HL0hV{}S>@ zlaTwj`_BCH;>$m|?f4z_D-VIIh=ITTu6hsn@>jt8`sW4$`m(qq1#zldes$fMH_qKQ za%R(w$e&e9m%dD}SXSLvzDfW4^o8gh^(`p6{Ob_(H>+6a+|6Rw<-aC4>yLRzsL!W%_()>t$J$(7{8r1m6;$M#} zK06A+13#|6ho!ImVreON;hguAd+yU>Q2*F7V^nho|1U*r&kiqLTDtg@U ziEe00AWaXE%vt)=)-WaWoCYmIpfN185j&fd>yDv)9Q}P5@d?DQA$|*y zG}?xP$dvxK7LmgN=TsaU&et)lPh2ZTJ_R2{T1B4g41M>Vh^)T}k%8+<8STOqu@Wow z9z?DIzl69Ja*0Qfa!ykLuDMLn%ivkahwcIE{s+>hkO#EF6Do@eT-&OMug85bnC*Qi z=AJ^@i*e1uEMsJN8nH)!!1cRFfG`eY^aLr@weYts{9_AmfWn4<%EBisJa6GgE&O#0 zziQ#@U`Qh~Z{ZUbZUcWR*7IQtUjRNImw($Tf5F0+E&K}$ZyM>#wB=k2k6(lTeyjYG zF@FE!ur2U+V%;7EHhp}_!kgf1ruG;kJd(0~=d?BgSJhN{Er_V5?itS#S#3&Oz5ev0SxM}Ny<}F zzD@8=g7*o&S@1oAZxP%PyjAd7!M`H-yx^SRZwbx|{=VRX;8z6~1+T_|q9?n)Qok&? zB;{qnWx=-#o)&ykFbt0Hh~OQ9|48t!3H~d=9~S(A;GKg1UGOf!Yq0S2)Na8y3Em^P zEO@Wr+Xe3vTo=4w@PmR62>t`X2L(SZ_>kb|1s@T79TvBqx?S)G1m7Wem*8W9?-qPq za7QptI@nbO-!1q_!GYk{1a}0FVzKS1uHah)e?ssM!M`Q=V}c(LydbzI_;JCDg8y9b zLxTTa@b3t|BKTp!Yp|gA;#1Wvf*+Ccoq`_~{4rqq+Y9@L)FUze%sQq1Qh0=A!2kc% zDlg!m){~Q)QXRpX|4%LavW2gQ+@5ApM+IviJ7<-DSFrY(mjvr^e;+oSp3>u67OVx$ zTlfzJ>+$-&U_BP^#s<_=_ezDFU|qLm;qw;$q2QCkw0UD+=Z^{wrMxZpl;CTv17@Av z0RK88{Q5}rMZue~n+(qDr=?ua*}oOMMdbfTu%5r%JbOydU%TBKP@am%g5_1zy?i1=QV$Rd?q`S%TLXyM$no|8EJ*LCav2F{kfJ`P3je` zdWjC%EVL*jN|?5;syz8Ws63!;sb4W?wc3X>*?#L5iaRZ`uF__zFSIX+U9s#rASRk9HPE&B?Z?M*vbcoBa@BJ& zm<^{LaG78^oauuwXMS7{byN?!VWm|KozQE?3>a|^`Uy4H3A$~+1z(Vg6Q!bfM=NsN zZl~jD^BdxHNmnAtYq_VFk>UNM^OM6$N=@WS;(8|(IabsvH!W(BzFe_5(sO*4sIvK=mlL4%nb$Bj<6J!e)#V9lWmPLGpHr!eFwXaoyhN0_j>kSRAlkqmC1 zt=n!VY!mVD&hTrK?gQ6N=!3U7FDDBKre)P@hna56KgBsZk9m$Sf*I!kcIbFr zfPt>XHVfa#urHkIq5pBuk;Y2271S+`LyN8xFYLL=xHyNlSuQ&Xm7Am;#RgK&$tk5U zWnT&xNnH%fqIgmZ`OR*ns#~2z5eZWy*u^j&ic2hp=(6FaL15CX$gv495ecFt%5x=C zL$AGMQ=w1b&W0*jl%nvp$+Mp*7p z-@^I0*V-czW902l*TR0&g}B!Rt^j4nndkX{T^gAExfwbQHT#{=G%MlBcphnwmeB_x^h^_R zkBjJFh%KpxjgM1WdRIhm`)gYP-D8)_>|idN*Ihj6oi^$gwLj}g({>$e=!&}UGCR-@ z7kf*rKv8?NbVXD8qg0HYT1KfBE~`izKp$~LL$vDJ{$2}fe#34w9{#wlCR%l4qlmTO z`+dr!?fr0BixRtkUSvj2h(k#wnVyrDX(C(&3=*|*q#|Z}JL*@{#(_n-MR8e<>NuNL z!(=&b>w=6d!*Rx}#{b=_9lCY=`l`d}1Uc;rE-<*!mAOiX#kjQN2OU2;9iM;YPy*kM z+j44^Fro*t-jvkC^uQfT)RpbO5Fe{hhJ%wZ>N#T0(TO0O7hL|VgA`dWrs8dMN^hfs zd}dcxMvY2jtTrWk0HnY_WV5b%QN^uOB{_A-{FKvN-0ybK@LkhAt(KvPL9{*MvmUo@ zzg72O5iw6}6@AuYwV-WUi4Sx0A9Ma7t>^#D@S@OvtD> z#r<2305~YbXMmW)7M<+=#x&T);{|StTR#QCzcJZyeBc4$q{ueQmYhwTg$hoMa?a&w z#C@MhtWA-&#bxt@T<&#Y5$j&J*)$f79mZ&rtQX+clLCHkh|O-~ozg1<$eb1wib)XW zA+?FCve4_ydsW*Psc;iVl`hZovizDcY&yY0OO8cWCp7y>zh#7&p=%De0`r9d)Fu;7W%6==F z@8O(_Vsnry#@syN3BerKitz!JyW0UApzJFB%}rDKb@ckpm3`nIc>4kIRHY8=*|R-0 zhO74Rl>K`*m7AWP&K7dT%waD2sWBnu(z$d#)$tl$CG^Jszq0j#;4K*pmkSd3DKwi) zXLCsZFUnLJ9|oezEYhf>Q*1{X!H>L7Tcuk;hmrbsBY4 zdal(?&ttCpL2Dr6fCjHf&jpbN?FIn9#j3PGEKGoWvjBR)U!o8y|Gm0?wV={&6m&uq z>qJDM{Yuk!ReClA1zVBypfU^H!5=i6UJGKWxwh+D`~N<$aRgQ&%G(&E_?(;s`B04< zzf9w*O8Ddr3kWIXO&Ey*M{zYGGKStgJ@-pz2$J{0J9{DNo@h;l5OMMu5bHlr5V%|SL3$PQ|=xq31 zl;Ijmw~KG-BT$0gNjmMrl=%jt;p2VxTJVjZA8Pz`~54Z%zJ+mD2w58=JZ=A@Zs7i35M?plo&p~w%7tbLnE`nPg;C@EHMT?vkKUJ9CITt z3%=|%_`YuO@m)e0d|N0e4s4h48;BeW_Ji*x_;%~7z(^#Jhk9IyQ}XfY$OtO&(TfS> zWB4v2^)rEddof}74uXMvwA1s5lx4y}+^O-6g9%2)KcK*1(oUt6YFPya{s1)2O9s+^ zbQ5@WR{k44Tx$)qd*97U{mTk`K4M?dbB!MjtM@MBw^s(r zB7vHi%u4OG79BGZssr?`I@dko(9Ih!_WxDn`}(Y3(f-CCY0sa6 z-vndto~7R^450C+4e+OTB5&$%z<6y$K7#+#j_hjzc?L7@w8 z5BXi>xgW94dgyaM^0Ytmls}I=_2HRdBj}$%{xR^IccH(JyqP~K_`_F_e-iX@;aBP} zkT?2nRPR#HAaBe64)SLHY{2|^5&0Xf_J4r9{Vw$i@}|A@Xz!=Un~);l!Hs7%T%=!h zPcGN%ZYK((ZmkA}HeT&I&feok?{E$uI(8h-R`rEqgbzCfP^y75*9c~D;UxzIdyAMGlbz29@AbXn=wtny1_tnlvL>U|(7BV2=hg#s%GrDOkzKbQ+M^s#POkXDdG!<9ojc9T z*sOADZKuAV@H-AiUMR8BliUG*oMk)Y#KD%ISb*cVxV%NxCHQvgx9m#nZ_KQp0oz1* v5Da~_Q4SnFx_j4Q=ji_Z$Mzj}j_=xicprN1webFT;AbFp?Mq$u{`kKDglLYA diff --git a/board/MAI/bios_emulator/scitech/bin-linux/glibc/k_rm b/board/MAI/bios_emulator/scitech/bin-linux/glibc/k_rm deleted file mode 100755 index 7de503024bbda1121f4090bd5d1e9f14f78a2bee..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 38300 zcmeIb4SZD9wKjedCNMx^0)k>i9Y3(37?O}c5NLrAJ}SsaAlNJ1AtW=Lz$7!BIm1T_ zIyj^<3{hHbulHVU`OsVMy|$OOiuhFnQa&uTRINp&6~9kRs#Gba8p;28);?$EOvHQJ z_y4}Xx4-w-11Ebud#}Cs+H0@9_CDwAIp>z@IWux{ay0wM)%s{e@vSa*Il_?Kwt?oEhtq|#56)9Ok;d~}&^(#OveUI8O~W~7uBP#1eyvEQ zF9lxuJC~d13#jm+{+iUw^jxrQsloY%%gyrvV4jqVb?|hf688p|o2Lhur=2z?*tl#= zu;H3uV{>dxaWqt1rqWQf$Tsu(g`iYDLf}u8brQ2JJXqfloRo(L%O8ew5&;hC!9K18 zaX!uhoY&$Ufzv*|Xc5B^UV(Ec&H+~37p!o!6*3r%^D>;&nxK-drGM4XpcanleMTJ$wmXa|EpT!@o>H`R_jOLzg|&N)lG z9ra}pB{-+p5ms1?aD1;g!m&6nx8lEKg?2E;BJ%ABM|hq^Uu=bLgp(cV13`N%e6=H< zB+TS5KG-+*;Q_&Z4Ps2O-`IaF`@uV0Zr05>_TLk?yWH#}rn3*Hyy>3I+VwH$=`!>4&=4_&jmdkM|4q4g&i? zlmC3+Ex@)s7XuHs+C%=!fky+=FA!e?d<6V6EL;ve3H4F$EbmLeiy{A1E4_;8;J*hU z)2~C=4Q%Uc9`F;uN38T(gmZw|FXUeaoR9Kt`Bo4k{ZCf;Ujyz$|5sRe4e)e_er^FC zj{G~U^1cZ?2l8EuknOo0;SsctzJm3AA9x+gKLncT_Yphze+b-(^tD#{Pl4|{Xpe_N zZ6EMG;Lk(I{4XF}41T*mUIN~NblMH;dlk4F_1pIRHt=ZhhpqJYfjhx(=l>J%6X2hP zkmdIvJdXC;_Li3m{UF`2@?Qu%3E0;6rNBJs^O*l?;CoP?J^nPGZ+TOw*%vkHB8JbW zVM=P^R5XrMy`rKYYf#JK`k6yx!>?N zuhL@Cpx+iJR$s4M-Je zY;H9C0i@P7Fd+~K#-h5`#A@pGrceXqL77cjAT3d(zK%H?{1N~1#;D3#PIwXh7GC4g62Q@ZgnbSurvBm)Naveh+9xB}>>5@tu*U)JcX|B%Wf3hITQ81MFtVi3siNhsB?Z;Q*{x8DgQ9 z&k&2WB8G4%Ll{DV!x*~YXBk4n9)`oPwqQ63YjuWLz>H>yg<1(iOlai{;kYUpVo^AW zAr>H07-FF@o#Ca>FGEc5a~NKxX0rtSW`UCSywai z%%7n49dHvf@x{Gmw1X`TAY3(afx7Bp1zdWBbXMbvq9}ef@z6*m{=1`i`3T;pFD$z5wuJ_ zPJBWzEmYq`d{i(kRo_b7CYTnh-%Y$rFfCW#M!ZchEm(hmc&lJqvc8KrE|?ar?;#Eg zre*7G#7hNh=vn;`u~)E*_$cud!L)e&7;%YUTE2dQ*dv%DKsSkt1al>=i*VEa+QR}dEww+ZHm(T5T563mgKdx*CQ<_OY95^ojEk))Rp z#|3jl>6OG`!5mro6yl|Vrx0@q(e4#Io!Cn}MKDL4ej{;-V2(U}DX~W|N1(0~7YXJ_ z)WgJ@V2((gOR@Ho-E2QcrXD9gA$TeACgP)l8;G|Ow+ZHm)$bnBpsHdmgfpL4r0kSJcqQx!re1+TD>G)EP<&Xq6%s3y(b|} zjXCsln%Td`T!mQ?4Xmv(OGI#YVse;$S-5c%3OU_!3R!cFTT;?4ulWhuNM+QTd%>RE zm)M_=iihjJfMhjhi>jxkEp}09Tl;^Z0Q4u>Ys?kY7uek`&lzvjnAc%aMYYhwi>Yia z{sGgltwlGrcvo9TRbq0GLK#DpKo=MTS7-{ev<)(l1!NSCbO0Zaf4JFpQb7Fbsx6t(@3vd4z zlVfX3H+9f*>d!QYZZWHqpwZw&n=9FJRK>I5EuD&n4a4+6>%WA;Qo_(GOF>?>hiNP%`ElcqoKj-0$s(tqpB^ET9J zi!;c)2aRk$O?!I?D+Tbr?Bsnc!&}%=2QK}0ndGp`l=@q`&}8;~TVV??%lAP0J?+#u z?L$(%GD)=F+YQbdvjKl80gS6~<8!Dq`D$i>e)MZw^T)wvYyKGNhdH2ItGkmeFQ_C@ z_z6W*(v~+t$JY%!GazP7yT-#bkShQSHMifT*`kjl^(84l*L zbXX9m=@zwp76`0@PxfFbo}=v~j2C?susB{Fb)$=Sj*2rtEX1tjN*%WC5BVjaZ^?_&r9M7c!!c zx!^;%A%CYmKK4vOEtVbZK|k8`q8f~u5n8!NmUmmi=<*TpKhPUQo4GKTN0C(g4B#vJr&(=qq^$raB*w?5SG$Yp|Sol zMD$dU-~1=U>TTd!k!!_#2lXcQU(r+H0_zHw75iUkuc~2xK2}aQqotjHdF;mThS9m>>;q90{y2H`|^ZTB>=kquhhKxTAD62f0L$j%)@EgZ9WMa z{i3oAG=G#%>TB)*t@JOW-Ty>pjkN_$TZCo$8t9!$IM}kzq7suAQ!#LXZItaCF2DA> ztd78Xtd6t&lK7(@J(|9+pV#N^S|`-9--h-2TUWzY^ohRs+FWn?I9;azm|B?#8O5fta=&3SQ* zzD;}Muidh#faC*lV`bs)y@{@I#@Jg1CAuy$CMCMAGQQZ(CpF2_iLN^1>RSdRx+;zG zcG^~=tHHRcy#kcX_wf<5j*r@}u*z5X{q`YQ_|Sf0E61tgGP;iC5aS=iJ5kcGFCz1-Dtv95;7yw0I} zTnr+=W96RVD6Kt?KU*#R0%)&RJjJ5he1!QZi~5P@z7DQRgbgw z9f&S%OD)-G%etX+6B>Xe#deO7)-^dvF;tA?bHuLOt9V6#{ymtt4ITu%pg1;2wZ^v9 zDg~kTe(BohS))VGL1QchUXX54X{x#{wQzrOZ}RyKukmqP;tg%XpE>Qt&TDxkHh2U_ zZ{l?=xwrqX3tKkB97PZjO$KEbz4C3CYoBI|!l-s9%-VpU_ zkjQIpu|+N1Qpxg}gs#2)Y5=dU)Emb-7HpRI?{>hW-`|O@%dIg#Md8VPNpTTaBw)mE zIZ78&-R0H$po014)tL%*Bc<>WB$?NOLPw*bjr-6Rw#9OEJ1T5fn}`7Skn%M3-9|yEG+g+>XVBV1lRk!avs}{h537r{~UiG86Z;T+4F9A?Nx}A$vYEycX@i}t*uGLu+n?%Ad4)0 z1^1*c0pDYXrT)G%sy2MmgMn~!JJ(SEXte>OMrAsrGCf6Z^Br8674GgkBl+=rcCL z-Z+)2G%TsEn>!ynBFr-OE&tUGbQ*7~`)h((5v-!uDzD%^d}rb7h0%b=A0 zTPb^z*L(}(!VKe2tKYQO?P4aWCHbx2oP>hC`clk7HD*5J{bzWa_0Axu2i z3d7s&mOBT7L57%Os5SRU`C^E?Mz(#q9iqM^?o=$l#+-+~!!$RVQ5GbgcvQ7S`JHHX9?Ap{||+4)ECd+vzV_+HO9_t9(YxZH_}u8N;?5iOwRs z>49YIgFtf0$=2$VUVX@d^t6zRJc#c?`o{qnI}DRvw1378oxmDZbg9<x6c-^88Pp2@i3psjW#Pj>k1djc2O_XMUx z3dcPGV`B2d4R4@wZNuBR+rc}ItsDFB%6SAKrgpjD&sot23te;3TQEmlboI?S*5OK? z#?2dL6v`*07P>cZXlSbjqL?Y(`Q~llSA8WDfYlzm{qP=GV_>rkh{LEaF=oBBg-YrI(qh>5F(rDCU2-{p;;4X^XQQ~!NQLGgd%U8nb3 z^Y4X0XsK_JBY9MEj8YlX{E`OE!)@(-&y_5}H8VZf+l3^%I~HwC94t({bF%c62~V$| zm8|Z1jAcE_;;r>jYx%vXLrca^oz5x3lZ#xbX2QY3TjyhBSTF}(d!H+@*HtxfN!Pj~ zv;pPiWd2o?+M~Q_mR7(kD6{mH4Or9VXvP((3hF}YwoBZL0;?u`Sh(@W;GFQQ*gLJ0 zM3DF$a>uPTnln){t)JDJ|1c#yy+IO;%G7P5k9`|n7ZoN&f3K0wc}B&_O}zd`lfqbQ zuE+Wf3$WHIjQw@ht>rCJ+&5Km6{&A#6?ezy7blE0W-*GhC-!vvWA4I7hTercLaB@H z!QbSog^ystRqz7oLwirSat@x(`#FHixIA&j73=?LQ+LNW&PRzexv_zt1^~Y(_VH=3 zyW=9V^zCly7=r6NrgsOLI;`uj?%>|nT%&%q;SKmw)X>xalcdyWO9cB)bh^+bsC_Fc zw8g3ru|5*9E)ubpbSIBxNp=MuPN3dTKZGz7LFdN$efl9KEB^FDNHtRA6P^LxA2xLi zvvF<=7!vkld%8ai?)7)Ou3p~_=VFO?CMmV!9vmfV^`Dd(GOfGyX(2DVoBH~F;UlNB zba%kk-4_x)u2|luq3({W5KMd?0o{R6M?aCTyP5iW*4EeQ z{vRf#mj6j#lSPy>B1*Qt($b{$1tBu}0)W0CQntQAz4ZkFmA;xqU$O2D?OVC-^~`9Q9bk4uy9U@6jG2;TcN8qg=#T0i5q(H~khwE9G?0=J+_@?5 zKB%&zTBX7Y&f_cuH&QuP z^vRio=aJAOV_u(=iG5OHw~_azOzaQrLTJDGicG@oNGNSd%+Cc68}L8zuxbA-PvIl3dwEe9 z*vaCE0JNRVw_yaO=sELIPy2YN7Hh%6jhBMJ_0y;7Ru(plVXouaBj(0MR%RjgESj5s zfP-Cscz~0t8ZM(VRaLZ;DoIrh+es5oRSnrmqfS-1cG8AZeRkf1;9wpr=g$Km)5BR3 z%2Grm3~cAqrNB;_8~Tw?m(HfHgRWey?DMsdD%i+Upw$14hfk--W1a_BCJrK5HGDf; zlB_D)&Xy#rhHYm{l2t>t%gj~f+RmmV`vkVLF@a>2$DZNu~X>NvFX>LZo z(%g(9rMVeHtg(=IEhmt?epulneQgcGPs=*Xx}VcqlXI{#P4rwEE63&2p<@_))!o=t zfcuZX#Z_-=){qT*gV;BNGTobJ6`k3;>H31rQ}Q>>$ZwBf5-ogW$dlAt;UoD^Qe(-v zUA?XOf3;Tv$)PfC=XR;-BsCXJ%n9tI2Mna9_6_W$j|2s?rt1SWAh7c|ss9_sJ_?>p z8T((}W82vlwkw$v*e$pwu zzpEE;X{#I_F55oOlPIqnNTEwq=gdfV&Wv>D%&aCl@I6llFZD`(DAKj7VUSW7#)BZpFIqFKA=(BF;U3t1WyDdun?33>>ZY zw=MP6kebUopIYZ+?Cw1*2+!Il{a|;v|D&dASRK~|^f7%lc$K%})*G_L-LF z*1Pwh`8^$@wqp3;&OMren^)Wr!m0EWw)@S^pEBQk{5dWSdkne#C-$4@98HI@(4AcP zLPlkezs&JHWWM>#QTh%(jq8c^!zR;j!wfd8&&N+RG~;q|=p+}JKl!!FfURQ^V{S(T z9-E~u;$TfxJOumM&fPyd1uuLdkX-m?YxOa2YxSF6Zj@@n6QLi&YbGT_QZis)uU*$* z)&+-!%FG#3bp9gqcOa}QyhHXg1i{wW{7Y!tU)iDUx1dJcl*Iu(Z|LO1e#@_pqe~t8 zD@fYH-H+zhm)KC3c?fsZu}}8`YIwi9*4zTCLws%PlenqVv&hs`0=;bVlNz%Wiq*d? zUNs=?!SjZ~7TnR$5>K*R%~+874vG1-=Ff!zWmck0eHt>=nty}@wdNP45JUR4}2o}bBBV}2!*?Ur;lZfP3mHE&0n>c0EA5i@g-3w5UE zVlS%UYB?^R@L9}-`4MvDy)xjXW(uBG9i42&V{a)c~%xe!V%!P9P|VDn%U({EGJlmpte zQ(6uip7;dKxbOzAc|J^HvzLa#!uzu#*8y$u6f|Q%t=H^=I*``#igDiNb5R6@Dkekm zlp3%33K9?CUXXgKpzM<)OAX`F(+Lbuqc0o)m=f!Ygf0?#h|oiX9wziK(AjEhUE713 z&?xTayr&o(5G&VOTRug#$rehsXuj9n@vK-+>Rv|Vd~%?VR@$TXyIi;VTr{U}Blol1 zazXs#s|q*1PqH7{v8v;>t!&C=9WTW{{&L~Q7nyJlHGX}^L0i92$TvD3g}-??{*4@5 zYuA`xW!07w+V;@_F7{)0C!WpKc`**X5AΜvyG9z@Xc|0o}H?oI#!mPZzc{0k!lP zrB(5Xn$aimtlQ315FA$ws< ze@BhR(Dsi}HB0#bVdB}G_IDA2FLrVKNh(pqC|Z$=jmJP18P(#E!4uqpfqr=ecrDS3f$%AeEb{ejz#2eQ+k+I-b$7*K1p6LO)L)fl_bdO-rry z{(EfE)V17(&ajfL^z^}&`;f-G2V1sT6dp6Swotlc%U1mLnmJ0w)V+i?W;0fjn4J=B z1CuQ*8JoT@p}b4DNe6qPB@;Hw{KqpWf_ueU`1|kFljL>o-kd$**}~S}qw3VXOiD`e z7>QGoEq4P$)~p|!eDv$t6Iv;4Ve7v$6CVGH@SF38ZF(mD=c{6~5>K)Ti;XX*?qvb& z<-(2sL0*w*v#aln%A>~cR4c3F{in^t&q=xfAq_1&K z{Lf#Gt+mSyqt3#g4Zk>fFYB4nBVzW55UD5G>fWu}G7;8w_D10TvM9v zRQgHsURIK6GMpZM4-~^MMVL2maEhx~%l_Q}e@rkYHYoXOrqS|Kf*Lc#68EW`$s#u8 zIisrMLOA9YR_Qfo;II8Fhn9<|RjH+?#Jqx5c7Rz<$9|QLJqHCMPGPTAAB zL!b1#>)jm{GQZTcuEwN)8(Zx)pU1@(3>uGQhjEdWKi?dI7}Y_;l)vd2Z{APIu}j~D zZC!1AR;V_?$ohOmThT`~W+(nS_PNE^yZacNO!K5fnTN0dV~@QKPHUdL5jD#l zKR5$#Eyh&sK@lodz324PIfmpdjJ;g-^Oh_%1(6t=AT{q(9h)->0NDd zPt>Z%ZT=1gVbzk3mS2fsF06Sxj;Hg9$^6To{q*TMns~Z9F|h|vZ~41b&RMd!BCiR9 z;_qDt;&;L3CD4ShFj5_OYz>c;t1XPyE%#sRS?P;3d2YHU5?JDy6le_k`AhdN4bY0U z;$rP8?V5mgO$7fD=-M?kT13;vH27DI`MN(6vJ31Lel-;HG{vHZN3UDu_e4S=!-L<= zuL}Abmiwa~Bjkz1nmvZz7)5kwIeylEsVWjb$(NEoCqG2{@AKD(V`G{O{1Sf*%B@%A zi0A-q0bVW8*o+_HH!t^unmy`u0iF>J+I7=sUN>#-yy?}TYAgy8u>PyqfU7+G`Msyk zQy*%MhJt?2GJhZx@q1!X7UiAmTe(bcG%oGc{J$bU-YrnCOa9+{5ATh@dE&1;m;NvE z$E|!@|BC$Ez`N_O;Qwpe(wpC@56UYqtr%Imz_)1X>;+S+7R;`#9;GbDFxH|w?IUeJ z%lt4izbCZ1*&p$Q0s`t|k%+(9NOvjB5wBjzGRNWps#L4j?PAj*jRJ3`Smm=AuJzyr z6JIoxvB==C?PY*=;Z3tHyy+|HtU_Fm0f8aVOe1Qfd0`BM^~U-r$_dvkgPmFVM-QlL zZt%pKB@Tk(JsJ(LU_S&@x|oUAN6eUa{en>zh8b5cph4Ra-ZaDY3#;Z-FRbx-r!JVK zjfq7g^2Vy>SbfkRi)yGa(74HYszj5gRZBl>h7pT2dnS8I){Iy)K=aqFQFKXVkZ@Txtj~rG*)ZCemA4@qE(>R+ zHfBL+&`K?5wb87^XjWoF7J^%HWDI1X`0m@y(w%Z-EwBrtt!jSC7TnhT}k6FcCQ5 z-^ssg;O`pvy9WNB(g3a}G2f9d5xJB5bzjwz%A{P*c@jF~? z&24x`62e&tmwNz0zH4b9LhQ%dObNE*{ z;%~O-i@popg5GDz_AStM8&5dsp)foB^c_N9q4D@UJ^cTP|1rv^Y}1Be{8;pF@ta9ox5r#a#DIxwyhD~P z!%&I$Nc=TIUn+F9(3c5)lhBt79T9qj&?%v>6nclyr9wX@G`1PxcwXqSLU#yVE_5D# zXc*TjguYnlaY9!LT`BYpLgNKvI93V`h2ywg=*dF=o6vZ<8jha{{biwF6ncu#?+HCs z=zefQac!E=xaI&|C3L0G(}li4=xU*Lp=SuaLFk!6|Fh7ugnmfq*+Tz9=<9_(2aYbT z-5~TAg`O|;RH18x{;JRmgpLS}--_T!3H?=}?-N?x8Tq5oxM70B4aXbTVnSao^f!c_ zEc7~||3TM-QLidAnk885mNxNL=+a-RA(BBgJ zA3)O%U!0Mn-EPsF3N>xF@CZwm{lDvoAA1hVSN0YWTJitLLBHvs&qKL!#iGp4@tZlv%eJj3Mv0> zq1E{1L>kxB_;uF%1;l%-zF>R-tRQioYUr zmbBwC8A~0tX2^*pnc5wc)o3Z}Gt!LD6q+fBO>yWmtE{LVir~(R)gP5Ad*!H!*NiP2 zKdy2j|Dx%N>oc`YQ0x=f9pfr0##Vq+sW#nXr6ra`B`CABtWtGbx}*%BZ3?9 z1%jbE%S^0(M_M^jHM~a_x3821Wjei*Num~KdZu$r%g8_@4Eookn_P+xj8@{6vB7J_ z5=WPe9$PlCv8iskg~ygLB9qY}mfeNpEV=Bmo%P#2GJe!V5zyxOjG&h8OQC!v>8em; zgK8u6OxY%k!oBh_jm`DJSc9MU)#|T_u5DTt3Py|d|8@v2i#6h%@r`3E$Eg>`k5TvG zkgHdLu!A6Cr4}Q|Dx5K@-hjUjcj5f3(;-cCZFEe1gFj$JH#J7<$2jBCw*uh_AjGmU zA`R~R>2-!Blz(}B6dq$jY4Nym=~m*cwJ0^aE_u7IU&SeUOgbuvrmebm!N^i^F46MJ z27f&|Gw2J4XylBCF+ldp#sZ8qLZ~fX{$*_K=^VP{`6KZtnI5EA&8ad7?Rp|r~i|M@uD=QPp z7Hi>9w9&wAJs(G+Em>KGh}P_1j>i+d(<()*#dOMi`*FRmp>cVm5vBPI+Bw_5KEbI?vc~NDEV;zGYBDxUSxB7gt^`*_zLmt)dKRc(L?ZvOzbh zHZ}{L8AaQaeB&qwGWCuhPZ=gUZFEiAN?^E_;bh|QQe?ih8HzI^v3i3xG?o)obnG}g z3GG81?5ED2wI)_fWE7mxRSe;5)+{%_!8XRQEgb66#;^N*QrS4_3gVWJ zf)p{I<=9IrtmsnI&3KtfC|m{gC_0dM4o-=MDl?_fNvddQ7SR=|kgvt+8dR+nh+@Kc zCOD&^JVcLUG>WdYxv3DSv_#5rCO}0@5GfH~I?m3ad~cKUj_TjbWk#rU|oaz-b0U??BxX4musdPRSLbjGuh;Fl(ZGa{9#&XrDyW=suLtL~MANU*UfU4iOfsethr4VPK1Ru+*~MwzqG z0lfFzE@`aQ>ap|yl|J7pt`FFxtkGXOkw(LbWL!CX4PGSg?4q%%xguqKR)Vyb?h9G? zLilv8s=*?EboH`eTBBoCgCzkkS+CC|I9eQNzyr1DN^2Y`ifkrt+(JdP~KW7l7 zqZY3nRuN;w4O_tW#>iu{^>*&U9 znnuT~X*8S9o|QFQ41SA1nbdfh15gU=LniA6e5s&br%1Buknt(2Ijh~_P_VJyZk`g$ zP7#GDePBp)X6Dr0*sS}Z5mAq&6}8r5Haw=c;;aQ8b1aY5MH=X_FswK;+KW46fNU$p z8E{A{)mV!FW=tm|<9N>BvIM|F!CC`Y9L}QCv%jqx%;J_G8_%hq1;M^C*s*-z0%4_; zZM!X5oA_4OVbv(>T=s_5_K9h2vq-1LW%5J0oa>_H@O!bQCR?MH!PwHI{ROzypn%=m ziA^zl+rsX~QVt6iia`)9L#a*p$VAj1S>Qdo$=yG zx4H?Jcran~Q)G3Pa5BHJA&93tz(aehG0I3KLB0#ZHKFvNeKC^G)4Pi;Yt3Z+41;|= zA}o%Erq`^HCLERh8bR2s=-mVbqVC_Rj}RmN1Ue-c24~njJtHNtw79gm z%oD-)ZSakmQGd_uxIyqYt}r~-kb^g2OG=ANN)i4o#c9R3bz#&kLuf=)hzV0suylVU ztQBKRmcMxFwAt4fb<4G4y$+vJDsEWYjEpM8$Bc@XH^+*(g@_*>asnUHV7JA~Lxv)j zMX}9@G2tL$c-vT0Bz!1He!2g!$-`&v zcY%+#%=95vNF2mz^W6i!d%%askHUAJgO5+AY(75A=d&_C<7atzyd)vZyBR0j)E6iB z5^O=@7|`}%%eN5`Hs2HAdjfoXMqwZ1X^qJIBh=eU04T& za!-SO*!6w~5#*!(wt;UO_#UM4tixl4eANT_DAH2=P?6sU9ex(RoesWr*!!?2vrVckpq~#a8fjvmonWc|6;2vM<;U?segJ zOdkMkH-$WuO@~d>W_YkX+QSPtS(bflyb0sO zF)-~ieg_7dChtSd*q82zu*tWPhHB(s`aNOvpM@FNe0WTkRqv#)sXZMwtIfyI(LC+g zDoyhs^F@dc;$%B$TeNv+JGySeGc-K!v=6&H8#_b#BVzT1Tj&}7L}67k{fok?2Ko_& zS-aYEqp<2NdrwRs=}|TQRl3p)$GO51XdKT9vlY;78e{O{;P_$``Q|9O+JB*yzwni1#N4r1>+phX#c?QD78l*Q^`r_B@N`Y;C5u7m0eT$x`@lg*ee_p$f92qdl4om=*Xn<^ zhyKXMEdSTQ8?F9ie%5DL{7h$k8TpGe{;15}x6Jl;WTg)}tN!Wd!G@zi`?DhCudVMA zt9?v&7GS6E`fesazw1d%7e)C70LP(^2Z7l?gMs-?4sMDgz7UvSci>1Rz6_XeAht30 zjxBcJ@xV(Rn4gH?YbH!A2qPkp8)3f4s3iFm|q33@o#|nntvPfiyv)B z=e|4I+q=MgA-|n|3OEjXWHzRM4B}Q`J3R+3vEln_k09kA2)qV(p(WoJfR6&-VBsr) z`L0(xe<|?jo!IMWrB4N33S42~1>~pyK)tMg3GrK)hmlU~2j+`VZQKORm!7Kfi?p@C z;r~?Mucdr(VC_Md`#%s6r+^;>-e}=FflGdvN&i0Zao}?hlK%$?JO9h&?r&l4|LgiO zzF%(Tm$wmv=3(2b=Vuvv-4Fh)PpR+cvb@m{F~bAIT&~lrlcd74_1Po-uiN2=l5vKfjf~-{W5(9@RoaBZrTO& z&jY?^hw?wf0pOB<$M_Nc0&NxWru)_RikZ%Ri<2J1_m{2w{{-BP^2dVzGMqmEzG9op z&Ha<)-wkZf4}&m2JOw-)_ROi7>AwX&e!%6PVBxoc_W%#E@G0O!d+@V43-dddwm%sJ z|9uYd6!8Cpm3}d>^ZUDB1|E)mzPt`#`{x0V1|DJI24MOhyFTuNbbhb*8^AmmaJIY^ z#2n-gfo6Gk0UKyfz2E|E2k?<6)!tjS@29|v!GDFte*icLe8R%qE4U8$VPNX-UEnRi zcU!m{*n|GC^)&!XjP55~?xT{wKpO_!h5lJ=;W5DZus;N%-!Fk!{HV)KzfF0*0(=k3 zpAF3V76U&BO#KiCfu8`LCH;%HS^!s~ex@=1oxqEM>1T;|0v`cC=T-7N1>6byq^_9$ zYhZrG<8}+b1$-R*6D|JJz+w1rG!wI9k#+`n$PY61ScFBfz5W@D_0M_0oyb2Q^|QW_ zzAT8s-$CYA@Ejwi{&OO{TIMqM|m#+^ZF0$D7`>C z0USjBXMow>KLWoA`OwW$UlBOhIpn(ncnk0@i@yTcgnirmvw=H*0(-UUUjTf}G2WH~ z--Gsyw91bW!yc}*@NK|H|2fm%yMXDho2~M`4?N4!o*x01b3VdBf5W}D{08Mn_$BJ= zDd2pJ2it!f0lw#e%gvQ6(_bP+d+hI#p9YRY9y{HQCI1VLyWDSD{O1E7cgS}o@Po+D zbtmnI`*n{af2+lR9k9Kg_dw&dz=vSZc7N)?Payv&EC1Jlr^DazyBw77o4`kqZjX<< zfo=af7+)#>9`JFbPqy;!0`9ah`*SaFH}IFN^yh({--mw-xcs2YeZHg@XxtmzjsCIy z*%{#dz{)=tX!#I)IDQvl`=g71o!?_GB}V&sYk~652A%`|2D1`;6YwPDx4(Da%yi(b zNT<9lz|QZ%e+T%AhhX1U|9=noq{E(m415IrY5TJ$fP*N{XO;IHu!;UEv+92pSbx~% z<~#;$&V>BQ59`HYd{A}+s;34m1>~}fvgGgt8GJOs3jrY0SC07012YolzV^1QD z^8YLF6W~9Bbn^cY_z3U}Nr%4&=7&gZe{~eN^B&xB{l~4q_o03z zZ=v=r;5O*{MXUYa1I~y4vi1FA;NieKP#@d>G%&wKW%uVVf$i~Egz@(>a5v;dH%t58 z1zzLuCw~SWjq*4jvb=l@gdy-ha0|kJK5zr<+x8Dv0=t3j^2PyALjHAD{_B9}0Ned} z6Yxogzchfmp$}Vs31Iv1fcQ3W5cw$!{R=j#H5$BOjE%>i*;g#vk?SKy)QANFUF%=L(8y1Q0^}K>SAjUTRqD+WB$~+)xK%f zGiP6qOsq~l310{w+e1ig;#6SFHG=EMlx6koL13c2g?|&(Vzd^(A)P1Y!natM-s7Iwp z^F``b`?!Ng<4zI01);XOX6m$9z=xMHq-ktM&;pP=SRILkB2{?w)Eo=rm)Fpcss?xN z8=LV|*6=OkvpcN;kEaZ5Y!kruBKQIgTJ@Snqjp*~3Qrdt!S0C+i29dnp<%iH(eQ{}JiMG;@pj2D6ybe1kgLP{)KDG9(GJJLQ+}4PF;(qLm zk!Qdf9tlK@SeSYse-!VC2xE7jVfY2(!7`pEq@%)hhF)AYwp?2l3m_b?!txT0@1O7* zk>axQv6^T($^aRma3Mo6BOPVYu^@IHKrhQ;%T>4FSNJ}w!`TC^@8 z`wg23__O=zcwT~T!y^@A1|dy|FUx4E!y6nl{9+!P2IkdN#UjyAWDd6a8GP^(iw6Dv z@RTVt=ggi~jqDt9H4L42HVBZ3x@$38rAurx> z;m5-p)(ssx`7C*+)itl2I!z1sLxElu@C^o52F*A9tJhDRJG;utG~+WS#tQssbPmiPr zoN_gW!a*m7-PQ%U3CkIY9l^_CPr*<$E7}(b`}EZswq9avIQbz3lxU47%EZyY-t(fI zs20GBNt%r;^?=>qyvkVycd*uFi53V1V^Q77!`4Rpe)ZA>(NSpH?0Gfbc{K}&EUWI_ zNz5{*aap7eY6BP4EPbX$F?8#*tfC2h?yS$K2QwevJ0np9*yh6}c)6+CFP&8vM3Wg; zgOTm?K||O=NZryzd*!CRsrO@eG43>9M)I^jsMq1BoY}C$7*;QKiR{;_7fPt?^m-ch zc%wFF4wQj+zVG%?zkRT;9P5}N*0Y`L_|UsV%p?xiB| z!oe(TUKYeSnBEu-(=owSHicGY*^bN$qJEB6c+}num>m57gY9BBJba9^k%)n+oiUJy z{cU#zAlf&trluZ|&5Ifvpm2)?@0yP`!uZ)n#)-M7$E$A*TxeEZ>?iTj2&tZ4**Oen zG)AIo9QGbj%#5u-%R<-~#feDfAx45|3^ejJ6x{q2F|+{6j`nJiW!P-g0u0qE4zF3* zv>$}=`Fw%Th#CmPE%zz|J4Bk7Lob*UW8ycbd*{xEdoVDQLXMbhR?Cc8)yS%ObG`V5 z3>hGnjJ1r-BL)KxTcJgxX#OfPEu2~}9{;mGOW7>lY*a(rv8mWuKK*bb-Vg)t*yM~4U>|0dTf^YMe3#9V?P*Kd zxJVNwF{LgJ?Tp4y^&Ia4=@#K}mLxXZYw|-`$YQw+*f+Mgi{n7NIE^_lCVvB_6^#>C zugu7)hoT1GR^_aRoKB3gdRbBxdO~@BRewYM>ITgF=#{9yzA4Mgf?*kU1xAD1V_}!H zhE!%Hrk!O1$Jh;WNU+nDqE=!>g8?4Je$(cx>Bi@0Ut=fJoO#ox&hgEgF$1sg@hzA- zZB8{-w{Q*4#=vhjs8{_sVe^UXX+#2RRoFBJ80 zhc6f54ZW;W>0tIe?;J{j%nO?vp@G@cEr>Pv)EQ#zMmLdO f!N6#lEDgWLYp@p)*x?fEqW5}R+j8Iff%wH&iQ3juYb}aZw6r~GsB)D{BSz=>|JT`P<_usz z-uHQa&wbus22S?=@4fcgYp=cb+WVZd&pEf$%%7c;lcU+cTy2m>wCfI+yA0vFr>&ea z&8rR8#%Q0?E=H(n%qxq62FEVMdF0`6;TVMDI1l9UI1h0i%p>n~ZOGGb91Un150=*o zRDKZg6UfIgYO1D1tKCvB^K+54?tkDY%5(F02$%=uVjVo(sKmX&<>ui9=3(beXlY(P zp`~ejOLJRfO;I>hRBGjcwa7N-+Qo=j^+*JNs&RZyfkG9sz7aSm4}au;5f0MwM?FlE zn5K!+9&c$&l4))z#9M0c7 zCs6T=5mL`*`prh-WE^uGnd4P_BEsp8bVjdH80Mi}q2e_vyikPHRqNC0*_t z6%HaCh4Pe(`K>rQfnPvKeqkJ=ARq0F`8VNc0>6;L8xS4`J#C8g8*#Xh&psqh5+i>R z6hV9^j#=PG8z#O7$0MMp{Sa@(!5?jq_5A=x6ZCaELgxPj#{;0hTj8Au_W|4do&|P+ zp7N3YXE=@{-`3Bsn6LCr{s(aw$hX^n82Dw#%YI<~pK#Ox-;a>|QaJdt<)iPJ@6h+z zz>k3bDbTR|2;e)x|53zQ{u1C$$Y=NW<-mo&-&FKtNe}thPoyscegxQ-uL5|KYA^X$ z0T*v`xkn>B7nVB*VHxu2GnjuJ@Ntyqcq6_Z*g$>j5GViT#E^G}%3lH81p0dsGCzcH z7WmPpu>30EGL*OVeG~8z(EnV~Z$M}OZw4*PCxK^y-j@F^;42+e*=7{ zgZ>TRQQ)^$ryqZ_Gaj_yN#wN1XLv z09*)ckB?6Q*P(p7%DwxY4_yRD0^naA6 z5qKZ?+v8dD`&YDv+WcXop~LX|HB67KoE9fD)@a4TMn_}&TCF+MXtZeU9nEb}Y5W_?z2;p)_~4 zr@4*n@LvlzuV`y%kqWIEATE`lDhgYzK}{_bKh$n$5WAtpXl{ij0^SB zLKDL16_G=9-q?n|HyV*HjcUD-seb>NbZQB2_gjk=><9$3IrHbutoD}{m84_VOqz=o z)ZhCz=nNF6r{$c1Di`ZAa(CvrvXHZG^31`%0*n(LUL5B%H)HxAr0HrLk<&#gAA!nu zNxqa5`dqC;(XYW8buh**=j=Qzl<3Ryuqff2oQK5~=Zd_`u$~>C=N^IuS(G6bGMx-D zX>MeAji%kk5EX1@2~<8D5S# zgdrB2I~bm)X-_e{0Bd=Mv*05bVzKcYLoBF%&JdH_0fsZ+gBYHL`I6xfO?#c;U`;#B z5YG7sLpULm;b*bNXNZOEF@~5tjx(&%v_6JjP3vb!CklNH!NS+Y(1mq8Ll4%(459b} zhFD}5GDOdeWLS!Mlp!3Pm*GtKaE4d}k6~D>X;(4CqNSK2CZ95fSUi?9#N=4X5Q~l~ zhFHAMVhATammwBk^BIoRG#^7O2J0BY3182!NYj=w#3ErCLo8&Q7>>|1o#8l5Yhn0l zO>1WedoUQnMi$5aP-~*u+Lt!${r&eeE%qc=5So!^z6UAdC(Lg{3Fe~DYg*!l{^$2< zsYwPjl^VSUe_1RwdL3dqqdkXH_>HCo>CEdnAefe<(=>Z_38qEqXo=RdT`(<6_Y!Xr zObgS;5N{TICowdr^+W~VO$^J>dfElwOI$^~OfW4_pG)i$OiR>##8rZ6k^1$-#e!*> z`Z8j#U|Oio2K5vOeuTK4SQEU1cn$HfkC8C?DdH&cVZpRueIxM!!L($3Gx09Lv}pZq z;_ZTI+4>gZErMy``a{H<1;0$Zoj5A^An^|3cEPU`?;>6%m?J=cj@T!dBSAkvTqT$z zLO)1cESMuhKTPZu%n_oS#07$n6CWei1osj55g+@A?e8as*FyURa|G!$qMieSIg<1O z;$4C{qV$o(+XZuE>0aV3f(wYp5N{UDk){_DM+I}l>E*=jf;sZ^D&l2=IRbSqS9*Mc zITCdrag|_>NS({ho?^iqnffwfui#>0owz_SN2=aVtO@3b)z=Uo>u38pa`h-3 zGQso!`g6oS!Sn?B0pcpb^a%Pv;$p${4EkYWui$oKlej=IJ%xUZSOZ4Cr++1X`EvZN z*pWV8-6H)etWot&EDW!!*N@!ia+|-0vW{=g`Yn$CAvWF33oDWGUQhf)(&vhgZ~-T@ z)Pb#x#LBfu&yG5*PrG&*!}O&vEpr?gb?31dWYC`98$SU)&+kpHqVL+lwI^sjx(^eX zRp5yaQz<+D`MnMaK%ZFb?sZo#jSSkKJ7MOg+|FH*_nzO2^xDJ??o^~870EX@!OG)< zz;g(dto7!W>=M@}^`;_j{aa{iY7!?>^GB#^WsdnwMn$OyW{bv7Tpg zPt2;$@ft&BGCA@tvfS|ly@Qj+6`EqaS?X8iKI?gAw^dZiMb43OMj?_dM&vLU99;1e zj`AChx*+V5`r5?${6wUn8#5t%|5i#GaVNX_(I%f+2y>0?%SY4ddM82N;Ew&u9J>?ThVmrv@vkIVXu-VDywq3BWXx4;}-HFMZjs z`Y3kPm6o8U-)G*1T&X@XT;GK%&4(qym5TK1Sk-8Hlq$Uu5+KDq4;*(eMfyiS%mP0~ zp6-1Ou?HE8GWK1@4l{NKV^xO`yOpsxW9u2)!dRHG`x$FSEVj>UB`;<2E+#Kx%==cD3X(RwlW>Lu{PnGUi1Lz5gl#_Th%3qp-k2A9Qyeg@OvuA<6stky)F(s~@e2 z-*p7Zi_jZTr%!cCVsZW=vk?mq{RObBHP?YYw(pXzU7oIw(1qPyCd#lg6L&FIF=7-3 zf+yK8%-Ma(yI5KLuEY5IOcgTqUxHD>s;gfAwQ&6!F3-jG6~?C5jlr~S6xQl5BV8GB zPoMNlLRc)SHS=bW*d6Oj8Pk2{HY{e)*EH-!<~t&t+vZcC_h#7K4>l#cdcI1@9>K~G z#Z-0Y>F;I8zACl3H|*Cyn3CpYHSM-aG^&S}B{qLjX=POT%x{TmTuVe5Z-FQEq*|G! zjJv=lF*v#=r@?dQuF({@H?Y~J%+kk=QlUGx-&Gy^(B=8s95jD}H06^NbSWrkHoEpk zx(`Q#%MPSt5FUV7G6*f3yb6nY`h|!a>ijRuEH@3VTxz%~CqzcnCzI4;Joz%Rt~1X@ z+1|_G1(j3bZYRP6QaSS)aFwJ=60-oEu->uj>Ta2 znV+j-ipyqop3|1!ESc6Hj1lm!n+BH;isV<%j#gkj9lctMyi+0M zp3ZNe=+uurotqFwznYq0jEtX5bdlB6SB(76Un^;@se2>GYLm%6C?lRc$R?Ssmj2@( za{k;usHoaHCREQ}IicSC-f`)z`2MaFk+=5`(h^pwC1wyT5|+LamZp}hM6T88&E?d< zCB0WcCcTe5Be(W>L&^?Mxz4;ZZcFYR1tkGSq2-m$n-Nea6 zV=P3KQVp~wZ`{v*dIlWn>imZsh2W8 zO_#YswZkg1?oA8~Qs~Pv1MlJYG3EltMF^P#3UIyzNo3|DF>DC-=`+7A;~bN3WTf!e zLRGwhc3=kiHk!ftxQnLDnE?{`l6TQe<98iHnmuWVe3Nimn;1bo#qTRNM-vV#FS0?Ubm^KVr zWW9NXwMtQ@F!jTAN0Sd80a@DaHXO}|h%)bU4aJrx78gvti@=k72M}FJCwo^P>tCFY zZbKw~A|c_TgrqMrpMXZUv8QZ5$$JysG9ZMfBKwxK(WOesC^~ic%&|H$w!Tm^3Nqt0 zuX^g7W=O^UqiwACHi6XnwZ*)$HctS!+_=19o*2xa@O?3 zMrK-j+gO=`OeBhWWX-(cXrZN_t-J^o@1hpE^Te}D1ErrC>*D&6O|{)LnAMscxatCp z)NbXlWlN(F!e=&G7L=Wu$|I3kfeSObiAI>0N&{eLo=%<;TZwK-biuEG%3>0KW0Uky z=S!Z>tsvV}ozsaD-$FEca=fRD22OuIJEyW4^X9zBEy*wE#^0b{_j;Zglo-LK{)t&L zbG(s)YNifDs$k=o=a~w4;`(ek%?IBT`_E2Q(yzy5s$@8a12|=j5Lt|~qnP*%cjb6b z=PIf=NxjFDNAWiyf3MSzvC|ghUzb?mzRvs=FWz*=_7%iZwVuwskpGq|W2sr5&W9L1 zJC^#$)A<+lN)P|UQu92W*ATrasKZ!%%dl9g!6@u`Q4+#NT`Uzb{5`yzp?`>qtYtrZ z8wBu~PfBZKh}}nukE!|>CDGNBK#JuLtWF2idU)Grb9WxQUT{#b7=YkcuZk34Ep`w3E-oq1RD5smw9WemYqM*&a)C@U;Y!eFR{p1@=&aOK9-&!?>xc38 zQF>)Xt=ae&A(XlEu~WI6u*@i%x5cIByEG2*ciHltMElPqU$zexBe7vBr)Q8C^%8$9($l`*DYt6-$cGj zTace9ydyfTDsoX$M!Qd6cG*yOa%PUtOo~eLduMiAegN%HOedp?_3riKVS>p^o)CYM znwSs@aZf1iGk^51G$OXwH3!7&-cXafr}Jen(Jy>6y`Ei+)|POFsF=>KT0iDVc4w_# zlp!egR!J~zJqd=(~S2#&m6490?RD^b1H>- z_-z!Q7MW>Dl>8ic(intW6xVYK6!@u`R%9AcqU=d~V z6AKEv=?Apq=W^*1P<8r2m= z*Q)c=)K^^k^?=q8UZoL#i8ujL@FD&(aPQ65_$F>3Zp+{%;xA{gPJC?!w-8^Q!R^FF z8Eg=LDuY)OpPj*91;%;}#ueYwJ8UPFkeK0$kL-F0*QeO--n<>`9JxegwSB`;-t4zl z!`)qV$YiPHqe~HsKkAdebMd#kiz)itYqXL>Phh^#DsCuPKP&#|e558<=foeKg-FRu zn_L$pByFRsBq3?ht1masnvr;vO!m7@E4R4?Z$R#Xk7hxT3cy_Q71^>|2J!KDfph(pw+< zK#yFv1B>HS&pnVg{#?&D5yaMy)FQ(~3q3L5#G`C;{Z_HFNPep9Yl+Cn)GM;8`p9Uq zY%3*->1hTf7DQ~z8pjJ{o6rP{zo+YbW)MAxB6Zv4ZF$no_<=1_*n?Vvq3Q8RMx z)cxy+p$r6%U-BQbDZlGKz*tMv6vT_;$C3f_G-nCFNk6dTD$Kh{*oaUxwOVqd%BUoze zp51TfE`s&N_iWfh@E@{O3i%Z2$Z^qnmU;#e;fQk4n+>b-9#yI&dNc6xm4~j&HVQ>6#8MhP`+Kr(Ifeq zX`G?ZnslMzb|I@K+)n4NI`f({6soogb>~qXh-=A6e|_?XzFM94$fJE~BNvV$GyM?1cRH$>vE#eYjlVQ{JUe)QL0 zC9g|G*PVx}RYUi?E}F1^)_FNvGSK%W`+7g@aGMWGvu$iE0oDh(sRQ&tS3y{H#d$S^ zz-5mu5D7ADoo~@$`7;da>&_#FD7GxI>5>qcpckY4`c?Ronlu+QW;Zq%Y-6T%iN{s4 ztG8HpJq)FEy~UL*i6B+HATffa5;ggZk_#P2fmDn;M3i9+x!{WTEx1^MsAjB6O}d2D z)qI{8D@Q}r)FdwxN|BJ7M0(SMRQ>Q|*nF-^`3UvK_KiwS8U@moE|q%a?^7wO2Hsl9 zy%{a717UX_xlp^^c~YsP%}0G$V&T3gl$N|dF;mtK^>`8CSMoKg0D}ie0M2-pKxa@J(obnp6@L?h==~ogMzFWzcNt(2dys!G z+x_RfL>FV8AGp4mlxln!*jlX^3(j$Gf0O>R>m|?kaOLtq{6O--7Ep7ww8y4#;H_CcwTd}?-V_eT9#N_-ZI-1t;*Pc;|zlGoJ;pHCI zXW=*HvLvzRF%clP>qx9`uIE->Rl$P%We9Jrcca6}&)vh5K`Ae|pl4qe_VzrY@K%zS zxv+eGMD90PI2X%jC(hYMve@AvKIhP_6NAX_y>Z7S;MNnxpUp}?dE20xo%iF<{yhHG zgzrQ7#t;kVJcQf1(c#R>U8K*>3?L0WH|0Hm^o`O`)!yDKlsxdq)Veb8f3YOMncCMI zVJ#)QY`?h!+oYuZbJu=kr_mkvPB4G;I}A~D!&%1pu|Ah^j^6h+dVVBQ;ZCoEvFOL< ztgxW*t+83(Pq3576N`ZHvVoSD?M9r?m;(hVm z@n3Ivi(8^&zt=W=z?m>|J{Fbdj^^l%y{*M}5B-&=YZJ^<1QF3>Q1;O)--@}mku5S& z?KY-korAe{q#k8zsioy!1gbxEQLhGxe5T75#&cUa`7;Y$d;4bre7dFHXsx*bWJ>%+ zhv3nNqo-Ep)|wG;jqizzi@+iQBmTAnAG0U=eEJ|%u*lp73Tdt9w#Sg;c^p~hG{i9G zdA7d?O-xPVc0O}1IHxA@l7cy1qOw<^6j3Y;4!tJE@-l;5^A`w|Jolpl75%o<?X%E|bfduX2W&{RY+w7T)(t+;7-X zIVcw^2>8j`?KwO5VPXExlRw4Zo&0lj<8IGm&&QtkZhY>Yov$&$jKO`D?Ap1Dgfc+n z+Vz>sZg}fWh?6Nh2W7W=Pc17qUBR-OEK3eyFWqIJ+xfiIKX`Wah7VI12sig|4fSQU z2IC1_1k1yn&sl|@CAImd52>fYv*Rbv8YC<#BM|cn~L|@0d3ux^uS_7;Jt8U^Yq>-uw#gsK3ZE z3&(@!d++T0rI6&zK(3oSpP_z}3nyE-mWCzQb@S1kKNsRT6|wHhCFT(rhPe%Y>_w<8 zznr^btya_Td2DXQ#^-kKL9us)@eZDK$KMOSyFKR}tf)8nrbJ)xdLDc2305SHe3DC7 zWW{!s$7_y@6p5PSp2y1LeNaKF<~Z-I-~6W?8VZOl1m6`kZ9fOu&rm~3O?zX%zh&b= z_SRqHCxkV)dLAnq6hB7gQ-wWB8Bb6NQs;QoNq=_cdfhkwspQbJRCyxOAKPzh{k)UZ zI+&V65%WBD_QvN3`f***Qu=R&ccst#1IC5Py>9ktE^J!Ngx3+iRtd(qIEz`R*1Y9a zbt>>D>k*}Li8QZ znaQu-JX`n`z)23*g*lk4 zmd}V_e-%o~7`Ekz9WAh%9*jrc3&w9amaIAE(+lg;)51+CgY-V+pA5={5b>fzGj8a5 zP>3$AbslHlGqo9ad$9yJr`a;>z;;~woW$g+L5*2`65I5X-|%8+ByYz|Ad%U`1fTNh zyD;UOkAewi6ARpn%j|kB$Sn9gw6TL!Hoqu%>$@hQ*tNf97Gie$WuvKH1x1;q%wx>X z+gc}cPUJjvH!O;0fm{}CV{#rRL&aa6>BCQ^a5;Vl&$&fjQEVpjZDc0DrfDZq({aH; zTkVP;>-F2$1TM6%2|NYi9oGbmiun5*evitv4S&SdjucM0lAVKi<~*7ZQ@fn-=d2ur zg|7MR%g_o=x(4SQwDz+pqp*Ae?m%wf(9l+$1vXW_MP>^0R$uLaY7x!a3y3p4tTC`$ z%`x(O&jXJgeHa_PXYJ^Ncd+71T?}hObJDwu_xjWWKG2k^U zi2Z+7oiv68B7r5JzKs2TG5TFeLt6$-4^r$tL0wWOhfhYex4x4~?f$(hesEAterB$* zuiv@FXmfB;U#`fYpO%2$zG&6?8v1lAFZWERTa4V)^E?u)`w`|&+&+l+ji%BPk>iPP z@xsrBw|U)Z=$^Qs=)dx+)4R$1`(O}S;to>84@ilzR>3sAD>;O%Aamn2eLKnP39?t~qh#5As6&fKj-SXWFg%G|sb*@o=U*0~ z_Y};5*WTlb?RMdkYu~z`dT?k5a-D8zjRhPuwc{*s}pApHN|3 z^oKKbkCyX-l_nSQh8~CuVZFItZbG?|)foHhYLaDL!tQGpyGe9Fh-a?$;F~2|9+N;jL`dfCtk0Vr~mzy-GP4BXV>?`xhN4oj!W&h21kkP%i(F= ztxpSi=^Eu;mJUbOXfV(9yEspaqKYr2T?v51nbue3C2eL;wfz5t*vh?K3b(5d=@fR?`6 zL|>8q4R~ynU3y~ZU*l5yne=7#t-5tka>(=eq%Ba{?mxN`!|z2T=fzE~iSh2rVB`V} z|GyrH9nOgc`ad38(_h{D2hm6TWc1|wk)hEA{kgrp@R9Mp%45dcmG2pER9<1cR#{}c zQaRapsq$*$#mXk*h01`jzjB4KhoxE~p8?N@a*ceP$KHjdNRJ1;4RP+@>KTMM+e6CM z$aIVH(+}ksXRmabD@gqohF$yw&S$aJ`QaugvZJ5oBtMTp>BR zD4%04!Fr}=t5rV78r2uFOgCu<++OFFWZFTTx!)&<5YL-7r6YWe*;l<9rwpShaaEBdi1TC)bAh_J1SF?c%@t4p2>&`ImfB~Y$kQ3 zq|(3XFJ@Bfgb6OBa;)gT%VbmtIX#YkG?O}7Qlm`$Fq7)Bnb3aqVSh*qe&S~w4SBS0 zpMGH`{SBn2COt&zD>JFjAr%*OQQ%=IFgcU;LyHleo==~ZNx#cV-!AEkGU@BntaeD& zvP{-;tH@K5-j+%K9MV&h9ze3bE|XejF;d<0b!3>=p|z?}@V#)(Y<03Mx8zW4pPTlI z`<>R!*bMxDZ)fTcE3|3idv0CmoHGhjULSAcl3ByHa@0#DiW$E}{ z>-q|=J@(~#x*kU6?p`;}ZV`!`C3e;G5aOGIiQ#NUVgwZ&+w*Z;B1)|gIT+8+1r2-U z@6oVnf0M@Zxa&Ti6b84E9T9-Gjpa6srWC1<|C;KV0@ZRiOy}i@)S5#u`qe`fnCq-_ zahzmj7Gf`=x#=4?c)AWZa1zy*$mmQ|7i^5Me?i6Xv z^WnUW-xvE`T*_8O8;8r#!7_au)Qy$NwsJ9#V z6iP;K-@+Y(Q}s4Tsm-O-=2mLUS86M;)CM(X>ka$cpt@w1>Ub&H>fHY$syl>P%2M56 zOLMbbmgZ)=EzQl&w=_4qz|!38LNyj*Z{-Bz*N*f&KG@cvb#4(ms;=jps>%7hEt0xC zQiju~;^#2I!9-4Q8$Dn!F=KFW8+{~VFl)L##D)d8 zJ;m7n31c4%PxjCD*jBcM?TY6Fw@Pc`XxCP0O&smoDy@m5U6!9yeVahnrti1P*uZHN z9>uXw?ry?mg8x;$kf?!rr5|eYKgp9=UN@LPmsp)MJKZ_6)15P0b{P3cXJ(L@*BJTit*bsBS)6*7>}v%}GBy!><20M-mgQdFLf$N)cjov- zcZ;)hPAYjbkzvnzc~tZmNpXqvOy?Y0mpXwdE8N&xx?$HcfyyAusPNm0vy0##{YLPi{50{21LoWY` z{l<=7MTfE29bf!%W~e@iyHwa8x5zBrMc=`@ajD1g=OI*sqnwazm>}M-?|7;Vy_~l@H@sVWBL0_`wh>shkcHxfDf52Ji`|2pI+|B?&vpem!npVGiln;0 z@SqfwCuS(`2WYX9_iCGEq=M}JP1xOMu|vV{WeVaM!%VRu>0;c{be7K?3@NSdJLMT` z&MXV^u^HIa^?ZcH!#Cw@%$+e4nGQe1sJHq5#+S=xaRbRfH$K=58v8o}6Y}e9Kv#FBum{Pfjq- z@BLKt4R3U+W?X!o&%7XoO%*=q-%aL2S&?hMwzLY(7*_8yxtSh$*eH7brt`o8LKTsq zsH)ay9zy1RTnn;puu}dFM>(>rVO)X@sTiAs;Q&Cy$4eP6kT@QkLcCDoBPBi(@ocpv z*QRh08tiV)dzQg|v2rch^%1JI9&=i<$Y+j2zruPF_fgcG5AiTiNy^&q^7&2Yp*fyT z?q|8>!sy9yp3Zj}9fEeO>V0c7oAT-2SEDDd@pQhzjI*inYkRwG{X!vM?R^6N=Fun~ zyN;YyYkq-MD<`z&ulu>!kK7%5F<0lwIP^Z!XZ{%{xex*(^?Vh&O?G{ZGE?_@x>|v{ zQbvh9!89oLqT4Q1;4>dh7ur;t>RoEdk0&a-%28;JUBYFTDD;^ztHkF~k95o!$nNPH z>Zs8e(Q^`2lgoPuV=w0P{23wWB6y6JO4JO9QLr-CdQifLj`EqG1z+s=eUOhni6;}^ zyy58es$bXRHf2HLvf7n!wO@ZqR3E>rK6&3mpszK@KP~1`YmUU-Gu+RN?LQ0SaL$v^ zLuS*I@vhDI>oembwL5ViVXfJQJ8Uq^ z*sinUUF3|%*1in^lQ(daPHn;}gv~PNB2o5=b(NvI#M7j8?%td?^+ivT&x9oIV^&<) zVttlU1}*zP%RYLe1=lK;*^xcw`_Z^|FJ@rCFI<05loPqPV2jcXG3kpX+z z)A@bUicFhagJ+i?FfK_XSskxGZMx*__?w-0D3!bRXP5sv@=k33$GsO?Tx^yy*mAF)O?8@-c?sFLYdM(adXcrw@}EOpx>Zu86m11a;kY94Wqf^rYOU$8%u7 zJ?!V?qZ$~({4|JGn|NA^cDwNOHSZMiT^HEnSev+y=^OU)`Q2JGF6QUPGxvQ+#r(%g zKaAhUN-|A`)59|ocpzCS3wBqzimaW6PoO5*t{Yu<*2fbf=fvO4G^n)oAQ!T-Fq<{a~G@hnX~bi`?fK&c)Bj7R;89yvH39A$M>_yiO4V0sb2#_q*>S} z{E>oQf6xRchd$|f*SmWs$^25AT#ZTpR<_z_{u(D+tZAExO)4$l&~#CmdxS!UBvv_C-*t zdGdPHjA;_vDrz3`)niOO^Oy*gsM&F1Z;s&_bxUtOgF7f2<;fySIGbmbEWI zJTe{469iD&-dHa0vI=YTW+iWX39ii4U*3poy5^qNX#P0wbRKY^RurY)eNwzhi zRc(PH@4U9gmPnJO!mziYBXCB>N>fUt#z;p;pv~~&jfl`?sAH`+)ZtZmc3Ly!47Udw zn}f}PChzjKQuVxRtLHDCRWnS(n=+d_LT#<&vZ|q@nca%VMu%w&+xb#Q5oFrwl6bx2 z8!Fk6S9@o)Q`?q?A_iXJNVT!EGL@3hJH~o%C%dvK5NwFF7-LW8Ya0UicX+MeoIqOu z>I*=lE$FaS0dG5$sq~NLrhA(W9n%&vyy3NY*Jdm9APNnisT%MPEB^CVw1r@6G^y-@ z%CyD=R!s9&@+Fp`BK>N`4CQMpq2a5&-ucQVo%)6b!hr_7)RM;K4TmBfjdsV58DGmm zfcnBAXuPGl=@aCeSBVDvL;O`kZF$Gf`}-9@{>Z8N%~B+ch#HBYbLHiu-Z3qq)he3R zgGCtoT2V(MrY~u6bK44OG`vSqQIU6;77Rt&nuclY7!^e)XZ(k}J~WWsi&Wa^FwC$n z6oL(*fOowvK5Ch zVf4`<&r|LpJ7=LdQA;TtrlXs*(QCBPA#HR-8{GoX0@MQ70vtquV}20t+I+y}p7Wr~ zU4Vn(0fiao;Z-5yhfm3~X^wqDx}E>G!l){%sd_g54PIML$tzW5wj-U7u)>x{H!5SM zrUX|ubgaPOAwJV@LQ`PXgqs2#p)+M7jnhGE1e1;40Eg2Ng7M-7xvN?NO)KDKFuXe= zoD?t;+B-rk@KWE)HDQTY@CwIID32cg+vOYEBNJK;ymEH}_%>QmwxJF$7H)2X`@`r8 zwRx?#1bfljpPx17^D`GLoK=HZt%@o6$FTw9tO>fo+X!bKf*W2Qz~~BKo+B&Y0{@N6 z^=9L=@kIImvGRPEurB4hw!?04Z2l*Yg8!HF#j0G@KT+NX+GYO){Xg55Q|X=hpuF-T z>oN6p{v|W!)y=4`n^#{m*0LPKSc~qoe`)(!jzt#c($H#5f?W9!*t5Rfr7%Y>Tb$+y zuO{}WNNl$0kbVd6rC#M%1kF7&#zfr>-Wv5o2yNTggfMm8f}rrmOvz|p~7JE3MD2CyS1UcR>v}`$;+vyxwX9| zz*P?L+JFHMzN)o+@|dySU;_pv=BEz447{VwJKbBnX7n1YiyGEg@#69p!sXepF&j2z z!*Fv}*`{o`yge(oISWFADz}W)Vxb@sSyF_vGMlmx+>)bUFbl27LV;jQLncL<*BG8A zVtmP~jV>--q@G%%on0SydjU_b){ z8W_;PfCdIMFra|}4Gd^tKm!9B7|_6g1_m@Rpn(Am3}|3L0|Ocu(7=EO1~f3BfdLH+ zXkb7C0~#36z<>q@G%%on0SydjU_b){8W_;PfCm0A)xbAjb-BNeV-t=p98nx>%D^)t z|Ce^?fY<{X7|_6J8sM8$PD^wq@KX+spG|*ixUMMktlbMqm-{swf5veV$FSR7?u&4Y z!!ZrV=Wu)x$4VSG;n;-Z9vt7tu@lD&I9|i?XB;PS4Es9D;~0ly8jjE5_#%##IBvqR z3CBG+zK>%kju&vehU3pTPU0B08Rc<|!!ZrV=Wu)x$4VSG;n;-Z9vt7tu@lD&I9|i? zXB;PS47&s6ag4(;4aetjd=bY=95>9lo9;KqD@hW;f-RB_-;r1PmVZ03Tx9(am1H8 z;;S6-I~?)<#}V&!#LtG3ZJwo$_)o3Jv^@BV=6T5XAYXNFf5x-$Pxd##7AlTeUcvjzoh>M_*1r-BQ@=yivRYS z9MKii54!LN11PF}ACYVsMo79>(#K2ua*5YS{L>QulEgnF@eYZPmUu$qS4jMRiI+%x zr^NBvcKm)V@re@em3W!N^YG!us5VLBpOW}wiI+>fT;kVBe5%B6lsFWQ-|Z5gF7bbr z_|+1BM&j2<{1u5;N&Fp&&ye^KIHjmIQ{sH@QdFy!c)7%9N&GsA*GOEK_-u)9koX*l ze@EhTCH{!S=Slo$62DgBXT$MDwd*8)rNkFWe1^npCH@78<0V!2bx0iF-oh^-@h?dH z0f}30-uO?6cSyP$jyS4CB>owRe^uhsCB9DLUzGSQ5??LxsKmb|@tDMaBJoa%za;Tn zC4N-mnyWrb|075Ih$DVJ_(m-fZK1?18%sLUe=2dyW)4f->i3H=8AUa#f6FCqF?nPx1q{ zpF9Wl6&HGIne#n~kHl<}J+2>-bZgB1LgJ%@{~sl8jbBczQOz2^&U!CGx>xlD)0-QPRx~!2;yoFy?R-&0 z5#Ib`Of$w5UsW=8dWQrR#l@w?=^s$Zl=QDcYs5P!guc|GFCAM^Tv1Xwr9x{7$;&e= zZWI48Zjm;=`UUT>u%#$-luOG{Tns5DriHNUI<4@ef1+@fw39OhOB}Ukq7}uN+8r^~ zXyJ95G*dE6GmO|2hd#4-h4oMe-t3|JqueT9KDJ`~#L_8~%PaU7O}D5{t8J=9K9$`u zdD5hblR#;yHr-<-#Y&=L@GL1Ux4JFODMM$QLJ66bP6Df7OQ=DaiRyRcl_6Ja3PtdW zHOqoBonFo?QHwJ_)43(3B%l$t1lFXRT!Ib^mv;mjTBeC5UR8Y6#L|l9)`k@dPb_6Z zrl3PCy9*~PxoqCf`t2T>GPXhlv}sNgRO!A1%C{t46>4s>+6X;Uwy9&aqM`}v^;mpw zOXK+P+ScWvmT-~&H;16S)^B|C#PZ4G@t(ZMnhDl>UQp^3hOmPcq)IJD3#)LZ$gAKc z1Op9t%S(WDI;6pC-zGHTopdU>wK?24!I_qR)eJlVgjha7q`{kI^aeu-6W38?>^iU*>7wm-n;Xu10K##N2muf3ILXmd7pvO+1Tqf4hX88F6A-|=5J9Fw} ztC00>p~khRWW)NI-x}gugH9Lfs*=fKdP_A@oKdQhsUjBhPZg}RR3uxfwTHsZe8Zog zBhi+ubdreH7FZ!~|I5xR7qOPoDf@#R4UPV$<`vCGnC1^1O)M?Gs=VS%>E%dAeg4L< zza6hm#7ipEWhPEWUON@)Uk)|2H#7!pc4cK!tnEz2CY2(u?Tp2s8>==p3!NE8+bsDe zQw|h5HGK+YsBqfonzWU`aFyX?()@la$saa4B8>)ZXd)-5@Wjb>7TSk2*iVB!YgJ6D zU=p0rIEHXGYr=|6Q-jek4JL+8gPQ#QMq_Pzz`tBrz~|5er;cSVjl#}0Lh_10A%b@y zQOVe=(w&fX@EGj}JlgrXYtX7M- zk?b6+;a2+^nwmP&Mc8nvSIh(vDa_ZADMgk@=TkvcaC2H=m|&#fM5eEBq_d^qBk9d; zA)8Mr+lh3Mx;50K`WyYncG?BnU_&>ii?E$`PAC{mr(4aG8d{v`Y$WKV3GEq?O0CY7 zP6=mB4OLs+D;XUv&8_JQtp1e>n4ZyascN-l5ou+VIvX7fXR4m4T0M~-pxp1rTShV3 zpq;GIUs6G%;Y2dI48F$iZ*q3gM60B&*)i|;&T6!ND;eb89REx{dz%ZtyASONzX=z;-AVzz;ktt>=2O8xRMYn9|SerJ5>8QnPw_6Dl#0@K8dt;Qb z$xe0dLLP3^arULd=p^QEZ@^nOInkBVONYx;YDaUZquE%i*1xhSfo-e0{K1B>K?`KL zDN+u@BWz$%DAWH$wX8xK7EVHFjS+htoo0mfLL*P>z(xGU6g7=bv8K^%I(t^uY%v-P zTWeEf4geR}hfLN@0i&T&r%1Buknt(2Io0m=P)l>8-8@SyJ4X~^=>tQWGc%{|<~F=| z8e@d&Q(CdsdMt+5J*qUdz+;IOk%o>YdMpep&W!fr4h10Fjp7VABrVmbMF0z?vr%vg z=Wkg8V4Bc4lkD2&}O@1F|_R$P|Mh zTnetOew=3nI##8%t`^A5X~Zj$ZT;DO*y@*ed`k1ujbQs){Ws#BnWuDJYnCq9dE&&g zM9XTkI46ilJEL@z-NE;ic8A&;m0w2@%S&Te+uS==XS_J_RX5=j4R6p6oXjt5 z2-4{e@KQ+C7|Tc{V>L`P&|x>;J{d`uIkk(GwPuQ*MqrDlqhRle}N4bC6- zJ4Z&krp>9Yp5`4h=i0?%z0UJpZ^_iDQ;R2-luejVr|-oJ({VCfQdCk@%6GO08p46G z1BD$I2>$=9Fx(T7AFtpRmlPG3ApGy1rWN5@h|#bdq0wQ5n1QVrhEAXZAIQKvgabu0 zX3iULG_25y^oB65;54mmLqRJvI<%q{ZIL3r^A_Jt$O3-kVIUN(2pLvnd6=)vM@oAO zQg|I&v!Zayh~gc|&Bzb&EF9eBZ$Rhujn)7@(}C|ipm>uN2u}#o(AtbocnD)m!_t(7 z7QJr2jW$E+@=#cH}0GBGh1F@ z`{z;-nnE59^5gyWF`%miu=5%6;Js?x77{w%cW=Tq`z^>|S=LD!+``a!XAD_F$NTiW zbH0wu)sM9N@eY@LkDd3|qqygAC(_7=KNjJ^yH>m>&p7YP7eWXh;3GM>rsIBr+d#*C1muTXRuYo#W*lr2Zqdqq zg-+aWnt-_dv*qhVf=%}b_BA{Lx^!bzl(caN-7ee@*@b&ME!OQo~!_>s&E@Zn{Fxg zS1d(AyDpO0@gF+q_%WSjprgL*pH24&5^R1t==4vZd(uJ2eI4zf%V$CLBR?LyaIi1f z4(_j6_dhi4A;f7f{E>!oJg-91RZYlqSA7rRu#ALWr1SS84o5W_>1JVI;WoJZ$dBrL z8HeajQeg}K3RmkGm^P2!A>WRZ^pPj)Bf4@+SnP=9}y2yEu`PE zuvIhti-oNk=tnHf+93n{g@vu&viIE#k{-3jzm;!khWmFcEP=-HY+<&-+UH|oI2Zi5 zpUA=(%=mE}TG$#89B&rp;I#G~Sr|8k@#FZhuu=%e34Vh_a~LnMOAE7CK%d6AA&MXE zo8chkv1!K^riZfZ)xskL(=IJc&y@KMl3h$rY+Iw1Hb}crBDP%(%JK}XpR-8jH%PlA z0}vYot8n(SOZ(3hHDvE)(zM}O9GL%U2M3$}n9?Wd$0OgR^pyjBao(}@kpq2j-f%ne zKM!n|&qetLU|YXA*vVx8mw&_3Kl5(^_Ca6NM2>d8wh>{KBmYj|We$vCtmQlEqrbBI zD@Qw5-I+!res+5_)&Fb{{gI7X|E~a>RDZHO>l>x$na}z%@)v0Q@SpvzeYU?hEB~A` z>YsidWcUr&KCmM4*OsqcwU7CO(1B6f4~8D~G2GFiHhuB748QY{e?7k4LcWyuGb~?{ zDL;;QVxF5Hha1+H@7wZO9+I0`)1fo}tz@4$Bh`yBZDzy{>~u99~LaKXR3+_Y25 z|5M;u4*U`@zh7+0d%pG>u%81Q!B?<>3;c%ttqZA7_hIz%K(=ApU6_w*nsl zrv91#9pK6zyWGD~{O<>zkN%?nBflqr5AVdfU*YG0H^M($q3}z<<&V4Eeue)CeDr57 zH^&9bzYlyI^{o($^%D%kg?+^nK~H(O2XooCU2g6NCH*MimtjxbLrOdm*xuiK4tC{M z0{{F6)_z{**8$&l(B+=0>Td+rfjJX0|0}>%%HGd`J*@&>^McDAQ~7aV+aI2T`DZim zvEO2kvC7{9TnKqNPf*_7z@vbPH~-+>4rz{^h*G@&|z*0sncxtnbgj z`+%t*;*-EH1Jh4aUmh%~P1MgkmcJZ0|4HnhR`yZ?d<67dS&(J{a2@q$3RttPD z?47z}`2g@n=<9Zc*8(3$dE4GM0dqdH?fJXF`%vD-KLobdbLZmB^e4csue;ofAP?*R zDX{*c%RN)^KLl(%ktzQUa3Sa?AfNPHZ2$aDmz#c!@|^`d3i)<_T?+gN^vRVc^CuwE ziTR*kwSNk58R%{K=K*iQc(m+kxb|h>S;*fcq41Luq{GY&=pg#5w<>$)Mg?y`h!!_>F zZ9@IigdcnpuovqiyZa*>?5x9!$ty0S# zRswH%#pPb0;JF7OC9#g6QMgD`X~f`0C>CNHyU`ZLmv}?A3;7& zzo1`Ds{y_nk%4p?)P_6Y$1gX7sZfcs}$sM#>M@x`<(~S19~#;3)j3t3bSF8LI;4`tJgM9rn*1@y!1ra6jf(xCz0}0ylyFUi1&? zUjjCOHzQ8m1KbJB_7Q&o9EHBD@s0D~^^iDt>jquOr_cFUx@+K>6o{9@jL0k3EOyP!;{Z0FQF` zvpDc^tmnR}_}>Nm2+CXjP}Ba6^p5fJBVhY{{Ty6T+y}f5^e>=1<$W1AIu-55kK^lA z;Fpna>*vqF?#Ep2VkOTzEG~0=w?8)*~z*1fK86Uk!Zkk6i98QhvA=1#WW8Pu~Q74*kI^0hH%n;6m{GreIC` zG4O4$7u%ox9JmwMwwFHvj{^N#Mc)Tp25j5o5L`mJ)6xGUfn7h#@EZ%<^r}7Ic(iih z_Lp4lSCqbLfM_yLrsEcAEST-j{!o&+|_pSBlXw$L|r7-1t441%D& zs1&z)XVooS)y-@Ha%(Ahl+$fA*po3u^o` zYv#LFX48H-(T&h+gYF7H&OKo4L;b5 znv}3Mu*9&C`g%E9g%36_j|7X#%QbxNG}O+=2C)Am9PlH~yFIwkQZ%^~Qnv*7Vd|pE z6SekM5b+z6{4k~5*TJ`8aq|{mQl#*KCJkTw^sj1UHb2a2Z3;l1zoTKbpL^9b?uo+p zWb12cXUvQQ{otLBW7~}uM0;CmIyyof)ws#p7HP*fETLDc8r)K9#s}Fu4F7W8rPi8o zBi6tcP67PFtUuVK)vReY>Sxw~d75zt_6cP`IIuzswKU-)v6e)P;~|K!B;v+cYjeno z%O@qZ#-ft)V(rENf)Z`jiU#ZzZfRJnaesz?mEmt_~JTPSdwE1kp-e;1WbEYsK-r4y%EVOg=pFZue=2c=~bHPLdI0SZFl z62&K$(@82G!PmqC(98133aeZ2JyXBxuvTnSM)!q{_Qv+LTDT#IEy+el8v!h{X%=qe zq1$k;&zMa}!(-p$gYu2KvJBpK!_I8%g9>QaGK0@IU(4Hf_%JE<&Md60j&y`W9rLjp zTns1@ZV3e1tE%SApEtAGUs_bGwcdy?Jv$R1ExOB@0$%d1fl$y{H$P7dp6aXAEKTl; zqvoIWg==Rlm{+a1&OXgjK@T;|hA=a*7m8%^z0i7o4_)JyFeWvu!naxZF*@cW@5Y{I3UY2D7!GTtZ#4Hl0f z;LfxUqgwN4MjdX@S-8;}bG2{?9Sv{{iqEyy7l183bgmj6nn2~wqF@i#3|m^l zokrE6Ry-XdMg}=%@Npx%F=#Qi(mIQRqPD{ty+Q1SY|H9Mt0f#^GqAy#qYNpQ43V}| z)QKE8xy5bETQJIIHHX{j9O158L#wjv40PfSph)bN`rEdRZ94F0PH~X}^*dA4Smj_5 z@n{fsU$HLwquNF!wk>IHLSG<_BtCs@xEUjb4P%;&hx7>duYvE*su&OVv_)Dq*fCso z?b@*PsmvCbmzwB!I5&y}P-zx-JbnjnClzC4&u;DrTSNQQK}svZp1kED>`>%9Dbpkq z5or!K^LxYGh1g+mp2ip8G4>D%JCzZ>vAKOUK6x&kuSN`&Q3roe&2c-IUK>{32LHm1 zS?Gn}X>AR*V?uGV#cmFHJcULWrvJo$XFm0(H?*yQ;xXGt#OcrSEtm&eF|bBJc0@Lu zX1oTHAba(~1wK6GMgkxi?U_-B6byakE$I_y`etctpb@f~NY!A_$oc~Fz2A=wB1%En zkQ-=gnh(FJ)-)J2&26j)R;xTrR-chS6cnbzA5b@E4RA})1=z%j0VY$PJi#?9 zQynN^a@C9KFjJvrdZ49UHE#h{J<=RH<80%i31Jncq7nH7n1DL5W9S#Qz~(eBXRna-azlr_B1N6h@VL zC~R;zI&0$$?!*|-O6F6Hv>N?nO>LGKO^vIYWX*uBey2>LAXtt~!{HY0m;w+^YZ%Kc zU$rwVY~XiVI4o%r8r%at3kq>b-p=_Ve3~cr2WSY`?>K+q%o+3j3un*9hvfZrGiJ`O z!TALInX_q_44SMD&O1|4f$|9Tb7sgoigj{Pn#NEa8tW`XKLJ;>ik=*H?aZkV@yO^ptWCBg>`D?g)G(5@>6*=l`rs z+usGVyT3$hiexPYP$%7ER^L;t8B5FFHY%!XZ)rBH{yKdi24&N)Q*^qkhUIj3=y9kO z-dxV=GNT*npBV}nv-oj&WMb90${z~*WyMGraf+dXA9OKqp>IB=LE*)1&CtZWSqkFh zXU1$9H%23JPhIMeqfn1lm@C$Eht+KF(p3gbTOoUTRdb8|4 F`k%T@u1Ej? diff --git a/board/MAI/bios_emulator/scitech/bin-linux/glibc/nasm b/board/MAI/bios_emulator/scitech/bin-linux/glibc/nasm deleted file mode 100755 index fbd335261cbac7c89678d8c6326b5bd02c0ce976..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 263498 zcmdSCe|%KcnLmE#N0I>sW`Lj(1B~)R5JaM&1QMP6n1Dj+Kuo|N5v)ST6cyoK)JnqO zO=@ng)6MSI)^2M{mbPnKKP|gkHU5GG*bFM&4QMM0ZPQBIJ6_sGjbR9p`Mlrf-bp5) z+kJgL-_IZ4z|6hp*K?lpoaa2}InQ~{nH`~(6%L0(O8+?}m&8!>lWxyKJOheLBrTKz zQnoZ(nkMDrDM?IQ7)2g@I`Ga<7Cvr#SfY;~r13Km@BA>0u!m|xn#A&oQ{so^CBKy} z;<9o)9r)xQlO&_TA?jti6WQifx}o`PA!sjAQrrG$Z_DcpgLe zr*{5j2pb4z+v$Hrd=lYw|E@;72XZcr?>>a{5Pr`t&vLU7F0;d>c=l$r|F;M)Mmqa} z_^m|#-ct$^|n>sa?j>RrOjLJdqCbOZI$nRP?4o=TkY_=b@#}R zZr-r&i_(`i$QvHm28bviKe%ZfvTxY(z}=gqjY!!l-M`^}0Y>5b-J3Q&c#pJY!~G9# z+aPV+xJlU>K|u?W{GhUV^M)AtO~ zW8KCrci+DO^=*7m+PHPYhA*?w1NYp&*?I!^EgP%~w{E@X?gutX8xg)&0tR<)lJC2J z15w+$L6$bk8#Zl{L=4-^@^+;g@7eU=)(vd?hAms9P50in4frVXJ<`U9x7;UhkTyJW zABsP?dBX$Jx|?oUCzAMr0{1{l>m_{$KxdeFg;1>x68{VZKv_Q&#hD z{C)S0<*afPOvpID2s@<{HdD?9-)93k%GWFiSjwd=2zkn*EHFRiLKXmWd}LuVjGoBx z<`Z(|>wIEDeVR{9KHuRJ6T>b(F~NMF&oPh#d}7jkj!$5^ zhfhpMKj#yZXFH!j{8c_NL3Z$o$@L(gn6wV@iHYklpBGC~H=mfG-{upO?lC?wxu4(@ zlT{C&n5a(jiHX?Y6O-2|J_BecpO-<$;q!9H6+Wk9j^UF77j(#(iTR&TOfVikF_C-u zoDKT&3Bi`jCj?&}pYt$J@`(v5z~|MF0enJ1sMh{a6*d4@x?|^o{i|J)uKpZ>rViPe z>W*!bjHMv1QTm2M(rX7_KOm(RJpxQpGq>ZLrBXB5BN4tPdQ$kC$)1TYEzvE)?4by| zKG7kuCxG{fK!DG?Rn?=ZZW;msn<9*qPUUN6Gz z*~oH+!y?Qcj)WNwiZFXRvXuOb&~5GaM9Qa$4jV!wW>192eC{`^k|J$N;oogvpr^s>z9N5hjO5{0w)9FgZ0s6)CYtgvqgy z0K>aPn4BA#&2Xy-lY=7*7>d9pI z*42@6%$bpAq3EruiEN6wJ;pvXsIRpZV?aISQHu{@O&}>H<|Oca+d%|kVYfDkFS?ZK z7BT8#Njce0WeOu?ta`97vL56xeubLiSuBrwrPmK={T9sE4_MFkJgdY6^9^>uowNUyR%sobLiS-|9vi=kRKdLbYLII$rf!W2mk>*VI($ z3QNYb9vSEH01qjiCEIVr^x#j?WGc=^3W9X^ok&7-oyT|<@?rPA2*$HE;ro%}Ie6P_ zmu#aX-o0F84j8|ijpEIaOGK!~_#q^zdeE;HiyGz0YO$!$*Z5~jjdJ8mypK21vzufL z=7MZqfxr5MLlgx;Rswix5i=M+cz^&0MO5TezdId2=LgIkK#~BI+U$<}pgP+VtL>;V z5`sQ`RmR~ak*STSt4W8i@fFa(_xMeiCe)UnJ$ybfqF=m6b2JFx8EQ$FtrB)+9BNCWNZUE5OTm3O#Fj(QeV! zOCh+CTU4wE-Kp-T4&{$_$U{KM)S{ChGkW+i3MMuHW0Z}DUM1*){(_W1%Em~(8U-Tz zQB9TcYh>R|8~`3brvZ(sNDq?gCK$z-RuFBD9>y}Bbt~FVpz*A7ypdZ!k0Qt$B0y@SeA%ByQqN_)hC+-)p}c4W1Y9AV?!8M1yr7uBW~F}2G0CEAQ~RmMTV zhk;?TY6qH*`%vt6J3lq5HYdl4gSp4j3q$ZAB z5pqJ}4Fp<8FoTHCWQb&BB3dD$jZy%%yC#4pVK9S304Lo&--Q-{ij9A`4>*$fEpF^R z?Y3CbYOWs4BZB}1Fqe@H4Ti(O!jH7>v&O@s0J%4~IMr?Z9`MXrX{?R8f`oqX&N;MC z_KO6(8WXGpd&tUJ##2y7keXUV$zc2y%7q9~Fc_a=+@oS+mF|#?FcunV6mkkWOb>XY zo&6cx@bn#bt$Y0d!j|0At37(it5^EtOqQZwaZ2(`b-&ZM*Qt-CO4nar;t0rNwf<5> ziGcEn)@{yhg`Dt57fbS(xG*A_mjEUx=-XTB2uA`Sa$SLOC-kX;4qI+|A^+l`K~{rW zn~uuaEzZUc1^6Y7W84>ACNzeDODr@PPAT4$;xWd7<+KAF3deno_aPlJyd~_24m_w_ zgz*5OfsQxUgW`!5NCo`pz((bI(6`F??sg1>{n{k503jSzd;ne*S&v30&H#Z{z0|8q zTB$$bOP3AHSz4K%UGA1I^fl zW|)gwiz<9gVWbkME$h!b20Dpmqit+C09=JEsV#2EFm~}Z#-mXE6M2Y?XOY82e~dy9 z^zVxV)$*i&ccw+OFT8?TNl}0uhp&)&2xR;nWLB1XByIk9-Y5 zm)sxFXm5xxdF@$NWQ&64D2U?hdCay3Vkif6Ny>}qA=Ds=K;zDt)CbvXf-kz zeza8&4aPPYLh4w0RKAb{eNogJ4<-3v_wi}uLSATHL%}QtLxWv{*4oGB720p-oYq50 zwWGf<-f)R}e=>^N5D~61#)_h`d<pcvZ6zP&Dek`+^G$=otT^_L@{e1e8T??k102GT8Y0n&MmDM>92 z^=_N2-rpxEQ`xsll zLL-)e1sfk;xl+y|*h%%!PPR!NY^xMz+Ym3uEb@K1@?! zI^x2{HntA39lf(uXchtSz6{Z5ajMeeYovjWydQV#Ik7cvtvVT99P~9kiM}IP2^yE7 z0xX#?8MzF#=sCf#5%}1eH3CijR1f+h(^>!RAF=+vx|FdCZ+gAw7Ays>F~^bj`)Z6A zK~akds|4U0<40+PmERyol~E`FfK8D*hIg&rqt_=62JkyVKrBJ@vI=Sq4O~7P+z7b zRSzzBCCtLbq6TW(mI zV@M9`Pj%z5+GvK|%O<+7@tthstw^cK9N!Z<-l3XAzL*W?85>*R}y=3^?kQ65(m#AM)mp<8>31zH>!&MS(R$jh{|t-ieu z-;23r{atS5DpBYP6q=4g(~5%frTtwV<)We)fHECW8syPdmF$8N0mfalM0r(xjbJ5? z70e4(v(~~!nD|F@7VwW2E>XsGIi%P_4l@hk0*)Aq3dVPC7sHi0Mg+M*9l?M8_xo6DeB%|F8NWXrceMAL#pl{^#_;NK%i!6S=wd)2csnK6gzV z!CkkuxWHXs0HfRtMyas5>yQ>B8<^L%f}vKCq2?mj|CF7qdByA7+pV1;4+rFz(rlGW zwu)L!avS4 zd|-e7FbjV|7WLRHia854>M?>_Rb{lmnoPm|8Y_|Hiv*Kf*ldL%I`LCjw}l+d;8VtJ+FbLcy_5kw&IRb)k95Q4N`a99B$Y(liL6;=U@$#yUH<#^&vCr};#z?HCq2xADi zKPKYCh&j9uW~0~t(IFr4hw?*4Ck-1Dm}Qs*6MvtE-PPE zfdwP_{1;#)+q~HqiFBanjbD+7>rQQG7v#Rc!k&)Ysf7vC`M%1|{^TSQ8f6<2X7_ z0=a}(BSn|YSNu?j<}0INrGWBw9dOl~STRjoMg2|V@fwh?RbN|(my~j)-b6&y9%sgQ z#CYMPAT}1BpNC|#j_pl4m92Ucw-aV^1HPDF%H8T~%#l*ora|7)-&BH#fLx)zcBe=x zR$seUye!P9gmthMZg=QStP6}N1);S)d@DOAkoXE3YSa0gMg9V8b%892^+-XVTE<{3 z#5pJFLP=R=X*0%OVbh}$0wWVw++g580=nKr8p3=B#e~79NSMyw!_0bVV z_$?&t7^5ajDp%xg!47nsvWgcq9=Avf#4FUfDIZ_GBcTVKWm z4r*AYGd<{EZ5!GA>baC$;&`4qo2}=`K1+EMa?6}4bX)x?W>`H!`>Tg`3i_sv>Q%;* zbs_?_=rN9tRmMe@XiO`RmYp<1f&5P>XaE8H+Jx#Tlt!yAZ4y<_3_E8NK~k6b*H2QZ z3R(R2z-xV#p5{*ntAOBS6=Z=>UfE7wD`b_3?lxF4X8pAdHN4_)3%V zGgWmb7vLjRbtvd*(!ydtQa9gfNjNh{>;D|uCf>o^c!6GS_gpX1hV=3(%5PgQ=f*Si z^5*}!UM}X!z}=XWUB)vxR)@nrf1W?Bswrd&W#RCmwnNJ5i6z^ zSF@w6q=i7Cm40MffdE(jG3cMxc1N>?0dTG<>tktqrWSh{6qQUP5$rIGh6Z9Aih5B> zFY#BQv8%9~C&qqa85kx##_OE6P9WB_r4X&dI>9uNFB!QRwUYk@>-iJ35DGoxUT%F{ zpc4pL7p`*}ZL3*LppC)>mbTk;sZcDWm0RMW=h!c?=Q$&rK7A6i2z{W?sVo)+uO)9&WZk@6fZl5 z)QUHeS8t+PL49q$uZd%ns)Vm;k9dPRAqMNPIx#1$P6R$25ypa-DK)S(7Mr8P%i*-5kU8-gm&3cnAtotK zDI8Ky-(vx=OeC`3QY^$zGrOF?= zN?@*lx*r;BaqfGTqcID6VcfZbc{c#_Zmm43Xq58j=#pBj8=aCi(Y&S=Pi~iG?x2my z+&`O$+_DF7SZV;dZG-d0zy)>~eNqqb(%p|YJ4#@OR!+eH_Yzeit!waE>Ej>D6Zh=_ zCYe!+SM2X4-e<0Umk?kzCKG7SWF)l0e;t>jdg6Yqhs5u~mUg;Ad>E4`OpY88#{=L%C3} z+c6mFMFFdy2bA*+3?zVA~oa?>@OK>>53de$YjAMI*g_n_J*j|mnRD-4!76P*JEdqBW9w)*+8;xK};v#Qw}#mwdCi)^a#u zqPf!EU>DZmu<=s?#nwLCY}ALe&lv;+~R@|?5Tkj>xfKfM<1?Zbcgtbk9$#&cLRT5=0jzKB3PtJ!X$HYJKT zR3|L;HO8YrZufQ(#f^N3Oq#cWL*0Zn=1g_#p}gIVc(V}}`yBQ@6dfZ`tscTo!q-6} z>XCiMU8v9{DhwM-EKI%;!UG8hpj={RD z$U3yV#<+K=qIy)KogT62RgwxD|HA6Twn>_!BO6dMR*@Ap-Vucts7aS{ElT5mm2oNU zSjLBfB?5>6>l@P$hrzy^Jp)mnI1cd)I*I&ok&`^%M$*@CMd3|#YrW}Bg0v47VF@}J z0aR=A1$G>F??SO*UxnN%QK`px?;Y@>wa1~1Cl^Gmu4ZAD ztHVb9F^p>4?`O5~cL2pH3T`Q%4=Rl(Py!swx$9Q|WBWDu*HmGzY-G0q(^bYb#4`@? zO)1L+Hv&(@1EZ=nh6zwwlAH<0j7*v4ja5()3LA-E4L4YMhC-=i!E5Al>rbC^zIzp&C1$0)>KJk(1W2Zt8&9$u<} zxHD5-h964_8gB2YMhmY}JS8Z_rf6@bS4dh{i=#R8*M4`6N69Lhq4-Za&b$Eqv#P>`PM34%n_VI)J~_l28lD2(RNIUxvZruRkR%0BFb1ha)o&f zXjZfekq?QooY7X8Q{cN%inuR|IL_58%u(123Jt;rAQis5H3Bu|$T^|AYTX4#Pxou_ z^sH1rI9ka;fb%IfTE}B$aX;#a4qV-EO{}!5D0|!7=)n4hF=%@%{3GG3gLR4>e%%~} zydtT4Y4zatv3j*P?j$AAA2%1CdpJk&F0D>(M+JQreFuF%>xwOOmWYbnh3{_phFaez z$$5}J7$o7yE)2*>5b8pkH70#OQ+m%E_ZGWUdv(QM&=DuzlH*8Wcl|W&Ev^4Y2&Lrg zcs8rk_QS|@lkWwGqkDz&hxB|C&-y-wJBwL!OdEr-uv44Fm-M{Dxuup|iJ?}b9h(W2 z05a^hw>j#QHJxWYz88*H88;!EIbPILpIz=UyPS3mdW8*ZtcZg=B>c{#-;VBo%dW!A zga0D}BjF3ZwVsWS-YEH+z6!L!tlC*xlfk1c&SqC>83M{D+~e;rJi9G>MRe(W1$*e& zY#9yZGn?x^Wq|co8IhyuNo5ho5?YH1um_!Bj%r1YNZ?+~g?>F`EeAPEjEdZixHZOi zfttycCZK#VO@`s|CGf2EU~JBVB#L-~So=RXfWgugYw&2t24CWlfscP;^G>=B-2-f`x2P`H)DK` zkd5$lfuAqh3F){Fb(mMR#x{Ejj)RZ&YzS#9J6oJ4Tt_&YsbQ`x__=uWLn0!<8{^(+{S$xmT|-c6Ya~p*o{AeoIBo)RX~9sa;yMeLg$!AF)0|bslWbKc1@IB@nQFUP9jbmZ6E{|413w&75wPA>RH@$5V&1wd~xXMK+iojBZ3_UsJf z@+80>h?hadg8VLnkro4ft9KvEX~}P$KBvKdM=QfriJtxho@82CAkKA)q}_ooO>;|{ zzLqYDP6)K>Q&A?hEnwV;D)3rkT*tcLfkAJM-;ErP&=b%rWo|v33v=_F?xkhkda4`1 zFv?2zBMqcR1`o2h!g<=NJcj&Qm0K_KYo$!HCmp;5MLSskR=;uM5P)!iWtQh^Z@9t% z*9xzO*KVP$r17`urq^Szda>qgO8LIVy-lR+HEz8$SHImq=Ro1v2B&rwb7-MjKPbtU zxJn^^2C)zxgo1Mz{pqM3G$){polpmvw+P(I-oqGOn>**XO{s>vtoH4Kj~3cj!S+>* zXdgm;j7hyhw67xFKD-RKZ=2s(Hv}LIGy;h#j5^ev?i%nt<^(P1i3j1LHRO9Qw1ri4 z1I^P*^7Y$u=N!3 z3gfqiz-H=qw#aT+G-%UItsPkfoE&wN4a z&!B~RO4L{D)$4OPdSH@({i2kbW!BQQdG%0Ju@-@6H8-8vVMyKLF>_k=>%i74^@?0q zMPA{7`d;nW+={%Wlzc65y$j^CxWZK-c)`N10}^n~Z@~>ZHXP_FEk07|&Vm>M^jm4{qs$b&jy{G~l6ukf%8E zU|Jc#K|Ler&bcHtb|JRZ^-270n}@H|!d7Ey-;gd3?;$2h4Zc<*&e_8X?)WHuPQ>`7 zm{YJ|VQJ(2k6F~3N77@rmUza>fK~{pVgbO>S+mCIJS@=caxazI7NB@x7AxC+Sr&KL zcQXbp=^> z`I_k2AWYw9XZV`VL0|RlEujlh1wB55cDzpZLtF8}HN*qgkfv`SPdvm`t|Tg^AJeE* z=wwj%Ip_ktR2EUv7tt_hX4|23qkJzGRcJ>}$Eijr?+YiTU!#I|QNb^Zf-+N}5h}04 zPw7A4r_>2QrPn~wIq$-G<2JA@#2ln*82#f{>rX=O;&MTtGUu3@9OL`D9)z_cvD!ZE zH(b9=f=)bai*uC;W1I<%j2cuZ5`e#Mjq#lv=x&u>t%SSUO&!}W4&pWLp#I#>uf*TO zECyPlOynTKk>_$)Yy*qcdNoYfqL@GKarXn$0|~urcWV%!`9Os+v3m`iE;Un7?1L>8=hK`=DQ|^}QGlJi6whj^EC&1ntSNHG@1Au=Imtvw0Gv zonMLXh_vXy74oR)z~#QC$A?K_5fuY*xwpk(ju)+ot+i>7lMPthxEFUTe-a7W{yA@; z2Cc?}vnI;Kc=mAhg;pCZ5`pVtp;O`2tBhT6a}^DCV+}imkJrX$DR`pNYaMohocjbB zK!@nS4a#(M`whyJ;cjPRM-u?Q5^v(GHCk9C@)c#~BYTWuK7J*3TluaQ`L52)N2|mb z=Hpj_o)&;NQ{5@Ys&we8&NFsJ$cVWjn?Z9={UQPLa=|--vu{2QSKK=T}0v^377FfzGp(ONQyp zcJTCRJHO10(Zah#p1U&hurDSs55LUPXyJC{YQWj9%o&D5{Kqp7zs#v(j1GxZa~uo^ zWDBP?hDNMcpl_KjwS#L)d4c+fTarK0am+`ap$;@ClQ~X0JR)MENc?c;zz(?c?BKc( zb}-at+aNOG%*cR~M>v;Sa9D@ON;7R+nyb}5Bb8ZxtsZs*g%5R4)9dmI^-O(3P(9P2 zjBh0_jJw{-(5s%=p-|Vi@ekPL)B(rC z<0Etc;;au(tbJd;}ZG@2YXCUx4AYJIl$8`G=xH+Ag5g46VC zztwu@BmrSZr>HAK$3#JWQV}HdZhmRq>H0-{kn#K)j&EadNPkQ3gLo|%Am7D0CNY^N zZmjDXJ8XpHMO0+3HNKP(5pAps*>I==OXNC4a($z@1aK|89ePj7%mY2f>62Jr;SphH z&DOf-9MUcl*r)Nd*CuEMPm5^r5qiW!Jjv6Nr=G)3`{Fwnq+lmLd%1jf^z0S#o&V0g z-@41u&eQ_qCm^)YCuHZpUqMy40;iIe7(=QssEll}Wl)fNEg~b6RrKq~)jX~F&g&gr z<=10Z6w86d8T7UBQ#|MGX55DQ`mjF8IMw4G6E?d3G+ZaNZ#7*RyE*JQTV*_im|-;< z{D8IUFfCR>pN@sPwa}qg;F~95lcd#J;j0~kD<17DIIb&)P^KUit8!@72Vwn&OUP|n z=y2!zPVGqN@0{F+^+F+j#P_r6!{jr+!#&ma;!#KLIJMIaJ!_eo%4#^S*B(^QW;MJh zYSAkXshzX+RcxI+10qgvlB)nBStA3{a{g!(pW?%Qw-EUV$K7}^EE z1sI9rVS4#@2OS;SyL#?-J3sKLzlZ4*$5b|IRA7 zhq}>TXrA%VA-fwUuzyj=X)*r$i z0z7<{q$;~{o(e!HAq)SqH9NY$yZNFDK$(^bbz5gnueum#ehZx}?DBo}2?U}IIJMww{X(qzWZ|#2J;I>;kx1Y6 z<=7WeSO@uDjK|zzH94wb^ggx+`+pc`sb+_E=q8rxe)zqOSdEYKy%_q{#!)W2)g*>I z1s(S*hceDW7pR%z(8i5N?*A3#RI2ju(%OT*$LYJGS9d$A4>ujHpB1Y;rgfh_2Kz1A zbNDa{v68p8e7Kk6Sp)g*0}L`m!1{9IZ#W>&HkFAH= zV|u9jS%)l+k77z(ZH&c=+0p9=9mcRlw^mgdX9r=!S-AN~eK(^}i*g9Y3LR|hk8OBX zFpjWia?M+i!WIQ8koLlqE6s(nM*jmb9CAxw->US!l^hkvO}DyjZz#N7-=U!@%=+oMka${0jP@YP*ql%Pvs`RWh#1*|iJ z4xIaEKZSaCZs_w#IB65=?dWlj4)rxJ%hp4^@N)9KSlu_OdrasQwi23`<+OzQo0qva zVnKAed0AFVDA~Ns$6xh9; z)Ost~w4Y7_$vTI~>P1!~b!v9MJ z8*JvnKJNE0{z!Ufm2pzMg1J6{TZib5DkF+Gi@A2BnJWi9p;!BxOPzwhaxDHDl>~c< zXmC+~vtX&y&83dSG@t>w{Wv9|n!L#O#2@&wUm0eiuFiAVjv*7hHHS+>%!Oc>Yzr}~ zPcW3K`&JvJ7KVa}j@wMM;b&=>Jz9# z=j%*)G;Feeqp=Klq+j8<;st-&oJEKZpxKVZ!DZb_rkc;dhSMy*nt$55D)LL zdmJ+4Q;SQW$kF4k4ibcXV-Gel(0ZF;$gb`kRedTwtST@9`Ra*~WMUER`cTOw6alYk*2Wwrln3JT>W7ysKBiuKjlyJMb-3lQ1xe z2;L83UZy5T^Bn$QI1;7Qa;1)+@1dy^0erk01de#uuv|Bm!5!V;NJri*r@zQ}KOHe1p#i+l*NrPn~_t)7AS0pfLBum@8$H#g=FL)_Vgni_%e>*fHMXc zpiO7qlc*azc2r|hiIaH#fuBX|6>7 zl*(6_<#;ZaujlETapv{5V~V*L_2HeOM#v((b6PP2Ry-A9G23JLTn#I;J@w1M2+<(g9dwdma$7G#7KSy@G`qa%@b$3(0uaOPH z2A{ZRso4VVz!|9;zdDeTg|GP-4ch$mEfu*q?TXRuq@%mA!M`)!wvoS4B3WVhiF_ z8{%DF$8Wh)<`ajx)cR9W!?o;|RP zGbwn8L+?opLYF|BtiCUP5wLtsK6E3tGtR;9RR0G->{4%G=wyRSY}iBFJ-I5i1(ykt zYvcbWxb_tWuxsDt&Le#y4+8%x<7FgbUtVxEeME65OB4x-*Qsw}oi$j8qZE3jvC0Vk ztIhm^1F9k&g7A6>cXcG*L~i2u4}wjqd*Y!JKoiyUiK0z=SjkC23nGi!bP1zqGWVk^ zPt2)2DS~5gW+0;x7FjMNlsio*_5L349Q9-33C24S7G4G4Ky|uu61A99#afZwi%Vms zqW$2fHOBprX52ExW_&}19x}ojq!0$cwybtO!gUUj+4%Hlz}t5AYeyY|o)M{q9H&?3 zr;f%$J*b`S5xA(bP{!>J1)i4A3kHz-5-H&lbbp~M%!4Xp+JdVW*>8`#HNigS2_LdQZsV>rU9{$(tWh-LC#U(Zpfr74%Xz+XbnVIs!hNWw3RmE<))q znb+YxATJQ_SBm%>R~gU*4cC=v=W;VlC> zD$tutAIkMTIYaa{=$k~2W1wL!?mO{^A?>ldbpUj9)xRx7N5eIgpgT#<<%I|Shcck{ zFfMBFHT??&0EyRbu@5)sGg)J9eV>*zSGP8Gz(Jr(J&@17Z_4Jv>YT%NDjnul^9uEx zlha%>@{ASB&NQ)RXH*;2I%PAu>X^tu1kc zy<^E$_zV0bEmSeakkJ;Z)p@C-2_83LTj+RDhJ36Xua7)O832Y7cu|Z_n7cMt2+&a! zpaMU$$Q`?nA%f*c|0SQ!4y1jvz)D_0*WJuj4PCPd_RN# zr8!m=+^IBLhU*^~p#88dXUJxfS8yC&gucdY=#3U^uI^u6QT#jL;d{csHyGvMli8kD z#5=ki2h6uYAH2uPgU?~HNPaB$&jv+uc)0Oub0P7X4gWmmX$?p>o|~j9r&P`zNVGPT$ZT7H{tli z!SAxfbqrUOCFb+VA^b=%CH%l60kohF%OJK2@S6k3A%;@iXXtQ_^)k0%u z9@ntqlxVd0jgD>BjZB%o9neohdDsT^H9m)PHPBUCuxEZ?d8t;NXZH_hPV|raAJ9MG zFUn6kxayU8kc(8jPQ#=Nc0d77Qi9A=lb6Vs?LeQ6gT5M6lb6ZU)Z_wr zmbq}xxae88GHZ_y{@{D2@_q82X^;zhviUx4PY%}1doJR;bI--ip;P8XmMmM}Ip90Tb(MIwy!V@hVEuLv6&%k9dlv{YK zD<}(Y-*q0sgkL_Ud~PV8Om0MrhdJxud0AUR1{g+onh^figPS3!*+tMlRyu=AD?RdD zz1+#ZV*6`zQ}X2Ht76{-L3^+)!ig(ERdAVgu8=JoT|T!u-)bBO@Of1ErML?!0Kz1e zP!WfZ(p#~{)#-VQsC#B>Z~YH=BKGw=L@A4*R!$b!uCh66FECsnSSgFI0lW8P=kirp z)x_M_%t>Z2M9@OYVm0#Lbr%0|kA&QM>*SGb%H$|9!cu>xjuUX4PHez35xh=XuC-|i z05*14*w~4FPZP5HJVL@wE;!_TI*w$Jm{lWg+)I1}z7ul-b#qpI!F2AmR3NyZHU0-O zL%eq~G$HMJbsz6y=)3*R;{fvvDMNEEmj( z1siZmKQj-lAmui_%ko>Ii;uvit~$@@1cP!49tn}TFXBA)@yK{Fn>=*NTE`@gK~$5K z!xa6ztsGYxU<4$7j(8Hv(o2wGZTVa8)vIG%y#;ZbjkPkG28cp?hE2Z= zdW-ML4anJeeEVgP2G|`PQdTN+W91GgD_aC0-en?EDKn~bQ~%Zhs1QQ_RYK1(T~^VB z!OlOrW98SN+z-J%V5H{SlhAX-=pLcxK#y$+4T2)E(4U3R7%bGEHi!Nk3;jhq5UV~l z2bLVsuT@yA(G0NB6pV=z1h50i7yG{UFYKzMQ@$5=M|oZ1X#~MQ8d)O}=xKNh^Z{Prrujy8}$EUrGgsqVlE0~>@tI6_*OQEeDeoEYDER4ah z8;Y$Jv#3?hv%& z-isozePX2usu$weGcF4Q<9YPu5Z2zMH)CMzL`=c)!Z+)$fTsYCnrQ!t6m|cMR^9!* z)7{gZ{RdsXCYl-4{R_$pKi+PL%r(6F9F{UcbFW@rFynMLIC6UV5|1*j<<=!097LP7 zsAN#@*w*ZcRo<*X9=&A>NQ&Us1X8{NMj_XobjJX+#LLQKwmiH}ls;0oUp zNpRUx_unfYiqHoLjo7zn3FUV5xV#<@#^x&-(PTQzqonPMp z!~7uMcjRmJN%4}a)t?eCd9c}I!zk+|@K{PcbE$lbdS;4zvwCK#98%8&WcbeI%S+WW z)8*^bGndN+>X~WsJaynw`3iMlihQ{`FcsI84Fq5~8OVp>1b4QKQwJ``iez9K<{HX8 zv}+y#UqQf^6YvxQ&LiN71U!y_M**;}>EF>ndMaR5#R5qdNU{L96{Z;$NU}hZ1(GQ6 zI0~R0>JGQx*Ql`cS%)&a@Q^&4V5YJ1$+TT(!&Sj4k14D?rHsa_Lvd?wXq|;`DA_Nw z;boXbaQ7z4PGA-*caHXkMU}HoT&V^`M}foogR|XO3FCHv(Qv|m@!;$z#lzAr?Tr-# z;6+ZwuN`@LI{FIlzQ*5x3b8WYwT8vTSy9@9(m-uoLfmpdWBGqE_W*Kt;RV-bpq;)a zzK@cSb3NY>at>qkDr=0+vc@QEO|KvaZB4HT**32A74ErXZh8d_0C*{!T1LO$GMl|~ zDbGB?rc)1g^I^vd=k@wKUBaiWpuf|h!0~f1tyDfdS!Bx<*~ayEI+anDn57>iInU-x z)PRn_4^Z3%L~I64RI|bG5o9Z7_@4L;@}m`-zlpUqh8+q^=4$e=b?Dfvu-=8BSYo}4 zR?WBG11y7@3tYiQq#rM@` zMf2wS8owuA#`_w-AzqLzhL=|?d6kkwoxk(M+@p(g#^W*%^iy#*U#>7Wwiaj4$J?Z0 z{x+1d2EA0J^;`XPv)xan_V~fMTeSY_9cX&C95CmSF5@xE;kq~N6~QHW;5jj-O!TqM zCt|GeMq-|~+d*AR^fU)qz8F0hiP7U%&t}VGIMSH!TFi_8XJZXLoYAeGW9U}wN(Noo zIH9Lmlb5i0312Xrl5?Ey{*e?6Kv$qzUO<&@?tg>w3%{v1?6xBTLqH0;rx^$)q8iMzJx@7<~knTIO<}ES;uIV4Uo2^UTKHb7;`M2VfV3fnGm2!Y%hv*ewTnY@9xYIQZr0 z!lgnuH;&o2@i@e_p!6<1s0#X!quE#?)5aNB9&KWNfhG ztN~35p0Jj5m0@4X^>sVJ*Z3Xs@PRztr6xb+$UUdLrr*I+;xDN6Uf3t2NRI(N{`N&t ziSAyiEOz8}$An2At_HDsX!GqB zO2va%Hi9RRHHf_t@us?$=D`c>7=57AoBXy76=(aB&~qfr{#b+H<{po6CoF(CeDpdl zY%B3Qa1wPq+y!xBbQKH?e$8*q6~ebLef}>E1M4aqMjl{5$?^9G{cd@*Rm9?fjNd)s z>EiksX&%TGr}*7PL1j|(G4!*~ybU%_9PiI&P+3XXZ~)qiJ?-=!27M;5-wOtShsQf< zKt2H|AAm-S`2;W^;2Lsq#6Yj`>?Zf5i7@hvVm+5`b&eY2cGhtKN0`y&&pLPq5^fIo zJ*&Z132yvLOo5Pu4yL~0(5m1GnvdV=@Mhsawmymc3@3G8OE%8nT_$kg8HeZ%^C4+5 zFUw=~G7ATjzV^tPE3&fP1t7o>fiLcL3YmpG#kE+dl=q zZS^`p(R8E62`c5GQKR^K8lp`@l$T%RAQ0=N-KlGr&U&gR3J^fhYDi zZxZ&OI>%}w0f#ZMpD#KF0>mND+i@jmJS$%2r`my2%EGQdVTZGgU_Y(QYeMHL6Qf;_ zd+5xBC0qAVkQE$f9kzUV^F`F+o+jj&yaCZ+gR4i~Jxx<7kdS~qCS12XtpVO7eG%@h z8s9*n-ENGT-4ebqrsu^;QYju3w^hW0u>B*H#bHJ4;#rg@K#=#OSkqCO8NiD}{9t8c z(Si5LN>D@Uhv3!zevzS=!!zt&xNsD8l^br-*Y zHtlaC%9`Io-SWANms;d47338e^sqeANQkVH#;gy z_-<7hE5YSjS}7bw(;XmWJ|-`Sjopg{t%~qH)TTSdMmq0AvX0@$qaC8rV7B6g$Y}h9 zM?=JkWC+U03`EsQ##8&jAOXA&`HRLMr?SVtcxiwS!EuT&UYbYEE^z`{9B5sP%?U}a zE#`4FxuTdnBi~re)4|HcZLXgA#hEII^f0`M&Rj=NZ-!rNl?}Fw;~VxakTtaKu?tlk!Q2n z{Ep#H)5nsGHfSK=y^ zwt0BfO7eFOh)egiqNyK>00C+BxtTpJR6pZ08e7^hza1Q+mbkMV)h|b!Qw| z3iZ-fRR$|b33s4x!Y@|Bi)9kMSir!`(6;yVZz~hfWfJ9jAOj7l*zx z7`t$<-Ra25J^)I^Ho$+j08X|JipR6aCRY*vEKvd8hU@n=on(rIE=9&pl7m&#*C$yD z`&*fp%{IRPyg^oF3?e9b&0@?$$>kzU7a#K~&ZmPfm*O2Ap=7oa-6o|J(s zngX>-?Z}6x+fKO1fzq|7v}v)je9(*Ok9l1UGtm>)m`!c<3We(=+;&N9kL6jur*tRM|B=iOwK^MzXdPIiV!%q@ z!S2z`ST}+1aj4hVcn9G=;&xJ}8jMUqa^y^Jy68Y%#8Pl z^_z$vn;Gv188~{)TZdy;E_OJ~^5L*|aRBEmGs8i1=7@0AoCH3`<|2D0tx#BlHmwc3 z1S4^pnpo^iX@h+vUKjoRee+V6qn}6sIR4T!fyXp25!m)Udnidoaph<68r^ zo$}NMH#QY;gxnp=)KYQgJQ)e2QLx=}-mdze={#O4KdE4*&a;GTFMF^G_EWalo#c{d z(l5;+Pc;`}NGewk6M3iu_?rR4(UqXRCxFJ8;!Xje_}|dI6U&lx#Uyg=A>5@dhzw7^ z{||{g1-2`j$e=COr1d8x{BYlyTKNVN@xJpo!{S$4A)JzdBgJqOZNsdgoG>39k?)h| zhub3L5-eNg>X~`+jp$f>p`QBxuAb*J%41^4XB|D}B-C+ci85}8z)=Vwr^O*Sq%Ub7 z;yQj#mU``TTJ78R>G8OI;5t1bw9p>Cmgo4iJN=9G&>>vUpx5rv$|n}-u+D7XaS86X zqsuVNozIE;NZ|sHlPkPf(ZM#CkQb3}1}^=_mJ=Q1OWZsM?Wa6_)QwH;zd)-)X|>ZX z!uv^3#P_uik)S5)m7?>J;!r4u6BhpP6uK`@6*qEd01V!hWa0x*n{^}`lu`O^ZVhhX zOxmGbGDHy?46*XMHE%hRAZv#chAUt*Xn)?}``Sam2Z2J%Pg>L?&qH$%_n|%>GdeV1 zw1=BfLy*+{IOxtQg61XX!xxAPJAwtP9Q45Xb)YX7veUnfPEY(hoa`=WKbB?Xd3O8r zhT7l6-zpxeSzs&8Wh1oIFYJ}f)QUICN`X5}Eggr~qPjcFnu#mV z*CKARg{0_{U5MQ2T`C2lQsV1)2Oc-n@5rWnwETCTC#{#kflutwP zfOwf&^czX}i(YxqRoO=;M|WYt@gJoy)yi4g0eI`qB=bcN<6g}|{i4p_JI6duiOW#7 zXv_F{uo~t2UT_x{9n0riY?$CQ}+Cg?4( za@UNZyDS#i*&F@>@Nkx}ego>Z9X{*FpB5+bfDiaz{Qi@#@e?#!{05Y-iCbotRf4NN z{kC$)aqYJ9gn?+}hls~=QKW>+(GD$KE__!{yO3wQuP%o_L2OkLQIu0V8+$PL%RjX+j;OC&$UM8K102y zpnvJ2^0#t4_16>}2O7GXivY|sYmCyb*n>qGW5o(RLxmmGDzRN0IXjg|L*!ae>jf#f2} z7T~x*;EC%?Ex4``aMu`RgbRcr34rtAG*|&s^aFlv3#0=k&|Zn7BwzdzpS*>)RNcPQ zEx{H!iFxpI5=@8J1emM?Sl3NVz11E?T*h7Wf(F8lit{_burAM-(Z*Fu+a~CAw2AU* z*+g|*H(Tn)9i7@&;PjuXmHM^YbJG~6_p{hDFmDD~dQv&dW<7#$fiS>3jEA0uKCm27 ztj%G3k-=LxyR#(S{rjgBZ%FZmpXmyGFS_ejyG^o@to>D?YFLC zBG^WdvF(eQj#KEc9I!3MPkuzULx@c=o|e)Q^2R`ymQaXI|q4j z00ze>n#Y%P4tT6@6H!iuzn9ZIo{_5@yx*jG{Q0e^Kx@zj{Zcer{P-cbFSUs5U{mTf zD}ySiDdD!@`}-VQ=pQ+h5dv!E!vYG^w*F}-!KUtGHUyHJfQ<%`JKYt{KV;d!aBn;; zBCr7=I7AMht~S2vaF4|v%+J3|VQ6(0_cq>7A9F!IG46)WAkk$fWle9=_r#)!3~n8B zuJ^$69~W)l;QCI^K|x<5?=$4s3ufj`{0XtpmEh+ly5=hF?9TT^sk1C)L65S8)HVd& zb~7|@!G_7wN$hoH6ylcS#k>~VAWNr+Zf6|%&z#123Y+ASj!Zyy3G~j0I^kUW3slWt zF$^sgEF~8&T||KLqNR(7q5cs; z-(ZvaI-AtB84wO7t;j5Po3v zE(o+`aF{9XJ*>}lT1QydXQqwRIq<9W@W-RN$GiNcHqts#jNU?TDz!I&t;-71=T1#7R z`)rrCs1yRG?CD*Ofp`efR^EC)`I`L;zi54nthU;04sD$Dla!NxaLv!x_~=n)av&g<<$Vm>dgw+nF?n4V4jdeSGKuJoV#0*kiRUMeHXaAR`AXh3xwa*|!$5>v@0)YQ+=-o*DrA z3!vDx>3q3{{()6*+YAGl6@Uzs%?U!oGP2ECOyji;Yp5D1yDEUdsco}=4;#dRvQU0{4y0Cm^X{4zcueldm`PY(9H21%uVPmDtR?oI3 zpB)2ZcK@s6uERD)2Uj^}_#YFXReVCg%>iK2zfpjO>j?orRREkJKx^I!0so-@I7Wa* zkrM)b*#L{=?+Sk!rv!9KtH!0jI{45C^xtD2ycJ;wpNKaa)&8eGq*=|EW%we!Dq*MA z26XBI=5}VH!dPJF50K0Jr=9g&0F=hT1=+2No5^l|I45d+lSh9n&p(EF6cY*ZXh``} ztx8JJVDgXC;85DqaPr5J9F8BmFV5trZ(+nqIs={-CC zd32hlfPA5m_OD7CW}ks?RcxpG5>zkO^U%O}#(cAdcz10fuA0IM=RM_Kn3BD%t#M}$uW?+eI$ZQ->w;)9ebC-{zlSQdy^F~8%3*EW1D=ys@_DOmJrLQK<+G#@cE04qBmIq zcaO!Lx68E$dWeK~cSY``nf;x2qZBMk1*A#k;l=nu%~-y#+^h zz1*3p-V!@q9?<6})312PA^wWi%jr;V{x|ub{dCyTI(}N`T@&-W zzQldHbai0d(6E2>=w~oIu`JWRw`J56z_~}#4pGkQ(^U29tC>Iq81ItL{Z+jTyZTAF zw=*8-$IFRd;m6ToNCXS+E{>ck_@EHX#q4&l?Eq{5cRDl@o929KPGL-@E}1t`V=HyR zyonks-0R^o=6(3MoTcv59ab%o5Hzsyu*%w=?a^Z)awYDF0;8t=U}gtI*U#- zqqN9Zi}+bqw*Y!I8>qhtpFqC`x$LKj)crbdcg>oL6te%js^E?n@sU2H`eYl5O<~Qe z8^;r0Hm|uteq`{}LS4US1A7*k-&hw`omXh@Enhq!~dM9wu6uKucSu&VgUdHnw&4yfSr?zKtE7G_TAUQF&&z z*bHuLY$sP&Obqq2VfW%E-W0n=VK=bQol{GbXvp2d<82{wVZWK~1=+B@%6n;SRiyVA8-v!oyCpgq{aNsnSpQ(V8|E=LfZH^G{x zI65zq!!*e0QTD6gNU$;orKq8(4$|`+7Tn~68zsM11ZWA|A9VNPo53Ye16*a7=5q_2 zzMw9>$aD~wQQLOMIKj>^F57-11va&=DlQfj`eHyc$Lb6Bs?3LmxeG0X5 zBZEhVqfEtYmW0lL6Puk+@}B_z39-mxO`ug*(@>qBj5b$cqF1ytz2rF};0~ z(%%5r+>%)`xYU2wU&Tx8Or`IJ6TpEYw*}e~fP<9XvF=+{fK#eO6jG%VIZT}%Z%PyIAdM_pfOn3{EhkUK zR}Ir;uyl1S6PrMkOQnW^v|orcGKk%edo)f96v z(z`*O(mP|*UfG$g-n_&_?U?i>%lttmcc@7-o{cmy)F%zY5qv0=qU7aB$88^f>O|u{ zsU(UM#o+u0NbD24=lmw22O;40qYYnn4c|- z{C0~=7DbD~{_P_{MNxm*C{UBM%(+NOlRvvS1IHW}j0TpDh+F4P{`g|ZJ}Hqb`j98& ziV@Lz=D*+CUBKD8d%48{%9iId0$KzUu`liD{kPdy(*KJ64YGz?W&DO&MTHV)sA;8? z80y+gFND~#%FY2CRXNe}o5`o+BhDCh9r*=L;z|%u>JuDUjn$ErOs24#E=iBWKqC?{ zKiL*SJPayZ=EqeAt`>C|^OYi93Fp3s{}drJ7eR9-a!_KP3Ayo3U5k;d9Bl9|H9@pc zD$42Yn@7@)0V%!YSxe}p+{`q(0UsC1@FVW@%5^mOWS{Z|BoBm`?3DC?kht^70qo->tD;a-Z) zL<%q@1TaWf#W3#Nw~J!DiJSQyDBD`YmX!Yn%I+_O?h8V66xQ#zG0L}nlc<5R2Z99u z^I*B{hkW^;RH&bjfTR8#0Y75Ej|RX@1^=`65d9q@3iv`V{~PAKhru9({FU!wuwZzQ zm^WDnw12oyxMgDZns-E4m+pAljN=NSOZr03nrP>`1l9$asxM@&PGq78(f}^?yFTWa zOb95bH20zoS)n}D;y!n8&yb;QhX1#loPfhQr}~m@?WXq1j>wGu^!VH)3nJE`><}sc2xWC8 zCm}!e;k^T$li*B&9aYtUyM(|lOL02bNd9xN&MG~oPZZCU`KNbNlJ=!TZH$qMCQR#_ z{14q^6xzdW4#o|e;64q2nljOT{W*-V&i>>!MY(4sjWECIpc{?!69s0pw=jb`}Gb`J-c;X$57N+wLdc{H$lBcBy9p zJ|-&ef+=wh2PxPKXpD0KYI(&T?ubFk;2_8jZN7lKH?pdD*Lul-sxRJkw@Y?79LT<# zPuk?Ygo3Y<3*J{7``3*mVd8JyRG^9uhSXbh$pws8Sq zuywsf-VsKo&!Y)RQPB;cc-Lbv1dD50m6h48JM-OS+2$6qoexM|akfvpY;}yi>^+1{ z9v*DH$MTho$k$Pv?Wx;aK0^;?od;Ox)pfS#96&M zIeX4ZI1rW)?>;zOtuv3=4@B-(*S>SU&iUDf@)mz_i&fdNzC1iXt0T$$rMvU97Qbr+ z!++%Y8FK-plmO$DcdYI%+r#%0!Dhk@8cn>_`0HTk#`D;hrf$YXExrJb#Zq%Sk5#0m zbskHks%=cK#t%g@U2ox4ykbt9EZh_^n|%w{MRLxE2XkOX=);3>GVo`kxsix$Da8X< z_dl?wlC_g2RQoj6%fXNp>Xr;!;HCZp*N3BIEapu%XZN|k@ors{vt!4!n8I-yHLS=^ zpE+_Mq?X$EjQ-qJcJ3Mb2G9k?eR>k9Mctp$FjCjs886}Fa39H~5Z_I!Kv#F}nRLtS zZ3;GYdTaWmunigH?W?NYSJk};-sfIjEiTWiHciz!KR|01O`Ee8O#y8ADweh;!K*Nz z3nkT|LUP_thxH^Z!n3vXbnc0nhRl>7tCYQ{XLXD{#g4JhwqtCJOgP5gS`3wKVZ`

0#P^rJVi?LR8+4aa%(Ful)*f`_jVKG8mJZx?GK3jTkz*}pA z`Ehv-;klF+|CHs{yPfS-5p>>+-QPsL77SZBRUId0y*MFX9s`SQHJJI>ya_f^E_ZZE zpr2}}oVTztJq`#O5n&I!Ab^QyVj1Zpn<~?IEPZFf94?I+SS%X}22E8-ssi;hUYMNv zd2zJ?u)3kA)ap-ORF$?2-o{#HG5|Bh6rJ3O9CDet_P$tpHtxo|MY2Y)S}yY@LxhV& zU~}N~lUm`?mtFl)NP^OzyW~~qCvU0>^phC1IsGI$|C577k4t3MzQ55OZy0o>K#N%+ zE%wa&XeD+yZjsEL7Sf?A6Z^Y)>nhWKjy~pHQ$cPrqhhZtkp=8># zvqC$iM%y)_yZR=Ka|vzLJtugE+MF>4P_yz-`-Ne%c`yctx|O{PYMyV$HN}BU)n<^_ zp!lP=Tt>c;G!iW@pAI#(m9$E5@Rz{psJy13!X9sGT}4go@`t&h{FP*e7yiuky+f46 zyw!!V^gA4;sds2{>=mPG-KrA8Mc9%HdN$eKTg;4fnd#ZEHjdsA%ic=MTtVqsEP+!f zOdkGJ+Wz9wh?jaz>aAWdh~62?P9bYAP8y~%i~|K*@?S%!(NznXRZ3;EUT;rONL{6YzSV=MThN$uZD ztHb3S3Q=V!&V08Z0o74%p-@ru!a|Ex+6+H#;_C3$?yVqLRMKw$W3Yxoo<3WT`(wOo zXN@e-)E4mFu<&5_R@lG5Ic3P+p5V%7aOx0jzBIHdxVL<+qq*xaj@_{VyTYP^!dLje zGV|AAfy(ze|tAor0dRs6s*2{@kla!r)xYzmT{h z{g`9{kYS9xukExB0h~L(t-R9wstJ{prQc z8&0V3U*M%2G8NFMT;Vr`Xt-+EXVk_>TPdEH)yC)4##v!qp=RYQM7^1kIp)<$wp??K za19erA<+tv!v=1mPUVUNI_59#U#k@_L6zx5r;o>GuDzOFz-%?UHTmx& zYy)2-pR*0TU4Tt*3ix^enDlD}c>S9K#vX7bCjBY_-teY?;|hSeI{>`-O#u@Hz+D22 z(Ts4I6yyp2NxbaXKvoy~-Hipkrh2pegMI2~cD#(~3Yq*KVhLMkb1e}jnO<{x#LTqv ztEc!kl5Bj{^qkYB=bTQ)rT&-x*2ZmSqAT+Yo$IEf=af=Yb*=x5p`kSYPJ?82Y5e#V zRv+Vn2n`wk1qftcHUP5WFfQn8ZT#9Dq~h)E8+ML728U8$UPXpEM@No8lu4-~2Vgq#lCve=`ZpuSxnB(GKv?mcG8q zwwRMx_0h!+)X&n4=@TQUDYLFThkR1WD$1#3ty|wox!bJsCko64kf~(tOFspbY(btW zvb#^J7Bwh)3^wcR?zhoksV)CUcK3l}+h9)`N=YaI`OoyJ@_jN=4;t_K9RtMaPUBtj za#PTU9>_k07!XR9o5ijtsk&jzSS1i67N_tRMNqbeAfA^ z5X>D0vt<;_ZG(T!?t*}}hPQsiU~V4)!<(psv8-%l9n1!USy+G>PhGK&+Xi3HwMzzS z?Y8vuMx;k6BZ@tO(leG`GAjMH!Q;7FOaFUI|IPcuwv4C4X=WsNtFQG-mcFZy4&e@I zUOC0)rA!W{)Ua`GYQARJH_7zkhkVnCryR=w^s&@NJ)h%!1d3&zwvInR(yiF-8TIYn={-nPIv>R_DSlS3 z)fqzG>RD=(yIC2Ui({L+SPz%Q;stwgX&IYaKMmH_?AzWOGWhb2>nfbRcysF)l`MPl z#xU9J#o0nBfoA)cgbCP-UsoY}afpcb;Zf9}kdFDMgVhrnH}1Yiu^srcJxlg`OP+8> z;1la9q+@=mvjHy+Y{30{KBU)FWV#(6!)3hv>H!*|yAL+su!6+=J2d?+nsKt2PMy;y z#^5zh@@5;KU@qxc?Y4K*-HplIEUacOXYe=sr<)!?)6(gCM@&nz`)>9x*LJB_geKc=A5nBBlJMX5H&o!xL}utrWX1{3 zM0CcX?Q!nvK$4yLv`v?qUG0;x4A#WiDV^l!=B-Pl%X=1fB)?rWT}@$rzM6h>#nks9Kg*M!k&W2mgOU;Jc3bWJp5qMz5UCS6~ zOZeZrRa}4(l36eVGw!7`0yA#>2+53_$NI`;$-Sh?yBenpoDo%Ce0Qa8V!A~Yd<(KS zyMKHYbli5N*hcycXPwL)VPn-;xI&NYX1a4`e&%D2>opvx8E8MJK;eVAu?yxcInX{q zlucL6yEBpgv-fk3Kk6V`aI9lIwfs=PQ!C`7o5QA2JT({R%{NAeD|vnIP-bzJtf>|_ zoKg!YFTXa~x>a2iN)FCUR`=WG@F$X6WDzsuC+U!weeQDF>=G z4>3pGeQM~SkNp02YBw+&@8IUr`klusyjM4$ zYJd55pUqJbl2fG~jIX`JE&gGI@a$Mf7}!C(_efV27idnc0(x`K^r8ryuBb^@IsW)b z!4|F9hSn)i2N&^Xr>q{xy+5#%7U}RbF4~Sk3eMfsJKT1oYs?Yn564KXE%Xa^&>{J; zgDz0p%I^n(z&3m|t#lAoa#6z}JB7L!Ka7JqLmG9|)`mgvAYGZ`sE9EfPGOtB>yeAy z!!q=QcFAtb|KguC!v>|@vZsA#Ps0zrhI@OK zZ1+GM}h8 zq*19WKM14yhbzYZZRTTWD5L3;OvO@*Wv59Rda4I54)k-nCy;4>p!kYsbjbs#;luIx zC5IV%ADw)E6JNWThWl`CC9Yd2du+R1%pOMcSJs2z80A^tL>sx~Pi+p?kQvYP;YR^|W_H?gz7t3;K zor&0b<*#AnV?Hu4M&mAc=n77qQ12aR@;{*oU!KU1fp_ddFSe)Q6&~Jvm4C1C?-2j~ z!oS1(JHo#~{vGAtG5)>IzoFQkhQIRn_$zx%`$@TScxEME7MAQ>;K>wNY;EKFc@Og- zd4}uZCA>W)k%j;Hzfw!ze5Pks75KbRBMO!MSo7O8BM~ToHr#8JvkmVCaLIli0`wkU zpdH$$2yTgP#?5%tmW)^8I~L#-=hgVb3raUPyaqyB7F2F7S;#{}N-tSR`bqlp@Pash zwk$|kVxo|Eic37z5|tsdpu#0?SrFS?f>%d)<2&lhH#e5V zAFdy>xv_LhedXrH*v{Wncza9htw$Tnf?#5EV|i(Fr5y0AU=Cmb;6#Sh&BC^#Gg1*= zjOb<$FiM7S=P1>g_DPuuV(poUny2Pnu>@hqn^oeiFNt|Km%y?O04C^WIz?kIVe>hR zLH_mc31@g1$!jeB9mQa*ZGSTgXl6fmWXt-r!mu_K1Go6I16XN!#`i3aPdOMZ6JP<6 zd^+hTiu2^tQ~dl24LPlO4qNQ7{G7!VBBuMlAR;`fDYE^WnV(lHTC{(7=3(gNNYXj~ zvPf!KX3=G_o*Uwwzdbl@cjx-cu$b3AEvRDFWquXIC3hp-+=$`iT!V&TFuxf5!d z9e4Z}7u&g~l0#xuxBhdZa5;f3(AJyYU<*V)jJm@So{bHk4cD<$_}97$SF}!-9MZj(=z;W09$Z<06rcD>O52a?J@&G$S z57&)*nbT-5Ff+rA>`>43CvjFf)UvF}|HD*tMt4_ucgKb=F&DR!e5DPQwSQ%`-Joik z{W{^NYMhqjg!Op)j9}8+peo5=sLFdXdjop|^%H%7!G}B|eabZ#4_`MYrssjgXV*wt z8*GVS(LBP@dzQ+-@8(Gfe(QGTDhPEhh?RJc7V7LgVB>Z;<8)=*({tT)93!*zVJR0I zrZD zn=*_8kIL9_mv>WT&|s(Ia`r|mD|rAdiurh5Ws*MJ#6~a@xeM|Swk4bVf1)uW|GLU# z>NG&4V&hOhJ3M!OK=?Zr>y&OcO)-PQ4v4!jn9LYZaz z|Hxqcd%K#J`tKy7=-!;QVbkj!)V5Z(puDNgjjM~4tHoisb`sI8n*dnmpF+HD7z{RJ z2Pv4#1(T25g+6$&b+f_z$w(lWpx&Lot?23OB8`IYAd?|)>znZt9!)w@ELiK^;K#2a z|5A0-RVr-&rwyI`(|aoCY(8TF;kxKPj~J*`y9)lsTR@qWL!G;iuba{vf4Cgc`IopA zjeTr$bV1`aANix{=a?AHE0+3CT|jXK&tc)bHXcKb`889T{jUi{JQmbXB?gnXxgpAh zz7(GTHrecdl(aD4hg`n#^=x^PXxubT^J}Iy`(tUsaGQtgBEQNG^V^xBCdtTp+UlD9 zFQPL6tX0RT&3+GGVR<9(<-vAV2F|g(*`K%xP3Ytfez$cgIB_$-{-JlWmFgvg*D-!6 z5W|%R3Zd^1($_%Q4-0Yqg!F|?Od;+dA$<*$9V)~P64KW|*&~IxM+>1R3ZcD(^fgfS zVj=F?LTDc$ePJ9_h}&NXy-Y}717$<}GW6u~OGCig@!mq{-a?MpyIg8t;<+&u&Dc`6 zMhIY=8oWz4`VJyIhMBCPx8Q6{29zsPmy}ygB+yS#tpDZn)f>sqT0=VCC4sp&Gh1Jo z@@@Llxgm-1W^d+}WTq4?yRu?c_&m}o!DfH21(JeFV^(@7f7dMkhb}RH*Bt+U2g&08 zU$rpf-0Dhy-u&fdCaa4wrQ7r;D15!k-|Vjma@Q&`l76PM)_OAa9`Zabz zWQ8bCf2_O;f3HCsO@16?6j{D+VcKeW(?53a)K7du`AfFxkKz335KJ-h1y*arBXxc+ zTYLwrKL&ey2x}nemrM>Co->aBn2p@zXUT(BJ+SF%$*-B=&q}IQIuaQ>&{$>q-;3l* zHvJMiUk83E(-PR2Ur~Ua2rTPr#JdHic&Nqy%~kNpvn}7#Bx(8fHdOa%j@Yq`0;A-! z={lEQSrt6l)cJa8ysK3j2s@olH`!~bS9h$#E#)F_&-TcJoEmEecmrlbkUky7@U|g} z#ZR6$F~S7MP9u9SJWz)}tw}PVTkQZs;~KwDgpilUb2RF$n~@ztyy?^Iv$*9IUQ;aV z6UV(xCft=9IoQG7&&inhVKR@uR+4z_H~n6j)BXuOXg2p-+7`oVclUjVayZJFtiSFw zhh!?kFO2~3aAn?~G@(@LsjOw2enT}oyynX6R<#QMI(BwxK5TFsM?sPFTxy>;p_g#_ zt+cC${W^!MU#4aL1t@oERpD^8U(GEYZmyfE>bz~3jfg{549!z zt5nOLzJ5_?hEqRyv-L$UaeT{Qq4{b`pO_e(!C`kLl5Q}-GIf=?F@!ZRIR)kU>h#HS zt+k>1{!Nq zAl@wrptGU6bmr5U_UbLXIM}<;&Q{0GPp1Ade{AZN=yFK`97b6(XRq~Cu_bn@oxRRY zzk+i`PEM~hQ@6pU75+z9$D%9Ale8RwojZRn3Vsey?&3YT?IQ>8w@M-Wp@#`3?18u&Zw`@timAb?S_5`UI)m9PcorzFha>)7*s!@|^si z<=M150;xD9V?1x%B}a?1?(LHl($f_6CMw|V)e*LEgpc{b0riM!+jHBa?~?0AlTnQq zOR$o|u=LbTzonB7x)Z;6*N2!p63kW=lPY_IVgo+K0ui248gtqVBc^FJd)$HF8+el~ z^t=nV>9zw_(Qj!@+*|3(zj@|Lj*-XKtc|7r!uh8=rdP$qylw6L%;E$xN2bB&Xu7lg zKqS2ymdgD#yfOaWccF^y1=yvno$u#f5d&h&^pJLfC>~Hmt{l9pR8Hp?l}`tCHaUmb zPk!M{0QZ$P#;{58*w*eVr4p+ria&ae<`Bj4KDF_y*=B0kM6DcBrcQH#B(EA;4993E zldPk%^yCo8nz6r_eiXI|5LTKEmYDp(sBy@#XLV3CZ|*Gjdu~4SIEI)|J*awyp5l?; z{2`(lW>krn4+-SWyq8O(bK_k2H%0&|#IVd;elVzZ<7IZ5x6+;FU7$xQlbAcI{M!)` z45?M4kg^;XQ)){-U9FS8pndVrxJTA^?mr3D??Kq!Lg53?!&`VuB6lG?$AQ+R&$P*} z{rC$1fj_Hjgc+=PvGkuS{4UtQh_Pw532Ed6(VIqM66fxB7bBOgq;GqX9Wv{x7&e#q zGgb5eyI1d{Rh_%4aMqS-Ff%G_ofao_*dtq~#fdKw3jBXhgO2oE_d_J455;A*+Y>o1#wFujg}Uo{iU2cK1gFc-YlSLgX6g=Ae)1! znWf2Tyox(^H+O@_835<(j0C;W;w?GI#cPn@?NbSBWX+ZKO0G(sU9(1W;)T>iAk^PD zeeoI&WjhIiQ{R5T1q&ZZomsQG0@(i4$-puhBP^r9=5E5D>%pD=IXzV~o;qfXYSS?> zkqsvUJ1rC0v`dU7_Xo-&g8T48_|l5NU@}#`-tq&PWeMh(d&8`*m?~-^_h94QTLdl_ zZ7C2PkNcU>J*q|Cs;Qc~F|*`AW`T59@04GflX#I*55G4Y%*xQKbFefmn_5Qefy~0{ z?BA#X*KnZ zo)dU(*;{!qdk;CV1rQy~5c}Ib?R?lMzInfA)d0!lqFIX7&<9sF|$V^3$89&3We1l8TO+ zOH+Trl?TsqnBDgupwURX@AO%MWylX|CG2|403y!V>-Wrm6TiMqtWI~l;Cq`vonn5F zmkjdK0VkS+9eQ%hvy_wjjn=vT}y8NyXz2pHfucZ@i!3#sFl}y*tDX3WMl9y^D?h zT!3KTG;~TRc{Fq%-k{w=)R}=re#j7wgp&B(lO!haW>86zvU1~k_3lwrdM|IXIsheQ z_TQLfHpkQd2n%eh^Q-33yA6l>q$bF$JmdvlJ-x|_&|GutZfcA_?nS)Y1PR>tTc zKZ=(}lir-}LoFCsID=pQs9OHm_H1CGsh|fIR*U5iES%%gP%Y~#sXyLRoja4>)l&u* zPPNZx^h)PV)BS(X!mCu<{LWqTy(VO&LzxBh2O=-uRtA5YKTwz03Opfi-4r)=I{y@n ze@vSYXx~0qtO%n^dw4RO?!V4U9}v}T>@55YD~rUD%PI zyL~kvy_q#JZ(!Ic9U)R1_bmTzfMs$=Oi-<9e*7CDzRNBGzK}ZKN)Ru6(=tp1xSPx) zWUq!p-VK#md+<*(H1{q(1Bg-muQeex+27#UjvFrJP5!UuxRq_etn6{|ck)!Ueo=YU zrH_rsd^jiR!sedE|ERvtgciw;b5eqcV{T>&uaFpq-&f;epJLtY#>)@3TMA(>6pydjR07Ah=yu8 z&wdsF;Uly9ju9{#l~t-Hm(rXeeW%hxia?HlKjf~r^tQ3BF9Kk6pG>#7={K*K=3|@u zwWMfD)Qu#(jiAWGMdgd)=>u#s;@z*IRAL@8-DebmXt7r1SpsWP#k zkkQG)D%H~8)P}6Y#S8i1c>@q&D-Xd|>lhIgO?{gwQ3{~suqHN~M)9uu9i1|FSIxUS z5%1A+%01212+2LOeni;O5MFdBf5(h`>hfy8d_qWql?-u<`u%L$QD21(PiFbSOf2Co zy1befP6No;|2DK&u8(+M=a7qQ5Qe4nySQMcR5ie~ zOQF2;NLI!P_wGr0{p{-$)%g*YtO;xd2TGH`=f=acL!rU?$d;{zc)}ZL4?AD_JcI^R zMtgRM=M-J?=$3mfE|$l;zePaT@6AVe#}${R$I^$51X9Pu|F4Lo&g68%t?XwK&)tOZ zJ9V%Sx@b?iGI1tClq<_g94GgV%#%i(Hmy(C=PB()?5TG|mIHbc%)e}WK(ct(Tj2l3 zLw^bJTC16u{^rXiY4yDf*}XZ=h{mhcm;ZNfCuK1W_Pv(MzlRg;8I{2Gz*r)bRroG{-0%sMsbwM=we@35z zc=I7!Lm9)%B;HIO7Z4>_R9QoKy5bSfeb2&}|5k1?1NO_z#Nk_OX?zsx z#Dz|X*t@M5GjR7ylH z>$ox!?5~UYc2bMQ?kAoib@e9sieoVxA3JBRep5 z-^zfbzcb5U*0!qqY(A~2FLPyPssN-IW{>}pLkqp-q#}lKW>KI2ALB&-wN9g|75>-X z8qT`$oln+fbwUVkO25p~w-nOHbUv93jt? z4=w>}ci*4}E$21*TXgX8GJdJCJiyw-4cg4|{mcAwEC$QY7rkrrOi4C};9|0o7Le91 z2Bg+V!>Xl{(gQ(Z+}!A8i=3rG0W=ztUY*OpsvuV~#y8)g4AbJ+UJbjZ>% z1PsFe_6zC^M9qXcK|?}iApJD?{!7*uND|BZR=|)r2C$|yFc<}<&rAJ7FA4^YGcF}8 z)3+^?_=x43F(RKk&6Uu@!ILC9+e2+7V0r(^6^1RYs+?_KNpn*pT`AHcuB6zPD~ug8 z7@lGvtU*{d;8vVWv#feP5$15yaDl@HC(9^xWKV*mNxqYa&gl~`!Vr+N(Csi+m{Fw|6Y9p*?|Jz?;z|wQ0o7?U#fh8 zgm|yFm_!FYdD^8r5@O1D^DtsU{MXMHA+`?0q$<)&C+r1+o*8Vb!|ul#Fxc8B(yAQa zBCK0f&gX-2EZ^qQ>P_f7c8v>M4lMh#|#Y^U`sSBkO}j zDRUsWOA$@JTu2E?yf`2+XOZ}^wli~16R=e=SwT3yKg>h;42Ql>9MUijH?}^wFC3Hi zs+nf-VED$nmcm?nGaC|_TdH^dwxn|da&lScd+ABz-dNne=&=o;Eu=pb8n;XYbhhLp{(Qaj@(;12jd&YbUwZc$%MUT>4q^K zk8jPLtZ-EEb@s;l<8CnQc2rsk?Wvgp|Cw^?Qs>iVw^y>^bCWeS814QH>nP>N89#)W z?^314LwjQV(d}ph2>WXEX9qhs%wm<+O+em-fe?`;jxr~buK+SXQSM*HMZGQNF zK6Oqt0$^*Tzli11iHi4|F%2A8bWXKEH6`@6_1eVx$E`UyQ)Fmq0Bwa1cKu`C+N$=q z_S~v>x&UcaR~Qw>Fc^r)&-%6@zuM7_vZ~hqJRC6Fo^!K@Q52VVn1G}8QU;1XY$gjw z@f-27Kl5pZaA~HAqeFIK*h1RAci|MwXppe4(mG<(S9JRk)!CdN2Cc~FK*m1Racx{c zS?0eFYFZSOy(XZnR6sunC&WMgyF*SBViQ#k)Fr_SGt?>i<7{lGw+(q%S3?igESxHv zTxj!Naw?89i3L;Dy$&z+;RVHb35}r;jR3QqOZ}fhl@PQ4Z4^q{#_C>Srb1#WpS~}V zS!rgnY;&kZ%&?l#1s$+=O*c~grjH~(0j|352u*(aEZJ;jQRFaQ>du~!K%x#f>;x^l z1xSWX>k}vFr`9 zbH+$pzg2)}E4M6P4w5gj(%%y%yV9#hl-?L77L|Tkko^oRy{Q1kRtmu5#Cs;eIlRGY$7&2k1G+S}y1(hG~NvBuf8%fW0gI`Qc=T&6f(v0{*+_T!|Fs7}|2&RiGoG`LCB!Zigo1TQ* zUI`!LVwP}N--!cI{&qhd@0tj+cMNAdp$zx#@vQoD@MDMuylfz>z}#D6(#JXFg-;4zu6?49u*e&rse#v`K5xt=j#uD89EBEiyJNC(A^^ z(es_aiys%S<1CO%wT^oWOwL?Wxzrz`!ESA^h5MJ(XrD}U$oUmg1E!w-a>&sC@>3US zQiKlS`^3{b2lJ^JPJS@k7}?lW)->|hQg~a@wZgcvCYcC-9?U%b=&4~vsGUz3n7VmIiIe9J#$~x1b z5RS;lA6HY|LRU(&N9+4TJpm85-d&kYmv%nMl}xJm1mm{F|LdXS`OKOMU7Gz#{CiJJ zrBQK#Afz#podh%EVbn!Q%fuLi!pg6W0+NNg4LE4+&!oA_GGoVr!~ zXR^ZH^O8eT=uk3CG0^rFz#E|FYiGHUGC?q%A3;*x-=|Ep!#uq~o()s6pSSULD6kbbnXF`+{una18ze>n*0vMd ze`DD9IvzB14Ekn9d(Sv!LCx+rG1{|Pkt?w&G`8jz>8gUqC_8qt1uM4CGtyyS}*>EYm^ zzS8OO`qb%C?ddP&wI%#LXHdc}?@sQjCAiFmqT5?o8Tfpuuf!s=x!?|mejmQG!v$*j zAG7UeaYgBKK>N z+&uf{QS{*ZV*5s`5qU_3gJK>sno2Gr5mtKW8L4R?^&M(E`y2F3hErE`5_-+H834^QL z*6{)IOzh%U6-NDy=Wqci$>%`X6n<5}K-ru^XjUOKpOC&>wyTt_j?aOz8ww!T7eY4^ z($_%QRfV`kh0wKy(9}X`xbo?RxK%-j5$#{YRM<9y2!DY>O$xnTq4yFJP6_`zXY<+0 z=Rny9`BhVVe-d%41CXfyDS@O6WL*Ga)8$ZWl115{%cKwNd@KB=oN!VwXOckr5B^#6 zh%eE~-$^;jSSyM|?5>GI+)L3P;FkHvPBX?AfCO*Ui(-Bkna!SS;`J_%{#c$pVIIYV z@7k+Hev?&5^=gZMA+2(F=VzxBF_Yx5uSdRXuMyWLy4kz-{kw_}o6}=m%9Wgh?Aftr zbed?acWFp_LTOTx*;!ty=v{k}zxZ8yTkE(*I9v4feqL<94=u&{p5a^z&V7R7 z`rbB!F1-F*bVnK|JMzyU`)sq3*bgS08+4J+F01HZ{KAe6(M!|GjtwPsc3)scYjSrH zR5l0VCdWfRqvl)|Y2%?Qd@eNPz0!hP`y@OleF~qVTfj7P*Yf^yt!S9845Ml&Z(gk^ zWN|tGq!LtaFkZ(N)tPPQj?CeeC|abXjFb$iOPa2`_VX zrY>^zq|S3?yBiU+HNts*Wi@~NXJGs`$n!SvL#8*(pGCv!=myAG8NnR65f5OglO@ij z$4A#CLLUhX!M19D*QugS1`l!Eb>aV$9G}%%5VBW}b}$hR&4#e%yAjjqd1XeSal!4J zTtlx#8j0}HCadE}ZidAfi4sCOsbNR47G^{I8x@%&akJCcGqRv&Ee0ml76~7*8 zh`Sdy)Y7_N^+tm67?eWwX2d(!)y%tD)S7&x2+$Ie>9Owd#|IV~I(1bm^-Gd=-eI4&7xg)MzVH7$4~1> z>)c(YH{EM>!CY}27FRAAq~oXk_ECZ7BC(V^@7Yv4oxkobx@ceOhGeC8SYIVJVmH;Q zdIz)VNuv9)!pc>Op8D$O+*1Nk+{)Ryjc4}!eQ=dRRNF;x-7Uz`E2AD52;YhBKN{_Um@B2)feTngsm=LQS=7|?^$%%)ujl3 z8V5<&7xB(*;8r{q4xjGUtq`Zn{j02iB8njL&vJFKs$3B1m-%EJX9A~exVARZL11#N zB2yRT<_{yYrqW;gyW@Fmjz+}gPNp@djEsxB!h_)w|JbdppTn8l%DxsBK2Wxv29l^$ zZdr@F`d^C}V^U0Mt9Yv~Wl|wKU3c(5M(j~L4@hpUv9eO{-=-olHBDWxaSR81sd2eQ z*r28^c0RgY_aV}LlQMGiZC(a(CH}pNn_3)K>USv)8+Z6nQ|tSS=Y1dpUaPwR;Q)Xy z;)Wjo=;UH{f)>vgEJa|GV7(4@n&ecg>s6Snyc1vs+toqaHjZPdJuUl`c(06PyPhF3 ztM?(`jcakrgvYxdGH<-sI*-?FD0`@m+hS`l(Z_L6wFR=xsm`L+1nio>5@Bi4;kihKt}npQ9oxU(4ZkgfYT z`h@pH?y7K`r*W)9sj|S?RWO);(68cEec2E86Wp}1Qdu^P_4ZZ9a%G~?zOj4pMfY3L zA`vE^R)kTdUjs(DDqu&%e$i#&1@KgS!#lVb%gx!>OGl0ywPy`*Bjx~czdvcz93XBy zwSa<7!|}OIlY4Hvf7os%@JllCP2?un$$$AKvi7HGdS|fh(iQ#+hcv_I9J=1yJ?*t- zmAe?vJgvOKf0zaYTSDl9Oc?s#3HJ-kF$P4dES>!y zV;(4mi0s=jBx#lZhT%-MN0!87>`8>M%sm1DL2l0tH80K0r2Os|+Q(Ukn--ETC?23O?2tv33oe?uY``^_Pb?C=7hmjNm*)jNnq{#eYv z2XGiQ6vOew8%FR)0}aXy_vqhbzIhWL;Mc#I(Y0->Ldz7oPob+6x?iEUVZyxaI|@x# zXuCq^DfB}^owZ7d@ETRE61aLNW{I@}%Z<|WvlX46EvVL2drX{CoxJ5x*3aMKz8|@# zOp=6?;2Sh2_w4vQS%(dnG41HjT_O9=|1~mx>~_iX!G7|qN;}bha=W$!#rsL4U;M%P zakopuUyVCeC%FpWXrIHExp@0icWV^3MR}0aNOKLcqeb-8N7-6f+}kZKspui~auA&y z2Gxr#23k1`dc3E8Tp0Zqq`A=73iG^0Z=dhI8*Oe;%})U{y5=8Q+#72Cngi`=9<@`} z9@)_720-JL9Z)bvT%9x*39G2mn}bS0wj@OMszRkb&72e!Z^a80Oc}1g%?G3Rh@zuG z(RkE}h1C7y>u;pPh)hoaKtxY-^i3-M1^_|JY@d3wY~r;~<(()VfC#tyxM3X8&)V*v zZ`=LJw%uo1$=I$_IMU6hdh56Lx#3*ISvK`f}yikXcg z&M2Or8@LV!zqMS~9%IpI81#;9*3%(Xw|h&Dlh~s}q0ieeP4+B5*qJX$pF&+D+(YIj zjgGOM>#O$rny?Go_TnIzT?1zHtD{`JTjyB?2hqPB-83~C;{!Q}HjWl~tf(vLD{IKB z9lPo_FIQW3{;uR9wI)C7Z2xY^K!flp$~}M)?Rku*mbRl#smvs%9petE?Xia1j>}V{ zvd$8o+E#>katU8DcmdB#g+_4~2v5i`{2b~D5j}{THKTbkp3hL3!;|B1@LXP?`?&$0 zyb2ecHV90BC%zFJo}W0Psp7897=NgO^=MsWPhXy&y_MPPKl=-tmzjzE#ADZc8ctWs zC;9L-bEY0hzY(!Jl8DxI~oD5IO zvw`)RMf_LgHTxHjEX?w5EGo=a^{@Rm3w!B#lT1R)EbnDSh1t5X$s$5L*Ayii{JX*`5jA_h ztdE}Vc78b{H#9|j+2Cm6h| z_qPZvKPlIV1tD;X+&)k?m0(nXi!5%SYO!j4r+zgw8aC7+4?ti-pDU;CJSs+? zu)`J3?4M_S-o8@%-oc&wWBCU(CV9W!HH+%rsw%jtgZ5T-1Fdz%QzXS?~chFWS>6 z8Q$W?SX?rQmaJ>h2dNo^w>09~cnA+R#?(h^n|b442*lZ5INl%bX>NaN6!N{U zeC>`4U9sNcl3VJf;D=iE_yc#;(o_x*YY7oM!4AX_d)t43Sn+<_=oEIvU!&pZ7)B{; zaiC%iCG+L0WOiw(9;F@Vbo0C5LEdL-v;_hE9= zG~GkK%IrDuS?a1{sO$yQ!B~;Fto;?02K%e60*i!9x=blThhoh)$UxbCWDV7ynJ7lo z{q%+_5mTQUtg%%*b%FO3mM8d>0jlSQs5e;wZ(q%$?bYzC8sk0bUmHWJv7**rj~S1u zPmN*QHYQhwul#TFxIyLZUPI9auKj@)|L(m;CvD)0H^JN~i!o&X1>V){=h@}vuIc3t zOr!R6TUJ(XUisYUOT#vW@zjBAozB8qcdEn)pX?mPgpz^)mGe>wi8_Gtvi-l8sOEbGHF>L=n z*29oxo9qzi{cz=Hi0@F2nrGV2s+lc>Q>S`Q8RpWar7v^@EWl(fjP+~}1@;c_lRJtNp=z*CW{i*6C-;v6vy-uKpKJ$X z#rxzrnj_<*vn7{hC#eN;?Q$xCo|Olo4Z5lpf4}LO5+toTkUiq&7JK5U!+YY$&qnsR zsLCkMUI=jb{!@Cr!Ozm3kyj`xwADp4VdBaE^NZD71x^Vf1xc>^6l=)&LKvL;?j7B{ zL`|@5`X2Txc8E*H+y%BXKH9Oft_b2jAWGB0#`jg*__Fs1Hoh(9TQYku_*rkU=hfDx zfNSk2Tn(EMd)`%}APj{;?Rg!U{~hk(8WrwzgZ3KwV*=!Cx2ro<#k<`W|3%{#MSETG ziu~*tbIa{^ldw7ecaIwr>(g*T=YFnjc5ze3Lu?I$GhXg^B4!0+dGv(a=7y_UY~~A& zZSHQLf2zeH zdj(Lz62JMc0%fylE8N#ub9A_!oHtohG~V;~ka}kR;o*AkEEIqUIMn2KVZ&O8%HK8U zud#^XdH_4#Y-(=o754rz>N#md@<} zBQ}adGFF7~n>(??ix%MjV6rk+dq3%|=gJ|kSB`fsNXk3rk0+n5r9Da>2IUs5u1Cna zCw8i226hqAV>qP8sotyvN=)t3z8m`m7nkL#=$?btc=k^3+hVyk$4(vL0n2;*$TK(! z7EeIn^UuT}&uggI6XC&7d~ud*FI!QkIbYfO`G04f;NGBpqobGG{ND|P#BK3!A#d)2 z?tc6mr-$6x;t}>K(*|{J`^oER`7jC%i1wrACVJ|QE6$I1chXLD(aCf>#c+bVy9DDE z9?{0fJC)gVq%#LwzY03d{%0Km(cK;M&P$ip^G;)aOKGm0H%Yg|&N08K=cNy+b&IRe zIseJ+Ne?x1?{u)K_1hG&!hhO|m;n&jHu?VmkQ!h6M47~}G2TJ5!612s|GMd#9pX;5 zmnLU<#mpCGKBf+ww&M|s%*>W=eA00i7yn-Dp7_7UJ{jG;a6#wM$#<0)VER9P(4Ek` z4o80L?VGmuDL=Yv=N~vA-nqYQ+TLlqJy*lj24K@3qX^z(W?uul!M1B4YU# zNa{X7uv-exG)(nBG9Pn{Zm@h0yji~Btio!^xLWkO{A$Yx`ygS8e`lC5-T!1Eq1k^I z(Zy$PCgarB!Lc%9w%MPxF)*3|ZHn4*L0DLokJlH_Q!UN@Nfs?F%`>W%BjO<(DG+S& zUn39-Jgy&{&cAQfozC?5pe75asPQg2<{(c~XPMGs{$8?jzr!Ha&2u8i1-18eAx86# z>*^QARBRI7EA{gZyiR1crZ$F&t;^CG86MW6D{}$FHC1{iGr_&36$1-& zd=T-jqKJf)dli6bdwHJW!@F%xz(%TSUSo@*x$t4KaVmMY z`tnyJb^tez&)2+m*OrdE^W)N8!20*HKSP6|CY3hv;_qtP(ecxZQh%EH^p^5mY~hyJWj24$Odr}4y9}BR_T4}MGRLc{#1Hd9@9-OWNIQ@B4v83S zmg!|vyZr%06ZW>px5P7(<<_y|=mqia1@vhA;l)v};o#v#_0fv-MO#{;9mg)g0nM?C z({o8Gi9Z;tKm15VI-!`UhaXAu4DrU2NP2S5+Nk%7#=sdAJ~<)0IwxCAMZH$K`5V%8YRL2SpV|_C zuxf!azP6>De19ZgmVEy~zF#Zfi{#r!zGvreNbSvPnvxG?rnl?xqULBU{q~Ndx27)Z zIC^R7l8&QSrlxir#Rovg(JAS*qOwRFOP{)Bag?$vDZ7HQWAp3MH$pq876FrvjZqY# z&q@FnPDLoa#ZWqzY?H}$1}IGwN(oS^1f`1k8#opspImQYtw<=hlYV#$WI1|X`ZCI< z7M+Vzzl}NT2HgDvIp@*zE0*nDd}NpNqq-lAHH+TlpOU_U%;m)>&IHIB6|1j^cb(6d z_Y3c^t6bL!H85feE7E_=j^T@OlX@3L5DZ(Hx+J7YGF27kO;ra23SUSzN-E~hi+BH+ zTx4ciYp}$-a<@g2UB2E`RRj$WZ*8@(d+k&dJDEjT~* zp^l?(wcuMBW=Aiu;0380LV()Tk}z9sYGKFGS_7y}(Z}Zo!RaCF6{&MOj$UZ77p6|@ zIJ(|~>r>-9j^2_UOU1XOOX+|{l(r?Q8^qxf{&%s8(?vC25k2JCBjOBf)@u@f>}kn+ zJX^^f+yHE$yL^KzFzxl`mi(PDKhkgPh%$H|X-}*);vLaU@2+OUP^1}k>*suy=mGaC zICce+q^_kedbuGzEl@?AiM!QL*HkD=3o8Rk*9hVjY9^m$A(SrdXrSHtlW=#*ht7X&jm;9!L% z$5_!$8!r9GQd)CMEUi-7oDZqEx3PYPr!?Re_y@+j_*RU6F=X$*dX9}rHbcfYh zTWP8JxT|&KTSPsnlk(=9;aMz}GYxx3_$vy|^39m2H#45=cx{rRQ5O``;oPM&O(z2T`PwQO89k~2XWW@Iv zr!DEJx%XH-W$86r&RjTBg^9Kd>Xgs9xrDbq2Fm4tdb@tIS5Rax-L0eBo(0D_!+GcL zU6Cx(IslQQpVn(Z6o0*oYT**@&4hvSsLIe!_833Co%xD*ca9L37(4qPNl%D>k5?cG z#0Zqox>E+q^+@w}{bY3`$~$bJyF$=i1yJZWPN4e9isOn`s@SJO*r$qNb)$N_ezL2J zU|$GfUnqu^fc|`=8$Nv}X9QjLgS_cr9VPmfrDn=l{bpGTbf5yd%{=92|kK=^I&J zLTqqag-hbO{{8?g6=y$QhCS%c_1%Xx+3nFyu3$JDZP^TUR$q=3`?)NuB*lJ!Ej?Jn zd77X03eAb%Ek=y^k6r?i)cr6vo5Pkp#!F`=^Vb!xo>++dO8us_ePt2SRC`I8$+Ulf zoB2TU9e!scMIM>|+y2^$oXmUVI{=(Dy>w2z-9fGZaz^Ka?6ggPCS~Wb*Y`#qd`S#f zJK>*I=#s5Nbe;lwn@)U|p0YBkT7T>3!lPnuNK;dhkD9Z7Q4%8iO%eK6= zeuxVZ(jLX_IvpIvD^6$b{hk`n@t+y5Rqn%i&E|bvOH~a5m!d5y`W~ zN6FKgZD!~t#EpwMO1;LZZPjN_u-l5Jys^WmoAuMbPNDVIxN=u^{0`=Ni;y_YZFeo?ab!Qyj8$5@Bz*0bGV$R zuzRfk*H<+1DNM13Sx7lx-h74)dKLSWvD*3eQC#_)B`ZTXBUW3jg+~z5d5;6xOP>T7 zy1!xTx(6sb4FE00Y2@?p2x^4d%X|0?EOtz}^CzxK>0zu$FOtPlZ2O}v*HD?bYQpTX z&oxjdgqgn-W}aYTh^k-p9r3qaWGqB<+TYO@YYhy7mNyL)~Y#j@i~fe{6SVcJoT3i*B6gkG)^wbmP1Nb|J*J4akqLcKCe4 z@Yz?^^*5#w;JHC!iE9UV-N;WtZE-Z@b2sT<6mpz|&R3Bnr|aI&f6lfK0p1rB+_F~W~R#UUL7%z^&B}|m`7>dv}Vd_T;3QOG!SF_^7ev_BK;c7LVt?H)67=#r76`N7xTIFe8 zv6mB1k_D^9LZ1KYabj@SdrS(Hb?vryrWd=l8@u@%h?|-1a4Yk#MaPPm59D@ciuw0u z(qc>H-Y4np??E|woifXrLT-N(g+8^6Ht=cd-uvvg-q(G;zw0d(f{lxpo+)f&;J?V@ ztm5Aw7;iAKLC^a4HG4h{*Gep*+Hd`dmeV@a5q%9`RVN~PyoN)clbho|(biUR`IWhM zl}6g8?3@^h-jToqjZCyf55IM^?gWPZI$C{f6Chw_2<7A~M}F$3@4qhL)D(e^?ZJCsHp*q#de#BaewTF&3~r7v+)j_SX!+Lx7!+-JAnQ0IXrdPF zm}rX~dNaqF(U!H@Xa$LtF7b#&(pd&4YMte*M5VJFoA{KooSm5IEK#0bGFT%Mmpe-# zR{)#OsKjVzIgZJq`FxBGb!Iu9=3$l-5(Ay3C|Qvn@@XlhUr0=JUSrrEZjsKR`!LIi ziPM~A2o3#K&W{HfoD@PipPA)jVv-LyW5rl^X>NSpcI%F>`nYW}ynC2y_Xci!bnOke z({09qXSR8N(!Cq@uG#Uhu2`8fR!ERl^s2T?`hExOALk+GHlQ_98~-JKVzw(@4n^~5 zwtq76mD+>tpV)r>yta#8fK8evF1QFnt)~!-X9E~s7RG4~1`Q;Dv6UzehTyVSMCo1( z(mnmVQ2Gy%_b$8{f|Lu*2gnlLw-7oKFe&UDLJFn*r`M}Z&+@(SN!no0o%*+ClbsSK%Zaw#r(`0My>w-LZ~OtJTd%yO zZJUx!cS4vhcSVgmz&zjb`HAAUS$xpz*{_+6pTAr}38 z3G*1VBJXjnlUn5oHg{ff7)(y9w3*!(iV4f&dx6$=9}At`Wq$wf3Dy`Q@n7b@!P$>e ze>nT%BR^F|>lQdWQTizA;GVV+ZT*12u5aSGZiBcu)vDNSKi!L&Icc5ajkN@ayzv>? z{|Rrzc2e!bjW@2%O|?B}dBaM5ImC20^AvTZwmP^r>e^+YnCE^44H72Sr;9(1qeK*~ z)UO?WB>vc}3j5C&!Y2EX^l;;k_XGa0Lpg`>N4DNRl}&a^m@MEAJ70P@e`NXU^lZ8l z!gTP5yTGRxe`NXT?dL=Evhm>$ccD)&{>b9BIgB4|{p3lIJtz|V@o2~&hD)jc-0O}% z)~oh7?Ir$58}VnxkAFpLy?^>nFa9X!Y_Is^AM6T<+^00w)Y!vUY>|I%k;O^n{=F9S zMPiDF#%L(8R5OmOJdL)#41lirHrBs994G;YfzsDUiH!?gCk;z8V}8QsvlCnAG3N3T z;~v#_of`@0iHm}dFwM)=9Db(1z)Dq^ws8b=$>xbez2r;1oa4R3RgVi^Px@iwxYR3` z-Poqoed@O=HP#~kJAVjDN$dE&dG`i9#!Eix02ik$yXFHQjed4Ea-eGx1v8F6xu?uL z({d%VqC6zzfk95*wNv7*Gj&EJq`@vngZoDs4M;pFaRvf&YU;i{5RB!IK4<9eyyBP- zY`vY9mTFZD5N|U}sUO>KPG0qG{Edb{HrCNSGmVjwbXT1hH{q6+y zQ6Z1a6F|?u%>fK%>A~ZxF0YCpuRMPv$p!5(L7U@uz6!LpKnrB##r~|JRKb9-63W8r zp+c_2p2wokoZKm?^~QZK_EnjrehV`x=@_&iZn7ucRWQ!dY&U0`~Mk@Tv3 zI)y2cOEdkyu~)9^JxV)x}xx0);paix!4)paL;q$B8t zr{3#tcT^m?VnHi&on%9=@`(05TUy>b!2jU+Cq=uv)xNUlLAjhUJ4-#3& zOO=~b6O`|FGP)XOLn09yjkK$?FoHCNd0#bQ3ZP4R3NW=`W&h?|QSP6`nLl{r)$>_dLUQq-DTs2%%8r)YzG`+Db>x>TZbn-8SMb%naci zh2tyWz`5=TgTU)tc~O?2SL%8MIe@P81-+eQj8p**UB57;?>-SkZv(JSK3ovn3baGO zdqiWvbnbDfeyL%{b>t}|gc?YY6JX`^0Q!l1r;<`DQHz-;Y1X=%{xB>-cE0;_@<~6Y zptkiE!M#^(J#wfF?7mRiz$2*wZOuu;nnu8=PFOiO1tdPC3f%lr;~CH?_s4AutH|az zt5tG6MFjm!j9ouW?}wys7()#YYW@t@AHPF&7zehirXqf#7ql}u=9}8wuk4Cc*%iy9 z?`}^w6{oh|`|by$UQRV#k)C=5PahN$WW82b%Q4n|I$B?%z#?Aya--LTkY46G2Ujot zOb-zAeVUoPO4!chfR{S}VroZVJ*09J0$=~~{}los2bh4sk1(tG5P>U@)Px&>pZ|S` zs?$Tf0f8$twsh=793*ooTlP#c(bekxYnobj;#@eM&bdqpNs&rUi z$r&(uM{!IEJBp3fgC1$tuvF=o)b$rQ>h}lnbqEaFB9&^m6$`gt+PD&|3j9YllT$eG z(B?){j-_Vic1$+(*xv{OAeA1h&3=^FKsVnylpBn+WWlp9lNpS=lBTC#5OzL6!^>Qe zo?c*kkJAIuyMKgT9W-<rR+n|tE{%&c^cSy~uHCxbrWa}7xwb}{YJJKDXA0N3`9t$2G!XK%Db;hT_xID6 zrylzSwvN_LOjYcMu%-TJ_<4h~<&3sGt9Yg-`w_OVGwTdHvuNvAkM!OJBZD z=b_aTJg34OLt!M-(L6?5zbXA%oAPhoG%$5-LAT*z$){R!r>DF)=sZsd^UE&qB)&jS zL$wN(4f}nFi`ySlyqio<*V@Q_m6_;+405hq9jy-sWp{gtQcg_%bQivw-)qeSIc0Ly zB*udDdeJOpnhf~7-08fu!nAU<#kZVxbek|sBywS7BO18leg-El(T$O4I9A#j{-9&-80y z8Kga}pgP@ZMQcy8pnE9&n4-;zuZBc)juA9(YIea4<#z67vOa>2M7eiuW}$`g#y*M4 zWU%kdz;!ni`PaGFnU7h2t@}=2V51i&57#Thv}3+VD#sy^VyRVvEWp6O3~;=_Y0&JJ z2{aN)H}-{~h+zvE&%O}JWM-5uMtXfG@ff)UPDi%sMa~(Bv98~0smJNo`i_1FGTjIV znqeCr)~5}d3~Lt?wV;>nnXh_(G@?C+I?BotG|zVCCcT^IsUjH7_NCt*p?Mw$PV22H zZ_Z7vxArMjp=!nT;%&x>nQG!W3LXc~&2eR$usLxod&&o<B;e$1V2MPRd0qxV#;hX|`7Lf0}DCsYxI{(n76n=tv*0mBOt$J^+sPed15nzn#a ze>uY>*F3qu)Ws5RuGK`cf}zb?6HC2mW3HJ_cQnVJ1-ClMaHV4y@Uy)Ft)dwh;X29i zX9f(JPpkv57-~6)VGTK~$iM#A2BlZqfBBJrzwJ*^IeXfE+60EkW;~)Yg!4w1V~3l~ zIY-(F#$|`K_s>g7a^&@{{s|cUK>Rx*_9}?&<`->kzQjn|_b_Lwy^j0^SZy(7xxE`h zzwsaR8~MpA!#>C+K~uCd=K||iq_pqv`kY+?{s1c##>eSaLACkj3o7fAA;8|EsNBC1 z4zba3>UxG`g=830P3oVfFvlN92ao=fSf&1c+dQV44i~jv;;D>>rP;7oPTU$!JF6nJ zs!?dh6w|cnGyU%plREEubWea^d>3mB#ES&+0!{kuLA=dDIcyH&Nf6GmISk#0tu9{h zm~F-hmgRqeKsAj~+c&;Msl)wtZts*m19L3P>oyk8OS3&nSM#Z7jkewa^4g!shSbCe zi;$z^JM0lz2H9^;mmapaBYFK3h@p&wjc6pHU@C{ zSgPcuj^L$Vd!y_WW_fM1cco@O4Zm4Y*cb2`qf}I1>eK23LIEpBY2n zWb*2Q_43Iid*%Df&;B3fds#ML+t;EqlJOWBK4cDkff4d6$_2Q%i~CrCQX?wsX+&3R=m zhnK0vl9zayWcEw!$Jcn3ygn6z&J4Gm#1`&&Hq3K&Cn?yv}$j&Fy^ojCDDBz$x;{yeyK> znFOmUp2m7QHNy|~j~by`u19VI5{Z#2*{U5!?=W2#fgw!$KiCblRC^z|@^8l0nf^^L zSToRDTw~jjURofehIrHFmtgBAfK;pLR{*#r({G*jKSx`>3Q%j^>;m69OPeEg`>Hsg zJ^2bZVsOtxN6Bug1W~X{ANI7dN9YN&6=D0kq}sIH$M1moQyo8NRvcVfb}Rt6lT!OP0fnuz zycO1F!>L#odPMXb(2LrV(wUnORn@QC20|W-+B4IC+3c~d|0b%*Ws57)7E_2`y^pJa zb5yb!+K-1O_oH$Idj)&VYX{&Rv__8lhR?l+XmpfxO4STDoW$*&`kSt*f>Nh#MwR_blSdG`dnD)&FTJ|GkB zy9Ui)VKW|)s)5?k7OA_uiRUKgHm`WjOU?meSvL@8bWWJD^S1N2j370m6N09G#lyjH zFb|DaIXv;?0Q0U{{&fyZDyVO+>5^R?x$A(>iH3=vNsa{cu}R)2066IWrw!>4lZ%FLd)BFQjjWx=({flpB3-5JhiPaK&XfIgrfa%tkIdu0!6Q&g;-|ox%dxEihdvaUm45RbTnd~M-FvfQQE3QL5{$Js7H4t9BYhGFCu~~FK z-R?-^x!s&$eb5*jD$Mk&u#?_6GS)SY)RLk3so8s(ogI@N1jcTExfp`;Z$FTnV##>` zR1MCNrJC|Prs+J0gaI00HkvOfN+tIi2GN!u5FnU)O9y>QQg7n&^*@Aba@6x zmuYG19E30}XdDBwVw;k^YG`}4@=->GhlIM41hR`zmzq5$CvVsL!#0@=>UtaHC3v!I zFd%sbZ!iWk_iSzJT-yI^9~m34L#W$?NRX+-@7h2l)vFEx?`1bPZU1g) z>&lWjAw6TS*l2I-GtriW{M8WqxmC(HG?Rc3s2+y^!ro-s&(W81E#&muX2C!T2aY-fE0lh z%l(==9OY2i(`9#)%5`8WMvlDpm=~no%h`h0aDXun%rxZMhHc5(yG4-w+J?PKm}+>v z1PPd%YzT+c+2dGlN~05D*V#6*<`qwQiEGm{oPsoz+`}Du-|ll~rtZ+2kxxT^CNVF~>@M-C)UPrFSuaZW!%^770B^wn z34g+`5)&wDe)@c;Qvkb}zV-;EHsSrz)USXuREn9wl%F-H#4*j>0`hk(IjQqgPxrmA z!QEx0K27Uf8yNQEk`!5Eb@{AFD);Oe$IBf^M-u1b-M+e=_Tg$n>KR7<`t#zCE8?$3|^_IJ>h@B zuiOKPKweppIzS{Y|CsRPijk_n&QS-_r}4D z!D)pPN)D{-rz<>kE|RSz`xfQ;-}@k*UC!3ywO2L^foeh?}L%55$9&cDg;F*?mjH{FV#?^#D_wuZ8V_UQtzf#>`h+`#y48(+|;{< ze<`l~MojHHn>>lp(k9i%e`ez$F74({@LF#$&>2f9$D@f3e!bfq*c~@ zZ>PX@lyvHorjX01Oy-BXro#f95b3lQb-}$9_CiBD$BH`2ih4#^)SjbE++G1pB?@4s zF1WWN_iKW#i_K@h1fV1`YelD*C`n&q3+E?br00mzMcuhyqib(V&t5tN>bF?5%KJ7P%JYG?dWjg~ zT@W9+6fRj^RluT>5dn6cLCAQRI5l}9BuY&#?wEXqik4bF-EGyHe6`!E)iJqL{^=>h zQj^D|t{Rq}d2VXY@r$NI`If>`s4J>Cj8m!z|v%K39p(ivD+hRxqRY8iC!U(cFyta*=@oIyX+ z%uPCj!#)}oPI4)@#!V{(k!XGO>**C%K@lgl?LvICVL*$27OhAG3lE z#wvzls74V2Z0_eNIGrcoHxsY!hEg+g<0pY)^KXjFH%tew?ybQYmzlPGte1b=H+N$HO8p<1syC(#JpVBqrkd&~9x7f}eNjH!-@txZ%CzWsAGIkbO~Z`~ zwx{(G?Mofo{&Q5-=ty#V)bViq3%UO(ecQ8-^4Bn!j z{SLWJPfZy{N5cpsU3@MPCG4*u;W`z!z(4-$P^iP{;s7+D<4S9N9akF7+m_Po4yFIY zn%$1XWwwc7oKhD0of}En-&F$}Jb2)hgM+S5pDm!%ayzC46&JI8C_z0e<7TZxYFt94 zRd=a%Jr17hY=a5xbfK}6ohg_nYWK^WvM#`HnBz`bAG;7&D=^0&>l9ak(E8M{^wcqw z*bu$Y&>8PP0H$W0=zspFYOkv5?xyMfdIB76!qsx#G$X9c-(m3z1E`RI{b(xPOuxbb za~ozO>Ea^WFzXO3EzmT`)k8Hb65u_(fZ@?~>EdCOu3vX?DPk-DoP~OfK}7>z?vMEe z{T|94kaQOT>3t?$1Z0T4{y#Q2?)ow$OYQeF;F)@ogKMq22q7JA=heXKiqBYgXQzkV zo)bqfwPdy4e%6ctn%(>VN2y=!GB-s2!|dE1rp5^09Y;md zN$YqNG@N8@BY9R(aoYLWTeN7&z1+WxrN&@-fNP!`{_lws=Lqs$Pp0ha}T*3RFX3Po4`=a8$mVPqf@E_OEGtT z>}2h6)L^aLzxl^Tq^>gos`-`G9mgGqd5PC7!pmA$U}{6$uk2S`7M@Wa88f29Vovi& zfJM3gQGlg7`>`Ie5&^+;cFZnuO+m-Jnrm7#^ zlK!e>7yIb%&{uiGKFjY98cmUZBLsDgrp%vj-i3g$jrd-&od(o=kj?Y8>LwjGB&LgI z#*95|CZG>43xF2-CmSGFF@qh@Aa(MWnS9dw8WA0LantZe3Fc7Uh;|^t6;HQ-3<_)@S zjd{SQ*gk54I5k8*Vd=AXRv;S|O)}u$Pa0E)MVTTn+AT*ZE(%H^=G?&@>HSnXOY{?Q zWPjR%^Pfaf!V*?-*3JKdQd&7^&Q@@nU#^h%;ROkZR^WHs*SiF_9=QZT{iz=8?i}Iy zStSf`zFl@G@1U0XgACJN_-*0l41b?u^}XKa&(UX>5epwTZGdXzmq}8$nM@6}T z?j@YMxPOQ&sja2)VnBCa=;QK>P##c2L7K!!6;a6-ozQ*ZR=)9RJ#qae#f@c#({AE3 zB}azEXY~X>W5II3Qv0 zDG(!mKO!n#)e~o45QoJIE5xEf{#=UDk!J*eG+XkF0@=Gpq=&F8k2GeB1E|a&219QY z1;n21!MJNRL5m{YFK5cuZOK!v9C{SZ0Ew*=n;4Z_!n1xm1Dl#cfq%|d0J@rV;jqz- za*8ckAR(ZgwJ!)GfF8r0NlN1JQtc2~c%NGzAkOkX1warCVkBSnk8|BmP05Dj(@l!Qt#T4DbffK3%$xRH8u*E&FD z-&%@kfKu2t_qpZ|a_Qp9eM`yS8@80ZH+M_PLGRAl&uJN(M}B{;FR$YKM&F@#mi+e4 z=kI(vMB))4c2_RJe@i`Wm|%VTuBnkQf`z?AjeHqfU6sp#@lfy&)wwt7J2@K5W zx~t@ueQ@|Q9=&n!?<(2SCqfq{V3vMB8Hk!*H*G^{YKZs84RAvOUcrrtjLcfruT003*AOX z|7-?mPNGq1w17kL-}6<+a6i()znUDkIkIXpQP4{3?fwhQU(sLM@AtkajA7r>qn3B6{Tc3WjFd^|fN^{lj!E&UB z$lUNCQlR^Sb^c5111W3~ldSwPZdRcG2qAXIS4UovfbiFmH#BP-7TB_7%ADTZp1)Dv z5Pj3Geh^ye{Ih_wQ8v)spx_AxWySO9!Ge|^qA-{%mHRC7^wbs4=5||z;C?Yd(_J|J z7ZHq^Q=9$O8-D_NmWN)SF+4&hptd-<|H){G^4Qiq2tLZojFyb`X}^)z}7SwP_JZe_%yoQTha$Qkm&1N31!x ziftjQhELLGWja$teM*1LM#WW1YG7^Q;dB;F-*C}(>Kuy0t@|Q>j^Y_=2J)C*@%+yd z7WROYi9Xy7F5RVEsqF@NvO!&S3AZ7LdN0;DDoLxj#2}v)!|tx{3lCN4wP8pSEd)lqGRfwJU0~J zo-zxik#5TIe`Hz%X0{Kn5KixNtwvk(YOJOHqZSnNkD*Y9>!<)^l2`YI*;JoB8m)gN z8LEPVe859>d|^zPUpNwT13Gu`*vRd@aGOiLjhLnqVY=ex+&@Ec*PF$kL=);L7c+X@ zlMR<%vdrHYhP$)2#l4Fx%4r_IDjP>`?t%{8i30z8YLs0j;|<mX^ zP*6xWx$2hfGXJxv;(7>G=6^XPjP1KD_v^CZB2>A5YZ&ebwfe(^D)Y;;aU9{Mh3>>L zzAkY{J(-zcJY*PL9fq>UHTsZ5bh$s?`K7iaqxv4<#uC7TmRx{_1?cjE8|MztAJeMt2zEnriTkf=N$j$kURmoF3*NLa(yxk zcjRjSFuCUVXJ_L$a-9^q;j0}wF4mE`IN&RG*@47IvJspzYEbA#PYeZ_cUr0}v9y~a z+EO559SGT~_dI)r8qys97^GUz25mj<9g>mn261Lv=~GbuV9t`^Yu?vgp@|`D-q%H- ziNR~$*Cn6P)+aI7{qwdu$Nx5w#C`3FuMw4@5q%$e!x~0RT#9=Q$D@opo8O<5$afhf zuQP^t&1n;12j@ODbZZ|o3^O34d!opt3pagt{f^pR2f(byQ+QaKbQVT|?RD+ao;>5r za{mdZ3M9YjU>TJ4wC49GCW;>ZJC*24oh*9zZ5)}w55KDq=b7H)TN?K=eIzCok(mi? z!1JasPp(O8en*`adiXE8gDaWQ>vS#X*meh;A?Ev+B~Q*APaVk5$ejlY4D}$R#}?4! zG5#Y)vrM7kUFxq5NXXF1s%^?ssTWzRiQX}vyw)64)kRy%%`SLcab9E08;9^~jx<2$e*kR-VB+@X0d&6BbF==9oCXjjO%-NSF`H z;{U5O$;p;kOwGFwS^U*$mHV%wUh7ShzhvVh2e^z5-plsW#4{MrX5+Yq@<`~0CM&f; zqYq8m2@PoSQ>-Oywa%KE-E`5vJGO*UXX4Vs*0k+L-5j>Mz!33XsSi4MyPi1pc8Bd6`0%jaLV z9ZRj|88#pFL%ey*p3dH6c_So4K$f3n!&&=)b)F2vlbk7KcVTY<1)Q!_*p7jHPd2V2 z&)U#UfAq<}8+kN0SktZB?GgoRx^)Y7;>^tSp0>4&BmvD9%ev{sH!>f!vhFkVukQ(; z;leXz{;&24HdIYp>uX#4F7in7@s4d0Oh@eJL)rALK)|s0Z++KiU3t>OZJ78z#}As{ zADvwOullEXBy;`Kqs=7BCsE?0%-D6LqknqfZP0-Jg_%=by=6PFZ@*(5SX&SwW_>1Q zIdD$m?&brd6Ki|KYL5&FdE*9@Zvk&4KLTGA<96`lKck+yHab2@Uub3d;A32p_rb@x z|L%hkiIdiRplihw(KR1vts&Z)lTG`t#>{_IZ_mhxTfh=`H3M~-)y&E-_hqcRoF0=N zTQZ2Zjk4jVntM?go^)s2h49;|jQxVCHaW*XJsSr(g*(uVYNh!k+dOHGzch45Th9aqwWnRZ+f&zgv8!7r z{$x*F4bd&Ti+lWbJ3qY3{44NQ-VkVlteaDvsh7vT@b3Q9rkPzn5yP^+8o`DX*Aa{t=i*-9`Nsq(%Qa`zzr8D&2;4Ee27 zl(}IP_fhSk`PpGC+cRZ}_n?-1my;2-N~o71z-P@tJ>ig?_fJu$+h`Xjhg5hDiD3{I z0Li$j%)iofo*K}vVoLcLwS{@Y;U3~zxko1J|3xMn#@mEGn@zQ{u^wQQJ4d)i0H;Y@ znZD;Jx`0$?*Jz8=cDpB`av*0((VByL;DRpdV1Kbm>wB1fJ}dLaSa~j9|LEFZ;LmNu z6W`MPprE_K)C~=}i&l2sOOW|7vI>0tH#5MOc2cS$?NYmqNN!h0BQ}etV=OtW(c

zOU!lYA?FfZ%H!nKFq5G$NgM1FLmv4&MVusDlgB>tIqZ77;E^w3nH6ux>@})G!-A41 zZWzS6`jO<(m1NVQK%D(`I0E=;c& znl6cr-M`Uz04-pLyIthnjzS8^{bhgtE7z`)dQVIfMB0LLt~(1J8!jDIYOvHBPn6lu~qn%$|Ovu1X`Xu7V<*}!nN81;5!efRE_M#JVw(gAy>@1E1EeQEUB zq8lrm5=Dn=lDet4yNJfHGd|uzm%3NUmRk?o( z$+(QeD|R(sx@eVuJz4nw%kmL3@NPto_73rW;9>d>wyRk+mlUQ3U(H^+)Q~GMH%`as z$ScJJE;SX;+G?@M#k&z%zh&6u>d3ndQw-gaw>lfzf=#ZDymeW>JF~XCvB}ku_XSLA z6M4ni(Eko>8^-J$kUwiCca+DlaG_fF)=-~6wmsy>BJEV^PUiaup@yYM7sqTHSoei0 zn?HZH=*?RhmVLBEmy)2HA1-HlYW_xjn?EzgON>dEjX^d{9RonlKi=k;h>+x;GDYdK z0)?ShCagIOD}XA| zC}I~S0!r7LmB#OPoF-Nf{p_XkF+9C_Uh-p4JWg28Gpo^7^%dH2`2}UlCe$zS?fMp; z8&utZJSNpp-1S8~)X%Pv*6s3@Q+3eucKpDPOFPvye*@2P*?SQ)oKUa~cyoU+8hN7GUDVQ*|h-Jwec;73*n^noT z6eb>3&ISHdm$NuHRT$(s#9WQJYEHZv^|B)-GkPcK#3<=({l?VPd@+t2Gt1tN(F%9xrF;aT5hCJqXGI>xBX(HoSe8tXN+i!?RzsvS2e!Kp-Cnyk{=H`&_y}%!GB@j(L|1Rg7<`ye0QIC3{T!u z&oWlp8ba#THGiTh?p^Z+#EPco9PL9GHDC52G1H3rHYb_-_EqgDyN$Bv*ovlUj3i&K> z%0Q|E*jLJahCwOjGWSfR(cXQ~D(D>lkMy15LXdwed`ZXElUoBruFzoNoLo3(*-|)X zYA#Qp4OM^WJS*k7nWxrZrm|eVj-gBfz|W@BJXgzqt{VX76~nYFHn90U+R1T@jyp=| zM(D5(;vP+9<0dyRwc^kkIzrlVR8%b$kerfU|gx7i_crkO|X^lKbF)w#E{^&yLTpOFgY8 zj*If2KWMFK%|S8x%HxPOI_<65EauO=Nm=n22J+f)7M`Y>HnE7?4 zSEV$h4n;0!D7xm-BG(zau)n_RT3l9d(y(w2m8ZwgOR^Dy0ewmS>hb3#{>~OcULAMi zR30Kv57Fzl?p^WY)=ecSu`>HU`Cd8efw!ffXF-+G$4{`=&G%nX8i^%+gM7i|TqONn?yx+zJ$qnk(ukbH! zr24jOxLdvBnBXi%+qC?R^6)QNLg2Kb)XJf5Tr8&Um{yF*XPEnF$DZW1b`o9^(-lQ_ zNTvMTj%g#s^c~a2C}P{RF{x=61Y4zp#~G)Mw~+Gjsq%^1=erm+@9jAx;(ofWUe;)9a=On-fd;N`Y0)?ucWmMwk8q-n7w@$N*YpygAe4y&i9G>!r16gy#v1 znaTUtPdECO$E(3(PMJR)$s3AI@>{d#Tu5R^7Y@;6sCF|Wm7pn?mvujczz-Gsr^J?Q(P?qsrlT+T zjgZ--uzM{`r}3hol^&w;RcieKFtd>-afhcHi=TLjxYjLMrSVuD=jU53)?+g15Tr0m zTf+2|ku;Y?bg3$dSB)9_aR1IRKc1QyNIn0!ER*x&8PrGG(swr$w>>89;T->??ye07 zWX-LPX~)kwyiDDVL*qMy`m2Z+N*-n!+q5gURDpX4%-lc;Ka@23_>){^DTEd8JuANf zf%;rOZvhRl?uMc9W8Nl%6}>a)ZXBjWCn=!HC2}cXMn?*UO05TJbsIFFrRbk_)KvfM z=rSvyEZg;toiL>+={Gy#>AoboARuQaI2qO!4|QLt8F7f$(0G;d)`*45q+JiiD{#)bEvTo5i!~-7D*46s>6t&5*Zkoq#BL|l%_fk=d7T7cQ6PN^Z%RWn`6;6@BKe1-)SyY@A3_o9wsPA;%cf%`?S{k z;2o5qRd(*`qtba?LFG9@9ZicrDf(?E|S(f|aFDQHi;f`~L&m&tR zGWXL)(WdC~XgajaRA-E>&;(f2ffT63l4pN8mE+g93?% zCql8|2tu(m6rG_^yuyuHTpQGp#%Rk&@Zt%_!qobGP(d||xVb_o9Scf9Yi%g732N#f zw;1(ryQdq9ta;t|;lQY^k9t((s3+TUPYs&HRl`!-Cp^6}H}&kOgWPaeUNq|9gzYPH zQrk_cSvKvtrER&F@J9PB8W?I9-@6@x%GLR;iohXZ`(C=TNS!76=V63KI(Sjp^wO=j zKm?oXrk))2K6)KcSea*-9G1zYWKv+6^o1-=3c8136FOG#mYwqTl0R_F`Ja$QQA`N; z5vflgQi&74S~Pl7&HEcqlk!7%tkBh$4NGn9p30kq5bbsqZ-mk8Zrj7krd23+rUf8pbbpW15qH6J*2WlrSzD<`~r+aFUF1$4>+ zEq4JBxg!9A_j>ozF2=IGf$>?Yf`tIfoVIR*z~^c0d!uYXY2LMplWmG}1yMTkG z`~B~^`IpWuh_?I~?^GwxR1PIbmJi8C|)6~)k`#q?3Yb>2V5JM$U&@wP=l z{JAhM@dHR^YAHv#LY@yp-k#_}W(jwN>I7tYX*>%3{DbNP*}%<1tUYTrI>tDopm~xe44fET&4n~4u8Te%Ne|hB zGJOu^Fg5*1HJxExx#^aD>k?ErrlhcV- znB=R0=mK_DKNQ}zxS|k+qwbjt)kBACDyN&5G~ z3Dcy1-|tjps}E0Lq{$qEeu?WBg!xcrDBOHzBQ~8PJH?@o!e(b?j`&jxFVD_H?$K`d zv16_G5N@XbphCEbj;nH}YDl9702qMO*G8g;Sj+3%OSDyyPIR z&MD@hU;LXVX?E@cDq(G^dm5%ng71jh#_F|o5o9~2E-|X4|R}8+mDU-kE zb*TV12)I(e+EJ8yD2p zFZJph8{!ppqiZYXSJyUqiz_M{>qj?L*Dh$RUJ$q%DjF*mH-+FxU)@+!8LO=f4)s3+PaAISYO$+|Q1c!ZHMzM<8`nu{^eO;`!rmngvwzMV@uTLgoiN=Z= zd=|#$U2?WpxxBKLoD8R!a2gF#)s5A4mDO2v4ukGFoMV+0wY3gvY-wXX@apQ%i`6fP z1!cMErfX+kS33K;o2FemYsTd3Zn|mG2(IWH(R4{{M3cAlLoj=LBbe+6H-Pto8vN#sXgZs5-v|{cHlnuboDo&P8{{pW-wQx}L!yRa&l^3W^6Xe+^)1Po zM#>N6DjF9;+PXxqxJR-k>l&*o>lfD5G*wq+bFXh)T#>N+W20lqrs~+}_=4Di`o>rV z^lj<`va+JCu0G+A&th$Hs~a0hvADXasbb;L37pOUR`Rc^o}XN(#M$hXX-JbE?_LE- z3i>6nx{9X7u^UDgLxQFTSgG1bI2SJnn@k8ZIjj@_m%Y}?Vj+WKz5Z@+ByBqHyz>-o z^jrf~SFyO-qJfZQHoB2CLJ!VwQWezHEvO%4QAQ_vz)fyys$Q%buBnTaRn}ZrT^WyE zH@R#E48ORcB2lBD#r0JV_UMH@39qcKt8Szr1Vj;Zk;UaC_N}f=Kr-ihp3AqoCwW6- zbwgu4oZUpLs9hc#xwNq+0cQlngx{JHRXAevmy^SSieznKlmk-H1Ei|H?(9UY7pRdH zVQ~aBNHC)(!NL&f85K8I8#`20!`4-_u^MGw7vvhysbr$!T&DDm)m3nAWg^y>ZPYLn z$D!8LlhZ$m?+O-V(Tk$huBkaDv)U54(bGbPiv?7L%Pr1A2@Xf!0N5ucQe|<&x1y?w zW`+Pr#KjuIGZ9xUSJo!09QRqEL%g)7pipyk5K91h3U|dslT4T0FlpkFirQrLWphRO z(NvC!v zO|d5Aa&48weWHRUK`U5XQCDSR+ey=EWPj7Suu65TfnGqu@4Taf_Xa_$n!_YllWHwS zW3QkXBjHHFW_UT;~FB&l|n;Y%eRTt*_|S@nm!Ruw`*Qbzoh&YP6;<+q*S2R9Dt4sHv`E z(dNH$^9#TD|IKd~u*2Wc^2q(aocG=9d&;7`Z^Nx`=@)YI=kb$0#N}{%=$=QKtxD4i z)_(`~p?n7q`iQ5x^%^}jW>|M|HMCxScnusjzUb2$-3X(u{wURApqi=|Y7{}Ahmg~V zgrQFYX&sIk4$tp!cMVN1p?YqNRWGB;)n`>K(D<(8`s+$&U2}N+!`+r;O_SwX5j4+m zXd|I}!<0{4S2p+XR6Xva=YQqZ*G`#ybx+JA+m4=o>a{awT>CHa51Ud`&8^k3EYCyn zm`jgHs;p&1td@5q45*#|r%4T5Fg}wcs;jSK#9LcmS&^_YC-nh4*x03_DK>dZ*|k^C zzOE#O9FTW_%+bq#Mah)eS7t>;(7D8r#guK%%I9ERk5b!bQQ}?CKB;*8fEF*n@<^MG%!+$C6?A79{+H6 znBMV`7%XY?h<`VImZ%>hpy=?gp@jJ#PX2!{wdehd`pJSB=Y=`-5WhE>uK!AI{!jSr z`tRKQ@%QECpZV3?{4aeiH-Gy5x%sgTx%qp)nVWybw{r6v__g!f#c$%bbMyD`yZC## z`GK79npEGga`iIWc%3)DCeh?AtgWA4QR}I%C!}J2Q+;hRQSDiu=LL-8X;6Jh%wy8T zR0m7okFBAiuBMW2VtE51$PK>ZXB$Jrt7{vwUHRcvYwpA3U#|{GlEt&h6=pEG`Y?!p zDqM+v`200SA6r$=P(xyJK}|vxaQ?WM(c#0;JEXG$7#$+4OKv$8u!0|5kfl>a`@F%FGMyiVK7$TWWxiY&{$D% zlg%f*vdNQevK@;j7gooZl&G_4@|G=Le6fs+WLzlY0vYGa7$;+_4EC5eUd-b-_)ufePL>TdPwn!LIOuMT@{H9xOz zA)kfN*sH7b>gMyAPdngK;Sr(MBY2@#?NxdN&G!hX@Rp%qfxh*P-m=*MU#;S(Jva328EA?xjl$go|&S_9Z zHYA(k3zoW1mHU`k;ruF`UxoQ$Sp6-Pr`f7*32pNgUw-jyXgnJlS15Jj%p|zWl>}dX z17}l>^A3E;gD}NttW`i`EqP(ezfss>%3f=swH8`yq129oE2@;Av}}pWc#n<79D35G zv(__5WT*^YgoMGRXq|SY6-DhF7eUpaf;$*Eb z(I**v8<$o(kH)3IQAnfcK&x2XbhF^q)WOU8h)jzsmYJ(!nR6{Pzp5(HoC&;3OH|rh zL(Mqhy8t3m1br}#$=tU_rC$Iy)QBR^68PW*5t%i0GLb0_3n~{kEKCGnWQyF?)W`xg ze9TIUv0z*cc4WV@XI77b$!oB5xa~`@eVu>xEzZCC7Uy4m3;q>LR47bi55DGCEwio) zbTBa}vYEz9xLjn^BF@`*32*TdAD2S*%9}~yEKNNYfYGIqR%Vr%^JPk*+=PMDOz=Z` zRxk7*4b2FXAd!ixx^O2s z0&jy-;etFd1d$k0V8RY&n!V{}%cd6bCq!$TYQ5U}`i5K0q#uw2p|6iKv5IaotIV8_ zSy6?I9XI}>(CXDnEYiRd9x4wEI=EViyIQ(AlsEh;7-?gAwe)ATRZh$@yYOly<`yk( z@D|bc-Rdop!O%Rh)XXX~J$j4UhK2gzf#{WSzKpRl#+Vfi19pC3f}x01F#0U|8h!YA zHL8-Ds+uKUO{Kcn8ud=`+Jv`YdF{Am4P)KcTL6<*RN}j=NoX%v)<{>;$d~SP!Lo|Q z-U9VS4GqE9eQE+{jdOYn5(r>xU<6n@lj-buh@mj$W;C=!pGxz=MpuIg&h;86fcJu? z>O=$Cs&4}yhgE=7V_lWXy`X_L3e3i8#u)a&WIBZ(%NNRwk7dMHIn_BRV%!BN-{?da z)K%AkJ@6QmEI?gYz06ZvCxYmadTcuoT z>9{c%Oga+iBZmqueLea?WtmR-d4QkH;#Z=wtVWz-XkBAy$!SP_skv>7@^u%~gV3}!MPsq`pw)qJn20-uTs zuX1S>qc0?T<&p%$lW`PLwuYv0R1dbSS5wV6K;e@OLiPi;vLT5)R-qNVxIv?}@$*C5 z1+?wJQ{QA=J);JTXI7yPoom`^(gM^mP?skgLscI zePW@MIaS@l(GB$o73sol>GSZU<~~Z?OPC(A;D=%?oYq&y(ITN!0FXwlIyvR#@U*dbY_k4R~&F!ao zTlG2FYmcnH{W$OW$Pj!YLr(T0MY!4{&9@I$41J#86ggqKx7Ex|k>jT;__)am#cYoh zPBw_E9mLfJakU`k31S`)a~;Ih4k8~Q_A`i>n<6;|F=7xg+oO}cZ8_2F338tu&fz{n zzQtwLVp+8)s}ag-1X-QwvTAWz@gb`-EGx`Sk<%@!(=02@_DF29mlK^$keNBr>&%MT z9;u{Unwl< z5li5g6GqDMTo@jq#l?t(F(N?>JY0-O03$byksHLo!^OxAV)PGV^bca-;bQa;V&sJ} z@`4z6xEOgsi~(Vc0YMBrT#NxO#_>Uf>o*p^`;g+*)FTX!{kd|Eb)9SYr{&>afhq0k))-QhwzWy9D$P=;)siq}az z^1fYp->wvU6%XSz*aQz<%0LA++gYxZ(p-3DUa{PuewXQfe0Mc(LZowzM=_uFa;U=`NR>lLb3iI*n<)Q^ zO0rEjZKJMV+a<5HguTP>0KdQUdz;@O1%PJGS4few?H_>H&G!R-Tu89(pa<~`p31ll zBj+oEig|~ERCzm;%PT7Mwr1#}ynsd}bPj~}o%t9$^Ht8BB1dP7(DoH7L$;knAyic8 zgif#G%-OaZ@Jj!R((h2*9g6#!Y_G}oifpf7%h@iH{n3kT8~8LvJ|x-p3^+s|fJ~So z^FDrmn~M?6*iXik9r;`{{d9e9o_?&l`I_k; z(MK+Ib3bt193M5?Rs*Sm>~96wTL5{>i|oPrNBSojk=^Q`BHgR4<%rsWrV zky>IdCgNf*^6Mfm@|+j>4Q!mRVno)`@%)zX-x99h8zXVZ09uPdYq9RE#e58t?pE^= zDsNf`_oj7lZ(0ZUrgd;#>fmJE8o~O4SznMfk{RhmzGh`)2%?UikH~qui1AD7voNu@ znH@9ojGRxI6I0~*iA%~yMNrb5=ue#=ANh%IqERtcG;)WR6CJ>heTUxz=kJ5m_q}H# zuaESemhr5NXCi-)6XRJK&qQ{~iSeuq!SCnb^O5UE&c#RhAY!8LPM1Wz$w^c`h*CM+ zhmg50gb!YFxDRyhaKpF`8^&$XFfRY$)2O+JPxkU3#I-4sR&FvkMeZX1_DD+IjLi1P zof=J@rH02GtArcd}PCLZ_`#YBlizi zUZ1tRFv;d_8|d6^{Rwum#GVr!C7>gX&{&}c_MGTSurV_yS_h_P=0q8~=0s1lppz`_ ziRK~Wc=J8Md@Wk3e9sZ^Kg(EU;g~tmdIN|V`8qZD4Uv#>FlHfGIEUzoYb&9upeI~C zJ?`p>4^==COeJv+^}x6k{b%m;kc-ZT(!Xo`k4d{jj7I;%kiaA-+1*DGZQO@R#AYwD z&Jx?`@LkEb{V*s4w>8wMJ~n<^L%l`@;}aRo_^kjJBvts5%Uo)#S zOU=GZ-eyFnN1hPZgx@z5Vn)JZV&+7bm=!Z8nlvkBPPEFbm^sk}X2r~jR+|+wC;H3j z$72E+W)Hshc_45;;6lF|IKS$g4+hQ$opW8_T<4tk2hRJQ^Xq~0>(2Rw!1)E|{7K;a ziF1B2aDLG_zZp2c>6{M*&WD`yTY>Xi&UsJZyvI4e95}!1oZk(c-*wKxfz!TE85Lwg zgd0VdzZ;1#bE31%>de2$1A}O<%8G&YO<6IpZkN@J-^(`FJTZ-^KT`~7ZQtGUG~&B))@?ys2;pVDDGE046F@C8D};!6U>ReZT^@!(I)eF$2>4| zqPLjG-^>FuC)&saG$;DHd0-O5JpN!Fn8dhUFPV z{Xc8%z2>a5&tx*{`@Y}r`@aAD@?`eRGwa!FUuN$;mp$io4&r~#;Ey?o|2cyfaS;D= z2A|47{LdNO#zFkg89bkZ_@6U)0SECvXK*72@&ARyA|IK&XfH2u>L9NGMN>#+^B=yT z!2cJLvr#s)Q6BSg?0g(LAK@Diz5(GIAoUlP!he`;Kw7bSk=w-=xS^z7X#21W|FLU* zVm5RH+s0_hA}tBw2Sn31G}JyJpc!OeW&hI5S-F1%oME*(z0 z$ci_x3s%?zD++Gry0{#zdd}dlV@x^tE=ubhlUA&dNZK%~#CO>-)Gmm>$V0LhxRcs| zT@(dxU>Bmm9z;RG%@`ZM!iIbcB=I7~rSOdhsvG$32uyLk_->Gx!c1wArk%b^GK!c$3!fcmv;sNxX=GCw%3hDD9$j^9FXo zee8kz6x@t|P`TS^(h6H^tR}5<20vvQLt2p&=fZ06U@CLvb72i}98|1RXs50EuKU>&Xk=U!lP?*h)f3n=$WDECT`d&MUAE-<-=6>{$| z&OQ9!kT{fc4cv6`Y_Avw{oDa8Sk}6eow$fy$Nvq93vonp6`CQ8zqZ2~NW4l$=U#XKW#PFO zauHleMKBtB5~Gm;m8J+TG(~_FG)J)}{%=TBaIEDVEB>!flu^n~Go5-U3eB?Zd^C|HAPJj4`NQ+ zb?dn`w0pjJwuv{foHxn%#Vvk^ENvYU3bRkOv@E8%5OE~5eeeS9v{^^`OBc}`A$nzu zrzy}zm^VC~B85i~&3JhX6QUM%clNd}@)ve@F5z4G^rF2d&k$6W`1D#v+cFPNsLji% z<~3A$t1Wno70{Uj6ka3V zjFM7mS-8-=pX5fj!dgJv z1L=op{@;Dsh9MG%(8P2gVx_5;2MPv;KV6674wI@_>ckUp!^p#^PcG+FJ_MScw0NrD|5eYUcPTx*3{C1 z2j%>V0A3-W9zT@fMD*ev=K&Pxd4InOMmd-W%ySQpoIHn~tec50!F-8yp6L+3Z$Kjw z^Op3fy-T`$dW8+|u>Dr3^)*>w3kAQm)nE$8neA)(XH`KHK_$td0-;A&u z$Hmwu(C58`Wh50enKBOM!H*f1wW5*1^^3O}alCG^9_yQdwQ9Y}a@W{>bUf`NJOYpn zail@}5Ka?dVw2CD1Xhmh2ZzIbL*iyza3SpSy1${oA+YC3pGoe-FzL zAH}&6I1{)5SOJg^S7N>Fum5|#P@EGHAH_KzI0{$=)C0t=z`7mSWVipf@@Wm?+YGD+ z)&g6AM*xcdHLRuX$5~_k;UP2;3Kx1jrH?OC>Ebu&-%`t$Ea+@E`!TDZC$pyq9P0YU zP&8Q^QyB5}2KvN^zn}$^qv=9&Ir?jScO*@ji_n4W8)*_gE>1Bs4P%7vHkui!)0JUQ zGc{Xm^xAER*g0<6l*8(<@xGaInw}NuFX>HTT6b3$UQm>jSOZQhPq@mG%-CUa0dv^( z^;vMEpb=N=J&oNw;GmiG8K%5p>>K6tDKrxv^R(srDU>y!{3UIzi}0xk9+>bQg+M4{ z{1Qye)puL!XB<1N&g1{-w+Lx?WoMQJQlSBzESlMto=;BiBJw>7+-|^kSa9u|c_k{D z5Got&?C1ST%))EJE2syP=#=Y(`p0X18Jg9f|TKtAYn6cXY%)V=&KLS-MEtM zMoUR|g>d7RTHP+XZAo{1m11V_#5wh-CzGzfW^aoHR_TDUr%4oT_}WMcU+m#;EszF%^o1|m%)DnbLAKDW zgtE_yUoN+)?XX`ap?Zf~dGkwqFo%mK_=Y7lJ;B)Kid<>>3mV~Ea4}0KW;}Z{TN|CK zvZY+YEC@`+i&}blR*T6N-2A1xi}w6B4QEk`nj<=o$NOirbmN8h)(ko8pZ&r~FmqZG zM*TY9Z-#HSXQY!U-Q;9^lf*eP?0$Ggw2nxo5r{;}m?V3`g=eHBiu0eQaS%K6z#36{9Lgj~QDv4st=4O0|Mb`K^CCC8Xic zj#TZ5u*cVnI+vn%K*L5KO6cs)EEyxB?PtxI?%VJ8U?>noUu3?h*3dxTBWajggAZCX zH2CFS5n4^Aym`>}i^{*|6}6dTX}kQe(vD8|b7IPK6D+c$zJ`XnX;blKHGiJ1PCggG z*QfxqjMR>WxG{rI9Ca`8rKX|D!N-eQN?S|)npt&zDZax|?3dP^REI0H?4`7{wX>(I z$>TMB1&IUr--QWnrKPBo*>ypyeA)V`zTcsS5PGPAL6JQ(s0;CY%#7G6dy>a#pKszej|NvAf(wbLwD}F)CbCR1oZt9`qEGO{9TC8 z`}N{kg=*62dsEs-h0{;n_!^=SR&D0-gBfv4+G%iskxeSyf*FzdQgHNjJieEQrihN> zFXdtEPXpLYDch>sdZv5{3r4l?pR<4YLj8k^|MT@v+`QxKoL{p2#)l6Z=1e}ZW^%p# z5JV@MH2d+!nX_=xP7lkq^gdIw`fL8Bhs^HRL_ycj{#2+Fp%37op~G-OEX_J2etWXv z!+FiU=*OsP%$`c$%rQ52XV=!JtC#J9GVHUuFRqa)YCKKrZp8O6&24thyJ@u*lWXQ= zI;FNU^d0}SZ_{UG_!b&bB}G))sT$_~n(nj%1Gc}7Xc;nE3De;4!)o*R zw)9M?s~LGDt|+j!4NZnb#^G5TrX$YU9qgDo>&PReXXT5g6h`q&@F_%|!dB%6)8_E8 zPP~ZFLDw7@qVU;4V=yxUq8^?axIi`t(9FH&MqE&FL|GL;wTjdNnvswmEev2Uon3m+ zU`7&c_Sz_8tPnV*0=obHpB+D_NLBE}whny$##UTTMUV?L&|T1i7dUKlF{aYI-oX!k za4QC*JT<^lnmQO{P)|>H+X8%62s0wh2%K&*(fy?0^ICNN%i+P$P(}sj3wv4R_dh=V z486YLx|DHslOFKu#3QWQ|E&HaPX8nGJEcvcI|t@7fOK_ZDm7oYIq}M-ia)gfQP)No zQqUKTGB1z@>VK#W&elj@NqpJcF&7T^>wZaH* zDYa%9V#l`O3)iX6g+0E>sSv4*<6~^ZzU1KMG~}97#~}?~x&tY~4NdcK+qnS5*G4+= z8LCdRZdr!UA#`-|%6#jqqtmQ0JZk0dnRRsXs+6vd@qq=eG_?rL2}b7#Eni~RW?Ord z8CLCw-26vv;uo24JHhmq!M7(v`hy^SU$FiEU%x)fOg=t-W#-q*sh-*XPOClA-Zyj1 zg3WZf@>>M>-Z{P~Kn-oWkn!{pUuDGQIzH4M*hwIUea2ma&v|({;PvJI)7OWp{(YhT zQ`!H&vj3wR)?fE0buyy+@sz!DbrR?5$~$N$RX#tN63*V|3q<@&7k;pIYC^ zpNOlsQuL>ue9^fcw+L~Sw3OZ`nruJ6-t8BqymOHDL;@czkR|id&fYj1)=*UL4=cj$ zxPETaiFNpT!2T7#qY!Rs_QFSu|3i93+rjend+41vV~<;G^Z>KpD86j_J!{I*GK!&2 zvEQ3jI7iI=C3TO?Gq*fzrXAV;ZI0;nonkl7Mfj64{&wDYC#Cq|iuBV#jL4mvX>^Io z!xO%sq0iemiy3pz2XlzOxMexN3%8^Z&raw^0dN-=51-|=c=smv_U6Mmj-az?D>dEY zu=m$OzAbE&OXT^wd?%FO6?gR9P2<1)uxLs4Lo)hN0i=YIv7CmSZX#SgcU!gJU#R`( zXG!Lhy5^Pw8XbHrlfD9mhgRlB&k=5IgC#>}Xc&eJcdG^WXh4hps;7-riN z;5(erW`PH3F}X;`&#pA%sT?vAkFJ;b{JA8X@%Fw|RDTc%+rWGbs)O&?o2s6DA30=Z zhg|T&zwy4kF_6(8VRAxmmyetCI4#Ybh7`UNj2GRT7Pa7OO|oRR4>kejrB9qqaL#We2%!u4M{WVsodYN zcYsjc!tZeK%|&~iP4}|8aQ%)S62Zqo7vT4AaBGV{!;EGX*@W{JpR~e%T-MN|67R^` z$@N|Z#Ssw zXIB579=qbsPStoHUejm#T76UuIE{pPUTk}M2?_O0jlpe0GyYCHYid9d zK4fOUgdKGWmwErr8XO`m3(bEr)gtV{oX&r)pt$anuT10p4}L4C5x=*D!XA(NwfNK_ zY81*Fzul6ecWdZl?DQR7KEhm7n2LaVr%Ul|M-Ny3E#3IAE+&*Lp{Mh1;bD8eVek_i z@+o-q6ZTh%Y*%W&eoZfkwJqqT=lc9^3tqDz#rb9(YHuiWxQA1ZzlDx#R(|e<1TI0w zn#|_ZQx`s;cH3*Cj*{RJW{Bf$QkA5>Hg?2`YL92&*fNlsmYCbe)FZ=oV7Q*=1pU{BVI5&>fZjVVkV>F)w`z`O7C z{1WYy{C=4;IOem{iO<~(z5mWmW!!&v&4TSOJARC^m$N(S{UBu@djFx{_mkqi-h=#2 z%YKpfd%o=b`N;Yq8RQN~LvM2PW7bfHpNq;wrt}!v%y>mVoq1jT`7WaeY=0<$L2b$o z*yr1HmJG+UDy--wI*joBveHqRx2&^`v1d*V9)M>5EL3o8cQZW{v%m4fw+QXMVY(TN zQ6qk>CzZYc9bVL2%zq=I-+Bq;5&xIFzr_B3i3Z}!wh#7tQawgA`D4527K|EuQ#9r@ zmjda8+mJdxv#u}Y^+Q}((4^eZB|X>=O3A$*q$2FMu?lV9A}uoAFwfq&e$Xs(dduFv z2re%}rr*`iv@}~W&i~MJQeKK6SNrQ8BuC`*r)Tsb?^p2YZO4{gDFpi+;i$oej79Zu zL-y$b$AITIe!+sG>~EQ)evqkVIYz$th0!&IIC7;bBgqZDvO|Th%FYH8ff`@0Ve18T% zWk~ZL^gD$8Wlv`RPK}8;!@mYJ9KSu-uPGC9IL^b*b^R==9W6_PC`}`PCQ+tGun(M( za(LDnA85c03Hrf9e%ZOX1fy^KSOC6}za-G*7gF%ai{_BD!2bq*AUAvjE}Zb<9L<*P zY!061&@DgyzIA3pXI{)>|Ds1hnP!=9>P1_cq*9$iXB4}A#Qj2<4 zdX~{z4zow$w+pb-9%B!|9!XRiMl^Vv2QP2n*P)OO1n4)P`DG5XDKCI?$IAQL5FdUS z9KN^U9tyij0rryv>0Rl4#x17VGaE7*bTh<;*hM1K2Ep-^7NUZqgM&R=2fZTvs05nR zB1snRz0s%tQ38_TaFpz!f;ec!8~AkzYQ*lLQm`Eg?hZ|ZfJgHgJEQ5ifl7ekg(!ofKvhw#m=1%7!+h1}Xfcb38q^CJxY z@L|JBhK=wK_Jo$MlZ*Ek+h}sF4|D`rS0VSASJRRJ@q3~fG0bs=_IbpN~m_m%xMh`YR8c?YBP86 z9F}8e%$zj`b4|uosY4Aj`DkX!%*pRhnKk|RIyGa*_YU-mifA+)a)1J07hq4I z5TLKs@8b=_6qV|t_TEwt`HbHwv_BDo(I{rJ;=@pQOwx(@%y>vNaiTYAk~eZBy!Q@2 z+?zPbI{^O=_a+_g9el8N$|>HNXL>Xq98b3V)S3G-ddrADz?Sv9!-$@jer))mEpn*6 z<@A>JBKl!&bRXTGfAaRe@A-JSL6-FV4@{=)z&okx_ti<;`?`0QS1dI?U(ka++`z`0XsICS{GfrK0N@85!>rQ#<`e;RsU9=IWZto3nm!dgp?*ZV|Q)|Az~9gFc^CqBo}e?B`UlDUcc z9Smv@!FK{sCs0}VJ&p8v#ZQ*;?F9UuDSn#`-webrC)p*_ULKaRJzc%x{40W8S{WN$ z-P6<0MJaq;XMR1J2c}3Q*Cg^#bb~4tZk`o?;F)rOe@lvgRm%Lfl=<~3^OICF?Bn0G z9Y2P2QkC|iNO~_cinzORSm;dw1w2a5obR2sG$9;l`>b^P z-)O%4$&b1F*AL7hV}L%5?6kOa(CH4wbxLjbAHR`}j2t?MA1z1w|3LgkHg5c%cU&S_ z5Rv}Qt^rGz(~k@GuwjwBX<>#(7}A)o7!Q;Ao2j-DYFl`SxDvYV-#@zCOgo5j;2q;J z&iOnMMCj8+ZDs_#Cp3n(Q0K7|eifm?$0P~lkz@&98Bhk`PB2mZ8E4uD!!T=QU;KzL z?$l$4)oJL8413*5#2*@`IsTV7jj{M`d5^)+LTZ_wbGIBiH3WaVY6=1 z=?phR-;bXdra4v1-o*EO{*j-2>8*Txw=O@q`j1~6XKuxJfq*yOH`x3ad^6||cxMT^ z6bI>h(Ep;SeizqMzc)H_Kgv(8+LE87eV@FOpIrAgzBTkge)435%l@37T=W~@Lvw7p z3Bs8t)q`7w$e|f$qNxZ$g`>MJ_BA*9b{RS>`t%G!xLY2&WFCX_K0R{^?Nv)Ren1`X z$Tc+B8$}Hb_7;+enfS@spm~>5jG9uMesW~^+Sqfn{MvY`*vBkpZi?_8CP^SgLGn^w z(P8+)$9NBy2IDdC_0^q{aQ$@uW$&NRr-%+9DSa-~=6SO_XkVX{tlYMjt7WZIyK4`e_v{xNvKY5SewCCU4 zwVhQu1M!?ByA>@O)86cRMP*g(bMcufx*b=9f7p|nSkyep^Re*#rltM3;N%~DuZ9XG zor5LbMBE9%-EhP($(x8X7q96cfL!aD6ny{3%um2H5o&|YM@Q_7Mm$}DZ;XU`KqhLA zMyeBEbVCQ#N|`|)-cP^Li%+Ad_wz+;{+W3Dp12MEcH~QJ8u|X}o+w4)^ie@Wpz3D-kn3aE^487}t%fq5o5h+Aufwi{}7- z9vr`Hjwa;uNd#u_lqRc(`bIm`^^1pRJc|W)`O;~#FIu|gB7*bJ{=E4smS&xfznMN2 zh_ONN-D>`tm}gF4Y0Ksh!;onh{@Hi8)APMEWrHo;#>kwBf)*ovuc?IZ1LH+xyoRhk z0~);GjQJ00Hwkfjh33RIBAB^A9?HGQl)BsFd0Wa0k{1Iv024+T&_04Vh(;bymzw=< z`od)i&3%!|MrSJCo{|ImS!cdK;l6e;(CoF(`Td5F`DS>A!@tih=YG(i@h^?fm^N*i zOfU;i0QHOmzug>eOMB6ZnVJ9G1ybW?=P1aWf2a6yKCn~foi5L->+J2ur*_a0(3@)V zUJyQ$hH3lsBkvjcONW?y$f!kaEiEkrOx}Tim^|2uTg0wD+Dh}-sQ;81rp~sh5NN~` z%XTL@1NxESzZBBvNQ25OnxJK7yV)sP_%a239A8xBrHz(unzdmY3?V=7`%eSTAJQ|2 z`1x%3ES4bti1|Nq4zdi5dTk+N^e43`TpUFd+z&?8n=ePln;#QQH=q}MkDYQPJ>V;* zA1*0MmF~DbzN}HEwkFq96;~G55>ZoMR94xH1GB(pW#wg~mEqJ`?vxWO9wGq)THRT$!T_ST^()kk&#unjz9m~*o;fy z6n*xL-}U$DGsYOHnD2Oalk27z&oSD?hf&-!XV6xV6O-#`JL3qm3$Bv8#%OXq9fdTJ zg4r>P|YA4z5252UH-pgT&9AnPD=yjfEoXjk9>^Cl~& z7)OqsMzKw;Gyf@l6spCm83=k5Mq<2LN>O=P@knn@kUkYGo?To*o|fo+Y;zdrMc96( zOT4)xPydVt)+OFaL2OL$rU>ahR-$$eM*bAf2yz$8%9#bpt-y0Y)hzUDKs|6V&<;fR z4>ae<&Oh#_7SUB~ocS+{>I#x;BhVAUkzL;a{K^6NYX;zN2jAYqpQ|rOJ`St} zZU%_%JH8-!4B!J>uy4g${8k3A;{NnE*dJ{vNInca0IUV>2JQmB2iy+a0^A5(3tRVernEieO^222Jf0TY0+z$joO za2Rk1a1ihnU|(P_V0T~_U?*UEpa94LK5H&W{tNgg@HgNC;630Ez+1qZ!0W(Ez%PJj zfu92Ffgb}813N7&NbUe^2NVE#Kn~ympCXQb10MnZ0R9Sm0K5nM5qKN;9q=3ASHLU4 zi@;{!=fJbTCg3UHNnkzjIIs@b^|XTIU|mF zMZi#C4`2weJ&*@{)(Ibht-u!GW#DJPM&NPaAz%$~8*m-43b+tB4>${04)g-uKqs&m zXayR9dB9xYcwi22EHE9I3LFkp0i%EtU^s9fuph7|Fa$^f3E<<7g5)+}E3gH49e4?N z9(Wqq0Q?Ae2)G;g9&jsg18_BPIdBQE0yrC326O|9ffnEt;3S|9I0l#oR0HFIN}vQ7 z0Sp872lfPp0NVjMz`vKEP66A1KLPImZvw9ZF96R1KLs8KehAzPtOjlYt_Q9JE(0zE z&H<#P!Y!BoD|8B>51^g9w7kCT! z74Q=99Iy#^5_k-F1b6^g3#**4295@5fJs0VPyrkU6afbS`vSWI zI|Dlc+W`eY0{HaQg5-Yze+B*oyal`tYzCeMHUf_U4*~Z8cLLu9t^vLcd=t0`I2TwB zq=3ah6EF{`1C9Zv0uz8rpcEJm90=?K>;h~L&fj5C)0WSg11J42*fyaSIfct^Ffz`lmz;}UbfvbR3 zz@@-N!1=)0z%rl*Xa|~s24Eg=0x$=d2^Yfij>NI0QHd*dN#v*ag@T*bc}A z{)N8mAHWB|AA#QkzXg5`ya@apcpBIMJO(@pJOJDctOjlcZUn9ZRst)4vw&ql7tjtY z0-AuY0>=Thz;s{=Faa11j06q^iU1$j2iOA`0_=zWZ(m?fU}M7behNGV%*FN`U?wmF zr~xJdV}LTC1ULjZ5V#EZ25t=fN(=+U@7q(SFUjc6rurPh*!WnzUbY zunRc$198%_ixZ#rlQ=p?G}#YpH^{NmeiEnc*bi%0VC({4w4cPmF5q%JSpH+n zL43(m+((8B>=Hu`@IdqOA-DuWVwa=1zc^f;;@&e{T9X9vN6Xue9r-ETZyb*N6z&yA zlgd2-nif}+>x9pg=V}s{XF1V~s-O9gaqDNVEkEIOxf4e*3&+0Lde-UK>2fE|wUav7 zX6$lBQ&VetUmnhU6^Wc_SE=scy$GMs-t)1pX^THUK zRQT?Bv;}qv>=#bgPvSrY9Os!mkACIY>H0~WYbWQ?OU5o&;?wn$IM@Z8K97Fk#Halv zPRFOuqh}mD?I&^CPM=3l8oR(3?I&^C&m1pZ&(^t`ihIbh)92BBCcYrA^?9_$;q-a* zJ;Mcl>htIp$Bz7@KU%JHIDH;{+tH+QPxvsx;%ai8@R`ceBu>sF(Tu9|H0Q>x^Y6hI zI*&9bb^aa8MQPHFS6A~N)=qPxxh;mK%;Vv-+wuy00*RzChx_)|w%Z<{c`AM$kuCPns9Mc@fiDQYwD&TZ{gB&}3J`hKCQNGapC)bw) ztfuC~7ve}$IPJ?mj-B>}xPg43`B=zhreLa#3m68NzNFnyfFv=`;{Wz6ht&aI#~k z(?FcI(`l#&M`;jEorYS=MWun}&betg*ZLxyP6Kh|i*Py(XE=5`4a8|XorZ33lm^k% zX*kt#QEAvUBn>xNUxd?XAdY+yPN(4-$4;k#IBloXunHWdK{Rz5F1B1$8fY#gokvtX zW%}cMvyCize`4?qJ^MKtY-`GXoL!x=d?vjjQM{}3mWrrAcG!NQcb|Sk(^w@^xQM=17 zG2)}S)LiFLeta!}?FFz)U@e@!4j_)=5svDM)U}fxJKeSt=h{gFbr_ocOe##Oe6hM_WgaaqP68#A!SB(b`Qjc7ZS2PvW$nIUe%U#~v(`TusG|b?o%@ z$|w_Gkk|TprPSf{^~wmt1%B%5m4h5R@{|5(8R~GluiD+wq;gOAFv8+$a-Hy*%F-lG z+E&qwI&bMa08~Hu+5xt-bix<(iiMh!Yl~LPMQPGE1YFHNYo|HUToyy~D&!?@O=0x)+F*FYf(R|I?X-+gZ z$Iu)WqWP}1)0}AjE{0}Nh~~eno#sUIZ!t6v4$<7mW9|G=&DL#>_W zM02+on!`ghORSydM6)P{Ce7V){hVa&G$)#4VrbH2L|1c`wbPtvPLH8^7&LPMwxMjFQY=zu!%H>czMFu#RqF2#F6XzMg5 zW&0^0Iq`FQ%SCBU2ub^XWQY9JoM`T8xhTzvA$}feebJm~ z4vXPu*vtFnY!}_mWBOdyGTPWhw)0`Xw=*tAeAQX8dEUerc2W5m#Z5(gbWZcNnvJ{O z#wVQAF`{SNvoQ|kK%A?2nB}508$vY4TRY-h&CxM5=UYvkXETkRC!Ef+84hR7vGTkc#ksy5VY#UE zHL^qKK0Io@pwv6~kozUC0Sh8T7&u%pVL^Lm-J6He!K%Hd!f)TIu^ zabBxFRdd!LuxoSeRDauSxu`N)2>;#q&a!sIx$y}XrP&&iFIQVl;dH)y%i(mstW=!q zr{-KgFLLcvzMN;ds5C4JN&EHIjyTsB;i5F#VCOD3lV)G^nD$iH2-~;ENW)?r=jO}z zW7xG@J6*3Iuy(@bRQou}Ece9FT!KT%7p?i2wG&QjJ`zK-BSiCQYbTu6d?JQsXNcwt z)=oIB`CJUmt`N;%TRY*j<|{EYPYcm}&)Ny6HQ#YKeg18U5np#md>>jn;dFd|iJ_T- zrn`I`!>-3Q!uF>z?0RvWTL%l5o9i**bQ*Fj7j;gb9-_I2wG&Qj?(A^790tXRZ)r$; zzO@rh$G2|`&1E5)hgv(~v}REZ&E+AQldPR^I_={ePG475I-Hfp%JW9X@Z}6XGV|Zm z7u{$Y-U0;aZ*J9Y6 z8)DZO!|uEgyOtPs=floD-_Npk!s$A=%;8|n#ZS?v6zBH+nzIIhU59I@#vyH%i)vq1 z*fgY9o_C(LBhK|jxG2pFVCOCu#qi}q*9hB}#<066#P0GKb{B`(eLIHTB_Vd-iDCB* z*m1#C`+>ssG3+i4vAY>|1GN(?L+tK|5#KjM?C!Dg3CHgY*;L$RG$Y@Uzsw%1R}aMS z<#KIc!#|8+w<^T$$Hp%58t+>nc0Y*`-xVQtPsXtOHtgIw@pKHkD?{v_i(z+Fh@ZcV zVRvg8~Iq2($ZPrdW-Io8!;jB5w z{)ZUxT`vZzE%*oQ20Ev22(kNjjQDP}b~=4S&M;$B;dJ_Ta5z0)DsVV)32QH5xv2i( zyJDcyz7Omu?ZWByWp|?)S3o@EHHFjpa;(GYd^t*St}mK%^JS`Qr}AZz z<)YGXYdS-Mygt#|5$F0MT$JW*uydD_WB77AjNJ6K7`t5J*cX+)`Id|F<&F@|PGeU< zoU3`N<)Sq24AER}?TB+VdtzvQFGTZvW0y;ut9iENqWoM9J9oJ_hTZpFBW$lUc9HMh z-xXqaowXy*E!(RU$LXU(O!<0QoGSNKF?{)f#8>SHUVWGC5(QCtwkE{x_84||2eG6B zcg67Yp7h~C=$;sM_XbC&1NX6)xmG zvVf!Ksq!8Oy(>0E+0lN@;XSg*@yq>z=jp(slm@&S8I^_yZ~&4C`1o&@O~%d>PQL^4 zgv04~K-R^G??FW2#<%a+*-uY69pCN_r{f!JxLmTMa^NyRp3;&8hj=nLDI?-=NWgJE zTf2l~r^|sjvCBn3;!F6R_b;R!@#T;&!VxbVc4u(>EZz6KzxQM3g>d30X})jlI1Ln^ z_$eHAWpEPTJN?*Ee43N|Bt2Sw3p=bh4Z@KPEw8II5J$cwd<3w(XzVic+Goo9x%DNg zem;alNmI`!8I5wt!#?5ke3CMU)ALCVGhD9Nk!H@2VeHIsQ??nJ!VPmc(iF}&T;w_S zF!>Ki{i6tHT20}&Y>B{fwAB<&pPSPhJAJMk;c)s~8D}-4@;Zup#JHC6e~!_Nd=Kf- z3=6Yyd<N$jQD;GJIZURn-u&S?5Ms(rEeV_=qz#C&&M1a+H5p_M#lGeh+Ulc zeiC9AC%*L|cFi&T+z?{dN_L6p_nM!89hXD3A1Ex2VfSQkbUJWa3_mxf4-Z1U#xC;Q z{AqA>Igwww47Q>g#A)1F6yIkS4rf<2Z^t}L0 zxBN=UZh(30zYOtZf{jl&?Mr10UtSFHWl9WRUJ9{0itO^e9O3kNo5i8d%OYG_WD>+!Ln_|TGYaGvY*H0UsX6=aMehggBkOTRE_7E=5a;-7^d;=)wst&c$@;p1 z)0ZgJoXlzZvE`zCc_&2kd26RR(cBb6^A91KzqWRo6U~=nX#O!obE~z}oM^rkLvyRu zq%l~|5V}o=IX`Fd{W{O#sJOhV!a2HyAY884(Yc^C=@^F#G()&R6I`H4_iaS;a`>X{ zEXSIcgmbKExj++oIWh)4-$@_1JcrA$lk=VIv@c}ma2a-T|LLp{JBJJG_te2T_f zmgVOGo@cpkhvWNvmTNa$ph-5Y3(Z!?jyQSt+Ze*JF6`zxn%ti4HiYxz1aN3r@}=BO zTW7fA3>WxfxgnIk+HlS%Zo11ME^hC@P05Nc%^mLA4H+^-?5eUkU${{YNA-cfQH1zP z!O=-0>C9)gr%y_rw_`|rp3jt*bU4&`@JO2ZRqy56&8NuCRxhP-Wv%ctW4Ll9IA()%1IVsyGNKe3A71oa_d;U+})NBY$Z5jkOa_=jW>qr}OidG2;6(^r;ilcE68d_kpq# zKmTs+gwuZh+2M42TVurc7aJdygXHJOG3>TkJMGJ7G3@@T?4;at&&Ihqz?koE)=t;K zy^LMH=0tN>a8w6{BR_@PF~Tls?V{@7-{Fh9>`!)BqU=6&jj(-yv5UOE{RfVdx+Ha? zitQ4G!s&7-cQ{=q4vXN5EEkoAe}<&t2)2t(`+wOq=zirm*kLf1t2yoma4d0H1sv5+ zdCqrq2$$peINbB5S}rOLAK^GRKNquIqEI-UpUn=Z^YfGlZm#8`eEHb=qVuH>c9bug zlYAi#CIP4OWqAlE`O(~zSkSwS3~qo&~%p# zRx>K?|ACR~=Vr09oc8lshtqy;jNvCmM&;*K4}Qos^K{tJO$E)#HS?4ZPOg~`H(ajR(K|DuIi7t{PdV_9_%ny%-5WZ>rNm|a8cz~7^1n* zYHCh28)InFiRSuwn$^^tXtu}D+%81(OslCm(OeosbNdj@i>#*RMDx5DnmdGOUSTyg zCz{`kp*bi-^G2h&yXHjm8l$;;RJrdMqPg1osX5WSEry>vg=jutH8m%i_r%Z~9HRNS z)zqA5J{m)FNQmY$R#S7LxiN<3&LNsFSxwD}<}YGs?h>N;TdS!#(fm~m&0Rw@-!YoI zYfd!z+PB(^tV_EoO|ko{@ug66)L+r^Clg=fGmYJqrr3Q-c70yH<|Mviix` zQ|xx=<2JHTa}r-ZxPh+2_f(op#} zMDySnn)`%kj3+0)>=)?iRSben)`)l(r-VZzC@lY z`@=35=Kzg&IX>U><{-Z20q*yFB_zHEN(1V=<|GYsDGdXh4}OSdht<@aXtu`CJRn5# zEUT$G(L6nd=7AxaE3KyHMDv0eng@kwUT-xuCz@Br&>R+`d6(7HoM_$_L$fGE^HHm* zInlg7hUUQ`nwzYq=0tNt49!DAG+(uvniI{4biN&nwk^MaWOPUhG@>Rnwk^Mqhe^5L6h2Yvf+CoXv`GhV^^p-8H4qi_#(%cqeC>mWi>S?nwQ4V9225>gVofWXkHydb8Lv__pGMoMDvyy znpIXa7>9VCx5jEl)w6NR7m4p-6W{KdlQO!`XhxRp_z=w}NfYB2&57nZ(i~uHGa*Ei z?xoZDpgGaxd+7t5D-)Hb*u7xVSExD3m!DA@1{l{Jt~AB&*Tybia}wVxCcen)he;ut zf3TXG6V2bn&^#hU^L?WkS+><7c7KauH#x-aqZoEmLhL?^VK)_a_%rP|*0k(*9_kqu z;kX^A9a#1@T&{3Ap3nQ~->$Bm;&ycH?E7V8w>@!q(n1y zTR4Dbo$^zBxy1OAuQ^G>3UE}HH0L2MTF$myR6VN?iSIfapXMaKtE{HxB)-dI#CLp1 zd_S=9X-?w1(`sr?;=4IUd?$p&x6a0=If?IwR#S5l-+eLSJ251_pWFB}C-H5vnwpdN zo`@0O+>rR*wDD<9;(Og{YEI&NF-CkRg~az48=vMRzW1!A<|MwiW5oB>kodgwP1~wD ziSOT5Q*#pEKVrl;FC@MlYW@Cuv6sxH@(L6kc z=7JE-W38s~fHwTsNzI&e>nV zj;>`iCw2E_(j4Gg<}|CB@Sx}SvF6SzOx@L7!p;{R6vB}yEd}6EAroT9_1bEBjvaBL z`7e`pFVoIw{vDjw%u{~;+1TZZ9dV-h#}H2Z++s8%-!W+_aKL+m=p zF2~y=D!yeQcHJhvNI#duj!kXZQCd$oc9HM$NBQzU!JQqFzB8?##JOo$297$;C|}MA z(LCR366b236GO8vL{t1E&ee?L=eaPV_FA8tKeT>oPR`ByLpaZe0G2i2=-d=LeQw_A z*y(fg<`7OauXQx_x%q8lmn-qKXG$YT=^Fs3F&qmYJoaD>a5KiKI%fy!u zJ4(CsV{bTi#EIrBA)ILb!qL?E@{F;|mH2eNJQ>1?<~pMpnJ?!jOnt#UJ~MWaZO?_)Pu({rFQ73)qEK_vkL6e{Dh(HfXzp(9 zG$)#aV`yF+lD?sA7u~*GVtvu)?QCnOIjKv>gm9j3GIkm`I&Z~J*UuvyJ6%7=g>a%- z;b`jmS#0cbB|cq04-Vl(^D9O(vVML8`Qk3elO~>pM3wEOuyfnNON=j`<|IE?gmB{L z*~ZU=*y;RS=Gf`{><-~XbFrhT^Rva+?;y^#lk3r67`t52r2U$MUBKyiD9<|aX+Me6@v)Ea zm6nZ;o%WMBI!60KX{6D1RR&UPgb7yLs!#7Ui%=htaUg&4`q#sFYrar zL;0S=>3Jx(8ZPj~v>_(G8yq|Glm2MA%Hd2MG~8v5Cgn-OH=L_UT#n^jP2%JlUNoc5 z+ixaJ9Qywj_(I!Jc9(_Ny>09w&xgxH?B0zL->MM14~$*pbG2{5j!momAc=oBc9GwS zx&lUSdnWyZ=A=E7{y}q|jZ*pt;Y^+AV}GQ7(41&W|DZY1l>R|D-JVJRpgGZ${y}r1 z8K-~vHu8m@xp5t&_6&c6FT`^->=rIK-$OXApVqF>u?x<3*twj<$LW9_x#7kqoToU6 zkGPLf?%Gb`6OQbn>im^3cI(7Z@CA0B=GYJHn;ODVe$jF`I2tpET@Dd`A5q>|$BsDB zEDzyC^H4`q*NI`qE?45yecb*boM`T8G$Zrnssu8Q9Iv*0mG5~?u%kL5oURitCuKx& z&U5UfjKVmHkMgD-cI1W|pK$Ol;3Picj&a3WoQyP_2F+%SlQqXY zxW$%>()zWX|v#p(QIn_SN@sh>a@d=T_MfrIxJ887!KYs^# zfN%F*7h<=<_!)U0<@yl2i;Z36wbKo-W7BG1-1Ju3d=XCPOBSc{MYyPZxe<|3I}y|g zgszper7p3{#5Y0QRo#sUIrWl$xai#=W!htnx7v1;Y9AbBG47*!G?Cy_Y zcPs4JwAv4xeF$~~eTVh7kobNaBfi^1>>f9Ek!`^pA$Cv1i0@9=v1xTWeNT}czRxF| zuAf<)s-MC|)urztGOC}{4$3vj-WQo`65;e%pEx>PIB9oj->!~b(9THl62zJeiBFaqDj7xue9VicG^$k=oqnMAFbUdCLnfL-<^fk#l4yUh4wiqt(MPHNr%CRFq>5rBd9nOpy z4ELO)NqL#@4d-eSC)XsdCUJ62BAQY4b9ExS{T#++lql4kv~~MiE=u$JA)4jZPIIDp zSPad(L=)+w`+2lfk=+3I@_qn2{AJwBn-s%tO^97h47j+p{x6;v;`(Io;uOyVT{xr`wQr$4<8)tq!N#kOi)$2S4yf z%gK&ij^d7YINgTKbTlb#2_J%3Tum+qpDEAPBu?58(Tu9Q_b0O3kng}3oOy+slk@!w z%SCBE08Mwfk?e*O$EVMSI~+UhCvjvKRkja@ z)R*VT4)sNIQeU37T$JVyLo{EtcA68-U&hdU1e*8@#x)fD4cTF=C|pjpPrG@^;%t2& zQn;uzJQ@<;?`?d->G-lZ6`ycX@%@MsXMC6c?{dCGUz7Ye#O{5v8{oHY)`i$@Gj@^B z#~ur@`;hDgco*Pt*tvaG!NuHH*XUh&pV3j zun0$eoM_e}2{X9v*XUUilo`W)EOGSRWqZQWRKa3hFMmmhItuj8XKq@~=kGrpub zI!5eto*icFf;12(=_3wi0jK+pgPr)apTz0-bUpJOJMAZNuATU@kFg7U(S8y~en!=^ z4V0t{?m2dY@x>EPr=2*8MmU}Js~tO?cH&$+N&6~emn)h&?Zm+@;B;NO z)QL~~Nt}+4d?87ZqeW2fr`aX2LM z`tPUk1%H$+!ScMZ%N1^l;+}T68pW-5I8Slw4CjevUkDeKXHUUN{AD=$GBojACRaE< zH|ZEG#9r#Jftw$2Rs7I-L)|J(e8!G+C2)BHv`ps7bdR+wgMCPDNL>c zhVEOKTn%giZXa5hT(loF_Ag9s12!E{nDh=TOjZG1z-nL%u-8F_$=SfRqQYd&!G+0d zfcJswL!b|A1tt!MKJYeBHKH)N64(M%9$J{Z75!idf+3V>}2@SfP4hD0{(pX0c--iM)&}%2DSi|3y?104WPCOX#>^) z9|FbA$V1>Ipr!?74h&le9|6A=n!ww@&_(bG*a+;^20g&*L^^@Jy5JwM9{31YbQ&Q(0FMCMfZ>;;P6O4eQ0IWPz*fNj7PNs?z}vvkE1(ao1U3Sn z0F~cH9Kahu?Ug8Vp!h2I3=Fy&^%-~{IQcu!1@f+eCa?zZu7w`38u$d5eI4=u_z0-I z9(e$K2n@OrX$Q^(9t7S8hJ6>Bz*=C_P4Mkz)E(gBTTn-UkASjUQBQ!Ifpx%Zz=yz) z+fW~YM}R@ML+cKd&7G(xz#8Cfpz3=_C$JHCV>Q~G?;~Azp?<7E8t%sNKo776cpLcS z9>jSswC{uF{m4(?8X)-q@)cMHtOfiBVFzpiyoV4E&;_gpwg7uQjC=sr1M?q6dV%DR zpaCoc)&g4r|HsHjU=?utV~86ldmQNnUit~jbUpG5cpo@<1L_L!9FX?}d>C%{eJ75geK6Mh0ENIvpa3WZb_VtZ_6K}mKj0u>C~zR~72sgt5MVek0yq>n z3@8RlfJwj+Ks7KKm;y`%YJh2gEM`nj*P93M^E29(@wVX(#Pt~cu8ReJ{{_zn67*Yb zaxAUEe?%)6To_GZ^3%YtJwbr_6@Y$R*-!D)`H|ufgc06*|nHegFgVE z?G=L&4*_wn+c`g3woiU?)o%I8*Y?a$R_~RcT)lUGaxJhM_BZd6&o-;D^sO#Po&wYZ zqATk=vF{eUU-UOZf91Z=7@40ObZ~z1sQvSk&+V6=tipCRa1`+VP@}&Ewm%86e?O+Z ze{VtZulE!r{|JardOaWfWPtXGfAf*YtKh@%srkv`arwzB#~@sRv`@)TZkw2&d<5(2 zGUMOPu)QqAzCFTzo3ihFxFC5nFb)_AXx}Kj9{X;w`^7&G^`Q*D)imZOE9>%;ZyW=k zrspR=nV+A`!@fblUekU4v0V?G3~asL z=vTv@G;e;UAh`lq3M>JRx9hC5^J%Bv{>T9W=-3!%fb^bHG!;I^aRzZs2y{df*D+GT$uz0gHhqU>;Bp)B;n1 z3BV|z7$^ev19k(p2l9YVk$?XL{tEmF_ye#7cn$bD@D%VE@DTi63;Y1M1Gp8q0k{gd z47d>J1E^j;iZ$gWg=Oh`8Sh5|#{)IMC}3~k-!By;{{~Q6U&H!GYWpUH`_y(l!bbt+ zz%XD>fb2efu^{;_Kxq)I7qGn%pkp7#nvS~(>pq~xZqLHn2gr_feu;7bD7;>UZ$$Vi z;1b{*fXal9S%mN@0EKI?remrAea!xL|1Qq{Tx@@ceEI|M8t^Re7$EsY>tQ=0y*nW< zcPU7gl~;_a96e@i)ws!1rq)b5lK3HeqFw;adle*C?F-wXNHaj3UIyx4>i>cI0{F9$ zug4W6m(4*PLH|%$hjXhQ+t|P5*Ae{#Y)=I!&OD5Fq#v0-8hT?2l3n9)o{mM`IHDlA zX=*|8O2Df@odhR-%6%(Y7yl;R7kzL^Uh*?wr*GsX_XkRWNx)3t6rck*8@LSkE^rU< zIPg61Ch!698L-o(um?(kNx)3t6rck*8@LSkE^rUnpGgDp<%z&-;#7jmC_KW?&7{L;EF6*9;Q@S|$K}6u{B~^icrIIY1u;u-pUm zQ2@&yfIbRfIS8VC95QpcB~14;CA>|Azk&qI{uwIVt->o+_@lxly%^~8p0+Whk3Wa^ z`@H{Z4j;hbyE%Lyho9i^K^!KnKCg(w+c^?5gPxP-$ub9g$!>-<^@Zv3&ej&}!j#ayeYZVSW63>^CLqc_|xSfI;O2e7s4cK3<0l(YW{VogU9S zn#1ONzZ_xFyw!$F@DQ2edV&P7NL*$sot6h!$LzfVokpKM;2922=dHhU_-GCvxGNoV z42SDDY|e`dIc&;e1BXpn{ENele0;@jWV?XFr*fEs-k#{(`b^M!VvltA5p-&@epI<5s)3j*l_z)l(cE%gmb`uHx`NIc(aiA$ybNcx#>3ITZVSzI$e>1xPysWr<#Npk%nov?vUOBe1YSfs@stG}G>;$iAQDZkBT44^Y7%`!2 zLU{$4_Rfx0UxY>(cGQS|g?c+uZLJ+G&4Ed!F{y;0Ua&Q4Y_Qm9vW!O?@lz|*Kr5o31xu?I$*tF!7P`?D&?_RewAyTAUwfKE$Zy<3G$?hG|I=Y zcU8#CQ59pyR864&$Z&ILR=nes%{at6Va({!qekO!lifi9mY30iRjiHhgp%@#DpQhy zWcpZCjNsUE60H~w$%XBmjke<0>Hw}1tk>Mxi@QUnPT9Hus){JiEzR442VY)62T-+a zZ&?;(LOBXIRn^_n*gl@?W^q~ZsEP?~OB!44_NWTlkv3Frp?JAMqi8vD(bn;!p!gUR z60%x3kmV_ggO5Z}RB$pI8W!}nwfD4jG@Rbp(B77^nSmlW6s}evht0|>Egjj`(bV4C z+%l5S#nkd83p(3VrHhD3El)MKbfrf2cC;;{jni>VNAI$c4byRob}VdbjXrEaTTg0a z&+@JoD<=^xY-#N2?RNJOnu?=G6{DKq=y7JZX)Hz+ zqk^O*DAV~+R154KZ4N!Hx3QTc9ECl!e=O}+dr{EXJBIc`w#puhqQzd+Zt_m;M?unl zb`QJD$JpahaM)iZhX?!VTmiv;e(_IN0;kQk&1lTgkU7>ubD1Cv(vlN?GDCb=eA zjm^#7VnE47ejsj3E?tY}KGiNrK^Q-GT&UPpF5 zXdKEXP{kR6HVB=@1Y~ftDy&ha5IG4=dcP^eQCx^<7pP!*+LlOWk22Miv#&SRf^)t( zWm7-O)KpG=%H>RLWwX@M1?^Hsm8P=t{-*ZMreMFRtm*wh_EehM%6^kyQu!)Px$^#n z%?(Q$Q;W^1sm@L8Pqk1}fJ$VNS&3w((3vbmDyVIutgb{7C99E(qmYf*SxNa=UWT@m za&mFYa+~T(dwxy`{tE(il?(5ED8iZu)x`q04Pf z1-(<3*)fv48@r);o&Gv8K0MX52*b=p$P*4VbTxK2E*W1xyox%CRHfb7-PYON*0Wsq z@~9U!s)mJ)sUE7$FdNHeIFVC5=;BbpFe0F;gi!$Yb+vWyappvo!9k$Y+>&adA?#T0 zjK)&$b0{`Yq{~v72SL8Ox2b2mCoVMh*qj{8z0g=R$A_mzjX@*O($m;MQV{FozI=dtSoM2{WYj0zBGo1+Ixi>~v zAsGRm7IP~^C#cDd@^L&?;+!)i6XQk{S5(;ek%}fhv8-OjXpVhCkPFm4ajhAPUiffi z9cn4g_lAb129xhpJf?x9eM=kLFhIgsjWXP(GE+=tD^+TkqyDBUk*&Q;mPo#FqSAKK zSm0n&r%`jIn3nYRv@Ek8mQ%gPK`7-^1tga=U_{i?eR@lCW zTDmiQr@f2YI>cVeW{FNb6%O|g87`@GmQxD?x6oQpLfK;_>Lj+aqsjCYu%IS{dZ6@) z(Y@3*@_b^TNKzPvG;}Z34smzIJL#lu>E?3=r6iROM=wRC3z90S!hSMv3NfgAV&?Kv z1;MLS1(grGyHdE23<|+kzI5>hX`=I#$1_-Aa3uL@c%7l9=Fo74dU(na6|+4fG9#6i zK{Tb|ur-H=K%CQZz=Fo^?l#*wqB5JBRlzl@3|9iU0-)xJ91f~Kc6PU%*4vg&s^mDB zE~<(_os%pFk$KA4+)ihX^+Tl|Jp@%J8d_0x%1ozInW(SEp{5?8i&#p7c24s+YF1IX zFhW?0v8mmsI|jM5U>kE)va~6+1UDLF59;y)ZU@=AyqqPmf(n(3KFMsMU@+E;whPA~ zCwt*Nq{a^)M~#I&0y`G)0Z64DM9@%7j+%hRklI6Z7}FaTc6FKoR0T(0!Ld^dh5a-d zL79oRZL`@?k}#t>BVqet=ptJxsE5F{cpx&mDk$X)5fm_ss7t<9G?}NH>}sPRuD8q% zADvk_UoEvXG)$j5Yvu_JvyK^GRxBGcXVJd#;a)7*{;Ov&lo*2g#dJ*HAmTu3jZ+#`Kx9=1enI zbx0cx1v!5j7NYO%q5Prz#|i~-D6LV;7uq(^9!Yn;(uY&k#$jj)`EYbk&fzWSzyfh< zIB+!eIea+vCv-fTlE9Om?#7N(+Jrk5vVmj92Cg}A7!#B;`Xc2UwfGzzoHV9zGt~67 z-j?p=Doz>;Qk?LY4XLRMHO$NmZpL6o&6Tl()1h`5xxy_9nZaLU28YQkJ6oC?dm2qW zuAt7R0&QVBzu09tNrlk4!Uv2VVNYKt_1xQ$3%B6^ncnr z_xQT1GVgC_QjXY4QIv|PQ4kB1+J*w*rcHBc1G$l;7cQD6IVTs%<#0~Y2I1A}fHGPY zkx^7|ih=`UQAAWw)V>M|h>8P9he551$RG;(RzX2|zrVHDbM|ur^O^a)|Gu8jCpr7O zo^@Z(y6nBzc~+X&;|^b188uCt%F~5n%qCS>K8BuL9_67&|LDMEo@Z5xLHCIv2Hh#L z9E|G4W3GH5-#<0@)&eSNLkG9ZlLHemV5r?N9N7Xd40W1NHHTCRFkG6N==Z@Y#h9L| zcCSpb($tVS3S|>(rHv&x7J;qne8u@y-2~65CJO}>Ls^KqifcOt?Sa|n6F0;)rVBki zRaqm&;n{`FgvVs-%<01Lj6J$Lx*@JIeM7EX5m%U2-)bsutWB+SdmfhAQ!~?pGs9_R zgu#HS4RdW+_@`1Tz&uoRYIuBLWbTS*Y;yC|(7^QA)MPp-Ra(l_iW#s_nj9GC-ikI3 zjaX@tFyI%{bkYu@i7soNstG}D!;BDBI|M>g=~;71JvKQ!l`5zn6lk`bR7H?+J!Lbk zi%wEj8{q0`Xw$m1UL~b7xXJP;?zrX3%*O<^Jlt@nqpXdwaU9gsgR~3iws=i{n6ScR zULS6HD2t|P=INnW(WqZsUh;HxaExdACoo%TD0qHfSr*gG)HgJoc%q7TOq{-{`S|3m zUiTK%y`IRCmCBR1dLG5uGI&jRvR4V<9@V9i_)LzaK;=fEzpaaVyF6Wjw#}cgCbVvn ztZ8aGp>D~V&UJ^^>9J>By`KLccl3(7C571{_hb_+)&|B8|9|#)%(A18s;^rzbnXbt ztGaTrFf{f&(f!?*wZPwN;_o#vx3m4vbmG76yX;vAAHDfrz9QYY{CBr>LzOD#|Cf46 zmhlR1dSH<6=~DX5^Sksa%>2b<+2qu8VOitqwxgy8Mv`Tt17+UU<N|udG z&Me!^^Ay$*RnU*DR2W}2GBurE43^93MR6P#t>2Pm;ZpYp$+BTwkWXoHB=+#XFv?nu z6=t$*XnLwd@O=6e;v^#j6JtZrn`!J&a2jH#Bre&UTUTE!J)x^S2y-%W+&1 z<=O`+|MEA(pZU|?$c;E^&!psRDXRF>ZY$-3En;DB<~0O*1K0Mk{9S;9`P;=F&RzJs zUWJMu`P1J&@@M`oV&BL`BzDVp<&u6Zz7K-tPkTX|@7*iz?y2_oPtl)}+KRue_*->l z>PP?U;-z+JDL%E`&RTwdG_!ZI{l`(rS6#gPG~ecLllJMh&kOmE;>xvl+nB#R{_^-! zz1qjhaU%}qZybN)|AoJ=Ie*&2I*q@ZEHb{W{&sS$woo~=|95G}yySYWr7!x(pYm}B ze@a(>58`h({`^Po`uvbT`ImHe^mqGbfcUA4-}mxuVdSLv>d;lT1BH*$mEJtSUsX!$ z=7l}8!4v;1j$gWK$yQCyOMc}7n!m@8kxb?Dx)Sy5^ve9PRjVr9qo(I2f2f4Y(v^P~ zJbCKedC8*F(%%S9QV5kp{T%hJiZA!QdCBT*J5;3{cze!As(>d!JKgBOV{^u})bdUXrN4 zrmPlB67|cJ*(}IM{V!!U3Gz`tOPLLUeAJ&(R?Q`e`c2Ae6~?^^vssRh`hmXZ#gSe5 zp0Y-=RIgKJ^BW)OZ^~?d<0CyyStDBZnHPR-;@Pw_b(Vtk^bPN8CmHxlMqp^JzUg@0_{Y$F{-4SBf8P2x z{Z#sY!M}a1eOAWuNxl~icsJ!!Pg8x*hwpW~0N&+zKlnj7osSnK2f+`)(o}^%5`N0@ ziSUB?{5Ctv8{rGCugT5ADzDD;eg=Lw-{LbRzo8~4%@&Wr%I~p}r{UQbDJ9{l&k__~mf3OYc?irjOU;`WY$| z-%_}a@M(J;n4GNef6KzR!pS8yx$&5OH#`pSLjZ+83!eT+O>TS4?*x1R`F~sV|2BA) zOaDFaCdZe+J9pIZ*K1 zwlMiA^6k$56Yy1z{|wjNRFhM`SNZp0im5{%51{0x;JJvF&aQT{k=AIr}Z_htEc3i)>O-+(98cMTOK z+dzGh7s0XW?8-vP^Rk?~EiY#3SozXQvj(XG+{k6_t0GX4oH zJ4eR<3Cre@@gHH?KiU<`zc&N3Y#~|vFVaB$+Kdl^Wh2SthrzO!WLyu+c9QWMVcAhK zJ{6WtCF2dS>?>LQ4Z*UtWc5*oWp~N=A7I&FGX5|udrZckhGm<{_=~XYG#P&zmdz&P zdtupcGX51TTTaG*f@Rmqcpq*SWaG(rF)Vve#`>L+Y(E*F0Lu=P@u{$ELK&Y9%RZFV z#|SK2QN}Z{>_(aYe}H8}%H$t{WlzfFSHZF^W&9ObcBZVozYELel<@`z&IkHNA< zW#ONOWtYn2FJN4gjVhBL1j}BP@sY4>R~erK%Z`_PH$nm9T7enS3=YyIsaz zuxxl)`{{RHvgc*t-wMmNm+=-@cD{@+gk|%~;=2Tv{V(I~uxx>u|Ifp+3ugRHST@3p ze*nu~nDI|x*$y*)9F`q1<7Z*n6f@qBTPoQXGkz5;TVpof9SO_sn8}ZaWrNIkEi8Lv z=6^jb+hkUr0xUaa#wA!b%Z%RzpXK;sShmcpey@OK*UZxUEG!#mCchb$y)%>F4$JnL z#s6bicF>G}3Ckv$@$X^TN3-zH!m^cSypUT=*-bM(7?uq+<0D|%Q!_pumTfiD=T=yD z)=b_9%jTM;pND0C&A0^17MuBh2Q0g67T^0}*=RHQCt%rYGyYdtw%e>dz6{Hbo5lZa zST@~^e+0|EoAGW~w%&{%hh_K8_;0Xmz!@*(mRt7Vj1Puo8_xI$Sa#x!kAr11&f2dT zmi;)(e-A8Ma^`;kmR&jHA}kwo#&3sZZ_fDrux!s6e;k$_I^%0$*`zbR36_02BP?5Z#vQQi z;u)U>%SN8@7%Y2v#^=JaooD^-9Y0n!m=S~{B2nF z1dV?P%eJ7U_aH1ggC>6zmd!!y&ria#Ke#-u|7v(7C0m46fBV6*OL$Gp|0`hGD75+Q z2w3(CE&k(R*)BA0hGoal_%v8H4UOLn%f6xU*|2OK8lMXXyN5CTcf+!QXz~xkvWIBA z9hPlG zJeqtPESrxe{}?R$kERcwfn^KQ_=~XYLYn_?!?F=+{9{=5B8?w{WjoUN53uY=8nYxz zWK+`OUkJ;-r12|Y*_t#y0+!uLpjrH4Y+1a%8H^8#FY4QRr z`7aXVc8oseh(aMkH+@=Cs=k!P5x=HR+AqE%a*J0iLmUt8n?l+@oKyQmc3Ww0xa9F z#+zZ;fi->)ESs>#m%*|RYkUnXTd~GphGjR__%>KJWR35EWlz@n+b>|*mbLo&Kd|h~ zn*Vvc0+P*Hd!vB zD3JYJlOF)fmag$@VcFF+UJlE~uJOsR?Clz#3d{Dc@#(Pa@LK*0ux#?0d^0TjyvFZ^ zWvkct3Rre~jjxAg!`JxRuJzOeB-VA&cr{s1hy!^WS4 zWrNuGIyl%Pj_vt%Shk5x{(V?>ijDsRmd#@0-@>wAZ2T-NTgJxwFJ?S&d`v#D_i=v!LqY#@_S&}TsHnWEc?sm|F^JgF*n5gJ`Kw*v+)af1uPrQ#s|W(*KGVc zShkyu>tWe(w)=%Q!LsRW+z!jWv+?P$Y&{zf!?OEq`7Ob+0d4#aSoWZex52UvZRNQP zmYrzht6`j~hr(oHhw)ARv(I-39 zCf^^HO=^?B5|({xTfZC*%T~4dKMt1NYU37IHmr?%VcD}b9)xAv+IR|~0&^!Lq?^;g{+~>6bEYfMuK8X6doL^--_~9qfo1R8@^=+1+uz1Fz_J5w@qH7PO>pDy!?F)<`~WOl z;l_``vKwyvG%Oq9#xJC!$ey_IL9lF#9}w?HUk}U9xaH?KST@Jae-kYG|)0 z@#`#DcF8UL1S}in#&3sZuiWbAeXwko8(#*?j=9BuH7uLv#y7&UZ*Kf8ShmiM?}laf z+}7_ufrAb7sK1ZGvWNa)%S>vsc2`{JbW27tfi+*TR?Ysma|& zp~TlK{BLV=U*)}z_-k;(kJ9}?y1)GnJWc##(f{}1jZXe!*gjT2`9EgwYk!9PDg4*q zN%8##mfZGl{0U|=W|T7-zY349&*ioT{|6?u@K(n!gdcl4+u!jr_|Rv_KmL{fI=IHg zcLba`UMY?r%kOT&r%nr#laW6|er9_+v6kbGxYOg-H&dJxq z-TT$%PDZZ$=3)C-e(pk^x-Cp5kvHFy)!&xq@js4@cJsd#xwsPt#s6NhOaD?>Hr=m@ z@+;s~POkDaJKhe@I^F@Vg%=QB<@*xc=lC1&Cg=Y)IPdre@TlYa;AzJ{gNu$IRd{U7 zA5OiiJb!{^i@ue80OG&FvP(Z2%k#olQyy&8k3{`H5SG1qRgnB20?T%NKJp4!cI+8u zgZz!K?A~kGk-oOUvVYHOzaU=^+sE3g0eR}SFxiA$d|FKZZ1|+ZGyPWmu5w&L-t721 zcq`>Uln7P7?}T?ceh-}B-{jliLtXd}!Al%}6kh81a(KDpE8&%nuZ0^Ne-4(7{x_4X z>hC6at&`sZZ*qJme3s)~@J7cE!+nmQgu5N@Q%CvPsj)rQ!8&8$+$bM~b?!i(=XomMW_ZUTwYjUK{6e_zP;8RN z@E?Q6Uss#EBFaAx>+FI9V)&cjMcDj5EXr?(ccM>V(5JiMtB$J8m0_j#3wZIe+T0%_ z{{hzd2d1yj!a57V^zTKlA-}Nc>%p+jQAo#|MadFa=P8)~V`2N4zUoYZ)NNt13c2{T zI4D2e@K#sf>){)bzcgq9+mFxm|LyQKj^7Pm!?E=F zddJe|TO7Zi@H-t#zi)Lc{l4AtrTD+m@#V12aCkJ9?^^gN&UTP}VAaQs@X{5vxj#qw zcVL|XFq|H*y|8jPFGF-Z$0eJ|4LPZfLB{&Fq!tXA@jpRh#>6l#j#PX%AaZ%)&aq z!u0DxSm#)1{iO1K6xO*E#-D|C4uM~cH< zygb@XTcjCkHKd-mj2hc_%|ch86iK8>Awr!vmTE6y$!y+wKjL~UTOZW zfOW>mp;7*MSm%ytpO*4}3%u#H+T15&e0Rc0Pi<~R4F3~YXO--nm-_z|eD9{LKkR|; zI9o+2r2zZs_m2g9UZSF-e{WS_tdN!V&0qeXJ z>kq@Q&Q3A?o`!XfiuH$g!a8^50KT+7*aqwT74!cw$>YcRLp$=+iT%aM#q~I-zIMP{ z;o-<%f>&~e%4Lyv!jB-Q*@FK&;l)FouM+t_c)=j;5&0)vZ0F1rnj`ps7+#Lt+T(Hf zZg@?U{~2CFd`Cpy`*r9Od|c!g!rS1JBEJ;A9qx+!YIt$JHg{y?!{KK5%*bzmx5Fn! zJ|2D$-Ws_HKC4ihyD)M)yveoS8Sq2ME&c+$i1Mw9{)=!o{QAh}!L#s^$QQyoL*`Af z{XYP2J0t5)8gI5b)_8M)<4f>=k>gLm7dyThzSQyO;OiZK1-{YoPWTqbx5GOf-wi+J zco+PHwG7wGsO1|cqjQ`SPA9%5v=o^()-0l$uD91*!ZY3m{PZe$#0R1m&f*e65e`t*8b|R z7dY1aQXO1J1a`l)%5k_Kb^gQssAH`UMjdOtIqq2Nfudur2c{is{-1UHH}YGDK3V(j z%Rp4exl*T)Kh^g^u+EgaIr8h_=1+0HSk$L_SZ7e#{YeX~bE%qRee}ZDf0A?3V)#K= zXII@8_491_P|mHA+A6*CBzO6HAN<(WwYg)X|4+h2`26VqI#}ml&BlM7{&o zxmbnB_rp3z%hrd#gms>l`Tsp^A8YS>k*99_-U#`2!q?!S`E>8Y8E=p?OojX}fS-Zy ziM$xT`&#lJ`4BkAnORhO@Q>Z6WI1f}*@>{u*!ozM>-S1KTzyENu6Nvw|Lw3cD1BNB zU*qIm@Qsc)z&APWhi`E_4DWPYgmuQ(Ow7-_;NoW)Um{-uFW6C=D@Fb^ycO<`d?UOY zUK#mY@By3~)*Sh6_$pVQzkqeFnB8AK4(qJ3B~jm=gmuQ4em5n3nMcLx{4teZydSKy z$gI6z3F}-kyZ<}_);VSe<6rG}46O6ato>KR_ObTYnO~{f!lWH}-ThhnuY*^?Hhv7k zTOH593co7m_Zu9qQt{ zg!q>@{%2Tcmi=SwPioKRuW(Ks(W?H`o`>F)^>?-BZrJ7{wdd^3wYl@6f3@cxxET2c z;=jt(&#mw^j(-U6cKUT6taH?KzK_yZ|7o}-TR;C2`5ySJ82=tvXRjR)_2I7yzq2-{ z-?=ILzAU_S9-HaIfw0bIGkrJ=);Vpa4=Z7v>t_0}3fB2{~2EC_*%HZ z@t5F}9Dfa7<@j50GrTnD)1u@KxcDDgdiTL9Z(pq6M`3=zTA2_22;X{N`ukwrFV`+* zJV9>#e_#0E+p_WRrEs6)I(Qp=3el?lmcqN>vB)doRZf48hnv4c{YU+6f;W}2{?Z}2 z^RM?88y)vZetT{1Kq^$}oe7_HS8eVav3x`D#XrjW!`bk`Kd8;MM150#+_qqTr9YIA z=kd>1i0^G&6#p%|U%CLEcJ+BNd=>J;V|w~MWVg%T$C2NCPi^kr7~i$hE7r z_>DR$Gy_9o7qyMAe-G8pleLeCqaLqpRbETO7H^H+x z&Q^=zJK(i0{&lda{&AA`5T-NFBX$*16Zo%}lZ5yv;ecRT(j{E*}C!Mh#b2XCkT zcg6UB3hNBJ55daMBk(Tg|99|%j-Q0Ly7qe(*7zq839|`Nsyl+SU4Y1D7v+;9{!3(04Ki?UhMdT@WGC+fG;Eb#u)xz;3wdL$Tz@!ubQ9RKeq2T;L%rS<+&4H>Ein# zd^hq#WB3Q)JuuxqYRTWTUp|GA2@NW_j89jUVyy$kombIV*D?Li-&SoYzS zzG+FuN5FR-K0o*7=zlr9^hnNNj^#fVegvL~`g0Pz@eTCP*nd~U4K9Cr|G3ogTI4y$ zJ@9hJXTbI`{nD9T>-opH zV?FyGpc#8aA>{!n$E^@5r726zNi2q9+Uka~s{Au`d z$2(x1FKO$SufjT0^61!}--R1EXYvbiez+gjIh6ZFefbr9nTt>N(?!R7kn8Nqe~Iz^ z71kM+7svMBcRBigD)xI~`y2%4Pn@4SDeB9S@bdQgmHVL+;ZgW4(SJL<82@dN&w#hT zG3(D0u+GXnI?B(7b$+JZU;QJjb2RPw#Yf>)=$GB!ej47%c!ZjS@&7u7C;fNC_}VD% zMpxdiAz$0UnWItu9e7vQ{L1r4J^$F`{6C2NV*LMG^#5x(-^qEjvA*=Y<1FW2&rA9o z>-k6C@gE4UvqrCt@yTF_&Lg$;*g{xmlUn~g7}go3nora}mclx(v^Mhbu+A;j_@?z} zJFN3b7esyweETgmxf9?Q6MhU{`;z(L`KtI_SnvCLqWmA=YnVS5M*c8-_gB;X4)T9F zTu1yTA>W_$u7WRSf61ok|9bcl?9r%xU(DZ5_$m0Kk?)0boKreN{Ym~X-2BCwO8S3* zyZ?;+sodkU#IJ;PHmmAG`8x_;ynk)3H-;gbtdH`yh`(pxtD-(B zzYFL%TWQZ*ktzLGz)wAcJuo5@9|o@_ewGm-{^Q||@Pb(Xr^2J~7o+^mlGEOLKA`Z! z@NVv}tvnNO_Z{pfit_W|ny=S{`$hSG4}AX7^K&dmL-@QqHXXc`_t#dwgW&G(*5p>j@JGT+{!$a}4;0_Y@Wu2O`4^u8?HVerTrH;lI-~y^;5wdnT6u1U55AN8;eFEn@IClq$~P7L-wR(ud|wKT{=r4`@6;%N z9NtQM?;H7V@J;wXGx}e24BZjl0ZYG+hI9AVCd_B@e-CW-vKG;P55RYk-33UN$f7;7p{6B*? zBEK#$Vx+aG2gD*lZyGW7`!_$mEABplJZ1&9RDBpSTV%kgV5#{II@N&j?)Hv|P@MXkT zADDA8VY5f|;^alxBA|aDPun9&z6uwaZyt`}Z-s9{uJyI@^J91s_HXK<{2};umt^^;M)4-1=Zl>eQP_k(x3@oF)wGs`zb`62LK#D4<)S>-tr-bMVM3-Tm68D5TD z&%-3|fFJvl>HEUu4EPcJ>$#-z`&L-?!mPi%1I|-F?~CC-0Pm(h(5xZ8kHb$9-sY1X zuy6k_!rPgz6}QsA1ZB8$4^rGKgw@6+(3Mn z$M}ZeweZIxPs80jZ%OrKVX_Urfc02ffBPk$fEO_Sn?8O9zMk=GAf|rBgI<5Po}!4Jk~`v+!bacx=K-`dmI(bB)VWldWrfs|Z&TvL*s zlCW&WiX<4Xjjqa5yd0h?={TdQVBw$0nq1;O!C>?@CK&v*bT*Sz%&kG1kCY|{$`h1n zYItIre;jR_ln0aYOi>5zVCdalhNBkB-eC)8UM3uiSS+Uh!#PpWrGKO_&6#M0C>a_r z3{1}8kK{OOW@fsaa8v+iByjv!|G+TU{Y9(=7m_UloT4*R9vCSkr9zQ|UHc2A(o~7O z4Ra({IiV)DlsJkrA%n%z6gkJtJZBP2j`Zs+#w7Ue4+SX|MmS!Sm^tNu6#EG}F+dcY zq*gBU4^8Al{?fEKhA13tfFkImiG(2GyEuRiV*UyfoXwg>J5yF-`NH7L26c#N|!f)~yR;9Nb9$SX_~%h+C4Lsq$Q>ROcp z=jm0rI904%b8g$Y^bu-3G=$3BKRGioSSY1u=u)nU8P1U{j^k}yhXWN#(;VU91(n>)S7&Z=NN-R+gwS9h&*;a2yyW|H0>cfFypJEJ~#nPqf!p9|2JWvr>OJxi}? z^@d8|rsmVK>-H?7ruM8PP3>*YkB_y(1?b2!*VNJ7a+)i9U{_6WdrP&vy=9KPZ;rgL zTHZM~0UYM|n43iB+%!7d=OltdbsSwizR}1w4%I%YbJ@E(tEi6dURQ;XYYoUXK}YvG z&U%`YQgEscv$1LI8Xv!SWy7&^of=#wx;ol?9Np{MT%OkVb+^^~0^rbF-|ZTEeP3@| zy^jEg-um7uAI}Xl*Utu*=7#2$N`9MNk8Ezts;4*RAy%J62@WxH=2e+UW8q$htx6YS)QcSNHZg zQPWx%MN@mr#w_-xj;{4t4YUT#DlPCF?40AhbM;&gbJ-P5@q6sbhQn5lJj>cTkS_w~ zp}AZ`Rp`n`(^VC|xy`9it8Yw!iv`LWM6w5RkIomqcWg}{9TW56%+dA7aeQRX}=~Aq!iniW$uJJ@JL7!fGvs1wK=B7-C zTicskIx@tPR zd_294>s`(}d;5Gb!K!k?ZWL|pZtQF9%(C0v)8d+0W$O zy-cMpkG(B@-7cNpHkSpUsmpbP-qU(qDqbh53p%HqRr*q0<|^d@TwPXclE?}BeB$e> zI)upeq<}7@crH5L*yt*Q`6;W#jdN;sV|BG|?CWW4aYIwykyx zlD4K6R|i#{xvIaqR-%n6ndEwPmB`KKZJlm92eSU>b%*QaSw2NayV(1xL{*Y5=WTs9 z>9uvPZ|}|~{kEPKS8~Algt9!H(zG$_x~H^Mk!!#9#`u66IjZJRx+1{M# zaeGU)kmlO;SQc27Vzjrq>osonZC~RAZC=psp~Ka1dskz#U%*DLcWa;au4dO*qO58} zS=F?6xgkf8^=47$9L%awQb)bn@Zav19PMre-qF~5Dzocpl}hPo-00RSkPFzs`J`FR zKwj3BjqgO*=sk8hbwReay;``o8r$b`wYa1A)M|%LzeFbb&OTR~s-ktRcMX6~*8n0{ zG$?Bh$+Dgft*g$!8BXYCTuneO%5}a8I$N?H>sx$|*RQFj>O|JBagl~QJm)*GD^TES|7-fH{jYI@SvUUIxZ$ju6-8g0 z^WVaJ;i7A;clR~jt&L6Dm=5`xW%IX*6OO4!NONZM`P349 z#vxakpj(r6Yb5g0w$3VP*Lubb*D`d>IcdvbLpEh}2Ok?;3&~-fPXeySc8}}Vw4C7+ zT;E=eoz>{cjr`qR-7Zgns~*TD*wvlQk%aQ~4tbBReR^72Tl(DkhXrVG=hFlMTd^|nAB6@p#MfCPm#nMw1 zOHWlS>sGrKLXTbLLVmCkdQ}zs{H$ADHS8d+8rxv!dtGOD)2VBp>*AgR@T^6Cd~XOY z?av9-{+v+lRiS#b)ou5>-nFh>MXtm`pUGag=u$|pQ9|c;qnoFCnz9uKV~v}%AUD7E zG-Z0&)7;@!aXe#kPwaS&^OPPm60KAS(@!DG!j1l|Ytrzfk2m>p?&^g!Xi~ zBKe~Bx`(ely?$ZX)0^F4FoO2@^+{k?6TN#dTKJUbpV;b$ZL4o~r~=Rtuu6 zu)REeXv!v$UccP!UF(uv>pGCHe6C&G^j+7uy?%{cRTaJNMvZHC3md4*C+3&ab81cK zE3MB}jhmC1fGfjPZ(sH80XNLPsvuV!$W@hF9@BTT7`b`P)^i#J9IbcS(7WDiLoW{` zvp7!I&AF@Y(|fBQ>Gk5U(LI=fy`J`YZ4NiSE)(nA^Otqa*;u@eC2J)I>Db~5k`67- zVSP(a*5`n%W;QgsoNeGf)UE3`^!RSPp~vgaM!&w<=RyZ*&VTKdx}?GN{La zLqnAko#L)})&bd@GG48uue6pOcT6%qIjmPW%Z@u%uhqiqGF|A6V=8D^o^VF_vW69U zdpA5Y$(x;l>7h|xI1LSq50&-CXrwSXq}O{xqXF#|T48{9uao)B1LMos63FW-uJl!2 zwt`#j@qxj@csac0;a%1MZ^a6Ey>`v_2Z>%GZceYpbqeVCaH&wBaJ+RLYlE*FNT6PO0lOL@nrOG;Frie`BEOVLz0<#2p!IG2^P zV#|q6j8zFZHY-RSLCSJ5S`Um8uvgxcnvBSn!bV~ zDov^mncLK~vh7@{ge-~vG|A#Xe%XqZD^vI2^xS;)hpG(`TiXW6R~k29rFB!EY4gTV zS^Ex=DcVa)7SgQrS`2g)iupsF!kC}6C{G?djxIgANX#fm?*s0IOEMhCa5 zs&*~}8k`zu91AKJAiZYefc9F%2-6;x0u@xL`ZT6ct<`Q+qk3Bmo;62dT&)p0eZS5# zhSTciLc0UB+kno+5HmooBxTdYj5dAPNzQf=hFJqOj;c*n6neZu(ygrDL=1(*ONhAA z>m;mnNP)ClF$Hhduo9#?tgEVK4Po$~btAb{8dZ?BsgdhLa#Abn+cmOqaAs_rVx`Ag zXAbl-O$c%rrch~31?{XvlDa86rwa;@szMZ)ue5Y}9bcPLi;=%C(0)aTau~L7&|A%$AfHeW}=vS8Z9uzDd6C_ z3|6|>GF8fli&Et(U%3ifkb-nJ{7!>u4{DzeOrV~T!AyKj3L65uj|UVBZ#Bc;M72QdRhI7<;g&) z6iUo@st?1HfkQ0m7&SZ@>H;6(J3lxwI94fKN-Pzn2`N-cGEO2YA{&45Q8s;UF{~R3 zktq%vyOP1F()a+Yx^z#L7FlzgNL*{JfpWvK8XoydM@3zsYr!E7gyA}jb<-4SB$ZiP z1Yz3a!liY8>Akjz5pN~?m57RCg&`IL5~}(u0poBNI85vPVayGjwoi=Sf=u_9G9R>R zXrtggYrcS$HVYJomGruzVKdXEyyl9Y=C0P(wtT`sF~KIcnc*b;N=unu=QU=em&^ns z)1z!tEEJ-5qDd=LTCB!rPUJFO)fGn4bsd>yA6>dmRd@xeuDrCwX+5yWOj4%5Y71cI zK!>h&&>}Yz=f~O2rqBZ=v?i>+rzV%JIA(cBvC=k5UTvXoYuhwSX{G8qt5Z>>N`tpl zv(pgPWkZG5TaDIJrLp5lX|=`)y-<+uVk;~4xLk@tEqhaM%0fuXZ|b;B2~x^=^YJ~fs`y2Ad?q+K&bydEnK zph~1c8M#3SDc$Kdr&ujYz)fIbk{eDYvT&&lo&5w&ibd^@ zOeR>K4biOzDR7ygZj@b`69t+EZ9R_a8e-*vswCx*Xk{EsQ47i$CJyB&-Em5)sIqO^ zWNs^JKumonY)G!uu_jiQ=!|S>aWoGGzhn7iW^(KtX7cFZBM<8_%Ap;Y=^eCg{mUT( zREY}#^~X)7Mcovk6co9#8<^i+t(@30-QM%%;BW`a_CP3;x_2BarMu!lL4x%Y0T!(fJS2M+N zC6_wqr?yO{sL6@)Xzwdk!fk8iDjnNVW|IuEIXPg(Pg0RqoZ^g-XCJvjhArde(Qv6L zYBQ_PDcu~?Ck9IW(&uDUj|fr+iD}cbC&?dchGH0(wG@!bXtVEZk#Uj#D+o~Jk%Yoc z2ABHq|7bOAX?gh1vl*`I!~fKMWw<^j{697slsJ9j5}x2p71Ku|Z=(Xo3Wb8k0KU>@ z2v-a;)yt>gnyr@tW(!H42hmedzZf`Wh;4nm7k%O&R!*2a$0#d2_v&QiK9sdw$DV*52?XC;QLLk9mg;s&TpHi4=ZU7E^* zD@r*~9vb5zlWG-WU=5culjqEE12{a!{1?{a=3zWv@jG790&1McQ*m2ojeL4@6S);dpcR;nUUmHmn zylqNRpzuI$iuDC$Om}^2jALjX&yQ_hwQ5a!+v=wN`en&j`;1&kr@m zr?wQT(vIn+&)E8#Pw#B(Xlr89m|`kP_t}R9nueHkeL&Up>v78jIJ$0iEiF`Zw$3uSxj3?rcxkl$hSkMbJ>ZmayXNkcHFS~JC8ON60s__>wLtX7z; zYKr0E@tN|dPggY*o(fSSRuoCOq{nSEdr;3%f0L`k_Rcfe?a+xj~1EVf0AoqGca{rAoM0N|mU_T6Cin#DZ-@6QOuU6$H6zZHA=C>rTu|U&nviW&5jkq*D z@yKSl$dfJR{leKk=DGUMIHFljxeLF1Nrtro_95^vnI9py7>!WImjA-HPIb zs`Wllzt~a88o#OXvd|r*mFWwKH2L%i*7y`FQo^b!N|UV8=Z@x@B*t_TI#fK@$ElG! z?O?-0<5Oj)#jI+g%A~7M@-ufrh{Fp%7YdIVtY1hC(kIyI+!qFl7#We4%EhWmQM*uQ zmC1B`YU*rW2&6-OVRo#l4#MpSvktT0n0`_gezX>DVHo*in6ygDqjZ&|ETylS*ZR|^ zX_X&s^|y6}`QO({|C;u$)s5}_+}rbFuD`Ewb$biHIOK+=%2$E$X0SXK)i!;OM-?+T zS9y!G+Mst-TW+B)H0@Dcx>IC)=9gmWgJY>>bwh>QnJk8|p42@`xW6gWP1Ip@U!w9* z**NgDjJs$OicdMyz8BPrpP)TQMN(f`63gjKVI7t#n!R*$9gbg$aSOsj%F4)NNlb=` WB~Vy|^!JajPKdptUrI2ic>foFDc4;9 diff --git a/board/MAI/bios_emulator/scitech/bin-linux/glibc/ndisasm b/board/MAI/bios_emulator/scitech/bin-linux/glibc/ndisasm deleted file mode 100755 index dd14a7ae41def58b20bca94a5d01a22f5d6ab70c..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 100192 zcmeFad3;pW{r`XOWC8;OCSb5ZK?el|S!5Fdw}3=(!A20ZDq@xi6Ub&VgJ=yT4iU#O znpSPqN|kDDt+rZg5v^zfD!5dGOAU*HiaO(9MWv8xG{5KjoO>rXL$LMp`FwwWnMYpl zv%JsyectDNmV55GcV?F7o_mIAnuh)7GSUo5oqVI)Gl?*8q2^68d`7x4!pJrT8a>Dt z-lST}fP0Ax(t#VKfj0&41cwk82v4+WjYQxHwyiP@fyf(~n!la&_A%)m!O}H`k@JM1 z>J`3=V$aPrjpsf{_XrwE3&bv|{R6E$I}l$D0sX*_zyKhB**Z|PwVJz~4~ya3!y`cy(`Lp9iqKIvyk*Gn4yPAh#Q;VbaPZ^HjMxETH757B=& zq36TS^uwedckrJkeG~F^gd)EITuSm{ehUrSo%me^BBx}EZWv(k%5KWg>QP)bxg z($b$bjfNA1!tc7;~CS>UGU>G&X}8f!Ga5>&p0=Cfw7>Z zyd-EWC?+r#ob_WA6#1*F$X`HEUa_FGqA)*LQc-T?2mMPaiQ+;_@dAk}dBm%#gN7k}mU?6;@ttR0pdH%PLh6ATz&|s*U0* zzu&0xTZxKFf4NcYuP8Q(3rj1i{UTcJ4~k5=$d(qBEKv%yx^hu#nNw|rR9IC}C3^FV zjN+@RN`ij7-6iDa+-vQmS9zFJDqpg+uU=6|+O_eM;ae zeCjXC59U*>pt?HADK9dNCe|I94>I4=S@dOHNoRqS`JK)}DB~!d#Z|^@I)hWzfpjhc zvykh_LVvD=EIfGoy#6scD4&wn9?D z^w>Ws71C+S+17HrKR@*H%PigrKJ}GjgoFsY3a?t9g==jrKMK`_e%O+m6qNO{9e+H zDlNSncvRB0DlNSoSS#sDm6l!)G)ejjm6qNQY?5@IO3Nq+v`9KfrDZe(S|vSBrDaqE zc1qf((lR;%F-d2V9{*|m>%pFLVi(ZVi(|hg=kkV`kGt=aITU$6ysIrQZ_b6Wr@rav z2*~9;Hd>XNhIn2~`e$!rW220(zfD1H_!OZ=uwP_fG_9j0yulql$q4ObXuY_hVTnPx z7dPngb-Qn4=*^AhW<)b1w?9s`8|xp1qSx41e}6J|M>2LBu}sBnOy=E`jIFR@u>hOe zj@h1YjmHS}j4xrfMD~SqGu&29LCQtzh1O0PG2qA zi%xr=$&9o#WXWd4i1w9rCF<@UZn`JjmgQafq!e@4-xhUyI(EjOc{jN|Gk>me|IM9o zgM8r&@3LDu^Cdl^!R>jaQRfY&+%D3RKZW?ldU1zLY;9xwOlriht9P=&&I`yg7<;LlxESjcUx7pM9<_3ckr`JEmKW?1pWAj(^Q4fatE zotF`HC0yg1BK6mzCA?0k5jr|r|2UDnz)8t^N2+==){5cr-?MH8E`b+SVtKK@X{#bl z^-ZCE+9K)Z#Oc^R-%;+?1Ivl!iNhIdR+U#It6cN7cp+n>>dFSPx63rhuh}R6hCQ+lq{?%#!SN3No z?6LgTza92pK!qv3|JRAydbO0;h9}47iAg;TPCXguao8PaEB}Av_xZ{ChB)iHo9Vk~ zv^`vAC?BffvQ!Nhp+@K!+uPSBm9(}w8h?>q1ETd(`~_JWB$DEek0x90cvxxH12Nf; zk0v!Qb87yEDbtu#BwF)gt87KTcPL8wwNudvPDPKaxhE3L4Y43E){A>whLpqGKV^Af zjrl(r=Wit&^vC@USB=Jwz+QN^%TH5Q;&RrW0UPV>%SrqL78Yy?eB~&6NH=9`4PX2T ztL(RqvLCBjyXvhqGUIY{BzoPuJ8k$|XW8K7fXBgE?cfX!WI8x2J2|0#3C66lyq49_ z9!>V3$wo@A{`c(@Ph{#De-ulKbB#$D@ji@9Y)hQV^>UrM6oy!(x6KNwjEoqXZ^A?%W+^6$mBUO7c zBlY)^8D1yU2=(4rFZ(39<|g{m9~%{ylo4GeCCvFxN0l8@)r<^Pgx5)9jNmEJF0BeQ z;I~+hz2eo3=qf2=u9Eg9O;J9GJ<4MFo!(i_oxj67jhH?)cWw2L2uJ0v4YwV+Jj=E{ zEzzqnE(ZhH9aUqSPPl_Q36!g&YU7gEP`_4X=B~|)jpIHn{9JaV{%*3u>x3G?W3=+A zDsy?Z)5SXPD!1$(oOHUU0 z-_&_)s|p(CH$_&-?g#~u`bvq+e|psXwUJe)>)R#ffdf3=n>hM=pES? z&u2T2Z|l?yk})4-s>}G#iw*u#35;(_n2pg@0rFnlz`i}an;kTJ%sM zMbD{PPvYLj7dJ%q(XP7PZl=g01M$3ArtPfA`m}kTIV$g3C6OTx3@%o873qmW8JD@9 zQw&6xq_34AQs0iNL?WtU%*}>+xu497-KaEVMw+H7&XPfam&KG1_9#a$GGimHYWGDO zM9Ik6p2RP(Pu*8h&Hk3i`nvbc%%Mj8>!FOb%rhhY6ja)5F z^Emi0;&okkuFPSgw9i^O-HrRZ@XXAkG*9{{epVNr%jR)tV#LRE;kj)d2O37ae^*{s zrbpGsVT=*~7k*VmCQ5FbX7WP4m)_-lnPLoLa7cj4b5{9Uvz$;U2-erZ7bIVazpseEbGpM4_y`&0Ot zo%T%;{)!a7uakc<{KP`1Unna+xAZR+{+Uj`C)3&fJA{9%lb_jzzgGA?;j^$9*4(41 z(X9GbIMPF7DZpH|c;Vey7s}~Cb6bzd3*nE_BBAzZC?ot)&q%0^iJ!)OW^Q(LURxy3 zqaxYSs=?t`-I2<{XpJAjMo-z2y)nm4Lu8H0^wvMF{Et}n#u*;wX2-^y3<=P%F((ry z<=T3BS86}EMbE_xCfopmLoH9cftw;Q3MI$v5F zuF1*__Eu@PI#9`NXOdzp?+U&j0$UuGLqevwe$vuqLUyzLE?s1IP>|cvF zBKxKg&IEbjG7tbkPz!DXs;wEy9~bDj@`v_Kh7Y}#Z!(lWv~N^DSiZ?{_$I^Qn+)4G zyRq*vW#4XxeQT*(>}w_51@?e;;JJtALm&(IfbI)rU!{&K`-*g2*>|yyEBnsX@uS7= z9359SP112?(+D*i4z>D2Gh|YzJ+e-!Hrdl*oJ@y4Oov0_YtYNR5p&|C_#af9^7b5% zc@e*jTt{Aa^CIZr`@Y}2uq2anCetxzQh7|)uJb98#yo29@4EDIHWq3>H|!!=U_H^i ztjN4}R@z8z+s53zw1C07M+dtlsH++L1pzk{xw~f*N%U_d>r2V%N!B?;8d*CyKIOc1 z02g*yr`o-1rbKFD?D)bpF=N>TXxj489kXLZIznlQp(4VSlPw};ZZxL2g1xyNEJPeT z6aT=^H8FSSJc@YNxF{8F`%%ybS>7|;)|0hqG&c;v!{wed*S9f;TMG>H>9|a^M3#=r zekdV_p}o-Dh|cuTw4}~cR>KYUKIK6Pyoo`UF1cXX@?1x>{EHb{zDMZtq>v z>9*#!$V=wy=1Y;y&F{IRH9JSu?224#O3R}2V&U~|k(1|H#874Fn~d$`h79A(eJSOESnGQxBMcz-o4Ix z84b@&qu!aycwP10ZmQm!Qgz*HwYb5qeHoX;*ns6+5_Qw|q*SrSu7YBRsKSSK7T*0G zg@3e+JA~L_%l)?I*ue_hev73TKR*`U5R1HP?la$weA)bgn>~+r&8d-^?a|Qo=8rtl zYx~UXwV!r~1E}h7@6EF3BzA=N7J1@tSG?;#RlKX4ig*3j6=(Xq_4*>L`{4U&%k0t& z+ZEqWM|O&i?5Vk#!Na?6erDtXlXX9Kr1$3idR`pmz2#FiFZ2M|`JcSCvm0;i{4c#_ zx9|Ju=-x-)Pe)fD;ecb8T>?FBITw4~@Ya-uA27LEQyMPwx;15Tg85$F{Flw+)`i)&&hq9w7TfQqt^1Mm{d9C4Nw)V=b%^&~Il$pA@m^x$ z_Y%@B|6U?`5V8;IvJiCb8G9i((R=f8x+AA~Z}B-ga?^k6$W7gJS{wgiPW{`Vgxm?z*m-kc-a6{b-Dm&E^diqRj{2$2bS;VHE5iaIzA_yHO z>q)3D?cGNhp zC(EbwM4fu}kPve=+hufJ3%e`xx>Z+}UDx!^x@OB9Y^ZVZD#^$`^0!KU-*C2E=o#7fRpw9K{cDLeDZUwEIJ}ijjZja>d zwCvxQy9;@431bp)zZl7V1zJ1h%V1v>e!)5Gj~F8)ylXs>+1&Ga;$GdCs=%HQ_hRt4 zAEZA#ak+EUUY{M7A9oJQTm$4Gpl zj$bEnIlCmkNaBa<_)jD*XUODVC~>)mPE3~Zf=$Jt%qPcT)2P{*k=ffZC^1;&FAQZq ztMY3yBQ=ahPr|L9xxB#9KJwC?!QSc=Kaoya&ZHx`H_1yPm&vj~D6d#a=KYcgN}_%y zbYr~_Dt{a6r=U#5a@#OLJ3o_C)X_V5YfC0Tdsy9%ze`8R^DQ@p^H|z|ESTGYESetB z9?hH+`$Vl`gQeEJG8DZl?m%*5?j|UKOff2J0bt^mrDW=)6|v!mMhEUf{|J zzt4$!kozkw5WV0!&;HjVEyIl*j*Oc^p7;jT(f03@4~;)iK2ymvHaZp8y)T~y;Go)- zs7%SvR0r5ceRnNsiCoV5yKTp4E-{@I&54zLq#k>zXK9&oR*iqeF^N93r6adBzLj1H z*K9I^mutZp*~5(vb5C^k;PK6ohLhn&>xE8L{kLR_PDNA-2~J?5xqBnIdm7f|P%5%+ z1hnC=(sxl6Z+~(;)qVNfaBjOho-IrnPi>sduym*651cXOb0edWv%w z@5+6s;}y51k8yyvvvDs$=3h8p1*5?%a0hv7K`RKH?x^yEe{@zE{}Xz6?mx@H-{9om ztoi3T`1d*ZoJj}fIe06bym^g*OB}q#PTthUzyb&F$4=gm#z2vSH_^#68}0tJy%nx$ zbuDovxRtVo$bhL?^*8a9CNwo#e;F>ziw*i%TC840$Zh3GM=jhrff7d@ue~KDcr-{i z@XVV!62DV@if&d!(d9%%IM9U$4`zoI1y(ODWJ}GJb?djknHP z^##CJD;EGZK(Y+IV2o!h#=qpPJGrKImc@ZSvCzBXBP?}t!tbk5_%?nEgdE0S|N3_u zeB^yK7&VQ#GTe^nWtYtmRq_Xx%TD^_i)sgC6Glcc>w5wR#M#*3YJ` zj8WnS`8hesE~ur;e81y}7fcakU$O= zFYs%a_BC{XYD2cQ2J7Aau{5RAU!5Bt#_D*e6UMdy>eX2lsQ-r8$tiUSpSo8(dEKBMA@PTt{O1htL@GUJnLxMSAXvu z+uS**p6=#4!!RA)5j>|mOBvduzjLYmrLzh(o>(UjwyKTm@UHkH?C?4@@OY))vFseA z`f=Y`eYT_e?iA3pN#?Q%-LYueq&a~N4tKr$io;#s*%oBEaxzA}D|pYDi8PLhH0mG? zXT_hX*Q(3@Cri3>zoPdJ&s@gdVaxt4k#jR=>Z->aq-wn~DeLkA8y!vE`LZ-sZ};MI z{BiJWKMj=$cGmalw3IcrO4X)^YNGfcok2Y^InVrG)YIEhk3F>J%O!3Ij?W9c=5WA{ zmpc1eHq;mM=Bm1W=}E1RN4Sm4h$!zxYu-FFqDE~;gN$8mq&zG0-q0 zEvh1EDw9_x)m8XLMQ`vVnyF)vOC~C+^I}_GR8|lVH@RLgeB5*;jE3J1Mw2=gk>}&= zrsWmJz&34tUTl~)UA;7{-&0cW=LI~qh7mhaX>{M0!3ToErwBDdM+81ZR=<0Ftm1ok z*Y6ai#?8HBdZrZP&w9TyMM44wO7`>wU8hRc^H~{_+oX2xRR5!fNiKP%CFpYVzSe&wF#CWiC-sR;az%rE+!53$9bKCr+AI7}TatZ1 zt8&}bNBTJL+THoyL*|8Z8^hYs%Z^yBdaTK#JsMum$CuM)xTofNs{3$G7N5(8pRv=e zkEMlsbPM-(TcEGf-Ry~u7dx+1%}CZ4+7lTUr3IDlj=s{jypW=oaP=^wA=@Ao;!E|~Qr30e>yGLpSKLV9gogdgxb#FmBmDQqdNN=E{oI> zBfdhvcWn>9QM_%+JF6^2o#XFpcf>IoU5O)+OB^Qe!%(yrMK{tYKI$u{f3glW_+$3i zX3e@Ui*aLr){=L&lKZ4G3g@<@PKZ5FH}rJKoTDy6Sv0I={^+ zFK;{tc}Ji3nnlx}lqOGPL!!SL8?2@$S;{v==6|PhY<21uz3fELdCBw2I{UpOkG6T3 z&W-REy&0J&<32CevO%}wyIP@+H1lG)s;Jz*%X{qe_ja}k{qr(r*eYxO3zfRQlC1_Wi6Ac4yv2&tf(F!Ymh2gJ7ri<`KcqfE%9vEdd7t& zpgqSfxKth_btW%HZh(50$Ns_Kh}ac>h)B{NH1ip^+`YoZ+_)UED*bJl&IE$U1L zg02K-U0PyxTVjEed4AWjS6XFdN7F&siO#Y!x|S`l%5rg4WqFNoFUM`2rcTXmyGqs^ zZP!NmdoAtfDL)hG^UWV4^bN1nOBzITx zAy=~Rj3BLof*=YpPBcs0~)EYQ~i$tK7 zcPKlr6B*HYd%Ta#+peA?M(4ljTvx46=kSQhnp*QS%=zqW+AtRXv`x*;Snf`!_t@Kq zlhwg%wOr9Ctu1SB-s#~Z=JFo-n%)hAO)e-h3!bOX+pTL;avk58p3Rj@6zl88YDu!4 z=c9Q8RdoHgm`GnHKWmVY=UpS0o9Hug5s_1zJX+e^MrAE?Vj-QY_Ts|QWfyc?_NFBN^Z8w9pca%-YwTQ_0nT{{7vN(Jl&=SI*;ty^cs1n^egYiwy95k<+jm1iT72W zzTV))>V6%wM7O? zyicus)RD)6fwN^#kQtqyB^!c_L}p`Pr89>woggXBiGBPxr9;*mkyLu$(0N_1wLGNe zPUz%-Cx@G)Me0MVZWiQ#L0Ud@)gEr5M0r*hDf#2cP($i2WT9dj8R{e1OIQ0hVdG__ zIpdrYdr(&*Pw^7ZC+m>0;fY>sSLKbg%Ihu}Q|DzYKO`}*Q73y#Qhkn(>t|l0HjB^6 zO>JyoAkFj8#`D?U%*l)0rn*CRSPZ4;%tl6&V5oQ zF9pb^vt~eGvkZf@=m~1G_zxzJRNQH5ro+^1850g$^`7Pup7p7IELI;?Wel_hq?4o{ z+te7Sf65vIsuk1Dj7))}8`RlpI!k@zhs&iWzC>MbX&D_L{j=PaxU3;}PZvMjWGn9c zfJ6hI8LIJ^Z%1mFdu`IMjDJrw^XxgXGuWW3owD2%abnQMx0B#ic`BQcxXbbt5B$$< z6ld!FH}BNzcPYZVGv?MY;C*!bfWRJc+991Qr)SZy*h2L&TA2c>D`;SQWF9vldpG7} zGu*jIv~8S`rDD=m;sD`G5kBc8Gla~)Nd=MCJNMUkBAa>2`;??dzNCuC1W4K&7g*Cyj7gTE*0#tDxzCYtv8QvLce7Ds0Hr0ys8K*I z;{9lzZ%%BOZXU_JShgLfN>Aby$6VrL2e=f~YPd#oGDl6%B0hCShWF+=+K!)2vrKN% zWg@1k!Og=^E)VDPhPfyD6L+*KJFPk^Qkku~MTUN~e&ye?Je_|m3l<;8Aa zqvuPg&Ez)oXqm@tdGbKhQG-?VxF>W`CkyL2IKlc*+sII+Sef+whR>5zKz#cD)b|&q z)HU4~f9YFpmHm5cU+TV9Q{J;NM?RWkpO>k7+wf9rEeoi=Wm0;gbFxO|4JI-*FJsxU zT0VNVN5+P*l|&C#Km8t$rBjM2cJvZo+Qoy}d02vsv`Yr3{UjrDF)H=FWS9G6TcfO} zGrQBmh6y*yrY8E6tWlQ?jwFX`(xjvf2k2M(1$!8!Tc0n|P3RfF9$)D7+p;`slvv)~ zfI3MJCA*Dtd}(=u<>i*V*zCvk;F#ZLCfiJd=eJ3N=eLcVuLj4mgBl&rmo>P{bwdqg zRvBfd+@t7fGp5eSw%)xXD=&5=9nDg!*=i9{7wMerv>Ck8mQmx9&){&qgr&|bT#1^* zHfe7=_t2weWk+T+S+We?`?*Z=W@U|<-4>a>hh6a0+$@<+S?p~|$rNIBN}Jb4i}&Wm zF8zyc@$5Y#XJavka=lr}i}?CO6irMJ_MaYzx`n zNsy7l=k|4`x~w`5Yd-(8_Jn;{qb!-4J_1F{N7t!P?mSjYM$*7MtD^SZBJ8q03={-kYaOnZ#SFsO=~~@p`1OamqisrjvM-tfrE_>)lQWy_nV!mgVtVR=~xh4 zV8zA;=UK7Sg6CMVoZxg7>rRb2S2@ZmI4qcL#f}d4vtr9QFOl;qWlg+{A*Q=*lv*t9v!+FPtGVB>BeYYMr7XZ29EeS zXU^TN@9mD0^^5)KZtpX_BQG^%+>UcN7?kgkyD>w)=tJ(tcPCy`>&_nT_ZH;_vZti; zoii+4$Mlg`l6amc_B63Kt8cn?xYWe25#R7=r2 z>fNTUidburO%qum@sX+>)@#4K^zT~IBfc7AXiO%)#A6C1@dh37Qb@e!)ZcBQyl9(kgihJ#7 zF7un`CYG)-)_PStWt8KbU9Z3Qt1`)X{~PrcZCvW~yjNZtC=L-4&*T-JuH~!j^0c%; zy;jZQ5sF)bKq+y@K9z3|ljAi#cI0$pt&n(=9Ir7*ax&CfAj8EJrjYo3FzM&`uXJd& z<=A9fj^e%ezaVFig&Q+(n71R@xzT}gdEve>GH;h9%4djG?8eL~^LFU7Bc2CniNrSS zh@K!aqe8nPl^$D0y|1^?=(ITlbF@r@dZnDjPQEQ?S6=Lkgf;JVvz6~UoAV}jVe!`> zw!O7eP6{2S3Q6O+<~;_J^Vf&ElsPptR+++Abe+6)0uLp08 zAKgXHQD2Ik{V2CqNc?k*ZH&uX!kuLWa{y+&zKwhZ`${(Tp#5mNPFLlc~iGBtg&h>coIj%ZM^yp`Bvvqm) zBHTabG)f^$K_3Z4fs4(*L$z>+1sLvt3r3YL?6ArkbTMRr8mHCOKRohnStd6kn+GaOFo!SMpvs zJY{)k+0C{P~*L= ziN^$tqHg65I)47Aa{Am?Zsx;NmhoIx9SJ3P6*jW38{63vQf|2#Z=L?Y29EnH-DZ-I;u( zjhk3`A}a@L+^3G>JdSU3Nlz?hZQ`CSP2Q!kUm7wuMK&~l%`+$Vs(X`ngR-~gUKK~= z#RlAOUDCPE%ZKl3n5vu$wdt|uAVfVD>KIq zys{xtxr21r?p{5mlP}ROe8qG;+miP@!l#HDBRGt8O4f+Mss;?_`?cr9F1pV$otN)j za!#dkL+?tiJ32qZmL8y`V%3@xX;R;rmWGwlfy$yx`NG8x{S1$Oo2qhyM@oUdQec#R z8j>t7cI$cJeD`CwdMtrmrzyMic{u8Bbls5qwY;sijQbinc1g=@n9(77m9ImG)Yg1` zRInHHSiYZ)HMJ(P?}gm2kMcf~`?d6sG}Gv8X3!0j(?6ceq~*mv;{-vD_2uweO430b z8w_2oykZG2d`EkOTIcO;m|=28e&g(~Z{V&BEor%X8}eK)xYQ9chv%7{eF>Yv5&Df) z0|Si*WW`pJ;}Q;@(3TflY}+86j>R09+SjwUl=S|!mnji`|?A<3f~BR4TIm5C|T$) z4~|r|snQ`IKU`7mn>ROi;soD_i4(?Pov*B-$UjoC3w+}zD}4n%_^N1msI0(W<*O)G z4es?1_v{*sE4qH0l=UtR4lE8r)M7N&?4S5=hxDl4i>Ca? zz0_YwOM?Nwud>Qt%#UgKi!AT?O3L|FjSvn)j7D0{8tuz3D;n)9yt=An>1ba`QE+5$ zAHy@sp1gS6?x4!m-@2Yn2rTQ`rq$TF|A0o8V)%7fLb zCWS#a8>*KLI@u_s&+gB83zwgk4x_6b1~mp{$_PC-@ceo>KeRaG@V9duPySv9nvqJY#5BNVMrx{I>Git4KrEmBl+%a#^mUv;nqNG_6BRs}_rKxE5Aq>L$2Q3_uo zLXB!wlgyOrK&V&>2CCrG;_84D3}Dhi;THSL3;hO0iXJFDC{-7Le2V9nQYXDsogXMR zs;t^oh}Np=G9YzTRnsc@wWO+wQhtOfSS|zsoWfFjl@JxXQes6y3XH0vU^PNTVpdgA zWtqgKJE{r=m9!EnwJ>rjr6Vgt)q&!xbWo%NMe}tYztSWn@)d=s{<}&tRjlYrJ60g& zB`=WV29n%>aOo3GL)b2<5cW!FC96wxwv|gA@T5dlsW7TasS7IkRbm}f;-!jPs<@?! zOYaCfzewtnOJ1-r&>3Sg+nLPiWOQ6I$|{(QGlOtZMWrZ&QXf=^7ywln6tAc>D$AB! zgSBN#%5_kxgN1$-hLo9Qp;EC#f{+zfT~(+vs;)whaH_-)%!;z=#iEa2Fw}v#sVsk~ zO64!rsf8-9s7QQXmS3o4xvDeYDoZAay~Q|@CP)BPgG`4d()waXLy34qN30x@7$UT! zTqtWwWidbSwJ>OftSOTA(<8+)@u7t@qj*9IaW+6wJsXx_33Vzt(kg_lLY?owQs?`x z)cO7^$Ln85K*aRRU!a*EvNh zULf>JA>~0U&=T~tjwqECOG;&7q?jF8*-A^kW*KyiC@(3OG{Zqr6|Y{bswrjp6GKa@ zOO4Wsippygse`$US>;K?@DEvTg30fE#lgDjj>1wo5kQ&iWVtqaJ49{Tqpq< zEWJV|3K=hCoQjT9ane`CtAEGNMluK-hT%7`?L8JKU(g{l| z$Lr82W{`5HKv*qi7cb=p^yueeu4s__GNV|oMU|CSr~@`dD!W7n{8}9gu$o{n)I1Za z<7CKyf=W8bZ`4UpsB(yLsexj1h3pfsn_s&NR#L58+ptGlWf@h){S_CX;>ut?1zED# zW2gYiZ`_f`K3*y#P!$nMP32mP4BX;!^+SWj<$iu>uvqTbBq%KPFEwPYQ$YMyTv~LE zkV=@PMWy8vRIpG76R?2H30PNJq^c<`l3Gf+a6^pZ672#BBq0rlLgXh7p@lk2RaBw` z=q7xwdaJlZ{7r%Y%5*h~)vph7HN_f#Ss9L!@|4kHP#u>HX-<(}*PwiA^`2G=mA;ce zQ3!J+q=Rxhq+yaRTOli=Ln~=#(>U$7!T=@}s74h?bFi68l;!yauqG^}pSUqH^u9$k zft7|i!-Wy+nVixFMGcHMXfumcQ9e2O`9|SYMeM#<*$bBh*`7?Gi4v=3)wO(CrU}FC1DHL<*A^MtuGV1uoPF| z`$Be9g?P1)OTOA1%B(M71uS5DR}eJVW8||#W+PNkU2GIogt&<0S5>l6E*Hz?%Ax~< z?xS+)N=1nk8u|1{K5Ifg*ZX{WhN;TSr!rPp9Saxx*m_ke;#ZWLA0vPKWC&*mMuo&G zBsQEI7Kp)Jk0Ez7KI1AJ=QE0QQ0~vK^0AGqs0#WFx$jwO7}JbPMQV7pO3yd0)J3^T z6v1K<;Lgi9Zg`O~yim)W%(7lZgN7HK%4m`sD7jm*PG~r)sR;V~Z23Uz~rW`5a|+s4vTx$~F&a*mD0l7DPB!hw9L#m9caUoK}S z(|q5lz*Z#}X?`;rzdYvgwEhr33(d*sgWhr7lf?i%&Y;SYC>+~)mo*QjnD zzwce6+`bv=CXSmyeaokB?KouQVKT=hax=)yCC_KL$YmXEmXvYW#tr8+LRgrE z`h_YYcbam`scuZ=22}1uxnW(%V;Qt^3~ihT@fG1K~o5?v$t^A5SN?f0mKv z{ZpIKU=MUhx99=AgHDrto(*G#k6L{z?H*b!Z#r(L3_Re}s%qNmujewLYTmq@otkfBSY zTP1qfC3;vT$j~KvSS8$c3Aa^(3|+!)l`!oRrd5IrUBa|Vxa<-xs{|Rkgv%;n*d>gm zVv`Gf`IB+89WthK0k=I+V z=nC{PAw;1Hpv)0b!9)@j1kg-T(FZ&!2JNpMDpu~Vl~(Snl~z7Tj`<+1{5`2=vtC&U zZ8le^cGZhE6WV015M7f*>$Pe@x<=8Zv<%19E6sKF%768ud5mZtgXYoNfA!jb1k^K1 z)dOudnGz^q=28!|$s8fX>#allA@n?Cn13+LuMP7X!~D0@Zmz(NDXNUJz^pTxHoLrk zM65*zq#mArs7gwR`sVt961-6_baTDbC0PVyLCI<|o5*Q0UzcbL1TDYSIwc@=zok<` z(YZqFq$^OcLg^$+bgBed=p+Z75^aHCeXX&z#eBrrx><<%ClRg-Ywv}X_rl`6A>zFu zcyF-wURZmN0Ph{Hya#PI4^!S7q`U`hGP6~GG_TaQtyH$HRJM^NwyDJCm0}w?*e21I zm4^8b!~8X#{exKf(^^@ZuGYHhw5~d(i*BLmWQi`7*jy*N$U&DxTU5d3S}j$pq-vEE zSt6wpo9R2Vi5#RP+EQznFJ&9%%Z9n0V1uy}TgHQlU;>ydikib(YglOwE3IUSR+ZSy zCDd#p2dxrqQ3ac?(^A(dsq2&!St6wpo4MqgP2?aY(U$9|?=#%1Xp4C_9dftvI%qMk zAbtgL2?IVd0$95!!{}j{-kzer<9bmH-R#L@e&?YoU#Wt+yag%>b$PE)QK-vXqM}fj zcae%hUEY9-LS5c}t0>gv-J+sUm$y|#p)PM+MWHV5JQanyyfGDpy1ZYhDAeU`Q&FhP zdnJu_c{i&JsLNZeGTu-bP?xt#WxTF3polP{UEcRp29y#i<9(F@rNs48;&YV&MXAd8 zQe{99Q5j#T45-W7w@yecB%v~)E#@j*yb4#ZBA!n?pLjlQPB+}*=v&k{f^PO)jH54> z?z&h>U!v%xin0lEdEZh|sLT7IibD0yL{XR5JIj1Ra*dT-qmvI<$p>`u7gq8YI{CPjd|W4Q zvy!*zTga%NtZtsH){zOYO5H^Arc_^6pSksLQ)eMWHV5H!2Es zdEZe{sLQ)uMWHV5rz#57+ge3k-rXt}>hgZ8qEMH&T}7cT??M%Yy1a!d3UzrGt0=U^ ztY8pU7-l)aXCyx}%zqO7IEy&M{3uI?WnCRhw*+c2uam{RFF9sk7V`|fnAhpWoPfo= zk6O&3&1P@4nD?44^3W#JqZZ)(YLS9+(Z0?wWv5{7SIZrgJhjH{SJxaU8G3W@1lkzV zYec^aB=xM$d`4$VVEz^he`}aBR+dw#qAqWRYBtp6U8ZuOE^oQYg<`@+y_?vmb`vki zZo;#chI-ZxGCYrxYBr;)Y0zf#MkNwaO@lU>H;B4pME%i1j#A_%V#9co%4h1OA}*Ndm{!DG7d1d>YA zDS{Wxog<7*LS7Q`qWPXAAukDe(R^Q$ke7tCn194?e>BX8u{0g@R9E-wRXyq!&eXO2 zRqH2c;_A;Oh&mtFc?4MgoFs&rFG{jOC85NhS8=EaxwH_0d5^TRL-jcHbrqK!wU>cP z4qF}blcCud`pKYdR?bg`WRnw@%`oJ3A!cF(Ss#obOOe+|y$0(wW$H>A#jnf1YM8GW z=I4g_cNynp6e%;zQe}WzfIH;s{jIFRIdpyw{7)(OsbTIW`XN_YA?7Zwz-CF#Q0U?u zhClH^P>Ivdl37Pduy|HKaYf0j!z7TDwEGd=ZUUOPUo{cRFjt$o{c1l0C4)`OUcsW6LhXe3yvX zD$G`4ZYSAfZkPI7>xC-}5onci+eyNeN!Yr=Nc+_e3cG&w4tBlcX(e-;nE8%O+AR>* zueLB;po-rjESck5*nMpI3VaQ|HC)?v5q_f-$>@5A?eCU$@CEo6XaipwE~(3;DilaD zl#;w2UJEKd05oXZd*FRBdy|+gL}J?^m@RXpwGN4Yf&};!>;`f0iRhGuZK)?ktG9TX zNNp2Oyi+UrLf)0+Rw3_7*{wo$h$TCu(c6UVkT!0+&Pe-}ShZz8sduI3twMH)=nm1e zO{o*ntwP?FHf zgfgM)n9xi-U>~9!~-i`1HekZG|3ZM_jvg`8xS?3Xucyzkl?)*+} zcOd2iQcc~;p|U2|tyEXYm2!nVg&gw~u8=3|E96Rjg(P5EI7t=&q0QzrwFpd=8cb-D zIfa{TCV{tyVSZ(p?S|QgwmVUFhiZ_za&}y&7DToC?@-rGs4S5z(B@rgiM&fKk$0&j zGA2tT;Az?$f#RyWF1YH3%;o)?<`O6_TW2Lp zDCzq&mwsAa^o?W3lyFxrWoE&pFo*kw= zyFz=G00l=Y1<+>mDCJqMyLcAbWODTtjkQ{%y2#h6BZG9&n2tub)>x}G5}+|nX@oYL zT&PfBDvi)4uU2@SR(PE<@j5YapeP)O!Yr-uI<1fZg@-7G&}MUhQmD>1OgY{#Io&W% zGt4)$4A+~z4f8F+w+K(vAK^MV=JveF572D}uY#AsCh$C151s{2gSFss@F;i~$PeB< z0PX|#f>q#7a69-JXaEsV59CMimV=*yt3WlV0E@vwAU}+E1-J~z597%X;>`i)fwRFG zUkL`^F!@*E61PlTLL4VK}^aAO?1mEm-d;Sgfg3rJw;6tzzYy2bi2mBJ;0#<_MUcy7zKudBf%ih52S&w_q#oN zz(-&Q*aBL>M(_;yD|iU32CKjw;5N_*8o-U$e@{2BZK+z;*ncY<3% z1Gpa4f~!Fgl!Ib$1-KN<13w0{z)Wx&m&_ zTfpn!C9nZJ4c351z=L2lxC`6{8o>3S4qOeYK?NuQ1zcYN#(?4A z2yiIq4>Euoe6yD^4n6}PgAc&FpcT9UUIj0Mji3qq4Xgow27d&<1FON^;FsX%paEPD z>cCGy2vmYapcv$X`CuM6AIt`4g44liU>cYV#)Hw|Sa2lB0{wsoxWG4Gx;^{B9uNl~ zfE{2PcpJP5Hi7lvX|M)71|9+rfM0`Of?L21U^%!7RD#984;Fx*fVp5cI0NK>lfh&# z4vYpPz%Vcr3@dfhWM9!9(D;;2v-%xE0(4R)8810%c$!m=ETHv%qQK1TYF51AJf*7yvRr zI{5Z8<|_CX_zc9shhPWT0^R_B2b;hK@CeXt$0 zf;YjdU=!E?)`7L)QSdu(54Z!|3Zh^o2!mxH1WLg|PyptG3qc+@8{~ooR14F>kK)%BBC~zd;YlI9hI1KQ8W5)4-@82@Ug8sk- z`1&nl0N@*_(eZ;fvD@`Ff?kHp2=JA(U_1 z9S9D!@+9~X$abV9Iu%R&6x-}}i7&-&@t^owd?UUR|A-%Zx4S((fg70M z+pk#@KpXfM_yYVBd;&fK?}Hs+JJ8o5cp9t$kAOdb`@!Ad7vN_g3hKc!a19873J?JK;1VzwoD0qX z)4|DLGB_TL07rqt!J)tlJiq||PNPr3Ztx-40p12J;3cpDJPn=zkAMfkZ^1p_4sa`I z05^c^z_lO*D#0R92rdN|fOEl_UNBfqJkUTn(zhVo(S!1@pjj&Iq+fiJ=*ah~2&%h_(Bk&&B4qCyR z;5G0fcpj_+e+7?%hr#c_ec&E&C%6?ffa^gWr~yks5LAEwC-OTY!-9B>9W4NL)( zz&J1(3wa3xp_7J__G&b6x)1b}nT_#o-~z&+qDa64!KD?uGt29|g(@xfBZt4cQ*}Ccx2MRNnM3tW5OP1$^*P$m$-60q=XS`g)V!oECiTg` z{MDt%iJdm@niQVf!K+TuDgACDDu1au)tK-pmXWGccy5bl>y-O7HMT{kH6|)7TWp@Q zZ-pn?ZJw&nk}FA(bM~$9QswM%R;cCDY@N=&6&`X)o^uRdo>HIFPT@K0bB@7_Q{ z3ePF$9D{STT+$Y&ox*e4>7xHkA36M;ld99fo0%f#9D_N!zND{Rj&XKU3ePzPCu?5P zPUjdLmm(*2%D?=LOyN1l;87_$rQb~-Lj0xbRAa)YSO@47p4;NtI>m9RV{nLNi_LTP zt?)#<%~SPRWAH~Qa?ZXLUaFiu2K#HdG+U>$Z-s|klII+Q87cKS?G&D~KIa(hks{}` zQ+Q4}=NL4!T+$Y&ox*e4>7rvzA36N}dvJR_Q-+d`^&iaHWa&lfsTatSTqQ)xC zbIZAx*rNK#nzz5OblNR_gX9+y9)7I&W8Gyj&ktYQh380ye~9Q)h9Z09K78rax)yfk5YIu9lV_>I%S;Mf2ndZmh8V&IcLYG z+TwE5cYsa@&(fg)4GYywKvq=5hWXZ|14K*fcpV}9Z-T==ew0X`wk?=&9%@cpxeX%Y@&bbx{FICR& zrzf;rnyu5h76=cyB+t2bdn~0sr=7xc)~9T=`tactIj5b%bIK_jEx8A@T+$Y&ox*e4 z=`!%Aj~xE)N!97#-H{^a+`HYT>r49Dxp%uIh3DM6-KcppXAB&yVSoj%}bN#n5lmOOKt*; z)Nx&)+mLSaoa04!h$MNc4c0nxX^Nb4ya+E<&K}nnq{unPi||BlVmEf4CvusF+vYj# z6dn&AlRT%LXQs$G?G#?BoNZ@Lik#C<;fb6)cQt|3Xa7wT9&M0kv8jKPEuK8TP5qmo zdFr`rDsQajrOET!)W1=dTuv&3^azW0I&ra6&3CKZuoRx%ZejbZ`fNEhS1h^1Q{-HR z&*JbbJB6p_ipBL>I%kp=Tbw$3TXHtfsneapbL#x|Fy-sCvy&EdM!phWj*)&2S!&Gt zhzR)mmzFcnB`&tu`4at7^9MMsBr(mnwI+#k;s0xnDYXsd7KJct7bzuED`e zmAk>>UDAzQ*uhJcTW0Yt?MCiu2QO7FXz?!VMy|raOO;z>@#b4{&Uxh5Jj3QW=g}1@ zyv}M3<5CANwZ022-sPPF$@y@;=JgO>s@%C2Z$US5XF7PPax*O66_%W{eWz%iVe_2r zo07uotd{qK9K6)}##+351XBNwvv>um4ARGFURq%{yrV3+qHcIYES?{pIMUg^>=d4} zeTSs*5Ki_(KL<~>PgGlLos(w?B;|Ug$~o3Sx5X>Q##EghgY-K8|220$;8~UR|3BLv z^ieUV4yB@cG&C|o{tOs}Ibaa#%&Dl9vjN*+)3MEM2;|hMGci|UO-04ToQk<}Dt=u` zxfBh*u0o@v#KNSaT7^YLMPGlf&pDsZ&CT(y>v#RGtLyhY7w?_(KJWYexj*-xbDrn9 z&$A&~I;Lq$0`2>|`b_iN_ve)6w{N$nrE~GMbS}S5`@Hu3Qnk838(#OcbbY4P<4bR^ ziLWCXc5zyOZ_}8UaGcKb2dXuw=Ff@mrL_Fg9Ho-&1=W^9C8qD&l+t|P)2cNFd{3q{ z-}ks`O#xqDO7ndWsn#6u-JjBY-#w~b8t|=6X}<5al;+Q~FRIoOi23=H=Eq#6S}VTv z)~Q-sT7X}r+A@yQWAvGn=GV7OwaWs&=9K39E=g&A+ZU_0JP>nXO7mk@sKNLF zs{-0@RJ$Rd{Zh5hp~a0Z&AC#qt9D~R+m0sltSg|sqQ1`uw3pRqTD;yvIoZCK`0~Gy z&;x${x5m8bfU^mCUbWQ$?U_U?xH+JGOMPDqXiuv4CA4(EJg!=IKzmrVTLLj3Qtj4& z_CTWL-xkpBO|*hF0qt(pZVza8YJGR0NgMpv)LT=Ue;wVN($pT;(52d)cG8gJf1d$iO%t~^u55>)Zlz)rhVSMXRd1NG|&AzzW48G>H18&M-6`aKBhj? z{Ps;tX@2{PJuO|Iucg~}a@yy$?@Ukzx#^R#rI?eerZ7wOid-=eo^UVpx!zOM!9`*sKjx!eOzF>feYZ5n zQ4~FdM(%NarrG+hXcTc;y!NZUo|MmD_ZH231sqs?c{#oZk@)hZ4W@~18mAA?;`O{- z6y5qSd{IENJSFB$UY=5)>wtj{E#Y}epp7q`JQ@yOQhwLvt= zB`?PT+hvLGz`oAKQq-)uJPs9~|D3A~P~d|68K=lsVsW`9z} z0Y5*QXnEf_;A}#ss_)5wHc5R?p-KB}T;=d&G#Q6)2}x~ZHRjW)^FlwEXwg7GJ5jZ7 z2ejiw%ZoD4pvAeA=3J>!sy*w@>^~T(F*of$<&KIHt>8I#X8%E<`kv=hTwiX#c9?44 z31|mt%+0EGc)on~nHG84KaWY~plSJ@wl}3^Jnc`OCf7>*i=3+eE~WY35BXI}^S>XG z*8J~>yq@?9Bu}f)^6@q4vs|er!ttwKeWD%jX+KP9qdo2WUVY*#^|TjKzL}o(Y)UKh zv~Q+j`qypR=U=yJUwrQ*C)v`untWf; z*Q_0)$@djai`$@e_NIKISsO(Y-(aA=`$c0j&5yZGweJRecce7m*R9(3ByeiGInnrQ zVQ+8yjp{Sak9nPHTLQi-6Rp5B-?v<~m+<9DF5VbjDjMI7c{vdCV)dEk$E;TE2Z5Lu zY0Rww?E=yGt8b?HbLnjw<7b;`KMce?TkA8;kNGyui)q@AtP*d3ro=3a3SRNf+2Lu4 zmcPwTc>6h`vHjRPXNNNrt>7ni!rOmLeXnvZ9;4iTahj*a_a(Ia!sFut#Q`m&+R0kq zc1osWo}@m}(lJj6XcjZ4F<%SBe7E{UOUFDWpjpf#HRezMO-#}LRZL$?$NX6!rnOzP zbWCfzuUSlM`wsQ__pC!{gWR)x&F)#E$-T!k|2is2`9zC#>JUwQuLtVeHzJ;A1*Z8i z|E${2@x|j_n&T+h{vaCHpK1QJ@;1%8R!rMPn7Ge~nO_)xJudn+F{PfA78iRXtjXJ} zNVNj5iRNO;`$&uVTGB5rrfPA_SHfBxQ#BWpc=>h@eJRyGv`k7n zz-Mzpda{xF^>`qTQWnE*I4brG0mVwVY_T zq&4b_uNSn{Z>w*=c4OLCSXgMj&%RyDnRazbllc&TUz7UU(fn)0|4y4|lCQO0d^RU8 zOZk#(B`3ur(PZ!YESKiQm+G^e6put>=d?IS>Xhx0RDFJ)qDdL6FV0bYwJD#Ur)a(} z&QX0;iO=OCnzcbRd`^q=%t<7^%MqwA%EeN2eoBkusdjd%zW8&hYGm|z@4NY$_1Q$U$kW6Vd-07; z`NU(|2h{gR%E^tK3(6VDb261H>LUY-LLgY!1zVIl<|}6h3y_RsmC-q?`tBN7U7HM45#i) z`TYBtXlb8af43yQ0*fi6oI~{n}#Y=jj~8WAB$Ls88Nd`kK98IwPRj`=vRF zR$x9^qqUf`&bie@oS4QLkgqls2fK%VKXB+>FR0j*el!vflP^&O;b_g_0sLX+1H zU$fVa6U2vhaKQII_4%6l-laadu;qI2>nl>9ubJ-%^&JxM9il#8Ghar1hX#EAb9B-^ zUo+p|(4>8b1$=)}pRbwk_v#xS@a;-`BYe$#ZzR4EhX;JGX??zCzHM6HI|9C!)#q#G z`>y(q2>8CEK3_B6GwLf0_%^D~*Ua~X`i>0v9#NmKnXgxUM+JQMtIyZWcaQpx4*2d& zd?S3#e77dP5hDV=FNm)r8s=-}yIy=~#|C^?C-ohmnXf&mZ`jCy?=toIn)xnO-#Y`o zOVsCU=3A`3cLjV4)aPsFyHI`a4*1SfpRbv(LVcqGzSGs`Yv!A+zV`%trzXA;?+a*C zMPnR%&0>z1m}t3xZ;bkU&3wnH@3?^Po$B*7^BtwW;{(1!)#q#GD^TD21HOM8m9)>- z%(n+k+BZ7j8&aRIneP|sJ0akEO?|#*z8|UY#DMR6>hm@8eMfyC2>6~>pRbv(UwvZ& zzCQK&n)x17-v*5d?Tg>eD77CubJibB*ccl2Z{(Q}Rhl&sFqXAz=>+?19 zy>(>Vz7eMce1Aie_h-IlzCDR=*vA6C->c8p%=c^cof`1Hk@!ZG2DH~yn-S1nQEg^G zdr7rfX#8`Z;pF}8chO{Tntc|Nb1x)Xfob_sPEN<$vuU5FeKYNobz$9}O8Me-Vbz{c zUzsGC+8#@^yx9TmVfD=kXb-9H;{ojf)#e7Ydo|{10qt(}osO1%e|?e_vwJ|)xhm@8eN}zc0bh^$e9e4!tFI>D zyIp<0X1;Fq)dqZDP@k`v?*{cP4*0HBpRbwkO7$%X_*SUT*UZ8Wvy4}!_ za`Cj;DJ|n^rCQ&`((u$aJ<;+m31}tiYY1q?>RTGn#;evC(8g-arhqm^ea&d;*VNdrHnJ*r9jd^g&Cz{2~ z3uqSe??)UMGvnpC2aReAtUl2!=I;ZV#r#zgv!E?6=`+9WKTmv-uUX930-D8qC5f45 zKELfRrF?$dUkqp#b5km&-}Y}MKGz1n?fn7GVm^|@ELcw4)7#g?mmeLoETBCo8qe)7 z3uyNx^&PY#pxu*b!&aija&CXEcPCnOWx%)A)6%{*Xfp6u1$?)tPqeh}X7zOhd{&=m zX`j`1HG*7Y{(R}u`h3mi%k=>*()M4CCfADj{P}Wu%ID9QWdY4%Hl||w^QA8F6Q$@q)H2=Bpv#I+0JVo>Ci*qDb*}j?b`FV;aWvqR1j_P|N@wr_5JVnFi zwD=m!Nu((1OUI1p>l^~xgDK5_?t5QSpUcI6?z=9f`OkgtOf;8Ea&JxQyCvmI=4YaP zA*ChrEYYq{#f;}mE*vwS6RM?Sie~Q#E#~L*k~sd)YpGB87XsRqiB@n^KwGK4o6%yq zH0Q#$CR+X%5z^OtqxyW!uFd*@7HQaOGJ#n7l+WrjO?jK)ts@)UNdR4nOpgpKsPe8jb(F*PhX!oe^ezaIF%~_X4cZ$Y$@=f#G{x;2P zyJ-&)P_Aj2FZLegR$@v$runb^qDgVnY<|kQ)hVC59#oSuzE9?%Y@bVf1*X~jG>yH} z{P!r=rRwwZ6ixgVQ*x19WxFcn^Yau<%9tK9B0^C(lI^l zl9bPXkFq4G&*kF3M_H88{P!pqC7R2{e~)rO$|rfsKiMi$T5|tPw9`^Cr7!bxiI$Ej zTE1%On4;Nx6pQ)Qykrg*iZA(UeKd>un3zQmq4Dp4&nu^>)*H~Ks`fQ8rMCF@r1;Zu zUk_-L#K(Ud`EWps*BSDngZctm{Cin>(TR_srLUuL#1xBZ{`?e8(lagYGrb*)BzS70&y`6(Jcr}@{>djj=IKC&H~(){b;$W(p)+&w(y^XG0hrTKHWARRLz z5B|ya&*2C5XTGQXC8hau_YaBY+AeL&%Mp+*9Wx$>Tr5TDn4;O-wV03PC1w4ezokAt z`{r*5XulGTsq#2ldcM3adGh*anm=Deli&X{EzVQt%TH21f4+#8_St;-LCWXP7tws5 zKVQC^^7(m+=KK8n?(-?1pQmWP&!1;cr+j{%qKU7c{*1f3H0Orm8=~>rXj=Zi)3h(e zY`$*EP4i-!_GFx-OEEs^lbCEz1+-q#_+9*O2DJ5}vHrO+p!FoaVc$Ya z&$BP1aXMp~KYpT-iqrggc3aBlkDq91pUtz?DW5-nqKR)n^OXBUJZCuBm1vP^a-Xo6 zs}iliv?Q0~aPfD~-{#}G#VcD!%IDAP%h5=~)#vw%XyW(llfIE{S<2`4i)d2Dd~yEj zYf5~s4Sv6fhRtbGSDY&+FHY6x=P8htpy z&96^#kz8dvHRbd36iv$bxtMQS;&Zw9d5VV3Y5CFq*RhG|n4b2bl+S;i{y27yrjN^d@a_gPc(K;i{}w>W&7J<@qOX|&E}bC6glWQ>f@iJ;2B z5jM75IwzLx@;`Cd?Me84vl(9GAb+Ju1b;ecko2UPnIz5)=RFU`fT z19zj&I-r^F2Gu6xOW)6~MU(r4uUVc~sx~#?TP|8@-od_R-$%Jr zwG#Ek=cRpY7Y8(}uST_LluPG%5n2U#`kKA2Tp&KQkEqXoJ*o(3R^REWeN=sZp0h-w zeZFSCQ&gKCsBenK^fmL1S8aBneIE>H=6k9d`I zn1`s(*DPj%YQG5h_8pRpgRhzIFRJ}A;QK>BGvBXO`&GdA^MGc)?W+Ac;QLWZlYTMZ zmXs#vO?&a*XwR!Q6sT_?rTO(esoL*6pVjxcYQOh18^d@lf$=lVkNL3re(U)x=2unw zgKBcEm=^yI95HvR=EuBGeSh|1S}tEsX}<5alqPjqeK-Fb?MBu12I}ifX?}fIq%^<2 z<^M*zRJDHu>XYBoko$|TSsUWt(?Hu7@LjAiea(C|s^xKErtfv14ru24q-rez-#G!z zeC4XO27I#vn)yyu?Xv-2NkB8-MAfbj_&yZS%y)unx8h5`Hog~4UK@Qa_T{2zq-u8s z>N`?n`kK{um}*}R_%Z>_eE*Y8=EPU<@$Z0p>s~aux2_Mwd{ceCW-))O+Jgb#&VXjV zpQ`p~z_%@+nePXx{a3*E-GFAk&8j^S@I4dI%=b;zo(=e(2x#VeRJDibW~>MFb+2f- zyn}iJ+Wo4PV@mth#WACU&kSgHsP>6~)~(uE0qqN_t&S^`ME7qusP+b@I|5ubP~X*96cm3TSamwDVOf4&-t+nzY^5ESEFTr0tUfzB%giHS?9KZ%V-TQT6$n z`6jDxYQQ&MeZFSClhjwDKG$dT-wEoQ9*CI>XcqHb8uRRcZ-n}M&3s3w?;LzGelkWj zeutpR`1xAwV~q0A7NfnzhAp^tmkrDI0TBn;?*f_G!?HOb=ccotug7idSA$-#S-kO{%yeZkQ>ll{Z2qfM%_Ip6#)x)x5ft;JmzDAEb*slfsV5^=Rb4^mN zjQs*VwmOENJ}f&1lz|1H9jpNxz!oqBvS$p-js~Tm6088-pbrd!T_96Vo56H2AGCqh zpciZgJ3(~ju$Xe=7DC=1=fR2U!|d^FbR}4SK<5uoFaGv>%j!d7v3|f%RY$ z*a7x|k)NmipaL|2RiFn9fbC!}DEb2J2j!p+bb_&5kGsL})wBtefd!x)tN|Oq7BB>| zH`69i3M#=0&<*;)AlL;mU!+Z7I+zdIz-rJ7HiMlY`VwsdC14(C23=r1*aUWfePCoa zZ2}db0jvT&U;u0fdqL4Hv*4@yAcUGxE% z3!3ktj;~M$7y#SBUQl!|b%1hE(?dM47W9LyU^f_kAN>c)zyiC@2r2Swzm=D^( zYS0TdgPkDyChZ3$U>;}&U0^-f1a^RZVC1)GKd1l=U=`>A17JJY3yPkm{h%Dwfljav zYy{iD9#A+y`@vjL13JK3&=0nP-C+2)X+J0f3qU(q12%vyU-S+p0F0r9NS{RZ}1^w{1f*n5#RU#35R zl;6UB2xRZ3Pk@{&WnZbsE7*5~J}{`~a_f?E)7j70<8&P(KTey0#H(Q609Jt>JvYF9 zyB_alUo@BT2jxIK>vX@7{Wd+8^9|=|-49SVkaKP9SA$-#SDF zlkRu0->1hCYn8@d_Xu+j$hmFo_khAj85& zHzPT}wSxHy%PGF0*U{hI39i*V+zWE)G_xa<_qWm!ndBr_yaj! z%f4Tah5Or9`e3*A!`KGyePAu<2fM)-##zeuYneTlFi$yO13JJ~FkH*5(D~5KzE6(_ zuTA{B*k?NRnAbmvx$FPaeu(>4X&Kk*9PXoF&s^F~|MW4>Gv{(ozlQ4pv~lm*3`Rc4 z{ROmhoo&%;EsK9Ns01rO7jf2u9bg|QB;Ht113JJUv3G$S@u!0|#NPmhK$gB)O+CF} zCy4Ih-u58(bFd2ZfHl;+0Stkx_M7zK0@~6JcFx8}y>+yu6O5*=Qn34K#)mp~ac|8K zyNi3#da(OZ&J#;wbn^aa9T@vi!Z&if4eSAhoSO@3R4eWyFR&f#1>$dDzY6q#0Z{Y^ z_gYX6>VT9Pb2)Pr$ngU9?O+Yqpy#%*AJXG&JNbiBPzl7dZ#mQzn+v`z&)fLtkHYP zTJ9nJU@MSVHFqWZ@${|mb=rp;*>BV1J-RRa40Qo1H}A@1-^{*CkLRD8oNHshT8}$) zZmnhCugBf@C*}Is59)DtS#oYP`%*m~#kC@Jm9U?u$18Ns{J-wI@%L$r|HSd=HQWbo zXFTs@UaqB|>EBJ{zV6F@XhT>yj^!N zhk^7-Gy5HSJeO;t2FUr1jN>*P%R$`+;8gISsGfjy; z*qH2d%G=nl2EEFMm|MGO(@5G;L>t!L#hjqcb=u}qv~Dn+_O1pElp6qbl-&q+Q@)Hg z@4!<`n>XSs)HY}FW$+YJemrISDZ8F>of^9my${T%OfOhPx$U5nvfIFL;w}LD@Kg|c z8@{m`d*ci^kbdiAzfO-ks3Sh7_qVYZaGwYLpzTxC12%(s7t&6!9u!wHmS6xBT}1t0 z9q3v_-C$%j*Xj~pPe3==1?JZg4@g~m7>h#Ux6h{^h_??6RWW`GDFar6Ua%SL1Q9Vu zff6teG=uHbQB*@efljavYy{iD9x#{tLMW-p3#oTE7*5^oU<24GWyzrn ztk+z&lEZGWi5#|5_g=7(dbfcZVy*>S!EoAH2DX4f+M1!RV(O{@edIF;RujKh^BGS6 zj{#+10T@O663~u+4JakX3eXMe$afz3G;2!2UVkQi0d|0WU?i_+#rm2ys+l%` zc|hVfv+n}y!6vW+$oWY3YnCQ_1N$v{yh7{gX5XjBV%f$0Yr}o&mlJFQI;Z<9lJn!w zXN)*E{u1WNRUCuz4#tPqtTDYwnR3e1fxVO~qFgzs13i=-0DD0Zo;uJ8cHn#2_Tnod*HXNd zU|%!+eJTA7DnJ8R1$w{$*berBB3?V@-pc$0(of~jGfzMRSOK~~H&_SOgFdhkYysQB zZm<_*zC+u=w(l`dz+RB~J~@CK7z>KQbTAiGf;!L+I>BnN2CM_UU;qq)9bgyO1NMSw z3-y2;7z;|lTrdyJ2Ma(0=m1?{9as-GfPOFl2Eh(61frL?w}B!s66C;GPy)(81*imd zpbd0@F0cmlfIhGhYzAAw4lo4vg3Qa@JHRL~1{8x*P!8sU8qf^d!79)V)`31S00zM} zupR6GJHaln2NeE*d_ggo4(5UiPzh>4184*7pc8a~Zm<^gfL^cxYy_LYAlM4FgWOii zfc0Pq>;ofzNWXvzPzjnrJ6H|+!6vW+41vs#C=bShQZNtHfp)MOtOe`A02l)M!0=ZX z1277V2ID~qCo}3c8|^`iU?w;RECMay8t_H%74Rr{2D}V@4*m%8KZhS24<-Vsn@73)8dtKfXFnX|sOxaq z@5;#c*rQz?nd~t3W!Gi02g&}LOjf@8Ex#jr7<=)L0J6z*;pwzZzE2?E^(q2Kf@8s$ z>oZw7-u+qfU@za{JQ^e~NF2!a@maGzk{k2!Pn`F`+{AHH$4wkJ>3{t>%U}9({Dg7i zC$RtDel8lm|?wvY(%&+4|O7ECqCE{;SM3zybcN8{pf z)lEy6);8j9Y-+2ODe-^1y_ySbQTo`_fC zNIc;)ftA}!xxJJd&p9b4*Nv4s!z(A());;{M6Nk0Cw?n8k7LO}u3fpdb5t^xW80)| z***oVTsh^+DYx5_N0WGhDzDsh?jzH=8Em_Vle$S6*<|o6p4>}vbx|}bR+1l9?^2`O>&P;E}m;Vu7%iHy(>Aka$~s{jXhWXtNHz#mFw`z z6;rPGUzEGvD<}81>6BZwKb-5AF3w3GOMY^H-$c3999w;|mppFKy_B1`lh^TidC_K$ zZL?hO;DohZG%2^i3VGVS95eLsCVKX~a5=g6N}aZCq}+o>*jrt)m$9&I41XYZ9Rnx# zaQVBh(heCrnPYyu&6njxYiv-_EFOn%+vNI`lktD#!(Oh#geNu2^_K9Y26^pCc+#74 z{Ultj$QEB z&kpVvoTl!>qc5}HpWi#8UJ-P&_V;=HBmcj>_+{pa|0(t*w`H;tN8%5#UvO(CEB}A6 z@E6(JX7RRBJ~?-2w3UOM#4BQ8B;HTqd<}l)dm@vu{3`_rpwG;d|g6Q+U6rx_ocF z%j5DL@HKFDarq2!`#nA!zRlxD!}ogpUGR}p_xq27mw0>(e7?s|hOh9rd^d58$7jO( zJucsomG=LHOI!Mf+fKC2(?1R0a7QNlF7g+>4!#9m#icD={?_gIb(w6IOG`Mn8Mj&g zu6TNX|6YMU{1-M}N5y}4ve4tJ0{+aV{r)ea7kTA-;3GXQf8(TkFq8ed<}2elvgE+= z96Rm6@$7;7q!0{aLxcohWLHJnW%J{zk-|O)o!AH-q_8lJm20q5)|A3G6_+j*W z_m48!4{5%~!uP;$RX!SC?3Et}FY)+C;I>(R+xED3Mnv3br!e#x%;(Zq`YcW>-6}YU+nEpCk)@TOxdi^b2)@!W%pW(80 zWAWdD%Q}wfhwu_7YdWSM4VU#Di~kto*C+h&3oH{|oqVxW)eiJm=|u zgOBy}0s@!9E#Bd9Sqrmx$HHY@%<4am16d=p@*jdP@XAkyH^8m_Q{f$+ej2>X)6a#k zgIm0d;Ih_c^)G?Tx*NOr`nZ$>S%b6km%|6V^4Gx!;a2}m@Ex9hJABB~?}f+fcN+g| za9PW<`k#Qyx}Fr1>+{gyA;j;E;{AX}k2Q>a`xU2~p{}Wu+2aW#| zE^CFx59W12)(wpx370iQsFm&UJx%Q~j<8{o30Y5YrYS>H5%7hKjljXwaFbx-4u zz-0~8_)~CM4>kTAT-HX7e;+REq{e>?mo-!4Z@^{!)cEhkM~wfVXdE^EG~Ukfkx^v}bm!!6!za9I~N|2=S7BR2gZ zc%`R54wtoKEB`cH){%|B0B`g758&+{e+@2c%~t+ba9MXY{wBQJBtht;1EL_&#$7sCo!euSq%D)1ab$QF@b-1k2oBmt4tk;iJ|DWNqc5m_Dg3CI- z@k8iHS<^RuG+fsAjlTyjYyHMQ0GD-t;}hWW48ZtD;qpAd@|g{nX9LF1g3EIP%kPtL zd1f$H^R0%<^8@SurEqzcV0<}z_$&Lz|7v)V$8Us>^7t)qdG=uS-wl`N5bWaX@j(vc znS|+&!R7gc>EGm_+|$1Um**Cyzr=w&!!ZA=@CHx+1-#AE{{WZg9PHxy|Hgql^Dut_ zO9I`VemH!srymQK=OX4m4ld6~%>NGq^klvhu%%%QGS4e}c>NA>;pq%d;Zm@`q>SxsmZB z;qna0=Ks6l@;u4<>jbzwTQYt!T%I!-p9Ys_PR3`!<@uBGGvV?q%J>Cvc`jvqAzYqO z+4XS=T%K21`0A1=?y<|_X&T%MU#Dt`km&(G#5{~cVOrIjfED_owd%~zgx z821mj<$oAlp0|xseFR*dy%~QWT%N;Oe|-=x&*ZFqli>1v&f0SdT%OgL{&BcGw=?~0 zxIDu%{X)1r&$Ie!;qq+H>T80_b3VKOt%S=nKZ|!QT%P|K|2$lt1zP;u;PPD1^n2j) zjL`Il;PSjMqwRkjF3%24e;O{&5lw#q9zRpm@;`vf^F@pQ8eE<=8vhkso;!}#@^8ZB z8DyFAf57E=q?I2=#qw;@_z`e)pEEd+ zXPj-y&wy95zWM>UtY)4AZ~H+eD~||{V!hxZc-@vv_G8Ky!y70s?UC|J;hR~HvGOb7 z?dW4wzXo3UU7mZY|3>)gH!|5N%5Q}apnqQZ-SFwGPe}YDdH?q?eD}+l?A5A21-JFs zBUvBa1fS2kd?qe`RP;T#txt;nLwE)2O(&}VHTY(){@=m7$Tx}4y$Qa6coiCt6r#20 zm&bnA?%|!^&tzZMc!luZUu3fHRsLT1R{HM|DbLQ6-%j}}wETGZcwH}(`E@GXo+lI%e-1o)asPN$z#42kbL;NmhgS>yOm!7AI|gpyOduCm-R}T73Y5^d=&a*)|F)Z?}ZQ2{+X(O4ZeW< z>KOSCA z|H> ze-$1vKkRz^6};r@ne4GVAe4N64`0vy`3)`qcldVlc@JFjIgA(5A^471CpNt9hx^Ct z-SB3&kgX>=QG(Cwftw`eOw>%yi(fJ2_Hp$&%!1D8{oF(> zuAW%MHxQcZ8)|FDMb#~Bt!>K|FGi`Vs%ffP($KVMVMA5?9fqof%T{o9*1WUMsha(X zvZ|^$PF2marAt>viKj`lr?%8Csp3l&wXIQg6P~vECR9o^>e>40 z#;Cr!DWcq@iQ^{9e!>*KYs0=|TyfOOe%xf5&u&UoBfF_lo9s%W#m&p)U|O_v=?XcR zFg{wbbZLAvAzEHnUtPy>Ty5*P3B}17Ng|^EY8OUJ7q(T`kyq==#%h|uZbig5OynmG zYp7quNja)oy0D?4sk*ARrKPDQYUKMQRjtHrsips07A~Z@eA%S6xwg8V6G>B>TWS~A zuTaw3R?}L&u(7JGc4>1fUp85|q&7O>T>WPbJke0w=n6D9(YG3)x~ZA*WIn`!qlWrM zj+QN5RNE4FXlo4#)3a?YOow{DN<+c%#%Y?r5?*n&OV8x}y?zG|e5& za7Q!U(JXgV=8k5&qd9iOkZGn9Tz(T=eiK}N44;*A`Au;7O>p^5aQRJe`Au;7O>p^5 zaQRJe`Au;7O>p^5bootm`Au~BO?3H9bootm`Au~BO?3H9bootm`Au~BO?3H9bootm z`Au~BO?3H9a`{bi`Au^9O>+57a`{bi`Au^9O>+57a`{bi`Au^9O>+57a`{bi`Au^9 zO>+4ayZnk>e#I`oVwYdB%dgnwSM2gDcKH>%{EA(E#V)^MmtV2Vuh`{R?D8vi`Av5D zO?LTBcKJ8O>y~6 zarsSg`Au>8O>y~6arsSg`Au>8O>y~6arsSg`Au>8O>y~6arsSg`Av2CO?CNAb@@$o z`Av2CO?CNAb@@$o`Av2CO?CNAb@@$o`Av2CO?CNAb@@$o`IWf*N?d*=F253&Ux~}F z#N}7w@+)!qmAL#$Tz(}kzY>>UiOa9V_B8bNNkk`Au{A zO>_B8bNNkk`Au{AO>_B8bNNkk`Au{AO>_CpaQV$}`OR?o&2ah6aQV$}`OR?o&2ah6 zaQV$}`OR?o&2ah6aQV$}`OR?o&2ah6botG6`OS3s&2;(AbotG6`OS3s&2;(AbotG6 z`OS3s&2;(AbotG6`OS3s&2;(Aa{0}2`OR|q&2st8a{0}2`OR|q&2st8a{0}2`OR|q z&2st8a{0}2`OR|q&2ssbx%|ppeq}DdGM8VO%dgDkSLX67bNQ9I{K{N@WiG!mmtUF7 zugv9F=JG3Z`OS9u&35_CcKOYA`OS9u&35_CcKOYA`OS9u&35_CcKOYA`OS9u&35_C zcKOYA`OR_p&2jn7arw=0`OR_p&2jn7arw=0`OR_p&2jn7arw=0`OR_p&2jn7arw=e z!+XY-YThlj^8U1C(aJV?o6F(imfG5=xrOglFHYXtQmkf~yu)ls-rdUk*|<=BYt^#G zOB$P&H%4-fH@h`a`th=><2Yi)C3m)0(o469B%tBN zlAye&Z&+E?TEDcpp_T$xH2xS6i_{l)Wb^WtdK#s9#yzyWo{tt%zpGplk?vhsQ&T0M zGLkAJXTH16Ckpu((MlVa&_>?Pi;q)D%*8rP+CTM;RY`*`T_#^fU))+-dx`sCuxQ!h zX1)*7zjxO1%r2gYxk# z>E+~uaXb_aHT9RtC&)GiH2HiLx18Ros&1%V*vPOYAN6G1l4@J)nrL@&%2+^43Q$%i<%M?Murb12nq=Stb9ZQi1HDJ$%Gr2%%n5-VsIr8 zyqUr9^tgI}NX@f+zAlJ3a;hYBil46fc6N<Rv7$aN_n!qvI?wbu`0`SpwLJ+7g^6YUFy!o=jNf--- zrwW9em*ayVrhOOiD~FTN0-iv>ILEEQnhm!Gt0o0&LVCR?8um;Pq7eNz1Fi*(16--m zE`7TSFcL5XkPBeLv;r>mweg^w0JtH(lkRl`=L6(AfXAf!UBEX1CIILo+Xw*Tba^Yf zyaT)fp#MVwY&Y6S{$7LMu><()L4R)mpCLzq7?x&+19LyvMgtf#HiY`8jLpplYbL%5aZL+{M*1Uf&X2a|2=RJ@~vt9IPg;#&qspL z{(k}*z%!S~e+bBh{L^Xv6X3i7@%R$_Bamk<5%SC#@d=|-45pg zIqnkIfS;ANPyeq2|HuITCh%RbKQC?X7VwKOz6Lzyr+{DoxWoBf;E}>5ih*BA$8Q{Z zO2ChW{G7D>-2=uM?}`CDNk3gW(4QkpaA3R|h_-Mf_?+)cS(KuwPV%>jEKB9SB#8>Wu-+R_zalqXB3^4kj>* z7Kns=L8(`_l_=x~PWu_wwMtPJfmF4KM*Y4}HB{>n0ZqUhDquiVM*_YoQTGc05}GT4qO1Q83$SNSv_#5P2ueIubN?o%Dk zJM)iun}g!S^PGdC$8(m0!oz&YL1ExI%t3L@hx`x}r_sbHMq`OlL=|Er^-aVm$VJ2` zuoH<<$R-n`_)a56VVpsX0yc{n$vTG^g?Sz^3gkj!6vsuxDCXtFD1yt0kzuQdQQ+4Q zqmZp9M&Yg^MzL0jQD}n1SYM{Ch<{jNl3Bf@?QIlZD&B2whVzNFz45NK zZPxT$Xj_GO_@$6l$kj{v&a)O;A)}yjtn-BA84Z<>p3YXuGb$=ecIPXSXLMAB{4U#2uNDh@kvw-veSv(72l=GW+1mz=lH@ho#P z{(*6>r@VaGO7mv)t1Lt28Y#C0*;{Tlfxghv(!%{d;DA|UHh+aSBHo?IwoVvr4&x4? zU%*x$YfEkskUQ3vmQSqBwREhr4K|&yel+LAt5A(!*A65V;@yx}6-;VP@4_38HJwB1 zM0)YjSC)0G4ddo1_#myQ)g1T}2GW8p{TtP_E~` zl@$p+H?cN9(KyQ*zt2@PAX* zGHZGho;&6}@Vz640@Cj3;?En$V($~fIcjTW{bje~j$IB{Y4PU`A7@RM#sL;F6%R__2?j_q;&qA;uuG_f0|myzU-l? z<-kT`zR(KnH8eHM$a3jJk7m0{=PyXjXfYbc3O&zgRD^y@YAoY3T4?!4vxk>b#5g)A zl@FPlgg(442D`GMT6~B*;{MS~*azbfHwhxfA#R9pH{XWdmDcO_Cgz%tBY(WzMtg3b zz&Hq4dM-}~Qze~e|9#Q2>=b?e6b#8Mh5yLYio{x{rRPD#d=x_Q>{zSjl%lEZ7H_L8 zF3jg0T~2H_vwE!)S*=dNfvrf!dNEzOxes&355tYvG5zWabvh4o-Iww($6>T3`82C{ zyxV%6@@5P}M!O@{>W)3e&6d5Y1+v1tUykL%i-+QWo!r{{J1AP8{pt&BPY-mP4i0D8 zb?IZ`f4zL{XtNxHk$o@{Kb$B?l;y^ATM`BFJ=86U7hu*Mhe&^njCRL@u&pkmw?}%U zx2K_qxTO6|l6$@j;xb^eCSm=o#pb=7;z%Mpo*z5O+LN7Jm=zxe`?G0Uzsfed**4n@ zVHwl@T5WW#VknbkFO*ko$~Kolg4@_*>8=X31}>$hp>CD!?{1%?-&!4OZ5URe#@T%x z{3~q2Ud-l?p5ChwEfwm^T*#MSFozRspF7qj{WZEK$};Ly|BT_pid<`o`64FkDCp(Vs zlgqe#g=Z;=vHf!F47tviBz?-ZA=lpdB)VGC5$Gs8DaB&!d)t;87`9Xxdt@fC_o+b3 zCb7x2NmzQX8S3U9=f%sqVy)Y9jGm%x3sk<{s^__JP1ra*{O$*8NtX4Lt4u4ZZO4H{ zYNW=*yKV98ry+i?Eq*glygOMs$mq#(@2obPqw%cJuZ>wc z3h^1FrqOsx=);W0lS0oiKZF6Ju?OAp^S9)jf7#)TwQkQb{{!87$rYb(yfL}9C*EDb z+?n>UC1uRdq*KncNW%y6k!&9PA3Tcr5VqNu$?{2tlrd(rUuZb>dcK;^B`m=(R=g2m zVZ83Zl-}-Qy~q9NR|xC@uAgUds`)258S6#!dl*q~gSI*WKgqHS<>u{|WPGIEV%qJ# zAnm$syXt!MSyPi`=gZAph+0!sKc!AUO64CJW&!-L^plo;%F@r=XX$4x-L&*`mfmIQ z7cBj}xd%IGw9ml|H>>s3eFC~12ujThW)-k>$aI0i9;du59AA_kpGQ2^{Df*#ZNcAg z`X^{?0Vtz=G~WN_bMZeK2BBo&9s5l}zAxGbn6DF~6!I*sk8zl4@3CB;K zCCLE2kAbEcleGMf961VhKeEE=`~xV~sNw8xs?VCFUA33w?$MT%Y(A|I)WL(r>g4y0 zrb{!mPu*{|;pHID{3CotY5p(h&(vqzxgf1H%@F!Eb~YT{b|m50DIFRhkXW1_&+7Ln zbz`4eo-Nfs2GI^4DuG#31^xXcak>2c@C*U6U$xRTc`@FCbKP&u%`#dK8a-b3&Mh#2 zmx$+{kU8|!9)~mU#}4PIG=3qC*+)1xfZsQO&WsbceoOyAnQxpRAYQAi& zC(XA2TR(89KS$1_w%}O``d>(Ivgy5~*V*)Qq?g(BFG3=6Z)24q-+GEqNk-ovE ze@nW+rr#v(vgx-#SC}(D<6|$C8}ELTTa=jVh>ynKL@v20DW2E;%$)w`+>S05Q<=f} z9kJyYqu$;luojQ40qZ^eCY~Rncx~RcBJZ(y_io3CUClRhq^V&<);Miw$x)k~X&lZi zErHzjGwB|YjIDwkUScVZ1eH(bKcZU1kKhm*7cFf%o;ers%y|b>7#F|Rys6Fb(YUx! z%iBKGxOkT~H1zvg&>lN@K!nzj>vmRRqz zw)K3aZL+i2l1uFLLlE(5xT43@p)C(BI}UIWDtGxl^&rdZ#~6)wBv$k^-6gaiwCo-- zOVMuI?wmDLo19t_@1AvozA)CUU5_lvHyV3|o_%zPV6~X`WU041H3aj~V$)|?sqe+! z)o+08cLz$O{YeeQx?p!nB`ve65R+ZqQiz=V1WW}<*TH8xrpk+dCw?j! z=&~y=--!?OpfDP<`D^w6eco%_fd_(2ZOjF^zQ51q!yn&oEPQt|uRSmGpWkbydM1nS z`$EbTui`B(E*6DRMOhh$L~Ft!1@t8TD5c@Lt&y6Is-_f`PN3Wr<(@#O3Sak>l0YaF z&@`7ztcdzH24+eny-HJqer5Hf>RJ2}cjsDVb#+ZJ5G{&MSPMy*)FQr6G>ET`An~rt1$hdnqN^}y&- zn^b&}z)Y7=lu5c`w@Gk6v?UOc=2k4ZdsW)HM=4!)>!SJNqf}A+woIUk_Sq|KR9(r& zyrmU=Ca$cXHY`o}u4H1d&(C=VS}I+3B~J!gs_nB>p+#!y;65~D$PghJK{+AzOSVbM z{F)%Xt16{hBsghaMz$`D7gs;@(?ORy!9JZ#thl#+)fe&kVFH^JR^*pnzb_h)8vg%> zhWr*x4W-EM!}j=s(FsyntFKSHn3)bAsVg`M2BLL7e<12n7W?XJYV}&BCaM%xNwst~ zAt{&PYp=r8iYnpibn-wuoi;Ki%qYc9KdG$tIXtf>S{L+fRn$PRPC+OFfsj(9shG!R z;A2D+D?+{vumG$4daYza%mjCd<>9bW>kDmFYC`yYZaXjzN8p<};|rtX;cRqsOgGe5XJgJe=oC~r$^{3s^4 zoIf+T$X_b%4sG!TYmmvl4NA1;p#Z+|X1eSHgATe92!-{Hs!|)M4M(IZ$DhD6AKSVNs}y!XTI+xFFad_-Y`)qH3Woyi4Fn7iO}Kdm#B)zR1Qq z6}cy@l=!xe?|>}EYcv!nh_A$D47V z06g(whZCRU#SSR*9+UdK(`4fdh!g$~0_NX=DC4+45(3u`qUnbYC+Tuv-jPiP@b0s3 zv7o=v7L=CGREicXSusJG;3#WPiie?nizAI4^~*E87*{LknUp6J$E90p+AH%Y8! zD0%f%Cp@YT*IJ&cts#ioSc?cxBoOp$3~M%liy)h*3!+C}r+FkP?~6S0X3Y}`SMl1& zWB>ZKa0E(KHjPLc^bZ)`@iUIh2l+n;z})jp;~3kG z0OlCwm~SR9ziBX^*qDa|-rFc%FFP z=HNbSBIr!x+-wg3GIBx41tHgzaUNr|N2nYi$9vo^IGvv{l9mAy+`NoEdB2N$Ib6y0 zwT#NfBYS~V7Of8a#vmT@5po;24d|3?J(b{QKK&8Tbzosr|qU=QRN*G$XEHK8LT zCs+q@uXrW7ode`pZ=8?|W{d&T9^nxHV@&^8SNXpxEub^=5!3#jG^QLsW#r+0Qp*%I s_5s*_2FR?PJmu<1q+4d}S@75@**L!ITjW>|IcHx}gm|%!>7VO=0UA7%;s5{u diff --git a/board/MAI/bios_emulator/scitech/bin-linux/libc/dmake b/board/MAI/bios_emulator/scitech/bin-linux/libc/dmake deleted file mode 100755 index f198f294431a80eefc3705e4bdeb593064da5b19..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 71264 zcmd?SeSB2awLg3&nMo!vVS)q<8Z=^1P*9?v1c(j^6Cy7X84{v|7c0R-L_l&5q8J!D zNzLI9J8iY4t+t}}*7n+#T5Y3M3@=Tvm$sDJUVN!irFO@`mI{WbDf4{4>zqjf_TK0D zJfG+J>j$5cz1MzSd+oK?UVH7A*%F>x?(ulE)W0+>T_e;J_xdNn%^T*#P0|W9pEgz- zuH|YO2xr`+DAM429DaU2d|rI%_+I0OIDW(6=f^mf=9CBz;`rS**rV}del5p|uLWHD zZJ(dtOKF<+z-UeCWjsJFp6$`%kNN!kS^)DSUaaHl)vLa6_39N9RJi zf$t_aYzEw0@MXI&or(Ca#5aKe{*fM+;Tw+c0(`UZ@n6_+9J;_i&4n*@-Sgnyh;ItM zAikUNmEhyQnfMCu4Z;_|HyGb|d?WEq$5)7N;J*t240QvtT=yc^CGGf+v@I5&rp<9( zI@h}XQrFFNUG_)nANi#`1)Ssh0auY}Z)8a0DiQ)c}40j6|Ne6<-_5 zXFn5Oj*sJr{WlccP!G4qt)J!HgHK_+!;$hf!0q{Re|?()PeFR}1Iug1cLeb)knnbV zJ5c{ea0!16Umoyx>Km#(2Do5nKl~%W2M5Hz47d&DrOMwA*bn$ua9Q3#dLcNlQX z0Q_GEtRp=f!T%k`4}jkXT!Z}NS(f)9zNZJ|KMA-6@priN`xJ1GOK+x6LwE(!kAxGe8CaHk;uJQseA@PPcU13oYS{xjgQ z-}U)>;1*znbiwtbJjyJVcLHz)(ocd*nCWT;(C-Xjh5ASj#{1BY0|W3M1h@h)nI%Dp#`Q_!2@WN#aXOzwjFVmK-TC>W~maT-NExT#{vIb*C-TL** zw3X}DuUccQ)K;!sZ8qpygRy@79r}9h?z+40Sa+YcY+2o!4Xf6#U8CK7`|8ze@6cAR zudCA<+&oCkM0eI1cig*zS?{|L2>~>$%Wi5DsGe3n#MA%ZX;T{ zvTiLJwZ86ll(o)8zGZ0gdY}SA7+aZqrkH}r%C+n7(pH!t%zX{ZQ1|po?YQ@L_UtmUg44^$1ab-OR;*gDk(6{v47zvd{Cn3bw8&foP3|tzrp^HBcc9VB z;4Zsk?HXhK+SMBCM^VcLqOuJ1+K3A4R@`pfj`Uw>XaH$%N87+GD;)myLE)hs_d&Vf zeCzW$^O6tBD&?mSlRL+W4-*H+gAWP_$B7Th2In&$2J_>X*E69&K1CN3*wb{Ols!Wi z0(=);2)}x;KFibSHogbfGjA(uIH-OLsJMO}bFFCenq%Gl}j<$YHuraHi7@ zL$9Wri#d)i6x<5BP-f@Sg_2cCH(S#d(uHzcLl+8kE!}IN+t4l0v=wy6K+e&H61|!( z6s2`^p`aRcq3my@dnwivbfGv$>CV)&Cb}aaN9m4-PD3{Udj8=JP1~z!$;mrFvE-OX z@fTFnl4IEOI=x*-llV7=9H29<>yW_Y1fA+-SG&OE2%YL@*Dis{8F~TX#|0*b=wk`T z1tzEHXsOl}6_^~O17odgoxtQAJw$l9z~mskf^en49H(z2eBulO#*p*$DB+_5lLPe@!iNMVC+cy+?E;e{^&NzF z2~5t^A1C~{z~oTt*iZNn;gG-q z!bb>C6quZ?A0=EMFgaXTgmVNYr|TyOYXXzw^&Y|}{>Ane5Y{mDcO4bDkg%WdA%Vvd z&LP|`@OZ*`gm($dk)an5eq3OV5PdA+xWF7K`b5G}fjMIIDTLPv93mVdyjTQJA2^=Nd zPI$S%O@t2+t`xY1@FBt>fwvPrLU)~`K>@&8b)-COiwRaKSs*UHE( zZDiwL;?sT;wPzOkpQN@K{DqH`L8U4}>tp-9Dhp)MsTZkNz#t6y-Dk<9`lu38OTC4l z#jP7OB8*ZJr{RzMG7cV&mGG}-WXJ9FfRTR$ALiXc>bd5h&|6A zy{|?KZokm0X`Nv*o)){WRtrATJ|+o&Wj*xpG-DBTx*83-rM zKt0xc{IC8cF=JyJbG2aeb6DJVhH{Bv*VFWeds&OMuesfr1AL3RW1I3d?*;Zcu{v}_!MhpB4cXYp4VgFTF^P8fML=5CTPacTaxA}HA$*C zl^6oNP-V5clmWoSZ!PITC7qVp6Kg!B85#DxQx*!D*Au(1KnpfKj&kgK3Syf9JklQg z`4J?ZVGoVnU#J;F?2OpPLd`59WM0m?XB5~P!;DdcJQ6*`zNNrUlhAal3bh$Ga|xn# z`lg^c^ra}T7m^)jE%zAy)UUcNApW8bnc z_HJR;A*+0$J!7I(J`pKn_f64^h4#%;ta-Q-x++72Axz z7o)Z21<89Vk{c@2mv84V{Wyd|%PYXri9z5!w4ef@U^E^WeIagV+FEkMbPTjqA1faQ zBsxdEP@!pCD}-7cTb0%7zi(o97Noi}Hde^GnaWgLr0 zV$BFx%{p?Tj;6r~v|9<;p6<}XG>n%}q1C(s0f`Z$d-#+qm|B5nE5l%2o&D^oVV8EpC?5@5!aOWb;;`S}S}cqD}#KtHYMs9HICwLdJpnbDO&x z(~7#2<`Fl~PkY!Oq-xVq@HQgU&zXC#bpk2UXXJuj#e0Ka-iOF~P49UDdLYtlC`FoP z>R#woNX(I~FB3I;U4HKidBE-D_w2^UMP3yp6PcaiBM8F~YSWDCImnMB%{I07B9=ia zNg2VWTTzGI%0lg%@|{N8lXrlJ5?+pJ$demV+?DU3&ypN2dxKnNe9W?Py2JZJ<}h+q zYcsK`R5xDA{tno~3sKtEccVbYp^o%L(CLd%%@{^x?d@!yi(K$(uFN*Q&4}BCybNc^S7@6U$!t8m0WRbcUWx;28V*AI&UKZw)>FB#4vj~nO5FG5gzsp$k zx=eYK*I{0cunNdmm**KQLjl1bW4PIZW$X7ss9S~{#v4YOGjwzGv{mGbfXcw?%-UC9 z7*S)TmVEF=xZayI{kj)P)MoNcM?|f`9BFl;uVR}6m}HY10%{R5be3b)A?Ow_2^bj> zRf<6CvqaG9Mu6#$s2Q;9TKlXct#zja4eAV37)*$$04CtOn_o3niQZw4jDuq)SRWx2 z`R%mgbR*MVz^**md^n{^0KarAf{DqCj{F^Tb?vEAbaY&-x4nzHFUHwFr69CTUXQV&J_2CFHW}knvi{;*F>)91rU^ z|J+*Fvv}#N(4mm8sNJseN2h8=5amRtUS)bhr2x%SZoJScU^nK}PsChv$H{?n&FhOm z+i7-Ht_5VP@~ns-t;=Yw4p@;KyDHy`J=<_t+M>2S*V^9Z=TgK7L{6&f^Ag= zEs^ots>ZiOChS}ewb3dov_^@iufu?2Bv!&O&A1IXN;M&Djsh=E$${7nknVp5ht_-QlX?a?I-=62 zkRusjXJEQqhoBSKaAA5VUirwd9U1KM{OA-Yf6-KCzhv%^l=kpbkgF5ht^e+Q0aYbG z`muH3^r4E%}4qO^*#5k>RR7N8tr8>>`N-hSV`5~Fp zga*f9=MWl5TGkd(N8GTSSR+QuC6T0={B1Bwg!>Fo83kz@R%Nu+(b}r^oH{h`of0>X2lE zSA7W5N7V1|S2D_YvcvvPbQ$LJ5Hue;&`vc?c#C6ciQhH@=(*Da`=E7W68h8Csscq} zCcUP!RPtK)`?=ilS;G>UaSDe@FGpILKji7L%KRw-Aoa$Mds%#yKXyMFoKe)CSPofG zm$}vRPDf_JEPJW9 zT7Bd!)~vU|<*#?lN@BwItKn>MxVN?LgosqBzdBOXt+b6Y>5oR|s9M;S>eKYA>92%; z=Xgw|6yO^tYUTvdT!#~{y%J$nPNY_G7`VkEZelw$u~VCl{5z*JYk$5!15M;(=zx54 zn2%v+=Yyy~e=WlLace~ldcxyKIJ9c`%u`hE=7yPCRc_stMvbRH+K#p^i=N!qhSuYD)3! zTw{WxUF8@T+B0&cz3%9|g{?mSxG)phY(cJtztA=2JxB1in!%%}SnWypV()n{+piDl zTbL!z`60ZEn%6vk_l#S;#x=3V=ODoCs^{#|isBg+5CVu29TiIx^%E>ytZ-EHK`dr5 zsZ=p*>^|_=o%THyDFpMJ9FFR@l~vuB5bU6XkfVPFPGk>N`HR3CUv{Zu+-q2IifrWF&?)j)GFNA1VT3TTU6ARjW9p~l5K z>2A{k1=H^{&+9I&@*3=#=uHcA5_!ZCjF5)v^w(I?==n07r0=Fj7M)RtP+wKjAU;TND$U28o;2;Cqv#yBjt>}CGg zdk|t&ih>e>`65Twa%?Zig#xz(Vd3%{SH?;TL^h0;gqUIe<}7LY@?!RR%?Xl$0^28Q zle$K7VHbW_Ca7%jx3q>)f=B$@Tf?aKV`R0$aWo<&)Tj_anx>hvU8(jU*{kudjlm=RE^6W2f%{ zkdX zo>ApB&u2FZ^IuF#Y@H<)B`#pCI!ZzN64{_hr&zFvnlqsWn-0Lw`IKWGT97;D{py1S z2rsXViRDi-uAuQe3ObfUdXBP}QcZ{b-%f`vGX{2D8pa)!`8bU4QPHgGL>+`+c@DPc zgl{Jovrw=q6;Ekd`;r?%5%nGo_hOcfsB2}&=609g7BZlZg=h=d5K{RP>~)M{>Y^)% zS4bpxi0v96dy?i;YA=QZd-X+epH|O``?&g{xR0tQ#NDC3CGIZuRk$hTA|J{H)*jF; zVAPq4B^8%(>BnHR1F9qEO zXeQ^8C`t3fSYw=-&A2La^E5sz0S~+56P(y00WIp1REq5quwCUi0o*nk^-m0OQ>o$N zzNNCoJ*0ea?Qm1;_i7P8z zP`X`mqXBt|U&Ya^xRa8|UdFWCNMn;`rqDbnE$+pp#uE}>%~BRuaL;7V<;bv)@b}*( z&IQ%#JMds1jsxgF!0+Ln);iT^n*=>!AMQ52SixTiE4!D1$6J+v3LkJ#}%_Kk^+kpOp}PSm63{X#Zs%oD2B<={Y!@#e$E zu;R3orSoH0I-7qagE?Sjc0CCn%CnaQ>^aapk9UR@N4jO6+LqB0?!g`?LGYw2y|9dY zdO4Xh0NGt)SFuI~Mnt(NM@w7|{gQiHpS>+@ zVx!T;YF!ynUF?m{@%!z@_%)p1d5Bz>`vmNbL>J@HdHM}xsh$a%_9R2llHyVH7&n4^ z#kb{|f$q}V{08<#XKKckkfpKvU?#f~;_UL+eHE}<#WvyZg~^5rE?L*1JDqlA!D`qB zG_CGfNr>V-_|Ufi)-MMEKK(P5xqy|HBEj9IXb-xw80^uvWrD@-d01H|*N;_usQqzE zst`z7w;(K_ev}Fexcp<3fZwi_3ciU7xIyR;ILOkc^_82xb@{>@x1hju7FL<-h~ZzM z{H?c3gjh(?5&>MWnQbA4H+&l!d9_;K1Tib>wl=9aB|u@-Adj--n`Z zg%5!*V~zWs2lIuf#0aH8x0r2EHM0ENX%{C*gJzSbvbp+$B=}{7Igry~~QI+6etHTLm5!LDo z9Cw}7>Ke2ToBP*-Kv9lNby`%uZ5n1g%=2+viGpAl#OxOp3B#7M@+TKE@Zp>#V3qG5QBr?5TeFP*l_gUi>P0EvUwLV zIjOIbOb=fwnJ6prI>7k>2@h4OSDc8-gg=fzYDW6q$f4Gb73$RoBKiix%K-1(0-qIr zYiCT{qbqkl2+v9@d~BP~g0Cg~zN{3k6ucwqVsL)7nt|b*74C1m+l+FlxWH}3%-0>> z2*0#P1z=x!auR5s(qtdT`G_7DFs9h^UOK&pH(Jbm>8%O+Hq`AwNyGs}6nD@%C^JD1*w5cQlXP8nsR{VlCEcX55>=9tEYNXV& zsfPv(VNR%&dz>XdW?>Js-hpUh`?puUSRsfydN2?HCa+mChD0dUU=I9;9foD~nX~j0 zudAK_9q3ni5q$?yY5Z@TMWO^ykt1wsVCMmJ$~LVf+}jcUS8Yf5jAp$-0kS}SRDgOp z`BGz;9-UTeo*&)h8DtJ^Ela}|$fYRBdIQmkL-uefBz;PnnGLIORzzI}h65d2Bc8;w zR<}sYSNAz*mc&-S#4mf)qQPX?qi7q9PP^PJwceT7p4uHa{d;R(Z}fq|XD&CdD6^LI zM%22CiP7iMbj%!lMw5d!iE(l6ryg;5mrNH?S3`hV`<&=ORyXzor4(QnQRmMQG?8#D zw^_`guv$d)M@gvd(}bD0s~1s!LxE6AHeud%)`n?D-@_(y4x zEm(4!NU*(Dy#=<3s6XMa0=Gjwa`p~m#|vc+HZMgolp1WVf~QY~t5Vy-$6M0s z1B>)kq#xOscLmUI{y`HOlT{M4zE0YdL>TY1%I*E z&TpOw8W71hjY8;tW!~a&uNh2UTdh4=hi!FUP->fNv+e@1f0nTTrw_F-zk^g#%N51u47BZi5BxLHLjqqm(WD z&rp90&AG9X=O80AqiiQ#YDUGeO;}f4i?o%Bmj^1<-C{+T5~>%eyHfdO%fDL9XKdL_ zG`62o4YiAq-=)+6QtG}#LMhIzLxdAB-v>Mf^kdi_m&G>KYR0X0+05dy5cG%O&rbmJ z5KJhW#DvliQm=zYPz4S=k)FoTopi0T(AGIMxTl~cg0$mEz#TP7&>rkxV3&n}SRyZ; z$~7c8nc38Kw=mW^GCF5rsJm>j*9fkRZCa>3;8#C&T6orevuk^p7ogtU1A^kbZy_|z zX&|{MQmh?&-ZKiHjG_uMPXT))b%J&$L)`;)oGyQGnC;-0G-S;4CsBBq;0np=`|dR;v<7frz>u ze_>n+RkqGbt5jJm4u*)HaXlR~GtP{IC5959S`V^yYngRlwMs`GRufVG0x|lFp6?V5 zD||$~gOS7I!h6yzEcIc;xiZcy^`6#w{#zodC6nl3#Vt6Ea593wobiUffFU^8d>F+; zI;DhVO2#{9I08swLel!Xj-c6y!>N&p?RH}zr4`C)ACQw03A*zi**7#wahL9Kl2E#= zoHVCG5RWy&AaRvl)f=6Djb@Aq?)F|&spqlb&*Joou)P_i;@#^xG44oZWKrS*X%j_^ z$8v(yoMCKOPNgb^N6zA5F7=!Q4iOdU$H4rm5O9&YFqJIUn2Y0OMD!`tmhfR7YV?!Q z9A(aFyEC~3cb9uA^$UqvUJA2d(;0BfwsMd6?cnbASkJ=XgS-=)ENp&wkJld`yU**N z_A@Umj`kL%DE{5`zy_0t!w|V0U zp0f<@&aj8`QvWvZ7h5vQk;^=Y0{@1!Z1i_#>;cRi7P=C?y#{ zoziIfuzBH`9io;TK%REweW~e96IMMe$U&Pv9R^n_c%q#1%0xCqcBjA(s9&32Xsq2b zYWkop+0(Nc$2GMZW4iu|aWTEX$nSa!9+WeElQDOCW3Y)9>#hS%81jmN9;}ncsnb91 zM5XNeTnb}s*PoDx@&Z=7FN5q*gL>3u*tY9>84+;_zn9%X#Rqw5tirP9JK{^hcL@dkog}B3>2UqH-8_oTy_x$Bmx>Htwuy6*4V2V)j;L~AhHbg3nJAi zL~;^Elo|C)iHp>Iv5N_L;%~j^_;3%-2BWS;>T#(t@0VzzmRRHRlGDU45C|HEi~pN| zkgr;;k$k$7FELHpEcC|x2{!auCn0i@k{dmn%*y{m1_ z>~N`V45!#FayarkAXb+LY9nkdh35I?PE--QC&sAvvHGyOw+(5Tcc>%W+Zg?1tm%bk z9BwM$*w3#($88zY$2sS-wu}eguHJGH*my&5`wqlS9~As@oNiWddkblPv(-I)tdW=4 z40n@}vn6BtRO5ogy6KI^@Ni68)TzXJm%iXT**79U! zYpJI);X~ck3)C&#+Td`-iE5*VdP9kkA1Cbw8-vSeh=$3y#QZz{1e-0i7K7{x4tA`F z$_1gfs#P%>-rC>^?&gSwty*oztirZ&0cH-Z)+^blH^+chOK}6pk22mT&!dbqmVv#a z?tQWt@?b>2#p40Dk$7RW1(bbD9YO3Obr^rGx5YT?ijf?&KvacHc%;LFO}**xf`5;+ z9Ps`TN_=^&XLj(x!w7{IU;7)cAN_UccX*TM_n-e-e*5{bbJO)6`rp$$?3VF3+%|mA z3@G!^0RR30{&VY4h$D_~{V!=!dCqOi|JU_L=N%1oeFK6Fbc5g9W%v2hy0-NBeO(QG zeoxn(eSUw};y!;t*Ze+zPFI=Z7ZdOW`aNWkHf&zG90@M&qP;85zC2cLot!en2s(Tj zEZa8k*p$KMKLs?;)4#>M56H%sSN06RV9lIQ!f%yXZ-ZBueu$Cd^0hyeAIX+78P0mX zr8eSNwiSMj-c@_ZZg(=EW06`62osJ6@*lCM)GH@k)*O!jRf5=Rbv^!~9_wxB3O7s* zHciHiQ!Wf?{-f(+&amCm&JlV$aXkckv)j(DQp7rKjDAvR)^Vq7-f7f;;UgPCWf6)g z^*m%Y2h8tzA0doEx4)eu24n6BCP*1GAAIa0R=`F)g?JKiGl=Mpz+1)4?N6+UHXa*o zu5pI^<>*(TCk8*ZoU*ayRBL45?`YFgMhRg4g@1DN4~hBvmryd%4gum_LY%^HosGo` z2MeNbiJ*`Vs^no`aqt@C|C5_P6Z6khW2j3b$eyXe=4&u{mv@cFU(zbrG#WlRC393Y zII^#gH~d{bM8@?QEc1&_nOz^jtnSho`${-nb5u=p@`04jOh>tFzaol$Yu*0O*^Xt? zstB^W7jsj38K$h^TLxo#n+3h?(!`uN=B)tlazv+XGD^x5Q=`)wjmcOU72RxJm6+&+ zLtZwT1@(;)wRd-FK1j3nl_dgJHhEIf54iiv$6pjInCdG) zh{0u@5>1;kRv2Q6BWWk1 zX0+i-XAbR23pQs%rD$ zblPZKh9@VcS)ajRgmOJSSn{n)E1uj0yLaQHSV@#te(dZ{rbqqcWnubi^>eiPNd^H` zIo9({ZbC{f+w8p(?-T%EH`BL%iJN^)+u_a7EL6ZrxqWjE&UHGazJLS>W0XCd2|Xt| zyg8b_5}o5Fc^~yrBXvNE3FYzDtRsMZs#$xuYwW8Sj%pCVE z3E9aU(i!&aXoP#Vin~udEE8Z@>>7r=pNAg{dn)Row0 zK_hV2ugw_)-9|Pjjs@r4!j6HCnbVR`sd_bYh?wkPxb>@lg3dfzHqcfVJ1%=sa+M7% zkG&?Vsuy(xe(55Pc5B?H+U>wSgt5?nr;lvEK7II{8*nqzlIRA*gJs7N2W><*VO?_CX_l;2U;v*Y3<7I)4^*;hHID6o&C%JM zf_%l=Q1$?^3&T_TW6;B-74HNi`KKUB--$Z8Gwd85lXH0!&T0#8URJ6%fL=e&?brbY z&OQdB&Ys11asc&lvEXd_n>_o~3aVJ$=a$9w#v3pI8$%$wrb6Jm_i-!LhO_FZ?JtzXRBfX@oBYkvYNStMOJJM^*U^+-IEu(4qH6$CP-v#=qA6}?w zNY_#3!6-{v+1Os7iUqDo;}~x)XSJ~_6S&`I?IZc~;@p$2R_h(|V>oBXywuf4wEyR2 zT$L)r_}|O85nVIQseTgYf+-p1Wvz2Ot<|0=w&aXlgn4lKB6EgZU_Qx~W>`lOIPV~+ z{kHGoo%E-4J|yqBk2VfJ*9cWnymv#k{%sP-xNL{-VRDPh+1p zRZxm2?eg3)+6mr3DbTP1xMf%gUl|ED1t6`vF2x^|Ew@vQ>=G@CB-eCNsK@Qo|OT0_oQ$)jA;P}I|-_RAo}nUeoPK~FL$CF*|+S-6t{ z9hhax^Q}D8z%!3V7Cdoy%=yi4ZpqevO_~o!Vr1OO1jRnaHWno()73v<{KweK5nCM_ zXAY58=bb)uNgDearP~|wvL?E_@XmP~ckdiqD6Qe1%GU6iN(cjWekf>8)OVwppRS&EY<=GNFIl`>I-pbGmKWVKbue=4Wj0H>`9k{~H`Ajxdt@vyLGF2NG~p01K{wdK!GT(n^P10>$#b zB&8acpnYXI#hK=LNW$aeqn~$Vc{^@DUWj)5g~d8A9iacgPp+(PgdrRUBJagrTq!r) zQ`GGi-OSamQ~U(-49dqDf%A}-73>j~;Jzp{X{q9EERHD>M!1InnBB^>rawYYA_Iq$ zGp!qtW|Uo)XU)pPqX^cle7mf`nuQJE+%ak3>#SM1=gMN-UzQOmXm0SUA3&G1_7ois z{$dYKG4!LD1Cz7gdP6Wdg$DDS^a7Xx{dT&QmVnF*{^IxWdIcM%GR8YJlQwOTHhuWB zvx#;Tsc^t)Gpg)_tp!}+Jg$(kA+m28aWv!*I8ZaZ(Rn#z>piZ~0QdhyAYkUeRM_3& zF>Z`)Myg`#r0_)1vlJI3Z#U-P?_-~gRQ=CS5L%9#=Q&n+PPJMH{lc!!&8o^l!mV{V zNxgxzk+h%=9w}+OI33Qwoev zqf@esk2^vhEmoKFj-1)S_;d^Kq5v}&?_U5LnD6K1$gb-J$g4ku`XXu`s0qS>0wyWo zx0VL*hK%zx2*|qiT`zbJ?H{uVUB#!Ba3N&)3FBfx8&_0Fkgt*;ZP=~F&U!cIH8i3B zi47S?j;`jfA6u;+V5d3*J=pXLC{{lX`^}(wRSr>AtKYHN zut^7ETkjmySmHr@$APep6;*~}rt-BV)Rt;h6ZZh*YYkug@S z9_#LFtdRw+*yJ8oCT=_=zQFZ139etTj;DqjkP@|9oryH-v=HjC9}Vo$VZd&Y8c7pD zI+%vd;8ps7b(^=d46{FQXK^?@0_&)jh2vg*Qw(t9)%c>rMQ_HpdAz4#+M5yUxjy(H z@5{loH|Z~4fAPC`3;O@3@86X@{(q>e&<)T3AL9St;FycDqQ6c{6rew&zb=q_?a|-* z6TEX2{cTQyc1_vn;1gVLLa1AZQs)odcMHvcyY_PrF}Y9GVO{2z_pa0gNPN9z1i0v0 ztl#QO-7{RX(Y5M!$UO&E-RQ(8pTU@hHCs+Le-nM|Jh{gn?C>q;c<=D#)9LgT(80e> z-{XBgF;7dF-WMh_o`h{j7&;X>kH@_C?WY6N1efV6nkOg^dDz z0ZH_0?Dm1Fc_5bBr`r1rI)R&RoRo66rMG03&6>W_@J=r?Kb)WVfc>^5Il;`BpU8xt z&!BWbZ`T~5tfA#twrHk@cyJfTtsQ*6K z{}kNU@I8m`0i@dx_ZYtY@U#9?_^6nI&yv^GuT`7h2zg%dYNt#jh) z2f>)7>*T=~AzHET(sh6)L!8$=<)*z?&2-YzH1*BX$)xi@jW_ki=l-1Nv_-+DuOOQ< z>Nx(o_2S1Icz2VdI#p<75H)orf?AW ze1XHq1mL^;ojwj_0YAfEl+7V4WhV$b@};ipZ2*ox+;td!wGUGVF0RhJ8d%Uifw5KZ z*9}ld-+(`f#n3@qcr)QS{qUCvPwR&tB79{({B^?EdrReig79F%5QRShpr)Q8{R3SU zs2DbtP00ztrbDF19{h=yZA{L$>EK`(EjigHH$X>$MC@fRdY`ojH*qCS64VoaaklNj0O56S&&Xim3d z;|@ZOaxd6C9&^IVSP3h_(SBFDZqX9+m=7t8E9wKSW!V3JfwZ{@dwQQ!&1=)ofL@6U zYF@?@Cvg(y!$+u9@=kkr&4F z<7ywC=CH!YQF2i`gzS}gNDM5+^Dk9XS*AZRn_1#8o1+3`Q7SH3l<2SOUg<_JPX|n% zj@GHKV_ZR}@a{hi$nEn-2t){sF;@0m?Oq z<8mANxJp9{P`h(0l_>o4KO}$?FDDSao7vPqS&IHI_;u|b1pGGw#Js`%RV>7Y)|ZAV z^)yDkgebJR!?ztqYR#U^3AZ0rH3Jir6X%JQ$VfH9t>F`udVrZ{aRb6xXc!lPzOaSr z+sUKm2`9l)DV_Vt49XK+umePWPil&m6ded*;emv#rKU3T zdEkfSxk_;XIRV73!P90>pEb)6#c3AQzf{Ki-ut9TQy81BwC1(85>iG z;D5zRM2~^a+r(mCgIq-~iav&`7S0=AbHG39TemU>ym3r3ZkBU`_VmYST>!^Uj(5+> z4VhzOTc81tPTm`!xuh6NLS(>_AP1oS5R3nw6z{ihgn{~C+1AfG(IcCGkurwmxvIu5 zo}vaura?5(Ng*sk>QQWIq7S-#V~{e=zJimHJaedpCOV)qMiLK$v|jcIn7jH%rw+ zTsg^Q(X-D{xd$cmKMDpdq_>xx7-*xxsZ5M{-ihR{nR$Vn7~$KD*MNcaAalJ4txdXu#Sg-v=Rx}A41Yqx z{kzH0*h+bUlF2#nAH;qP8Gko_fRlx%>mvzLzTJL6)OFgB>7KY6Hj$qN?4n+PHkNWoSQ^Lw)m^|p`e?Q71p zp`->wZeM%c!N4)a=41UWQGH{~-IwFN(qK~u+GvZQw1R0H!>-du52?`U zW1QpbU)nu@FixeowC?)kUBeu+gpHK9{?wOfq6OPy%gnqCQ_8h!JWM#0u02U(xTH&W zQr4zY%0mLQ9vizX2eYbPT;oL*HpK>U>c8Ua)J@FDivw)sd}}gVBJ-(neyn5%*amwL z?xQ}Yj|wJch=&ZqVs;}oJ{74=x_B!#v~FK z|D`Y^Q$LQVL>BNrPw(zawM0^3aPc;VQ|b?0Hs6lXfGrICz4tuG8hNqwp>GS762bUR zMt5j~l0JG;wV=8wzysU95TQd0`z%f}4qL;x1tigElSrQg+U49UMx2DaE+H5j;15Yp z3OT(g?MUVPDbjWN8016>ArYC9sd`!ihT((I2%PfW7uwZ_e82>QfQDIvXPG;+0v^IO zPmBDW;L>;~ayu=ajuuDs6@Bn{p+H{OcTw+v#Ol~LQ|Z*}@am7T{`ud6?_K)B^aTv~ zrqOo;eMRtL3tx{BC}i+{`Yw>9CVV;cmC=_$-)8!HS@`qxeMH}f^eOtT*Z|+#@Uh6- z3H+YH-=MFPz612VOy4K;{fxdF?uG9M^xZ|@cj@~IeUH$$hdvuV7I~V$W(H5&2%kaU zV*2XoGw54R-_!I})AtsAbLks=AAF_smC`o_J{H+X;7SJXr0){?_R@Dgect=w%cgH8 zed+Xlk-krM!1pYD|Df+r^!*h+7U|st;D`XQoT!H`fgIt9YT8M`11(?}x7Q{ytzfW#S$0M_ci$JQPc*Y2I4JS>>J}<#5IiS`35WV$DE(^=+YY)_#OgvlfKvC zOWDe>6Ae8hP=8gWI*bB&cBJhkBueqAV~2%oy~jGkCx_}&@A6Fgi^Hg5?a9D#$i!cH zpV^$%x-?n*nQ`HOd(}Sxa{wLGGkQ+(XXalAL_LHk>r>R44*R`zD3Kk<`bq3V*6IFD zbI_&_k7@^x`6)b}Ir@1#iqBwr--}ixu82G6DN#IUBvq~efQ)40tRvV z(K$?T3=AtM9Rb3KumzF>sy~OQOZCv8ci2M?#MQC-Pa`Jx{*@N6RCLfQm3Fr zY9DIG$%+FHV*m)UK%#37gfMJJ4W6zU@Co5k`z_Az;9#7V<3fR}=iupsN-We{!XK;* z{`?SbgMXlFPe3J4YYl%;sdoT1^(a(Hot<8` z1T>)1)&II3xam z2z`ZwqSi+l)b6Hj8<6%XM(`Y={xCzm4&u8Q%AX`<(XTnl+YqL|$cT+h-aep^{S5tr zo1BmD)t9P$SPfU|uQR5C>Ak{e`d?Ve`wZpki^cC?L80Vi=F>l7OdiueC&3On-3;Xk zN~Eu!?Sy^Gunmx)daaW(i2&Wxh)|wE(W4C2bO{YI^h*eh?H>us~KAEHa1X9< zuC2D1s|hm~`0krDErX z`C5Slym^+3+uBQdD0Z=x+6&7|q859TC1f+ahqjZh`#v;Y0m26V);p1;7;_2U&OtV7 z4|c?6U~58-2(5k-5a{N4*5|9OrF?fU1&e}m(Tju8>a4FhuRr(NXU zBXZZpBkIQp`M;@Gx@z{9d6T&fb<5pU=X{^rOPiOvau_oC3!txSW2r)47Klj#Pgxjv zC!247VlKs-j(k(e7=qA@1u6g&7|yg@@4g9#pOG2(_9vbzfr^iHMjqZKT8{388lD&X zjBon?jV}*4KVjhNB1>|h5tKajZB~QlW9vieNud2C1Du)Fr$&Gt*nmSw2z|DbQM6`Z zw&S#S5k?~J3vy!{#uSu-shENZ@5TJL%%+^VovV#jNd-CubbUZ{kSu#R1s;F5U^oRO zPUw_M=~nKpa=f%pJtb==MPDM*>fT9_X?dTuz0cw==-?@L66f#goVg3885rxoia%{% zYy|4e>uY-e-by`&zv{2B;wDV=JFLnko&Awnh)h>MM}Y7?P9;dE1#D-J+IctDN2AbV=s*2QcH)k=z?$O` zr2l}RMQ}Pm+7Zwdj8RYh88{7RsQfZRXJ{cT|5|6MoP$eUQSP{rRKq{r%a-Nx-$Y$bmJ=T^=$w1NyT- z9G!8qL&-`t@-XFjeV|f*9x>|K*Gav6p3}ep=RI)!WrQcMQvuX=)_FxaYt+b>>HT=^ z9_n4-DuCkxz3O5hhR%T(XML^!fYbRf30rCXW+mZIF;e`7 z2>s|E{p}*3;*3cnt&$nG&_~XS++#cSIH!O9h8%YJBnyW?a5e|O^W(LaPD*j9@ET7I zS3%!3ea??(geGA)7oe@hm3a6ZkFp@@6oRtd-$z-Xt`_QY?DVal*2lI?(u~#ivPoFB zEX7%x20W1K+K>dIoKB>_Vm#TP{e z$}N%qd|GBMIEkV?*gOF~JTVN86`NaZySHvma!=CaoWNpf}L09d0J3kI3UL^Se# z<3}2CjB7#7o)3ob_YPppuNWr+v{q@&}jYx??9g*wO%%F2 zIQXqNjCh=xdY%bzR<0IyMm3oA%&JZ8@_4Z|8FH8uKai5Vw^j~>xztz#>ZcU|40jh&9`8jv)yTs0kF`t{Hi`4lLKSIGm*ni0Yhm9>5m$*GE?*lt~K!b0sagQI!?;FH<1|5I! z10FMO4dJ2NeI8y$IfYum@250lqHUgtb@+`-VqmyVGOmm6k3fvkb;+?Z}|(O?z^-U z?hw_TAu8~ieT!S(TdCItgl9sW_C!a7o_m|nnsVvniyjf#MzPrdd&EMc1Z!KE_7@LVi2 z1e=B;nf@qyXW9qYFz5OXIuFZbH;tm~=)vn1JSm~?MKZVa7k^99i{G>x!{TT|xE2Jv z&@C1g=uQ@?x=3U9Ep|bXog=jFS_tMzB_AA}w!|>OxSmA5Y*q8f?GV_UiKB4|PT`vQ z>_NA3zBTF?(y>2W0X{)?GpL_nm8M%|ky{Ri2Nk2dRAD1i;bxHG&|p(EjFr%bU$}S? z60WE{g`2Of0615wb*L07E4NA=(ltMbbg9yUO-+F6Gb?rP7GQB_v&-q`jZTVn^zyBgv~|QV@B?4^udv&G<&6aB&yPhth!zvffIS@ zW#E7w%KHuT(|#3fQW(Vg2-Z}s80zi%6GHF?#AKGDmojF$#Q3{jLQHDH5ne5Td~?@L ze9`MDsDT}fjnXyObo#`DpibX2Q2!X25-e-gYk$SuqOWA}*(g4-1brn_%+kcf)RFZO z_{|y|&-j&4jO;ohI&CxF1*LMc{EJ}8e_)2BEEvx6cT&By^W#aW4Rd5$f4wqFy7(eK zq%R%>$GBYLmq(yfCkmoiX*b`1GPJW6$m2*<$>>`kVeQ+)yk&(vXf@ zp3qvNQ?kurc%WgBnT^d61n^*Za-I`)ftl`j6M=XKF6tt>0=e-J*+$O=#)o)6k0iol zb1bLU1VeZR8DK#P2IZjgcYPObANS#hce!6YU@#1d78j&m)a9|ShyqKwb)@ETYLQh;H(7_-*oL$-{TZ;;qyVGRyDLZk)&RMfAhW z^OJ#je3Hl4m&aGBA7P%yoII%K9p>58mnVNfJ$ONpsG*)?NR(JDczwY1bNbR3O8Nlt z66`RQ_2v2pb6tmiAZ{Ns->|-XS41}fH{|n4J|BOSNooUzpE2q54vg;bQA}@gi+mKW zHj~stw}1t3%lQQmGc}O+2l{&A{R5Ojlo`{mG8bD*PHanWksk&oPhcX~qR{{N)5fIBkfkMB51hX56SV?DrdhqX% zhS_-g4i>76qBnW&pZ6^K4zB|zk-e)$_CAb)C+2L+@)~r2{<5#N1`@- z6rGlBe8>qc(8g}+nna<1Ef?(HU$&D&%?dxd&G#HUE#b!@0$an6R;t?_LUe6I@$ruE zqsfl&V_ISh%7!i$!*4Yj^IIE|k+cdzr*?S>3NI$d}1Dy-wjM9Xu6XMLt{>wIYT0wz7DLdx6x)} zG+(hnqZE$rNzb<9=?7jDn385VFPOc(EuμFXvQx`Qsa%FYaO&F;%pjzS{p?O(ag zl(w*T!0RL0fXN?h7@pS-lrMajp$K~#sMxjI=hXR zGrIU140s9gqZyyk7k^J1&KYWn)slBC<7icrMT9X7$;Y3ad{7%}mh-5Hyyon>vgF(* zX@a=x&y5?zj9y2+^z{GMy1Q2y_E*GuvV#v6qI?{*tr-S!w?TUj&avS>|H2Wl>;4a4 z9BEQ|}VZ#T6;V=ze_Lif`(5+IX zZ}4HBDDz;L7eKt?6^WcUug&?O!<)W};uGdSsUpdnNds|8pOf&E3GTAlxN0xz=C7Pa zaYir=kFFhd?sgY{#36Ts+(kc2OPCWO@hp^kdJ{zp`eJy}$8M9pTiNLi2iSX>fWh7WS9{+d5La>Se<4c*Btn!ZD%u+j zh8WoVFwsCl2Zt;i4hj!zk!eI|W2*OY=6{x*fBH`qm7*)Y9Jh-0 zb9@ifnb#kopb30nUUv<#=h!GGviV|uOSWlp>#0Cb^S;QOvsuq)urH5Gapt*U%v`vv zWgfxw)Us__Mg^)gkAZE}{1exVW~=*0beu>)j+Dg1l?^bY)S0yF*!CLUJ>)$E0Pia- zZx|@T?LE036W(m3s_V{_^|Nk>A;~*^hlXHuLs?!qa|4TnCphuly9HnDbhsAY#Ko3Z z#?nw$cEkOi`E!C;-73i}evJ-*DxN?X4y`+|ntt5@s%1<)0m*~@3(-tP5T)TPT|kwF z`;-Lamjc2WOBCd08wA!<=E6I`l;R6_(f>IlJQ7}FXIO1RV=LF=Lim*6MSOuj&b~14hg0-sKHJae-lMX z!7sKZ27ew}jh&5w-;R8E&bFk-up3#c_x>7<++;SP)+#Y6^O|vkoQvUMd+hn4h04r) zQV0#g79r?uNu?tdovf)m&X%tiFb5IW9^_%p14cMWEcrcl^xcKi}59{g6S%6R`o zUONI_Q&k0OFzYJMoN5p2vFzA9+oGazrIBh=(74<-@Xdrqq)cup+b5gcjH$RI@PI-8 z9s58_<$qtGc`53UcnH4l#MorNwx>+dN? z_VGm&ehLAeIBGUq1hw}P8jm%b*{XXfyWHLI^cSkhD5yEUc_em)P-rpv6*w#-4i$25 zz-4eFQQ(>gT#U=dfJ8xQHEwUbQtp2-zalL|+rk;44Y=$e@Eo4i(l?#{_`Z2B%!8m$ zD1i>zr(m{=>jcC*0`{*T3%WBxCDmA7_(%OFd^YAa1+^LQ`cVt_IVRZ}Hyv6Gj;nD_ z;A{ZB111zt-X~9^ARKLq68g)Vgqt8dd0#s29_&uV{VD?#rv?|{ER!I2zKKl`GHp88 z!Tbr*iJ2;t{pibBxdgADGaB(@1=|me3{pzS-nGOlqeB@ZgkGOa@T>?o{|^1e@6d){!Rfs|5O;FS-mU z^yHj;OEONECkHY{wza^LIsyRD+y92OA#7w0t*8WG(*EFQcw}PH zqc5SOdT+&t`R88gg9)!y02aU-#wO!fsBpaQR2&N}I@9w+qLCM$XnMDmD91{4mQ}C# zG>%i#%v1#_d~j`ym1d?YXLA0!g8iA`9)r~tEawvZkMz0(beAtsD>9g8o-OT=8=qaY z9X43mo!Sm)TORcoCAmrk#u2)HK7>YwTlV17A|SVm9~a1F-Y*a`OF_n$lxeqknpM(t zw3Ag&>_KOnvrRKbxcPxxvqV~R64zwdc^vA&*cF{7_hm_){J}xm%Z+)H>0mL419c$h$I-#!5${i!M}y=6KNB!zz!Pkm_W(ne z+c~2xx%ug72F_8S@x@HHN%eKa#g`GKRos1@?Cac7l^F_Tp~mxRH_m{$j}9XKj7e!Y z6ExrsYMdY8_;rPeQ(7YCrRjfR6JD*CDqkgOSk8x|;MuhJa_#fiNHL0G`I2rOx3g$e zSiY|~0Rvu&to8u>5{#V-ckFZ_8`2saMp%tEZQinybCT+*?TW{h%*O2QtOeq=Zx7>*=U`p9DD=FERgK6<)Ny&Fx zzkfm)zkh4})>+}h)-U7Yp92VQHWRtu9b2EV_g|bGxy}8LsGfKL)B7Q82E(zYG;E)H z>jx4X)_Jd0f13Fg?Y0LIhn-G8LtK;jFgTw(|F;}JBYh{=qv8J>LE}g9igu3{&>Srw z^+fTE#Pl6c0YDY9Srsz=5JIBxvrmQR?yzRF5_`t6Oyf$!R!iVlf~3vnJi#F|JV4z# z?ZnR#xG&NBM>g)E=T!xGhlSfbcR$fbz2!#gbKwYPWXOR{CrDT9;A`N6(0thxv&IX^ z=xp;aa%nb?u=2Q;cL}exTf1bzYsd&4`GS$6`B3M$cV#hO%spV^;6;2D_0nFlX1|3_ zz2Mp5!kK}oKhja3(pwW9ugJ;t8R@rhK?JS53oRBr;h3G2d>n7t`2Bx*%(%2it@kYC zHT-Ns_$tt1_}M98Cw}2buMjI}&z=$1M~9zH3SSr(b|!4J!_TJ3If&tBrvtPIpf}@y zdE$a+gNJOLdF0qKnRC4i{ITA3ME$&^ex6r9zg0iS)epUo+ACvYu0#ClUTQ7dPU!;i z7*EY)l6e zblR9AuA|*+xN5V{hQmZA@T*|!dt9EeMFy60E zyI}f`qa5hAybJ^N1$e_GVgno$TgYSGav!zkpyCF-u8&-OP`YS z$=wvt zTT1YQ&>(N4dn@S2Rp#)g*m@lPp5Ooqc_%=%3)MUmta)kt-H#x5xt@8n2Zi8RE;xTW zYK1YGAe99qp?Z+}*lV}p)Ag#`4o^$m1nQsLk1m3KoY?!49U2%Wg}k^)K35+7_V zK18Yy<5I9KGjSi8p1yMvvJu3+Unbz|SX~3+;~fZQ9Rru6^aQn(8f-llP63Xg8Z-Fm z>|m=oRz@?JHhz`D9aqme(sy3Yl;V)47&|kfxgTWi4_diTMKITWKw_YIh$~|7-EN$5 zFliAM&QaXUaIkJmddT>rD24E-&}DRT54-Pi=BMsuz+vCtYQ_;R?Ck{I!!H0wnYpF{ z)3Fl4G1Pht1Wg+qX>a&Q(eiyoV~mB^X0r_qse=D9QltY1&469Yyo6jxUk0y>)<9-` z-Q;2{*fdo0a&TH5Y>;9lXuykb3GUQGS2_k?0@p?YzzNQ^Uoy{vY9Gekb_@oZD#Cmn zTTU^L4<=Y*Y=3M`1Ho|dP*51~6w~Xau@+qEzIFQWhlR#P+tP|E3sO6zov#_#FgBkV2C!*I zwaeMk!@TG2VEbbQnceKQK#B!N1C+o8W}c{MObA>!Ttt?_nzc%{jLBx($&7~3MY+TR zGwv@5kKwEnn=-Pv691a1I1dymYe-8@f$zx%G`fvM#$FZ@EStYKPk!?h^E?@@XaAVN z#3@ZJDO(%t1hZ9wiuuE}4Oz-T+U((>WNov98@<$R?tcnrVlUq;G&RPB%H(0|j`t?> zyV!7>A~(l{Hb9i5?|cFMN7eHgNhx%Ek1i$!87F`&v!IfoddJI*MqQ4X4QA3L57#Cmi3Gy z>~l@#c@M*BU=q`C=}uI3SvSs=={fcFv5E#7uVuC7Wi&ePjFsbY}SN;f^8-)A8T)Ta~YPNb=xj z!<&)EkJ136bk_?fJBjE*sme)2coo)aEoA@p5{twrXJmEf#!%era(p=uwYMfVW^Dg85W}7Eu$5+c^m?rV?z4QLh@PT#BkxVz~!ab zMcKW)-h84}+8IQr(ULyjcjSrWC$lVwV1KJvBM|=b<3I+w1~!%l+GwYSJH%_*=cm$a zl+1fD_g-&jhJ_8D0bo_I@Phk$ZpGp^bHZIBk`Gg1YGPeDc}NmE#HNg8#fWjgTrPYa zin=beSPasrRAQ*5Wvmp8j%rA=!F`@s9Q2fzl+~I*+iz&Wecq9JbM{Y(a4?n}Vir3; zQ(9WcWf9}-X0z@UZnO~tFv7x^YaG)8=gK$>EANE&2wV1PEdQVZIRNUwlWoxWI<6Wi;NjeOn*y_q5bz~>=all3E^?!@JIex#zO$Nrz>?XMF#SKK* zAbx(G`2=I0$>d$9yjGQC(}|}tcmwAsv^Zoj;z|2`xEHj?k^{I`3$)?9+O(Z8i=Bsm z%+HD_O2hpIp^GRZW0G<#i879T*De$DB(s(TZPc;ZU%(-!;g2N)f#@@71O_sK$u#e! z%>UOQEV1C`m{e~$gI+|?ZqM^Fi~}!`amk{)pJYC)!9ncY{7+^^hmg~}txV=sIfZI6 zM>ZmKP4GF`8bTYPEgGd_q_iA=eu=2vXKkXtQV|K4qOObKC@tDCPv6&Si$59T*NsFvaoOF z0Q7*@C>1kBlzI;mh5b(mDvxl)|@{j;o|ZJei8F);PU-WHsd1^QUl49_8& z#-+_>50)Z=PdA%+&;l_0x{-ON`5Qn5U75i*g&ig^lSeQYL(Km(mFd&O*jtS}z^l#X zZ|@f_!DliYZNT>QvBx|8gklZqO7B4glGJ3*3Q%Qt5YVdw-%oCPD<#h(S8 zdawosu9LP+-+BA#^Z;_!eAzp6x!hWsjr>Pp2NNWhC?r+p?}X8xu^$OxWRYo948Wv8 z(O;l~j=bdvPNVW>DX7YU$Rzui*c_*MtBBi6kZHuNF(Z^%(4QPw>fOlTg!?FgB$QJl z4m&gzz4L7ZctQYl=eTxF1DO=XW}`XGOVH9*9hJ7jI?^vIgb_|B6+DT% zWJ|Jx@WcHp_%90nyr3l8z`c<5*#)K9fr(Hl4w6djb=ko~QG04Lj1l&k(7gCFp`SW+ zU*7QM#E-U$!ZacKe&lAr`u(IHWI)pXO?as@r+pn&ehL9}wm)f;iR|lxW7I8JXS3zb zEXW<)+2_i@)n6FbZerixG7-8uG?*OxOYqhBRq5a%Z2x_Ic=_zWoZ-z=BeMgSa0I*` zJuI~4^@HWhBO3SBHJL+=ByF1b1cOw7sdXZ_DI4Q4JhQtpLah@lU|Y7FHwb(I5UJJ# z5obuEqEz$;lC^&pd-vIt8OyPC7koGJRC4gIBTr&A0R26&AOU{q>m8vg&O~@O;V}+1 zzeG#IJM>P zD0G1L>LY`d=K1nT)8*m7P2wup$R9-+SSAb2|I)MpD2b)V+;PzNP|NkybF<7s~nNR$PJi{N{;XH)_T!n-j+U%38#+y##U4! ziMD-xgLXN8T88m8&OL=_PxjqIctt;e*&b&|(D|T4%?(|AqO1`v6l7X&E`$O~GX{hr zJ16KfH8_;17OsEEhA2iuo(!%KUdMUp6|i}yg|=ZFJ{cT>Fa5N!6;xrhu@&5@fB^(P zl#TPaAc4*ACr$S^$rKri4C7GX?@Kh!W)4@=+1oY>fc>xv?&SnS%E=BE@!gtUa1ZTE zv3V~i1dYijN*i#=&Sy~C$jxZqsUtUICb&UdY0qjvn?+T_uhQQ5CZ;4Oe*`Oz_U<>4 zc&v05@f^OU;ezeg$kD~I()kP-D-~KsO6x+Ub-}Xgv9cu+TqgB`8}6|(si;(~-n#73FKfc4VJJ7~@1-H7KvuX_vmcz=U`#t$PDwxGWy z#=`%=a2YQUuE)aPXZSZP_~cml-x+?Z6`lbXc2@pLw_tx!V08Q6h7pI0yRG1948|Es zEU%&y#lp{Jc!h)~$A@3SaHoXp@!@$4#~umf1HBS^{H^>KBiwxTZV|3ehGACZZ4GaIo3de;jQF#0_h3XC7}JXcTw?Y(#z!jw$1=7X?#(&O z>%W}oJHG|ljy>5w7SlKuK>iKim~7u$Bzs9s{H$4?lst-Oeo0bt-qq@t@6RA?0?)7& zmRlT)yUTii8F5&-Sq;R01QVCNzxFW@NgJPwqR_sGU&nZcsoC)~G+?4Oer7bjoAIfP zUvS{vZyBlSKfqSzAFPVZImF9u(|5jw#y}c}HvTH!RGtRYK%M!dG~ZKcG<|$uG|kQb zAPv{F$XtozebF?-QQS|Dn~P~UM;l)nO|$DCq~RI2$21*j&WNTNWtw;zA{rJ4j3cVP zcQT$*>l0}76F>s@1a17`XqtUdJnqxp{Z?SwW5dkzi_!S+M&nOkw=T&OiN>#wrg@lY zq^+zxY0VkGIvW2I#>1V?C*e6m@&q%CpBYVaFq+276EWI&82_lczsUG_+MrWu z?Zs!M-?9te=*3=i)6skJk68+TRMzh-yz|?zen+iehS|>^yg!Zycqi_%X-C?p@0dUp z5S+~57|B!RB<(nLI7Fs1QtBgVcK#J<_LDcq|BQcBn`IJ4_*Lb*2Qf&h+ri_zR6yS3 zf~M^!?~KFNXytPSdm)aSI3x(Dz_#JD9w*7pkFBKGC&p7ff^-g@R z;diW(i}$l1^B%K$G3Ty6v2ep*-S(P5UJ5m5F!{ zS=BbqIauM)Lg$7`GjL={paXw6^&TkrA{HXOW?VsAIQ6hJbM&jW`ga~Q!eaOlp?2m6 z>zdp0P}wk?=TNG;_gf|(A6wcE$G6a^(gS`#(}3f3|*0dnM!N|@D;>0 znfGv&dPN$hH_$P20#{%{8sV&W>oo6oS;I@EhK_?}xWA(;C1JNa4ZaWPc>_mD--Gbd z!dKyJ5v~|R=s7%=G7Vsk5XvfZz_$=SaPJUZb%+)7%;A+OI3xHT(rF`4r{T;N{9D|@ zR!|$IqqYO=K`u$Y^@0<{DGBg?Fn#1e+LD%JtV{wzwV{K-PM{9gHVyO4%`WgYeV3TmkAfZtyYrgN85XPS zm=TIvg-l+l?vf+4^8Z}^<+*>~WJVh7FOcS_v8!mk(mjnbB^s6N3UVxH* ziQWu>y($LF;YVQ2txzS#xgiB-r@iM0T)GXX+V)=Nwa>~c$(toG;WC>h8DdA7P38A< z00M4F-irlhEDD3W5xWiVEQGSr_Te}Hgk7Ea!p-Q(u!dxa&jO^oOwxTWnr?||yPKhu z5H2meSn)%iz^#wM2@f6vo`iB>u8wp~=GTahWo$`TEwboVRU&RiJ0Go26GZ&_uy+TN zaDaH`RiX$f7Fb{(s7l+*qZC*sE5>lQe*rM4^Df4}=8kV+N4>Q7D?uKBvbK3WD<8lY zrYdu~mL?K(n@c5iu}W1*BHyN$}9 zR`rmp^)7Cz@b;j9X0s6#@je4SfEO0m=U9cT@F83|d~4&xE^$)j?E@U<*c=7DHxc^{ zw-79&&g{iY&;>)SLlC)(2gdgVYu=lTO6Kk@_p%M*aM{lVPPPsYI$jgS<=Ij$7Rvs? zW^?E^!oc6g?U3=f{_rkoI$ieF!lzT38Ik~89Qqmc68<{Yl+{*A(ya%fk-#3a1HU2H zUAsM_VsztJW$o|e9m=%0Nb{B8kOMD}PcyILn=8$0psr137YHv`x1Lfjp_x#(*_;Lx zSsge9iP8IIIk%LCoh3%Dm+BhM)6f?hE}%DGmZJu|ujIISR2GD>fix?8z{cNgUJOXq z`dc6gxGGlbFG&DueH&hI-y!}b(p&M1-JSN%K*dAWec;?8EMEPpsgoM1*k0sTvcqQ7 z^cbUpnQ#xH>%Ae=o|{C5fjL`gQ?zbaf>?y@4eXZ5DAjFFMQvbn$MO&>yTbcfB&{=h zib**3h!Z#t!fV_o%!iN;A>B9-H{snyUOJ3c#z#|RF}sTSZ2`y%PvhFwgn3^H;bGzp zoUcwr5lD5M6hO-6Ia&ANA`TCzVx=7SN~^YOHoph{tTWg50dlN6wb}eDQ9?V>%l>TX zU}YFL2;??*7YS4IG|yoRjN0L^sJa9DCajs6f9-Dj_Ez$9^g@zq_g)?|Z-E>ZaX znC!pcgyhboZOES;7A<_?sM}pp=3frY}#Wyk}YWO1SE z7TMpw=pI(jvjYWj4@PoX!MmH^VG%x%ui5nCUs(0+3ah@KiFS#rZ)GnNPe^?s4=9z# z)MayVwQm;`rS{xoCiPcXqyBNYO8wuk>kn*WO8wD2==-2b14Fq1ghNG=`7DAhvV4SU zgfCV!c@XcX(Bw@7orWfhmd0o@AGmSD-J*NUBH?E$)#rvB_u!ZuuAC1#K99AZW1-A@ zunC5w`mY7A6|^4PdI91hi@riqUN90PW$UqRZkO%fzqH^k`I`!i0}y zmB{?aLh~SMCwuD@^OK=|kG<4f&U}-<2WhR9T@U7q_y&L0nOCv}ua-}=Mb{F6Ck^HL&`;h zHG6h*h`Vph^?<~?9#TI?1*YZ>Y;1+_%wkg4L}D>lps&zPpkoOIewOVgz}w1X@`(BN>Cce!c12HP#+U3_5H8jk*&!Tdp^AsnQ?}jv|aRI8I&=PQs6I4#YKG zE*z;hi+}-oV>r9sT&P~LRp6xAZRf^R4`IAX_TG>3;QLMu!{=_}sHYTSYfX-Q{@wL# z5o?UQ40)hz$ahs(llhX+02^%rDUuESVoJW|LA0@LRf|81BaWjv`9ID>8b`s=-~%vC z5|o~BLvYJ`!B%d$M+eiq4*NzQDdt6a!=SVmY=h#u!sFX#!Fw5Hb zv9hj5Su~u+>?kp%;bFSXid^Y7uS0DiKqDI*viC#efsq#)VLUDbANes~uz$_=2s#ar z-WOPv`N%#v@iE)1x;LFJ#^DXieD_KKK{H|gS0E#@33fq&WH23)eefTv9(L`ZM5X8jX?uglU=F@QdX)@|6h1T#_-a4@Si+I!wrapnTKs!(^$mF zlgolN`^Q|55NFGe&?6)@rpMEPC%qJyGgKKw^#r1JyIw}^uocz@9FoLeq|Hc?375VQ-X>s2Qi5BEL{A zzOY-{OQecteKc}l*_0%b0HwVr_@<2ye?%?dTzsM1odxblhc8=FgMKg}w9swul@5b; z68W@@>Mxw(!t3*1A?JY%=-J;y22I{fY35Jk-EBTBS=ubK+w(YC%3j~cZVhaZyr>u> z4wZJ~T~L;WtEPEQ{e6U>Cg2zLdu$Xs3~y~W!|E=)3tc%OkczDzi3dxQ6T*&AVsI+# zp$RZ*TD%*z-IF;3X{r=y=K_D4A!p&Sg%;;H1Ajtk^Sd+5+=Z%9D7li%v+l%~Kh3)E zdM|MdPNB&)DEQ7l0FIA0_KqA#sWX4KfQ^a9!lWk2eD2>sICy8SK+Ktl!A7m%xpGB$ za&Utqd^YMEf~y0VNh=(93HCd14f(+ec*A_6Ecs*WEm$CjX0%qYLjzqp+Pu3A87~BZ zMcp*gu@RzRtt0Sz#3mu{n35G;YlD!3U?>uTM~p7)0a`(N^V-7qF=n-(=J}yP_-aBq zP39S3s^A-_O~Ife@P~sda8L9KSi`t?hHGA080V%29iyxt_OpR{f(M!f*Q&2zMKo;7 zVcP#=SB5%z$c1ZN=)jw|hnQuGKfYv(6y;Z8eLI%#trb{@j28`w<3DQFtbqmm_#DvxH$h zD0zpL#_hg=dWkrwcHcu0aD;&m5fBMt#PD7KHaGu$6GYY!Iuq_Lq2~v0HbcL{&>eB1 z7c+E(p_>tk>qTsEoe|xP7>)zKgrN-#-4z!)i=oRIdfVhoE@MOvBSs}6Z7(qj)p1>5 ztXSG=FR_u32|I+CNXUD32vLxb<8}y(mylz22#XF4rP-e>Fw}2zGGD|i zvBZ@8oXFzryU}{bNXc)1L0EaOfd(%~Du&isb0=-5;N@a#F+zVEpm1%HdbFBuRCr@!~6(4Zc;*vIhley;An52gB&>WICw=w zioyhUC!?zcXDBRT#o(C&oCqQFD-xlKj)FG>KcO}gZy$A!6!jCzD92p$B2sGW9Nh1~ zu;7s=k0y;QON2k7?sVSyXttmVAa|Jp+;#+QkYKKah_u?^PqDQ+k=fX7Dwzi^?$#rV znYsCX9(bIANCGt`$@G36d^KY;Lq3cIauysem?2nP7@9^fS>OZ~IHi$Ns-m_X3;x%W zze$>M5#z_EutP)YQuo_LOImOf_6uePH)WWAzlRh*#{j*`vf)1n<&zqbB(enwSVX#F zwGh@La|gyxTgb)qcdTihC=krI>K0Xw+frjUH=po|Qq8q5k7M9i+${ z{L7QSP71Ba43Tf6RN++zQvX;IWi;KQ09McypP^k7l4IQVw&FT? z@DrUmZY`NSUXvMRkV{nya@>yNk?KU`73C3ep7iHAst2o)ZT;;;IN7}MCWKBAHU=|; zjls-W!pzxV=6L4YoCt&CnZY%QS$HzT=Z(gv8A}hX?R}F#U%Iag*sC6zs13Y7Vp@%)iGU%kqJy504ClkA)vE&Hq+roy!*(w-B|W8AIv2xC`Snq-T^@bG6ex- z9=tX!m?j@?^K9VHpah^3EP-kMuV1t9NZQ6=Z zfp|q2?y9mt{DB$tv=0sd)_=T=`SHXe=21r57&Jrtg8z=|)MrNFerUO==aNpI) zR?HBRkb|0M-=)l=qwXK?fRr04;=d7N8qdnVH1hPxk)<%AuEzX^{=v+Z$oVNvE9qU= zwLZ`n@atW^PS1eH*Y45Vy=`4Szuwt5pc`!i>pg}(JI6m;8}Ru1dNz3UHc8TDY}D6z z0OQg72m0DQo{lcxdZ(7-FVyuaW;K9sL?O?c0$qN?9TU#`tj zW#laEP$fE7)URr+tE*pCy=sM~K3sKG{LpSdmGv$l+OHdZdPke#v5GAXboH>Vy0fva zyrjWZQeBN&p`w0|&uBBcKp|Claa@H?MKsqxCypHP7?XYtUA-RNZ?yIH>wTS)8!^f0 z=}1**`T7hb3HUnlB$M_w-)sYoq4&0Rc(hr$#f2T~=4e&E4Q)ML9eR5o2x)Zn`PzB_ z&_2+odxnUuA3>70R=&~K*4x#t*GR0-<2Q(Ik7t9Y2e52fGzaUXm3s`d2)^382HFEX zZ3B9TmA1pv@9}kjeKs!D*L!@P0T8T1@r|_ca{Qry8=13)yb239<#cR8Qz}|5*RIx< zX_skhar8pq8~Z_W0y92O&qd|+94@Lrc}l`$)DMeSL$v7Y|ywx9vuc&W6{VPR&{Gs#(?K(pINxjc%8_(p6op zm946&DXA^jHhTP;uTRrcQs?Fu=kQl6tEnw7sbArim)epV7aGC>pM%$$l9euCl%fgu zB1>P}x*iV;MQ`)1mp8@leFGZ>hdjIUq3KBkMVB&x?qI?gxT0ZQbGcS7U4~hpmhCs{ zp5A`+Q}*Nmj}aK~>74_8y}HxwYACO&*UI_=AS;RVNk~jCbRDxiP00;4uDG6>FHW0`BElH&3Zk(>pTM%qZsTu(o>wZjc74xn`Lvgxy#WAy*C=@Qf!4w)@%S1 ztQ+W@zhL1Nixyvbm9`0?vrfa{s>?_NRQcNbdi#6O2R@-AxzN${-oB2m&MqL-8}J)C z>x6F7*3;($6}r~@ATT>L_eO|{A&XjFJ{`gna<0uVJOjQMR72m59$(kZDD9ufveAdc zy%%*0ciq8@*7$mM;O0f@9F9Vp&-`+APUKgiY(U`XzqRtD^4lhji>G1Sm_$aK=<5gC`n`Iap+t$EQk*|G2mQZ)<3QJX zuc7C*&(RkY6wJ@VSe%EKtMqjn_2z~uy{vDb->Ff0m7$Z@bg9nU*Ute3Lj*ZibFOr` z>aKS;U@+7+Y9);;2(CG6S2dKBx;1CjirQ86_;y!SyJ{Qo>$A4S#asx246DliYpN@0s00y3aO#C?^;x+RROp{qI8UDk4W~n^sx2#b)d7retcHw7 zt1v>dEcCY8s%puWrD_d*9Qk}G5daeGcVeg>(kE*I)Id6%+MqU|4N}%?1D>`HCApci z&mOF$7O0z^%gzk(U8ed>G!~1MTeYQPJPiCqsrB=0rVE<@TWe z0Vz~S6FCAMPuH5;1_T$rgSx%cP%%VcOw=0vZR0O=rYy~u1AB48AQ|beIs>~{r=D17-JnN`Gv(rGniymz-%V-v0vyWvEqi?>x z!85R~&(EFGrBN}4XSR5 zY2GRsJTTA6#c0Z*l&vUw3mVm<=XXI(Eh@sVo)2N~Q*D=Dg7(YT0Y|mj8e?=n$Nkt4 z*$Zup+73YV{L=UY> zd>w5AoKy9RPUELO5G}DofYBu=%a|s{7Q$C5OP7KY9k6hwNSoMB82JCORbq9W?~{r{CPTN zmOjc2nJrjpe3Hh1?uClMP$0$Tp`t=f&yc4*fWA(`Bi2gOFKJ>3woy9Byq2x{G4Xek zfTM$B7K765&JaJxcj|h1AGm`p*ntUN><u2DYs0}Huf&odbunk}e6*EUzs7M#2ok;_vp5G+! zu~xO)R1J&@W=LQxMM`>$niWVtj_Xtkx<#NZM!j?zOy; zkw~X8MEeb_YhckHGzKOzRumb}<9DV)dzRTN>=5qes)n-4l6q~8Hcx|!>~__;8|wL1 zTECKSPM5o^q|SAHT|HFR7A>Y|+ln_L%Bog1LKU}+TTa{JRlBOHw!(!h;&t+~#Q|^#)G|I9AGAhCkg6O;%>BF&QJ~oSp#q+On#}*-|Jftbqs9 zRE|O&mYEUL=4sLSLvPm*1fy>~fH^+Ik5{TgYZWw!>H#0rA_#d{A6sW@UB3370IZ@; z%!H~N%Uy+-eOh{ z(E%yS$rhl7=Lb zUsVM&A}k&RN)D2vXXb>{vwP%a0W(V{}+B}Miw3$T;v1ndQ zZrc%<4d|~5vsM#SHDahU^VL-qt;nXneidX@oWy`UR{TiTil1kSF(TRsHq%|Ims8zG z^GNTrdZlfS@fT{TmlpjKe_AXbOQk7HMcC!)PiL3bRgbpAE{}_@fCz8UA!O_IatQ2N zSNUY%xZGpIshDqA*EOobq=nU!oURsEStCp@ljJjGsWQko>nc~(emYKyE1@1II~FT_G8Yaf(H`qf1!qBUxS1%DRiubsJBtHEgA1-q_pWd+RusyNhaC~UUD_LPan zsis}5I-g?F&B+n5lBf4tHZue$Zuwu@>R?svQ4?LLd9bI8WJOQL3|cL%(eB;@b7{0! zSxm{E6|D&;Jc5v2+l}a?V!yOSuP7vHvJb+$WZ^(f2Sit~rw^9a43OgdoVlQ3Y!M-5 z*K%@1{&Yhn22ZVu3ju5yC2nuvh!r#Tz(Qk-X6de67?YxC%>_#}xCy~+Oh`80iD3L)* ztaZX12#m1QBqU_Zs7WR@T))MyQ4z`78>yk(8lC8{b(HoP-BHb!M=6N5aJ8j%wDDtWj?o%g6;bkB2|X+l(7M~8xs_~=6X8+~HDbD2>Q>b^Xs#Bh zxl*i^le}9ssj3ketH051Ol?W}UEFvZGmBe;kF|d17Ns86^3yC3M;C_4fv1dUAg)@F zh+4cMB`r(0C=5u_rsquJN=+@4Xix$*C_|ohZ=VLf@W67X$pW9|3-t78zOEikgPhT3 z%I8dg_6=x$h$7AJ^#FkDUQkjre_$PCXTaBWlLoVRbTM2>D^-@5XK2m#oT@3a&!tk+ zfg;FdUc9EBqPP!6ReC*TZhlU&=4SD_2ezYr4=~mS=V}Iw>RjtA)a_M!dzBM4gAS(+ z%(dd7}%2eOspVIA|a?Ay?h1vPx~{vbKSC?{aJ&fb!52z%;U0 zvlrYi$C5i+)mj_Dx)T-@sKKD==gbTE2j=zkwYT-mLrL>QX__Z<=0LywD-zXOjleX! zP**e8*a`}Q?3oN;v9O>l($PT3b>TgX1F}$5C<+v(cayYZVzy*K!N(?U497&hx{r&k zmdPBA!Py9eoJ>l}z#3H0W9B&3Y}Rg-=vD*7!xl*cuo`J8Z3u}0#sfn*SC(ZFg#L^E zH-9tx)!uBTN%-F+JOy^!XK*&KGc>ajzBRpq)4(ahY@hrzvi)Sq!AD*pvZpU*so(J(ff#(H0Z{YbO zo{#XHHH!3joOqVwsl~Gvj}OmQJh$Vy8_$Dyp1|`0o;UFP5f9s*PZ}N_b%ApcE!&%v zjGf<_IqXP=O9-uFmm_&9e#=K3$>g&yCTbd-UeG<6HUkg;a41W=1N26eb`%-XYvpu2 z=iw<1IgSJLG{uSo@7Y)c8 zHt&#k=Pz*12UY$R_AeTIA|Gf@7)G(EhF@bq{d(;;Spn(SoZdFSS94~DV+m4-1NYtTz)cMoXWHp_m>>IY zDIOb+<3ll!;J86J#@lc!@y@(C{&0NKF+efi{v#a!uEk@+yL1Jn()|g z6Bz#{P`O#JT0j;Izj%DkhU0jcZJxf|bru}!I}32L0C(l3_^|$%2miY9@SP~F!PTv6 z;O8{gjzpMUkN!9~?v>twt0zuZ-@!Pz+W>dlC%|ougX8#o2jF-<)c&*SGJ*ionD|j2 z8l9G)?ZUf_7k`PzZPqX0vT%GW>#PLrz^CwG{n@yF9^Y}*(+D@8M6&+uxUb?H&Z*>& Z@s$~;ha>N>O#5#LPDl6HANaNN`@g`nu(<#L diff --git a/board/MAI/bios_emulator/scitech/bin-linux/libc/nasm b/board/MAI/bios_emulator/scitech/bin-linux/libc/nasm deleted file mode 100755 index e312a0b2394252ac0e86a67af467f76a7d4522a7..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 168228 zcmeFa4R}=5xi7vanMsB)FcSzNXn-I=K|Ul3N`PR#2B?4yge10#_yM?0Q4#hAt0WBW zOv%pf==4-uy{DdS&s!=)Zo^E;?HHHvV=Kg+b?@1s@QTYwfjn1eY&%xm;56FHK697<$HVd*{GC8A%gK zbEE>vBTbdYNI6mlVwg531QqCzAAZrzFZ{Iw@MGr%CI^WqSEU5#~d>SjH6_@4W4bjq7G^yz_4L zzFAxDnN=i7QxHE7&qa80@C?VpzbxC4vf&QU1%Do%iFiig;omGglZDUznG1*IU51Ca zXXEkVDZqo`#NSl>UV>*lo|$+?;F*TUi)S1j*5e91$-k@NnUoB`9qIUorNq&jkLMaZ zw@%Z6pCL`g_Nbz6l_;Ve1I$ZLdZCvQY zT?KcH<3Haa@7ZpQ&z3$)usvSR8w``q89HPGf1^MJdArb+;e@j!@`-Z6GPA+;Qn=kM zw!E^vR^qwgqD=2=Ol1l(s*!XGd_g?ijvyiV6`M-&1!ut_cQpy{Ha8n9@E@nFLZA1kLKNI0~2;br4 zpM&sIDf#CkJSQc88PikfU(Eaty`*mi!jB;QB?sSXhEwvdL3niv{`CkKBAs%;{9j`j z>9;uHdl5e5lt+5+V>l&$1Hwu9D}elk5zYZV_Itv&AiNIYr=9S(5IzNbi=FTj2(L!^ zA}72D;l1E*8p4#<=MZ+M&sSrsX|)2WcioN%a*VG^5VtS!PRS5mz6IMu9eo_dH0=)v~~j=Y32R`t{Nl2M{1kqH`aiImqT&3E6rQ358^TiT$k-?&lQux<05%6dtFZrO7Ct#@x=&9}?AZi$Tt$J6)1a z)5YM_MHfoCn=S^_Ub@gm{d74HK~^)N)ZKJ30DI|TaPZNEk_phAf<8nSN-mEs2A6!g zP)Y@K(NPQOVt|@T7X#7^x)?lW)5Typhi(SOdAb;Y7ShGQT}l@NZzWv};!EjbP+m?K zowkZD2IAFpF)-gi7lZ#zbTPo+LKlO#`NwT8>3}39=C-3|i7AKhi`q$vDdeb3Z@e>s zzbWLb%(Qri2$RDyIT3FcVRBmL6eGS@gvoKafZ-=an4Fiv87UqWVYYzGVK5#NVYY^#j` zOl`HHdW|){nCJB6b{C0xOvfib`9rtYoB}mvwoj6z-5r-^dh5OBLiEes$Kj88I`O*> z#l$?P;A2h9KcF|7KY{9~t~E2D*|b9etwi8fF49T_YJb!3F@Bo204V-8e4x4YO;p_| z^@iJ(VO8e2Iv4V}<)=S!dlPe+WDeiVDAY<6ZDjX_lo4_hwDaXMcnE~@g@Md=h zasW8ou1*rMvW4{eQRY|kNRQ7N9*ubjLxSt^FAq;c5$%{vw6aEW6Z_Qmga?8S4%DZ~ zZD3DBiA2oP=F~jqc^N*o1B#A3EA=N5dXF(iM2;blz-^Se6CL`& z@Ckp@Q!L#hk3iYgW;MV;8c43Gjf8uFxhfLwrz4LR0JjN%9IZE9y~+>(#-mK1c0d={ zce5ZlfrUn`O2?H|+)y z3@t58bjXuYJG<$gMCne`<$w=4Lz?dU7-Uclv*L~eLzX%=65{I zkmJy!<~b5JHPK-jz>$>6$#&W6`b5nkQI}AnM#yx{>+M)aY!#3B-!Y`2Byie%5u;yX zF1vyG?ScV(YDQ7Jm8tiL{uudT7pipQ&95J1f74F8>+IfE_+~4=_Yu9>n{k!~#NEC+MQMY%`Ke@fWZ`;o%gdangF5~jQ zHRxwJ8K3kg!yA$37AH>>S1ni>|2ESWZcwLIn=fvIreODlEQQB=W9f__}I@my7V73~yliLJ{8R4_^fj%0nZ?Co@i#fwYaY zDXoOHkQ7fF=U7$d8@*7U|Mo?xPc!wMFG_ugss8jYz`O~mR0xZ{2;j@izVC}ti;((~ ztu6x5w$bhkZ|J3y4(Wb`suFXa=t3AyCmcB!aTlzid4_c4RA`^2H$E@V{vxpb0_=h) z935M|mFmzuPO|R=8u{)o!leQiApaGRdXKIAh1_tt4Bbj4D%}e?`6k0Hi_;cPS4J$H zsSJ~M1EaN0?-3P`G^RV1t20lC{!I;)Au93*)MiIEL~y46k@jYdjIqk}9vi{rs4a^x z0$Y8NsbQjQ6-Lo{(c+Tgmyg-;Ut_#4T5Br=S5G2g1p6cFyKcOB?duo^?LJvs{ci=v z8gEN_Q@c_E8jG6`R9JKL--Z@QN_KSKXvJFrui9g|52s5N2>0q;`Y&s%^qPM2QlS97 zMomBHPAlpm;A`mA-g>Fl9EQZm`fhfAQ5HLYgYU3MXc#ygy5Nvx`3wj)L!SyAgpShm zZ{S;%xd0Py{UF8$XyIye97525@$ZnQTFh-^hUS&3_sFzSnU5f^epv1Y9wW1~%3O`g z>IXTX^r)ld1kq;$q&{KxF{LMbLYY=AveueYMY$Mylo7S&AMH7Y^?}}l@c^*sy0zvM z%1+D;e^I;E;B_^o8%x|(iEGS4D7eVNUDJXbZxbuL{_t%e)@cdVCy(%m7J5H`QJ%a2 zd1QPU^H4O6*qvRL>>JoDa2MK@rPEI>~QDd$c$LF3m zj)!wle>T`tnCT=$LB_L;3oV-B4}TYBIs<&Ixf$fKJ=&E_c?!50J26~vO|6Il|}x22MiIh!N_0S6LYJVhWgejlR|y7l>Funkv*p;=2iU&{2sV6 zLw$|t$cZvwR9^}w)Zy|T(tI_?=1}o`b@*YI6#0tF@__e6C+upObvLn1#0YmEW*uUh zQ|+W(e6tf_>sZP*|IJ@v^aJ}@PxJdC|BUzoWCmWOXVpti+5;a^Yyw(uK=Ek31?q$$ zscY=i-Rw5;em0iCD8EjkEewqR|K@EM$^0Ff`2xHh!o^<;4*BBaC_9FzqutQ9jEwZ} zdn-jot`D7Et9&VRc9v4vd_*+z!lHyV55lm)@Rjwvc40Ai?ek)g2veAB32Mo0I;vm} zbif#4OJkX;*+y8P>s>324q=CTWFEwZ+ZgK3tEZ6zb|)yyaL64I73=&lMg`k zq!A$uW!OhPD8q&HeM)ijI^vdAbRrTi02D-qz-BWPD*CJT3L}wGzLGRNj3O~ca?xUo zTXmJW0fS&t&@yghuDtkBNCx26B9C=5#%n4&=!Jy&3n)WdWOf(am*I_th0OseSR;w0 z5X3hkBC8P7{tT4C2kTrycjRM8DXTWWeTmZ-Fn`|#{PiyL6zoh?S)ANen>SD9oDc<8 zo0ri`eaqBEf~J^v~ncT)AX-$Bs4^dwtseooq0!0d*uco!3_Rgw1Xjv!#c(%|DJ8bb-vycnm0=g zgzj_AQnNz$rIq@_^FXTh3JZ6sm-mF%!&9J4(i)l*>cuGyX={yy+LTa3)(xOhWJyzR zH^S?XWeSbsCHzrWY7L=;x=dgQ_5>d-P_ES)_9oO~t)VTUUUdPS<fb3;XJjO>S<*&Cy~BbCy)yGWK+zg z-f{+8^RIKTtrx>Yb^t+^E=FT(tlm?X9Ih=GPto+k7U7^VFa8?i+|FS35zL?nC9(L! zqcBU2PsR`GGPssaE&ylRD@SwHpE2tdCWISKQ{`eIA&eDR^*xV@LtxqgVb50}bIG;e zXb1*MOD-I9ME%6Vq?J|#$|?GySSI$vzPtM*SaSY=nL6EZW+gYFf1AtjBPx2qIZ)cb z9BAsm9B8~n5;;i$h0>r!;_u9XuC%qu7tDe7+#=>c5g{DT`1<$eL!927Hy={B4a|i$ zfK1VU)#nE$L3!wAm;~k15tE==^Bw^vOdby#VFDP>GW`oDIunp#(Bu)XgNUNdht74j zg0g|R&UmzBa<21h^hC^cHh!OTohJOY<2i+A;ggu>;Mt4k{HAjh6KAW=TxW!wm5J{D zb6`W+_B`kNm_A@^5VIQSd4JQtqjjk3?U}yN_aDXo1(8EW_Z{)SHTK_Xr`ltG2}*Fr z{^=;bKHa=q*gt&n$wSLl7Kkxskv+y(GeP43UCP90i)-P0Ws-kiN6L7WjzLI(e?W@E z96T5!Sh2D`ovJCxh8(gXC;l^la9ubsuBZ_Gzd5d?eQsQ7xp{D0nOkix$QS(#`qV2g zM-8oN*sDfiXTTXtP9S|?EV)9IFK;2-bY~1nb7*{&V@Ua`)G>s+`|@Kp+pd9lP|2OP z+wZ(F#2$TZMN^+<{%b9P^IF-dF|n^Tq++oKP?tNlk*G+5%`f6E-QVf9X9Kay*;T-v z)FA(X8NCi89+5zkgpVp?#5hx&rtG(}&_0f_NDNfD&REenLThN3l+2y$A4w#3B$9)T zGE(TDDzkf~sK&sE#L>qF!U*IKKaC(qA%FM>!iSNl=`r|{BT->;B>JK;sLEOyO^!j; zpBsb9#2Bg=HKWKKLbI4B_V34{h>u`lwpf?dL;EP zA_AJ?+W;_D^e2M-c8oI3DB=8*{Z{R7$ym5R84EjMPvsI7IkrOtDQGoq)m z%vGR%s*eV+0v%b-Onra`eVo0H1x@~aE@KQ2NEq%1n_WU{oQBcm)#uQ=Uf`glAMW2H zeexqEm$CcKi&cHXZW{kF0ec8>m=IW7C-bRUZIB2_%t4s`3#OyZQqrOCBugfLkbd;@ z`O(28YpIj|+s~&Hn>E$u@2j0m$M7%NRQuX6q$FS~hn3gUhSe*q8n!tJ@Mzy^Sdw}U z`qliNSV9@AAD<#6Bx!%IH`FF9d;Tyc%Tm*ch7nqcuzUE!uyRU02LsBb7c%Y1aTISh z|A&~5SXZEogjnH=Wxd>m#0%vzfAgUjH}vCLr(Yd^ArQG2d94D>Be9(@>4FexUKBmT zE;2w65cr z!L1^~SPPR|7Ne`oXHg@2a`w^(f*FI8Gwf7wayA(Sfj{O?k}f3N=qO5Vr+svkMi5xFTnQT)l)jL-v#EM=Ph-n26ib*;UpIM(>@ zJMD53YJaUMy3yfC{xu-gdYm@=iN&9&7uTAR(P{%~F~|y!tXgH>4hE3y;d)P%`5Z8SSKK!H0t{#`l#MYs zqsqKbP-EL%*@ow{4{Kslgr$ZX%lGV|6rs%OI`h}>0ic(y2!o|93#u=I?GJN$N@YHu zwHEcQHops)!|n+X^He#2JgpFVAFA>aV=hm8=snPv{(Ym3obMFpd_&DFtDxP<;!hTB z$sRP)C9ri5GsY0yzb_qXwb#j4vqDw&vP>Ogrsk(QCZ1U@v3~ zs@E5z3lFH4j4`&!q#Py_U$g@C=&6JsW666h!>tV9SkmGju;I9?yy{;1Qns_zA?R3z!1M@Q3T69<+vDNy*`Aa5Z|F9Kul8>U1=8Tyt>WgN+3tX$Tax z$2huT2=}@^Dmqcz)i5FY6ND2=Ml4ehb721m-Y@x|bGbSyia*)@VbY3kw|mSZO}E#Y zwjOO|FjAGKkDe0tTJzWH<75_|C!hS+=*)QdITKdwebywy@Ig%ag3i+ zFpOeDWI{3`;6#iN*sQ#2Gkp-1(+@=bXo(BAu!1#S{gcpq+Sppsn$ycG;8#BtDsQV# z?^zaFFiXjS`s-;)UkKYW=1Uo3->0vx+N}G%&_&Sp3q#jpf2mFmQHceN6*-BwET8JtFRgV&ZPx_^T^YnghMI$MlJ z;7h$^egkqcpwqk>=9EM`gmC?`zG&}YiD+2oReHhldBkNC!?l&Oks(0r(sQ~QEmM>+6Mms$f^{Fp3 z+hMNK55_9;MAKKm$b=cg7GE24Jbvb!aHnT}+{UKB^i4T>S8;`}aRo@3OYj3mg

>+s?6Hoig+M#-HOzj4i&q}CT%e*2J``AX`|EC4jh@{Lsmt^?_1KD{ho?@0Drdx$3@%p?Hw z)dJT+V^t200_7TI*cb&O2Z?^%N-Ju2xNOUwa}K2e(**K4+|zhH)>=zgbkL~FH^8B{ zi$4L6KLL-&+uW^MiRLif4qTlsf*V_DP?;`Igys;&MYU|l(3J;(k?0JFF zki)*PqTi@sLBp{-m|l@z9P~8~t2Tdyj>B$K?X^a-tfO@f(mkL6jV@uJtm*CL<0n@_fvVC z7?F>y8ep#uupo`en$Z$Es^F z{{`uX-3z4FJY@MjQ!ti2YcB8!_X!nP?QCeRj`*149&RcC(!5-sa#C{eQUfai% zL+iyd(g54WpZKMidPL=A@XFF=u730FJV9u0Cr@@vN+&#j;yo~)L}P+z@=JfB3sk=} zV;c%ZzaFjsW_EjWA$#U6{g>C*u1Y*h5Oek0tev1jz0O!L2&TVr=BOcHBCB&@=OiBu zcX%F9k{65J^%LYu1Xh_l+4u+aS}~hA>W>6z$~)*zh%DMG%$Vl?#x}66ezBHH*9&j&Wt0a;&0)@pOKor%o>lkN7=u?$X^+xQdjf{6*R z`n#`wZ4}H$G&l+Kkvc|9`nglw#-Df$Ns#$>U%lsiI0|(R;rJ8(zJL>%*#Xa~%3U3PZ~ece^4=4<=YbkRXXh74xlPy8#$AbN|3QT&Nxu82KqA-yf5*>48+ zw!P{w(Mu)*%n|Hlm+f(vd6i2C`f5k1*eiCr>a%uN-RkOb-|NNRwjd-_JWKt0q|B89 z=->AxmmVRoU8W&2GLv!{d1vc^zlmG)EYUZvgo!oTH)0ulr>TuU@jKAP^`2?JwF_EV zZ4M*g!AQ6t<)TlO3f2be#{99VmWDUuS1WpK9L#-I2kU?D3@eU#~#gk_g{MdlCp>@Rd=V-Ieu{vfk_u1!KEm@S{=K2_B?7)A6`uG@P{}s_#5WFw zx9MM$3Qzoe9j=W(@r6U-CtVo-AUugmq2IL=Q~1{`V? zCX5Tvmf_$}1#)m*kf*TMy?&5npTRz35?>AZf52;`ak8!T?od9~?nf(}*5)^=+^0#V zjZH}tz!_S52<_8`VG?kTaQhA{V6A}up58UB7nygwCJIST zB7t8!JqJa+g#9=P`vsLxbigAm`}(IiBGqtAZ+J6W)B~Aqz>75QwU}1>pU>Im|Ji|v zZvqJjxK>9xrf@cAG`#6@KfG8w=V?5O6UUy$BLZclrq};`Zw@pO=c}R5epuoC$8hCCA+z%J=C|}-^37RjOrwqjE0FL)K)$A zO1EJ4P>*tQ62FO$we@>Tu-)CUaM-r1LJjS+)oiWd5bQj#u`Ecec+2wd?NU!l?S_GdzJkC6r=|Li?OH01+!Se!k|BVC)$@Y&(US}frXXk z+eg@r0ax(N4Y6Q{6v754c6r);#Rs?e!J7>#jmIO5nl{?)a-)eAZP$y~X2v$O(Jp5pV#@=O>$(3! zyZZArFGt+vTJNyN5k!Mc+V&pK%Wa&^F8#=tii5{CA4AK&j6S--sOi`+Y_!7}a!eV| zMt7+r?JCji%=PJp{daY^EH`L4f|1oG`az!2rbsm$fsJZPWX@H)AcA?+4x{D>EWP^J$oi)TWlpSvRbSBwVL+eu z5trsGygE!=ztUn^QP{ft&$}=;TG9XZ2l_{E_ih+=5OEvyar)bwU#{paKHK=aQqlaGBIFJ>p)bwV(Ua1|zVce1jeczuxHC03B~(N&dR(-$1L`Frg@EpAefs zwhc(w`qt#|n7L1Cz)Ktk$ME237^a)cGB+5(p5`+5 z2LE%xGtFfl1bdsy(ilA3T$YYtU$cv$&zj3z@u$#}A`cc}+O73o<=>@>;K!uxz?t9a z9bZq6l>7Jhy7i!GtTAEw?sV(#;JA}&!U$PsmV>}HgMY+5Ifrce6ZWD zny7Ln?6`)gDM1!zYM;4wj1}!R?f3?xGKliP7`Hg50*J#{P!J@?0r5Xq8T?d$c&tp3 z?m>DQ($Q$B#UP3_Cp~RQ`e6QaCml;#ycm+x#(t5K-(_V+i9bUmk8zR*v%4(Vj7XnL zvL>Ss3xl13gocbELOzk+-X6x9Y|Bh@<=PF`AHd}$_eAz5- zC^-k@+cs(k8Yz+9I=BeH-X=TCnw6_50>>fQttaK}?P&)M)r81lAM`D(mqb%d51Np;T$?^f zTrPJPS!`rkVo==1P~4tC9!S!lunF1Aa>UJpJ!ePW(nP|T^CT|a;&_oFbLjwc?Z_1^ z0x||f#zkH3v^gR2k`Sq_&T;wgw!7PI_t^*kR=dL}{Y6c`q8ob!E2)`g_NKOef~_Cy ziYyhHX;UH+J$Eg1QC|WR+-(hPdpGwM+J(r_&^H<g)K{>gyi!4PAbZ(=(osdX3**di{Zpr>(~kb>(|qyS2XV2>gjb{Gcb05!3z zVb_5=$f*b3ty+>HA;RZW$jU^!9bS@&-t5{j+EFH=<(rqdtqi^A@Df|mB-2EjH!tzn zX||FXovLJ-m!#Qgwt`8fIr-A6v|hJ5eAP<4H~kR0kTp~5^*Z4XAXe6R ztv5^YSIIrpS?P(R&{UrB>IG;*1z~x$*wOJB zrGZ38ay!AEAI#ufxxoi^8NmX*0pm};KEjP``WR;3&BCxRYpl%E`V#)8@4;@7c$3EsmqB^mC++zhC@;Qa0o%|oJ+kzdmxZd#>hXI%xQirD=UtbTQ~CjP7WHVp8u{$ zFkvk~elBSyx2+bry{e}Trz)i?xqWDEpEW+QB@a7vk#8V5P!*}j!6pjEq8G&`M4s!6 zbu)4Gy3|@@8Fu52;pEYAY(0jLHl(>eW{KEZNo+xLdF%9=a8%Q@Qe69{x%(xhJ4*NL?Yv__1XOa~=*%C{OgI($bAsakfTqmT%4tj({V0=xi z=t3@tGAGpWrQo#Qv$O9}>Z1O;lIO6RFCE5#YELY>@7o^;7sex9r4~CP} zKfQz!l1=UZ+2QzS=rUNd8~Kl#!*Qx^0ebDzh{FDfnp16l89U%y$@H%Chc!eSH|FST zPC+@~m`gyc2ByF=uLnDc^XH^UG@d^~^QA1KWpGqrMSkKfAc+?UyvB-7*IBG!icZA; z6{3Q*PL5IexLa%gSnDnJ@45?d==aL6*zfP_z&nrs;1l{gaM;-yz!io6v6S%NE91%k z1=v(vdysE0o}2KzjOP%ZP0l03<-_pd;JL2&gWw+eJp3P9U&k05JokxpuW)BscM5lr zb*peMwZ00$C7 zRDFXckbCn-#Hw7Zp?98kLyd5V!`^&Do?b#_ z&%N_H4rl5x81SbH8UBJX?dNF0qMn$zI0Rl;MskcL&WN^cDWrPoQMY#;9tDr?Jlo+m z;n|2sjAgj*L5yQoZd8n6*2t(Bzi{4gAIC0Y{XW$Y3`(#i6}`^0KYeLxMwvC7V@97# zP3M@AI$%WHSuQ~q)xP?sA^hhLc8&VXuph*Bw;rM@cFwT)DRfB~P7W(U9y!m45FZGVZ z7AUP8nr)zN&AR{+Zr}bDun$GmT$MOrLB=?q_=@-Xa9 zd6;%X%ER>YpVTtWPhtOsk=sNf#m8DPfT{6yEyi=i@GI=?`YzxQXFz!yZW)r5VbREV= zfwjw9e7~$k2!{3qeFn#uWgAc=d5KcY}2VkI1K2O8%et+;``uR^O(v#2m zX$(J!^yI^E;Df=3;ZB5;&xP{;zqrry{QoANRDB3pcb*H?JA||-p11zv!hCuXX?y=h zdOOlCgf|)2jr8QhWrY8^-(tO(hdCGa$M9~yYfWCfispfu9HV@O);ms_v;#VHq%zW~ z)Osf=6Sdyi%B9x4y(2?saaG7(KiKJc)91^%EjmbF5D^!MQy;GC|Yd+pXIqSilGQs}V_@`XPV$Ie6Wc*L? z0#7pSC-L7V)Aq!FX{X5t&oARy0RxrfDDWC6@U*8et*tVDihVFBvX)WOf#w>#N}6Xc zuEg32JUN25<`-*+^5Yu;hjKxK6yIQ%LwuE`C$U5Dp*@r=sPu%Ol1s3IE^W=0<0L~G zP^Y*GD@WTtx)f`8zGG%oj;_>$xNT|lQaq(HX8VDJ+8KWhX*jbeaPvR_aHA~%EY6pf z&~6UgS(l!N8)M4$1sGH=GAb9?cozWgf&skNChUz0Jl0oH4;%lXB<(x5FQ{~=E<7Kz zL$#9s1r%Gkz$b>%1(j&&q5Nz96IT{_i{mrw_P5Jz zuLNQ!Z5=Bw8KgvCaZ;G|j1?zSFhFLu&#TlMdVwpU0ErSPjUP|ppO_1zLZJ)}_mHuG zl4Xsu*W+r|OISBbmKXJS2~&Jnvjgg-*sA=8sd36lDDyzWywZpUBz!BhQ}nAQTt?u+ zI|X_1%YYHGj+)<(if7BWvW6*E%j6qkIIXa4sWA8&b)|eCKcBUCSIMB0LL$)4IWc=du(C0qXHc_caw zJw2EY;T9Q|fe{+$;x%_&Z?VKz(kw0BPW#AT3FU;2+N5gHNp$_j5`UE^F@Q0Tq zqn6n7-fNQKYwYyP?C=KbGCQ3Ia)4rkH5Srfl;;aYoE9y}&h%bL87}~tP{w)j_n-uY zOgQuC|3T3koVa@9G}Q>1ZWa@1ApdIR+aJQF{*aCo%8%f6DQ;>Ked&F?%N_q3l5i&$ z=GXpRRL7ySJGM>Mj||MI(b$p7%)%-tBU3>-4c048S{?yH74&bMkb~uc2zG>B7tl^Pabs z)La7c!58d;0x7m7lsx}KPl6V{KfXrmbt^Z-zlETqr)!RB+vj7bxY($iZ}+_Ukl^`) zLq(q5-)fE#;BzYd*;Ash3abqGhSrkG;d6QiR6*^f=tBhv($`=kAm z!d zw&yjzFe<3vmE?Y6OjfWH7Y!sA%JzP&;3IaharP_yOh?b5fVvu(D>%<6c1KE~<&=yv z?d-&@AK}NpD;E}eah@1R`ARFDmS9eMXL|F2&>QXg5$vkr;BY!#HuW9=70uPY_#GmT zS8K#x;##fIhj){;#(<=X`xz>5?V^&V?;k*_oh?v@0kdFA7Er`0+^hmlZ$#X`XL*Fk z^m*dfLWX=9ETqC0PeUQp9oUk;-e=T$jhh4dnr>rj0j^JB zP3e3kJ5nxShG~5hv3ChM#_Ov92Exe>!i$M8mk6^Rgu}?p@aqtEYzzEjn7I=U`n5)P zz~A&Rb2fCl)Tza9Fna=v9+Y}faZQ)%(GqD&7Q|T{uHjO;4822tL*HNghU$HhHBAJ& zxfL;1WX~p;$dIYOVKbtkJ53#_ot>-<1Cx3xrn;3;08Pg+@P=*=TCSmc7>rNA;L+bm ztmqbKe1ONP>$hHIcGd&jS(u7O}qJrg5(buxOZCj_5Zt!*2U?@WxHLd_J46?fT)F2aNUh!sLLf&(kx zVYf!GUxVVVMW9Uj~TI`>t<|5?#jS#Pw%tAhU%qOS_IksEy#62x|R zRkTM&^i_^0c!NoZ*Gd4Rf{zgQfBx6juMp+kf@dk7*?8{5vk(vKw-IhE*abo*YZclI zeo@QCwqMkAzU>#aon`w)jW4nNqSjpNBCn{qeg9Y&Yme@xVm#<3PV~hz<%%7+gsj`8 zTpTY2Zmu)YO)nMQbVi)FcM3dW5VUOkBCl9W1COA`#@|hP2BdtVkaC=9g_MsLQa-{~ zCF$aBl47Bwr}pf3sRcs?{34MhM`RhZ*|%Ug(4>&-RC>BazxFH&W&# z;X+y{ZY1%I9aKqsz+K>PB1M9aNP|Knzo;HZFt3-dKNh`J^ajy-fEGF#(HTW=FtYd! z+}2ERL|ukF{-);T>2>itA1~y{?Xu%xrv% z>XIG4k_>vLi957PGG@U)ri9<-QR~oi@a~Y^cdm2#PPx-}=Hs27OvnT(p8?y}bn+!z z@q+?&qTQ=_{_BGMO2gzQ3tQVH3oxSjCy2Jh5DO(YN=sxYBa)hq_tO+p&n^4kl7Xa- zgJw%q$2UIxofCZcfTut3xO< z4F6*}{Ey=BKf)RQJsAGg0JepbuMt^ei1%E*QoqX@#{@#myE|4eQytw6Y7A}1% zRk1+x;-%49cp-m8-aH(lThVWE&X;#t2Chvq8v2uO>xyfq?!%=W{q`Lycyrrz7#G0d z4i((2^0_#@E8NqN9$7rGuyfjBBmda|jxlHp{;HH}3(l#T#*MgWT$#hS+Hru)yy3fC zY~ehWIu46H%pG05Rpy5x64O?H)05z^b}$e5)pouW;BWdT^4$GwlvwATQ)kQkexmu! zXJOPh;Kb`yxPneVU?HX3zAAGBlpQv*oRk<(4?y-Xuf$#cNV-67=dI6Vj?w^%9w^&J zn}@UK$$J)3zAb=59Gv*$>o@I~1xw0Qu?{yk!z8O8fJEf=lm}eODBO0CZj`(A40|MY z<2*&O-E5h2@>BP{e$d7-3pge| z0dDTWJ#Mw~0-|!^CRwmzXB6j!NUk%Kd|kf3xNF02As`%RbD z>7t#2r!8=GL`?y%+TdYQ`!a%*`sA}dd~ZfSI8YzoV12ArK39_ZY*0T)H_xfdk@Kj- zYC}lKAT{;4sCR&hydhMGGe3|M7~!B(Rs>qolKm1dWzJGYu96Sf=-;w}IREEbWzG?F zk`-WmXF7%)W%`b3sQ8pvMSx=*uDuv7v-{SXt05P9h0nf2v_ibR?3@yI$}Q@7i5=7K zJ=gymIKbO$AXvAe{{feg?sOc)Vv`u}%1vxMD*Mm{%mP5~&OsaP4&Vn_X2n=-DOM_O zABvS?Ifami%}8ou9(Do>DzrDpV|Kj3Gt2xCgyWRU!p#ooA1j^bv z#)D$F3zD7C+Rf{}{z+`7i7527L~LgleEdT{gX}nGtZ}#8QT@Hwc9%#cIULtRmS3BT~ zEKJkS;_x+2rAN!)x+?JXpdQTogT5B2*_8&6{Hfk-m1ei<#FPu4aBV&Z@l zGscz_(6JBBjwgcc-vG+&O}(JC(Zugiz){V0jK% z5POj4ut1a)@52w$cAjN*{oy?bY9*}fQh)fL5lE8qA?6H%MrilBqQWW~!ATXj?88!+ z_>F$Bm2KeErjRGb&qCQ$o5lel+o(f<{JrzpHb9Q`HPVSInD8#3I4cG}tSvWG$%j(& zU?jFGv5yuouFKJ|w>hTXEx&g@fZuL2V5)rBomi5StjV}!O{k$pkXugWo6;c(JI{&+ zA9sNU_cy(Re%8tywv4O-1={^NQsZ1yt0-2UcQJSvD=#2pW95ZX0i8+&;P6GhM6A4& zPCN!hhj(H<(^AAIz6{8tcCi>e%JW*Mq97f{`0Mg^o+W0bVCUJ1bn_xRPXU;7`4KzM zPGA&fTQk)xZ0G0=T~;pNo$X?|_zq4Q7erlRX+eHr##g9J(9T}2jML6eQF0<>eA8g7 zZ|7P2VEO}C=79S+{W@JncKu=Yx(cy& zPF|Ry4l}+1HcA zJe1#=q};=nrf;xt+)-oKiG))A%JD|b6xi}Ad>m3O*n+02!x5rRr7_r%-NWCmB02QjrhNI2~|{4|9h@ ziMiyX`Q1wAZP-|8SPo9;7 zK97BV`NmXMfCr+dK`?OEVTQlyevWy7dN>s-o(s~@4mlbjVKL> zY+o;08&@d!oBjfioO5|fuLf<<3!pp^KZ-=0YdZxk8zWpX;N%b}bu@YW=ZJL-@;DzI ze6x^sfflb^G!;Gx?sCViqMK~rFJVcMY+qJTg&_p6%q^Aht{;E+5Af=r2;G7gwEVk% zgfOjN31NHegwu;>hU5|MJh)YO+;}SS55xzoB_e(&;5qJC^Tw19?KcA5Z>DDmT$#+XX)0 zDNS+dpX$WXKL<|$kEqKc@TkJ6OD=eHji`TU`6BQLb_Y@S+(NIYFZsBrFz`3)d;7l+ z)|YpC(5WST%cWPg%X^Jo=Pn?tR3hwbd2jx<7twM;hIuX@i2jP;} znk@JltIVBRz##RC{OEZUC7XV9N)bbO2x@D5lPIBVk`6Ls2H9S$DugaAs=>1=Ac#)?C@^MQIR7CdP?$G}tQrw%$e zl*3l5%$*18CY*&v!y#j$_SyCwW3jo2_Q96Snv=9StT~P?cWuAda8WnS1c$WV?K`eE zzT(DfvkL5>$6-&b#Z*BL9@p0#v&PXzdorPnL^u{aMvh`~HrEsb9?`5iJq7JvXjwKu-s3HLUt!;G)H^@a|Sv_s7{%5WZv z^;(J;YlP^t5HEp}HBhd_T{QlO@I3*JFIQ?`cjIDJ8!zl(2;mMPg5|;Q@`wLFz~QbM z8)YfaIoaYWNE7euI(Zk^c|jh&R&)mK7=IBj6M^Pr&4iRYHCr@Lv+x==6*_%oZlNCA z`72uc^zFHYU4jcP;PBoTZ%WQ-c_ zev~RsgdyXZHVX)t}JNFT&)EUAp- zwBw$nC6)O2KxF+hgLk$Bs_pCJcoe=K-=@Tpz+Rgd9i^(mu)F{_xVOUwjhaZfT6xWB z=RPQIm1{3?>V}n$@ojowchu;vGTWaNGUcSJo%U@k;v3;K6f}5?dWz?s8kOm7oc7Yo zaPU3xO}IX#>_KM3N=3~u(s5%G-y>LT1MWCU8>Ve(6SgKB4~$&6Vtl+nH3zcgeuC%{ zvw`l#0+3SN3(_wqP4ab+qFQt0P8N|t|lrj-!R`5v8_zf z7KTNgUquk}lkb-Aa6s)w2OI z=>V?8Nz7#x%!_`Ep=&N{VEW-T#??qRanW zO+W7Q)m0pj!ZwDhaU$-0_$zmz4ru4xYBoaW_ICzc2U>!7hb7O2+oyfS9`ZxYN*5L2 zSXS&IUsSiN&l+CrAwSggbliYbf$M5**y*2xot6SSov@hqxYbF`9r##{-odL6Y&U@G zp%Bc&{VC$!er$&GBcXOIZvDX*K=Gam3~qb@ez1OzqkgE8{c5|!v3)LO!C~3(J)*~G zC8EU}XX9NQI~|?5VuwgetmqXRUw=$y6bwEp&;kvSnR^8DG4vUERpxu&qoT0ehc?qcMAmnvzUw0HAcl@!!>v=CPnCDrYMuftjwHj>kx-}V zy;C4n;wFhwf74zJkMd7a0pm{~O6W~*@fgt@Q&O`4?>hvSS_kkJ_1N=xz>5YOwvV;4 zuHd+XIMKYr_OW{WW&<{AWdDp53<4T;PALU1BE1eG@s5!)zj!>6DpwYdCnDwY;_)O( zxuoZy3*X>f0Zf)hHi*zQND{1qytYKyOcXiwiE1E6jK8YZJcji!8rO*sa)Zv^f_pOh zjWp-hjB;^nMmcZIutp1B3cF~s=q36wdvlCbJI7wLqcKoOo~p7MhV(<38<+l(~QlA!>uAsGzik+G8~AKVoc=rQMQ~ubEpvDV-V_i+>Sa+9UFQe4M)VQ_Tm^nMIg1ZZQ_$fyJ9>RUmTx_&wCgHm+ls*Tvt_y6kNxPuX>fa z3Y5R#`yPt;`Z%`0U;Q?U6sLsjD}_fIqU+!rV%(g^9ar90A0G-4FhoZJ#H;H-fHjLS z-zN-Dd!&BXD!vO5;H~JqgqH!&!tbfike@=1YV)zjg_eO>-iWK!hsi%hEc>whEtGHG$YSybr2qKYCI4btN-WmI&`x0~ znRf8Q9#@?)47!T+UyUp;aFDaPFk7@YuEW~|`gU`K0}0~u03+r3so3pJR@|q@`3b*9 zZsW%eoqQAEoL947{O7^%89~x8((mpDPJK)-e@FD=7en}*e?eKB;E#El@C#xv9Pn))@EsfQ?H%xa)A5=0{|yv` z5HfF}?{}Wf{{8?<1?&wX37QSQoB>~8z~>wAc^%*2TsC0iMNh&4CWki# zLA#jC1y(np*%ano6a|rYE}KohWi+V9<`Dl&tK{Qs?zgo=v&~8ZisCK^*y#Wkm=_aJ zPVklO8325pfPxPf1pHJ0rsx&ZJp!XHWzH<8kJ4q%gU_6deW=9T zZibt;f~j)_&{;GWr&uLIK$QaA=S&}VMd_?EUwee<*cBD&>idbg0^vql?ZD5!v? zv&wut3Co~FSjvX^9l$2$o}%~1;7?*MCBh6L)@d(vSk8*EWj4%CxfV8w!>_uoI4|uf=7JpxX_-tLRA0l|P;i3#%B@ELguPvMZLv=~n{!?@ zrVpP~dTl)pcJYT}EfnQZ^euPzy zFjrvTb!KX{pq|D2sM@>)b6cFd$z}Yp$iO#3^o;m*v|sfY8IetS+I@Lg zu#W%%@i~Z{eFAIK=HtoDc5c3R@D@Ht1b+f){5*hb1SP?d-3)->)Ca6%IQS62yy(&P z=3oa7j_BAX#Wn0WV}Ub>!$Zs5Y4I1pQP2^@LWJV0&PA*nbFVS2RJYiD(Z|yxUP3{8 zl|&H$wGT4ecm}NdIUi(x3bHyA`7@9|yLB&uB0oLWYS<2iI##dK$J1k#C-YIZMLvGg zC%g4nG9NuwKJp2Lu8z{j)8m}`5c__-k_M;Q0@&cPM#5U~0IWIbG^kVqmA~m;2o~e~ zO?S|TNfF+7hfls4Z3b(X8Qu&=9j=vcal+sF7Tc8vZnAbRbJM74T^FsD?{tzki)5VW zQpVKEcRP`5l96^EpvQSWZ85F0YFh_-Ta-{r5Dt9C64<+qM12&oZ9CPJEAnpKOG=aI}ZGCN?y}t}| zGdcn&*3KoAVDa1#P%A~nb1A>dq~f`POk6{36Zq$ELj}|R($)*+;_P%=A6sxv%f9M{W`Kh@0yMmXwK&YJ1{=kmje@;t$~IcwqBWp zavY@s!;VlHBW)RiWlpF95ScAsF?&ca^MbUm+N3RJv)3j`!}qX~q{YeuT)4p4l~|19 zLV*;rP^K7P?e9L~zIJM;Ab|8=-4khINKOYM`%#Zfz(x{!UjjcQB~B8c;}jVa<{`Xc-e6v?%7J;oqc z$;%)iz8>BvxLkmBAq^>f}9Il!5A zWrTb$GK+;dcua$gnt{@Ae{oU;4wrvSi06l-5ofPwM>RXD~I$pqv(*R@9 z@t{uQoY(+YE9bZZc6jPGxm6KJGHV!v4 z)=PHoRVawL^ThWyTRHPRKfnAt&Dkiq%$Ht)jJcPlvWqd4z||_xr7V&dixW?d`qy`~Pj3?6ddUYp=cb+OM_OUORa^ z&%wx7cm{(DSBI~Igs;hl4E-)X0d%r(Y6nI&@@Z~{_b^v=SQ{Cd;ocx)1&BFCoz4DS zyf+68#>nY($YA#8;S(58D|9mX5id0}HZ_I7$(6a!G#<^d@j zN!0&g3VSQA7nUC1!jQd3u-}ABou_I$F*n^_zUF3S2UOh6k<8S_8GeIITV?j z9E@>Hf?kbfsTxNd^XXW4)8!9Z#iZ9fIst$igpp7mqA~!%lu0$>vU* zp!3wPH#sc8p;YTT&xF-eh(S2EZ@AdH=Hmcfq|H+gYjKH&L+Rmep`*E*uAg5uBR43M zmE_EHDMq@KreW%u^hfIUfLe?%dMdz~A6q+k_mv>XHml~D8f}bW*B%mohv%trSZjE0 z_qyz^YjywQwFSac2lpe4Y_>M%V?Zzc6SjhoP>g@j^@yIQ1VLN3pwsZ}q+wm*q}gY2 zCCF?Rmg2Y9H@#BphI)Nv>Cj9&1RKjwKsL9`#&@r8jvcFdLB^H^_)%8O%*Q0h@^04laba~CkkU@c zD)_pE)u6|$4lPkrV{8_$Rj7f#9$Sk`Mt{VKDABY$l`3bv`VeQaI2~dzUpkmjJO&iw zbcnG536f&P{^ZCW_5e*~svfyHeM1jKR_8>9ZQKxO%_)PzCOHmkC4S)GIEac@A+y{P zfc=SMgvuo%p4r7_vH%u|{J<)of2iUpI?t`*z}lT0O8V4`?Lbr$XyRT9mX~4m@lU{^ zXH6+rMP_|b7aIsmx(XlbxxP5oU9yEy`q@dT^RqY{-XdHnB#dy=EXK2w^2MJ;S!-zf zjq=(MJkWqIFuplJB1Jdh%ZScpsP!$gs#pFc@=l81M2w0^!iOFv(RD^q?)AHgeA zuvzu5E;J^B30OK(2vd7{z#Mcm+_GZvP_GBumSO{)t$PW!l_O4Gpx&RLD`Uuu`Gy<} zEaH)Yi=+|yykM4`7o_Q#g2x}39Z${)Eblh6nt5Mw`hwQw=G19nNVyKp1BQH%gvFs|+~UL@`gR zI}cr6NF4IetOqNq)sUbWPKXo$+fsMlW%O1oNr1_s3d~z zuVspg4l;f~$jglc{=}Q}m#L#S2wAP`^X2^F0F%$L&o7p#{ntTkcVN=T1+GEy>Qws< zoNw;1<*;qoa(DvpMXre~EmTbtf0e z*;6~A(~8+>F;ZPE8<{HKfF38byJbs!O_bz>ujj2mP`L7#3`(E_YZU3`7%B1g_97VX zqf%A@zWOKQv1Ude7`&)R_6<;~c<7q|xkhlG*umCtdR`h$6|@Y>(SxMlDDL7=E;?eI z!OOW|&w#e%x!`0u7aT9=f`#?Q2{%Y$5oOSPGxK~Yl#;)OZ)yMPx#pYBz#zATmSEPu z4CSd@4ush`@V@dep#@hls58;yl|8;MZ3BF-1rv=mR3WNU(qg9GtB;SMO`5B zQgy|1>-%CYm~sa7E-XOhAQ(9K9E@q*TvL<`c0!kkRIN*dk7_~|r^-2daEO2C7bc;RCKxsD}z*P=y!$E~);G4dX4DNzK~hotF12*o{>z3Phf* zu4p*k@{icMKra2wI~B^qXa{{3I=9wir557uFF?lGogxa+b1L;J#vQ)jh4V(&-B8;W zXGL0X!u=>mf+Dt)F{wOz3~^~y#%WCj?BPMbu?T?j^rqR9oJYfUp6lb52bfsVv*8TA zYJkm-S=&e5%6`0TWqCWO+d%D}Pr;W`LtjP1{`K!bb#ejEP@8fM&e-Y&Op%;^YyB|k zi;|o?*N_&%ITFjz9V*g!9FN^c=V{6!^Wt^Ics`DKoQ@|cCD9>T{lYgYB&IA{ru8o~ z9R165Ac~9^1iyD9pt_}>eG7;AiGv8ZbS+~(mQ9`LTAl}tlmT4})gQ1oh+tSiBf@AC ztR8C2MK-ZkmABQ>33DacZ+r&H&=cBJYZH$Cf2d1Az`7N-$78$MVY4`+dH>Y47&~#!;4?mmCXtslr5O z@GUe7&UcZO;LJvSC83}e*9xUm)2=l{UAE!|W(;w@F+uQw8 zr5XL1N}XA|pC7tj_((3!QfuhE*{TgEbN0sH!E!PzImOL?Ka6j%l*Z;?n=OG4C+{zw zXc@4-aP}2q^hRlod%qN){mTL%f~6h4vCP9uixn?#SZKa#4ddX4KH|Y;lgL1M+tFI@eE zRUB!vC;+>P?74q#X6{d|DoU;Lr&i5Ot(p##%SNsRl!agaE*R~I0lk>c%c=Ed-I&|tTYe9jW!PtH#q1t4_`$>Y}a(YVP&&6M}0P3B<3=8gA@|7YXfG6 zUC9M%bovVn8l3(hTR$bZOPrj=>S{#DTS_99(+Qep7&l@_Q*%IJ(?~Y{ z{(ALQ&>P!T+BDLb4za6O=ey}2S+B;hVgRmJpGFE*DAOyX(>31$ym|4Jo_b=o#r#o` z`&W4kC1UJEqf4ke*0`i1li*jgkzn)2(-er;?hmUjp{mGyLzmTZFUrV+>q6F{iFJrb z5wa=&8@f5^Dz1>V(dt@zF_++4W_wePxU-Ah0oM!K6H_>KYbbSVku^UM###wy(7EPw zOVv~$1P&-%I5@0%Qhbw$jszkne>v7c>9T?6W%a@>HKZOF42|1C(6V~<*6K`ebJ;z+ z;s3Cd@T)caj|afhu1(w(V1lbH*wP6y%)(9l9rk(r_WG{GFGt2+-?iz`aytZ*A`dzN z9x5-qMSvq|kX3d_EeD?oupSXmH@pN{;%BRT8iVKL!w_W;kd(dl%x1)8pZ*_TVlXmQ zPH^=wz)l9*UA3hRsj!#Eucp*Uhi6AVzrF} zF4LlF7|ty<0?3U6Gg{A1SAT+C25a%qN98EU0J~GY|~1Ezb{LGxlS*cZ}>JlU*M~MCl^R8Jv6Z)@JlzHgCG!p2)W@`Nx(YHL9Drda< z@U!fmlq!`kJ(cpK#-OEaVd#S(yX>g!ei99ob!YZv^wwY=c6Mpv@n(JQ2|OY5IbK}Z zLNUQ%Jmp3$MtNHp!XBWDQse2bvI+@Nv8Uz5`YtBr`Irz^<`w8rSuqR4m^PVM<>}wT zzs>~c+?8mWqn`N;WJYvy8v_1F0Da+?l)F6eqPIrYAo2Q{W_?+Dqhl-HWQW6j`#ESi z*S>v77h6sIKdX9LbKpiXmYtMxmBhGmlIkj~=8=S&5`cx(uFJtcYUc1zAryV^8c_f( zU2n~7cA+lzb?BU7gpYt$)-g&e>!g8-foqF2VIg6p=|x#5U;Ifc>-2t4{7Po*XG>Vj zT7V^fgk>AnX>R*jmojXi{cLrXeh%hKq*oLx{L`<$GKx5E8&1-f1>61u(Y7w`0R$n_ z|J%Aa=&8!l6piY9FbbG^f>@3uutz>)Lz>cY~vmm zw-AhZz<@mphosaV8wj`(+!TUl*D_01P?4ajZaJZlI--@ zP5mDxejw>lNuQOK?nQoYqC?W}l=Knl^dZ3SMgC*SPa7L0?cgm=*-Y~wuP3?0xLeYG zpPhz$Cz9pHJ(BixCJl|p$|uKl8k;4pE1gE~bR5&EQ*FN*Ld|~gZ2)C#^&;~a_YmWT z08(2&PiNdu7{}Z?4z5xB&peS87oEr+vjcHyCU3<6lS=U782HQeG9|fr8rI8txZ0dr z#r~rT7u)p~bsK?N{-}Y2?GK|&7B-;64sHrHuGrG28eE~JXJ$!%bMP~=wA4Isd#e>k-B}7ZiPNt)doKG{Y6Kvay;g0c~H8ZUnZ0ok; zIX7nb6>NLRj^_;Mj_padyQu=`G&25)?zI`WqQ#E0F#z|-&~lUE` zJL`=C`}^)slAAPz^S55^&!sPldSil}*d&RV%p%Z~Pq8B#oXBWCa(I%3sAat|1F7j@ z6^&2d=<|3sMl&Z^OtQ%t5t*p1J>f^*D5-ct>^m7dpOs7V(!_C5P_A3+a! z1%{q@5Y;yHboCONOGd_bu``=>#b!AJ96TSt2{o=ONuGsnG_zjz@wyw0I=LGK>eW(c zI3NUEr|FjJBKys{f~qYH;M_Fj<90{n0^{!sw9&lSUHkY=Pi4*~wB9?=6jDFL5i&X_ z-gTZ|CaUkN%52s5e8)_ael)Qlq-HyLai_gBgpOOJcgKc_maLX-9XEtGnjgO;&%D$x zYVQ3s$Bd3#mMRx9nb?Ge?aqguTa?_m1mjQ5$GM5tV#`==(>Ci_r-t0^@dft#N~RdlFac3*=GP9P|M6roWafMi$dtlpwEdQVu9k${H$!T5Of9pKP z4?qWPs*FFeM$Wn%13xsHSV7qb5}1X8^Rm;;_cra`lviW+(H2nu4QQc9r7~QCa>IEp84%%&Yo|ad8YP)lcUn0eL4nOhQ?O|0lpCe|jS^J1q zhCpaS#-EsZHBy{7mH0R@mD=BV>i76gC-!GPa#Yg&@rGoBB9(fUrYiMocjETU$85DJ z^O2+0Wo64zpUNaoS1Z#WjcRE+EJF_}5>^)u$b5Ag272Db?vE;b#A~-=Zhb1OzQLiO z_95zl9L|=r?{H?Y0-LQRGhsb3ZfSh}^sqX{CG`$xw_t`#T}=LUeD=@G=!0?ZL9{WT zVmqp0-B*^8m09~JX`X3I!&RUe!=O+-dvj`a5wpS&6mJG!UI4Z15l=MN8oe~Nx_F6I z`{LZH0j*s)E$9BYMWSBB;*kbt6dKi{}e%peR-?h&R#4`pW;68A>_|>Q4#tm6iyAw zxqL@%(YZPV*sORFGaMN@J-IlmTU~f6{@|Fx8?W&|>yZ~u-8LO4Zz~19!7hSYfRAjn z%4I?G!TN`tev^tmW*ni;J#b+vr7i;Dsd6^BdgmH+uINLmkMeob=FGZE=4gG!Vj^f`j{5$ULsr?XtPrTPti>+FSm*t3cn1fY2P{VK<<=cOK0R6Yn=MjCpA@%5c z^!Vi6wD-hr*vT_IBwmxkpb9J1Lyx95N~1O;zYcodKAuhJF5M308s6hqz^l);Sb;hd}7O|i)*jm zkRd&BH5!)ZRYGT+mD+{6+TUMfgThQp=;l&@bVvUGqI;62oBOS6K{XzWa;7o8UKIQD z4Su-f#WIL*ypv-3dsZ)9hkEpAxs>`@_5RpVUvsdFTZlZ-x5lr`{jj43EbE7rug%<= zd@{FY5Sd$pCON+SZNIrEuSU1ahjtJRaw4xjpdFpS&K}bkkJ?w!HVh;6cn}PNK5zCp z$D59Rn%=56;MyHWUQ0&Sxc6cVxbPri7U!DlbG^8GYF?Y`pKl6`?xx&K6_Eilg*B=` zI?UtQ6YQyaa?4Tg;X_VmIoZwX#xbU^i-Ubwy_yDFrk)olttS{7Ul=Uy^Y{qm6j!1i zPD7`nrRp25ujwl8`kJX)@a3rCG47}LH?vX|m8@p-XSH8ysjXFfF7_fztjo^z#^0t!RH-m{P_k5n~9l&w~=YYRQ?{R8N8FbF{R^aYsfmyh_ z78A;_r|`R_o52aY@T-cEY0C=;_4@YUm!l+n2wd!hUPp*uy}o_vxOWiZ7wohzao|c2 z;#aS)G#xh`A%6AxR66hebf_;KI)D(raQ{D@w?CbF93g)7`U2@xZ#v{hh+l9wkd6zb zLq!PjtJgOZzYs;ZCD>}$QVx#nc2Hj^=Hx;SsYzfd*1=Xe3$^mM@K3C{1TMBZt(7J4 zo?chNlmF{+P+YIB#xIpVNRPhNs4kUHSX>MF(I;_v7rApH3!qz?z@U}4g@1@(k{}ps zBhY}+--|sEZh{gvcMJb4RR^zRA;2n45Pb{wA*^BK~QBopSPhN(S=y`yzsN~=hoo=f#9!9lP6;5eTB~jM?jP=Y**VC{29p;9x z=wmCIz0oQVd?pCqxP$~-b)_J8Wod@i1mm-4B|Yy$6cTT8({hM+rlLP-Dp3~^az_^j zFerk4r{Bdg%lS>VHha==a02$SZ`jTB*PVkq*+B@6WL$p@eFjKT}G0{3@7p-VdxD&w38-pUi2lLgE_7Etc| zvD%`%WHr_zUZc@Qa9-Qlc5N&q3ricZ$y{%m+GclcCiWQ6>k8yP{G5fS}|j)>-g z$s*kCBYEyvi-p#tJa~}Ux&4@@ivu30xZ2>OgzC>YN{3`|DuZP0(eGw#;V0-w!qyJm zG@o{M(WyGaV;_}a<4&qdp`?RIwfxeIZ1$#noH@JrLp`*pJ9*RqHS;ZQ>4@L-x@?DB z=k0J3d5o`A*M_E{4IEEz8_+Y1H{1+KG$9K2k#*nA>ag;%AUf<$=(YZ7hYfXBtn{Li z>}&_|Z-g=Qq5*vyPEp@Q#ez^iZ+wfy;7w#)NLU;&7awR(1;4;91bJyxe?>qHC9qT- z(Wov0WsT~$cBH@JSaYs<47ZdIbaB>CJzB&jXevP-yt{!Ivy(BsRkWYX@vJy7<4w;> zDDMO9sg^B?7}4PV6YT^-k$;U5-w5~*1K!D zbrL!y?vrIjK8eVzs-q`LCYuF#YCtJ|(-WVl^B7`o+D!G4k66U*5UiVjDTBhaQAq6$;XTts=A z(+9{%!&;T*m4(c~H{TO>c$2Rn-W2w{(+$84xJNqppH*6_kCt05>#?m=~Gy)O|1cSLvbOP zcg=P>kslXJi)-Qh)S8deQur;$O=0-NF5>fKwFeSp8E8ibj|O8e!WRhOio_uw&VBk) zw|b3DEHyo@yco8*g|SK|PpqZVafu%RTc>6ph?xRUIg7x*nk@d|DJ8scn}`7v=O8x! zrs7=n67n#d#Y0j=4j$n70IKX;!-lOlmsSK_ zTyZ9<@u~yhz)(a{99t{Sjs`kYbX$hE?aq!Iq=+u=>+o=S@+-jb3g(3Vv2eVzpvF@Y z9S_((9L9Cz65tUHAW4zGp!HhmD4p*Fq8H)VPJiEpZ}76AFSu=Fmqrzav04-0Ghop- zlUK3*gWEjr^2WHziGDJOoF}7H|hbD~!L?+I+ufo_Nt4ytX z;2_jHe>#5gN6bMmwCG4|&ly?7X{vXAnf{uo|CI0#%8uHE%pO|dKE6UXlL6&-S-G6T2>y|IM;JFEQ`Yvbq2IhZAjiXUk9Pyo$@W5_j@zYiuz-Y#LRgJlfHgM- zWhNvkaTrx<@*8b7{GXAiH#{01O2oHo01x!lWrXh~e7+I4;U9P4gYERn%iUvLaZMzb92dqcXj*yk>$>wDAr#R`BdU30E7Sf9JExhZ6iKf##FZAPb4f87M_+s zPSG4!=3p+3+|UA#zF3PymM8CIKJ=34t#U)m*h*Sm-4}IWA4)ulANF1L{Q~3A$xtkU z^UZw#@QE zE{LYQR{@;~uG-8WVSLk#7t#7baZJWDaU{={8b)0RX530l>=!jp&^t#XQh@EFoCFdp zj^9$r2|PRCw$hc@L{{J&q6({2e;0M2)UT9el#fo&2)3EP1IIBHw}+b7#OFPZFU-G- z`%|}0$J6RXs&J~)!^85u7ze`eh;A*26`2cuT4dE1Y=1k~Y``tMerrA+L>O0;s-YK} z*d2kK$QWQTUUhSsyd6Z|qJzYG;dTG^P|Fv&G77fS`u$1jpkkGxN{!TXT6wU%_e9HV zdR7&wyQVngjJNWz_=HU1u}9(y7vV2#{qmCeoj3s4Ssc3{C%O$eImF}bOHQ06fR=ah z7KeI06dcW^>@$t&)Ole7#WRC281H$8LxRh|vi%b%6H8AJjDYzD9`nS0XLU{;U-di+ z$MGHcP-{%#JnORVp4?d{@k3a&F^qp*fy0O$<1aV26#_eyO`2XJ93 z`Sd^JLwar41i6pyrFQhz5}O6~h^{bZUuG@i`$E=&yCJ7vElMp6SyvRq3%Jz9Q-ToG zxri&kG+Fsl!5bE7+75qihBi#dF32pYit2*Ff^p#@^9Ft=Gp$mLtxf z6EAZP1>A*%!%EP0_S#;_!48|8-{XNealCP=cF?{zvgC18mOR>CI5P5>XUn79C+IWZ z6x5RkG;zuQ6fbPWuQ|93oIq5hxYwidqwKEnp99W_nQaEb3gL5uNUapm7mM{a;K z7b`sY_(L|uLDU|8jNgz>{J-Az#*a`&qcSgW`pS^li&cq@Ql{~9N&9pr zGqy>}&n1Pct1|n33=f54J-$X&fOd}Un>4sr=HLFD$gD1NK*`Mvc612fA93c1Lj@lF@lb((9YwuTRdbOD_f*k$RJjD_#JjP=@)_kWPOKFNk_m&S0?A?~=oyZoJC51a<=zVeW;g zWQC3(`f0k|o8;MT?$~}*t7|tN$1BRo*J~FvQ?TP+QZi_s-6ZtkCMHMb;_EA~YiJdi2ZiONMpx`6+ zt8!o@XIQ+)xfSQns(LKXZvzYD{B|tXGtMEC*58&QORw)0O#H8K5yLD7Luxp-OeKpa5Q;oCB=lW$x1V~`d~xsbaZPSXgcE_V<>I|ds&V(2j? ziB{tEbi^}cX`?zF38D{!tKDbZhy+wuU5GycK#;9hOW0~c%Tx-{V>Ni~gmQeUdilT;w4eFClYgKbwK4)f~b<6O~22XDM1luAL; zhseq(=|lbT{$ZK}xB>)k0lKVRgEPFxiV%BeC^O&y5f@#LTVdMtO-4g}i%@nO3)Fra z%JxyTAN>kf*N~$OIVLT&oB5N-CXElzHYqrrz?~G%<=Y7D=8e>DE^3V$SQi(?=gBgH z4O)8~8d9mtAnZl+VlU>}m5d+^>pGNZ_q!GY{SS{)H%~)1#{#ywkaZk^t_3SRF?&e8 z1dJPB>_*|q3jmD2&3-+ECC`i<4K@#oy?8y}AwfTH9=h?x2M9>}U@U2wR>gBSjI0?( zF4H_Lz}76y9gu_@SiAg(c?MJ!nG(Mnf4jp=)d?&^gc-d1_m=YkdB>8h5Vhj%aNRrh zBQaTs_N+Y~{CQOZu*#WZ~BN6wdX)GI_7Yz-G9)z@(b+q>X=QSzWGVcS(x zu`<;1>kNTVMnZCRJ0FJ%NBB(pM}Ni2f@YZZqfCRMWY@v(zz}~}J?ngOWEAWLEqgSm z?${ij)J3Q`DH1655BSR->BRu_a3ez$5wk z2EL?$&^$a*mflf^{1Ry&(IZVWx)6+(3XFC&2y5{ua#QEZ6vKq6?JJ_rUh0OU?C)J*u*z zZ@DR?4$$UuNL*T@wVh&S|<~sp89I zxMMerO^QwG*AA}>gqNrCZvi06#pvEBCT)pXbr?-pc_`dG_|Hc9YYz25GBWs z3>E0%9jKg5U$BiTI%7LxH1n^*r^9bO=wRSS55d^q_H#gW!j&8ZY1jhIiXUc5_)jfNfH5IB{a==s``S3^4c9^k;X=C6LB$>6Z}7vlfoee>0H zhlk5jSdiz{#45%1F>)GpX{Vvi(4$#}kBl4S@9=&O>7q_|)V5Nxmd{ef204Huhq1>G7nGrp4?5Rh_};=vdXpJXQLT2gowtR%hYyUX2xOnj1SD; z&kz3WCGo^Ah5_*W^{NJ1qGnQ|B^ltds8QXIJQ$iQqM_A+&fw4TJ-u}ZuQ{ke%>KiB z1w&Zf2tdc8m%QQ8VqnX?mt!$hxEa4q9`)y0Ft44BFuV`r7aYM5ds#ZPC>;tT#4qIe zG4ouBaIbH9I{lV($Vi7)A;d5EnStx-lDlRq;5=_Ma?sD;}gm zx_W#l*-qxD(|{VCJXT2-b)5Rz=5Iw@SQ3$Nc|l}@=Ys4!}1T_ zzj9#tDQ{YlXte{dsdCb)UPk?3uFc>hh_z|Ue$xtD2t4iw5P8$;^R;eGcXY5$xk%ov z`qIEOa*kskbY+{FhRNG@K;e4RicHPCX~n*au2oLP!F^3u=Z!BkUghE*YK@`+<|zgD(VZg(#(^tY674ka*i%D za=I=jG6{|WfE!0E<&;m{d2YiW^#zJBLn#qkhh2KCa>fkwT-eGMd7A0WG$&eU)!}Y& zWO!^X-YfTe)`sLQnWiGRfl^0LBU>!oCWjd+{$H#WT(n}l6bdc8f#Zil%UWD)Udq!R ztKm3MdZJ-GhYBKimpg!ph{+cpk=c;t)MK**m$hd%+~5B)=;@ueo$&!qkgEcRlq z$5fQ%dsOb5K!gUkA01;H$h5DC!#x~!@f_2>yo~8;taEpHD6ksEbjPMw*l(xws-}=!Z36<_(v-GjORr_C;j- z4VT9B8!nfLAyBeb--oS=F2b^V&emTdt4)+|Yd1c^#&d3L@F?1-I8~&{9?}5>ph7b&Sd6#*jHk}K$^XwMozz_~i zpPH4}g>UL$0v#S+eDcVxoew+a%j2>0`FQNIC5>u727?TBUy?jF6Xxj0P8t_xlO?6z zrb~@h!9X@w7ioEB^wX!{<(j^-=;b>9s#E1Z*EaYI8Izgpj0nkbz{e}VAY0?}hB*bk z4Q=bd`$4l_v&V&l5JUS(1NO7ktL^yr5YI7st>26Bp-TF%Rd_u>JmG+~$UAhA-(2Li z*1`-k%1~^lH#ut~mjyX%0(%?U>6X*u0|U$_d^ z2_u{5SLU=LFt(DBktxYpc6K~5aW;+$k`puEKLUp2@XYsfg3)Q`;N5WYX0y?r1HT42 z>-BY#8vKWaJBKIrKiUm@8eE4B~|EH@&hEkpR! z$FL;*7{jUq=2o+89%5y)4k)10w^8P*Pi1}QscZCi*ywQgJxA{!+rI$QyUvV-J6=5q zs~O0Fy+CS~`aV`G+!fq`$pSqi*tVU6@8WKA@l$xJjYQqjG6Zwc=)|`;e$mWCc4i6L zARV&SggT$BLVaT=s#$5uMM4foTLSF83uQ*KhEb$ESNOU6+<|?tU5SMOxPpNCDDZ&jmIJL}wH%mG0X&h2 z9J#^ved#7ht?{eproyEVcYB@0#N$EhIvR*=JSKf}$dfYv6@&MP0oZE)lkC3e_fT2- zM2oG9exe)EQn>GleF$!B2@t;7Z|)6v2k%LG%{_znhShT(lmIGs`70%Pgw7pS^Fc^5 zD6&m)4yy+M$u$jb*M^!e!mW?USls1_lyc9gGm-u~0hN|nd>@6aMOtR@JsM~^ufoD0 z*j|h3#cz5vy-yr)&+jkjcpv#@3gF=j?CeJMO6ml$qVXq~J7;`Q->8?&4P44w4hi?2F`Mr+QybTqIF@SF@FB>TS@;Nk75w?9wtSNz>Jhg*z|dzIdXS;7 z!A4`tqYT}{&|?g>Gqe?#r^$l>Qn;}OCk|{XPuPyQnGwg?c6LMq zA~0kT$nV6>C(wy_%@8M|3=yt2frHx>{_b@iS3$#>#a+;cSoCBSv>y>DC|-ZkmW=x` zq4rr>DD~58s?04?4r-L^D(Jh!3)*rW+U{khdhft}UK(j6gOq)iq-XfEjM$E2?c^}5 z4iRbjl=3scXGlq&e_GOzOi7Rhloi{5CAXrog~Y{gdl%UbI08^uF>dvWfZ6CH27N{}48;c>|r(U{RNhWTZH$5oW(X+5=%LU@!ChjYT~gIsh-+B@MQN*bQ!*LflfNTr}mXR^XR6A-*P|Luvg$;;ft^8??(xL z9PnPi$8UN-24bn3+>^*`kWkI-Cp>&?W30J%8c4~y95v`-SRw>r8@+lwUfPX}HfAFt zEw~9Dxq@fBCIF%SKkhWt$lhMzh2Ao~y^53>odaNGi({|-eR4^NwwhHMK3dJ^eTU&G zO7!Cd&sWVuSHy64s%;jK6}seUJ~~@I5z(?hZ4)+F(bkIiJ;N0|N4q3A9{Rs0GUG7SbOg>!gy~02Q|5^ zJE~k1pQkB?1mxa~j5nK$HNl_7Qp2k4_w<7@d7QAJzv+Zrl(6?t!FEcmreo42+3fmn z(D5HoY=U!i7m`KCyP$6%9mi>odvAD8_s3|0bZZn`=u023)G8}UpwBKetWc!IYoG!o{UvZ#b zeGTY!l#S&PUf(GfS$hdVA}szdBCJ=Jy08g~m4Z#?K}-z)Cbka`XJ``?A;Bi&@l_I( zGA>6@wqycRB?)ArsziQkMPHVW^^N=6(D-`jd!_=dpYcmdeL=_*ozm039xT9SIS{{} zp?LcS{DxKY!4tSJ-->1x(?k6(%y(BIO$HvwIL00>%H{(ta`Sri*<>LmI>*vA+6NmyV5B2Cm`T9gj_|I_Duw3z<{@1ChyfPobTy+6hU*o zuj?`SI~YFdYW-EqV3qLA1C(7bqF;^0HOl1a9ILu<0ei*%WIn>?isNvnawZOXVM>1w zF3P4fEy$m3k1RSb+()}`YV;ONM7($2*v?$&e&A!dUX4Ie=!NJh##WF~ulmqh z9{5l7w_Y$M>ZvhyN$j17HGAU=3&LtV>(o<^0kYrdL1Lq-L?Q(#dR#Rj5mjwe^JQw; zpI+nJdc?(k*xBfta(~LX z&>?_>_3B5bf~CY)cB5BVgSN<@HFzX7!Zn^<&RXP3-Cm&93XUeh!8e)TyXIAuIr270)>FRK8cbZaX?T_s-~pR(1xi)xrSyL?64zesoC8BTLcW({GxI zvB$M}sfrI)4{2SO8WL=S`%t`VHsdfRuvqt@ir(f&HtOQgTj2XgN{bht50OlM3G2TN z`*WfbDn5vgZB%7Q!^UD(M@?$pkcfBQu&Dpip1hoj57zw6xE^xQs1Ch{b(^;=r)wYh z(}-&tI7!~a;|=%wK)U@i4Pvh7$7vr7qJwP;Is~jcI2=sFSuiA{W2I-)ioVuk>w;}x z1*2MzO%As41iSUvwCJ3U%X5R= zDk7>;{35O)NNf(a{{YnBWSRm{*D<>F=(_0X(0O#^&)X0gys0iFC$jJL)TMId{=oOq zq=_#4pe{tiq3;74Jo027>KGl|w!>Pn|7I&t zbLf}e==9d3*F~nb9z8pPhlz!_(T9HNkB-0xX&c;n6r{}s4vno0q2!Y&Q{x$?XQ}xf zZ*(pZl@n2!jR>eqgY7ZYr=!t>QV%U4+(^O=Bb;But+^4kMtj*M{F>ePe@HJEvzp#k zglu|SkDgA(Oo>k4w5JY5a>pth;+?I|Ir+i1E$BSL=Jyku5yah+9k7Ftd3e6ZA4TTU z=sC!lpC)!PvYO9vX7*P5gKZ6+9ZBVZm98jmI(#7AfA(F>xZY!Ex1wkWs`ms*0dg- zC&772`d^qWWM`ZZefLprPB4>4?M6rNvR5!D< z!x;>GA@V>xGMohqmRE4ENh+dWt#sD^y_! zBb=PxX?z?5aac_QKd=DQI7Sf%e-fs~Arvr@w)BYzBB7JckB;YUlGJTpwUaFg>|iLL z8$BoaDWv8{Lm*vJM|3KZQf@- zhit##@S|NZ>2e1Xo<9k`hfA>bY_I|$k52?_Ml3#Wps1i4%JlOW>--xsss;Oq&s+?y4Ly*b;9%cQORkwZ$!`_)sy4JRCb z65m8Y0{8W7xRBr*MmYW?*Rag{PX!Yq41bdKgn8gpFdRF#@+Wx?VYZwKhL0w0X*1F#BDUHsovPJ^z{U@Ho zW{ln%d{68I{L)3?CC09S86BG~oT}s42JX$HgCU35#9=jxKw;tp0vO9dgXrA`uALTj zT$z_@J$h|qI0oOy;2v+$IXw&VJXDWTVMyBbyLeBM2CIA~)|;@l9q`&TclE2`eKxZ$ z!=N!^cUaw;kMXA$4y2C%MfOv?zcqN7`V7`+7>zK3E>k~w_e9F*1M+2Rj5?88hCx_; z57~HPSKE(HJ_WYK@WW`W^uo6EwdmK7%XpuB$W1eF;5o2X4q}lNJrkpSX>?knT7#LB z17LS#wYA(^XN+3P1zkHz^uU9*KY1ceC2k3BS&LSyt4d^ z&cdLpy=+9h6}{0Z;#0n`VqG9QhXGzkycwjeV1%c|979+5 z5AB3gHZGU>Py@~h3qh8Gdp})Ru#EKU#eeL}Jz&?E`DKBh9>|K##uI zx8O({P&wAp0<+q}zW;ZWtceGfE@#!8(Fp8;ri*u{7_gM*5i@mDkP5mAgH-qh9Y*wT z!^mn1udfD%M7^z1<*83JV}{3?SOHLzu@>~4f{w97Qysw4C~_7K*YFT_wHK?X(#WK( z9G8J|DBfa?QKXD^P2NzDN84sP6A;?og8EPIpie=Y1r$?-wxJGfZ$rd8sR?{=IxyAZ z_RK!ngJaPI°e_JKDPFHDRBL=h%c`&jRNsQ0U}4f}GUV~ziC3nvgKR-yJ%Uk!>| zs+tdhlE_HVgXib)J58t>MuyU%A@&`@*932+aR0s!z2v6|vp{$yIOdNQolH-#?RnG& z8aoRr4ERs?(;$04eBAI*{nCo(`9R1!yi2|c#&G-ClCQmG_sZy4zIT;L_(2ZY$nHAS zZn)(6-~~_6FCWh?_2GY+b_0k1f~VsE=K*q zkzv8Mi*)F;U|YEk4G*@TgOEJ$%r@&g&2BR&O>~2ef*m?(@<4b$NK`*ShxLClJC^O_%C;Z}VF|f7c5f1LVmoXkfv69Lsa5fzh89KjMIEgwapw zcQyeKpn7!~lyI^niB52hE>r4VLwK?Q{i9y3hN2M~#QSswleO%7=`rnh1G-g`HY%?4 z8X|PYJiHSG>b64opby=X)(zuq0sVtRKKgn4BRF<8+h4#h)s{a+ipY)M@|$tS#-8Rc z`rT%BDggw5H`u<3-;2B*OFYn_KTz~_G1pm5>``~pvDEbpJxxN2gKhQc5BSrmOMgrV zwpFA*e8IMv>5qxQwn^y^sByT7(AXvg+qmV`AA^Ezbn2)-N`h_4^anIIZ=^q<7knxG zF*w+^EB!G=8(V1vP=Hclr$43!+wM<)4AqYGbxLWlEtXCRMDEnF(;~O(z_5s+1E)o< z(}CfUMjbdkvRDU#kp((1J#v8#gd*qaz>LTY9T*WQ(Sb8Cf$CQ1{yS9xgLQO4^eU_H zb*#405a;Nqb0Vkdz?qQ=PL?FI1Y>u?(Ah>jCJMwNLy^gr$Rs`0-R|x>P(R!=L9e}} z3Cn|bUx#lkSgF$Z>p$W;=AB1<{s((~{`HUh{O|1a`EPvUzyELElUU>6UrD$AR}6gp zTYdgE{AC%$|JX17`~SR8`TTQ!=JVh3oX=nMQ=gyTj{^VoKgZwgKEEH~wJ7_s|Mb}% z1OvU@jU!V}*@e*yobH>4H=DldW?T_=>R`#4-c-MM@AF zv^XE<6{QGq6VmIOZl@+z0uja}V>@w4dF;72xNwzdTo@v3T)hC*xQIV_x$#^U9n&&- z@ut=uq@`EAi9VFx`OoojzoBVkX^9 zk4$-}XJr;Jx!jpy=jYzVNZGqg9ij`*UgHM9@}%b&PLer3!e0T_8Rcv-*oy??|B1@W zCHKU45$ZH1Y`7~NI1IgG!9TnFAsc+#c%r;aedSM>BpzoY;Z1bZq~7=;vc~Vn z@enqObM|t(c;{cZU0kY8gH3@)V6*v&V^ZE6d=7GO%4Q9={U?&rO^YSmxB1Nmn+eMn zl%4njA~?qmqlBAr(i4BY55H(T5$}Ju-)%=NG6H-~x_s+muNi*`h)+U`Yab#7^yVRm(fw><2u{7xEFixYkdO`X z6hN{Y2)Zk-oaAaTSKKGBoGwM>bRITju>AslvoRrKTTxiz3`9`I^zb}~n&b!BY_1ig zUM-8iZOfJ&Y%Kpv zb9GUpyAvNnp*9a-)G@-ikf|wej%&7!>spry}}y9Ou#3B z2~=<-z6taWkN(Yh@#ZW#xr%nTM@Dw<2q&vi^ux`61ivzcH5kuns6)=4zMZ&FsT^nIP>_ z$5dCl*liE*P5+j}hK$i*0!^mYn%ekI13svXbboLE&4yum$dQ40418B(%e|?cooUnd*jpY`c56+3weIgC zX_R>@>^Dd0{ARt^T(0eCu@>wF3?$|z$S?zVoe1d&mZeseLz;v2p?n#W4db!*Fs{`6zGE1FD7|%#G?E?)+qf@4J zHP38^@Y07bcFY?c64O9;RptK>Efp4jCq%HE;jWNIpKEH$QOW3m^4Z5 zprW(sGBtU>j8d{^w1pTu35&5i^-j{f8mHubdoMY#z2G)qyUDB;cRIb=Q?YKNe}~%q z$oZ$F_7LU#P8(%N!ZjMRMFdA56v&Mp!dUpZr2S=jNQqxHOpY zB{ydDg0u>TBePur9LERSK16BM$_CqID1>JA=g68lB*5($KtMHn-wP-MJ*ZlAxTjNR z`U^llK`}C4(nlL3oH}3u(USNMQESzYYu}h3IsKHpcya*67z$;4SdwYC3#2uzVN&@e zaK?#t(={KT2C{4J8US=V<3YcQ>Hr?MNM@G<6s#DOQ=el!^>Uof+Ga{UPh&ktUFGIT z)aHdLgc1~xa+UZPRXX$S@r7*!R0mw1;NVg?w!BG_)^@? zRhlRVBaKcH*IBnb?;xwl)UPJcoFBUrx7emxHB#IB*gAZTLFvW>P~n)q_~qLd24z(eG`hl%ggO;u8L`qh>Ok z_#xMMwhAXYG1F=nk~}yy)6-KT2jbsJrbT{>LD=r9miK;g!^|}cB+%=VF@|U_gQ1|k z-m}RfA> z=yPA<%gUvx$0Zlk&b7eTa2ceHVpu)rP+5+|_pAU|bNTwY8+ zZPqnqGPbXS8=Vi(bR&#bcNTPqMz#JphljlSDzm=oj?m#hn0w$>Xr6WHycsW`3uo8jW@LA$p~MBSbpmlm7hGR^HWlB4HE__}?bWd@|ofVu-^+M5TO z(Zcaa)1^oQidw%qWd;3#dsg^>Yr zqmOa_rlUrRiWG0Y$fiTTcaa<*Qg+|C>^JsZfJ76xaf-F>d8gJF7TZFBdFp5$hD0p9 z26Nwf2hJkh^T7D@+8}f_M*^oC)E{)ZDm<2&?N71irnP9%$$AkSR*PTaS}k568&dN= z?ufyrq{GYvdZ9%aw5g*DwvXq`daL)DIjBHy`({9JYP8}E$@Ca(r{X@lmpG&EgmkS= zRvbo08*{Umav`3d!Pt<_k{4{>Ochhj5OaQ@#M~bTY@{asz4q3HPQN$(>j}qR1`^^orvCwQ}ED|L#%d& zOnM%-^#{KqT#qKhyp1-Vdi9Ef&g|WWA71yZxYP?KKh?6ZOyt5ENchNk%2|P+UjM`X zJ1*US-_4SQFT=9OmiUkAzwuw8jvvu~6MK=4D=udU+Zv}36;2N~k`??GeMt50qh`zONgumwBpO;29|3=ui; zIK^uTT-fP>@i-X^HEk&tO&6s_d+e!1n@hYZ%J3W%kdfhYUvSCrkKbU~whW8pLd0^l zG@BzbGCY_x?zCl?J1|>@Jp(iZmtY4bJ0ZI|uvoL@cOxgFY3^H_blyFM{2`FJmW8M7?Hz(q~&vXhTlm z7hAbSs0M7y&DvM&TR*H*u)i zF>Bb%E#Vz*0YvXk+z3>l5y>#8@3_j-dhD!V+cuzWDZu@rNKNapGlOk>(=pM7pU&1} zcv#1=CZeL=nc6j+MCC9kog!SFnp@-06+=<~m*<8QX2u?usw)eY)+U_b)&Qg3WW?$Ua7 z&y#GMlEl5B4fTo7x9?7d)o%d_V&Hzxx_n;6^Xt8{QprLXc)|7K-n=?&j*gfwTXnOo zd7GE1I0Vn!&aQJL6^Yn{TgCBjLI~)XBb0*FB5d@aBD4p_jZ=OnquFKN@Nbkk)>US7 z5m;X&&_i5a!AwI#EURIcovbH%WR(uq{(a|~%_B0PNMF2` zeG!)y8+K>)#e2D)Ui^x=_^|}n^{~(NTek&bC%n;Nwkf5)sTn&lC_0rR&U{C8M_cl- z<_he^LsBnqf;|&7S`E8FAV4`{IkPgk44QYNvkwloe-9r}{jrBwD|W*HRqGtw`|HFf zjW_je{;+x-D@qfOTkty18kqGu#_0+T?CD9Z3D{lhG1Z8eGFaa~=I%m|xNkon#{H5< z;tTT7p$@{R7gvd*k1bQpKbH>Fh&P|NvTN<;v_Jn<1Q+i%@4$2oLracWpTXR~i$d!H z7<U z+#pVSVtZ0%Pe^Qh@&ONW2oL;t#}P_IZVScTjJaKQgP6NlyZ}(tSg82{*oSc+bxvCo z!wZEo%Q;A~7u@e25WtK?6-HL8VQWRhQ|r%)?ZDW-H6FN+q?(H#T#}0JQVVhXY}W2d zMITH>yH$mJb@NOYZL#7hbQd%5b#(P!FKuK|!3X&VwZW#Aw_Uj9qYb;8`e6GZz|i0u ze1>Sl8`mzg_>1Vn7j(upJebomNy`N*55sdBue-D3bpUtP?vxig1x3M7bK{e=I^+?&8jRb1`E)y;r_kVXZ?Enbun zPzKorWC$RO8c<|djEK@R)3a#L^w^7l2?`FN<49hTyvZA576}@SCNZ0dafyQ%(Zm=q z8bMS{)YwRjaVKh=?|DvDb=Tav)6?e7`~Q9S*Qf6C)H!u(J5{%;ZZ&K4DtyZ}@Om|M zc>2((BQky4=ij3L`}`K0^{vD-%5Sn47d;afI-+hvAxSQtNel2*Sh`xefv^B<=z)b$ZNobSIC zpT%#c1^qN@20ImOb(X#b`3CkYJVJgn zUxhJ&D^bW>=I`9Jd}qt@TUzI!`FObX3)k%4G5dCSLYCd$I=^l5MeBB7HFq;YdUF@e z-7R9LTVQ5x;XuMg)O7hRn8DW{#G5fW)3n`Aq4RG?{h2)Pn%!65+scr7b59@0+X8tl zFk1au=JHP=vWGDyb4zy2mDUS6-f|Q)M5W*A z&%MDn#lD{F59@EOkYE&k7JRug29foPkT~*9690MtrZ$XTxi*n{9PkxXy5skcf-j(T zpFwWrN8XsQ=mYaxMScc3G5dhL=wUBP{ADmc^Pjvk@?Uo#2|2}(=`*=vK;(v-Fd}KY%n7r)^FUWKTKBgKldG<$F^}ttT{OBcf*rj+U zrCfZDt2ds2diWM>M+xhz!p_0?RCo7*dHg~(UFxRCTaR{1kI07OB@;eEk_D9CgV`wv ziQi`FjWVPUF&=#g^W_h|S7w+yX8%KeD*=<+CQw&aQzXPf?N9#XDP%LC#K;=t|mR&WqOSv&UDsQ$ee zkNz?RGy{bg|MlCl)EbYL)f~8&1i-80%<;5y=S)J1x12L|$IR(S7$n(?E$7VA3v_0l zr5EU!X^EM~Aw64WjBYvSxYqMW;vYR}I-g8miC|xUoWbe|1pJrwAv^ScL>im5X(ir( z|JM3BGbuR%WdnBZSLErX$EGkgd1gQS{T>a@5Jq86$&NWxvlfxk#5wfI{c=7trzpf;5f&nnMx|zRI(tCt znt`pE!CN^sxuYkSH!*E7*^;~BmM(mTRbW5HyzEwHm`)4Z&DYcUJEqG-i+sIWk^S5c zkv0$Mq*zc=k$o4exqECjJXi|pbUnX}{|({3-I0pAdRpnjO@o@B@)^^%c}I!N7K?Ve zv(3xtTwwPy{yih7?u%GEFrMpr%eifg!e=6QEyQx1{@gmIMdp}V$~mWrP0(8UbGp-h ziE6%~$J{1 z4pk}gMfR}HYC)NtQPO(WNKUIXz~`m?uqjja;@=`!3Kz$Nx#BpjnUkYqFU1#|2eU)T z8Bi#1;PVcJ68~n)a%nOH<+2a<_F20>3$e@VB7uRU&#Njgf#Z#6eT#j+0=WALCh^w=m|t3$odiKkvKKyp7G%2!#Lm02vrR?zc&jZ| zv}!qA8kfBnO7Gu_tIgR%5lqW=B=%LhoN%eb)pwXU!U%DF6GqO5EYGEo-rikSM7H*j zx|LfPiCEyD?XtH$N^7tMF5gVcnK~$YF%+TfbcBpS&|f`-nV8MEHj@bH=8Ej5pYygN zyBcG3*c~eywfwTGAajyQW#&9A3%>-%KBf5g#3k9&xeAVNtV^>0kRDYDb^)DydrA6G zbV;(mzZ)qx`=i^jsqtGFaA+=PeM5nN1vhp4`Z9YcLfXpuv;X@{6T4RGR2bi;9VnaI z?2?X=EuognbGs>>GZI1W|2D+feUzsAl{?%P4QPuDKv(QjOR}30QF2y;b4j)r2F_a^ zS(2UkKA%#+5!`@z1NYp_9tPd_PZfVx-Uom9tAvG2rsJvY7TP)bXO*`$@4%qV*aPYC zR`HRy1l;LM_mIS9h{4dcXby6`ZZ5OePV(AyE!lmTeKj{jv(Nqv<&jy@-ZV1%Pu#Rm z;9d4!c)~_~W@D`%;0^#3%We?>R!vNFIaDwat{t^c4ILnbcifjwzz~HU>W+`_gY%hM$L7nXU$h+)We1;d9IsLG_Me!@fiF}f?s;0MK zUX@U=|A+D)+QR+EFxz?|-rN{~Y8k{Q9pa?-ox8N0LQ9c4EssFG3&_3$7w7R}JGRqn zIRPUW7}xIcNH6({@~14PJy6c|vvQ~_QTXXRsCy&1=HeapBfMRs$4O)<2$l?^F&zt}AMUzE2kK!wlrUt9h#FCyzXRMOsa zFk09433Tf+NW%6BBXODi<1Lco#&7y0?A`|peMI|&f%N$KyvIAlRAn zy|rwd*gwQb#qxfm+a6?O?HH?kGSG3uxmn?ln-3m-#Zh%_h^FLl_P}>PZqGh}w=g7u z$$YF=lU%RRJ|2S)TQT&$D)Sg520F0Y>-+&GDv|Y^0BSCm)QD_&6E`i7mLl5!XnA5C zK5fG0?QNOG=VC|T$oi)MBEHv$+p;C{>GSn#n^17^*B;l0n_rCByMH}0`(t?>T{^dA z@z1k|K}hT3pU;G%6q9M&e}k4&j!*_fHk2WeTf-O{k8I#v(Id0}vFwrA|6Kma><<+F z6m0R|TDEQ5-}}1xuVYuv0|TyGe$REw|Gq6d_`2C`*Uf(8x}APi-fY?FsPfizkNQ2l z-Ga5$IbGkme)c_nAMfIsQ9@EXs#9G4$44Xc`JHiH*HA%JqKN8rB2xc?G!YthbI5E8E5Z)^Y@2?WM-6p&} z`K)1ihDk%|nYns? zIc9xP&$DM^TumD;T8p}8;9yHzv3J?bcd&tD&j)D&x6txzrGYj3c4G7{R|oF|)25l+ z+;yd_aqG9XKPzNN{!3V2hwpg?s&fHc&wHN06?RUiiO>ENL!OUqZx_S1g%$|*dxG?W zPvf6+p91r?>;Y+u2)2Yp4}3~srnp+fc!^Eom+7VOKC%n%jGpz5_uIVw>5Gl-$5Xw2 z&85`+V=Ysz|0UP${h0*Ta^m|h30m}-JhSAgqjM>H6clhQ=rej>s2x4WgB?1+iciX2 zO*L1!|7yT1cc$L~+U4f9-dhQ8d$9)+i_FQz3Gyace&$ZBF>&>u!+g{`*_TR)+_5@1j6{QoK+;cPpu6eR` z5YJl(wf2`V`fY9(%>36O4YMdd2A#Nf{vgqZ-R+P6m$x_Ro)0nuvTva^IdFFQ)hN$b zXC^;%ReuaLF34h&koMMI2TsO#=>T*K7iQmpH;gcC?|onpW(|7GDZ%bsm`m5snjfKx z%?H<{FKRsk1^oQhUMMxg)_p*!S8Y9T{AT_i(YiAvknxa*|G4=!m?4gQXQ<3R>t~wy z8N>nNiPhmjltH)U1zkM zf%&kbn^%{Fuqrq-8JoV#u2+X(UsyC9ifTO68$(^0N6idv?jPTfPfW=y7pqiUdR3O| z@v@&`y!mGoqC=J|+OTc-n(Xfgo(NF(y(V8p_Ox7j_se2J5Fg(nz?SzavftI?kI0on z>Rv$oJ1_+{1fIG2sf7P=*;_w8Y4iIJfn|DnK+8`2ZBP4y3$nE=G-q#q@1YRZ4)wiQ zUR~xP>g_wZ{p;o}D{wt?Az#q3sYmuOQSY8LjOd5$>0X5*uO0eoziU>?c_SvCsHoUy(f~hay(}?M=FGb_24lW&45C zHamW>R4ww0-Al54w7-^Tk@7v(z7<-SJzabwFLdm=kw;|xSjIm0*Q0uT@jsULW8`xX zllO~kgc?8IDd4Db1SSRlX=b*z;Mshd$KaDD~lf`!~ z_MAs5nD^V@!OZ_hHl%Qa!hZ`+cvqH^-bD>qn!OI5So+)2zlUwd3WjB9N*652#?hct z;K1e&%hSEreaKxRGv_SH4$LJ5ZqCCXpwyN$B0I+-=_9mvyEoAOM^VZkCU?)3086sJ z%`qP;3%vGkVOd?0{Xhoem<@B+eaKBG@oDadQ`1M@^BfX;-G|&>GIQiTdvJ3g((>Lt zFYuz*=6hbmc|qMva4{xg4GUs+U_NBtVZ+KCv8kC~S98SlYi4JkksI2s8aSp+i{{@v zO~dw6hqI32nJ9p-0H>nIfsnCZXnW?+?7fmY2l}_Xw;=mPlTszEgP7EtWhiDn=Mmcv9EZA0KOEzl zgERkQ>ned{0EX%D1uXCHP-}B-AZ^zFKAxY)V4tzr71?jws4z{< z=jZGV;wk@Wq2ozEjOWETk3l@Yc92Psi|57v$MO7%42+rl{DqAg4)*W0_P!!=Z^%+#S`0~1>~n5Z=xyYO0QhWWs`)G`!AeO zpYYEHT{T7I{IgSle~Z2b#=>$L`x_faM)sr_h*4>X~CUZ3-T zIIpoci1WMeNu1|xUbp5W?(dsE6c^mVH+{^3)3N^-yfPgcdEVBt`;RXkIFfy!i_P;T z_IY+e_IeS8G%_~e8f>bft2;J@l@`kx>#}ux1LLdP>r5p&L5bE0g>CgBFdz)r>Rrtr zpNb7LKQ2ojabVbHY}Wt4JGwCTJ}_AJAA}+QGQRo&veh61w@`TV!Bf*;Z$4O-{z|?X zHFk$t@ICY_bD4JuZjgD`^VxfKX{7D`+05McTBScyC@U`}kLgw2-`svmx~d}k`i3-awKze`)QH&KZozD zk8Ezo&V4L=WE;N!t5BQ$>vrzD99hp1t#$1j!i=mR4|jhC4)BWXD62{ODEx_1Hl+hV zb2uBRxSv}AF3I+F{h$prek!s<=%*BZDzZmf&C*b_kG;|Vept7`Ev5Uvfs!I&|HaCU zY~b3PCD~p12e;!vMfPPpV2ON==Z9K$x9l48cN4G3 z-fnnr?!bE>Rgt|k=WRCr(>ZrDsUn*;Jn#Qy(+ags8{mg()I%< zq3+QSH9p0aurRyqZCzSTb!qu#V4YY!HUY{8O5_I4_=4fv90|9|7Q`GZq4Cv?S5Q*tB9 z;0IS_5?%ROlC5`xm}y2 zDfIgON$PX+ z2g5T}T?*Y2hpo`ND@uYjfu~t&{fKn`y6_5!S%gO@w_S3PrK#l7tK^SbHly=ro@C#|*C2>J{skV9;b;0+LaLrOZ^D)M;|GypOrzjl?Y|Ii z>!4dOK(Tg8X=c8*#p*>Zuf9^B6s z1hVb=GRw2&BFQ~zDl*mlzqsQqRJX`gbU#;5p?b< zf$BcKm1B_@G7JAZb&!v+Dy<^Bj-R4nB@+i#+S3Cr4fR|LXhF6f&+)LUl9Ig@_<Ki+HvbGF=qi62}hhh&r-n{cRb_2v(qW&ChXpw=3mO(6+{QLL*d^^Ek(6#hu zx?ni=1W`E2#7;PKV)v$~BqwmGY6WxICOwEn~X)%v80y#+a9A^y2l6v6Q#6K3$i{ zq`h=9T8}5S-ij&1bO>HmG#=L;yp_oWpvJ@~FHz%}kXNcqW3)0J^U?_~(G+X+Af^eD zYU=T9MQLi7DpjQnM3u_PE3H1YwAw38sg;!~(Uh)-4lBw^tA=^W*yWk}B$R=|(PS-R z)R>0wWUMMt+gP89Rp&$}k`2+c7M@8(YhzQq#%QX+TUG`YGHHgq95*#yjdnmAr@^+c}>Y!Q!-H% zOQn#G@zrN|Wl@7vCmM&P9o#Uc44jHJR(r8zGLcL%)l%tdCVgWf%}YEt-s`6}MbmZD zyl8bb(gf+9uA`=8N!P`oQdK-t9n%R-urFg!)-;vzpT^M3j2CkAAvCO>D#d2nvht}{ zMB^Ex6a7`kYNQlEe-oEp5(zIRxr+i2O*W!nKvpHS1q5*`%jl)LKE)D%$kfFe zpvB6%SQ2^xsX|s(#-{XDiJBUfXjIg&v~0}8RB6f^j!>hScp61vL|@ex>eTykI3-zt ze2hZe@D-;F^QvP=B?M$xM?muEQIk(s=gz2@pUW%AF7qm?>KDbT>bylnsuB%Ipn8^4 zBxXI!T&l0CZ!}@*LWpEtQMPiJuf#b8R5c`^htwz5o%+UHF;6wcs_JX%W7VRFN~RT) z2z8_(2Ak}%0S{-MH-G+l=jO5_Rexp7%cUq2Lwi7`SH)rN zn0rjoqWqx%vR-9UF+`xTEE$U@s-kJJSBNf*jnwXF%9}B>;=Fl_7tLk?;p2|QAfGqO zN>j_#?DH2(dO$!`tQsj+x!M!Esw$(%t<{a`=qf3@@R*O6n-wrAO;H$*^vXoegHA~% zaYih2&O=V~PFgZ`a^7rt_D3bqQ$9wnDyF!o6iXtKIkpNVp;1-Vr&Fpno~Vq*73xw0 zkZ5Hp5znM!ik5eZr%F>(N~>`;W&&4D(Z>2JoYSkDQ1rw=m(>lEWT}hAoBFDxzvXah z6ib~t#$Szmjhu&?UY&qBU>4WZry0?4V?EJUnjb0k(KuSd>eVo0Fr)B6(NkWu1aV6rX6FT9rtu zRq<%LQmv}0t5vHi5#v>;c4}p^A(ce800kL0(fYJP^ShD`ib_M`3I)@jR;f%SBAf&z zQY*!+7MD-!LAov zlu6aqtkkD!eG)gSpGEbvs62zy*i>~{d?g>sRrTfes*?WstS*Pv<nXafsv;q^^*&pqqX8zS2Mckv1k~*5H#_ssj8u= zHVqGQh6g$8=dsK6^VsG3dF*mLk6sa@+gRNwE*uCJR}u?%l2|x1v3Q~~Jd>>&<(4k5 zt1bhFzDVUSAPklOymYI@MaLJm0f_~}1!|(1P>3FS7*|}mif&4~E9JUc+)BEa(~)}> zM;(Zx*2hzE6;C9Zt`xV?oMLjPU0hOky4B)V!i`p=Uq5!zM0=^?tTD*Nv_eM=4(vpn z^&<{zfzBNWDMeSsVHVI5gHSClZD>-L!gO4zE~SG`3=*GiwYUnEIo?#u6CO0C+1$Z$ z!5Kqmw79rJ*l_3t$%=j}i~vs{RnL^EudcsB)mPCr)ze_q#nY;0b$slqrZM`gYF6Rp zr3z1BRp3M$R858*zb13mr+RZ+uWwaN8r8N2r9BCNCvo*PE}3s|c@N8f1y5D-1Xq`% zpI4KDk_lQ=C|Z+>rJE2etVleD6Vt0E2|ER$$;N6#SJgD(?F?=*25T%Qxag4J8D88N z7)}xp&J3whOJO0YLH`>zv8FNB2<;&c=DP+j0kKu821x`DOsJZ8^_6s*0LH81jbr6h zt50LWj)!BRR~#Kb#3x?OP~z3l1{JubUMB%hykW%Q!jX^>SN%u=suu?23!*34Q&Z3M z#tlwzQ7cqUO)`eSL}U5{su|$wYd&B^(7O}alA0#pv^coTHJ-$UgG!Lmr$&25D16*l znY+*r%&mQlXz3KIsza_-N|2R|2((2YqBHt7s%Gpe%+yj>sub+8YKo~Ql~6DqjTlRSJ;F7LaARCG*5XtP1Eo+I znYfLW=*4X`wLufCEF)S(-rD~?Kx8>H$nfav9_!!f$EnV9zkIbd_D!eLySb=b;ow5tLpH|fw!WhvcoWi z#G+pkMT(g|d}+1E&N@SY?gULxZ&Ds;LEJv~r`pYE$dPvQI&&Yw}c+CuBD8KQRb zbhK&g$B$J ziEFjQwIXpXCHADmo{(6gC9c&Hae~AiA`$MkP*@~}L?Ya_h!(hB3tTS(*Hd6A1(rhK zP%Uu17KjrBo+JX{ZVR0#0*8n|xNRYiP8Gy%3ss6YxVyH6Blq)0PP}_S-{G_?6zTma zVik_uyM7QNs?WUNN}+NR^jd@B%=`N^ij$xl4T>}Gf2L8K1l?dzoOyqzMsY&&wqL{K zh5Mwqe9|mWn&n9|H2lVp!AOm796eY)8T!WY;vRPbuCwFu`0Ma+qY52Vp^sGP0~L<+ zQlWP#c-^%_C}-WZlB(A-Rm<@tRE|`gs#En^ovJt?xz3Q}g1ap=MN)M#)eOOH3r(7# zLf?ac+rWRD#Nj784mcq~Ki2WQO+Uj4&%P(_j&;!JyWqMJ++SCrVJdW*#Cn~?aUEoT zyiV=vjj%z``u&Xr;I@U{+X&v3D)i{!K^PAW@A(Jl&nmRLPaB-xaGrzH7J6rId+2s{+j8pS%qKN1I5}w?qoZ zFK?fxxIJqjDa#8!+Or;auYvZ1{swv-bO7{sMiFVfn`!+V97K_d>|Uo3#Ya^b`4>hq zg%Q&*lnU=*sz1+|?4eG3kk9*G8_sjR8PDgK9J|+3 z?JQ9`ym}5^fHD5U}W^BCwI(3_xts?a+s^rqCDYo+E;;rFgZZL6O?1nyJViFdS&cWKLr6D#8e5lQ9W+W=v&L&)nY^fz3-0+U83^fGN)sC})}XJ-A! zYf+!4qdrepp*Vatz+;07{eGYdJ+4AepicKjB1S^j!h-z)_#c3iUK)-YI*_(rq^%bV zxL%%!ChZ&K2~~MbY~pKT6JHaX_?pHD-4Xr*-i12U3z`@1!Cb@Zw9MfL=dDOn#^y3;kud zdX&y@={y$tGjHMimd<0L7kLZkw{#e04=o=j-u+bH;lyyz1hj>A=tg&kG`f$l(d~WD z5G3+FN2}gH#@)71E1BqS3tbN}ZJ`#LW4djj>t;a1lh1;45}gypxdB&0383K&N6>J> zK`Gu9+IpO7+bM47yT_?*yFy!zSKD@q8@l;;hV?}W3oe4WL7K4}#GvCELE<_bxeDQm z8;&$WCvn4(tK})&a3mp5;f8KOy4{L&yHz6ppiYBd>omZLDe_Bw`h|Xo69Rr;N(o$) zPAMesOT!5l51LhIvv`u`^?lax_mGun57!~tc#>vu9g;58A5TL4(Jc1E9XdkmP-XN9 zQ9V?m3U^zmuLRpi;t01b)EiL`y#eMoROs)xe03nM;e`GQYQ%#C?h}aXWfE7o;YgKS z!VO1i28=Hyo*!OSs`kjaVJ zF(1DxmvF<8g>nfu9QmAF!VO23%O%`!p|}^Ih@g6vz-9LQ zmzWy3yLw-M3UC3;NEAsOMN&s`{ViO73)kO*+ylZ7HylZ#XBLjUB@f_+BPn_Cwmg6v zj$AGe-joM$!GaE9IPw>H02e;w!Jp*;T==+#KAw~Za3NG4{81jj1&ch`B@f_+BM0RY zZaDIRT*3`UvT_MG99b-vaKn-PatSva*)5lF!;w952{#=1r(D7fN9yDfZa8wOT*3`U z>g5t{II==6;f5oXatSvaiOMD1U75o$5c1acFBh)H9f{RCOp*B2e3q8rpo#Js@ zv*r?mw@WHBACXIL@CaOZ0xn+eM29Le7BmhtMxiZz24JJDmUmWaZFK&9Yp z!y`(R8$5zUJb^@B?i7#P)@iPF!nKax`G{O{vuho>@C01E+(~zuuLsx0cx5-NfAAuc@z=$VcnVG@i1q{X>-=B%^6NGXUB>;gS#zsjAYf(Gsq9OEi@Rt{2xKUUEse< z8aJfLu5jd5fIIaGcel(qQf_&MrrYGDCiF)%%Ft1oX+C0nRQ zdBWWfj7&MBQC$a*kqAP^HPQ#YoPVj%hbnXjw7V19-6^=_&$EgMah4Nq@aoJcF~=hjbOdigk?8{(Enc@#U^s#k+%_%p zds-w;(CJzU5pG*(BjM1s5)HW9LL1?u_h!^iG)4GjNnX`svr#7vPLMfHWWwDR8Y`iWkx=2bg+@!Lk=@h9kDPZm4TlMc>|Q&bk=ng^EvDmR zWgK+z%%mu0wY+FL9cyU995BXR)3MrE(o1EUFl3{LFrwb9(kcvpV3Z@H=Lhksr&O|1 ztH29cRGnam6Fl8VJH;~JD;U%C0{+2_r{ngXsT;Y=P^r{o#TGKz+1bD()$$z;r%G)>mf)! z(NnRPW*VA2PR3yEgN?rNBM>A2Wp>D59tJ}j%W}CTIm8tTC=#7!-g9Ya3yY+;&iPs> zJbZ-0C@$9qVL-iFFBy>eXjX!pwAAW`%0yg0Phxoi*XCg0HeZbNBP{CSVg{^i;(9Qz zGKTd^EPAUEe=HKqLmi4>Aa9f_giw?*v5&+~)^mMC#{jwVB4)yK^#i9_7vMad;^{RX z&hnIoOe*a~o0>52Yc(|tqL56DD@-UcCRldm7VVrFh;n^YG$}bF3(BjSRe+fr^{?=;rL?p{u-C4YLojj1V=iT9%4bV{)v+${%YOt@7?NAS~_Ssuk~Fpa3t z)e0--s<3G8bgY@{tIm}bj$C+ForICb0zz$KP&bgpO>84MhoY7)T!dUhg+cR;`4?>- z*-|CZ&X@(7vN+PM=A5f&;37F`GLRz6>{6oTrd4u`5N8DIv1TvD<&a$E#w6srM6r;1 z{SZpNiG;)0DHNMcEYGk8TocHoMtiwpR2nO8hM^_utayIqkBOr-!nUGrw%960W*8)C{`-vT2|i@kadH|1m>y9 z2pdN=dd%2y<0ni!ebQviHtLnSl3yZG=Fce6nv4Qou&gz)5~c$ciA&)U$=VJA&s#Xx z!vta`j^-WRCcXYksZ!KES*fa)fx{~uvs{(d%L7!*T5rs$qZ$)j@2g5pb9c!l6|>J= zbjc;&GLuW5B*t>)5e#uOjdiTa2G1lcdzV4m+VYb zVhM(Cv9wdBycMORPQik@dG(E%RbG@U(>j+&M?R{uF156#Tx!Ynt@&bFgO%kO^hF)( z!WF;Haz5$aM1j}qj;Zb=*eF0YN)_6xTvbymBpH#OTm~*{G!ZmC$dYjMPS~gED8-l? zlcE2%9s4)Tkz>sAR-qUxDE8#vF(v0MUUbRA8B1r)SY*}23(n*+Tiw-OFmF*llVNbAkxdP!0{9~D$%{Eh@#eXs6o2Y$-5|` z2DDP08%xiun04A5^l5PRbbLGb(?PCq+oHZ2-9?@NjqPrz>b4y}v!|2pzR$|>w<;;IK%+_FvX_q!ZtN|AJ z=+4&vRa3CEz7cDAP3B7AInCMBRL1Z=WNN^~@p>RbUO4gkf;QA?<#G{7r<3)SSh9@8 z9lBS-w=TY5<(8GRh+FS&OWRe6{r8*j!2X%!UWeWpGAaMs*U3_K>Ymx(}_dl!3EQ{C)b_%q6z5CZTmz;7&1|_s}!g7abwG{#M^BrR6!o5 zweDFJ^kx&yZz2majhWaoMyQpnjcR^9z79$y zYSNyLN&vfz2>P6&`%F^J%ayHyd6QF$S7AM_CryYL|(7R<5k=aU{oSolUue|uDn{|6NC`)esyC@$+$W6w`~0#cLG!(6tFLp2qe{r<|{v zGTe#RDzp&x6IkD?nDkQ4n|Y3HJ!mAmd|gAy(C=N&tD(B&5`H{6YxW$zL=-j_3`Y+; z$$DF_kD8+Jop63w5uFU5e(bDDDZkdv=A`Wm{JIRif4N69c&Y( z;!gragkD) z8}wtT^e7o$HFEB&Lm=esG61VOS_S)hVZuRX2ftv*C%L9a&DXjn^vUt9K0e~AjMrnm zzy87!m7lRq#jwO3F1lYFs8Vz0%~+&rkuLmNp+1gr7#0>Y&PDJuL-5rAN@cmMSdT|n zm)n89oT|Cuz0PB6PMPRr)bsr@yeCbX;z0?1)l%yryPyN~ESj5Ry*~D_6aIJn<3~@P zh}U7=N6D+IGY(T6wt65rIt*Ew4_SxVs_5l%GGOS@CZUuUbV=>UrI;y@d8sJ&T|m}M z!KeT}{6YRBccPc!mD7AGjG0QEdAet%vkfo(EAeTQ!V5qwi7yZ_QPIFrd(5WD+5I-$ zjELoi1NA4an2LzkS0*{SFEcinj}U%+4&>L6_73C2$xw8M8xt~~i0CwwE1h%_RW=ZKvwkb-kaD?L$V5;+v*hD?rx2O$1U^1ys_HaD?=+3R zX$sZVCZ8*t-|HY5^!Fa-r9p-YaovDXD!ef*)5+Rl+}J$I4;?Qvad8Ki%_GNCF3UOy z%Re2RABxV8S?kESg7uTU+-}FM`JR`58=GHI#&K%XD>`rfoDOevod=|&DNN~i)ld8n z4{AtQ9R@W%S?lTawmUVoHs8CRIdZrI`|4dzSpDy&eu^08D3}K}V*b`PaBM+_L<12S z+qBC#^1TAR)CDH7m<}uTRA!i%#b!7rNpRxaBRUw~=uzW3jvuInvoN?h2H!h#EY0jb zAsgA47kIw0qqVE{FsFeEg%@dD4==4ADL-_3Wq{Kez*{)$lfTr668{H9-1G#UF+&|I zW2jLCv?nIw$-(0h4pM3(uNvR8+T|j27MuUls zlg^VFG;a=P(C6s=g{~MgYRrG?14(`wjjtr(x?f6`N*_;V^h%S7H2Z+1_|`Elt}5mJ z0C4f?Z>gT`ER|I~b~`1kx#I>vcIp#ne4U)+32n2S?5(}8uf~_d#BpKHazZ;Q=c@E7 zo~<|I3!k#$q48t9;E8U0aRIZ8!C~aps`@mv#|5`GlDyNmcCuEcZRL4Avo?;74qT%( zFGNqd5Y6Q(|4geT4@EO`rDd=$V6H?(f_a9Vf5wGS&UenU9X3^^_&yl#siihr=q>Vl zQ)~la6C8??A5stoPjZ8f2kw5Wn7 z6=B+?QF})2dZnYGnVxz#kR#Y4(!s0r#*~e<-64*o;(`9)*Bd@`XxY#a-pStZ;iY3n zl#LnTm5$Ac73L1S{1{%o6!uC#KNKY;Q^ij2noC%b%7zauE7cEW^kjrrUFqd@tmmqo z(KdMyijgy>8$PVBakN)%2vc-L#V9E?$*HYxy)n74I;jdqn{wEihRlv;`FKrH%j~O* zHyR5aP};c6&8Q&#|I#r=hmI;}nRyKiXMQn6POe)%au1#S@5E^>y31&v<@sz#Ii>A` z{5p(|0%S=;f%O}Xpm}GXJNuGLoCkBxp4agK$F(k*fA+cOEyThPY!YTuPLFt9GJnQ7 zf{fNR*qeFY+{G2n$`((ZnBTI_;{poqRmtJL9-uy;V?jrNjsbBu#lt`YLC1rR261OV z{@2N1P+!oeLC1lP1aT9_exRP92|ML29&{3d6K>VWCzj@v<3dxNvcFfo5 z7^1=oK`bQ3i+BR-G%>0$b*h>+O`UccSXFtsnmSDlfm^Pom8+9aRu^BazVHRb*Rv_) zm2o<0jX2uRHQ=jNSE!8CmEw&vc10{+%FWnd^aD0?a<-?F*TA6|Yc!d3Vrl9`+~x96 zeO|3mBNg6Yv7H{qkEC~kg^=+C2KhK1h5-j{Wbh8ER~w3UrURMEMM2(T<<%1_3E>3| zS7{2R*A7y$?}Irk&-EuSxVk4Q8*)Jy7E5B`0mG7xsu?f9@Nsg5V^(@MxdMDlkzAi+7?#FDC3IG01T>$rGR}krzu4OW+pS;;JocUF$Y_UI zgi%&90tZ80ByMB_$NbVxRiXDqlimTwLuBVfhHhDNQDk5pgyn*9q{)5}vU7yqKSJ*? zp|_nl+l&I``DFaUCp8~lsWlBK&BIGm*q?F)b&yv7-;I)C&Ii(2U|zj^+IOkCPno=2 zpYml?9x;_pnO9mmR2U^F_Xct7s;oj$=>lP>#}rjOF@2wWJhYs43cbtbh+?^h$4q<2Uz-Uo=W!-d+wB7LMXIO>}v>R9NW zMAaye4u;XHjsaq*PptdKx-$2&xU9a+TTlL=uLxT6$# z5-6sgb*vQT1qK-b*|d?q230n@k-ENe_TFH+_&H)654k!83yt;k7}A$%A`DamL9^n+ zJ+ZlE>Xa_R^Ly8uWUeT~Hn|vCYRK?&BfAh@0)#61JD7&(D&p!?W&46=Jpm($os`n` zWo$Z3%Oq;p{KGO$_V(P=DBNtA*T`XrgzmE=Ga9c*T*kQw^TmrzI?gj;ythyz#FtTu z;)@$EJ7r@I*ROthcTw&oj1gC`5%wx!fG*RCs=JX+aqrX`tKll2jCq4#vK5V-PMN}f zV7y1zKoD`{INn*1OK8kZfc(l0lPNL9<}V)er@xs_!J=cVv(y_j@_PikNpdc9Ry34g zZEJ0a{C2|M$>=Vfb29L5&p4K{K;#8V@xY64WsLKuK_JXCwiM$Ce!l1+53DAV*P}*F zFO6qLDPKp*Ls!m>lk<}q)K@NJ#}zlT>Tv5(w)Kl*6-&yVx<;VPTjsh^Cc#;9kr~E| z@XOR^YNUsyc+$a%5WDI1%DrxtJe6kf*UpGcI9PgDp!A) zd15Xo3~FKrXGBxsHSMypX$^2av&W~rQBk=ZD^dqrW?^2)e)ExMw}spm4cwc$BBjL* zD&L0{#dJ!ccxo1!P4fvCUs2KDmBn4owfO`Rn;fD)oYPHbrbxsltP`zH1nZAO{J)JmsT5q2i^Qwe-51p83S`0&%p{3IF{j61W;YQ+~Y zu`HiwqW{~)5`h#-9X=_OkWd>h{=^(7e^L&-J|P+SBE>|9JKlNlHP;+_Ub(dbT}vi>Idor>ILcn zQlO9e^y+;O^bY7Bpw~gKfnEi@4Ei(ZdC(rv)1Y0T--8|lJp$SedJuFU=$D|Mf$jp` z3A!D03+QIhw?N+jeGT+w&=*11gEoS$0bK>U60{PO23-zn0M&zHpeSfL=yRaOpz}fV zL1%+zgJyurL0>7+v=;PvPzH24r~y<9ss^n9T?D!SQ~^2<^jXkc z(3zmmfTn;Zg2sYIf=&i`puwR2pdO%q4d~VTpP+X@{{a0Bv>)_W&|g3=fcAoRgPsQM z1pOBD2&fHoALtjLAA{}$-3q!H^bOEgK&_zlpf7+@pvyp2po>6DLFa?c0nGxHgC>DS zgH8dJf=&P(4LTguA9M&P1o|)nok4#Gy$bpZ=sD0+peI0&fwqGl0Q~~=Q_v4Vw}Ea3 z-3avxbQNedC=F@^)q+-lE(BG8&IQc{O$SW^jRBnk8VWidbQCB8>J7qHb-h3Q z6!ZhV0eThmXVCMYXFxkazXSaS)CRg2^mEV;LAQgx3%UvP70?Z!^`NUkSAvqDIH(%5 z0<;XY7_IK|clE0s0Q;M$lJ4n?Tort^s`>lm<0|E(O(qDnS>6 zJ_lL^Iu~>nXeMYXXd-AVXcXua(8-{aKqr8X1|0$F4=MqD*soXbw?Kab{S~wi^bBYx z=uuD`=w8s>pu0fd2WKGJ1+)&d8gx0R4zvPvA!s4!Y|u>58K7~Xk)Tr037}&^ zM}h```ht3b+7Cs&0=)}*1GFFX66kr*GoW3d-+_JudJyz0&`&{kfVP5e0(}Lv3DgW) z4N8Dwpk<)*LGwU!K%W6k0*wWo3K|MJ0dy?rD9~Y`LqR=33iKgt=zE|yL4N~fK`((` z06h!(6X;3M??I1&9tO36?g#w>^kdK+pj$y(K;Hy?9rP8@7eOtc4WPB4FMw8o(x66A z9jFp?G3Y|jV$cH6XF+p7GeA>7<3Xo^P63sIP5>PX`YvqN&7g0BK8vPh9%w%3pSXVy z^bY7v&>NuFK?gut&|g6>fnEeX2igOA8uTRS51_|EkAi*!+6MYH=swUrpu0go1N{W_ zBha0o?}KgwjX4}?4jKkJ5p+Cg5GVrb1L_4*pbz1<7UwF^#h?p8OF#=j^Feb#GeA>8 z6G5i&EOB4B0mxr=cU#A2cc z!sLb_~zf1>P?Bfd! z7@`2naX!PtRXz@RY@QD*arovEbMy>RAbvb%`1q)&#isbM5(gXSlgWG!ft80}rj!X! zAmx`yti)heW}*7WIV*qpeA4J?F*o0dF=UI0E~cD4?&EXwotU4`mcd8JhxD{E-Fzp; ze7BfeKDYV8bM++VhUb>g`+R(^p2S=}w|w4BK1UZw%R(=DH0@$pel{&?Kr!`$+@!6%dX9`eA1!!J|HgeOoZ znZ!yAW@Q#CpPWDSm(P<1>U6P~oA1OJvc*IfQ$COP@wxd<%+F`b=TYQCdRm!oz7u1< zTg)w=hx@{F^(5wo=a$cYK0a4ZVlJOsK6{bR(Z$u1n5$Z^Bq%OET3CG-|%5>`FxF-D-+@I$Kz!mAN91@^FGWipMUbnWWI;M%EK>H z%7iD7^2;P<%cqrDsC;rx-6VFctNG8`f_+?I~p2!CmvvDBCe7Bez-ee!2Th54)uaGWWKjGKqTqD!PtS-bT(_*eJ zbA5cSF2uUih3hnsthxRWF4bc4p;J&O4qWfSI7nGC_9ba_v6!3h#HfqKq?{SP%Y1xp z9EiDmVddrOLzNG6>%%gG6^aAbwD{w&+2~?1Hx9(8i^beHwD|bkI1qFB+&HZBVQw5& z8>~dyALhp4Zi5wy1IJTYk61kI5gCN=a9C`*XA$V`!#oG; z<6x35CxXx5J$zW$!Tv=(aWFi~7dCu;ti<7a-^9=5vu%Kjg&@~+BJrjZ9R_)p;gN5;gYEP2&2+FmK5UkQ{n00r<;5O;K9&i4`1x3t?BUlX>|mW_I+&GNsJt9z z198p+P2Lvb<61iZF_?U)4~6)+w$FbYS44PR1L!|aD1wjc{QSp>MeuPwq5mi)UpIXQ zt}pZ-BZ>%*>lvl4ApfNAiu={z3*l@rx8F*P;aH62#g?^{kI%JP#Qc1=95#>-`DbOi zHj5bZ)?#k|y3QA#t0yrxJkimV(Mlhmt0ys+PjobV7m?4=#nqFTt7ll{`=5*bG9Bz( zAD`R5K8N8sY3=r}XZtX>e?6U;qo@1+H^s+CJ^AA?&WE{ez(}7==6lEk6Ar&jDHEPR zon#WTw$;ikRByTV)_+_DUHGgJAJ_5vk9Fijx)kE$I$-~?p@{If7T8~p{)cJSQ?C;y z=9W)le6e@=Y(3iS<8#X=F+ZQJM=d@+w|o*KU!k~jt+PK4cT(n1y$;$R2V%;>B;QTj za*L18jRP@1pN+$}e0**kh>@>Q9Jnq!1fnkX_zC&CiTerGvvdAs5qzHG-(KEFJ{*Pg z9AZ5?=LgBxP5C_0@oz7;7ZKh`*0XbdqzJx3aVUhHjBuC_woEhF7fg5-vw2SJSrd1Q ziOnK_<7ppXSb6fC&L4c3*eruSW@Hx9a~S+mPdB{38<`e!!^`?GH@v?T5ndr({$1=; z6JPiAHg(xhxD1X2gVc8q7bG0-lMe|}NS8ABW13kWUVdcKg_y`>LG?g5ELKS7DDAa_ z`!QusFRaUH9XRw&_{i@0M#C%PP%_=qOmL4ed=~5NV1s-Zn8_~306%7uhv10GSI6A2Gko&lVwba)8VW4IeST%*92>oDv|j+VBzc%e;Ungkd210eXBe4o zn*Ex55NI(s&3@&>3_DIr{oKL)y4+>3Lh+j^QaU=@i{Lx6Ba7VaARmB2;mr!*`&|*? z%?{xELlJz)da<8wT4xQP#oV-h$%lbCSC(FIFiC5QHf^el8HOC+9zUOBub(nlp){L| zIQYYR-S83fhi9=uGS3P~mtIHdGH5Y3T|z$0O_z_1F68s;>0*98-}m!5>GD<)>2h{J z+z&N+67%a~u|nx`4*2}X03)*y-)F((kKdpo_~sctw|t&p_$(Hl?&VZErU;qy17wac zd=_(M4lP3FxdAfA89s}-GDj65^Sl6=<%Z8qR0BN`{AZYn~T3&m$g=dL37mVrg=r(^4W2EN|Y3->233gEk^ zi13zoR8j68D1z_e0KRQS@LdwX_nRX4Rs`@pRs>%(fbaK3@Kpxz?J9z=3Vi4(4yeUCc1#_@4FiIsJ*J4OXZPuQqYWpOpH$;UnhP#bSkI#=z%4 z-Y!Cy8b1^6-!Fo%Hh}NLBKYb8_}Yu$s}JDoF+0etMF8JS@^zE%D+BoEkguD3 zSQWr`P7!>o1NhD@B7RqbkNM#C-7YeG7ISU+QXgj6CG>?wg!g&N;MjsF_`0jpUkKo< zEh4-%hR==P7Yv`p-1x2ZVQzmZ>BFo_IID&tbh*khIC0+yKE~Z*u6T3?>Z~t7(Fy#2Y)KY%&&{Z z3dw8+pZ|EY2wm2L$sfO6Qi?MPifaJa6QTZ2kW#}1y~_nHV4GvXvU#eVZJYck7dGL zvoPGm-C|+o<)okJ!`w9s#}VsMIJ_?hg!g$P(_(IT86W0`moVXxkNF_$Ly)FC>VR?G znv2=>BgCku#Uu|5U)0Cv<^wUy2liZeAy26b$p97+%Q31&(p#^QW~ZkSa5} z6e`zWfmh0O*D`*UGI3bUUCX%Hhq-GRTa7N3k21pphEkNe&c{cY7F+MbDAQtVjm$!E z_;1J$fo%C>ct0{SEhc$H0LL9hrp4U4d8?1ltt;R0VQyWy(a0>MXCdrsTD1=DPbm`- zE5!Fd9XRyO-9_l~^#HzK6%pQz;A2|bvdPN_$cLklp5LGc-%*VHyvfJI+hX{>8Nj!# z2tB_Q!1r(weBTb>+d;mP!s+rI@JV`3_i_?`R|Mb9Ip6tS($~( z{P%Pa9o&&7Jqz*O1`g(t#Lt8|5q$j4)WvN4iSe5ei{<(gka3!ikC;sxV%>dfa(jR- zXOa(x#oX}94OS?A-w%*^p5e2YEA#9kWZprAe8*z)g$moHJHg{m>x)fz7ISsEpa@-l z5Fqn1@}d4&%#~SfutI6}L&!u_lv{R_p6E?1lIEavL6st8@~3eaU^5xV?1 zfbRywXEC?_b;3|~?P0M(asNp`cwaW*S1p}+UTkH41G>0; z1{0b89gK-g!5o>87q)HZ7k%*qR?-3U@!4`lK35m=b-;Xl_Wl040KN{G!zbe?(^oJU z)!a$XAxar+jSrJ?6oaiK=Ex+E$c4xu_pA{Tr$KABRF1`d$)hyvp`ce(tN zI;OFUh&j6G`Zr(zy&1ikC>aDq9b(WG29oPt0yt~ zvEfO%HGC)f_*^}SxqPCd;X96eUFb=ylb#+W;rs4@@RTQzI>LuZcn15FFFYA{GgxmQ zUzh?77V=?I_YC#{?5-OJ$@eZ~O5S!MlbC&z)Q;Q+pUMTGYo@G+0vdh{mvN)VolSsOx(x>$^P zWXFwP3&6t46U|;SSfMyP5}-@3b@wiwN&AD&{**GcpV5`CIV# z^_*t-EavJt$%namjx9pZ-yuBdBuz&-qm99_8GO{iVs86DjD9Spz$axJ&#w3Jx$Ofn zKcBT(>&b_5W@YlZi?Iw^Omsw;Jg)YI=jus}ek`9`|5p3>Ts?`oe4>X5FGW5_7gtYW zuAa=JkVi>M#r-lJEau~L=f|Q95B&K!3{hZ}<02pC&W|l6=IH6Rf9L!7q%0Yk=lC$U z{X5eqlldMpe14fyCc2PGti)heW}*7JUr{EoLUG>(8Gf0M8JR9-WjeRDjIaj7%4^GG8e|=FbTKRQup(sc36MF&$aFC)^SB~pJ{ur&q><@j zR_3rGWbO@+dAgD5VpitZB4j=nAakaX>0(x9c@Z+750E*ZGErV!%*s5AGP@~DF9gWE z!072>R%S&JdhQF5S!HCpn3Z{P5i(y4klAQtx|o$&Uxds*2gqD)WV)D@nJz-+Ujk&V zH!@w!%DlP=nJ)#%{4XQZ#jMQhi;($pfXuH_W;f;Kl>ok*is1We0N?ja99+!CVM`Hl zcr`%gPmC@uW@Y|>GP{XiHbCb6My88dnZGPT=KcVgJB&;hvoaqlLgs4$GM}VOv;i(= zW&WNryXj9H2$1=_k?CSq=I$b7{w+Y}OO)A7KD-{lx4#I!zX$NWQ3T%`0etTk!S@gF zp{tpDPs61e_-Ujy4vX3MEj}AS4EoZTEB5`!*<`WkOq&(3);!$YJC@xA5vx0lD6I27W0+j@4+UJ>EFh z*Lrr&!;8@KJ;%Sj99cwo@58gd&prWsthX*^>)2?@?55rx43Ig;$aFC)bB2-WVz#KA zQABwE3Y~^;klR%ugb`DF&p0UBEtJHAiUKkJQuU! zrHxD%v*9%s5#C1u;azXSb1@s<1|!qOYd(6rpF&0GaJZri)pb9~2?8SAfjECum#lVpe8PVBOjBLjq(DGBRDv z${bLHOb&F~GHA<^XJopVm3eFtGW!I`Jk`i_F)Q=rB4qXrkU7!FbTKP)Oc62<4Ujp* z$aFC)b7~PX`vu6HXJopVl{vQvnf(J~E;TY;%*tF?gv?JtCVn0Irt8Ru!(wjVbPX}| z2Q3y>9=*!3($D8$m;3pgK4wE_%!*W(`DBK?9HeTAq0r`Zaj;4sR^njGO?ZX+m=Pw5 z@7O>-JTJsIAb_u>i0}>z;M-J0c!vk@eW?h(BLeuoT7;eh1Nd$%BD_K1^V^s2f{%S# z7qeyeTa?*NpY}*2Q_rugmE77xJ{&FnZ0ZSMY&R^QlxuITfRFn4h*_Br z1z=X@eLk6bK1a*En|!E8Hauch=3N1pm3cd5cJn@VR7j__n=TPgr;Cf(@cIT|HoOvG zOc%@Nrpw3F6NiggnFj+fEAvgp!I9~v%K`EsepaTNF0TY&R^|(o*-g3(MwtF%AmiS% zaGgFnfNwDQdKKn7CV=m_BEmZse8TGGwe`q{qmb?Se~ozo@jKb*Nz5OI6N`w$kN}xw zhL4zE=7=I>o){q0>PgHmvlu;30u$|-TgReC7Zgj0j-4KWS(&3Lvzt0L6!Gw<%l}X&4i~d=_;LVd!@Ggu zL7wGv(`BQN&rO%L0hpD!+9$JwfU)x_@*#dUJYrVQh5*dUtf9Gj5rsqomn3ee)WpoIwS5K)&noXVIm#L7}1{?3g-1SSN8J^0=UDneW zzEgdeyMF0pVve4=je{T@o{vwLU5y>>!*m(c*x^2zQeHfb`DIF(FqmH^u@Zw>nT71& zsZ0RhQ4L-As1V=C0KQuCAzcdbl?Cu!Rz!HCz$dKJy_~iQ^5J`#LgAeTCcj;>cHYIT z4Y79K#gqxs+IfrVyj?5$SUc}xR;IP{E@ov~J8v=9E?GP8VpgWL^Dbs(7Gvi}BVCYH zVwa@udP=n-J;Qitv0S|kz@(hfp5fQ*#46VF` z$%k~Y;SsYkzY&00nO~ty@D-{nV?&+G#6Iw`Ojyh<6MoF*5yO1O$7k~>2qPcmG9Ej@ z$1>p$&ti zZm~jnG(nWK()3yO0XeB~-cAhA^KGN2#aul*VUC^_E2QV?0eb$E;o&I6Hz|Pcqayew z2k^BQ!8avA5#g1CPgtjWI@96yCm-5Bi@EvN33Kw# zVukdahQR#&))fekI#|r@4-%td7PEDl&o1=wB!B7wXF6Y#*PiCo%f5e4?Y_JCl5lF0P)$Ts^}IcFuz!98>)=9c+S+ z&+WI4VR+!Ty14z;kv`1rw+(%2C`nM})&r!l`wVqt^% zWfHUfRx7hm`TR_%bNT#=(bHmXz7wNX786}eIosspbMu{;pU;-hYsrW7v@+d%C&qlY zn45piox&TEOY5tAn45pAec`$Jm-6w26%rah9&sP$=3mSwlj#!jz=XpuQ_{>6sFO@$ zHvg>5Lism6)H(m|r7kC-IvUK)KVr(kL>H5PKlAaq`A5vpXY=m|K0Y`9h`D^Oefge` z&()Kd%jepc@A&v!J&Cz|q9f9j$Jc#)uAaomS17G#AU*NR**RXekq>Q$#lj}6K+L4G zixmoQW%{IK#tHh;LQ^-yg__)qREdW(V;7k$l~Z zRn7sQzfFAwd?AEqF}Excqb?S6%lr#IKDR6p^Yhs<|BR2%Elb3@i~C#?2e(|m1wQUY z>SBT;{fV)BTFfoi2Y_)eQWvv&66>y9pOw>v`y_hIZZ+&A@Zqo+?WdJ_60sh6OsClp zdRHfO;)6W{FOOq=e6B4x5*XCTh3DoUG4fko+%y~Dq|Z-4#aHy zh`I4&c@bS9tEVr#|F6Bfjf&zr12{h5&g>OYmxwJYP1gpMDA}Tth#s06#g`~r(rQCJ zwh>$!G%6fekFParG!~UaRN7KPTau7U%(hhzO^vm!wwzP6XsE?V?3!4m29>nigcvoX z>Hpc?k#RMo-`WqElV9%a-se8|&YhXdtR$;-oKk1)&w8DG#CfnDpLLv47un7n%Qb2D zG2@gv8D~%T*n`q(#5O8C&Ys%Mpk3rWwkCY+W}WrerB1pr>#WDVJffZT*rhJAoq6nq z(vIUZb6U@l)XA}%b;0w)d6I2$M1R(CN}a@*?X1_5JEEO+oKk0P7aU`_zi&x9%UG=A zlsfA;qqXkmf`=n>TI#YR+F74_vZTM8j$x=q)8IBOqR#rG$thjD>&X5N>Q0(vG<{>oiMUxzw?lb>7?5^>pmB=!}1E z>hKwI%AZS_b;0{VV%Vhalh%o(m4=#+J+Q4ZR0jNO47GNhp%T{{st66peuDQAzrj$g zsNQI(1y33(X_KMmlp3lG4d_DJWW+E5<&(1!FMFIev5? z={a(u0!^?z&z!>pABt+32XrCr1?Ca8@FV`G^ns0Ng=3eYro)T<2q3wR^MXn=L%qnn zU?tk&+|9h84e2k@53+sa{u%R(8gyd%&zTPdko*gBq60~L7(Xh|gq*#GDu=d@`K+fc zs(;CN5J2+Fv_&PFp?<}9uo8RF4(ERIpd5|RUg0=@&2hqUkaL6m2q5z}^F) z@}e0@r^$;Z*#64#!UG@5{NzO!($0_@weTbL4bCYXZ*q(XV8K~(V&dO8KG@E2eDFa# z&%B`yUC3@D7p@}f@8m)!re7e>Tbv6tL$#9+E3pT*iyZSM#&enRpca0_cQ7Vop#U4v zij=n*A1ePr`+ss>z!~5g{TK6w(s!7T_vjOqXok8%%=`3nm42>~_c}Sz3daZJ!+r#i z+(lbdq8SrEBgYcVl>0{QKV3l7|a&m#_We`5>?&=5T`fQbI#CyIR~{TaVLhTy^M5i_=vOGGcU9&bD_np?s!m+jiJ;$yY7s~%EWi`sk?--`5#(NmsD8?~DR|)s&DrK~;oRmK5P7?QO zIJT2MZx@>#j(tBPlt1xHtWD@3zn8k&DY`mzzpmORkpHXXMlveW>9-)?IXmC8Vv#%F z`9MiY{?fc9`Nhsu*Z6V#x#|={4aX3~;k`^lU4ZN#qdXkmucNFE@5{U|r2Y|PaDH;= zCubgWH&<8bxhQ1*3m6Nf_iOA=3yt|WaLlrJGc`=FbD%N z0R0e)-mt@lD11on>$rk<5y0EHhzmG}H{r+YcnvK$fmhLlqi94dX1@N3uSc>xisHG3WzXi)77`bxPKf&)~C=bxGEq1PsEFEY2Yg zU>|&V9#zr?BL>m*xzY+y_WqVd;?kdGNj!w$~ef_&9>KObFV^T z-=LJZKT_7=h4AZblnWs3q<#|nBf@pMW&bkAa~`K~400YM{$=)kko_H$60-@`m?h!& z7eu`O5U(d84a1RuK498{TZ5nV@C^6oIo8S1W5%Z4d*8V9@efRzoH=Ex1UN3}suFYF z;vT%j{fFAi+}9DC`I*Tq-GjQ<_ZgdQY91D2HMXD%yKw+VaT=F!9Wh&MYA{A(0%l+y z7GpKGpbEQj07r2emv9|1TWODxn1C6Whs9WpEvUk7Sbv~RuCsQp zP08~>+mkjW_pJK~`k*{RW4UML-Z$@Yxwj7{*n|J$wfr7f?tfVm3gpK)f|kyalYi*NgeG%ZINSwOBcd2VQ79g^>~k~PEJq)s;ZoFZ$K#L0TqPPvv!S&w9spOHd7 zs}klWxX>ub9X#%$n%TD$-36ShbLLrq-`7| zpR8|_V8+Qh*h!qMj}j;KX538nCAX}zvJR)v$htmCoNN!lj7uXfjX19iBD_hQ_&UtE zde-}T4!(4`yc62YeDir}#>u*$v0naazwXV9%L~UzSDD0R61U-zTjLgoO}Fx;3uI66fRRhObmUZgp>FzbhZoPe+ UTszXIxn(>Rt<{(>D9wET0h#s^00000 diff --git a/board/MAI/bios_emulator/scitech/bin-linux/libc/ndisasm b/board/MAI/bios_emulator/scitech/bin-linux/libc/ndisasm deleted file mode 100755 index 9fe81a3a3e9c01568eb6ca707c052e726e74dc7b..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 66888 zcmeFad3aPs-UVE@(}4y89UvemYO^WGB0)gHX2Pz527`d(0$J%`Hj-`@hb7Q7(6rIa zylyitqvJ9ezA^A3-YrrEyx*EkYD6qGPtaGaIz46nGbXa=u105KVY`muO5nU;oMQhFT&ZQ z;yeumTC21h=Zk?0fB`^1fX5}kg}`|L>u(SA2HFDM0JcLv2I&bE?+_!8S%U%gvvsiT z`f)B2=L20-W*?nIyg!hj^3K7zjf(fgS&jqFT~!|Yv=h)vrFlxy;(C<*$}wSHNAW|H z<;G}f_Q`>D7XT#^B63z;s7=JQ?RgEZ~3{O^I8NaG~=)i^%}`&N1#B7Kmy^mihC z0{(NXsmIh5Q}=QSYlHNY zT7M=XeL~~UMLI|Grzg@!z+b8C^+Wn)t^5$AXQF&Ac=|H}={4Zzsq`46t?~9?yeA?( z5#@0SOMkCKItS%B59t5()Poc0q9&Y@>)*mMmgXRg-i$FSj_44rJz7j^-D^PhW09 zfyi52n(xb{vt_wHfikAIC4L`#F3ZimRamVr$jM&>$Jlz+Npm5|EAeM9MmElKvx|#- zrNsqeuIjj4^cVUvHz(7Vi6U8LW$2{LQf3w9$nlHE0?z9`9t#<-w|Gnr&f9ogXq*r6 zSnxOx;<*4}JmayjPsO^_8jJTdp0Qx2^Nf+6$ukzRIXq(ly@_Ys6z1`aMKgzIEcjlY zv6vU|j0LuYXWU?XJY(To!ZRlMGM=#*m-E~e^OfhGLagT*H;CJL#v)wFGj2|I@r;H4 zKAu|(@c_@bpdaQL3*BQpd(b|fadUZwXI$Vf@QfSF%RJ*|6PceP#8x4q!&8wH?K=@6 z=W(axdYFD#rrASYcp&O3 zWtu(Z<Jnv|J?$-FTF5ke+`EM7W4|DyFMHlw&h%lK<_LJ#GhHjw90_kF(^WFf z5%J!~^b0c0k?}sv^usdE5%NCCbfrvlq`WUMT`tocG4Cd(OJtfO=dEITo=kHDy*rpr zmuZfqx0dNtndXRk_b@#K=^H{{g$@UfG=|99VU<9HQB?GQu~z!v2Kt zh|tEDQB_Uw1%z~}CirA?jD2V3J%CuEWbbRvyGz9)gK!C7?Orn^PKb()Zz4Ce@pgs{ zfk_EYR??w7Wsp1AfF-|tsUh5Jjv|&;o`Tpq+gsvZsqx!a~272{5Gen{@co$Ap5{0%U_7{Y>BT`#SEjqbLG{(_EuB7);mKD z$-9HQ-D_T9+iKq$1^sL28WDQu%#-5y6aJ2-DRyVwTIM%|K7DJfRmv>WzNNbQ+{&mN zBX26om=4|u2Lsy^>aPkl{O^8@W9#IITo>8kL484vTwuE^u$hA;+`)k;@me9Q*G)o) z{9kOggDi@yh?*$9*Vh`S=Z1+>o4wx~Ux~Q8ybCA7k>r z+xt68FBo`T=-?uuKP|?lpfxfp=PqDORNmWu?#9I);6VYBS7G9W8p0bXd29c6%p`QYkaNVnrZ22{KSyR%@{z}(2n8!m4}(?iUw!I48JQCL!jys*tW z(<3w;*q#)lQEAu$H8-k$WvC&#k!zvZt>rq)pc0KR>(`x_{@-9hQ3HSz35yT4m4iqzOxi= z1U9q%xH;q^Q8DRoN=@mg3V&5-;~Hd#PKEaMZ^D|p!3fKY^{vt-o77c-rl>y>Y8()h zL$fU`hs&~d=M<;|o8|4x-_`7-$X5*<4kxaaHT^)Z+HB1eUprM|6?!+hs^W1U=o@dD zyK@`vp}c!8PYC-Hqkfn7+_y0XH^NTx{`&41$H3{J-wROFtJo`xFa{a#=m&||*~PA?F%BM-^SoW?N>Z!Z~7z@(ZGZ17zH|3k-D{X)s2 z_&207V}Vf-&e|Gw;G8(g}?PCu3kI0o!shR(zS`V#hu$KPi}RZX)K^-+L73YJYSMX-bn1lG`mfv z9cG#@c9dT7*odffQlbmx`9eqX!X*r(`H-sgE~YWLnKoT?B)S~_9=L21D$;%lG#c)8 zJ3)t?6+RK~+PMvVL%&^4f47RXGs(MAVsYzml4L`*iZ_HuV8i3An5k*3ykRYQPAe~| zB@ecRPxb|Tr;WQ>IA>yFqRe~wtUQm*`?w_!4jVG>L~~y4Q?5jh@U>2^l0L$2lA+q8 z#>g2QhMcf7_(0T&hRS&pIO*d5>D&t!4^e0*S!##6)+H?-6RIxG-^|HB%DIQzG(2ps}@k9k=4x-W|Ei=|aCc z?{>Pn0Rw?lU?wmRC;*lKsH`TrHDo05QMMNvPy(kzF4TXVSy zs+`PI9ciFzi@v^Xi~T@jE59e$;O}A5Y)W8xQlhVQO`4ONxGkL2fnN+? zqWg{;c_;bB;p<-aEMgF#hg|M0qeDwQb$><lNSG;``>%G|Luct2rvei3M>L<0`q_Zz;uikPyJ-mZ(a!Xqs)8{4v!VTdTfn<$h&% z==w8^#s$7?jhQmxEe?2i`k9Zuh3U}J#6T0qp3gtgK6f96<7l(E*Xc?Cx&eKFA;1`5 zDlij}J|)PuU1#=>Y};frpT3}-bTUD8DHjWBMuIekwm*(g)K|7k#Mj zg~^p9d(<>2o#&pwv`POtz0P0R8f$dB`dO8nVHeh4!?|64ZI9IYiDucBxmKUdIgYgF zta;XEYxA5-G~*jE{koaa(4LCiWAetqwL5S$NnZa6p_|XtOlpJ+qGr+wp6Y_}avm>t zxnH>=wESpvk}K3WHPGl-+&47oXrM9bJ0JI&4P7_HO_&_=yGCwx2j7DtI{jz>h5cV4 zbox2*Cj=VL@%35R7IWR#vF=Hf!4|-GVckQ@evg_d16d*FsJ}*M0jRA+1PjowC(^=Q>2g{$mx+Mb(F${ojQ@p_wBGmQNd*>O`yD{&wi_ zHQ4meWjPE))d`MC*9vDU%3}#ahlG|5nK+?*+K|+8S>PB8bW{aiX)Yi+4CHTe5pow; zx^^@?4Tj-!^_Q+TyJSKdIl_Y1pkS!F`U@v`>2wNo((qv#zPutKRhfkcGm~|*Rzey?qS+wg(!w5EXzrZLr16pLoRO)9 zEKth=msBLBR(}c4+p)m3QO#9U%S3qMsMG|b&(9&8rRY71O7#ZE@=P|kcT0n9{*_Nl zPIc6`<2Aj!M<6F9^=HhIiZzRJur6RIk!gBq_KP#*8)TqjwoI~$cH*r>I*jlr;K(iLl zSB`A!Aao?IFSB+yMyDM0iJ=CS!`>U2`ZJaXI?5XbZXY$lkr*n(aVJX*RrEt5 zRM7`vO>meZYJvlsV|;aN7IuXydLR*=?%L3CeXX;@7-O-UyNkP7BrP=ERez+s>6qVb zs*gd0yHI^?dDCFudF4$bd|k_%#`!vyH(lgQfc$|m*vsE1y+D^5)CU^J`L0}fPM~qH zuh&YXF7jPn|A)#z;|O2x`Vh`JzN-U`xxQI-OHm=-AJE+&@W@k_-;(w-eM3w7U8b*W zNk7AMN=y0?ru(;~A7Z*Y)8$Qh{&QX%0uKkUpV&iaPu4ngw@|xgHRO6@#a+k@8fi6auVDCRL9PbJR z#~?c}63^cJ7_wqBuQZJJY+TaOjnb`+(g8e6R)vk{gn+9N2fY{9m5k}aGk7uN~C&(@0$9a*dHsy;h8VELbasu^x}7& z+{%yhF)b|`I#77pX>D3MFX|gTFg+6dfzQD%ykKc-dVtzQVB3(%mJmLy3Z z@4Slf-{2W>QRh`n1JKjHb``5X#-Pc^#!WxGk5^e^H${0GQ5oIHfr%9U$QMt;Hm<>A zn78K#*lSKoF!rQJ&i@u;#ig_koj@NpeFR;)SF{vq`o=7h5ZElQCtnwD>lXHaVqM7% zDH~^^sued@hSzMI$fh=?`TDKw!0VwS)@WZ+{pEOH**M;JUj5)oZ+qCN?^@~Y#B+yA z?>RiTs`U0~v0ZN2o@|<4`9#ZjhefC%#ksK(?QyR;2enPcHfPcI3@&Q!ED;?RoYRCB zU({lBfYqFupa(Lv8g~fSfM5?K3^~(UDv^_FI5%(=oUWmYZU~d{GHya(vlQc*z5&m~ z(-Yotx;*t=(SK%qV13)>_^7ayHB5A;8otrtNl9_Cmbi)Ti6Mab4u6}zbcN}_@@~SH zv_P1usLwqyk^>Jg@tT{3`Pt%p!*++SRaCacoV4v*>T~*TYBqxjy!~IetfVujXrN^d zmK!F%(8j>H_HXGX=hx<_qgFOL3;{Y*evZM;tZU+vxqSU1JmmuGKl`9v@`Sn{K%ngn z+i~Oi3p)2n!#Bk{sKxNpN6s=_zRaB}mS@5K#9-C(jwko94@_f&Ce&YrXARmNFrog6 zP{WfBpUZn0Ox5?QeA0<{3gcZXpG-wOmGQQfYpRxa@lI~3Zp_)$u|K`jLD!|2e&XU! zohSUh=6;$Op6TuvX!7_v%1bEFgqI_mWTo+&SYNuCy;@QZ@xCH_FK-F?YntGeYa4bBo3i)<9L!aUm%8Jy`^fT};^kemR7aBi?KC6xz;hWEdla8k(onF)$!v9v{H3WKZ7;#On8PX zZbm}N^)C17k2v-{s>8l&Cvrnc)!`Wlp_$dr&<(E8!i1@h(uVo6Y&fIxQ@)fR+;`pq z9iL~ept&B^DLqat8d{NVr2M$DRmx4(u0?&#d}%l76z$GD<&=hdoC^66t*IXi{Zu0~ zy)mUdO)ncqNz$p5nboecp<9?2fk2AR6-@#jhxv`+rBPG;p@3x;S;J3>DNV8 zLWG65zFnvxJ<>@goS|*MX~CSUSj<|bM}{4YMwQLk{DQ=gs?eb`uhG*Vp9}3cS(_f& zdH^2blVoQw>hE~AN2oJnb|j4j8Y^-eZ!|wE;s-AY6_bth$T~8rF~641LVGhJFQLpk z&I|BFMGLnmUtnXpD|~YTK2!Gf3J>SEr}&)-!@Z?*IO(30q_zImX%j&D>lw5y$5%e$ z@rc%|(!HfkxC@KBx5R~=t5cjCmbv6bh&`Md09gzAfG_({2`;Fc6NCF#T+F&I4v*F9 z>KabEHzjGEKOt@M)hH3qy1ro$kB3knhscRadunyI`i(lxkEhIaB5*W8zGrl)my8(4 z8qN>y_uN}VxC_7g*D!Is;qfI@PCz?k-2YSP(1v#Ptzcuy2Df|5u191sXS&P(@A6Z9 zeBYIi9^&u5A;TzdTH=c@Z<^yzcnu2#9t0fqv+@0g(S7{wWX6R0sj#tOcC@@{Dhqm5 z{RlT8edDEpUF2m#LJ7Zcc8c^OeZv`5>HBj|b zeY^6e)D>tI5<63NEO*zR2VZ2eHf6`M4zi1Q5uv-YD^vVu7PnTfBtq}HpZ^pu<0qXM zGjBy(+<7W|iBHvcuPk4FB9-Y$Cy=qT9`(pr?F70NT!8t_mj?Jy9G_=?!WFn2`!4H3 zJ64e!kyoi)^Eg!zYUJ{apNZ-?*HkXIFWLEQ9`KU>hjTpeMu?D7dLE(8#CC~b`4e%_N%{X zc19!vwy`c?&pD?23gL6l_8K2z5yM72DY~mZ!8@)c^~g%ZL#-YO@HE-EA$}bq>nFSF z+k_fmsqQm+X?LX@J2@Wp zLn^&4Tm+GaR9VDT*<~mjx&Y;P7p;%4tj=?`z1n{&grT?AhXo?C7V|{je>nwQfpNm$ zZdPP7jMewU7*yQi!gtQFj=_&~_01Z(GLF9LNdIa7p5TlBCeFlnDtdro)xtEWR~7!5K%p%lm}6?*;%Nvw z36%Mr2ah|~CH3DL>KaaS;eAb-OBo66sdwOuFXjSZuCc10mt&j2e#Tc*uEG1dDXe-@ z7_XzzLm#CaM;{+YAD?gbZu$%iN94wj%x;{1#@K7j?a}`rw4I54R8!NRw z!1`eB3&P8jcr9ShI)N3n3#WFAo6sX=Qo@Qh8Ice9LJgNq2Hs9_tQ{d)XbNWC_-=9I zlTd8=ci}Sb4hKx`7L57^Rfca#>c7pL32~D>8Ti2BOyteo(!KtNF#h2YnDwoatFXcQ zSlgfe-~74a|Fb`GHV*v1_+x!PV|hYGqy}F!L_bvc&s5IJh;)=*u(vv42|BX?o6mFQ z03_Cbq4#mL{Tdgx>s=T=vJ63VSY_nsiRL|UU@RH2qC@0EF6d@z<&SbMsfG3Cgo+6; ze>Fs*nv7YqBR}lo4tBJ7q#ROyyDOeHmR%6fFB3h=%<99A^yqL_7fFTeQN}bMLSrhU zQo~(z%l&TE(H=0sTDz==z`ey0Zf|Z4)37z{hwsqdeUz){r;|g&S->n74l>idCDmw{ zh;sgY;r1jqbX>FB-wFE|^9G5RyNj`x;huVH_;NnKOu6-8 z!`m+ZyGVQvAGek_t?+FQOI`mx=^2r0U;q~c9_(i&gmzUtDCFIl-%$0PBcCI}UHIke z4bIi;<0kNH+5UR$ZUUR7@9rQUOBamw`tTJYQ=1V<$Hq-rbn*_ods&z9SoLaJ@#C>g z4C*ez)}zvUHKJaxBOZ@7Jxt9ctlmn~u}1KZnKm(~YvAYYHPUJJSLnfG@cNCrTBA~2 z*PTP34XLu8#7^!CeQ?dJ>!KT3BvOL8$uB6v3;$K&(JjS7@1EQpmSrktcEvX&*^l^~ z<6)R&Urcr`xWM}i64ymmaqzc>X35>eZg<5bzRKO^j7mvhGldTK+QsO$1?{})7!<1? zrb;0em*zHg4{RNWM2&EY<9@uK zIQZ7lJ@~FKQs#Gk{axgyzcULmsH*{mIe+l2WA<{K)JZJIpzbfSoD}l{+{B=612QWc zwz>RQR4g>i%LU)4?&I$fsCI7C`)U@it<}s+7k4rq%(0{L45kAgt z!-Cr?f@e@KuBq|(n8~^VBLBc1IIx+F@Fmu?;%<8rgSwuu!mdnB;GC`z{4?H74C-1- z`{hj+`_Ngv+(AAOuHU6y_i~Ej?G`(T4f_pNac%(w_}p#xbb7gnG;MG5)^gw;5yn7Y4TC;ZBY>jkaNF z26bl;z^+yPQd#~|y*#IMJCHVgNQV zs4FG&^5bILZ_n}! z>Yh2f{6+qr=>LoS=bhdE{3_-q2K@fF)%Ul^vbX4E**Be7mO*_+OW9@qWY}HiA8@wa zjx5Wd{$iA+x_OPS?;@`|_bd1wLPDskIoU(C6_4-1jMUx(*2e{^T=)>$mk?Ou6uuwB ziCEgr_f~i>5WwBd+5@8;NnZz9@P}1RD}_j1@uhmtZ0?)!y@3BW_E_%`vtE8-_Wx>Q z`HHb{%#ZJ$DBqQhz{r(;H~y$ewx`y#i_loy;p{e=bt%XBOoL|ty3(OCFmf5bpdbzS zj|WCBci&YdUtz@Xt(CH`7gDxj_5t44?c7GUPli*Smc8rQUt3*a2RGY+#+AMw1Gixm zjs`}p@XPnOioUjHh3~GN-4Ts$6~bSZIX`!lrzj`CEVHc8 zbK{`Qn-SzQ@G>Z6;AfEK$;$VYF;?s;F3q2xU&MHsr)+6a_Ta&TZ*J>3`?zsXt|x1$ zFIP%#^~k@G9jG$$@(XfVeo!V%c?RWsGP8a8i}07oWu8pGuh`QMe`}1tGhz!B?XyF%RD}BJ_7tnuOv!!BGAS>{$x=Az>KoH82AEGx?`%)-w<%(qGMN{b6UCBhRoZLm3g_tNMx!L)7`MEi5#UN3dC41aol$lk4!nlU;XYQVPeakK$<>^a1Lq-z9l7tx$0 z0HWDAXAz(>mk4C%l!+Ypk^^6I;6qO7P#_r?B611@G&x=YRd$)khMU|2$6{pcCvs>l*=rDAvj%@>CF?RWrc#jYrx+SD9!a1F+i^T zT>==uwai~AC|k%Nhe4Jo&GD6GBP=Oo$i|gs69uA#olxR0^X4r!PdVmEhM8s_eh`5r zGG&OMs3iN=g2l{~v7CigEQ{rt=WS-a&8(L!`pgXd@RTV(yyICV%ks@^m5VySu|#PB ziP8epg^>BB^bR581(Ge0Yynv|sM;W=}@40CeW+`>%!umowW(Y}1x#P3VY_aQCMC?L;fe(pju zKX;*-pSuwGnTv867UdMl5CII!P<9qlva@hzXYs_^c&01|^Ohmw*|$PrM#@?uFjnmM zLCY{lhFJ^+I;*JI2b74S-1!2{6PV<;En!$@hKpr9M}}Dp7c!7(QGjcp09SoMS%D}h zE-txEhDGX>D^q5OD1B#`Bf~6&nK}3|jiDn)SW!{HD+Z&;pAcbyb)taRM*&ug0xS~+ zx#%f|q5#W60j`e%UKR`Ra~=z@blfHuFu*+xozE~wh5{FJLCJickWu6-W^fsUWClZI zh#2Zdz#{0@{Gx0u0z3gCpFNY$-}lJR=Gv6c1;bn56M0JuhAt^dHqRn&iLVsf51g^^ zK**xW|WWJfi?~LHG&BJUj1;LXH%{ZbQH-t?4@KYl^;Ri(!0t@k5 zA$etRvY0C>9K|n^_)1VMR*`~SoY-G^rC6t6v=lqDB9t%jWujn7X)ab{c|wREAVFS{ zSs6~UBAi)Mk!gjKB(F&R`b%C>E`I$bk2^h{vI}yTh&*%=3b3Q{3UY2^Py(_br=V!4 zJk2*xL*W53hr+Ld99d044r?jMfj78-^YYCu;E4$~93cY!?hL|gGfP&KF9jGEG*1ps zUOxL937in(st|edmu2##$1Dlf6d*L?%wR)ua!uQ^H`TbA<`8n!c#2qclsG&16E|4gS+dIVL{_mMKV6eq zT7vs5BXBP>CtGB~zf4>YnOK1{;U}gkJ}YEziQ7aO)?@r+k0=qv0*gmcnJB_~ggB;f zQGqC$kJEfCPy!btJGUrH6lLOsWdN&z06kxz)dEzO0Ffzh?ycZ>%mV(f(NfferwEjoC-;f4jGr*_EY2?|;D(<0MR;l(jQopZh`pJt#e-*? z+#){4jPm?P1C}Y?RWk87mg{MLIzdgPnVECVUscLTOM?qOugB}3pXdz5m^O{&(~F-_7TLH=o?X{&(~F-_7U$UpAlI5DK|1#O~7ELz}m0)7*8?W zU1D#FO)a*K=9W`#Lh;vdg?P-x=JhrP*b6hvWhet~UAc#q`&#a3xwXY!dOqG;`9ziB z-cwmF_LTG!yAdrPCU#ZhoH|w1s`IWYW7XQ8qL!!bC||y|qu6B(M~*SPyD)|!Rb>R$ zwr2^RpubG25mp;Rr;<)iBa5)g7?LK8&zQGP<{_*y)}~RlPO1=A8*8C*Rf<|*R~wvx zT~!WuH6`+duqsVB+(Upi!nmL9a0g|$2DTjT&NL=Z2s_aUhr6RG#|eo<)LCVmEbmFr zPL{J}4dravQ^+x%Ld%|%Eeld)AgnUhNXe?8l&lKM&InR6h>}5&3^Y3Q}& zfr`=Ea$&sNO&I?a##WrRiNmNr8Mq7>D*XtU76Z~^Kw3l=Ey~2M04*X178$LT1*=z^ zs?}1pTB?vml}zkfO%-yWVzhQO>iajkQ--z10~mk@aLqq}F_?$=Jj8kSdXRzNH#HU{ z;77y_cWc^@uBBmwyIkqGD$`*qQ<_5PaA(OVLWg^vj3RWn^JNsF!@WR85jx!XWm9;7 z(BVEMqX-@Dy)uf>;oc*o2p#S^8Aa%DUoWEw9qx#XB6PT$WE7#p-6*379qxr_w8Oni zW*~I9%Vfq!G6SK*T`Dtn%M65&VEQ`TU&suEC?PYxlo<$7Vl7MjATtocsLVJnGY~=| zGk%mA2p#Tv8AVuYJcy2c5FPv=;+cqNBA$uPjTcUK@11hyAl&7egYKQfE}A3NzmwsO zGQ5dKKao*{4)@nGiqPS{Sw;~$+&9Q5LWlc08Aa%D|0JVkc#DkBWOlBMB6PU(WE7#p zogX_kI~g=y3lmqX-@D&t(*$!+k(T z5jx!8%P2yJdxnf6bhwYoC_;z(7a2w9aG#M;gbw$78Aa%DXUix;hx=9;MObSTqo0d~ zQH0aKk^HwX{)OnbNr)pbzDZ)wuUdsQh$p!!t>UWG9yvyPtV#*ysnOChr3ud8==F!LgpfLxQk>iLby<4-so!NjqV-Z z=vHh4BnLjR#uGd(>K44~7c& zE3>wZrhS~4hqV=TzHH{<1kblK!O+;rWQ9y3MEq?TM@W&w6yaq2g{_Rr5l6UN#+f7U z$OxH(8@BOX&u(z^yYAhvIDB_L!@6O@sP6~rtA1c)@F7wkg8EQ8xDHLh&+UC6jQ51` zgD~Fb>@Gx+LSYohYURoj<&EeUE-$GV@>KBOqulqxIEv`kxM?sjj^Ku3uOFGLF{ePwmCity4R&1M;Vy%M(*K!f&w0enffchGGHj2%D#w|QmkSp~(vfO_D2;3!ZBd`FvX*xn#gX!TxK z6;k`z6Q7qepTR*U_c1ugvileuq9=#g==}^1v5oszi@5vg)!vgx9c0b>7#yPX5H0PO z<|y6A;2_(ykHJA2*~j1@E$w4)kcIb^3v_c84Pz({x{k4ljcg)<14yEYG_?oaeUN#3 z+OP=A9Y7K+&F@)D1L&u{4M0>l4(?^iJuJx~Jiwaw1O%oIgomi!&)9ymzFL;!P#&OP zd$36Fqjn#(D96Bzq1X4b>-V>TVm}m!RWXKO9|vY1*?na9k=;jjpV_)E;n-nVKSX~I ztzm0G?qP{Nj2%D#2iPZj%2Ae$Ific&8aujipRrh8M{?73k`@}U^TH}2*GPo8m{;Lq z#zhAhmkQ%zT(kG#TKyBWf5kL(*MP_AZ(L913E>l5XdUiOjxleD>&zP>PFN2{^U7yfZH$sve+tbT2&;^dc+|t} zcefHolQ7N*qY>8r1Y`Hf*2o)WbhTXn7IEOuf{zK%1~FPSV(l9kU0VCCb3!~KTI;v`vY{G=9VrXMv~oOT&* zj5k-i&E{%{6H{-RDV)$9S+YA2RvFneXslY(ll`%3jqJ}g?9aZ)G5VrE`1l1v{-Ih#0eJTq(y|)2JS{M zU`UGytK6o+)uzGK(#6$uu?r1$fx#rx;A+z#PB7S68bnxabdm<;bG5<8Y6DNz#udW& zI7v7@ZYzvWaQ+16%Q3a_qXGDh{T}#bnC?JVpfivNvfHQA9U5&sAfWHRy zFQ6WX0AB-N0G|VUflq*4!27_vKn<`Bcnf#~coldFcpl&{MLh{T20Q}rm!bX)+ynd( zxC7V#tOZsBD}dhvO91`~)k2^U$Om$POyFkV2H<*N1~47C5|{*}0T19uJMIJS0xE&q zf%U)|U?s2=@B<5hTLCYS1Iz<%0%ijlz_q~Dz!YEtFb)_6i~xoJmjHc$9zaK+HDCZg zzlXjAP5{S%?}6`tZ-6g>L%;!GFYqz&0q`!c9e4|P9e5dd9(W3P40s5*7q}Bx50nFo zfns1jFb}v9xE{C$mctu+5;}Y0i4;&Ehs(?3uSAge$M}Y@{dx1Xyw*zZ|mB1396et1~0C_+ba5FFm zxDJ>GOa@YcQNRdbC@>hf1h^RJ4V(|019SvjKy-)G)c_m=z5~7j_5&XS?*ZF^Ex>EQ zOTe?hlAPt_#XHc_yX7ud;)w3>;$#}n}Jt==YYQfe*x|V{s624mIGx#J}?)!9!LkS0ww@s zfDyo@KtG^2a3OFW&;@Vs84Zuv`THq>R5-<)J30wvY z2KocNfeV2ruwFd|JPcfozipTXOb32Ox(R3megcjI{AIU)14n`HfNy~#z+vEXU@!0~ zz@Kod1>OU80&fFbfwzD+f!BanfsMe6!1KVfz|#PKeVD&G>;d>I!@YqXKri4z0DoL0 z+yH+*9e-^m|6M))6u@ABzjW;Y+5nvZ{B;`tC`|CT81QHBc=sbjPoM)Z1i-%)Ao>7( z0qejQrRC8MA^)_AKeMhMosr<*apRw6YW_Fs$e#nqze{IA9Vs}E0!9O40R9b5GB6al z3>XFs2SxzAV~+$b0xkyn0sVnXfC0cjfWNZDI#@s3!gjEaShwXj`wIWelk6Y%CEL!v zVEfrmf2zeg4g3#K2~+?ZfOWtcU=^?&SPJ-og+LK-E8qokfh^z_;CH|*;5y(M;3{AW zFcC-v#sDLMVZabzAkZJ^3-kmo0L}x>0XhS2pdHW}hy$Yd34qf;Bk&XOBk(WaJK!7O zOW+`|5BL<=4SWE+3%mnt1-1a)@rQ(6fQ~?WpbZcY7{Hm&u+9NL0{;Rcz}LVRz~{hT z;A5Z`cn{bCYzL}F~H?OGB6Oh2w(q4GQbZM1708-xEZ(}xE8nym&0k;5i zfEmCvU^0*fj0T1SgMt1)Z=eT|1hfa@0Rf!;80#GHJ@7T~1#kfP6xap42kZpi2DSjN z0WSm315X2w0}liD1NQ)b05$+YU?s2=@Bu}@0w5R21a1ay05X7UfvbVZz<6LRFcP>7 z7yx*HbAcqF1JDMD1I~Pez6Jgb)C1oFUjc`JeZVKchrmu?8?YI86?h4F9(Wq~8}JzL zFz{#KF5nIz2rL82fI?tCFb|jm%mA(g(ty#x2w(_s3D65T7w81E1sp)rZd_|X9qj=m0uBNDflq;5zfy%_KV zr9cT#1QY=Iz-0gM4sfDynjU?^}YFc7!|=m)$A zJOexlJPJGn+yhhs8-R7dDqtB90geENfc?N{z(>Fbzz$$5uo-w2z^(9qJ#MHo%W)53 zKd#p}$$MH#%upQnBKBjt#@TgODvo;``!QK@yzfi9sUBhA=Yx5qfuk*pW4_L@jKvA) z97;FZrenU&*>z5(8%`aZv}`h8=eS9;IOzxK_s zf&Y0pY&!aBai=3^*XPu@6XZ0T9Crg!9(J2@PIx3G>^8|c6=&JxzS=$qk11a)P9Ixx zv~F>-J~fxVv+4A)C1=-J^Xv$9XrEaILjuVW$bhCA?1t3>0?Wd)-6uf zr{>^&Hl04U9Ly!B`Kiyrxi%gB#p!)bjy5e$j-R^T6Ky)(7jnAJAw13V z%w^;Bc_tLc_eFL;Pkn2Sk;UnLl4E@qr~CP%O{e=wPS@#verMx!KfhEQ-yPZg+^_1h zINeWjtk2?fKR>qVbU(@II^ECrY@F`rcE#~spWV;Rsy>U;{UpcwEKc|H6`M}?lbo*8 z{d~^G>3%+;IKE%w+~st!jz`Ghu((u@#R#EuvVFb4DgJ&b=mqd6MV>Lb@n;{rCWkH#(6>Z2}I;}+X=<27!fjhm=(x7uuS+^xf| z#{*q_!|OttCsYm=N^ zXN}W%>Tum!HuY(lyL-%Fiq}k<_njlC#zx%O*dIu^+#DV~ztq>#-kAI%{5kY18TRg&cMK49D*00qXj+aJrx5_`#K~lXDw( zKC$U^Kgrp3mY*Nkbh@A9sN?5y2Ecx?jveIC27WeYKej8*V<(WVB8Q`A4DL;G7~5Vk zxYv}fcMR?o#a#rBep-FPqA%JwtKHid6UD@R4f%aoPxuE$up`1$|lpt^f$iWGIen?-ed`4HP`p8Kg zJKY1|u(-iy@~m(Ey?y^A2ZI);x9=Sr*HWzz)f#87?@h&xhroVpQrrYP zf%MDdKunCmy`XfHVsK9@4&5gEMQ`5|HcoHfBQ_4==5csH<7E42TCH_Drv%Nqd+j>y zdjF&1rod0T%?gdP+qAf;G1|9Y=`2ofU%{ajt_ETEC0B9N6sM2-JR9do^)#ElQE}5_=w{hCT{lB<*Tm3GvvIm^ zisG(~p&M`Gblq6RrN_{Xv~jxbGR4h^p&M-DbX|WNr_ZH6in}g`%?oXuZu4BlWk6>? zx+-p_oj|&y;;u)W?i zAGUE2%kE(n_iLPet$A9AI%Yf8D_x!~pUE|f zn;(NKSDZHnw@h*QF}Nj)TL4ZrI@Qx$s!VaW#^8#;ah?^#;PREOFb0>SbQUMy>7X2s zdDM*;qR33172c$57N3=CCgv!vBnCH=9QH2@V{qw8R~mzxrnoY2_I{b7IA07dO>zDh zHpeP%Q4B7H9NNA(1~;4>+OQ-Bm#ny@F}OjhzT3dD4f=ZB&&KK3QEwZk zIe45pjKfN$)BXIHvT1R;pLI449WJL0%!nfz=U@hhL+x92P6?WIhwM6S?b)Zea%qev zTk88nkLad^e_E8Sz{@Q_2!uKSDP*2d8NS>x=wyA`)C zhOUwv{3K`Bg%!6Roc&m*xR9MdIzTQJ|M*c1Zl%WA`|LK2lfG#4`d6IRpMIqa$Ea_i z;%<+@6)LVG2A8k6J7REoo%Jk(oA5e;;|Hjnm&pUQaGgh(E@#nXYser`x>B z#_2XEYBt%Q@*Qrf2QmEp1UP=CL7Nt5z2hZk`9e;<-&ML1Hl6-%o1CSC>E`+j58iE3 z2V<(FvWC@9d!K_ZvD9gR}gk&7PW{tk3e(;&eYP9c`Zb8#+5@^%?E)NP^C4 zgT+z9ql4B4a;(qrAcDh1oi+~A7muWbL;3PQNK&VNmi5b*(BZH+{j;o7HctO6>jXK} zXX$9uk=Tc(#1A$dZCc#-HjXweu1?v!3pNbEnn$$xwbEIfY##|6U)Xf|b#%a{)93uB zHcp@OwaVr_W))|J?~{Xr_nwt&CUz>_eKEMVmF`dA*gk7q8LcLV<9-IVV+*-fLOfv0 zXYviDdoTvKNpTOw;9e%@6yh)7q%WzS=2Fio?&0Q~mdM|g%|}|YnqyCp!<_hQb52X- zuS)kQvSfXp7VbgCJr;wzPuYB2apjusE~T?Lp>cQGxYXa^csxsOSR!|$d%)VHPWi{T5$Xx zpw3zCAjj`ySe$Hws&lGMN6u;^IqIH_QQvrSI4n-LIYx0$#n6qgak_4Z;{HyN@sDp&7O*TCWh`@a+tdor|UW^?pf$iZF4^}+MXQxjJ zzcA~29y+_tQ{-Utg&5p%8>i2uUvZoh>ae(fAZ@Sjdu7w&beq58G@BOpqE(4@uA|M~ zLcFBqS<$b_^}=TxR)%)|k{phWTAmd>NDgE4ij|?A_bJ`0$dm2!w2+@@9LGq2b0oq6 z9JMhxr{eyp>f3~JcAM`g9XY$r>KL45^G#**wHP*ERXTEZn=i)TESt|No3H-|o8*4W zrq0=Iz7fNw)pl}rn^xO(&a!E>{Y|BlYf`EQDIuOf8@OiaoV8|=s{E@F*s=#x=A*ha?U3u%Kk_N$L~ZnkDt6AOl~we z%@^}pNlb)EF(NkSA(w3DP?vR$4g6JoE!@R+U1DOQrR();&SP=s+c?e#`Mpc{(hZz` zt?1uPBS(L&wwu?OhgqVNO=n&!EgZ|}I?I;?>VDN{rjDH6pVCM8%A>WdKHX1pEMwIt z=dIEiHl6M#IbA1xRJzlLf7?%Tzw*;VOG2Ea4(GFc@sJVXM;j;W^GHg3Z>vu}iz@D0 zo6aFXDDJS0lh>Z&_S$U9asLgQa%_LYCOPZ5!?IZ=gj{!BT$91`_z3kS28F0XoQoJa zYurBo$Crv0M~&2?+zy+L8jIVebk&+otG>Vsql_F5i?cM$E3|ReeS_S5WpfAOcAHsB zXK}jCn{1qJbC$BXlNH#G45fP)`S$v*v2l8RQ*E4H-*{EuKVehe)Kf8jyk2mO1;=_U zPG8T+v5dtD=;WM1-sLu(zMhe@>#XZ9nL3QEWs~_j$8onf=_BgoG0;|@?k72xv2^;p zzR0H2{UoRBq#vq24|SR^x}W59KRFJDhnDdBKX#iM*U6@n`vs4bi4Lp}(Uvy!6p+fJ zjg8aaV>-!ce(LM>FNbV4X;9fbY2) zmyV)7WDA|M_DkQ!;H>@9m*n85rQ>^8%jO}Qj+|w4e+1x4Q_apWVk9WZF-l22Wy`!2saJx{>u6sl2bk5SfqIA1s=w47dowIaL zE8RyibdM{Y&RM#LmG0vhx<4zO&RM#g-Ad}f zeHKHvRMn?*md>Z@+Y>`qq;xuG>GG9sZwy_w(&?O~yG7~t#n8=BI-Rq08A`W5hHkpj z>71pTs&ofp=*BCZ&RM##O80pT-R0DwuXWDS4W$m;!5F%Msy>~wbQi1o4#m**R63or zbUl>ra132nrPDb}*HP)dh@oqzbUJ70S}EO^F?2%dbk5S9K4@O=U&YY<1di*3&RM!+ zN_QlN?mOzx*I&orjwtS%7~DZspUzqJ?N#-C8$d>D$XX&1$4qSZ<-QSc>=Pcb{mF{Q^-2>F2?cc}X?or&o zVsMp;`*#d(gW`^X!)>W~Z-%H?3yx=tv-VibTTKr4O^b5~53}X5%&yb8MRpzE_o%~X z)5-TeiYrmNAFRUKxquv;|53}cqF$vtZe?ia9Hl#<Ll#Hg(Rj>4~LNHqTYu=@>SXluezpY`SCVl+8AZI}^iZoU*BNmd#&2H^)Ketm)gR zxSwO#{1F_-R_836-^bD^KfhJnFEMO>p=|1$W%EERowE6<;-WEZ)+(DiXW9H`ES<9X zw&Hl5+2{3J%BId)HeXjdBZlr}rPDb}_q@_MV(6YyI-Rq0k11VT4BbQ2Vg1xOOZO-0 zz&T^+{zuiPbC&K7RbPAz-Fl_dIZGE%x>hlC%au;&EZq{NYaK&Zs&qPM=?ayO4~X{h zo3C^_XX&z(u1yTxO-iS8mTtDvwT+>hp>#TD>82@NyBNC3N~d#{E=}nYV(3OIoz7Xh z5lYuShHi+`>71n-pmZIe!~bX9H!miK!{YS&W^Z!1Z(5vw-#p*06YAoFt#j-;eiovR z&cEg?N_4c@G(63eXipB4q1hLWbJ;kj#>J`n+-$h*h#r7VH8`%FociM#R z9K-B0z3q=vhePKqn-9m}ESrC(P1v(^dfV@^>GZbW5reaAuCv+H+rElAtqpqHe; zvuqBx+0^I6rPN_;t@`vi(LV-f+3ZD|(Di|@_O_o-9S)td+TJY&XW8sTo3Ll;^tLD1 zbb8xc#o#QP(fw!Jbdpf(%PDYdyHy`K%g^I6ILqcy+JvsJ!B(DqM5x2{a8V5IYjXcj zb@w0JczGXi{ChWNGZ0uP23!cO*=23Gn&7)LJKtf74-A;A+XhHWVD8A>`HJuG-I+VH zx-@HDaH&C=>PlhCXeOmnq*-00Wm=}Wlcjo-RYjAfMU^$VRi;^+Cq-TU@E@7xbqk?%;JF&Fc@35m)2^myiXD8J_z z&zz^k%<;_cP)d$GbDk12^ZIjSZ{&Da@{GBd^OTr5&;GTw)2z3geOm0bip@G==65JL z8PB@D_WnQbS9#YQG4nf=%Mvr@X}=@sh$H35v+qwkcE%C2?=w60lB3W5{o=D@&ORk} zP{o{mO3bBVy3bF@A|1yIj3=l317gohjP*S@Aof|6H$ki)j`;R^enw*adsYt-a6a!* zm1oBE^ZwX?n5DWsK}?=^ooDZ7zCY$MN1nuVpAQa*={`T^=+k`OeUiu8^?2s%ob<^N8W4L& z#ZC-}y{%#=2gKe|u}22Pz9upDIy@lu6_xiWv3@w>+uNSkCB}8oF>~$vV#eBa?2~lp z{2Y>@PZ>wY%%ATPlfiXN--B}Qq9bqbo>wtxW9G@dCPz~8Si6qtdr-$@Uv$j;9P+Yb zJae8BlYE^gbCJ2q@uDNooTtR3jn3=OQRO`^dB$AKc}mQj=Ru42l8=r!;?6#e*prSt z^K-~48IOED7xQyS*by^7ha8ufF;DYz$Pq`L%u{~Jao7>F-;s9gkfTr8%L6_;=Im2q z2UX13r^NK<5Z&iv2ln5CA5nABG4t9=Oh(qR{&?zM@;dU&Yb!Blp1ub^Bzf$a?$f-s z5|eAIW9BuwZQpqJ@9pPJj+l9kT#oU~YxEyKwy(P$@1VtI@=K0?b;QhT)RmYqPuZ6P zK9V?`efIav*AMOMQ)2oW={_R|_Fto)%6Nx(tW?arMiR4(SbscqjsDS*XI>+TIrH>2 z+H~ZZ*GOV!p81~mTSuNbPl=g%=6m9A9C_wEC1&RJ=g7XvvF^w-=P5DCJH?*yYww*T z)xVM$?{XbGsQMciQ+sK~9v{$WRrRT3W}o|FMxQ$NM1PVp%Jt*>(kDlBK&%8zwbLQ!L=?@%v<~5R-Luu$ zQ)13Mz1Ocw-UrN6VlvNXWaAu1O7(e~nDZVyCw%2@jZeW>&Iy)G5L-` z$INT=%Z@zr8c9s@RjYjyIq1Z zr|Oky`&{x_yBvLb$Q^?8H$|Dj9LnlkowBX!yOiG8kUNM;NY1h2YN{K0C(0rJAVLdeD?!Y=h8|=b+lD)ws(kNmX zHEf~>&m%+b0OCkt_EF}AHEduT?oTo=M36u|!ZpAyyr&oglSre8?i1`&lzl=JGnmB! z)-d)YeIbDy=CO(fwy=1bJx3E=41bEg5XB5;v4AyfU>oi@{UU+{a+t>|8rXvC(?f0_ z!k9)DC9Gf_9ax`X{}93yGMGadb+oYy?`K&zCXq%F%cx-!J$NSBTf~t<0ZXW&h5WOu z={eSfSu9`;8`y^XdDeso63Ag5t7u>gt|``pFs6}32`gAf2iE6U6GE6m26HH*jy87T z{XA>JB+@8i88vL82hR(v32~%Qz!IuxVFx2T(~H=6k#)dIFg`*Ud71JYVL744a}$5BQ!8_iM|j+5_v45f+o5czD!?; zVg|EVz#2BNjj=0S2PBZgJXX=b7Lr-|#v&?cV*GXbguIu6H?d|&Jxy7}GHUAFCS_06 zJvXz*h$98bsj9L?xufd(y{6xtGc(K`(td$*4I9{2=iFyl2P7V$OdyAOb#6~LT&UK{xRXaXP8Nw7Y>RerwZOUC$m%ep%yq%8`zXVh zMpm6GQLd=^I%P-d7rDP6{bW=*M_E>NIUiR2w_jsi$T{y-?srTg4LMh&TvqiON~twM|iJF|2LvO&igEi8ORumj8#EXjoBOF zTHkKRYScF&?VLxKJs4Jf)Q|EGM(`N-B8sR%a++$d=7^WE3oo%WmQ|aPhwZk0%9yIh zPTS{_lzCO}@=h97@1y^Z^^se6&tm>o-nsCyw`n9l%r!tS#gEkHXD7$8a zQ`WGFo;sJ!un!o0jeJPE6@I^t4lK@1A%i)T(eLXNeL?D*ls$MJXKcv1IAu!J3zSQ! zqNUE|_>4G@RWz^#*JJE2!kC8ilR3e-kb0JLC9Gf_9as@N=6{yGgS1ovYu)9QDr|>Rb1!Io`><5ymvKkh#Y{%0B%X`#;8BevJF}6YRgAYl+l@+-GoK zvD?nR$Y&F*L2|q7%kXo2)`0xp|FT`KgzR!u?O}*=O4T!}oTDtO`bN}lzfI}pGr06M ze2-m@Q$|(YleW(VDC4RgN!jNTlsQ!|@b?nZ#}Z{#)jMbHa~7ZfMj`PXb1}M${uOalL+%XZZ`P_qTW#u)lN6J;i5K8FQZa7D}|~V3~G3EYWrcUD`)ycrTC> zj0mj8D8rXvC2z!q(WIs~Ot$-y|(ZUY8KIX`N zv{|qB*XbKY)DUM4G1ibrfp+Gus0YXCVMi&vp=hz|IK6exgMn_XxEpXvCArDOVt}5)&$94BX>jP zZ&SLDvv-If0co?K;sMoXoHC{AJF3r-)2tKHUXDEPsM%Mp|6a~btNS;7w|%}d%Co|` zb-145Ucx$3Y3>6^j&&dR2uieBK?fF}rG2yuBa0F`u%70*Aa4mR?5I9=@3Q;aR`Us} z@yAm3d9V7tTm8PoysBz_r8^lH>*&CuuTg|Bg$(9U#tM1sXpy^v9Q!wqRWz^#7eC*9 z2xA&ql#ra}`GYKZ_I2)SETW7m>exUFZEVB(ZSEQPFpeO?sJuaYw9r8h)>mi?4@NPL zFk(m`i41bcV-8DLK@IC@qJ=iLVa?Jfd>BU%Aw&?z4ARJ>h?y_(Ko~JhVFqdBP(TTbC}RyZG|)l^UF;%~XDqB^`0MNi{D>fl3<@Y= z84a|s1M5xN!;c82kislVSjH-exUF zZET^79;^b_03#U1ID&{Ej%g&3K?x1C&_NfwaDRhbjKPl}!iXY{DI`%q4Q-6R%~%K` zj3~;8f0H$!i)fMkK@%hI&^Kb3MiOb{kjESru#76|XrP5Qw$a5dtao|lF$@nvm_-3| zn8zZPv4RTpcR9MOe2ae6@w0Eb+&33p?t5?;Cvh4t;UeC^yLcbp!(ZU9@e}+MKf}%M zkdMPSiPLxq7x4z(#ryak; zK{-$2EtDg;6LRoXl@(?^@;zM}9^8(*vHP~mE%iDj|JsHX!X4OKJay~oC!RRz8-MyU zpL@V}bmI8L(TQUN&K>z5ICpGsUa~)dBNG8e{a-t0O|)(oXKbEy`(va(~Go_oa9Mat}&7xi2GBx{#RkC8gY-a_uBn+R1$! zpmVu@^`WaLIB^rCo!qB&Zg{y*C0FiU=}+$0$D!NFeZ5P&Hs_?B#C5w*QJ22uxsm5; z^H;9lL!9cjlk!>Ub{*PvXt$v!rP@iKpEugA@%*kaiOO+Kszchyk$~<`p5yeX!Q-A) z?PR@K+GT0C^>Kcq4n2j7{9fv^zQn(|+=&a!?>*IsLXVrFuG{%}5BT}k+I+rsyDu5- zg0u^MK)bIR?c}`@rrj*(^dbF;w;+2g^ON^!g?1(CdORs*9&@UccCiva1DLJ+f2{PO t=lX3<=(S5s+DWcHbnJajaH;x-#G4<`PVOBUQy()24p>Y2H%wC=7ywEk=aO2FNAsmr$P!ft7oZf~AR*NE(xlIY#{J$EKd zDYku{y?MU*zVCcL=R4o|&bdD)JF8Yy=jG*z>@`B<3v#WU4(D9pIqD)K> zC1NC+D4W|39l&1DgaUvAkPkRPfQ)b@XaZ&QJ=_~)0(`djX!1VxLP8%U(LSQ&zI$%_$Z9K3XM}{Z5F^49} zA!aY;kC)7mO$ww$OwQ1kLpNj^rvYC9xEkOB6asj0o_LM5k<49Dh9**S=v-3fgt^Bx zUVLhCe0wlYS^g#v{eNNeS75}m!0+3WJ0 z|DS_bbNc@e@MVw(kuchSLOJ;6O#f-{CivCBlz#yz%dvMr?2I`{4BQF*YUtA6jo=S}2Py4mg5Q(F&jr66{oR?-zYF{#&osdv!xpYxGAV4I&T->QPlRdxOES zPeiqduVou-ecHAbe}fhdh9B`qa(KO^1w7P3)C+`L{2>wW1;bIl2yFIiQRzXAh?YoG zNDGJtyQi?OH3%6*z#k5XK*aBD6oD2U`VELAf_@OX=8uHDLDA3})w~)VHR>%Q@JOUd z^NVQI=M4o!c1Y+d+=7uda8UNB^$_;EheX65@;3YF)~}%l-y;L5$7wO=4`M2Z*sTzDJA=sGArwf0!7X=27CQSQEt9h>jC0xOWg^V?9ZXjqWrt zHoG&#*o@B-V>2^}M+(tLj19V<7#q@gVifxTF*e&FVr=MU0?a`nta&e>#VXy4U)G^j z$`Pp~d(T+7N;xu>vfks8=Ll8a7J9oS&ylL!?t9;mJV&f5PX3JKnOU`y{Bg-M!)lUzx8#{=br1PBB+rbid&%#W zJTtGpN)R+&TX?@pLaR7S>yrez{ zUHk5{@MBc)S7>9CiG1t0amZoZA@uX>55?1mlF1|js7-7rvUJS#A-F#Kg=HNnc<}FF z5&v2pP-4T-G3Y{1eFJ@4^R~mAHIE|oJqB|S7RL@jZk|L8(u)VkKFG(!~wWUnG_OC$C zVrxCA8$r?4(`2ruN}f3zNt5HbZ*6TtFG_4ENwiHeD%Nqx`eY_Tph~vnS@UYpWWEfm zmmmClBw{T2{IOJwkMn%oBOfPH*TvI`k-Hru78YvGn5DTEj@8F3>B;9bq^^jkm%K#V zn+s@FesKGVya}WdD~sdf6B8&ZmkoMhk5pj|c)GLEjD73^W6=uataka&uiw~k>=5US zv9}c^^y0(>2d1sdF|mT0JFY?eTk_Ue^NMjlF>gogJq1*deovKu);0xokr+#&y+HU!M5%+Lgl!#G(w_}uJ$n`$ezyH7!>3 zgu~efIClxC;7{hX?a!ev)%_}-evP(bq1_hmfBy5fV$Al8pT@h+A{0+|`O&sV6VJ(E zox@m*n`n=ref#{pLVfg+{KCrWWvTf|qiu@N zi;Xr#=r^aPFh7%oR&peNY$a8UBO_8J(3vLmvBNp&%!g_D`sx$6{G#`fQ4mlG?+{XI zZaf`GR2@wpUZlGNvF`0?zxoBVqn1kBF&7p5(KB;3E?KKqKx+Q$=d9txhW9e}1f%a3 zxs5tiFT{!ZB5St!J%rO!HGq7Jo~k|~5BM`Ada6ttowd?3zVck0sBCMl9&DFsdAY)K>#YUj5r|K+z zv!SPo<7te-Zpn<|48#~?FNbmI2+vRxvIA0fnq2RGNuRWR$g%f6kEUc#mCQg-)d{H< zW7|L2TDfUUg;7Ih0#lmuC%1?#gm|Lg)qNui?OG8$ffs|K@^rJUYa>cNUmG zLGw%G%KO`H=-Mz4PuH?`=00vo9rK(F%9&Bw{wsM)HuwB5ZpFL_+iaXH?_?+$qk`>1 z!>ZRy)O{SnO%P+ml}HQobqBiiq|5aI*OPo-e3#?rTAXA4Sa!z!qT^?fs7GL}{s2E+ zRp)EW+XrQSq~Bxo`|)|{HwE{wSNqXs&FQM@uQ7|DYRyqUqtt9`7^bWo&qTadjM5o^?n43d(>Dqx3}ia)W*L=a`z-l zYIdB`b8T>Av3mcK&IT7~pSnIcgolG-^Bu&Bt@)R*U!YgmwIIE;&lmbtb~PN?aWLW7 zB?HP)NUSW0=Ut2`b;Gb(v8{Dc2Gt%eDuG^86EC(eiOb<1Kx9ae{iv1MlUL#?xXAVP z;yk1KJ!8P*+O-u9@DNe=tgN9G&pDjkfX)nFm%(f!Je$Ke=FnL=am!b<=jwbFJtbqi zJ%h{sh_AVq$X?Cxi-4_%9qP@fnbcO?OF_FyZ?S0)>5Vo$m-HH&zMXWnP2WL!flc2< z+HKR7q_4N>WuzzC^gW~tZF&{xTJy$pyzQlm;^`l9iV}+*@kz0dwL&>5DX!N8telJY zxySmrnaT<->50`rM!T2Rz*{`_09endAL9NY$~P46DDxbPr*}KXb#~lDN&EJ3c~iB~ zOODv=0^`G?$|ca-c{p0 zOU;vd2r(KLmTSd3M;jOJ(nhE5$35kOs@EQXoz=S!ib**dx#io>ZLW?^G+S>md|BjJ zi`Lv-crCGh&b@8m3vG*C#g-gmuMdjo$8(Cqn&>$O+V!?$T={WrG)KWfeA4Au|KXVt z?b}D@P1UbREFJ0S5ll_*blcW?i(|{ft~D7MwR>^J3ehGr-1W+GkQbjzkYPNPw>ft# z!z+{L6yAC2i`utOrf*A|>~y_7vPNCY>AVuLa4XL?2GD5!^(S%PhHdk!dNsXvc6J zyr-k9;`r6^lU@Ekd&jMPw-dXfQNdqp_?>*nxC1wX>^r$x*>73+W;4edjWZjt^V-yr(SjheCc$D=ZZC zQSWB|0%@c-YHHA@te+WJ$PZ_CZcx?-nu7jlS#-t*Xu_oy@rI&7d_)9^PiKl0D}hM3 zSqX>yN+29*_G*e2R=lCGrurj_*XIjI8k<6!*|^mkX$tGnLV@pf2sG-3)73Vqcq9G= zg+ftg>WY2MMEIet{)lu}zv}LF8SieTa?PzPs;5V3qTo{=b^ML=&sOQ9@p3+vuC5(+ zae4cUW9he1C?8{H{w2 zrOfBW^mv2O8PZs5ZOw$3?GE3XYuO0|(H5`IA9X7$y{%2ndb83LRZ1JBS*Ds$lxy&< zS7B*Im2e@cTB?OQX{fZ1ka~mKIcQp;#5x z6t5ETZ`Om}h_q5Jqoc^L)2w)Z6ypp1p-vrFkI?HImwFeg%bQn5YqbS+3jzzO7X(-M zD#hKQt=?c0D%rb9i8ejz$2a9{lf7Wjz)<|5u)bMUn*Gh;$Tl|`8ydJS8yeiLt*zpb zO`_5p!tzs)BCJ#eAKbHpRorgHyD1#e{t)et6N_9~h1QP@o1RDe&00OKC2zB{g0!z9yTXmcR$uIOqHs7hpIpI!- zZ|3+a$jz1)?k;>IAI9=*lMT4W;jHCafE#cpU=?5^AOzR}coOhk!0Uhy06zizC*Xeo zUjoMAZ01^kn`bnDRe+6v5PVHxNm0MG95DPEr0;K)gsIHTpcP5pP_?lZ5$=dT=*D4-O|%3x;g*M0Zb`~B8Mi#Qa!11QXvS^-`m}HaMvXSw z9EKe{dz+hl!gl8iH#hr3Xh!+_htv3{2%cp#C!8mFP7juDbZtfTCeCCkyk^K|O5UW!q8tQXp{ zhUkxVvjmXUV|~qs9_x;JlxOw64w}AMzpU?m5R_*x>hZc4kkuQ2-T?I4vq3>dJ;K@? zJ^rsmE1ccJ0cNhOzX!l){qd|~-=xd;yD6i`@p50-5514FPBJneu_Z%ud^{E5|4HO@ zD`TTxOO76&tvaE1x$!=dqnCtU@+rrH0;vUMUxFRz@~bmtq2E>KBjz2wxHb&M5X-h36E{d4->(@n1hx_?g1b zi3r~)k>4u(j+h7+h@0S|;<=>oG7%E5FySZ4fu9+_Fn%TAZ){zKB!Dr1YrOG0<2vIH z&XP_g5fgq?_HZGM+!q;_l;gO}<`pv2;Rj+8+~B+q=MerRE9oY0-eUL}fTTzbFp&UB zjAX_%_N5SVQVCtt3DOJ#q%mePW-(?Ha1LAPY|Ujn&uT9a@I|&>V(VqLUSaE1#%qk% z*>{R@nm6BPe88J;Fy162zQxwtjCUCCGTvi+#Q2zz!IGJL1X+xEjQNag49wvI-pE0o z?_4$)G8PeVFf{{OF^)6tW!y)Ary2M2<|yL?V~p_t<3Ywl z1bCROM;MRt=3|VYr&oG{4oMb%5NJ=LpGo~?87^#dkSWh!J`Bsc$&`{&4 zlgm8TX1S@Q-m*@v@wjBG+ahlkuF1>%?H)>QA48M14m^xI-Ad{5EHeQZF&Ru1q;4X^ zSXv5Dh9~ay!Hm}{$0e|8yfb9GB5Fis)QGC65!F#6)<%t}i5jskYQ*}e5gVdLY>XOF z8#Q7RUAT9=cX6@oa6qF{D*S%BpJ5u+ z+JuwN{2B0lDvUNdEe;(gvB&2f)DfmTWKDmOWUyIm1x8bKp=4;byV}eS$>4C>Z4S3& zkZHr_YAoQRGm%kvc%ZjST2Q-Ll%tJ%ozK(-l-$cT0v&%No-{SF? z*xIF%?N+J8E*YkJ-|-wzyg6t65SYQydT+-_PtU|N2*X|RibT#cSlTVkW}7AQU;jPc zbLte*$3!=MM@)DT!tfwPOyS7>D^qyhkIqr=(7=eV(<{jXeS;IvqEnv2`J-JKrh11{ zdw9C{_7yz~t$l+7zG11Ux5KyB*SoiWf@G`BF{Q7$hN<4+1jqePyTA5xjsCw)Y6dD` zI9=?3=2L0B?Q)x)?iNR}Z7bN!TP^jL2A4EM0_lL9$kYgV6mE_)!NqF zUOxVs7d|y11|y%I83iq5!W^~+ zeIh=Vz5*(t3bNIdP^}2#n#3Gd!&<1Jr<7<~t+oi`5^xJZvItSi2LVaqQF2f9UAX8NlEs~Z}iG%MpLMxu?Tn`p# zpc*DxL@lLYhK?&RyCO?p-w2z*3Uk%qNLs;4th}>{am7=ex4>3tqPGCi!nH&t){aZ~ zM3%nZ2F+lncMj3QwStv6QIft|1m($wH^Em4WJTEeHM=`wc1 z9@tB7*`h_%3RYtNP6?c^_^NXUbV3)s(~B0aB`UFYT*4=^^z~loh8{>&gCl7Lo)Mv1 z@jN&7K`-p5uOiXHwL~S>Y6+jn($^n=gV0CcV4_9PitwC|uR8a`01QI1kcx0Gw+1U# z$hhLFVu!#7L-Z9ZTKKp`CDv*QpUBeJ55ou?rf+7^B58$R8}U`=BXAUs@uGyWbG6a_ z87X2%ZAQ&bC33Fumhp6EJpZa-A0DT{ZNT-o4tL;oya#)*8@zv&jo5$|tVbE^(2Sd~7B^xIuElDs!b+^b zax6m=8nF~hu$cZ^d^Hx~DlEhTT#5O(0u7jl%W)YkCs>M0XpO-lT!^`tg9|Vl=i@xg z3Myt|2CbJ!r_~d)aTd From 7a1ac419fa0d2d23ddd08bd61d16896a9f33c933 Mon Sep 17 00:00:00 2001 From: Haiying Wang Date: Thu, 23 Aug 2007 15:20:54 -0400 Subject: [PATCH 197/259] Enable L2 cache for MPC8568MDS board The L2 cache size is 512KB for 8568, print out the correct informaiton. Signed-off-by: Haiying Wang --- cpu/mpc85xx/cpu_init.c | 2 +- include/configs/MPC8568MDS.h | 6 +++--- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/cpu/mpc85xx/cpu_init.c b/cpu/mpc85xx/cpu_init.c index 7b9961013..79ad20c91 100644 --- a/cpu/mpc85xx/cpu_init.c +++ b/cpu/mpc85xx/cpu_init.c @@ -247,7 +247,7 @@ int cpu_init_r(void) switch (cache_ctl & 0x30000000) { case 0x20000000: if (ver == SVR_8548 || ver == SVR_8548_E || - ver == SVR_8544) { + ver == SVR_8544 || ver == SVR_8568_E) { printf ("L2 cache 512KB:"); /* set L2E=1, L2I=1, & L2SRAM=0 */ cache_ctl = 0xc0000000; diff --git a/include/configs/MPC8568MDS.h b/include/configs/MPC8568MDS.h index d5a14fc39..ba744e99f 100644 --- a/include/configs/MPC8568MDS.h +++ b/include/configs/MPC8568MDS.h @@ -63,9 +63,9 @@ extern unsigned long get_clock_freq(void); /* * These can be toggled for performance analysis, otherwise use default. */ -/*#define CONFIG_L2_CACHE*/ /* toggle L2 cache */ -#define CONFIG_BTB /* toggle branch predition */ -#define CONFIG_ADDR_STREAMING /* toggle addr streaming */ +#define CONFIG_L2_CACHE /* toggle L2 cache */ +#define CONFIG_BTB /* toggle branch predition */ +#define CONFIG_ADDR_STREAMING /* toggle addr streaming */ /* * Only possible on E500 Version 2 or newer cores. From 4bf4abb8a4e9955556b120a1aafa30c03e74032a Mon Sep 17 00:00:00 2001 From: Ed Swarthout Date: Tue, 21 Aug 2007 09:38:59 -0500 Subject: [PATCH 198/259] 8548cds fixes Restore CONFIG_EXTRA_ENV_SETTINGS definition which contains the correct consoledev needed for linux boot. Standardize on fdt{file,addr} var to hold dtb file name. Set PCI inbound memory region from CFG_MEMORY_{BUS,PHYS}. Signed-off-by: Ed Swarthout --- board/cds/mpc8548cds/mpc8548cds.c | 14 +++++++++++--- include/configs/MPC8548CDS.h | 15 ++++++--------- 2 files changed, 17 insertions(+), 12 deletions(-) diff --git a/board/cds/mpc8548cds/mpc8548cds.c b/board/cds/mpc8548cds/mpc8548cds.c index 48753d7e2..796ae22a6 100644 --- a/board/cds/mpc8548cds/mpc8548cds.c +++ b/board/cds/mpc8548cds/mpc8548cds.c @@ -362,20 +362,28 @@ pci_init_board(void) ); - /* outbound memory */ + /* inbound */ pci_set_region(hose->regions + 0, + CFG_PCI_MEMORY_BUS, + CFG_PCI_MEMORY_PHYS, + CFG_PCI_MEMORY_SIZE, + PCI_REGION_MEM | PCI_REGION_MEMORY); + + + /* outbound memory */ + pci_set_region(hose->regions + 1, CFG_PCI1_MEM_BASE, CFG_PCI1_MEM_PHYS, CFG_PCI1_MEM_SIZE, PCI_REGION_MEM); /* outbound io */ - pci_set_region(hose->regions + 1, + pci_set_region(hose->regions + 2, CFG_PCI1_IO_BASE, CFG_PCI1_IO_PHYS, CFG_PCI1_IO_SIZE, PCI_REGION_IO); - hose->region_count = 2; + hose->region_count = 3; /* relocate config table pointers */ hose->config_table = \ diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h index 682f0c057..608371518 100644 --- a/include/configs/MPC8548CDS.h +++ b/include/configs/MPC8548CDS.h @@ -633,7 +633,6 @@ extern unsigned long get_clock_freq(void); #define ENET_ENV "" #endif -#if 0 #define CONFIG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0" \ "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ @@ -646,8 +645,8 @@ extern unsigned long get_clock_freq(void); "consoledev=ttyS1\0" \ "ramdiskaddr=2000000\0" \ "ramdiskfile=ramdisk.uboot\0" \ - "dtbaddr=c00000\0" \ - "dtbfile=mpc8548cds.dtb\0" \ + "fdtaddr=c00000\0" \ + "fdtfile=mpc8548cds.dtb\0" \ "eoi=mw e00400b0 0\0" \ "iack=md e00400a0 1\0" \ "ddrreg=md ${a}000 8; md ${a}080 8;md ${a}100 d; md ${a}140 4; md ${a}bf0 4;" \ @@ -669,8 +668,6 @@ extern unsigned long get_clock_freq(void); PCI_ENV1 \ PCI_ENV2 \ ENET_ENV -#endif - #define CONFIG_NFSBOOTCOMMAND \ "setenv bootargs root=/dev/nfs rw " \ @@ -678,8 +675,8 @@ extern unsigned long get_clock_freq(void); "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ "console=$consoledev,$baudrate $othbootargs;" \ "tftp $loadaddr $bootfile;" \ - "tftp $dtbaddr $dtbfile;" \ - "bootm $loadaddr - $dtbaddr" + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr - $fdtaddr" #define CONFIG_RAMBOOTCOMMAND \ @@ -687,8 +684,8 @@ extern unsigned long get_clock_freq(void); "console=$consoledev,$baudrate $othbootargs;" \ "tftp $ramdiskaddr $ramdiskfile;" \ "tftp $loadaddr $bootfile;" \ - "tftp $dtbaddr $dtbfile;" \ - "bootm $loadaddr $ramdiskaddr $dtbaddr" + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr $ramdiskaddr $fdtaddr" #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND From 9468e6804b7e25b0f6f52e53f47bce3175400a16 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Mon, 20 Aug 2007 09:44:00 -0500 Subject: [PATCH 199/259] Fix MPC8544DS PCIe3 scsi. The problem is pciauto_setup_device() getting called from fsl_pci_init.c is allocating memory space it doesn't need. Signed-off-by: Ed Swarthout Signed-off-by: Andy Fleming --- drivers/fsl_pci_init.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/fsl_pci_init.c b/drivers/fsl_pci_init.c index 3a13eea1f..a4ce458a5 100644 --- a/drivers/fsl_pci_init.c +++ b/drivers/fsl_pci_init.c @@ -54,6 +54,7 @@ fsl_pci_init(struct pci_controller *hose) u8 temp8; int r; int bridge; + unsigned long bus_lower_temp; volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) hose->cfg_addr; pci_dev_t dev = PCI_BDF(busno,0,0); @@ -134,9 +135,10 @@ fsl_pci_init(struct pci_controller *hose) * but do not allocate any windows since any BAR found (such * as PCSRBAR) is not in this cpu's memory space. */ - + bus_lower_temp = hose->pci_mem->bus_lower; pciauto_setup_device(hose, dev, 0, hose->pci_mem, hose->pci_prefetch, hose->pci_io); + hose->pci_mem->bus_lower = bus_lower_temp; #ifndef CONFIG_PCI_NOSCAN printf (" Scanning PCI bus %02x\n", hose->current_busno); From 2d1f23aa1e74e4a8f8ffa67f246eb98c522dfd7f Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Wed, 29 Aug 2007 13:35:03 +0200 Subject: [PATCH 200/259] Disable network support on cmi_mpc5xx board ..because it caused compiler errors and there seems to be no board maintainer to take care of this. Signed-off-by: Wolfgang Denk --- include/configs/cmi_mpc5xx.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/configs/cmi_mpc5xx.h b/include/configs/cmi_mpc5xx.h index cd92af235..85c2b96fe 100644 --- a/include/configs/cmi_mpc5xx.h +++ b/include/configs/cmi_mpc5xx.h @@ -59,6 +59,8 @@ */ #include +#undef CONFIG_CMD_NET /* disabeled - causes compile errors */ + #define CONFIG_CMD_MEMORY #define CONFIG_CMD_LOADB #define CONFIG_CMD_REGINFO From c5bded3c88e48ae648a75d357dc81a8255fa81f1 Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Wed, 29 Aug 2007 14:05:30 +0200 Subject: [PATCH 201/259] Add mii_init() prototype to get rid of a *lot* of compiler warnings. Signed-off-by: Wolfgang Denk --- include/common.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/common.h b/include/common.h index d6286bc6d..9a5a0ab79 100644 --- a/include/common.h +++ b/include/common.h @@ -565,7 +565,7 @@ ulong bootcount_load (void); #define BOOTCOUNT_MAGIC 0xB001C041 /* $(CPU)/.../ */ -/*void mii_init (void);*/ +void mii_init (void); /* $(CPU)/.../lcd.c */ ulong lcd_setmem (ulong); From 2602a5c40ae37ab965a4e240854fdaffb51328a4 Mon Sep 17 00:00:00 2001 From: Kim Phillips Date: Wed, 29 Aug 2007 09:06:05 -0500 Subject: [PATCH 202/259] sbc8641: remove unused OF_FLAT_TREE_MAX_SIZE this had slipped through the cracks, since the sbc board was added after I wrote the original patch to remove all these symbols, and before it was merged. Signed-off-by: Kim Phillips --- include/configs/sbc8641d.h | 3 --- 1 file changed, 3 deletions(-) diff --git a/include/configs/sbc8641d.h b/include/configs/sbc8641d.h index 3525ab4c5..54eac38b8 100644 --- a/include/configs/sbc8641d.h +++ b/include/configs/sbc8641d.h @@ -270,9 +270,6 @@ #define CONFIG_OF_FLAT_TREE 1 #define CONFIG_OF_BOARD_SETUP 1 -/* maximum size of the flat tree (8K) */ -#define OF_FLAT_TREE_MAX_SIZE 8192 - #define OF_CPU "PowerPC,8641@0" #define OF_SOC "soc@f8000000" #define OF_TBCLK (bd->bi_busfreq / 4) From 04625764cc93ce8a61625ac19d7fe2a2ceee8143 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Wed, 29 Aug 2007 16:31:18 +0200 Subject: [PATCH 203/259] ppc4xx: Change lwmon5 default environment to support Linux RTC The Linux PCF8563 RTC driver doesn't do autoprobing, so we need to supply the RTC I2C address as bootline parameter. This patch adds support for this rtc probing parameter to the bootargs: "rtc-pcf8563.probe=0,0x51" Signed-off-by: Stefan Roese --- include/configs/lwmon5.h | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/include/configs/lwmon5.h b/include/configs/lwmon5.h index be483245b..50df84813 100644 --- a/include/configs/lwmon5.h +++ b/include/configs/lwmon5.h @@ -200,12 +200,13 @@ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ ":${hostname}:${netdev}:off panic=1\0" \ "addtty=setenv bootargs ${bootargs} console=ttyS1,${baudrate}\0"\ - "flash_nfs=run nfsargs addip addtty;" \ + "addmisc=setenv bootargs ${bootargs} rtc-pcf8563.probe=0,0x51\0"\ + "flash_nfs=run nfsargs addip addtty addmisc;" \ "bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip addtty;" \ + "flash_self=run ramargs addip addtty addmisc;" \ "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ - "bootm\0" \ + "net_nfs=tftp 200000 ${bootfile};" \ + "run nfsargs addip addtty addmisc;bootm\0" \ "rootpath=/opt/eldk/ppc_4xxFP\0" \ "bootfile=/tftpboot/lwmon5/uImage\0" \ "kernel_addr=FC000000\0" \ From 8f1bc28408ded213418d9bc0780c7d8fb8a03774 Mon Sep 17 00:00:00 2001 From: Grant Likely Date: Wed, 29 Aug 2007 18:26:24 -0600 Subject: [PATCH 204/259] tftp: don't implicity trust the format of recevied packets The TFTP OACK code trusts that the incoming packet is formated as ASCII text and can be processed by string functions. It also has a loop limit overflow bug where if the packet length is less than 8, it ends up looping over *all* of memory to find the 'blksize' string. This patch solves the problem by forcing the packet to be null terminated and using strstr() to search for the sub string. Signed-off-by: Grant Likely --- net/tftp.c | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/net/tftp.c b/net/tftp.c index fb2f50564..27f5e88be 100644 --- a/net/tftp.c +++ b/net/tftp.c @@ -238,9 +238,9 @@ TftpSend (void) static void TftpHandler (uchar * pkt, unsigned dest, unsigned src, unsigned len) { + char * blksize; ushort proto; ushort *s; - int i; if (dest != TftpOurPort) { #ifdef CONFIG_MCAST_TFTP @@ -272,22 +272,22 @@ TftpHandler (uchar * pkt, unsigned dest, unsigned src, unsigned len) case TFTP_OACK: #ifdef ET_DEBUG - printf("Got OACK: %s %s\n", pkt, pkt+strlen(pkt)+1); + printf("Got OACK:\n"); + print_buffer (0, pkt, 1, len, 16); #endif TftpState = STATE_OACK; TftpServerPort = src; + /* Check for 'blksize' option */ - for (i=0;i Date: Thu, 30 Aug 2007 02:26:17 -0500 Subject: [PATCH 205/259] Revert "Fix MPC8544DS PCIe3 scsi." This reverts commit 9468e680. Commit 16e23c3f5da removing allocation of PCSRBAR is sufficient. Signed-off-by: Ed Swarthout --- drivers/fsl_pci_init.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/drivers/fsl_pci_init.c b/drivers/fsl_pci_init.c index a4ce458a5..3a13eea1f 100644 --- a/drivers/fsl_pci_init.c +++ b/drivers/fsl_pci_init.c @@ -54,7 +54,6 @@ fsl_pci_init(struct pci_controller *hose) u8 temp8; int r; int bridge; - unsigned long bus_lower_temp; volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) hose->cfg_addr; pci_dev_t dev = PCI_BDF(busno,0,0); @@ -135,10 +134,9 @@ fsl_pci_init(struct pci_controller *hose) * but do not allocate any windows since any BAR found (such * as PCSRBAR) is not in this cpu's memory space. */ - bus_lower_temp = hose->pci_mem->bus_lower; + pciauto_setup_device(hose, dev, 0, hose->pci_mem, hose->pci_prefetch, hose->pci_io); - hose->pci_mem->bus_lower = bus_lower_temp; #ifndef CONFIG_PCI_NOSCAN printf (" Scanning PCI bus %02x\n", hose->current_busno); From ff13ac8c7bbebb238e339592de765c546dba1073 Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Thu, 30 Aug 2007 14:42:15 +0200 Subject: [PATCH 206/259] Backout commit 8f1bc284 as it causes TFTP to fail. Signed-off-by: Wolfgang Denk --- net/tftp.c | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/net/tftp.c b/net/tftp.c index 27f5e88be..fb2f50564 100644 --- a/net/tftp.c +++ b/net/tftp.c @@ -238,9 +238,9 @@ TftpSend (void) static void TftpHandler (uchar * pkt, unsigned dest, unsigned src, unsigned len) { - char * blksize; ushort proto; ushort *s; + int i; if (dest != TftpOurPort) { #ifdef CONFIG_MCAST_TFTP @@ -272,22 +272,22 @@ TftpHandler (uchar * pkt, unsigned dest, unsigned src, unsigned len) case TFTP_OACK: #ifdef ET_DEBUG - printf("Got OACK:\n"); - print_buffer (0, pkt, 1, len, 16); + printf("Got OACK: %s %s\n", pkt, pkt+strlen(pkt)+1); #endif TftpState = STATE_OACK; TftpServerPort = src; - /* Check for 'blksize' option */ - pkt[len] = 0; /* NULL terminate so string ops work */ - blksize = strstr((char*)pkt, "blksize"); - if ((blksize) && (blksize + 8 < (char*)pkt + len)) { - TftpBlkSize = simple_strtoul(blksize + 8, NULL, 10); + for (i=0;i Date: Fri, 31 Aug 2007 10:01:51 +0200 Subject: [PATCH 207/259] Fix TFTP OACK code for short packets. The old code had a loop limit overflow bug which caused a semi- infinite loop for small packets, because in "i --- net/tftp.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/net/tftp.c b/net/tftp.c index fb2f50564..5ee767646 100644 --- a/net/tftp.c +++ b/net/tftp.c @@ -276,8 +276,12 @@ TftpHandler (uchar * pkt, unsigned dest, unsigned src, unsigned len) #endif TftpState = STATE_OACK; TftpServerPort = src; - /* Check for 'blksize' option */ - for (i=0;i Date: Fri, 31 Aug 2007 15:21:46 +0200 Subject: [PATCH 208/259] ppc4xx: (Re-)Enable CONFIG_PCI_PNP on AMCC 440EPx Sequoia The 440EPx has a problem when the PCI_CACHE_LINE_SIZE register is set to non-zero, because it doesn't support MRM (memory-read- multiple) correctly. We now added the possibility to configure this register in the board config file, so that the default value of 8 can be overridden. Here the details of this patch: o drivers_pci_auto.c: introduce CFG_PCI_CACHE_LINE_SIZE to allow board-specific settings. As an example the sequoia board requires 0. Idea from Stefan Roese . o board/amcc/sequoia/init.S: add a TLB mapping at 0xE8000000 for the PCI IO-space. Obtained from Stefan Roese . o include/configs/sequoia.h: turn CONFIG_PCI_PNP back on and set CFG_PCI_CACHE_LINE_SIZE to 0. Signed-off-by: Gary Jennejohn Signed-off-by: Stefan Roese --- board/amcc/sequoia/init.S | 3 +++ drivers/pci_auto.c | 8 +++++++- include/configs/sequoia.h | 3 ++- 3 files changed, 12 insertions(+), 2 deletions(-) diff --git a/board/amcc/sequoia/init.S b/board/amcc/sequoia/init.S index 45bcd4bef..5fe3af9a0 100644 --- a/board/amcc/sequoia/init.S +++ b/board/amcc/sequoia/init.S @@ -126,6 +126,9 @@ tlbtab: /* TLB-entry for peripherals */ tlbentry( 0xEF000000, SZ_16M, 0xEF000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I) + /* TLB-entry PCI IO Space - from sr@denx.de */ + tlbentry(0xE8000000, SZ_64K, 0xE8000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I) + tlbtab_end #if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) diff --git a/drivers/pci_auto.c b/drivers/pci_auto.c index 2378553be..acfda83ba 100644 --- a/drivers/pci_auto.c +++ b/drivers/pci_auto.c @@ -28,6 +28,11 @@ #define PCIAUTO_IDE_MODE_MASK 0x05 +/* the user can define CFG_PCI_CACHE_LINE_SIZE to avoid problems */ +#ifndef CFG_PCI_CACHE_LINE_SIZE +#define CFG_PCI_CACHE_LINE_SIZE 8 +#endif + /* * */ @@ -150,7 +155,8 @@ void pciauto_setup_device(struct pci_controller *hose, } pci_hose_write_config_dword(hose, dev, PCI_COMMAND, cmdstat); - pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08); + pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, + CFG_PCI_CACHE_LINE_SIZE); pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80); } diff --git a/include/configs/sequoia.h b/include/configs/sequoia.h index 824a81240..c2e138621 100644 --- a/include/configs/sequoia.h +++ b/include/configs/sequoia.h @@ -400,7 +400,8 @@ *----------------------------------------------------------------------*/ /* General PCI */ #define CONFIG_PCI /* include pci support */ -#undef CONFIG_PCI_PNP /* do (not) pci plug-and-play */ +#define CONFIG_PCI_PNP /* do pci plug-and-play */ +#define CFG_PCI_CACHE_LINE_SIZE 0 /* to avoid problems with PNP */ #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ #define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE*/ From f75e89e9b5714db2b0e80074071dfbdd6f59488a Mon Sep 17 00:00:00 2001 From: Ed Swarthout Date: Thu, 30 Aug 2007 01:58:48 -0500 Subject: [PATCH 209/259] ft_board_setup update 85xx/86xx of pci/pcie bus-range property. pcie is now differentiated from pci. Add 8641 bus-range updates. Signed-off-by: Ed Swarthout --- board/cds/mpc8548cds/mpc8548cds.c | 2 +- board/freescale/mpc8544ds/mpc8544ds.c | 14 +++++++++++--- board/freescale/mpc8641hpcn/mpc8641hpcn.c | 16 ++++++++++++++++ 3 files changed, 28 insertions(+), 4 deletions(-) diff --git a/board/cds/mpc8548cds/mpc8548cds.c b/board/cds/mpc8548cds/mpc8548cds.c index 796ae22a6..36d7e1ed4 100644 --- a/board/cds/mpc8548cds/mpc8548cds.c +++ b/board/cds/mpc8548cds/mpc8548cds.c @@ -542,7 +542,7 @@ ft_pci_setup(void *blob, bd_t *bd) #endif #ifdef CONFIG_PCIE1 - p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@a000/bus-range", &len); + p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pcie@a000/bus-range", &len); if (p != NULL) { p[0] = 0; p[1] = pcie1_hose.last_busno - pcie1_hose.first_busno; diff --git a/board/freescale/mpc8544ds/mpc8544ds.c b/board/freescale/mpc8544ds/mpc8544ds.c index 80822bec7..4c3b27f23 100644 --- a/board/freescale/mpc8544ds/mpc8544ds.c +++ b/board/freescale/mpc8544ds/mpc8544ds.c @@ -516,8 +516,16 @@ ft_board_setup(void *blob, bd_t *bd) *p++ = cpu_to_be32(bd->bi_memstart); *p = cpu_to_be32(bd->bi_memsize); } +#ifdef CONFIG_PCI1 + p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@8000/bus-range", &len); + if (p != NULL) { + p[0] = 0; + p[1] = pci1_hose.last_busno - pci1_hose.first_busno; + debug("PCI@8000 first_busno=%d last_busno=%d\n",p[0],p[1]); + } +#endif #ifdef CONFIG_PCIE1 - p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@a000/bus-range", &len); + p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pcie@a000/bus-range", &len); if (p != NULL) { p[0] = 0; p[1] = pcie1_hose.last_busno - pcie1_hose.first_busno; @@ -525,7 +533,7 @@ ft_board_setup(void *blob, bd_t *bd) } #endif #ifdef CONFIG_PCIE2 - p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@9000/bus-range", &len); + p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pcie@9000/bus-range", &len); if (p != NULL) { p[0] = 0; p[1] = pcie2_hose.last_busno - pcie2_hose.first_busno; @@ -533,7 +541,7 @@ ft_board_setup(void *blob, bd_t *bd) } #endif #ifdef CONFIG_PCIE3 - p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@b000/bus-range", &len); + p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pcie@b000/bus-range", &len); if (p != NULL) { p[0] = 0; p[1] = pcie3_hose.last_busno - pcie3_hose.first_busno;; diff --git a/board/freescale/mpc8641hpcn/mpc8641hpcn.c b/board/freescale/mpc8641hpcn/mpc8641hpcn.c index ffd11cb5f..931be9f37 100644 --- a/board/freescale/mpc8641hpcn/mpc8641hpcn.c +++ b/board/freescale/mpc8641hpcn/mpc8641hpcn.c @@ -338,6 +338,22 @@ ft_board_setup(void *blob, bd_t *bd) *p++ = cpu_to_be32(bd->bi_memstart); *p = cpu_to_be32(bd->bi_memsize); } +#ifdef CONFIG_PCI1 + p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pcie@8000/bus-range", &len); + if (p != NULL) { + p[0] = 0; + p[1] = pci1_hose.last_busno - pci1_hose.first_busno; + debug("PCI@8000 first_busno=%d last_busno=%d\n",p[0],p[1]); + } +#endif +#ifdef CONFIG_PCI2 + p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pcie@9000/bus-range", &len); + if (p != NULL) { + p[0] = 0; + p[1] = pci2_hose.last_busno - pci2_hose.first_busno; + debug("PCI@9000 first_busno=%d last_busno=%d\n",p[0],p[1]); + } +#endif } #endif From 56a9270521baaa00e12639a978302a67f61ef060 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Thu, 30 Aug 2007 16:18:18 -0500 Subject: [PATCH 210/259] Fix ULI RTC support on MPC8544 DS The RTC on the M1575 ULI chipset requires a dummy read before we are able to talk to the RTC. We accomplish this by adding a second memory region to the PHB the ULI is on and read from it. The second region is added to maintain compatiabilty with Linux's view of the PCI memory map. Signed-off-by: Kumar Gala --- board/freescale/mpc8544ds/init.S | 2 +- board/freescale/mpc8544ds/mpc8544ds.c | 6 ++++++ include/configs/MPC8544DS.h | 3 +++ 3 files changed, 10 insertions(+), 1 deletion(-) diff --git a/board/freescale/mpc8544ds/init.S b/board/freescale/mpc8544ds/init.S index 900c3680c..68ccba746 100644 --- a/board/freescale/mpc8544ds/init.S +++ b/board/freescale/mpc8544ds/init.S @@ -237,6 +237,6 @@ law_entry: /* contains both PCIE3 MEM & IO space */ .long (CFG_PCIE3_MEM_PHYS>>12) & 0xfffff - .long LAWAR_EN | LAWAR_TRGT_PCIE3 | (LAWAR_SIZE & LAWAR_SIZE_2M) + .long LAWAR_EN | LAWAR_TRGT_PCIE3 | (LAWAR_SIZE & LAWAR_SIZE_4M) 4: entry_end diff --git a/board/freescale/mpc8544ds/mpc8544ds.c b/board/freescale/mpc8544ds/mpc8544ds.c index 4c3b27f23..76d909191 100644 --- a/board/freescale/mpc8544ds/mpc8544ds.c +++ b/board/freescale/mpc8544ds/mpc8544ds.c @@ -26,6 +26,7 @@ #include #include #include +#include #include #include @@ -222,6 +223,11 @@ pci_init_board(void) printf (" PCIE3 on bus %02x - %02x\n", hose->first_busno,hose->last_busno); + /* + * Activate ULI1575 legacy chip by performing a fake + * memory access. Needed to make ULI RTC work. + */ + in_be32(CFG_PCIE3_MEM_BASE); } else { printf (" PCIE3: disabled\n"); } diff --git a/include/configs/MPC8544DS.h b/include/configs/MPC8544DS.h index 9743f031e..f580ccade 100644 --- a/include/configs/MPC8544DS.h +++ b/include/configs/MPC8544DS.h @@ -310,6 +310,9 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CFG_PCIE3_IO_BASE 0x00000000 #define CFG_PCIE3_IO_PHYS 0xb0100000 /* reuse mem LAW */ #define CFG_PCIE3_IO_SIZE 0x00100000 /* 1M */ +#define CFG_PCIE3_MEM_BASE2 0xb0200000 +#define CFG_PCIE3_MEM_PHYS2 CFG_PCIE3_MEM_BASE2 +#define CFG_PCIE3_MEM_SIZE2 0x00200000 /* 1M */ #if defined(CONFIG_PCI) From 41bb76e941929f54a73206fb132f7a4c275543a3 Mon Sep 17 00:00:00 2001 From: Grant Likely Date: Thu, 6 Sep 2007 09:46:17 -0600 Subject: [PATCH 211/259] libfdt: add convenience function fdt_find_and_setprop() Given the path to a node, fdt_find_and_setprop() allows a property value to be set directly. Signed-off-by: Grant Likely --- include/libfdt.h | 2 ++ libfdt/fdt_rw.c | 26 ++++++++++++++++++++++++++ 2 files changed, 28 insertions(+) diff --git a/include/libfdt.h b/include/libfdt.h index 340e89d9c..38c65a989 100644 --- a/include/libfdt.h +++ b/include/libfdt.h @@ -140,6 +140,8 @@ int fdt_setprop(void *fdt, int nodeoffset, const char *name, }) #define fdt_setprop_string(fdt, nodeoffset, name, str) \ fdt_setprop((fdt), (nodeoffset), (name), (str), strlen(str)+1) +int fdt_find_and_setprop(void *fdt, const char *node, const char *prop, + const void *val, int len, int create); int fdt_delprop(void *fdt, int nodeoffset, const char *name); int fdt_add_subnode_namelen(void *fdt, int parentoffset, const char *name, int namelen); diff --git a/libfdt/fdt_rw.c b/libfdt/fdt_rw.c index 693bfe43a..55fcc41d1 100644 --- a/libfdt/fdt_rw.c +++ b/libfdt/fdt_rw.c @@ -188,6 +188,32 @@ int fdt_setprop(void *fdt, int nodeoffset, const char *name, return 0; } +/** + * fdt_find_and_setprop: Find a node and set it's property + * + * @fdt: ptr to device tree + * @node: path of node + * @prop: property name + * @val: ptr to new value + * @len: length of new property value + * @create: flag to create the property if it doesn't exist + * + * Convenience function to directly set a property given the path to the node. + */ +int fdt_find_and_setprop(void *fdt, const char *node, const char *prop, + const void *val, int len, int create) +{ + int nodeoff = fdt_find_node_by_path(fdt, node); + + if (nodeoff < 0) + return nodeoff; + + if ((!create) && (fdt_get_property(fdt, nodeoff, prop, 0) == NULL)) + return 0; /* create flag not set; so exit quietly */ + + return fdt_setprop(fdt, nodeoff, prop, val, len); +} + int fdt_delprop(void *fdt, int nodeoffset, const char *name) { struct fdt_property *prop; From cf2817a84c2e9bea2c5dfc084bce2f2d2563ac43 Mon Sep 17 00:00:00 2001 From: Grant Likely Date: Thu, 6 Sep 2007 09:46:23 -0600 Subject: [PATCH 212/259] Migrate 5xxx boards from CONFIG_OF_FLAT_TREE to CONFIG_OF_LIBFDT Affects boards: icecube (lite5200), jupiter, motionpro, tqm5200 Tested on: lite5200b Note: the fixup functions have not been moved to a common place. This patch is targeted for immediate merging as in solves a build issue, but the final name/location of the fixups is still subject to debate. I propose to merge this now, and move the fixups in the next merge window to be usable by all targets. Signed-off-by: Grant Likely --- board/icecube/icecube.c | 7 ++--- board/jupiter/jupiter.c | 8 ++--- board/motionpro/motionpro.c | 8 ++--- board/tqm5200/tqm5200.c | 9 ++---- cpu/mpc5xxx/cpu.c | 60 +++++++++++++++++++++++-------------- include/configs/IceCube.h | 2 +- include/configs/TQM5200.h | 2 +- include/configs/jupiter.h | 2 +- include/configs/motionpro.h | 2 +- 9 files changed, 52 insertions(+), 48 deletions(-) diff --git a/board/icecube/icecube.c b/board/icecube/icecube.c index c027f6f34..07ba2459d 100644 --- a/board/icecube/icecube.c +++ b/board/icecube/icecube.c @@ -28,10 +28,7 @@ #include #include #include - -#if defined(CONFIG_OF_FLAT_TREE) -#include -#endif +#include #if defined(CONFIG_LITE5200B) #include "mt46v32m16.h" @@ -386,7 +383,7 @@ void ide_set_reset (int idereset) } #endif -#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP) +#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) void ft_board_setup(void *blob, bd_t *bd) { diff --git a/board/jupiter/jupiter.c b/board/jupiter/jupiter.c index b2274875e..efdc33349 100644 --- a/board/jupiter/jupiter.c +++ b/board/jupiter/jupiter.c @@ -28,11 +28,7 @@ #include #include #include - -#if defined(CONFIG_OF_FLAT_TREE) -#include -#endif - +#include #define SDRAM_DDR 0 #if 1 @@ -308,7 +304,7 @@ void ide_set_reset (int idereset) } #endif -#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP) +#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) void ft_board_setup(void *blob, bd_t *bd) { diff --git a/board/motionpro/motionpro.c b/board/motionpro/motionpro.c index 6eb5fe9cf..f83998e5a 100644 --- a/board/motionpro/motionpro.c +++ b/board/motionpro/motionpro.c @@ -29,9 +29,7 @@ #include #include #include -#if defined(CONFIG_OF_FLAT_TREE) -#include -#endif +#include #if defined(CONFIG_STATUS_LED) #include @@ -196,12 +194,12 @@ int checkboard(void) } -#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP) +#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) void ft_board_setup(void *blob, bd_t *bd) { ft_cpu_setup(blob, bd); } -#endif /* defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP) */ +#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */ #if defined(CONFIG_STATUS_LED) diff --git a/board/tqm5200/tqm5200.c b/board/tqm5200/tqm5200.c index 51f4aebc0..21f67aa4e 100644 --- a/board/tqm5200/tqm5200.c +++ b/board/tqm5200/tqm5200.c @@ -31,10 +31,7 @@ #include #include #include - -#if defined(CONFIG_OF_FLAT_TREE) -#include -#endif +#include #ifdef CONFIG_VIDEO_SM501 #include @@ -780,9 +777,9 @@ int board_get_height (void) #endif /* CONFIG_VIDEO_SM501 */ -#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP) +#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) void ft_board_setup(void *blob, bd_t *bd) { ft_cpu_setup(blob, bd); } -#endif /* defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP) */ +#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */ diff --git a/cpu/mpc5xxx/cpu.c b/cpu/mpc5xxx/cpu.c index 1eac2bbfb..7f16b92a6 100644 --- a/cpu/mpc5xxx/cpu.c +++ b/cpu/mpc5xxx/cpu.c @@ -29,10 +29,12 @@ #include #include #include +#include #include -#if defined(CONFIG_OF_FLAT_TREE) -#include +#if defined(CONFIG_OF_LIBFDT) +#include +#include #endif DECLARE_GLOBAL_DATA_PTR; @@ -111,29 +113,43 @@ unsigned long get_tbclk (void) /* ------------------------------------------------------------------------- */ -#ifdef CONFIG_OF_FLAT_TREE -void -ft_cpu_setup(void *blob, bd_t *bd) +#ifdef CONFIG_OF_LIBFDT +static void do_fixup(void *fdt, const char *node, const char *prop, + const void *val, int len, int create) { - u32 *p; - int len; +#if defined(DEBUG) + int i; + debug("Updating property '%s/%s' = ", node, prop); + for (i = 0; i < len; i++) + debug(" %.2x", *(u8*)(val+i)); + debug("\n"); +#endif + int rc = fdt_find_and_setprop(fdt, node, prop, val, len, create); + if (rc) + printf("Unable to update property %s:%s, err=%s\n", + node, prop, fdt_strerror(rc)); +} - /* Core XLB bus frequency */ - p = ft_get_prop(blob, "/cpus/" OF_CPU "/bus-frequency", &len); - if (p != NULL) - *p = cpu_to_be32(bd->bi_busfreq); +static void do_fixup_u32(void *fdt, const char *node, const char *prop, + u32 val, int create) +{ + val = cpu_to_fdt32(val); + do_fixup(fdt, node, prop, &val, sizeof(val), create); +} - /* SOC peripherals use the IPB bus frequency */ - p = ft_get_prop(blob, "/" OF_SOC "/bus-frequency", &len); - if (p != NULL) - *p = cpu_to_be32(bd->bi_ipbfreq); +void ft_cpu_setup(void *blob, bd_t *bd) +{ + int div = in_8((void*)CFG_MBAR + 0x204) & 0x0020 ? 8 : 4; + char * cpu_path = "/cpus/" OF_CPU; + char * eth_path = "/" OF_SOC "/ethernet@3000"; - p = ft_get_prop(blob, "/" OF_SOC "/ethernet@3000/mac-address", &len); - if (p != NULL) - memcpy(p, bd->bi_enetaddr, 6); - - p = ft_get_prop(blob, "/" OF_SOC "/ethernet@3000/local-mac-address", &len); - if (p != NULL) - memcpy(p, bd->bi_enetaddr, 6); + do_fixup_u32(blob, cpu_path, "timebase-frequency", OF_TBCLK, 1); + do_fixup_u32(blob, cpu_path, "bus-frequency", bd->bi_busfreq, 1); + do_fixup_u32(blob, cpu_path, "clock-frequency", bd->bi_intfreq, 1); + do_fixup_u32(blob, "/" OF_SOC, "bus-frequency", bd->bi_ipbfreq, 1); + do_fixup_u32(blob, "/" OF_SOC, "system-frequency", + bd->bi_busfreq*div, 1); + do_fixup(blob, eth_path, "mac-address", bd->bi_enetaddr, 6, 0); + do_fixup(blob, eth_path, "local-mac-address", bd->bi_enetaddr, 6, 0); } #endif diff --git a/include/configs/IceCube.h b/include/configs/IceCube.h index bdd92bae3..4c16d2295 100644 --- a/include/configs/IceCube.h +++ b/include/configs/IceCube.h @@ -178,7 +178,7 @@ #endif /* CONFIG_MPC5200 */ /* pass open firmware flat tree */ -#define CONFIG_OF_FLAT_TREE 1 +#define CONFIG_OF_LIBFDT 1 #define CONFIG_OF_BOARD_SETUP 1 #define OF_CPU "PowerPC,5200@0" diff --git a/include/configs/TQM5200.h b/include/configs/TQM5200.h index c08173b07..e0c9d81be 100644 --- a/include/configs/TQM5200.h +++ b/include/configs/TQM5200.h @@ -701,7 +701,7 @@ * Open firmware flat tree support *----------------------------------------------------------------------- */ -#define CONFIG_OF_FLAT_TREE 1 +#define CONFIG_OF_LIBFDT 1 #define CONFIG_OF_BOARD_SETUP 1 #define OF_CPU "PowerPC,5200@0" diff --git a/include/configs/jupiter.h b/include/configs/jupiter.h index 4070ab971..b7100e986 100644 --- a/include/configs/jupiter.h +++ b/include/configs/jupiter.h @@ -145,7 +145,7 @@ #if 0 /* pass open firmware flat tree */ -#define CONFIG_OF_FLAT_TREE 1 +#define CONFIG_OF_LIBFDT 1 #define CONFIG_OF_BOARD_SETUP 1 #define OF_CPU "PowerPC,5200@0" diff --git a/include/configs/motionpro.h b/include/configs/motionpro.h index 82827c692..9a2163216 100644 --- a/include/configs/motionpro.h +++ b/include/configs/motionpro.h @@ -417,7 +417,7 @@ extern void __led_set(led_id_t id, int state); #define CFG_RESET_ADDRESS 0xfff00100 /* pass open firmware flat tree */ -#define CONFIG_OF_FLAT_TREE 1 +#define CONFIG_OF_LIBFDT 1 #define CONFIG_OF_BOARD_SETUP 1 #define OF_CPU "PowerPC,5200@0" From e79021223bc339df655e360645a52c457a74b067 Mon Sep 17 00:00:00 2001 From: Grant Likely Date: Thu, 6 Sep 2007 09:47:40 -0600 Subject: [PATCH 213/259] bootm/fdt: Only process the fdt if an fdt address was provided Boards with CONFIG_OF_LIBFDT enabled are not able to boot old-style kernels using the board info structure (instead of passing a device tree) This change allows the old style booting to be used if the fdt argument was not passed to 'bootm'. Signed-off-by: Grant Likely Acked-by: Kim Phillips --- common/cmd_bootm.c | 36 +++++++++++++++++++----------------- 1 file changed, 19 insertions(+), 17 deletions(-) diff --git a/common/cmd_bootm.c b/common/cmd_bootm.c index bcb927fd1..919188f67 100644 --- a/common/cmd_bootm.c +++ b/common/cmd_bootm.c @@ -962,29 +962,31 @@ do_bootm_linux (cmd_tbl_t *cmdtp, int flag, * Add the chosen node if it doesn't exist, add the env and bd_t * if the user wants it (the logic is in the subroutines). */ - if (fdt_chosen(of_flat_tree, initrd_start, initrd_end, 0) < 0) { - puts ("ERROR: /chosen node create failed - " - "must RESET the board to recover.\n"); - do_reset (cmdtp, flag, argc, argv); - } + if (of_flat_tree) { + if (fdt_chosen(of_flat_tree, initrd_start, initrd_end, 0) < 0) { + puts ("ERROR: /chosen node create failed - " + "must RESET the board to recover.\n"); + do_reset (cmdtp, flag, argc, argv); + } #ifdef CONFIG_OF_HAS_UBOOT_ENV - if (fdt_env(of_flat_tree) < 0) { - puts ("ERROR: /u-boot-env node create failed - " - "must RESET the board to recover.\n"); - do_reset (cmdtp, flag, argc, argv); - } + if (fdt_env(of_flat_tree) < 0) { + puts ("ERROR: /u-boot-env node create failed - " + "must RESET the board to recover.\n"); + do_reset (cmdtp, flag, argc, argv); + } #endif #ifdef CONFIG_OF_HAS_BD_T - if (fdt_bd_t(of_flat_tree) < 0) { - puts ("ERROR: /bd_t node create failed - " - "must RESET the board to recover.\n"); - do_reset (cmdtp, flag, argc, argv); - } + if (fdt_bd_t(of_flat_tree) < 0) { + puts ("ERROR: /bd_t node create failed - " + "must RESET the board to recover.\n"); + do_reset (cmdtp, flag, argc, argv); + } #endif #ifdef CONFIG_OF_BOARD_SETUP - /* Call the board-specific fixup routine */ - ft_board_setup(of_flat_tree, gd->bd); + /* Call the board-specific fixup routine */ + ft_board_setup(of_flat_tree, gd->bd); #endif + } #endif /* CONFIG_OF_LIBFDT */ #if defined(CONFIG_OF_FLAT_TREE) #ifdef CFG_BOOTMAPSZ From 041a2554ad619e80dce520c1a33210affcb6a3f2 Mon Sep 17 00:00:00 2001 From: Gary Jennejohn Date: Fri, 31 Aug 2007 14:29:04 +0200 Subject: [PATCH 214/259] Add support for Sil680 IDE controller. o add drivers/sil680.c to support the Sil680 IDE-controller. o drivers/Makefile: add sil680.o. Signed-off-by: Gary Jennejohn --- drivers/Makefile | 2 +- drivers/sil680.c | 110 +++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 111 insertions(+), 1 deletion(-) create mode 100644 drivers/sil680.c diff --git a/drivers/Makefile b/drivers/Makefile index 3ee6312e9..6bf05ccad 100755 --- a/drivers/Makefile +++ b/drivers/Makefile @@ -43,7 +43,7 @@ COBJS = 3c589.o 5701rls.o ali512x.o at45.o ata_piix.o atmel_usart.o \ sed13806.o sed156x.o \ serial.o serial_max3100.o \ serial_pl010.o serial_pl011.o serial_xuartlite.o \ - sl811_usb.o sm501.o smc91111.o smiLynxEM.o \ + sil680.o sl811_usb.o sm501.o smc91111.o smiLynxEM.o \ status_led.o sym53c8xx.o systemace.o ahci.o \ ti_pci1410a.o tigon3.o tsec.o \ tsi108_eth.o tsi108_i2c.o tsi108_pci.o \ diff --git a/drivers/sil680.c b/drivers/sil680.c new file mode 100644 index 000000000..a6143df4c --- /dev/null +++ b/drivers/sil680.c @@ -0,0 +1,110 @@ +/* + * (C) Copyright 2007 + * Gary Jennejohn, DENX Software Engineering, garyj@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ +/* sil680.c - ide support functions for the Sil0680A controller */ + +/* + * The following parameters must be defined in the configuration file + * of the target board: + * + * #define CFG_IDE_SIL680 + * + * #define CONFIG_PCI_PNP + * NOTE it may also be necessary to define this if the default of 8 is + * incorrect for the target board (e.g. the sequoia board requires 0). + * #define CFG_PCI_CACHE_LINE_SIZE 0 + * + * #define CONFIG_CMD_IDE + * #undef CONFIG_IDE_8xx_DIRECT + * #undef CONFIG_IDE_LED + * #undef CONFIG_IDE_RESET + * #define CONFIG_IDE_PREINIT + * #define CFG_IDE_MAXBUS 2 - modify to suit + * #define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*2) - modify to suit + * #define CFG_ATA_BASE_ADDR 0 + * #define CFG_ATA_IDE0_OFFSET 0 + * #define CFG_ATA_IDE1_OFFSET 0 + * #define CFG_ATA_DATA_OFFSET 0 + * #define CFG_ATA_REG_OFFSET 0 + * #define CFG_ATA_ALT_OFFSET 0x0004 + * + * The mapping for PCI IO-space. + * NOTE this is the value for the sequoia board. Modify to suit. + * #define CFG_PCI0_IO_SPACE 0xE8000000 + */ + +#include +#if defined(CFG_IDE_SIL680) +#include +#include +#include + +extern ulong ide_bus_offset[CFG_IDE_MAXBUS]; + +int ide_preinit (void) +{ + int status; + pci_dev_t devbusfn; + int l; + + status = 1; + for (l = 0; l < CFG_IDE_MAXBUS; l++) { + ide_bus_offset[l] = -ATA_STATUS; + } + devbusfn = pci_find_device (0x1095, 0x0680, 0); + if (devbusfn != -1) { + status = 0; + + pci_read_config_dword (devbusfn, PCI_BASE_ADDRESS_0, + (u32 *) &ide_bus_offset[0]); + ide_bus_offset[0] &= 0xfffffff8; + ide_bus_offset[0] += CFG_PCI0_IO_SPACE; + pci_read_config_dword (devbusfn, PCI_BASE_ADDRESS_2, + (u32 *) &ide_bus_offset[1]); + ide_bus_offset[1] &= 0xfffffff8; + ide_bus_offset[1] += CFG_PCI0_IO_SPACE; + /* init various things - taken from the Linux driver */ + /* set PIO mode */ + pci_write_config_byte(devbusfn, 0x80, 0x00); + pci_write_config_byte(devbusfn, 0x84, 0x00); + /* IDE0 */ + pci_write_config_byte(devbusfn, 0xA1, 0x02); + pci_write_config_word(devbusfn, 0xA2, 0x328A); + pci_write_config_dword(devbusfn, 0xA4, 0x62DD62DD); + pci_write_config_dword(devbusfn, 0xA8, 0x43924392); + pci_write_config_dword(devbusfn, 0xAC, 0x40094009); + /* IDE1 */ + pci_write_config_byte(devbusfn, 0xB1, 0x02); + pci_write_config_word(devbusfn, 0xB2, 0x328A); + pci_write_config_dword(devbusfn, 0xB4, 0x62DD62DD); + pci_write_config_dword(devbusfn, 0xB8, 0x43924392); + pci_write_config_dword(devbusfn, 0xBC, 0x40094009); + } + return (status); +} + +void ide_set_reset (int flag) { + return; +} + +#endif /* CFG_IDE_SIL680 */ From 5b729fb3bd98f49855d6bfc657c3fbae95f2adc2 Mon Sep 17 00:00:00 2001 From: Bartlomiej Sieka Date: Tue, 4 Sep 2007 17:31:22 +0200 Subject: [PATCH 215/259] Fix do_bootm_linux() so that multi-file images with FDT blob boot. Fix incorrect blob address calculation in do_bootm_linux() that prevents booting the kernel from a multi-file image (kernel + initrd + blob). Also, make minor updates to the U-Boot's output and to the coding style. Signed-off-by: Bartlomiej Sieka --- common/cmd_bootm.c | 29 +++++++++++++++++++---------- 1 file changed, 19 insertions(+), 10 deletions(-) diff --git a/common/cmd_bootm.c b/common/cmd_bootm.c index 919188f67..9f5e0b4ee 100644 --- a/common/cmd_bootm.c +++ b/common/cmd_bootm.c @@ -817,27 +817,32 @@ do_bootm_linux (cmd_tbl_t *cmdtp, int flag, int i; /* skip kernel length, initrd length, and terminator */ - of_data = (ulong)(&len_ptr[3]); + of_flat_tree = (char *)(&len_ptr[3]); /* skip any additional image length fields */ for (i=2; len_ptr[i]; ++i) - of_data += 4; + of_flat_tree += 4; /* add kernel length, and align */ - of_data += ntohl(len_ptr[0]); + of_flat_tree += ntohl(len_ptr[0]); if (tail) { - of_data += 4 - tail; + of_flat_tree += 4 - tail; } /* add initrd length, and align */ tail = ntohl(len_ptr[1]) % 4; - of_data += ntohl(len_ptr[1]); + of_flat_tree += ntohl(len_ptr[1]); if (tail) { - of_data += 4 - tail; + of_flat_tree += 4 - tail; } + /* move the blob if it is in flash (set of_data to !null) */ + if (addr2info ((ulong)of_flat_tree) != NULL) + of_data = (ulong)of_flat_tree; + + #if defined(CONFIG_OF_FLAT_TREE) - if (*((ulong *)(of_flat_tree + sizeof(image_header_t))) != OF_DT_HEADER) { + if (*((ulong *)(of_flat_tree)) != OF_DT_HEADER) { #else - if (fdt_check_header(of_flat_tree + sizeof(image_header_t)) != 0) { + if (fdt_check_header (of_flat_tree) != 0) { #endif puts ("ERROR: image is not a fdt - " "must RESET the board to recover.\n"); @@ -845,9 +850,11 @@ do_bootm_linux (cmd_tbl_t *cmdtp, int flag, } #if defined(CONFIG_OF_FLAT_TREE) - if (((struct boot_param_header *)of_data)->totalsize != ntohl(len_ptr[2])) { + if (((struct boot_param_header *)of_flat_tree)->totalsize != + ntohl (len_ptr[2])) { #else - if (be32_to_cpu(fdt_totalsize(of_data)) != ntohl(len_ptr[2])) { + if (be32_to_cpu (fdt_totalsize (of_flat_tree)) != + ntohl(len_ptr[2])) { #endif puts ("ERROR: fdt size != image size - " "must RESET the board to recover.\n"); @@ -957,6 +964,7 @@ do_bootm_linux (cmd_tbl_t *cmdtp, int flag, "must RESET the board to recover.\n"); do_reset (cmdtp, flag, argc, argv); } + puts ("OK\n"); } /* * Add the chosen node if it doesn't exist, add the env and bd_t @@ -1013,6 +1021,7 @@ do_bootm_linux (cmd_tbl_t *cmdtp, int flag, printf (" Loading Device Tree to %08lx, end %08lx ... ", of_start, of_start + of_len - 1); memmove ((void *)of_start, (void *)of_data, of_len); + puts ("OK\n"); } /* * Create the /chosen node and modify the blob with board specific From 8ea2c4e54833deaebc24c3ca6b7f21353c25b0f5 Mon Sep 17 00:00:00 2001 From: Shinya Kuribayashi Date: Fri, 31 Aug 2007 14:41:45 +0900 Subject: [PATCH 216/259] [MIPS] Update asm string header This patches contains several bugfixes and cleanups in the latest upstream: - Don't include linux/config.h - Remove buggy inline version of memscan. - Merge with Linux 2.6.11-rc3. - Fix undefined reference to strcpy in binfmt_misc caused by gcc 3.4. - Goodbye mips64. 31704 lines of code bite the dust. - Replace extern inline with static inline. - Fix return value of strncpy. - Remove a bunch more "$1" clobbers. Signed-off-by: Shinya Kuribayashi --- include/asm-mips/string.h | 68 ++++++++++++++++----------------------- 1 file changed, 27 insertions(+), 41 deletions(-) diff --git a/include/asm-mips/string.h b/include/asm-mips/string.h index 463a111b4..3f7c55e55 100644 --- a/include/asm-mips/string.h +++ b/include/asm-mips/string.h @@ -1,18 +1,26 @@ -/* $Id: string.h,v 1.13 2000/02/19 14:12:14 harald Exp $ - * +/* * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (c) 1994, 1995, 1996, 1997, 1998 by Ralf Baechle + * Copyright (c) 1994, 95, 96, 97, 98, 2000, 01 Ralf Baechle + * Copyright (c) 2000 by Silicon Graphics, Inc. + * Copyright (c) 2001 MIPS Technologies, Inc. */ -#ifndef __ASM_MIPS_STRING_H -#define __ASM_MIPS_STRING_H +#ifndef _ASM_STRING_H +#define _ASM_STRING_H -#include + +/* + * Most of the inline functions are rather naive implementations so I just + * didn't bother updating them for 64-bit ... + */ +#ifdef CONFIG_32BIT + +#ifndef IN_STRING_C #define __HAVE_ARCH_STRCPY -extern __inline__ char *strcpy(char *__dest, __const__ char *__src) +static __inline__ char *strcpy(char *__dest, __const__ char *__src) { char *__xdest = __dest; @@ -28,13 +36,13 @@ extern __inline__ char *strcpy(char *__dest, __const__ char *__src) ".set\treorder" : "=r" (__dest), "=r" (__src) : "0" (__dest), "1" (__src) - : "$1","memory"); + : "memory"); return __xdest; } #define __HAVE_ARCH_STRNCPY -extern __inline__ char *strncpy(char *__dest, __const__ char *__src, size_t __n) +static __inline__ char *strncpy(char *__dest, __const__ char *__src, size_t __n) { char *__xdest = __dest; @@ -56,13 +64,13 @@ extern __inline__ char *strncpy(char *__dest, __const__ char *__src, size_t __n) ".set\treorder" : "=r" (__dest), "=r" (__src), "=r" (__n) : "0" (__dest), "1" (__src), "2" (__n) - : "$1","memory"); + : "memory"); - return __dest; + return __xdest; } #define __HAVE_ARCH_STRCMP -extern __inline__ int strcmp(__const__ char *__cs, __const__ char *__ct) +static __inline__ int strcmp(__const__ char *__cs, __const__ char *__ct) { int __res; @@ -84,14 +92,15 @@ extern __inline__ int strcmp(__const__ char *__cs, __const__ char *__ct) "3:\t.set\tat\n\t" ".set\treorder" : "=r" (__cs), "=r" (__ct), "=r" (__res) - : "0" (__cs), "1" (__ct) - : "$1"); + : "0" (__cs), "1" (__ct)); return __res; } +#endif /* !defined(IN_STRING_C) */ + #define __HAVE_ARCH_STRNCMP -extern __inline__ int +static __inline__ int strncmp(__const__ char *__cs, __const__ char *__ct, size_t __count) { int __res; @@ -116,11 +125,11 @@ strncmp(__const__ char *__cs, __const__ char *__ct, size_t __count) ".set\tat\n\t" ".set\treorder" : "=r" (__cs), "=r" (__ct), "=r" (__count), "=r" (__res) - : "0" (__cs), "1" (__ct), "2" (__count) - : "$1"); + : "0" (__cs), "1" (__ct), "2" (__count)); return __res; } +#endif /* CONFIG_32BIT */ #undef __HAVE_ARCH_MEMSET extern void *memset(void *__s, int __c, size_t __count); @@ -131,27 +140,4 @@ extern void *memcpy(void *__to, __const__ void *__from, size_t __n); #undef __HAVE_ARCH_MEMMOVE extern void *memmove(void *__dest, __const__ void *__src, size_t __n); -/* Don't build bcopy at all ... */ -#define __HAVE_ARCH_BCOPY - -#define __HAVE_ARCH_MEMSCAN -extern __inline__ void *memscan(void *__addr, int __c, size_t __size) -{ - char *__end = (char *)__addr + __size; - - __asm__(".set\tpush\n\t" - ".set\tnoat\n\t" - ".set\treorder\n\t" - "1:\tbeq\t%0,%1,2f\n\t" - "addiu\t%0,1\n\t" - "lb\t$1,-1(%0)\n\t" - "bne\t$1,%4,1b\n" - "2:\t.set\tpop" - : "=r" (__addr), "=r" (__end) - : "0" (__addr), "1" (__end), "r" (__c) - : "$1"); - - return __addr; -} - -#endif /* __ASM_MIPS_STRING_H */ +#endif /* _ASM_STRING_H */ From b4d8a55145442f136982634862341a3e02002bda Mon Sep 17 00:00:00 2001 From: Shinya Kuribayashi Date: Fri, 31 Aug 2007 14:41:51 +0900 Subject: [PATCH 217/259] [MIPS] Remove inline asm string functions Stop using inline string functions on MIPS as other ARCHs do so, since the optimized inline asm versions are not small. This change is triggered by a following MIPS build error: common/libcommon.a(exports.o)(.text+0xdc): In function `jumptable_init': common/exports.c:32: undefined reference to `strcmp' make: *** [u-boot] Error 1 Signed-off-by: Shinya Kuribayashi --- include/asm-mips/string.h | 124 +++----------------------------------- 1 file changed, 10 insertions(+), 114 deletions(-) diff --git a/include/asm-mips/string.h b/include/asm-mips/string.h index 3f7c55e55..c42ad82c4 100644 --- a/include/asm-mips/string.h +++ b/include/asm-mips/string.h @@ -10,126 +10,22 @@ #ifndef _ASM_STRING_H #define _ASM_STRING_H - /* - * Most of the inline functions are rather naive implementations so I just - * didn't bother updating them for 64-bit ... + * We don't do inline string functions, since the + * optimised inline asm versions are not small. */ -#ifdef CONFIG_32BIT -#ifndef IN_STRING_C +#undef __HAVE_ARCH_STRCPY +extern char *strcpy(char *__dest, __const__ char *__src); -#define __HAVE_ARCH_STRCPY -static __inline__ char *strcpy(char *__dest, __const__ char *__src) -{ - char *__xdest = __dest; +#undef __HAVE_ARCH_STRNCPY +extern char *strncpy(char *__dest, __const__ char *__src, size_t __n); - __asm__ __volatile__( - ".set\tnoreorder\n\t" - ".set\tnoat\n" - "1:\tlbu\t$1,(%1)\n\t" - "addiu\t%1,1\n\t" - "sb\t$1,(%0)\n\t" - "bnez\t$1,1b\n\t" - "addiu\t%0,1\n\t" - ".set\tat\n\t" - ".set\treorder" - : "=r" (__dest), "=r" (__src) - : "0" (__dest), "1" (__src) - : "memory"); +#undef __HAVE_ARCH_STRCMP +extern int strcmp(__const__ char *__cs, __const__ char *__ct); - return __xdest; -} - -#define __HAVE_ARCH_STRNCPY -static __inline__ char *strncpy(char *__dest, __const__ char *__src, size_t __n) -{ - char *__xdest = __dest; - - if (__n == 0) - return __xdest; - - __asm__ __volatile__( - ".set\tnoreorder\n\t" - ".set\tnoat\n" - "1:\tlbu\t$1,(%1)\n\t" - "subu\t%2,1\n\t" - "sb\t$1,(%0)\n\t" - "beqz\t$1,2f\n\t" - "addiu\t%0,1\n\t" - "bnez\t%2,1b\n\t" - "addiu\t%1,1\n" - "2:\n\t" - ".set\tat\n\t" - ".set\treorder" - : "=r" (__dest), "=r" (__src), "=r" (__n) - : "0" (__dest), "1" (__src), "2" (__n) - : "memory"); - - return __xdest; -} - -#define __HAVE_ARCH_STRCMP -static __inline__ int strcmp(__const__ char *__cs, __const__ char *__ct) -{ - int __res; - - __asm__ __volatile__( - ".set\tnoreorder\n\t" - ".set\tnoat\n\t" - "lbu\t%2,(%0)\n" - "1:\tlbu\t$1,(%1)\n\t" - "addiu\t%0,1\n\t" - "bne\t$1,%2,2f\n\t" - "addiu\t%1,1\n\t" - "bnez\t%2,1b\n\t" - "lbu\t%2,(%0)\n\t" -#if defined(CONFIG_CPU_R3000) - "nop\n\t" -#endif - "move\t%2,$1\n" - "2:\tsubu\t%2,$1\n" - "3:\t.set\tat\n\t" - ".set\treorder" - : "=r" (__cs), "=r" (__ct), "=r" (__res) - : "0" (__cs), "1" (__ct)); - - return __res; -} - -#endif /* !defined(IN_STRING_C) */ - -#define __HAVE_ARCH_STRNCMP -static __inline__ int -strncmp(__const__ char *__cs, __const__ char *__ct, size_t __count) -{ - int __res; - - __asm__ __volatile__( - ".set\tnoreorder\n\t" - ".set\tnoat\n" - "1:\tlbu\t%3,(%0)\n\t" - "beqz\t%2,2f\n\t" - "lbu\t$1,(%1)\n\t" - "subu\t%2,1\n\t" - "bne\t$1,%3,3f\n\t" - "addiu\t%0,1\n\t" - "bnez\t%3,1b\n\t" - "addiu\t%1,1\n" - "2:\n\t" -#if defined(CONFIG_CPU_R3000) - "nop\n\t" -#endif - "move\t%3,$1\n" - "3:\tsubu\t%3,$1\n\t" - ".set\tat\n\t" - ".set\treorder" - : "=r" (__cs), "=r" (__ct), "=r" (__count), "=r" (__res) - : "0" (__cs), "1" (__ct), "2" (__count)); - - return __res; -} -#endif /* CONFIG_32BIT */ +#undef __HAVE_ARCH_STRNCMP +extern int strncmp(__const__ char *__cs, __const__ char *__ct, size_t __count); #undef __HAVE_ARCH_MEMSET extern void *memset(void *__s, int __c, size_t __count); From 1d2ca446e1a731df420206d04fe278c27ea6b8e8 Mon Sep 17 00:00:00 2001 From: Jason Jin Date: Thu, 30 Aug 2007 18:19:05 +0800 Subject: [PATCH 218/259] Add BUILD_DIR support for bios emulator. Signed-off-by: Jason Jin --- drivers/bios_emulator/Makefile | 23 +++++++++++++++-------- 1 file changed, 15 insertions(+), 8 deletions(-) diff --git a/drivers/bios_emulator/Makefile b/drivers/bios_emulator/Makefile index 586e83be8..90c64dad6 100644 --- a/drivers/bios_emulator/Makefile +++ b/drivers/bios_emulator/Makefile @@ -2,9 +2,11 @@ include $(TOPDIR)/config.mk LIB := $(obj)libatibiosemu.a -X86DIR = ./x86emu +X86DIR = x86emu -OBJS = atibios.o biosemu.o besys.o bios.o \ +$(shell mkdir -p $(obj)$(X86DIR)) + +COBJS = atibios.o biosemu.o besys.o bios.o \ $(X86DIR)/decode.o \ $(X86DIR)/ops2.o \ $(X86DIR)/ops.o \ @@ -12,19 +14,24 @@ OBJS = atibios.o biosemu.o besys.o bios.o \ $(X86DIR)/sys.o \ $(X86DIR)/debug.o -CFLAGS += -I. -I./include -I$(X86DIR) -I$(TOPDIR)/include \ +SRCS := $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) + +EXTRA_CFLAGS += -I. -I./include -I$(TOPDIR)/include \ -D__PPC__ -D__BIG_ENDIAN__ +CFLAGS += $(EXTRA_CFLAGS) +HOST_CFLAGS += $(EXTRA_CFLAGS) + all: $(LIB) -$(LIB): $(OBJS) - $(AR) crv $@ $(OBJS) +$(LIB): $(obj).depend $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) ######################################################################### -.depend: Makefile $(OBJS:.o=.c) - $(CC) -M $(CFLAGS) $(OBJS:.o=.c) > $@ +include $(SRCTREE)/rules.mk -sinclude .depend +sinclude $(obj).depend ######################################################################### From 28bb3f72c687ac6b2eb076b01dd21a5fd657d45e Mon Sep 17 00:00:00 2001 From: stefano babic Date: Thu, 30 Aug 2007 22:48:47 +0200 Subject: [PATCH 219/259] PXA270: fix compile issue (invalid lvalue) Code is broken for PXA270 due to "invalid lvalue in assignment". This patch fix it in pxa-regs.h Signed-off-by: Stefano Babic --- include/asm-arm/arch-pxa/pxa-regs.h | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/include/asm-arm/arch-pxa/pxa-regs.h b/include/asm-arm/arch-pxa/pxa-regs.h index e8cb29903..9b4da3ae9 100644 --- a/include/asm-arm/arch-pxa/pxa-regs.h +++ b/include/asm-arm/arch-pxa/pxa-regs.h @@ -1288,15 +1288,15 @@ typedef void (*ExcpHndlr) (void) ; #define _GEDR(x) __REG2(0x40E00048, ((x) & 0x60) >> 3) #define _GAFR(x) __REG2(0x40E00054, ((x) & 0x70) >> 2) -#define GPLR(x) ((((x) & 0x7f) < 96) ? _GPLR(x) : GPLR3) -#define GPDR(x) ((((x) & 0x7f) < 96) ? _GPDR(x) : GPDR3) -#define GPSR(x) ((((x) & 0x7f) < 96) ? _GPSR(x) : GPSR3) -#define GPCR(x) ((((x) & 0x7f) < 96) ? _GPCR(x) : GPCR3) -#define GRER(x) ((((x) & 0x7f) < 96) ? _GRER(x) : GRER3) -#define GFER(x) ((((x) & 0x7f) < 96) ? _GFER(x) : GFER3) -#define GEDR(x) ((((x) & 0x7f) < 96) ? _GEDR(x) : GEDR3) -#define GAFR(x) ((((x) & 0x7f) < 96) ? _GAFR(x) : \ - ((((x) & 0x7f) < 112) ? GAFR3_L : GAFR3_U)) +#define GPLR(x) __REG2(0x40E00000 + (((x) & 0x7f) < 96) ? 0:0x100, ((x) & 0x60) >> 3) +#define GPDR(x) __REG2(0x40E0000C + (((x) & 0x7f) < 96) ? 0:0x100, ((x) & 0x60) >> 3) +#define GPSR(x) __REG2(0x40E00018 + (((x) & 0x7f) < 96) ? 0:0x100, ((x) & 0x60) >> 3) +#define GPCR(x) __REG2(0x40E00024 + (((x) & 0x7f) < 96) ? 0:0x100, ((x) & 0x60) >> 3) +#define GRER(x) __REG2(0x40E00030 + (((x) & 0x7f) < 96) ? 0:0x100, ((x) & 0x60) >> 3) +#define GFER(x) __REG2(0x40E0003C + (((x) & 0x7f) < 96) ? 0:0x100, ((x) & 0x60) >> 3) +#define GEDR(x) __REG2(0x40E00048 + (((x) & 0x7f) < 96) ? 0:0x100, ((x) & 0x60) >> 3) +#define GAFR(x) __REG2((((x) & 0x7f) < 96) ? 0x40E00054 : \ + ((((x) & 0x7f) < 112) ? 0x40E0006C : 0x40E00070),((x) & 0x60) >> 3) #else #define GPLR(x) __REG2(0x40E00000, ((x) & 0x60) >> 3) From 80172c6181c912fbb34ea3ba0c22b232b419b47f Mon Sep 17 00:00:00 2001 From: stefano babic Date: Thu, 30 Aug 2007 22:57:04 +0200 Subject: [PATCH 220/259] PXA270: Add support for multiple serial ports. This patch adds support for multiple serial ports to the PXA target. FFUART, BTUART and STUART are supported. Signed-off-by: Stefano Babic --- common/serial.c | 13 +- cpu/pxa/serial.c | 345 ++++++++++++++++++++++++++++++++++++----------- include/serial.h | 4 + lib_arm/board.c | 4 + 4 files changed, 285 insertions(+), 81 deletions(-) diff --git a/common/serial.c b/common/serial.c index 13e9f30e4..dee1cc0ab 100644 --- a/common/serial.c +++ b/common/serial.c @@ -32,7 +32,7 @@ DECLARE_GLOBAL_DATA_PTR; static struct serial_device *serial_devices = NULL; static struct serial_device *serial_current = NULL; -#ifndef CONFIG_LWMON +#if !defined(CONFIG_LWMON) && !defined(CONFIG_PXA27X) struct serial_device *default_serial_console (void) { #if defined(CONFIG_8xx_CONS_SMC1) || defined(CONFIG_8xx_CONS_SMC2) @@ -65,7 +65,7 @@ struct serial_device *default_serial_console (void) } #endif -static int serial_register (struct serial_device *dev) +int serial_register (struct serial_device *dev) { dev->init += gd->reloc_off; dev->setbrg += gd->reloc_off; @@ -110,6 +110,15 @@ void serial_initialize (void) serial_register(&eserial4_device); #endif #endif /* CFG_NS16550_SERIAL */ +#if defined (CONFIG_FFUART) + serial_register(&serial_ffuart_device); +#endif +#if defined (CONFIG_BTUART) + serial_register(&serial_btuart_device); +#endif +#if defined (CONFIG_STUART) + serial_register(&serial_stuart_device); +#endif serial_assign (default_serial_console ()->name); } diff --git a/cpu/pxa/serial.c b/cpu/pxa/serial.c index cb3a47899..51e7f6588 100644 --- a/cpu/pxa/serial.c +++ b/cpu/pxa/serial.c @@ -30,11 +30,28 @@ #include #include +#include #include DECLARE_GLOBAL_DATA_PTR; -void serial_setbrg (void) +#define FFUART 0 +#define BTUART 1 +#define STUART 2 + +#ifndef CONFIG_SERIAL_MULTI +#if defined (CONFIG_FFUART) +#define UART_INDEX FFUART +#elif defined (CONFIG_BTUART) +#define UART_INDEX BTUART +#elif defined (CONFIG_STUART) +#define UART_INDEX STUART +#else +#error "Bad: you didn't configure serial ..." +#endif +#endif + +void pxa_setbrg_dev (unsigned int uart_index) { unsigned int quot = 0; @@ -53,63 +70,68 @@ void serial_setbrg (void) else hang (); -#ifdef CONFIG_FFUART + switch (uart_index) { + case FFUART: #ifdef CONFIG_CPU_MONAHANS - CKENA |= CKENA_22_FFUART; + CKENA |= CKENA_22_FFUART; #else - CKEN |= CKEN6_FFUART; + CKEN |= CKEN6_FFUART; #endif /* CONFIG_CPU_MONAHANS */ - FFIER = 0; /* Disable for now */ - FFFCR = 0; /* No fifos enabled */ + FFIER = 0; /* Disable for now */ + FFFCR = 0; /* No fifos enabled */ - /* set baud rate */ - FFLCR = LCR_WLS0 | LCR_WLS1 | LCR_DLAB; - FFDLL = quot & 0xff; - FFDLH = quot >> 8; - FFLCR = LCR_WLS0 | LCR_WLS1; + /* set baud rate */ + FFLCR = LCR_WLS0 | LCR_WLS1 | LCR_DLAB; + FFDLL = quot & 0xff; + FFDLH = quot >> 8; + FFLCR = LCR_WLS0 | LCR_WLS1; - FFIER = IER_UUE; /* Enable FFUART */ + FFIER = IER_UUE; /* Enable FFUART */ + break; -#elif defined(CONFIG_BTUART) + case BTUART: #ifdef CONFIG_CPU_MONAHANS - CKENA |= CKENA_21_BTUART; + CKENA |= CKENA_21_BTUART; #else - CKEN |= CKEN7_BTUART; + CKEN |= CKEN7_BTUART; #endif /* CONFIG_CPU_MONAHANS */ - BTIER = 0; - BTFCR = 0; + BTIER = 0; + BTFCR = 0; - /* set baud rate */ - BTLCR = LCR_DLAB; - BTDLL = quot & 0xff; - BTDLH = quot >> 8; - BTLCR = LCR_WLS0 | LCR_WLS1; + /* set baud rate */ + BTLCR = LCR_DLAB; + BTDLL = quot & 0xff; + BTDLH = quot >> 8; + BTLCR = LCR_WLS0 | LCR_WLS1; - BTIER = IER_UUE; /* Enable BFUART */ + BTIER = IER_UUE; /* Enable BFUART */ -#elif defined(CONFIG_STUART) + break; + + case STUART: #ifdef CONFIG_CPU_MONAHANS - CKENA |= CKENA_23_STUART; + CKENA |= CKENA_23_STUART; #else - CKEN |= CKEN5_STUART; + CKEN |= CKEN5_STUART; #endif /* CONFIG_CPU_MONAHANS */ - STIER = 0; - STFCR = 0; + STIER = 0; + STFCR = 0; - /* set baud rate */ - STLCR = LCR_DLAB; - STDLL = quot & 0xff; - STDLH = quot >> 8; - STLCR = LCR_WLS0 | LCR_WLS1; + /* set baud rate */ + STLCR = LCR_DLAB; + STDLL = quot & 0xff; + STDLH = quot >> 8; + STLCR = LCR_WLS0 | LCR_WLS1; - STIER = IER_UUE; /* Enable STUART */ + STIER = IER_UUE; /* Enable STUART */ + break; -#else -#error "Bad: you didn't configure serial ..." -#endif + default: + hang(); + } } @@ -118,9 +140,9 @@ void serial_setbrg (void) * are always 8 data bits, no parity, 1 stop bit, no start bits. * */ -int serial_init (void) +int pxa_init_dev (unsigned int uart_index) { - serial_setbrg (); + pxa_setbrg_dev (uart_index); return (0); } @@ -129,26 +151,32 @@ int serial_init (void) /* * Output a single byte to the serial port. */ -void serial_putc (const char c) +void pxa_putc_dev (unsigned int uart_index,const char c) { -#ifdef CONFIG_FFUART - /* wait for room in the tx FIFO on FFUART */ - while ((FFLSR & LSR_TEMT) == 0) - WATCHDOG_RESET (); /* Reset HW Watchdog, if needed */ - FFTHR = c; -#elif defined(CONFIG_BTUART) - while ((BTLSR & LSR_TEMT ) == 0 ) - WATCHDOG_RESET (); /* Reset HW Watchdog, if needed */ - BTTHR = c; -#elif defined(CONFIG_STUART) - while ((STLSR & LSR_TEMT ) == 0 ) - WATCHDOG_RESET (); /* Reset HW Watchdog, if needed */ - STTHR = c; -#endif + switch (uart_index) { + case FFUART: + /* wait for room in the tx FIFO on FFUART */ + while ((FFLSR & LSR_TEMT) == 0) + WATCHDOG_RESET (); /* Reset HW Watchdog, if needed */ + FFTHR = c; + break; + + case BTUART: + while ((BTLSR & LSR_TEMT ) == 0 ) + WATCHDOG_RESET (); /* Reset HW Watchdog, if needed */ + BTTHR = c; + break; + + case STUART: + while ((STLSR & LSR_TEMT ) == 0 ) + WATCHDOG_RESET (); /* Reset HW Watchdog, if needed */ + STTHR = c; + break; + } /* If \n, also do \r */ if (c == '\n') - serial_putc ('\r'); + pxa_putc_dev (uart_index,'\r'); } /* @@ -156,15 +184,17 @@ void serial_putc (const char c) * otherwise. When the function is succesfull, the character read is * written into its argument c. */ -int serial_tstc (void) +int pxa_tstc_dev (unsigned int uart_index) { -#ifdef CONFIG_FFUART - return FFLSR & LSR_DR; -#elif defined(CONFIG_BTUART) - return BTLSR & LSR_DR; -#elif defined(CONFIG_STUART) - return STLSR & LSR_DR; -#endif + switch (uart_index) { + case FFUART: + return FFLSR & LSR_DR; + case BTUART: + return BTLSR & LSR_DR; + case STUART: + return STLSR & LSR_DR; + } + return -1; } /* @@ -172,27 +202,184 @@ int serial_tstc (void) * otherwise. When the function is succesfull, the character read is * written into its argument c. */ -int serial_getc (void) +int pxa_getc_dev (unsigned int uart_index) { -#ifdef CONFIG_FFUART - while (!(FFLSR & LSR_DR)) - WATCHDOG_RESET (); /* Reset HW Watchdog, if needed */ - return (char) FFRBR & 0xff; -#elif defined(CONFIG_BTUART) - while (!(BTLSR & LSR_DR)) - WATCHDOG_RESET (); /* Reset HW Watchdog, if needed */ - return (char) BTRBR & 0xff; -#elif defined(CONFIG_STUART) - while (!(STLSR & LSR_DR)) - WATCHDOG_RESET (); /* Reset HW Watchdog, if needed */ - return (char) STRBR & 0xff; -#endif + switch (uart_index) { + case FFUART: + while (!(FFLSR & LSR_DR)) + WATCHDOG_RESET (); /* Reset HW Watchdog, if needed */ + return (char) FFRBR & 0xff; + + case BTUART: + while (!(BTLSR & LSR_DR)) + WATCHDOG_RESET (); /* Reset HW Watchdog, if needed */ + return (char) BTRBR & 0xff; + case STUART: + while (!(STLSR & LSR_DR)) + WATCHDOG_RESET (); /* Reset HW Watchdog, if needed */ + return (char) STRBR & 0xff; + } + return -1; } void -serial_puts (const char *s) +pxa_puts_dev (unsigned int uart_index,const char *s) { while (*s) { - serial_putc (*s++); + pxa_putc_dev (uart_index,*s++); } } + +#if defined (CONFIG_FFUART) +static int ffuart_init(void) +{ + return pxa_init_dev(FFUART); +} + +static void ffuart_setbrg(void) +{ + return pxa_setbrg_dev(FFUART); +} + +static void ffuart_putc(const char c) +{ + return pxa_putc_dev(FFUART,c); +} + +static void ffuart_puts(const char *s) +{ + return pxa_puts_dev(FFUART,s); +} + +static int ffuart_getc(void) +{ + return pxa_getc_dev(FFUART); +} + +static int ffuart_tstc(void) +{ + return pxa_tstc_dev(FFUART); +} + +struct serial_device serial_ffuart_device = +{ + "serial_ffuart", + "PXA", + ffuart_init, + ffuart_setbrg, + ffuart_getc, + ffuart_tstc, + ffuart_putc, + ffuart_puts, +}; +#endif + +#if defined (CONFIG_BTUART) +static int btuart_init(void) +{ + return pxa_init_dev(BTUART); +} + +static void btuart_setbrg(void) +{ + return pxa_setbrg_dev(BTUART); +} + +static void btuart_putc(const char c) +{ + return pxa_putc_dev(BTUART,c); +} + +static void btuart_puts(const char *s) +{ + return pxa_puts_dev(BTUART,s); +} + +static int btuart_getc(void) +{ + return pxa_getc_dev(BTUART); +} + +static int btuart_tstc(void) +{ + return pxa_tstc_dev(BTUART); +} + +struct serial_device serial_btuart_device = +{ + "serial_btuart", + "PXA", + btuart_init, + btuart_setbrg, + btuart_getc, + btuart_tstc, + btuart_putc, + btuart_puts, +}; +#endif + +#if defined (CONFIG_STUART) +static int stuart_init(void) +{ + return pxa_init_dev(STUART); +} + +static void stuart_setbrg(void) +{ + return pxa_setbrg_dev(STUART); +} + +static void stuart_putc(const char c) +{ + return pxa_putc_dev(STUART,c); +} + +static void stuart_puts(const char *s) +{ + return pxa_puts_dev(STUART,s); +} + +static int stuart_getc(void) +{ + return pxa_getc_dev(STUART); +} + +static int stuart_tstc(void) +{ + return pxa_tstc_dev(STUART); +} + +struct serial_device serial_stuart_device = +{ + "serial_stuart", + "PXA", + stuart_init, + stuart_setbrg, + stuart_getc, + stuart_tstc, + stuart_putc, + stuart_puts, +}; +#endif + + +#ifndef CONFIG_SERIAL_MULTI +inline int serial_init(void) { + return (pxa_init_dev(UART_INDEX)); +} +void serial_setbrg(void) { + pxa_setbrg_dev(UART_INDEX); +} +int serial_getc(void) { + return(pxa_getc_dev(UART_INDEX)); +} +int serial_tstc(void) { + return(pxa_tstc_dev(UART_INDEX)); +} +void serial_putc(const char c) { + pxa_putc_dev(UART_INDEX,c); +} +void serial_puts(const char *s) { + pxa_puts_dev(UART_INDEX,s); +} +#endif /* CONFIG_SERIAL_MULTI */ diff --git a/include/serial.h b/include/serial.h index f7412fd17..30bfde308 100644 --- a/include/serial.h +++ b/include/serial.h @@ -36,6 +36,10 @@ extern struct serial_device eserial4_device; #endif +extern struct serial_device serial_ffuart_device; +extern struct serial_device serial_btuart_device; +extern struct serial_device serial_stuart_device; + extern void serial_initialize(void); extern void serial_devices_init(void); extern int serial_assign(char * name); diff --git a/lib_arm/board.c b/lib_arm/board.c index d37e5dab3..d28afc52f 100644 --- a/lib_arm/board.c +++ b/lib_arm/board.c @@ -314,6 +314,10 @@ void start_armboot (void) drv_vfd_init(); #endif /* CONFIG_VFD */ +#ifdef CONFIG_SERIAL_MULTI + serial_initialize(); +#endif + /* IP Address */ gd->bd->bi_ip_addr = getenv_IPaddr ("ipaddr"); From 5e5803e119de3bebd76fc9a57baac0b5aeccc8a3 Mon Sep 17 00:00:00 2001 From: stefano babic Date: Thu, 30 Aug 2007 23:01:49 +0200 Subject: [PATCH 221/259] PXA270: Added support for TrizepsIV board. This patch add support for the Trizeps IV module (520Mhz). Signed-off-by: Stefano Babic --- Makefile | 3 + board/trizepsiv/Makefile | 51 ++++ board/trizepsiv/config.mk | 3 + board/trizepsiv/conxs.c | 146 +++++++++ board/trizepsiv/eeprom.c | 85 ++++++ board/trizepsiv/lowlevel_init.S | 503 ++++++++++++++++++++++++++++++++ board/trizepsiv/pxavoltage.S | 31 ++ board/trizepsiv/u-boot.lds | 56 ++++ drivers/dm9000x.c | 16 +- include/configs/trizepsiv.h | 325 +++++++++++++++++++++ 10 files changed, 1217 insertions(+), 2 deletions(-) create mode 100644 board/trizepsiv/Makefile create mode 100644 board/trizepsiv/config.mk create mode 100644 board/trizepsiv/conxs.c create mode 100644 board/trizepsiv/eeprom.c create mode 100644 board/trizepsiv/lowlevel_init.S create mode 100644 board/trizepsiv/pxavoltage.S create mode 100644 board/trizepsiv/u-boot.lds create mode 100644 include/configs/trizepsiv.h diff --git a/Makefile b/Makefile index 0477cd3dc..0371d4619 100644 --- a/Makefile +++ b/Makefile @@ -2334,6 +2334,9 @@ scpu_config: unconfig pxa255_idp_config: unconfig @$(MKCONFIG) $(@:_config=) arm pxa pxa255_idp +trizepsiv_config : unconfig + @$(MKCONFIG) $(@:_config=) arm pxa trizepsiv + wepep250_config : unconfig @$(MKCONFIG) $(@:_config=) arm pxa wepep250 diff --git a/board/trizepsiv/Makefile b/board/trizepsiv/Makefile new file mode 100644 index 000000000..115e17ded --- /dev/null +++ b/board/trizepsiv/Makefile @@ -0,0 +1,51 @@ +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS := conxs.o eeprom.o +SOBJS := lowlevel_init.o pxavoltage.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/trizepsiv/config.mk b/board/trizepsiv/config.mk new file mode 100644 index 000000000..4486f6b96 --- /dev/null +++ b/board/trizepsiv/config.mk @@ -0,0 +1,3 @@ +TEXT_BASE =0xa1f00000 +# 0xa1700000 +#TEXT_BASE = 0 diff --git a/board/trizepsiv/conxs.c b/board/trizepsiv/conxs.c new file mode 100644 index 000000000..7c6c85500 --- /dev/null +++ b/board/trizepsiv/conxs.c @@ -0,0 +1,146 @@ +/* + * (C) Copyright 2007 + * Stefano Babic, DENX Gmbh, sbabic@denx.de + * + * (C) Copyright 2004 + * Robert Whaley, Applied Data Systems, Inc. rwhaley@applieddata.net + * + * (C) Copyright 2002 + * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Marius Groeger + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#define RH_A_PSM (1 << 8) /* power switching mode */ +#define RH_A_NPS (1 << 9) /* no power switching */ + +extern struct serial_device serial_ffuart_device; +extern struct serial_device serial_btuart_device; +extern struct serial_device serial_stuart_device; + +/* ------------------------------------------------------------------------- */ + +/* + * Miscelaneous platform dependent initialisations + */ + +void usb_board_init(void) +{ + UHCHR = (UHCHR | UHCHR_PCPL | UHCHR_PSPL) & + ~(UHCHR_SSEP0 | UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSE); + + UHCHR |= UHCHR_FSBIR; + + while (UHCHR & UHCHR_FSBIR); + + UHCHR &= ~UHCHR_SSE; + UHCHIE = (UHCHIE_UPRIE | UHCHIE_RWIE); + + /* Clear any OTG Pin Hold */ + if (PSSR & PSSR_OTGPH) + PSSR |= PSSR_OTGPH; + + UHCRHDA &= ~(RH_A_NPS); + UHCRHDA |= RH_A_PSM; + + /* Set port power control mask bits, only 3 ports. */ + UHCRHDB |= (0x7<<17); +} + +void usb_board_init_fail(void) +{ + return; +} + +void usb_board_stop(void) +{ + UHCHR |= UHCHR_FHR; + udelay(11); + UHCHR &= ~UHCHR_FHR; + + UHCCOMS |= 1; + udelay(10); + + CKEN &= ~CKEN10_USBHOST; + + puts("Called USB STOP\n"); + return; +} + +int board_init (void) +{ + /* memory and cpu-speed are setup before relocation */ + /* so we do _nothing_ here */ + + /* arch number of ConXS Board */ + gd->bd->bi_arch_number = 776; + + /* adress of boot parameters */ + gd->bd->bi_boot_params = 0xa000003c; + + return 0; +} + +int board_late_init(void) +{ +#if defined(CONFIG_SERIAL_MULTI) + char *console=getenv("boot_console"); + + if ((strcmp(console,"serial_btuart") == 0) || + (strcmp(console,"serial_stuart") == 0) || + (strcmp(console,"serial_ffuart") == 0)) { + setenv("stdout",console); + setenv("stdin", console); + setenv("stderr",console); + } else { + setenv("stdout", "serial"); + setenv("stdin", "serial"); + setenv("stderr", "serial"); + } +#endif + return 0; +} + +struct serial_device *default_serial_console (void) +{ + return &serial_ffuart_device; +} + +int dram_init (void) +{ + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + gd->bd->bi_dram[1].start = PHYS_SDRAM_2; + gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE; + gd->bd->bi_dram[2].start = PHYS_SDRAM_3; + gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE; + gd->bd->bi_dram[3].start = PHYS_SDRAM_4; + gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE; + + return 0; +} diff --git a/board/trizepsiv/eeprom.c b/board/trizepsiv/eeprom.c new file mode 100644 index 000000000..3d3bc0022 --- /dev/null +++ b/board/trizepsiv/eeprom.c @@ -0,0 +1,85 @@ +/* + * (C) Copyright 2007 + * Stefano Babic, DENX Software Engineering, sbabic@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +static unsigned char srom[128]; +extern u16 read_srom_word(int); +extern void write_srom_word(int offset, u16 val); + +static int do_read_dm9000_eeprom ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { + int i; + + for (i=0; i < 0x40; i++) { + if (!(i % 0x10)) + printf("\n%08lx:", i); + printf(" %04x", read_srom_word(i)); + } + printf ("\n"); + return (0); +} + +static int do_write_dm9000_eeprom ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { + int offset,value; + + if (argc < 4) { + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; + } + + offset=simple_strtoul(argv[2],NULL,16); + value=simple_strtoul(argv[3],NULL,16); + if (offset > 0x40) { + printf("Wrong offset : 0x%x\n",offset); + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; + } + write_srom_word(offset, value); + return (0); +} + +int do_dm9000_eeprom ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { + if (argc < 2) { + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; + } + + if (strcmp (argv[1],"read") == 0) { + return (do_read_dm9000_eeprom(cmdtp,flag,argc,argv)); + } else if (strcmp (argv[1],"write") == 0) { + return (do_write_dm9000_eeprom(cmdtp,flag,argc,argv)); + } else { + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; + } +} + +U_BOOT_CMD( + dm9000ee,4,1,do_dm9000_eeprom, + "dm9000ee- Read/Write eeprom connected to Ethernet Controller\n", + "\ndm9000ee write \n" + "\tdm9000ee read \n" + "\tword:\t\t00-02 : MAC Address\n" + "\t\t\t03-07 : DM9000 Configuration\n" + "\t\t\t08-63 : User data\n"); diff --git a/board/trizepsiv/lowlevel_init.S b/board/trizepsiv/lowlevel_init.S new file mode 100644 index 000000000..d8869381a --- /dev/null +++ b/board/trizepsiv/lowlevel_init.S @@ -0,0 +1,503 @@ +/* + * This was originally from the Lubbock u-boot port. + * + * Most of this taken from Redboot hal_platform_setup.h with cleanup + * + * NOTE: I haven't clean this up considerably, just enough to get it + * running. See hal_platform_setup.h for the source. See + * board/cradle/lowlevel_init.S for another PXA250 setup that is + * much cleaner. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +/* wait for coprocessor write complete */ + .macro CPWAIT reg + mrc p15,0,\reg,c2,c0,0 + mov \reg,\reg + sub pc,pc,#4 + .endm + + +/* + * Memory setup + */ + +.globl lowlevel_init +lowlevel_init: + + /* Set up GPIO pins first ----------------------------------------- */ + + ldr r0, =GPSR0 + ldr r1, =CFG_GPSR0_VAL + str r1, [r0] + + ldr r0, =GPSR1 + ldr r1, =CFG_GPSR1_VAL + str r1, [r0] + + ldr r0, =GPSR2 + ldr r1, =CFG_GPSR2_VAL + str r1, [r0] + + ldr r0, =GPSR3 + ldr r1, =CFG_GPSR3_VAL + str r1, [r0] + + ldr r0, =GPCR0 + ldr r1, =CFG_GPCR0_VAL + str r1, [r0] + + ldr r0, =GPCR1 + ldr r1, =CFG_GPCR1_VAL + str r1, [r0] + + ldr r0, =GPCR2 + ldr r1, =CFG_GPCR2_VAL + str r1, [r0] + + ldr r0, =GPCR3 + ldr r1, =CFG_GPCR3_VAL + str r1, [r0] + + ldr r0, =GRER0 + ldr r1, =CFG_GRER0_VAL + str r1, [r0] + + ldr r0, =GRER1 + ldr r1, =CFG_GRER1_VAL + str r1, [r0] + + ldr r0, =GRER2 + ldr r1, =CFG_GRER2_VAL + str r1, [r0] + + ldr r0, =GRER3 + ldr r1, =CFG_GRER3_VAL + str r1, [r0] + + ldr r0, =GFER0 + ldr r1, =CFG_GFER0_VAL + str r1, [r0] + + ldr r0, =GFER1 + ldr r1, =CFG_GFER1_VAL + str r1, [r0] + + ldr r0, =GFER2 + ldr r1, =CFG_GFER2_VAL + str r1, [r0] + + ldr r0, =GFER3 + ldr r1, =CFG_GFER3_VAL + str r1, [r0] + + ldr r0, =GPDR0 + ldr r1, =CFG_GPDR0_VAL + str r1, [r0] + + ldr r0, =GPDR1 + ldr r1, =CFG_GPDR1_VAL + str r1, [r0] + + ldr r0, =GPDR2 + ldr r1, =CFG_GPDR2_VAL + str r1, [r0] + + ldr r0, =GPDR3 + ldr r1, =CFG_GPDR3_VAL + str r1, [r0] + + ldr r0, =GAFR0_L + ldr r1, =CFG_GAFR0_L_VAL + str r1, [r0] + + ldr r0, =GAFR0_U + ldr r1, =CFG_GAFR0_U_VAL + str r1, [r0] + + ldr r0, =GAFR1_L + ldr r1, =CFG_GAFR1_L_VAL + str r1, [r0] + + ldr r0, =GAFR1_U + ldr r1, =CFG_GAFR1_U_VAL + str r1, [r0] + + ldr r0, =GAFR2_L + ldr r1, =CFG_GAFR2_L_VAL + str r1, [r0] + + ldr r0, =GAFR2_U + ldr r1, =CFG_GAFR2_U_VAL + str r1, [r0] + + ldr r0, =GAFR3_L + ldr r1, =CFG_GAFR3_L_VAL + str r1, [r0] + + ldr r0, =GAFR3_U + ldr r1, =CFG_GAFR3_U_VAL + str r1, [r0] + + ldr r0, =PSSR /* enable GPIO pins */ + ldr r1, =CFG_PSSR_VAL + str r1, [r0] + + /* ---------------------------------------------------------------- */ + /* Enable memory interface */ + /* */ + /* The sequence below is based on the recommended init steps */ + /* detailed in the Intel PXA250 Operating Systems Developers Guide, */ + /* Chapter 10. */ + /* ---------------------------------------------------------------- */ + + /* ---------------------------------------------------------------- */ + /* Step 1: Wait for at least 200 microsedonds to allow internal */ + /* clocks to settle. Only necessary after hard reset... */ + /* FIXME: can be optimized later */ + /* ---------------------------------------------------------------- */ + + ldr r3, =OSCR /* reset the OS Timer Count to zero */ + mov r2, #0 + str r2, [r3] + ldr r4, =0x300 /* really 0x2E1 is about 200usec, */ + /* so 0x300 should be plenty */ +1: + ldr r2, [r3] + cmp r4, r2 + bgt 1b + +mem_init: + + ldr r1, =MEMC_BASE /* get memory controller base addr. */ + + /* ---------------------------------------------------------------- */ + /* Step 2a: Initialize Asynchronous static memory controller */ + /* ---------------------------------------------------------------- */ + + /* MSC registers: timing, bus width, mem type */ + + /* MSC0: nCS(0,1) */ + ldr r2, =CFG_MSC0_VAL + str r2, [r1, #MSC0_OFFSET] + ldr r2, [r1, #MSC0_OFFSET] /* read back to ensure */ + /* that data latches */ + /* MSC1: nCS(2,3) */ + ldr r2, =CFG_MSC1_VAL + str r2, [r1, #MSC1_OFFSET] + ldr r2, [r1, #MSC1_OFFSET] + + /* MSC2: nCS(4,5) */ + ldr r2, =CFG_MSC2_VAL + str r2, [r1, #MSC2_OFFSET] + ldr r2, [r1, #MSC2_OFFSET] + + /* ---------------------------------------------------------------- */ + /* Step 2b: Initialize Card Interface */ + /* ---------------------------------------------------------------- */ + + /* MECR: Memory Expansion Card Register */ + ldr r2, =CFG_MECR_VAL + str r2, [r1, #MECR_OFFSET] + ldr r2, [r1, #MECR_OFFSET] + + /* MCMEM0: Card Interface slot 0 timing */ + ldr r2, =CFG_MCMEM0_VAL + str r2, [r1, #MCMEM0_OFFSET] + ldr r2, [r1, #MCMEM0_OFFSET] + + /* MCMEM1: Card Interface slot 1 timing */ + ldr r2, =CFG_MCMEM1_VAL + str r2, [r1, #MCMEM1_OFFSET] + ldr r2, [r1, #MCMEM1_OFFSET] + + /* MCATT0: Card Interface Attribute Space Timing, slot 0 */ + ldr r2, =CFG_MCATT0_VAL + str r2, [r1, #MCATT0_OFFSET] + ldr r2, [r1, #MCATT0_OFFSET] + + /* MCATT1: Card Interface Attribute Space Timing, slot 1 */ + ldr r2, =CFG_MCATT1_VAL + str r2, [r1, #MCATT1_OFFSET] + ldr r2, [r1, #MCATT1_OFFSET] + + /* MCIO0: Card Interface I/O Space Timing, slot 0 */ + ldr r2, =CFG_MCIO0_VAL + str r2, [r1, #MCIO0_OFFSET] + ldr r2, [r1, #MCIO0_OFFSET] + + /* MCIO1: Card Interface I/O Space Timing, slot 1 */ + ldr r2, =CFG_MCIO1_VAL + str r2, [r1, #MCIO1_OFFSET] + ldr r2, [r1, #MCIO1_OFFSET] + + /* ---------------------------------------------------------------- */ + /* Step 2c: Write FLYCNFG FIXME: what's that??? */ + /* ---------------------------------------------------------------- */ + ldr r2, =CFG_FLYCNFG_VAL + str r2, [r1, #FLYCNFG_OFFSET] + str r2, [r1, #FLYCNFG_OFFSET] + + /* ---------------------------------------------------------------- */ + /* Step 2d: Initialize Timing for Sync Memory (SDCLK0) */ + /* ---------------------------------------------------------------- */ + + /* Before accessing MDREFR we need a valid DRI field, so we set */ + /* this to power on defaults + DRI field. */ + + ldr r4, [r1, #MDREFR_OFFSET] + ldr r2, =0xFFF + bic r4, r4, r2 + + ldr r3, =CFG_MDREFR_VAL + and r3, r3, r2 + + orr r4, r4, r3 + str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */ + + orr r4, r4, #MDREFR_K0RUN + orr r4, r4, #MDREFR_K0DB4 + orr r4, r4, #MDREFR_K0FREE + orr r4, r4, #MDREFR_K0DB2 + orr r4, r4, #MDREFR_K1DB2 + bic r4, r4, #MDREFR_K1FREE + bic r4, r4, #MDREFR_K2FREE + + str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */ + ldr r4, [r1, #MDREFR_OFFSET] + + /* Note: preserve the mdrefr value in r4 */ + + + /* ---------------------------------------------------------------- */ + /* Step 3: Initialize Synchronous Static Memory (Flash/Peripherals) */ + /* ---------------------------------------------------------------- */ + + /* Initialize SXCNFG register. Assert the enable bits */ + + /* Write SXMRS to cause an MRS command to all enabled banks of */ + /* synchronous static memory. Note that SXLCR need not be written */ + /* at this time. */ + + ldr r2, =CFG_SXCNFG_VAL + str r2, [r1, #SXCNFG_OFFSET] + + /* ---------------------------------------------------------------- */ + /* Step 4: Initialize SDRAM */ + /* ---------------------------------------------------------------- */ + + bic r4, r4, #(MDREFR_K2FREE |MDREFR_K1FREE | MDREFR_K0FREE) + + orr r4, r4, #MDREFR_K1RUN + bic r4, r4, #MDREFR_K2DB2 + str r4, [r1, #MDREFR_OFFSET] + ldr r4, [r1, #MDREFR_OFFSET] + + bic r4, r4, #MDREFR_SLFRSH + str r4, [r1, #MDREFR_OFFSET] + ldr r4, [r1, #MDREFR_OFFSET] + + orr r4, r4, #MDREFR_E1PIN + str r4, [r1, #MDREFR_OFFSET] + ldr r4, [r1, #MDREFR_OFFSET] + + nop + nop + + + /* Step 4d: write MDCNFG with MDCNFG:DEx deasserted (set to 0), to */ + /* configure but not enable each SDRAM partition pair. */ + + ldr r4, =CFG_MDCNFG_VAL + bic r4, r4, #(MDCNFG_DE0|MDCNFG_DE1) + bic r4, r4, #(MDCNFG_DE2|MDCNFG_DE3) + + str r4, [r1, #MDCNFG_OFFSET] /* write back MDCNFG */ + ldr r4, [r1, #MDCNFG_OFFSET] + + + /* Step 4e: Wait for the clock to the SDRAMs to stabilize, */ + /* 100..200 µsec. */ + + ldr r3, =OSCR /* reset the OS Timer Count to zero */ + mov r2, #0 + str r2, [r3] + ldr r4, =0x300 /* really 0x2E1 is about 200usec, */ + /* so 0x300 should be plenty */ +1: + ldr r2, [r3] + cmp r4, r2 + bgt 1b + + + /* Step 4f: Trigger a number (usually 8) refresh cycles by */ + /* attempting non-burst read or write accesses to disabled */ + /* SDRAM, as commonly specified in the power up sequence */ + /* documented in SDRAM data sheets. The address(es) used */ + /* for this purpose must not be cacheable. */ + + ldr r3, =CFG_DRAM_BASE + str r2, [r3] + str r2, [r3] + str r2, [r3] + str r2, [r3] + str r2, [r3] + str r2, [r3] + str r2, [r3] + str r2, [r3] + + + /* Step 4g: Write MDCNFG with enable bits asserted */ + /* (MDCNFG:DEx set to 1). */ + + ldr r3, [r1, #MDCNFG_OFFSET] + mov r4, r3 + orr r3, r3, #MDCNFG_DE0 + str r3, [r1, #MDCNFG_OFFSET] + mov r0, r3 + + /* Step 4h: Write MDMRS. */ + + ldr r2, =CFG_MDMRS_VAL + str r2, [r1, #MDMRS_OFFSET] + + /* enable APD */ + ldr r3, [r1, #MDREFR_OFFSET] + orr r3, r3, #MDREFR_APD + str r3, [r1, #MDREFR_OFFSET] + + /* We are finished with Intel's memory controller initialisation */ + + +setvoltage: + + mov r10, lr + bl initPXAvoltage /* In case the board is rebooting with a */ + mov lr, r10 /* low voltage raise it up to a good one. */ + +#if 1 + b initirqs +#endif + +wakeup: + /* Are we waking from sleep? */ + ldr r0, =RCSR + ldr r1, [r0] + and r1, r1, #(RCSR_GPR | RCSR_SMR | RCSR_WDR | RCSR_HWR) + str r1, [r0] + teq r1, #RCSR_SMR + + bne initirqs + + ldr r0, =PSSR + mov r1, #PSSR_PH + str r1, [r0] + + /* if so, resume at PSPR */ + ldr r0, =PSPR + ldr r1, [r0] + mov pc, r1 + + /* ---------------------------------------------------------------- */ + /* Disable (mask) all interrupts at interrupt controller */ + /* ---------------------------------------------------------------- */ + +initirqs: + + mov r1, #0 /* clear int. level register (IRQ, not FIQ) */ + ldr r2, =ICLR + str r1, [r2] + + ldr r2, =ICMR /* mask all interrupts at the controller */ + str r1, [r2] + + /* ---------------------------------------------------------------- */ + /* Clock initialisation */ + /* ---------------------------------------------------------------- */ + +initclks: + + /* Disable the peripheral clocks, and set the core clock frequency */ + + /* Turn Off on-chip peripheral clocks (except for memory) */ + /* for re-configuration. */ + ldr r1, =CKEN + ldr r2, =CFG_CKEN + str r2, [r1] + + /* ... and write the core clock config register */ + ldr r2, =CFG_CCCR + ldr r1, =CCCR + str r2, [r1] + + /* Turn on turbo mode */ + mrc p14, 0, r2, c6, c0, 0 + orr r2, r2, #0xB /* Turbo, Fast-Bus, Freq change**/ + mcr p14, 0, r2, c6, c0, 0 + + /* Re-write MDREFR */ + ldr r1, =MEMC_BASE + ldr r2, [r1, #MDREFR_OFFSET] + str r2, [r1, #MDREFR_OFFSET] +#ifdef RTC + /* enable the 32Khz oscillator for RTC and PowerManager */ + ldr r1, =OSCC + mov r2, #OSCC_OON + str r2, [r1] + + /* NOTE: spin here until OSCC.OOK get set, meaning the PLL */ + /* has settled. */ +60: + ldr r2, [r1] + ands r2, r2, #1 + beq 60b +#else +#error "RTC not defined" +#endif + + /* Interrupt init: Mask all interrupts */ + ldr r0, =ICMR /* enable no sources */ + mov r1, #0 + str r1, [r0] + /* FIXME */ + +#ifdef NODEBUG + /*Disable software and data breakpoints */ + mov r0,#0 + mcr p15,0,r0,c14,c8,0 /* ibcr0 */ + mcr p15,0,r0,c14,c9,0 /* ibcr1 */ + mcr p15,0,r0,c14,c4,0 /* dbcon */ + + /*Enable all debug functionality */ + mov r0,#0x80000000 + mcr p14,0,r0,c10,c0,0 /* dcsr */ +#endif + + /* ---------------------------------------------------------------- */ + /* End lowlevel_init */ + /* ---------------------------------------------------------------- */ + +endlowlevel_init: + + mov pc, lr diff --git a/board/trizepsiv/pxavoltage.S b/board/trizepsiv/pxavoltage.S new file mode 100644 index 000000000..5e411321f --- /dev/null +++ b/board/trizepsiv/pxavoltage.S @@ -0,0 +1,31 @@ +/* + * (C) Copyright 2007 + * Stefano Babic, DENX Gmbh, sbabic@denx.de + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + + + .global initPXAvoltage + +initPXAvoltage: + mov pc, lr + diff --git a/board/trizepsiv/u-boot.lds b/board/trizepsiv/u-boot.lds new file mode 100644 index 000000000..f0102391b --- /dev/null +++ b/board/trizepsiv/u-boot.lds @@ -0,0 +1,56 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + cpu/pxa/start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .got : { *(.got) } + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = ALIGN(4); + __bss_start = .; + .bss : { *(.bss) } + _end = .; +} diff --git a/drivers/dm9000x.c b/drivers/dm9000x.c index e0d531bd9..6131b5c35 100644 --- a/drivers/dm9000x.c +++ b/drivers/dm9000x.c @@ -99,7 +99,7 @@ void eth_halt(void); static int dm9000_probe(void); static u16 phy_read(int); static void phy_write(int, u16); -static u16 read_srom_word(int); +u16 read_srom_word(int); static u8 DM9000_ior(int); static void DM9000_iow(int reg, u8 value); @@ -537,7 +537,7 @@ eth_rx(void) /* Read a word data from SROM */ -static u16 +u16 read_srom_word(int offset) { DM9000_iow(DM9000_EPAR, offset); @@ -547,6 +547,18 @@ read_srom_word(int offset) return (DM9000_ior(DM9000_EPDRL) + (DM9000_ior(DM9000_EPDRH) << 8)); } +void +write_srom_word(int offset, u16 val) +{ + DM9000_iow(DM9000_EPAR, offset); + DM9000_iow(DM9000_EPDRH, ((val >> 8) & 0xff)); + DM9000_iow(DM9000_EPDRL, (val & 0xff)); + DM9000_iow(DM9000_EPCR, 0x12); + udelay(8000); + DM9000_iow(DM9000_EPCR, 0); +} + + /* Read a byte from I/O port */ diff --git a/include/configs/trizepsiv.h b/include/configs/trizepsiv.h new file mode 100644 index 000000000..84998d439 --- /dev/null +++ b/include/configs/trizepsiv.h @@ -0,0 +1,325 @@ +/* + * (C) Copyright 2007 + * Stefano Babic, DENX Gmbh, sbabic@denx.de + * + * (C) Copyright 2004 + * Robert Whaley, Applied Data Systems, Inc. rwhaley@applieddata.net + * + * (C) Copyright 2002 + * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Marius Groeger + * + * Configuation settings for the LUBBOCK board. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ +#define CONFIG_PXA27X 1 /* This is an PXA27x CPU */ + +#define LITTLEENDIAN 1 /* used by usb_ohci.c */ + +#define CONFIG_MMC 1 +#define BOARD_LATE_INIT 1 + +#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ + +#define RTC + +/* + * Size of malloc() pool + */ +#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024) +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ + +/* + * Hardware drivers + */ + +/* + * select serial console configuration + */ +#define CONFIG_SERIAL_MULTI +#define CONFIG_FFUART 1 /* we use FFUART on Conxs */ +#define CONFIG_BTUART 1 /* we use BTUART on Conxs */ +#define CONFIG_STUART 1 /* we use STUART on Conxs */ + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE + +#define CONFIG_BAUDRATE 38400 + +#define CONFIG_DOS_PARTITION 1 + +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_MMC +#define CONFIG_CMD_FAT +#define CONFIG_CMD_IMLS +#define CONFIG_CMD_PING +#define CONFIG_CMD_USB + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ + +#undef CONFIG_SHOW_BOOT_PROGRESS + +#define CONFIG_BOOTDELAY 3 +#define CONFIG_SERVERIP 192.168.1.99 +#define CONFIG_BOOTCOMMAND "run boot_flash" +#define CONFIG_BOOTARGS "console=ttyS0,38400 ramdisk_size=12288"\ + " rw root=/dev/ram initrd=0xa0800000,5m" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "program_boot_mmc=" \ + "mw.b 0xa0010000 0xff 0x20000; " \ + "if mmcinit && " \ + "fatload mmc 0 0xa0010000 u-boot.bin; " \ + "then " \ + "protect off 0x0 0x1ffff; " \ + "erase 0x0 0x1ffff; " \ + "cp.b 0xa0010000 0x0 0x20000; " \ + "fi\0" \ + "program_uzImage_mmc=" \ + "mw.b 0xa0010000 0xff 0x180000; " \ + "if mmcinit && " \ + "fatload mmc 0 0xa0010000 uzImage; " \ + "then " \ + "protect off 0x40000 0x1bffff; " \ + "erase 0x40000 0x1bffff; " \ + "cp.b 0xa0010000 0x40000 0x180000; " \ + "fi\0" \ + "program_ramdisk_mmc=" \ + "mw.b 0xa0010000 0xff 0x500000; " \ + "if mmcinit && " \ + "fatload mmc 0 0xa0010000 ramdisk.gz; " \ + "then " \ + "protect off 0x1c0000 0x6bffff; " \ + "erase 0x1c0000 0x6bffff; " \ + "cp.b 0xa0010000 0x1c0000 0x500000; " \ + "fi\0" \ + "boot_mmc=" \ + "if mmcinit && " \ + "fatload mmc 0 0xa0030000 uzImage && " \ + "fatload mmc 0 0xa0800000 ramdisk.gz; " \ + "then " \ + "bootm 0xa0030000; " \ + "fi\0" \ + "boot_flash=" \ + "cp.b 0x1c0000 0xa0800000 0x500000; " \ + "bootm 0x40000\0" \ + +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ +/* #define CONFIG_INITRD_TAG 1 */ + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif + +/* + * Miscellaneous configurable options + */ +#define CFG_HUSH_PARSER 1 +#define CFG_PROMPT_HUSH_PS2 "> " + +#define CFG_LONGHELP /* undef to save memory */ +#ifdef CFG_HUSH_PARSER +#define CFG_PROMPT "$ " /* Monitor Command Prompt */ +#else +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#endif +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ +#define CFG_DEVICE_NULLDEV 1 + +#define CFG_MEMTEST_START 0xa0400000 /* memtest works on */ +#define CFG_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */ + +#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ + +#define CFG_LOAD_ADDR 0xa1000000 /* default load address */ + +#define CFG_HZ 3686400 /* incrementer freq: 3.6864 MHz */ +#define CFG_CPUSPEED 0x207 /* need to look more closely, I think this is Turbo = 2x, L=91Mhz */ + + /* valid baudrates */ +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +#define CFG_MMC_BASE 0xF0000000 + +/* + * Stack sizes + * + * The stack sizes are set up in start.S using the settings below + */ +#define CONFIG_STACKSIZE (128*1024) /* regular stack */ +#ifdef CONFIG_USE_IRQ +#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ +#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ +#endif + +/* + * Physical Memory Map + */ +#define CONFIG_NR_DRAM_BANKS 4 /* we have 2 banks of DRAM */ +#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */ +#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */ +#define PHYS_SDRAM_2 0xa4000000 /* SDRAM Bank #2 */ +#define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 MB */ +#define PHYS_SDRAM_3 0xa8000000 /* SDRAM Bank #3 */ +#define PHYS_SDRAM_3_SIZE 0x00000000 /* 0 MB */ +#define PHYS_SDRAM_4 0xac000000 /* SDRAM Bank #4 */ +#define PHYS_SDRAM_4_SIZE 0x00000000 /* 0 MB */ + +#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ + +#define CFG_DRAM_BASE 0xa0000000 +#define CFG_DRAM_SIZE 0x04000000 + +#define CFG_FLASH_BASE PHYS_FLASH_1 + +/* + * GPIO settings + */ +#define CFG_GPSR0_VAL 0x00018000 +#define CFG_GPSR1_VAL 0x00000000 +#define CFG_GPSR2_VAL 0x400dc000 +#define CFG_GPSR3_VAL 0x00000000 +#define CFG_GPCR0_VAL 0x00000000 +#define CFG_GPCR1_VAL 0x00000000 +#define CFG_GPCR2_VAL 0x00000000 +#define CFG_GPCR3_VAL 0x00000000 +#define CFG_GPDR0_VAL 0x00018000 +#define CFG_GPDR1_VAL 0x00028801 +#define CFG_GPDR2_VAL 0x520dc000 +#define CFG_GPDR3_VAL 0x0001E000 +#define CFG_GAFR0_L_VAL 0x801c0000 +#define CFG_GAFR0_U_VAL 0x00000013 +#define CFG_GAFR1_L_VAL 0x6990100A +#define CFG_GAFR1_U_VAL 0x00000008 +#define CFG_GAFR2_L_VAL 0xA0000000 +#define CFG_GAFR2_U_VAL 0x010900F2 +#define CFG_GAFR3_L_VAL 0x54000003 +#define CFG_GAFR3_U_VAL 0x00002401 +#define CFG_GRER0_VAL 0x00000000 +#define CFG_GRER1_VAL 0x00000000 +#define CFG_GRER2_VAL 0x00000000 +#define CFG_GRER3_VAL 0x00000000 +#define CFG_GFER0_VAL 0x00000000 +#define CFG_GFER1_VAL 0x00000000 +#define CFG_GFER2_VAL 0x00000000 +#define CFG_GFER3_VAL 0x00000020 + + +#define CFG_PSSR_VAL 0x20 /* CHECK */ + +/* + * Clock settings + */ +#define CFG_CKEN 0x01FFFFFF /* CHECK */ +#define CFG_CCCR 0x02000290 /* 520Mhz */ + +/* + * Memory settings + */ + +#define CFG_MSC0_VAL 0x4df84df0 +#define CFG_MSC1_VAL 0x7ff87ff4 +#define CFG_MSC2_VAL 0xa26936d4 +#define CFG_MDCNFG_VAL 0x880009C9 +#define CFG_MDREFR_VAL 0x20ca201e +#define CFG_MDMRS_VAL 0x00220022 + +#define CFG_FLYCNFG_VAL 0x00000000 +#define CFG_SXCNFG_VAL 0x40044004 + +/* + * PCMCIA and CF Interfaces + */ +#define CFG_MECR_VAL 0x00000001 +#define CFG_MCMEM0_VAL 0x00004204 +#define CFG_MCMEM1_VAL 0x00010204 +#define CFG_MCATT0_VAL 0x00010504 +#define CFG_MCATT1_VAL 0x00010504 +#define CFG_MCIO0_VAL 0x00008407 +#define CFG_MCIO1_VAL 0x0000c108 + +#define CONFIG_DRIVER_DM9000 1 +#define CONFIG_DRIVER_DM9000 1 +#define CONFIG_DM9000_BASE 0x08000000 +#define DM9000_IO CONFIG_DM9000_BASE +#define DM9000_DATA (CONFIG_DM9000_BASE+0x8004) +/* #define CONFIG_DM9000_USE_8BIT */ +/* #define CONFIG_DM9000_USE_16BIT */ +#define CONFIG_DM9000_USE_32BIT + +#define CONFIG_USB_OHCI_NEW 1 +#define CFG_USB_OHCI_BOARD_INIT 1 +#define CFG_USB_OHCI_MAX_ROOT_PORTS 3 +#define CFG_USB_OHCI_REGS_BASE 0x4C000000 +#define CFG_USB_OHCI_SLOT_NAME "trizepsiv" +#define CONFIG_USB_STORAGE 1 +#define CFG_USB_OHCI_CPU_INIT 1 + +/* + * FLASH and environment organization + */ + +#define CFG_FLASH_CFI +#define CFG_FLASH_CFI_DRIVER 1 + +#define CFG_MONITOR_BASE 0 +#define CFG_MONITOR_LEN 0x40000 + +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 4 + 255 /* max number of sectors on one chip */ + +/* timeout values are in ticks */ +#define CFG_FLASH_ERASE_TOUT (25*CFG_HZ) /* Timeout for Flash Erase */ +#define CFG_FLASH_WRITE_TOUT (25*CFG_HZ) /* Timeout for Flash Write */ + +/* write flash less slowly */ +#define CFG_FLASH_USE_BUFFER_WRITE 1 + +/* Flash environment locations */ +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_ADDR (PHYS_FLASH_1 + CFG_MONITOR_LEN) /* Addr of Environment Sector */ +#define CFG_ENV_SIZE 0x40000 /* Total Size of Environment */ +#define CFG_ENV_SECT_SIZE 0x40000 /* Total Size of Environment Sector */ + +/* Address and size of Redundant Environment Sector */ +#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR+CFG_ENV_SECT_SIZE) +#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) + +#endif /* __CONFIG_H */ From a89cbbd27a60e6740772000fd0688ffba1c2576a Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Fri, 7 Sep 2007 01:21:25 +0200 Subject: [PATCH 222/259] Update CHANGELOG, minor coding style cleanup. --- CHANGELOG | 539 +++++++++++++++++++++++++++++++++++ board/trizepsiv/pxavoltage.S | 2 - 2 files changed, 539 insertions(+), 2 deletions(-) diff --git a/CHANGELOG b/CHANGELOG index 2749d69c7..671c836b7 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -1,3 +1,542 @@ +commit 5e5803e119de3bebd76fc9a57baac0b5aeccc8a3 +Author: stefano babic +Date: Thu Aug 30 23:01:49 2007 +0200 + + PXA270: Added support for TrizepsIV board. + + This patch add support for the Trizeps IV module (520Mhz). + + Signed-off-by: Stefano Babic + +commit 80172c6181c912fbb34ea3ba0c22b232b419b47f +Author: stefano babic +Date: Thu Aug 30 22:57:04 2007 +0200 + + PXA270: Add support for multiple serial ports. + + This patch adds support for multiple serial ports to the PXA target. + FFUART, BTUART and STUART are supported. + + Signed-off-by: Stefano Babic + +commit 28bb3f72c687ac6b2eb076b01dd21a5fd657d45e +Author: stefano babic +Date: Thu Aug 30 22:48:47 2007 +0200 + + PXA270: fix compile issue (invalid lvalue) + + Code is broken for PXA270 due to "invalid lvalue in assignment". + + This patch fix it in pxa-regs.h + + Signed-off-by: Stefano Babic + +commit 1d2ca446e1a731df420206d04fe278c27ea6b8e8 +Author: Jason Jin +Date: Thu Aug 30 18:19:05 2007 +0800 + + Add BUILD_DIR support for bios emulator. + + Signed-off-by: Jason Jin + +commit b4d8a55145442f136982634862341a3e02002bda +Author: Shinya Kuribayashi +Date: Fri Aug 31 14:41:51 2007 +0900 + + [MIPS] Remove inline asm string functions + + Stop using inline string functions on MIPS as other ARCHs do so, + since the optimized inline asm versions are not small. + + This change is triggered by a following MIPS build error: + common/libcommon.a(exports.o)(.text+0xdc): In function `jumptable_init': + common/exports.c:32: undefined reference to `strcmp' + make: *** [u-boot] Error 1 + + Signed-off-by: Shinya Kuribayashi + +commit 8ea2c4e54833deaebc24c3ca6b7f21353c25b0f5 +Author: Shinya Kuribayashi +Date: Fri Aug 31 14:41:45 2007 +0900 + + [MIPS] Update asm string header + + This patches contains several bugfixes and cleanups in the latest upstream: + + - Don't include linux/config.h + - Remove buggy inline version of memscan. + - Merge with Linux 2.6.11-rc3. + - Fix undefined reference to strcpy in binfmt_misc caused by gcc 3.4. + - Goodbye mips64. 31704 lines of code bite the dust. + - Replace extern inline with static inline. + - Fix return value of strncpy. + - Remove a bunch more "$1" clobbers. + + Signed-off-by: Shinya Kuribayashi + +commit 5b729fb3bd98f49855d6bfc657c3fbae95f2adc2 +Author: Bartlomiej Sieka +Date: Tue Sep 4 17:31:22 2007 +0200 + + Fix do_bootm_linux() so that multi-file images with FDT blob boot. + + Fix incorrect blob address calculation in do_bootm_linux() that prevents + booting the kernel from a multi-file image (kernel + initrd + blob). + + Also, make minor updates to the U-Boot's output and to the coding style. + + Signed-off-by: Bartlomiej Sieka + +commit 041a2554ad619e80dce520c1a33210affcb6a3f2 +Author: Gary Jennejohn +Date: Fri Aug 31 14:29:04 2007 +0200 + + Add support for Sil680 IDE controller. + + o add drivers/sil680.c to support the Sil680 IDE-controller. + o drivers/Makefile: add sil680.o. + + Signed-off-by: Gary Jennejohn + +commit e79021223bc339df655e360645a52c457a74b067 +Author: Grant Likely +Date: Thu Sep 6 09:47:40 2007 -0600 + + bootm/fdt: Only process the fdt if an fdt address was provided + + Boards with CONFIG_OF_LIBFDT enabled are not able to boot old-style + kernels using the board info structure (instead of passing a device tree) + This change allows the old style booting to be used if the fdt argument + was not passed to 'bootm'. + + Signed-off-by: Grant Likely + Acked-by: Kim Phillips + +commit cf2817a84c2e9bea2c5dfc084bce2f2d2563ac43 +Author: Grant Likely +Date: Thu Sep 6 09:46:23 2007 -0600 + + Migrate 5xxx boards from CONFIG_OF_FLAT_TREE to CONFIG_OF_LIBFDT + + Affects boards: icecube (lite5200), jupiter, motionpro, tqm5200 + + Tested on: lite5200b + + Note: the fixup functions have not been moved to a common place. This + patch is targeted for immediate merging as in solves a build issue, but + the final name/location of the fixups is still subject to debate. I + propose to merge this now, and move the fixups in the next merge window + to be usable by all targets. + + Signed-off-by: Grant Likely + +commit 41bb76e941929f54a73206fb132f7a4c275543a3 +Author: Grant Likely +Date: Thu Sep 6 09:46:17 2007 -0600 + + libfdt: add convenience function fdt_find_and_setprop() + + Given the path to a node, fdt_find_and_setprop() allows a property value + to be set directly. + + Signed-off-by: Grant Likely + +commit 56a9270521baaa00e12639a978302a67f61ef060 +Author: Kumar Gala +Date: Thu Aug 30 16:18:18 2007 -0500 + + Fix ULI RTC support on MPC8544 DS + + The RTC on the M1575 ULI chipset requires a dummy read before + we are able to talk to the RTC. We accomplish this by adding a + second memory region to the PHB the ULI is on and read from it. + + The second region is added to maintain compatiabilty with Linux's + view of the PCI memory map. + + Signed-off-by: Kumar Gala + +commit f75e89e9b5714db2b0e80074071dfbdd6f59488a +Author: Ed Swarthout +Date: Thu Aug 30 01:58:48 2007 -0500 + + ft_board_setup update 85xx/86xx of pci/pcie bus-range property. + + pcie is now differentiated from pci. Add 8641 bus-range updates. + + Signed-off-by: Ed Swarthout + +commit 81b73dec16fd1227369a191e725e10044a9d56b8 +Author: Gary Jennejohn +Date: Fri Aug 31 15:21:46 2007 +0200 + + ppc4xx: (Re-)Enable CONFIG_PCI_PNP on AMCC 440EPx Sequoia + + The 440EPx has a problem when the PCI_CACHE_LINE_SIZE register is + set to non-zero, because it doesn't support MRM (memory-read- + multiple) correctly. We now added the possibility to configure + this register in the board config file, so that the default value + of 8 can be overridden. + + Here the details of this patch: + + o drivers_pci_auto.c: introduce CFG_PCI_CACHE_LINE_SIZE to allow + board-specific settings. As an example the sequoia board requires 0. + Idea from Stefan Roese . + o board/amcc/sequoia/init.S: add a TLB mapping at 0xE8000000 for the + PCI IO-space. Obtained from Stefan Roese . + o include/configs/sequoia.h: turn CONFIG_PCI_PNP back on and set + CFG_PCI_CACHE_LINE_SIZE to 0. + + Signed-off-by: Gary Jennejohn + Signed-off-by: Stefan Roese + +commit 60174746c668b309378a91488dded898e9553eae +Author: Wolfgang Denk +Date: Fri Aug 31 10:01:51 2007 +0200 + + Fix TFTP OACK code for short packets. + + The old code had a loop limit overflow bug which caused a semi- + infinite loop for small packets, because in "i + +commit ff13ac8c7bbebb238e339592de765c546dba1073 +Author: Wolfgang Denk +Date: Thu Aug 30 14:42:15 2007 +0200 + + Backout commit 8f1bc284 as it causes TFTP to fail. + + Signed-off-by: Wolfgang Denk + +commit 1900fbf255acba8b94fb442a16408ea85a1d46a6 +Author: Ed Swarthout +Date: Thu Aug 30 02:26:17 2007 -0500 + + Revert "Fix MPC8544DS PCIe3 scsi." + + This reverts commit 9468e680. + Commit 16e23c3f5da removing allocation of PCSRBAR is sufficient. + + Signed-off-by: Ed Swarthout + +commit 8f1bc28408ded213418d9bc0780c7d8fb8a03774 +Author: Grant Likely +Date: Wed Aug 29 18:26:24 2007 -0600 + + tftp: don't implicity trust the format of recevied packets + + The TFTP OACK code trusts that the incoming packet is formated as + ASCII text and can be processed by string functions. It also has a + loop limit overflow bug where if the packet length is less than 8, it + ends up looping over *all* of memory to find the 'blksize' string. + + This patch solves the problem by forcing the packet to be null + terminated and using strstr() to search for the sub string. + + Signed-off-by: Grant Likely + +commit 2602a5c40ae37ab965a4e240854fdaffb51328a4 +Author: Kim Phillips +Date: Wed Aug 29 09:06:05 2007 -0500 + + sbc8641: remove unused OF_FLAT_TREE_MAX_SIZE + + this had slipped through the cracks, since the sbc board was added + after I wrote the original patch to remove all these symbols, and + before it was merged. + + Signed-off-by: Kim Phillips + +commit c5bded3c88e48ae648a75d357dc81a8255fa81f1 +Author: Wolfgang Denk +Date: Wed Aug 29 14:05:30 2007 +0200 + + Add mii_init() prototype + + to get rid of a *lot* of compiler warnings. + + Signed-off-by: Wolfgang Denk + +commit 2d1f23aa1e74e4a8f8ffa67f246eb98c522dfd7f +Author: Wolfgang Denk +Date: Wed Aug 29 13:35:03 2007 +0200 + + Disable network support on cmi_mpc5xx board + + ..because it caused compiler errors and there seems to be no + board maintainer to take care of this. + + Signed-off-by: Wolfgang Denk + +commit 9468e6804b7e25b0f6f52e53f47bce3175400a16 +Author: Kumar Gala +Date: Mon Aug 20 09:44:00 2007 -0500 + + Fix MPC8544DS PCIe3 scsi. + + + + The problem is pciauto_setup_device() getting called from fsl_pci_init.c + is allocating memory space it doesn't need. + + Signed-off-by: Ed Swarthout + Signed-off-by: Andy Fleming + +commit 4bf4abb8a4e9955556b120a1aafa30c03e74032a +Author: Ed Swarthout +Date: Tue Aug 21 09:38:59 2007 -0500 + + 8548cds fixes + + Restore CONFIG_EXTRA_ENV_SETTINGS definition which contains the + correct consoledev needed for linux boot. + Standardize on fdt{file,addr} var to hold dtb file name. + + Set PCI inbound memory region from CFG_MEMORY_{BUS,PHYS}. + + Signed-off-by: Ed Swarthout + +commit 7a1ac419fa0d2d23ddd08bd61d16896a9f33c933 +Author: Haiying Wang +Date: Thu Aug 23 15:20:54 2007 -0400 + + Enable L2 cache for MPC8568MDS board + + The L2 cache size is 512KB for 8568, print out the correct informaiton. + + Signed-off-by: Haiying Wang + +commit 94c47fdaf14cb29fa3fb4d4da2efdd96c803b46b +Author: Jason Jin +Date: Wed Aug 22 17:54:49 2007 +0800 + + Remove the bios emulator binary files from MAI board + + Signed-off-by: Jason Jin + +commit 7608d75f9c87c9eb5b3a43219d0506d3e979a13f +Author: Kim Phillips +Date: Tue Aug 21 17:00:17 2007 -0500 + + support board vendor-common makefiles + + if a board/$(VENDOR)/common/Makefile exists, build it. + + also add the first such case, board/freescale/common/Makefile, to + handle building board-shared EEPROM, PIXIS, and MDS-PIB code, as + dictated by board configuration. + + thusly get rid of alternate build dir errors such as: + + FATAL: can't create /work/wd/tmp/u-boot-ppc/board/freescale/mpc8360emds/../common/pq-mds-pib.o: No such file or directory + + by putting the common/ mkdir command in its proper place (the common + Makefile). Common bits from existing individual board Makefiles have + been removed. + + Signed-off-by: Kim Phillips + +commit ef8f20752712dc1cdbd86f47e3bd6e35f81c83fd +Author: stefano babic +Date: Tue Aug 21 15:52:33 2007 +0200 + + Fix: TFTP is not working on little endian systems + + TFTP does not work anymore after multicast tftp + patch was applied on little endian systems. + This patch fix it. + + Signed-off-by: Stefano Babic + +commit 5f470948570526e9186f053a3003da7719604e90 +Author: stefano babic +Date: Tue Aug 21 15:50:33 2007 +0200 + + Fix MAC address setting in DM9000 driver. + + The logic to check if there is a correct MAC address in the DM9000 + EEPROM, added in the last patch, is wrong. Now the MAC address is + always taken from the environment, even if a suitable MAC is present + in the EEPROM. + + Signed-off-by: Stefano Babic + +commit 4a8527ef086ec7c89f40674ef024ae6f988a614a +Author: Martin Krause +Date: Tue Aug 21 12:40:34 2007 +0200 + + MPC5xxx: fix some compiler warnings in USB code + + Fix the following warnings: + - usb.c:xx: warning: function declaration isn't a prototype + - usb_ohci.c:xxx: warning: passing argument 1 of '__fswab32' makes integer + from pointer wihtout a cast + + Signed-off-by: Martin Krause + +commit 16e23c3f5dab6937f5109365416808c7f15c122b +Author: Ed Swarthout +Date: Mon Aug 20 23:55:33 2007 -0500 + + fsl_pci_init - Remove self PCSRBAR allocation + + CPU physical address space was being wasted by allocating a + PCSRBAR PCI inbound region to it's memory space. + + As a rule, PCSRBAR should be left alone since it does not affect + transactions from self and other masters may have changed it. + + Signed-off-by: Ed Swarthout + +commit 0e700ce03a23bb1921149bc77008ace7103d5289 +Author: Martin Krause +Date: Mon Aug 20 13:56:47 2007 +0200 + + Fix compiler warning in include/s3c2410.h + + This patch fixes the "type qualifiers ignored on fuction return tpye" + warning for include/s3c2410.h + + Signed-off-by: Martin Krause + +commit 9bb8b209ed2058a5756ecbeb544c067e44a42aea +Author: Dirk Behme +Date: Mon Aug 20 07:09:05 2007 +0200 + + Fix compilation error for omap2420h4_config. + + omap2420h4 switched to cfi, so remove old (already disabled) flash.c + and flash_probe() calls in env_flash.c. + + Signed-off-by: Dirk Behme + +commit 3bb342fc85d79dbb6b8c2039e7cdcddc82b8d90f +Author: Kim Phillips +Date: Fri Aug 10 14:34:14 2007 -0500 + + fdt: remove unused OF_FLAT_TREE_MAX_SIZE references + + and make some minor corrections to the FDT part of the README. + + Signed-off-by: Kim Phillips + +commit 6af2eeb1e99c2dcc584d4c5ab7fcae30a325f4de +Author: Wolfgang Denk +Date: Wed Aug 29 01:32:05 2007 +0200 + + Minor coding style cleanup. + + Signed-off-by: Wolfgang Denk + +commit a861558c65f65f1cf1302f3a35e9db7686b9e1a3 +Author: Heiko Schocher +Date: Tue Aug 28 17:40:33 2007 +0200 + + [UC101] Fix: if no CF in the board, U-Boot resets sometimes. + + Signed-off-by: Heiko Schocher + +commit f98984cb194bb34dbe1db9429d3b51133af30d07 +Author: Heiko Schocher +Date: Tue Aug 28 17:39:14 2007 +0200 + + IDE: - make ide_inb () and ide_outb () "weak", so boards can + define there own I/O functions. + (Needed for the pcs440ep board). + - The default I/O Functions are again 8 Bit accesses. + - Added CONFIG_CMD_IDE for the pcs440ep Board. + + Signed-off-by: Heiko Schocher + +commit 9c02defc29b57945b600714cf61ddfd02b02fb14 +Author: Yuri Tikhonov +Date: Sat Aug 25 05:07:16 2007 +0200 + + POST: limit memory test area to not touch global data anymore + + As experienced on lwmon5, on some boards the POST memory test can + corrupt the global data buffer (bd). This patch fixes this issue + by checking and limiting this area. + + Signed-off-by: Yuri Tikhonov + Signed-off-by: Stefan Roese + +commit 75e1a84d483e36be10e206e539b028c4889e1158 +Author: Stefan Roese +Date: Fri Aug 24 15:41:42 2007 +0200 + + ppc4xx: Add RTC POST test to lwmon5 board configuration + + Since this RTC POST test is taking quite a while to complete + it's only initiated upon special keypress same as the complete + memory POST. + + Signed-off-by: Stefan Roese + +commit d7bfa620037a6d2210159387571bdf93aa32c162 +Author: Stefan Roese +Date: Fri Aug 24 15:19:10 2007 +0200 + + ppc4xx: Change GPIO signal for watchdog triggering on lwmon5 + + Signed-off-by: Stefan Roese + +commit c25dd8fc25e9ca3695db996a257d9ba4dab414db +Author: Stefan Roese +Date: Thu Aug 23 11:02:37 2007 +0200 + + ppc4xx: Add support for 2nd I2C EEPROM on lwmon5 board + + This patch adds support for the 2nd EEPROM (AT24C128) on the lwmon5 + board. Now the "eeprom" command can be used to read/write from/to this + device. Additionally a new command was added "eepromwp" to en-/disable + the write-protect of this 2nd EEPROM. + + The 1st EEPROM is not affected by this write-protect command. + + Signed-off-by: Stefan Roese + +commit c64fb30e4c5976007d56fc1789c7a0666082b536 +Author: Stefan Roese +Date: Wed Aug 22 08:56:09 2007 +0200 + + ppc4xx: Remove unused option CFG_INIT_RAM_OCM + + Signed-off-by: Stefan Roese + +commit 3ad63878737a5a2b1e60825bf0a7d601d7a695e7 +Author: Stefan Roese +Date: Tue Aug 21 16:27:57 2007 +0200 + + ppc4xx: Add matrix kbd support to lwmon5 board (440EPx based) + + This patch adds support for the matrix keyboard on the lwmon5 board. + Since the implementation in the dsPCI is kind of compatible with the + "old" lwmon board, most of the code is copied from the lwmon + board directory. + + Signed-off-by: Stefan Roese + +commit 3e66c078003607a7d1d214c15a5f262bc1b4032f +Author: Wolfgang Denk +Date: Sun Aug 19 10:27:34 2007 +0200 + + Fix some build errors. + + Signed-off-by: Wolfgang Denk + +commit 05675735ef77dc23b5e0eb782bad1ff477b55e86 +Author: Wolfgang Denk +Date: Sat Aug 18 22:00:38 2007 +0200 + + Update CHANGELOG. + commit 79f240f7ecc0506b43ac50d1ea405ff6540d4d57 Author: Kim Phillips Date: Thu Aug 16 22:52:39 2007 -0500 diff --git a/board/trizepsiv/pxavoltage.S b/board/trizepsiv/pxavoltage.S index 5e411321f..9659c2b02 100644 --- a/board/trizepsiv/pxavoltage.S +++ b/board/trizepsiv/pxavoltage.S @@ -23,9 +23,7 @@ #include - .global initPXAvoltage initPXAvoltage: mov pc, lr - From 8d17979d0359492a822a0a409d26e3a3549b4cd4 Mon Sep 17 00:00:00 2001 From: Rafal Jaworowski Date: Fri, 7 Sep 2007 17:05:36 +0200 Subject: [PATCH 223/259] [MPC512x] Correct fixup relocation Signed-off-by: Rafal Jaworowski --- board/ads5121/u-boot.lds | 1 - cpu/mpc512x/config.mk | 2 +- 2 files changed, 1 insertion(+), 2 deletions(-) diff --git a/board/ads5121/u-boot.lds b/board/ads5121/u-boot.lds index 038d84955..34ceb0fda 100644 --- a/board/ads5121/u-boot.lds +++ b/board/ads5121/u-boot.lds @@ -51,7 +51,6 @@ SECTIONS { cpu/mpc512x/start.o (.text) *(.text) - *(.fixup) *(.got1) . = ALIGN(16); *(.rodata) diff --git a/cpu/mpc512x/config.mk b/cpu/mpc512x/config.mk index 8a07c5a3b..3259d53a1 100644 --- a/cpu/mpc512x/config.mk +++ b/cpu/mpc512x/config.mk @@ -19,7 +19,7 @@ # Foundation, Inc., 59 Temple Place, Suite 330, Boston, # MA 02111-1307 USA # -PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi +PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi -mrelocatable PLATFORM_CPPFLAGS += -DCONFIG_MPC512X -DCONFIG_E300 \ -ffixed-r2 -ffixed-r29 -msoft-float -mcpu=603e From 08e2e5fcd2e06670b62e1680a3934c0e55c72810 Mon Sep 17 00:00:00 2001 From: Grzegorz Bernacki Date: Fri, 7 Sep 2007 17:09:21 +0200 Subject: [PATCH 224/259] [MPC512x] Proper handling of larger frames in the FEC driver When frame larger than local RX buffer is received, it is split and handled by two buffer descriptors. Prior to this patch the FEC driver discarded contents of a buffer descriptor without the 'LAST' bit set, so the first part of the frame was lost in case of larger frames. This fix allows to safely combine the two pieces into the whole frame. Signed-off-by: Grzegorz Bernacki --- cpu/mpc512x/fec.c | 34 +++++++++++++++++++++------------- 1 file changed, 21 insertions(+), 13 deletions(-) diff --git a/cpu/mpc512x/fec.c b/cpu/mpc512x/fec.c index 3c142a9e5..810457617 100644 --- a/cpu/mpc512x/fec.c +++ b/cpu/mpc512x/fec.c @@ -32,6 +32,9 @@ int fec512x_miiphy_read(char *devname, uint8 phyAddr, uint8 regAddr, uint16 * re int fec512x_miiphy_write(char *devname, uint8 phyAddr, uint8 regAddr, uint16 data); int mpc512x_fec_init_phy(struct eth_device *dev, bd_t * bis); +static uchar rx_buff[FEC_MAX_PKT_SIZE]; +static int rx_buff_idx = 0; + /********************************************************************/ #if (DEBUG & 0x2) static void mpc512x_fec_phydump (char *devname) @@ -235,7 +238,7 @@ static int mpc512x_fec_init (struct eth_device *dev, bd_t * bis) fec->eth->op_pause = 0x00010020; /* Frame length=1518; MII mode */ - fec->eth->r_cntrl = 0x05ee000c; + fec->eth->r_cntrl = 0x05ee0024; /* Half-duplex, heartbeat disabled */ fec->eth->x_cntrl = 0x00000000; @@ -520,8 +523,7 @@ static int mpc512x_fec_recv (struct eth_device *dev) mpc512x_fec_priv *fec = (mpc512x_fec_priv *)dev->priv; volatile FEC_RBD *pRbd = &fec->bdBase->rbd[fec->rbdIndex]; unsigned long ievent; - int frame_length, len = 0; - uchar buff[FEC_MAX_PKT_SIZE]; + int frame_length = 0; #if (DEBUG & 0x1) printf ("mpc512x_fec_recv %d Start...\n", fec->rbdIndex); @@ -555,31 +557,37 @@ static int mpc512x_fec_recv (struct eth_device *dev) } if (!(pRbd->status & FEC_RBD_EMPTY)) { - if ((pRbd->status & FEC_RBD_LAST) && - !(pRbd->status & FEC_RBD_ERR) && + if (!(pRbd->status & FEC_RBD_ERR) && ((pRbd->dataLength - 4) > 14)) { /* * Get buffer size */ - frame_length = pRbd->dataLength - 4; - + if (pRbd->status & FEC_RBD_LAST) + frame_length = pRbd->dataLength - 4; + else + frame_length = pRbd->dataLength; #if (DEBUG & 0x20) { int i; - printf ("recv data hdr:"); + printf ("recv data length 0x%08x data hdr: ", + pRbd->dataLength); for (i = 0; i < 14; i++) printf ("%x ", *((uint8*)pRbd->dataPointer + i)); printf("\n"); } #endif - /* * Fill the buffer and pass it to upper layers */ - memcpy (buff, (void*)pRbd->dataPointer, frame_length); - NetReceive ((uchar*)buff, frame_length); - len = frame_length; + memcpy (&rx_buff[rx_buff_idx], (void*)pRbd->dataPointer, + frame_length - rx_buff_idx); + rx_buff_idx = frame_length; + + if (pRbd->status & FEC_RBD_LAST) { + NetReceive ((uchar*)rx_buff, frame_length); + rx_buff_idx = 0; + } } /* @@ -590,7 +598,7 @@ static int mpc512x_fec_recv (struct eth_device *dev) /* Try to fill Buffer Descriptors */ fec->eth->r_des_active = 0x01000000; /* Descriptor polling active */ - return len; + return frame_length; } /********************************************************************/ From ff7640c9ead8806b5d827f2b29f9cb2632add729 Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Fri, 7 Sep 2007 17:43:36 +0200 Subject: [PATCH 225/259] Fix typo in MAKEALL script. Signed-off-by: Wolfgang Denk --- MAKEALL | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/MAKEALL b/MAKEALL index 68bb1ad6b..2597d1fa3 100755 --- a/MAKEALL +++ b/MAKEALL @@ -341,7 +341,7 @@ LIST_85xx=" \ LIST_86xx=" \ MPC8641HPCN \ - SBC8641D \ + sbc8641d \ " ######################################################################### From 15ee4734e4e08003d73d9ead3ca80e2a0672e427 Mon Sep 17 00:00:00 2001 From: Grzegorz Bernacki Date: Fri, 7 Sep 2007 17:46:18 +0200 Subject: [PATCH 226/259] [PPC440SPe] Convert machine check exceptions handling Convert using fixup mechanism to suppressing MCK for the duration of config read/write transaction: while fixups work fine with the case of a precise exception, we identified a major drawback with this approach when there's an imprecise case. In this scenario there is the following race condition: the fixup is (by design) set to catch the instruction following the one actually causing the exception; if an interrupt (e.g. decrementer) happens between those two instructions, the ISR code is executed before the fixup handler the machine check is no longer protected by the fixup handler as it appears as within the ISR code. In consequence the fixup approach is being phased out and replaced with explicit suppressing of MCK during a PCIe config read/write cycle. Signed-off-by: Grzegorz Bernacki --- cpu/ppc4xx/440spe_pcie.c | 59 ++++++++++++++++++++++++---------------- cpu/ppc4xx/440spe_pcie.h | 16 ++--------- cpu/ppc4xx/traps.c | 6 ---- 3 files changed, 37 insertions(+), 44 deletions(-) diff --git a/cpu/ppc4xx/440spe_pcie.c b/cpu/ppc4xx/440spe_pcie.c index bf68cc1e9..2d0b4067a 100644 --- a/cpu/ppc4xx/440spe_pcie.c +++ b/cpu/ppc4xx/440spe_pcie.c @@ -40,31 +40,24 @@ enum { LNKW_X8 = 0x8 }; -static inline int pcie_in_8(const volatile unsigned char __iomem *addr) +static void pcie_dmer_disable(void) { - int ret; - - PCIE_IN(lbzx, ret, addr); - - return ret; + mtdcr (DCRN_PEGPL_CFG(DCRN_PCIE0_BASE), + mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE0_BASE)) | GPL_DMER_MASK_DISA); + mtdcr (DCRN_PEGPL_CFG(DCRN_PCIE1_BASE), + mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE1_BASE)) | GPL_DMER_MASK_DISA); + mtdcr (DCRN_PEGPL_CFG(DCRN_PCIE2_BASE), + mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE2_BASE)) | GPL_DMER_MASK_DISA); } -static inline int pcie_in_le16(const volatile unsigned short __iomem *addr) +static void pcie_dmer_enable(void) { - int ret; - - PCIE_IN(lhbrx, ret, addr) - - return ret; -} - -static inline unsigned pcie_in_le32(const volatile unsigned __iomem *addr) -{ - unsigned ret; - - PCIE_IN(lwbrx, ret, addr); - - return ret; + mtdcr (DCRN_PEGPL_CFG (DCRN_PCIE0_BASE), + mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE0_BASE)) & ~GPL_DMER_MASK_DISA); + mtdcr (DCRN_PEGPL_CFG (DCRN_PCIE1_BASE), + mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE1_BASE)) & ~GPL_DMER_MASK_DISA); + mtdcr (DCRN_PEGPL_CFG (DCRN_PCIE2_BASE), + mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE2_BASE)) & ~GPL_DMER_MASK_DISA); } @@ -81,17 +74,27 @@ static int pcie_read_config(struct pci_controller *hose, unsigned int devfn, devfn = PCI_BDF(0,0,0); offset += devfn << 4; + /* + * Reading from configuration space of non-existing device can + * generate transaction errors. For the read duration we suppress + * assertion of machine check exceptions to avoid those. + */ + pcie_dmer_disable (); + switch (len) { case 1: - *val = pcie_in_8(hose->cfg_data + offset); + *val = in_8(hose->cfg_data + offset); break; case 2: - *val = pcie_in_le16((u16 *)(hose->cfg_data + offset)); + *val = in_le16((u16 *)(hose->cfg_data + offset)); break; default: - *val = pcie_in_le32((u32*)(hose->cfg_data + offset)); + *val = in_le32((u32*)(hose->cfg_data + offset)); break; } + + pcie_dmer_enable (); + return 0; } @@ -107,6 +110,11 @@ static int pcie_write_config(struct pci_controller *hose, unsigned int devfn, devfn = PCI_BDF(0,0,0); offset += devfn << 4; + /* + * Suppress MCK exceptions, similar to pcie_read_config() + */ + pcie_dmer_disable (); + switch (len) { case 1: out_8(hose->cfg_data + offset, val); @@ -118,6 +126,9 @@ static int pcie_write_config(struct pci_controller *hose, unsigned int devfn, out_le32((u32 *)(hose->cfg_data + offset), val); break; } + + pcie_dmer_enable (); + return 0; } diff --git a/cpu/ppc4xx/440spe_pcie.h b/cpu/ppc4xx/440spe_pcie.h index eb7cecf82..38745eb79 100644 --- a/cpu/ppc4xx/440spe_pcie.h +++ b/cpu/ppc4xx/440spe_pcie.h @@ -38,6 +38,7 @@ #define DCRN_PEGPL_REGBAL(base) (base + 0x13) #define DCRN_PEGPL_REGMSK(base) (base + 0x14) #define DCRN_PEGPL_SPECIAL(base) (base + 0x15) +#define DCRN_PEGPL_CFG(base) (base + 0x16) /* * System DCRs (SDRs) @@ -161,20 +162,7 @@ mtdcr(DCRN_SDR0_CFGADDR, offset); \ mtdcr(DCRN_SDR0_CFGDATA,data);}) -#define PCIE_IN(opcode, ret, addr) \ - __asm__ __volatile__( \ - "sync\n" \ - #opcode " %0,0,%1\n" \ - "1: twi 0,%0,0\n" \ - "isync\n" \ - "b 3f\n" \ - "2: li %0,-1\n" \ - "3:\n" \ - ".section __ex_table,\"a\"\n" \ - ".balign 4\n" \ - ".long 1b,2b\n" \ - ".previous\n" \ - : "=r" (ret) : "r" (addr), "m" (*addr)); +#define GPL_DMER_MASK_DISA 0x02000000 int ppc440spe_init_pcie(void); int ppc440spe_init_pcie_rootport(int port); diff --git a/cpu/ppc4xx/traps.c b/cpu/ppc4xx/traps.c index f5365cb76..38b6f8955 100644 --- a/cpu/ppc4xx/traps.c +++ b/cpu/ppc4xx/traps.c @@ -151,12 +151,6 @@ MachineCheckException(struct pt_regs *regs) int uncorr_ecc = 0; #endif - /* Probing PCI(E) using config cycles may cause this exception - * when a device is not present. To gracefully recover in such - * scenarios config read/write routines need to be instrumented in - * order to return via fixup handler. For examples refer to - * pcie_in_8(), pcie_in_le16() and pcie_in_le32() - */ if ((fixup = search_exception_table(regs->nip)) != 0) { regs->nip = fixup; val = mfspr(MCSR); From 7f1913938984ef6c6a46cb53e003719196d9c5de Mon Sep 17 00:00:00 2001 From: Grzegorz Bernacki Date: Fri, 7 Sep 2007 18:20:23 +0200 Subject: [PATCH 227/259] [PPC440SPe] Improve PCIe configuration space access - correct configuration space mapping - correct bus numbering - better access to config space Prior to this patch, the 440SPe host/PCIe bridge was able to configure only the first device on the first bus. We now allow to configure up to 16 buses; also, scanning for devices behind the PCIe-PCIe bridge is supported, so peripheral devices farther in hierarchy can be identified. Signed-off-by: Grzegorz Bernacki --- board/amcc/katmai/init.S | 12 ++-- board/amcc/katmai/katmai.c | 9 +-- board/amcc/yucca/init.S | 12 ++-- board/amcc/yucca/yucca.c | 9 +-- cpu/ppc4xx/405gp_pci.c | 17 +++--- cpu/ppc4xx/440spe_pcie.c | 111 +++++++++++++++++++++++++++++-------- include/common.h | 2 +- include/configs/katmai.h | 10 ++-- include/configs/yucca.h | 10 ++-- 9 files changed, 130 insertions(+), 62 deletions(-) diff --git a/board/amcc/katmai/init.S b/board/amcc/katmai/init.S index 5202ae694..e3f3da6bd 100644 --- a/board/amcc/katmai/init.S +++ b/board/amcc/katmai/init.S @@ -67,9 +67,9 @@ tlbtabA: tlbentry(CFG_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xD, AC_R|AC_W|SA_G|SA_I) tlbentry(CFG_PCIE_BASE, SZ_16K, 0x20000000, 0xC, AC_R|AC_W|SA_G|SA_I) - tlbentry(CFG_PCIE0_CFGBASE, SZ_1K, 0x40000000, 0xC, AC_R|AC_W|SA_G|SA_I) - tlbentry(CFG_PCIE1_CFGBASE, SZ_1K, 0x80000000, 0xC, AC_R|AC_W|SA_G|SA_I) - tlbentry(CFG_PCIE2_CFGBASE, SZ_1K, 0xC0000000, 0xC, AC_R|AC_W|SA_G|SA_I) + tlbentry(CFG_PCIE0_CFGBASE, SZ_16M, 0x40000000, 0xC, AC_R|AC_W|SA_G|SA_I) + tlbentry(CFG_PCIE1_CFGBASE, SZ_16M, 0x80000000, 0xC, AC_R|AC_W|SA_G|SA_I) + tlbentry(CFG_PCIE2_CFGBASE, SZ_16M, 0xC0000000, 0xC, AC_R|AC_W|SA_G|SA_I) tlbentry(CFG_PCIE0_XCFGBASE, SZ_1K, 0x50000000, 0xC, AC_R|AC_W|SA_G|SA_I) tlbentry(CFG_PCIE1_XCFGBASE, SZ_1K, 0x90000000, 0xC, AC_R|AC_W|SA_G|SA_I) tlbentry(CFG_PCIE2_XCFGBASE, SZ_1K, 0xD0000000, 0xC, AC_R|AC_W|SA_G|SA_I) @@ -109,9 +109,9 @@ tlbtabB: tlbentry(CFG_PCI_MEMBASE, SZ_256M, 0x10000000, 0xC, AC_R|AC_W|SA_G|SA_I) tlbentry(CFG_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xD, AC_R|AC_W|SA_G|SA_I) - tlbentry(CFG_PCIE0_CFGBASE, SZ_1K, 0x00100000, 0xD, AC_R|AC_W|SA_G|SA_I) - tlbentry(CFG_PCIE1_CFGBASE, SZ_1K, 0x20100000, 0xD, AC_R|AC_W|SA_G|SA_I) - tlbentry(CFG_PCIE2_CFGBASE, SZ_1K, 0x40100000, 0xD, AC_R|AC_W|SA_G|SA_I) + tlbentry(CFG_PCIE0_CFGBASE, SZ_16M, 0x00000000, 0xD, AC_R|AC_W|SA_G|SA_I) + tlbentry(CFG_PCIE1_CFGBASE, SZ_16M, 0x20000000, 0xD, AC_R|AC_W|SA_G|SA_I) + tlbentry(CFG_PCIE2_CFGBASE, SZ_16M, 0x40000000, 0xD, AC_R|AC_W|SA_G|SA_I) tlbentry(CFG_PCIE0_XCFGBASE, SZ_1K, 0x10000000, 0xD, AC_R|AC_W|SA_G|SA_I) tlbentry(CFG_PCIE1_XCFGBASE, SZ_1K, 0x30000000, 0xD, AC_R|AC_W|SA_G|SA_I) tlbentry(CFG_PCIE2_XCFGBASE, SZ_1K, 0x50000000, 0xD, AC_R|AC_W|SA_G|SA_I) diff --git a/board/amcc/katmai/katmai.c b/board/amcc/katmai/katmai.c index b804d55f2..a9ae4a373 100644 --- a/board/amcc/katmai/katmai.c +++ b/board/amcc/katmai/katmai.c @@ -392,7 +392,7 @@ int katmai_pcie_card_present(int port) static struct pci_controller pcie_hose[3] = {{0},{0},{0}}; -void pcie_setup_hoses(void) +void pcie_setup_hoses(int busno) { struct pci_controller *hose; int i, bus; @@ -401,7 +401,7 @@ void pcie_setup_hoses(void) * assume we're called after the PCIX hose is initialized, which takes * bus ID 0 and therefore start numbering PCIe's from 1. */ - bus = 1; + bus = busno; for (i = 0; i <= 2; i++) { /* Check for katmai card presence */ if (!katmai_pcie_card_present(i)) @@ -418,8 +418,8 @@ void pcie_setup_hoses(void) hose = &pcie_hose[i]; hose->first_busno = bus; - hose->last_busno = bus; - bus++; + hose->last_busno = bus; + hose->current_busno = bus; /* setup mem resource */ pci_set_region(hose->regions + 0, @@ -443,6 +443,7 @@ void pcie_setup_hoses(void) * Config access can only go down stream */ hose->last_busno = pci_hose_scan(hose); + bus = hose->last_busno + 1; #endif } } diff --git a/board/amcc/yucca/init.S b/board/amcc/yucca/init.S index c92dcf7a5..67e8f8f3a 100644 --- a/board/amcc/yucca/init.S +++ b/board/amcc/yucca/init.S @@ -70,9 +70,9 @@ tlbtabA: tlbentry(CFG_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xD, AC_R|AC_W|SA_G|SA_I) tlbentry(CFG_PCIE_BASE, SZ_16K, 0x20000000, 0xC, AC_R|AC_W|SA_G|SA_I) - tlbentry(CFG_PCIE0_CFGBASE, SZ_1K, 0x40000000, 0xC, AC_R|AC_W|SA_G|SA_I) - tlbentry(CFG_PCIE1_CFGBASE, SZ_1K, 0x80000000, 0xC, AC_R|AC_W|SA_G|SA_I) - tlbentry(CFG_PCIE2_CFGBASE, SZ_1K, 0xC0000000, 0xC, AC_R|AC_W|SA_G|SA_I) + tlbentry(CFG_PCIE0_CFGBASE, SZ_16M, 0x40000000, 0xC, AC_R|AC_W|SA_G|SA_I) + tlbentry(CFG_PCIE1_CFGBASE, SZ_16M, 0x80000000, 0xC, AC_R|AC_W|SA_G|SA_I) + tlbentry(CFG_PCIE2_CFGBASE, SZ_16M, 0xC0000000, 0xC, AC_R|AC_W|SA_G|SA_I) tlbentry(CFG_PCIE0_XCFGBASE, SZ_1K, 0x50000000, 0xC, AC_R|AC_W|SA_G|SA_I) tlbentry(CFG_PCIE1_XCFGBASE, SZ_1K, 0x90000000, 0xC, AC_R|AC_W|SA_G|SA_I) tlbentry(CFG_PCIE2_XCFGBASE, SZ_1K, 0xD0000000, 0xC, AC_R|AC_W|SA_G|SA_I) @@ -112,9 +112,9 @@ tlbtabB: tlbentry(CFG_PCI_MEMBASE, SZ_256M, 0x10000000, 0xC, AC_R|AC_W|SA_G|SA_I) tlbentry(CFG_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xD, AC_R|AC_W|SA_G|SA_I) - tlbentry(CFG_PCIE0_CFGBASE, SZ_1K, 0x00100000, 0xD, AC_R|AC_W|SA_G|SA_I) - tlbentry(CFG_PCIE1_CFGBASE, SZ_1K, 0x20100000, 0xD, AC_R|AC_W|SA_G|SA_I) - tlbentry(CFG_PCIE2_CFGBASE, SZ_1K, 0x40100000, 0xD, AC_R|AC_W|SA_G|SA_I) + tlbentry(CFG_PCIE0_CFGBASE, SZ_16M, 0x00000000, 0xD, AC_R|AC_W|SA_G|SA_I) + tlbentry(CFG_PCIE1_CFGBASE, SZ_16M, 0x20000000, 0xD, AC_R|AC_W|SA_G|SA_I) + tlbentry(CFG_PCIE2_CFGBASE, SZ_16M, 0x40000000, 0xD, AC_R|AC_W|SA_G|SA_I) tlbentry(CFG_PCIE0_XCFGBASE, SZ_1K, 0x10000000, 0xD, AC_R|AC_W|SA_G|SA_I) tlbentry(CFG_PCIE1_XCFGBASE, SZ_1K, 0x30000000, 0xD, AC_R|AC_W|SA_G|SA_I) tlbentry(CFG_PCIE2_XCFGBASE, SZ_1K, 0x50000000, 0xD, AC_R|AC_W|SA_G|SA_I) diff --git a/board/amcc/yucca/yucca.c b/board/amcc/yucca/yucca.c index d08fcf356..252e4fe07 100644 --- a/board/amcc/yucca/yucca.c +++ b/board/amcc/yucca/yucca.c @@ -846,7 +846,7 @@ void yucca_setup_pcie_fpga_endpoint(int port) static struct pci_controller pcie_hose[3] = {{0},{0},{0}}; -void pcie_setup_hoses(void) +void pcie_setup_hoses(int busno) { struct pci_controller *hose; int i, bus; @@ -855,7 +855,7 @@ void pcie_setup_hoses(void) * assume we're called after the PCIX hose is initialized, which takes * bus ID 0 and therefore start numbering PCIe's from 1. */ - bus = 1; + bus = busno; for (i = 0; i <= 2; i++) { /* Check for yucca card presence */ if (!yucca_pcie_card_present(i)) @@ -874,8 +874,8 @@ void pcie_setup_hoses(void) hose = &pcie_hose[i]; hose->first_busno = bus; - hose->last_busno = bus; - bus++; + hose->last_busno = bus; + hose->current_busno = bus; /* setup mem resource */ pci_set_region(hose->regions + 0, @@ -899,6 +899,7 @@ void pcie_setup_hoses(void) * Config access can only go down stream */ hose->last_busno = pci_hose_scan(hose); + bus = hose->last_busno + 1; #endif } } diff --git a/cpu/ppc4xx/405gp_pci.c b/cpu/ppc4xx/405gp_pci.c index 28379298b..282e7a1ba 100644 --- a/cpu/ppc4xx/405gp_pci.c +++ b/cpu/ppc4xx/405gp_pci.c @@ -443,7 +443,7 @@ void pci_init_board(void) static struct pci_controller ppc440_hose = {0}; -void pci_440_init (struct pci_controller *hose) +int pci_440_init (struct pci_controller *hose) { int reg_num = 0; @@ -459,7 +459,7 @@ void pci_440_init (struct pci_controller *hose) if ((strap & SDR0_SDSTP1_PISE_MASK) == 0) { printf("PCI: SDR0_STRP1[PISE] not set.\n"); printf("PCI: Configuration aborted.\n"); - return; + return -1; } #elif defined(CONFIG_440GP) unsigned long strap; @@ -468,7 +468,7 @@ void pci_440_init (struct pci_controller *hose) if ((strap & CPC0_STRP1_PISE_MASK) == 0) { printf("PCI: CPC0_STRP1[PISE] not set.\n"); printf("PCI: Configuration aborted.\n"); - return; + return -1; } #endif #endif /* CONFIG_DISABLE_PISE_TEST */ @@ -477,7 +477,7 @@ void pci_440_init (struct pci_controller *hose) * PCI controller init *--------------------------------------------------------------------------*/ hose->first_busno = 0; - hose->last_busno = 0xff; + hose->last_busno = 0; /* PCI I/O space */ pci_set_region(hose->regions + reg_num++, @@ -515,7 +515,7 @@ void pci_440_init (struct pci_controller *hose) if (pci_pre_init (hose) == 0) { printf("PCI: Board-specific initialization failed.\n"); printf("PCI: Configuration aborted.\n"); - return; + return -1; } pci_register_hose( hose ); @@ -578,13 +578,16 @@ void pci_440_init (struct pci_controller *hose) #endif hose->last_busno = pci_hose_scan(hose); } + return hose->last_busno; } void pci_init_board(void) { - pci_440_init (&ppc440_hose); + int busno; + + busno = pci_440_init (&ppc440_hose); #if defined(CONFIG_440SPE) - pcie_setup_hoses(); + pcie_setup_hoses(busno + 1); #endif } diff --git a/cpu/ppc4xx/440spe_pcie.c b/cpu/ppc4xx/440spe_pcie.c index 2d0b4067a..158f1c559 100644 --- a/cpu/ppc4xx/440spe_pcie.c +++ b/cpu/ppc4xx/440spe_pcie.c @@ -40,6 +40,23 @@ enum { LNKW_X8 = 0x8 }; +static u8* pcie_get_base(struct pci_controller *hose, unsigned int devfn) +{ + u8 *base = (u8*)hose->cfg_data; + + /* use local configuration space for the first bus */ + if (PCI_BUS(devfn) == 0) { + if (hose->cfg_data == (u8*)CFG_PCIE0_CFGBASE) + base = (u8*)CFG_PCIE0_XCFGBASE; + if (hose->cfg_data == (u8*)CFG_PCIE1_CFGBASE) + base = (u8*)CFG_PCIE1_XCFGBASE; + if (hose->cfg_data == (u8*)CFG_PCIE2_CFGBASE) + base = (u8*)CFG_PCIE2_XCFGBASE; + } + + return base; +} + static void pcie_dmer_disable(void) { mtdcr (DCRN_PEGPL_CFG(DCRN_PCIE0_BASE), @@ -60,18 +77,35 @@ static void pcie_dmer_enable(void) mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE2_BASE)) & ~GPL_DMER_MASK_DISA); } - static int pcie_read_config(struct pci_controller *hose, unsigned int devfn, int offset, int len, u32 *val) { + u8 *address; *val = 0; + /* - * 440SPE implements only one function per port + * Bus numbers are relative to hose->first_busno */ - if (!((PCI_FUNC(devfn) == 0) && (PCI_DEV(devfn) == 1))) + devfn -= PCI_BDF(hose->first_busno, 0, 0); + + /* + * NOTICE: configuration space ranges are currenlty mapped only for + * the first 16 buses, so such limit must be imposed. In case more + * buses are required the TLB settings in board/amcc//init.S + * need to be altered accordingly (one bus takes 1 MB of memory space). + */ + if (PCI_BUS(devfn) >= 16) return 0; - devfn = PCI_BDF(0,0,0); + /* + * Only single device/single function is supported for the primary and + * secondary buses of the 440SPe host bridge. + */ + if ((!((PCI_FUNC(devfn) == 0) && (PCI_DEV(devfn) == 0))) && + ((PCI_BUS(devfn) == 0) || (PCI_BUS(devfn) == 1))) + return 0; + + address = pcie_get_base(hose, devfn); offset += devfn << 4; /* @@ -101,13 +135,24 @@ static int pcie_read_config(struct pci_controller *hose, unsigned int devfn, static int pcie_write_config(struct pci_controller *hose, unsigned int devfn, int offset, int len, u32 val) { + u8 *address; + /* - * 440SPE implements only one function per port + * Bus numbers are relative to hose->first_busno */ - if (!((PCI_FUNC(devfn) == 0) && (PCI_DEV(devfn) == 1))) + devfn -= PCI_BDF(hose->first_busno, 0, 0); + + /* + * Same constraints as in pcie_read_config(). + */ + if (PCI_BUS(devfn) >= 16) return 0; - devfn = PCI_BDF(0,0,0); + if ((!((PCI_FUNC(devfn) == 0) && (PCI_DEV(devfn) == 0))) && + ((PCI_BUS(devfn) == 0) || (PCI_BUS(devfn) == 1))) + return 0; + + address = pcie_get_base(hose, devfn); offset += devfn << 4; /* @@ -137,7 +182,7 @@ int pcie_read_config_byte(struct pci_controller *hose,pci_dev_t dev,int offset,u u32 v; int rv; - rv = pcie_read_config(hose, dev, offset, 1, &v); + rv = pcie_read_config(hose, dev, offset, 1, &v); *val = (u8)v; return rv; } @@ -794,12 +839,12 @@ void ppc440spe_setup_pcie_rootpoint(struct pci_controller *hose, int port) volatile void *rmbase = NULL; pci_set_ops(hose, - pcie_read_config_byte, - pcie_read_config_word, - pcie_read_config_dword, - pcie_write_config_byte, - pcie_write_config_word, - pcie_write_config_dword); + pcie_read_config_byte, + pcie_read_config_word, + pcie_read_config_dword, + pcie_write_config_byte, + pcie_write_config_word, + pcie_write_config_dword); switch (port) { case 0: @@ -822,14 +867,9 @@ void ppc440spe_setup_pcie_rootpoint(struct pci_controller *hose, int port) /* * Set bus numbers on our root port */ - if (ppc440spe_revB()) { - out_8((u8 *)mbase + PCI_PRIMARY_BUS, 0); - out_8((u8 *)mbase + PCI_SECONDARY_BUS, 1); - out_8((u8 *)mbase + PCI_SUBORDINATE_BUS, 1); - } else { - out_8((u8 *)mbase + PCI_PRIMARY_BUS, 0); - out_8((u8 *)mbase + PCI_SECONDARY_BUS, 0); - } + out_8((u8 *)mbase + PCI_PRIMARY_BUS, 0); + out_8((u8 *)mbase + PCI_SECONDARY_BUS, 1); + out_8((u8 *)mbase + PCI_SUBORDINATE_BUS, 1); /* * Set up outbound translation to hose->mem_space from PLB @@ -886,6 +926,29 @@ void ppc440spe_setup_pcie_rootpoint(struct pci_controller *hose, int port) in_le16((u16 *)(mbase + PCI_COMMAND)) | PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); printf("PCIE:%d successfully set as rootpoint\n",port); + + /* Set Device and Vendor Id */ + switch (port) { + case 0: + out_le16(mbase + 0x200, 0xaaa0); + out_le16(mbase + 0x202, 0xbed0); + break; + case 1: + out_le16(mbase + 0x200, 0xaaa1); + out_le16(mbase + 0x202, 0xbed1); + break; + case 2: + out_le16(mbase + 0x200, 0xaaa2); + out_le16(mbase + 0x202, 0xbed2); + break; + default: + out_le16(mbase + 0x200, 0xaaa3); + out_le16(mbase + 0x202, 0xbed3); + } + + /* Set Class Code to PCI-PCI bridge and Revision Id to 1 */ + out_le32(mbase + 0x208, 0x06040001); + } int ppc440spe_setup_pcie_endpoint(struct pci_controller *hose, int port) @@ -963,8 +1026,8 @@ int ppc440spe_setup_pcie_endpoint(struct pci_controller *hose, int port) /* Enable I/O, Mem, and Busmaster cycles */ out_le16((u16 *)(mbase + PCI_COMMAND), - in_le16((u16 *)(mbase + PCI_COMMAND)) | - PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); + in_le16((u16 *)(mbase + PCI_COMMAND)) | + PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); out_le16(mbase + 0x200,0xcaad); /* Setting vendor ID */ out_le16(mbase + 0x202,0xfeed); /* Setting device ID */ attempts = 10; diff --git a/include/common.h b/include/common.h index 9a5a0ab79..aca281bda 100644 --- a/include/common.h +++ b/include/common.h @@ -275,7 +275,7 @@ void pciinfo (int, int); # endif int is_pci_host (struct pci_controller *); #if defined(CONFIG_440SPE) - void pcie_setup_hoses(void); + void pcie_setup_hoses(int busno); #endif #endif diff --git a/include/configs/katmai.h b/include/configs/katmai.h index b6d0f519a..7834e3908 100644 --- a/include/configs/katmai.h +++ b/include/configs/katmai.h @@ -66,11 +66,11 @@ #define CFG_PCIE_BASE 0xe0000000 /* PCIe UTL regs */ #define CFG_PCIE0_CFGBASE 0xc0000000 -#define CFG_PCIE0_XCFGBASE 0xc0000400 -#define CFG_PCIE1_CFGBASE 0xc0001000 -#define CFG_PCIE1_XCFGBASE 0xc0001400 -#define CFG_PCIE2_CFGBASE 0xc0002000 -#define CFG_PCIE2_XCFGBASE 0xc0002400 +#define CFG_PCIE1_CFGBASE 0xc1000000 +#define CFG_PCIE2_CFGBASE 0xc2000000 +#define CFG_PCIE0_XCFGBASE 0xc3000000 +#define CFG_PCIE1_XCFGBASE 0xc3001000 +#define CFG_PCIE2_XCFGBASE 0xc3002000 /* System RAM mapped to PCI space */ #define CONFIG_PCI_SYS_MEM_BUS CFG_SDRAM_BASE diff --git a/include/configs/yucca.h b/include/configs/yucca.h index 906f046fa..323535aa9 100644 --- a/include/configs/yucca.h +++ b/include/configs/yucca.h @@ -68,11 +68,11 @@ #define CFG_PCIE_BASE 0xe0000000 /* PCIe UTL regs */ #define CFG_PCIE0_CFGBASE 0xc0000000 -#define CFG_PCIE0_XCFGBASE 0xc0000400 -#define CFG_PCIE1_CFGBASE 0xc0001000 -#define CFG_PCIE1_XCFGBASE 0xc0001400 -#define CFG_PCIE2_CFGBASE 0xc0002000 -#define CFG_PCIE2_XCFGBASE 0xc0002400 +#define CFG_PCIE1_CFGBASE 0xc1000000 +#define CFG_PCIE2_CFGBASE 0xc2000000 +#define CFG_PCIE0_XCFGBASE 0xc3000000 +#define CFG_PCIE1_XCFGBASE 0xc3001000 +#define CFG_PCIE2_XCFGBASE 0xc3002000 /* System RAM mapped to PCI space */ #define CONFIG_PCI_SYS_MEM_BUS CFG_SDRAM_BASE From 6efc1fc0b63e55f94c5bc61d8dd23c918e3bc778 Mon Sep 17 00:00:00 2001 From: Grzegorz Bernacki Date: Fri, 7 Sep 2007 18:35:37 +0200 Subject: [PATCH 228/259] [PPC440SPe] PCIe environment settings for Katmai and Yucca - 'pciconfighost' is set by default in order to be able to scan bridges behind the primary host/PCIe - 'pciscandelay' env variable is recognized to allow for user-controlled delay before the PCIe bus enumeration; some peripheral devices require a significant delay before they can be scanned (e.g. LSI8408E); without the delay they are not detected Signed-off-by: Grzegorz Bernacki --- board/amcc/katmai/katmai.c | 12 ++++++++++++ board/amcc/yucca/yucca.c | 12 ++++++++++++ include/configs/katmai.h | 3 ++- include/configs/yucca.h | 3 ++- 4 files changed, 28 insertions(+), 2 deletions(-) diff --git a/board/amcc/katmai/katmai.c b/board/amcc/katmai/katmai.c index a9ae4a373..afd60ece6 100644 --- a/board/amcc/katmai/katmai.c +++ b/board/amcc/katmai/katmai.c @@ -396,6 +396,8 @@ void pcie_setup_hoses(int busno) { struct pci_controller *hose; int i, bus; + char *env; + unsigned int delay; /* * assume we're called after the PCIX hose is initialized, which takes @@ -439,6 +441,16 @@ void pcie_setup_hoses(int busno) */ #else ppc440spe_setup_pcie_rootpoint(hose, i); + + env = getenv ("pciscandelay"); + if (env != NULL) { + delay = simple_strtoul (env, NULL, 10); + if (delay > 5) + printf ("Warning, expect noticable delay before PCIe" + "scan due to 'pciscandelay' value!\n"); + mdelay (delay * 1000); + } + /* * Config access can only go down stream */ diff --git a/board/amcc/yucca/yucca.c b/board/amcc/yucca/yucca.c index 252e4fe07..397b01873 100644 --- a/board/amcc/yucca/yucca.c +++ b/board/amcc/yucca/yucca.c @@ -850,6 +850,8 @@ void pcie_setup_hoses(int busno) { struct pci_controller *hose; int i, bus; + char *env; + unsigned int delay; /* * assume we're called after the PCIX hose is initialized, which takes @@ -895,6 +897,16 @@ void pcie_setup_hoses(int busno) */ #else ppc440spe_setup_pcie_rootpoint(hose, i); + + env = getenv ("pciscandelay"); + if (env != NULL) { + delay = simple_strtoul (env, NULL, 10); + if (delay > 5) + printf ("Warning, expect noticable delay before PCIe" + "scan due to 'pciscandelay' value!\n"); + mdelay (delay * 1000); + } + /* * Config access can only go down stream */ diff --git a/include/configs/katmai.h b/include/configs/katmai.h index 7834e3908..7908e5a47 100644 --- a/include/configs/katmai.h +++ b/include/configs/katmai.h @@ -201,6 +201,7 @@ "setenv filesize;saveenv\0" \ "upd=run load;run update\0" \ "kozio=bootm ffc60000\0" \ + "pciconfighost=1\0" \ "" #define CONFIG_BOOTCOMMAND "run flash_self" @@ -322,7 +323,7 @@ #define CONFIG_PCI /* include pci support */ #define CONFIG_PCI_PNP 1 /* do pci plug-and-play */ #define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */ -#undef CONFIG_PCI_CONFIG_HOST_BRIDGE +#define CONFIG_PCI_CONFIG_HOST_BRIDGE /* Board-specific PCI */ #define CFG_PCI_TARGET_INIT /* let board init pci target */ diff --git a/include/configs/yucca.h b/include/configs/yucca.h index 323535aa9..74033b4ae 100644 --- a/include/configs/yucca.h +++ b/include/configs/yucca.h @@ -182,6 +182,7 @@ "cp.b ${fileaddr} FFFB0000 ${filesize};" \ "setenv filesize;saveenv\0" \ "upd=run load;run update\0" \ + "pciconfighost=1\0" \ "" #define CONFIG_BOOTCOMMAND "run flash_self" @@ -297,7 +298,7 @@ #define CONFIG_PCI /* include pci support */ #define CONFIG_PCI_PNP 1 /* do pci plug-and-play */ #define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */ -#undef CONFIG_PCI_CONFIG_HOST_BRIDGE +#define CONFIG_PCI_CONFIG_HOST_BRIDGE /* Board-specific PCI */ #define CFG_PCI_TARGET_INIT /* let board init pci target */ From a7d7eca791a37f452c9da10fef4b31dd7aa9a622 Mon Sep 17 00:00:00 2001 From: Grant Likely Date: Fri, 7 Sep 2007 09:25:07 -0600 Subject: [PATCH 229/259] Bugfix: make bootm+libfdt compile on boards with no flash Signed-off-by: Grant Likely --- common/cmd_bootm.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/common/cmd_bootm.c b/common/cmd_bootm.c index 9f5e0b4ee..6ebedfbc8 100644 --- a/common/cmd_bootm.c +++ b/common/cmd_bootm.c @@ -834,9 +834,11 @@ do_bootm_linux (cmd_tbl_t *cmdtp, int flag, of_flat_tree += 4 - tail; } +#ifndef CFG_NO_FLASH /* move the blob if it is in flash (set of_data to !null) */ if (addr2info ((ulong)of_flat_tree) != NULL) of_data = (ulong)of_flat_tree; +#endif #if defined(CONFIG_OF_FLAT_TREE) From 1d9e31e04911a6bb7cc66dd91132c699101c32e2 Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Sun, 9 Sep 2007 21:21:33 +0200 Subject: [PATCH 230/259] Fix compile error in spc1920 config. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Markus Klotzbücher Signed-off-by: Wolfgang Denk --- include/configs/spc1920.h | 9 +-------- 1 file changed, 1 insertion(+), 8 deletions(-) diff --git a/include/configs/spc1920.h b/include/configs/spc1920.h index b4ab9ad97..2efc8f10e 100644 --- a/include/configs/spc1920.h +++ b/include/configs/spc1920.h @@ -31,14 +31,9 @@ #undef CONFIG_8xx_CONS_NONE #define CONFIG_MII -/* #define MII_DEBUG */ -/* #define CONFIG_FEC_ENET */ #undef CONFIG_ETHER_ON_FEC1 #define CONFIG_ETHER_ON_FEC2 #define FEC_ENET -/* #define CONFIG_FEC2_PHY_NORXERR */ -/* #define CFG_DISCOVER_PHY */ -/* #define CONFIG_PHY_ADDR 0x1 */ #define CONFIG_FEC2_PHY 1 #define CONFIG_BAUDRATE 19200 @@ -100,14 +95,12 @@ #define CONFIG_CMD_ECHO #define CONFIG_CMD_IMMAP #define CONFIG_CMD_JFFS2 +#define CONFIG_CMD_NET #define CONFIG_CMD_PING #define CONFIG_CMD_DHCP #define CONFIG_CMD_I2C #define CONFIG_CMD_MII -#undef CONFIG_CMD_NET - - /* * Miscellaneous configurable options */ From e251e00d0db4b36d1d2b7e38fec43a7296b529a2 Mon Sep 17 00:00:00 2001 From: Kyungmin Park Date: Mon, 10 Sep 2007 11:34:00 +0900 Subject: [PATCH 231/259] Remove compiler warning: target CPU does not support interworking Signed-off-by: Kyungmin Park --- cpu/arm1136/config.mk | 1 + 1 file changed, 1 insertion(+) diff --git a/cpu/arm1136/config.mk b/cpu/arm1136/config.mk index e39e7741c..6ab0dd35a 100644 --- a/cpu/arm1136/config.mk +++ b/cpu/arm1136/config.mk @@ -31,4 +31,5 @@ PLATFORM_CPPFLAGS += -march=armv5 # # ========================================================================= PLATFORM_CPPFLAGS +=$(call cc-option,-mapcs-32,-mabi=apcs-gnu) +PLATFORM_CPPFLAGS +=$(call cc-option,-mno-thumb-interwork,) PLATFORM_RELFLAGS +=$(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,)) From 7a888d6b3c32a126dbb504ef146bb4c26574ca7b Mon Sep 17 00:00:00 2001 From: Grzegorz Bernacki Date: Mon, 10 Sep 2007 17:39:08 +0200 Subject: [PATCH 232/259] [MPC512x] Streamline frame handling in the FEC driver - convert frame size settings to be derived from a single base - set frame size to the recommended default value Signed-off-by: Grzegorz Bernacki --- cpu/mpc512x/fec.c | 8 ++++---- cpu/mpc512x/fec.h | 7 +++++-- 2 files changed, 9 insertions(+), 6 deletions(-) diff --git a/cpu/mpc512x/fec.c b/cpu/mpc512x/fec.c index 810457617..675b7a2e0 100644 --- a/cpu/mpc512x/fec.c +++ b/cpu/mpc512x/fec.c @@ -32,7 +32,7 @@ int fec512x_miiphy_read(char *devname, uint8 phyAddr, uint8 regAddr, uint16 * re int fec512x_miiphy_write(char *devname, uint8 phyAddr, uint8 regAddr, uint16 data); int mpc512x_fec_init_phy(struct eth_device *dev, bd_t * bis); -static uchar rx_buff[FEC_MAX_PKT_SIZE]; +static uchar rx_buff[FEC_BUFFER_SIZE]; static int rx_buff_idx = 0; /********************************************************************/ @@ -237,8 +237,8 @@ static int mpc512x_fec_init (struct eth_device *dev, bd_t * bis) /* Set Opcode/Pause Duration Register */ fec->eth->op_pause = 0x00010020; - /* Frame length=1518; MII mode */ - fec->eth->r_cntrl = 0x05ee0024; + /* Frame length=1522; MII mode */ + fec->eth->r_cntrl = (FEC_MAX_FRAME_LEN << 16) | 0x24; /* Half-duplex, heartbeat disabled */ fec->eth->x_cntrl = 0x00000000; @@ -248,7 +248,7 @@ static int mpc512x_fec_init (struct eth_device *dev, bd_t * bis) /* Setup recv fifo start and buff size */ fec->eth->r_fstart = 0x500; - fec->eth->r_buff_size = 0x5e0; + fec->eth->r_buff_size = FEC_BUFFER_SIZE; /* Setup BD base addresses */ fec->eth->r_des_start = (uint32)fec->bdBase->rbd; diff --git a/cpu/mpc512x/fec.h b/cpu/mpc512x/fec.h index d2d877aa5..9c3850287 100644 --- a/cpu/mpc512x/fec.h +++ b/cpu/mpc512x/fec.h @@ -164,10 +164,13 @@ typedef enum { #define FEC_RBD_NUM 32 /* The user can adjust this value */ /* packet size limit */ -#define FEC_MAX_PKT_SIZE 1536 +#define FEC_MAX_FRAME_LEN 1522 /* recommended default value */ + +/* Buffer size must be evenly divisible by 16 */ +#define FEC_BUFFER_SIZE ((FEC_MAX_FRAME_LEN + 0x10) & (~0xf)) typedef struct { - uint8 frame[FEC_MAX_PKT_SIZE]; + uint8 frame[FEC_BUFFER_SIZE]; } mpc512x_frame; typedef struct { From 754bac48156f8958d8f6a53a51eda88ab5758929 Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Mon, 10 Sep 2007 20:42:31 +0200 Subject: [PATCH 233/259] Update version to match current state. Signed-off-by: Wolfgang Denk --- Makefile | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Makefile b/Makefile index 0371d4619..c1c64462f 100644 --- a/Makefile +++ b/Makefile @@ -22,9 +22,9 @@ # VERSION = 1 -PATCHLEVEL = 2 +PATCHLEVEL = 3 SUBLEVEL = 0 -EXTRAVERSION = +EXTRAVERSION = -rc1 U_BOOT_VERSION = $(VERSION).$(PATCHLEVEL).$(SUBLEVEL)$(EXTRAVERSION) VERSION_FILE = $(obj)include/version_autogenerated.h From 38c1ef728d19950414a8ab1ccfc53767848fa346 Mon Sep 17 00:00:00 2001 From: Sean MCGOOGAN Date: Mon, 10 Sep 2007 16:55:59 +0100 Subject: [PATCH 234/259] Allocate CPU Architecture Code for STMicroelectronics' ST200. Signed-off-by: Sean McGoogan --------------------------------------------------- --- include/image.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/image.h b/include/image.h index 2f575fd2d..432fa2239 100644 --- a/include/image.h +++ b/include/image.h @@ -77,6 +77,7 @@ #define IH_CPU_NIOS2 15 /* Nios-II */ #define IH_CPU_BLACKFIN 16 /* Blackfin */ #define IH_CPU_AVR32 17 /* AVR32 */ +#define IH_CPU_ST200 18 /* STMicroelectronics ST200 */ /* * Image Types From 6c2f4f388e8181655ea8b69343ea00b68aa6e8d0 Mon Sep 17 00:00:00 2001 From: Grzegorz Bernacki Date: Tue, 11 Sep 2007 12:57:52 +0200 Subject: [PATCH 235/259] [ppc4xx] Individual handling of sdram.c for bamboo_nand build Bamboo has a file sdram.c which needs special treatment when building in separate directory. It has to be linked to build directory otherwise it is not seen. Signed-off-by: Grzegorz Bernacki --- nand_spl/board/amcc/bamboo/Makefile | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/nand_spl/board/amcc/bamboo/Makefile b/nand_spl/board/amcc/bamboo/Makefile index 0df86f99d..8b5461dcf 100644 --- a/nand_spl/board/amcc/bamboo/Makefile +++ b/nand_spl/board/amcc/bamboo/Makefile @@ -84,6 +84,12 @@ $(obj)nand_ecc.c: @rm -f $(obj)nand_ecc.c ln -s $(SRCTREE)/drivers/nand/nand_ecc.c $(obj)nand_ecc.c +ifneq ($(OBJTREE), $(SRCTREE)) +$(obj)sdram.c: + @rm -f $(obj)sdram.c + ln -s $(SRCTREE)/nand_spl/board/$(BOARDDIR)/sdram.c $(obj)sdram.c +endif + ######################################################################### $(obj)%.o: $(obj)%.S From 38ad82da0c1180ecdeb212a8f4245e945bcc546e Mon Sep 17 00:00:00 2001 From: Grzegorz Bernacki Date: Tue, 11 Sep 2007 15:42:11 +0200 Subject: [PATCH 236/259] [GP3SSA] Add define CONFIG_MPC85XX_PCI2 in config file to allow u-boot to scan on second pci bus. Signed-off-by: Grzegorz Bernacki --- board/stxssa/stxssa.c | 9 ++++++--- include/configs/stxssa.h | 2 +- 2 files changed, 7 insertions(+), 4 deletions(-) diff --git a/board/stxssa/stxssa.c b/board/stxssa/stxssa.c index 588212415..9a2bfbef8 100644 --- a/board/stxssa/stxssa.c +++ b/board/stxssa/stxssa.c @@ -378,9 +378,12 @@ static struct pci_config_table pci_stxgp3_config_table[] = { #endif -static struct pci_controller hose = { +static struct pci_controller hose[] = { #ifndef CONFIG_PCI_PNP - config_table: pci_stxgp3_config_table, + { config_table: pci_stxgp3_config_table,}, +#ifdef CONFIG_MPC85XX_PCI2 + {}, +#endif #endif }; @@ -393,6 +396,6 @@ pci_init_board(void) #ifdef CONFIG_PCI extern void pci_mpc85xx_init(struct pci_controller *hose); - pci_mpc85xx_init(&hose); + pci_mpc85xx_init(hose); #endif /* CONFIG_PCI */ } diff --git a/include/configs/stxssa.h b/include/configs/stxssa.h index f32ff67d9..b41dafaf9 100644 --- a/include/configs/stxssa.h +++ b/include/configs/stxssa.h @@ -230,7 +230,7 @@ #define CFG_PCI2_IO_SIZE 0x01000000 /* 16M */ #if defined(CONFIG_PCI) /* PCI Ethernet card */ - +#define CONFIG_MPC85XX_PCI2 1 #define CONFIG_NET_MULTI #define CONFIG_PCI_PNP /* do pci plug-and-play */ From f34024d4a328e6edd906456da98d2c537155c4f7 Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Wed, 12 Sep 2007 00:48:57 +0200 Subject: [PATCH 237/259] Fix memory corruption problem on STX GP3 SSA Board. Signed-off-by: Wolfgang Denk --- board/stxssa/stxssa.c | 4 +++- board/stxssa/u-boot.lds | 1 + net/net.c | 4 ++-- 3 files changed, 6 insertions(+), 3 deletions(-) diff --git a/board/stxssa/stxssa.c b/board/stxssa/stxssa.c index 9a2bfbef8..9bacb98d8 100644 --- a/board/stxssa/stxssa.c +++ b/board/stxssa/stxssa.c @@ -381,9 +381,11 @@ static struct pci_config_table pci_stxgp3_config_table[] = { static struct pci_controller hose[] = { #ifndef CONFIG_PCI_PNP { config_table: pci_stxgp3_config_table,}, -#ifdef CONFIG_MPC85XX_PCI2 +#else {}, #endif +#ifdef CONFIG_MPC85XX_PCI2 + {}, #endif }; diff --git a/board/stxssa/u-boot.lds b/board/stxssa/u-boot.lds index 95ecf66a8..65e1bcfb1 100644 --- a/board/stxssa/u-boot.lds +++ b/board/stxssa/u-boot.lds @@ -145,6 +145,7 @@ SECTIONS . = ALIGN(256); __init_end = .; + . = .; __bss_start = .; .bss : { diff --git a/net/net.c b/net/net.c index c47610e74..cde26801b 100644 --- a/net/net.c +++ b/net/net.c @@ -541,11 +541,11 @@ restart: case NETLOOP_SUCCESS: if (NetBootFileXferSize > 0) { - char buf[10]; + char buf[20]; printf("Bytes transferred = %ld (%lx hex)\n", NetBootFileXferSize, NetBootFileXferSize); - sprintf(buf, "%lx", NetBootFileXferSize); + sprintf(buf, "%lX", NetBootFileXferSize); setenv("filesize", buf); sprintf(buf, "%lX", (unsigned long)load_addr); From 6e7b7b6ea1b6d04dbe96242eb6a0c1c664c98e8c Mon Sep 17 00:00:00 2001 From: Bartlomiej Sieka Date: Thu, 13 Sep 2007 18:21:48 +0200 Subject: [PATCH 238/259] cm5200: Fix a typo introduced by afaac86fe2948ac84cd9a12bbed883b3c683e7d9 Signed-off-by: Marian Balakowicz --- board/cm5200/cmd_cm5200.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/cm5200/cmd_cm5200.c b/board/cm5200/cmd_cm5200.c index 513c36553..354f2bf6e 100644 --- a/board/cm5200/cmd_cm5200.c +++ b/board/cm5200/cmd_cm5200.c @@ -27,7 +27,7 @@ #include #include -#ifdef CONFIG_CMD_BSB +#ifdef CONFIG_CMD_BSP int do_i2c(char *argv[]) { From 66b3f24d665be678a9dbb125b1e84185400f63b5 Mon Sep 17 00:00:00 2001 From: Dirk Behme Date: Sat, 15 Sep 2007 11:55:42 +0200 Subject: [PATCH 239/259] Make DECLARE_GLOBAL_DATA_PTR global for DaVinci As discussed in [1], DECLARE_GLOBAL_DATA_PTR has to be global and not function local. Signed-off-by: Dirk Behme [1] http://article.gmane.org/gmane.comp.boot-loaders.u-boot/31805 --- board/davinci/dv-evm/dv_board.c | 6 ++---- board/davinci/schmoogie/dv_board.c | 6 ++---- board/davinci/sonata/dv_board.c | 6 ++---- 3 files changed, 6 insertions(+), 12 deletions(-) diff --git a/board/davinci/dv-evm/dv_board.c b/board/davinci/dv-evm/dv_board.c index 604edb56c..dce821ba6 100644 --- a/board/davinci/dv-evm/dv_board.c +++ b/board/davinci/dv-evm/dv_board.c @@ -31,6 +31,8 @@ #define MACH_TYPE_DAVINCI_EVM 901 +DECLARE_GLOBAL_DATA_PTR; + extern void i2c_init(int speed, int slaveaddr); extern void timer_init(void); extern int eth_hw_init(void); @@ -115,8 +117,6 @@ void dsp_on(void) int board_init(void) { - DECLARE_GLOBAL_DATA_PTR; - /* arch number of the board */ gd->bd->bi_arch_number = MACH_TYPE_DAVINCI_EVM; @@ -202,8 +202,6 @@ int misc_init_r (void) int dram_init(void) { - DECLARE_GLOBAL_DATA_PTR; - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; diff --git a/board/davinci/schmoogie/dv_board.c b/board/davinci/schmoogie/dv_board.c index 9f271a166..0a07523b1 100644 --- a/board/davinci/schmoogie/dv_board.c +++ b/board/davinci/schmoogie/dv_board.c @@ -31,6 +31,8 @@ #define MACH_TYPE_SCHMOOGIE 1255 +DECLARE_GLOBAL_DATA_PTR; + extern void i2c_init(int speed, int slaveaddr); extern void timer_init(void); extern int eth_hw_init(void); @@ -115,8 +117,6 @@ void dsp_on(void) int board_init(void) { - DECLARE_GLOBAL_DATA_PTR; - /* arch number of the board */ gd->bd->bi_arch_number = MACH_TYPE_SCHMOOGIE; @@ -244,8 +244,6 @@ int misc_init_r (void) int dram_init(void) { - DECLARE_GLOBAL_DATA_PTR; - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; diff --git a/board/davinci/sonata/dv_board.c b/board/davinci/sonata/dv_board.c index 99857c427..cd2dac610 100644 --- a/board/davinci/sonata/dv_board.c +++ b/board/davinci/sonata/dv_board.c @@ -31,6 +31,8 @@ #define MACH_TYPE_SONATA 1254 +DECLARE_GLOBAL_DATA_PTR; + extern void i2c_init(int speed, int slaveaddr); extern void timer_init(void); extern int eth_hw_init(void); @@ -115,8 +117,6 @@ void dsp_on(void) int board_init(void) { - DECLARE_GLOBAL_DATA_PTR; - /* arch number of the board */ gd->bd->bi_arch_number = MACH_TYPE_SONATA; @@ -199,8 +199,6 @@ int misc_init_r (void) int dram_init(void) { - DECLARE_GLOBAL_DATA_PTR; - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; From 1218abf1b5817a39a82399b4b928b00750575bda Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Sat, 15 Sep 2007 20:48:41 +0200 Subject: [PATCH 240/259] Fix cases where DECLARE_GLOBAL_DATA_PTR was not declared as global Signed-off-by: Wolfgang Denk --- board/amcc/katmai/katmai.c | 4 ++-- board/amcc/taishan/taishan.c | 4 ++-- board/amcc/yucca/yucca.c | 4 ++-- board/bf533-ezkit/bf533-ezkit.c | 3 ++- board/bf533-stamp/bf533-stamp.c | 3 ++- board/bf537-stamp/bf537-stamp.c | 3 ++- board/bf561-ezkit/bf561-ezkit.c | 3 ++- board/freescale/mpc8313erdb/sdram.c | 3 ++- board/lpc2292sodimm/lpc2292sodimm.c | 7 +------ board/mpc7448hpc2/mpc7448hpc2.c | 4 ++-- board/mpc7448hpc2/tsi108_init.c | 4 ++-- board/mpl/vcma9/cmd_vcma9.c | 4 ++-- board/sbc2410x/sbc2410x.c | 5 +---- board/siemens/SMN42/smn42.c | 7 +------ board/tqm5200/tqm5200.c | 4 ++-- cpu/arm720t/serial.c | 2 -- cpu/bf533/serial.c | 1 - cpu/bf537/i2c.c | 3 ++- cpu/bf537/serial.c | 3 ++- cpu/bf561/serial.c | 3 ++- cpu/mcf532x/cpu.c | 4 ++-- cpu/mcf532x/speed.c | 4 ++-- cpu/mpc86xx/cpu_init.c | 3 ++- cpu/mpc86xx/speed.c | 2 +- cpu/mpc86xx/traps.c | 4 ++-- drivers/qe/qe.c | 7 ++----- drivers/usbdcore_mpc8xx.c | 3 ++- include/configs/atstk1002.h | 3 +-- lib_blackfin/board.c | 7 ++----- lib_blackfin/post.c | 10 ++-------- 30 files changed, 51 insertions(+), 70 deletions(-) diff --git a/board/amcc/katmai/katmai.c b/board/amcc/katmai/katmai.c index afd60ece6..a49066fcc 100644 --- a/board/amcc/katmai/katmai.c +++ b/board/amcc/katmai/katmai.c @@ -34,6 +34,8 @@ #undef PCIE_ENDPOINT /* #define PCIE_ENDPOINT 1 */ +DECLARE_GLOBAL_DATA_PTR; + int ppc440spe_init_pcie_rootport(int port); void ppc440spe_setup_pcie(struct pci_controller *hose, int port); @@ -322,8 +324,6 @@ int pci_pre_init(struct pci_controller * hose ) #if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) void pci_target_init(struct pci_controller * hose ) { - DECLARE_GLOBAL_DATA_PTR; - /*-------------------------------------------------------------------+ * Disable everything *-------------------------------------------------------------------*/ diff --git a/board/amcc/taishan/taishan.c b/board/amcc/taishan/taishan.c index bc976c752..f00397ed1 100644 --- a/board/amcc/taishan/taishan.c +++ b/board/amcc/taishan/taishan.c @@ -32,6 +32,8 @@ void show_reset_reg(void); #endif +DECLARE_GLOBAL_DATA_PTR; + int lcd_init(void); int board_early_init_f (void) @@ -266,8 +268,6 @@ int pci_pre_init(struct pci_controller * hose ) #if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) void pci_target_init(struct pci_controller * hose ) { - DECLARE_GLOBAL_DATA_PTR; - /*--------------------------------------------------------------------------+ * Disable everything *--------------------------------------------------------------------------*/ diff --git a/board/amcc/yucca/yucca.c b/board/amcc/yucca/yucca.c index 397b01873..d7cc384ba 100644 --- a/board/amcc/yucca/yucca.c +++ b/board/amcc/yucca/yucca.c @@ -34,6 +34,8 @@ #include "yucca.h" #include "../cpu/ppc4xx/440spe_pcie.h" +DECLARE_GLOBAL_DATA_PTR; + #undef PCIE_ENDPOINT /* #define PCIE_ENDPOINT 1 */ @@ -668,8 +670,6 @@ int pci_pre_init(struct pci_controller * hose ) #if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) void pci_target_init(struct pci_controller * hose ) { - DECLARE_GLOBAL_DATA_PTR; - /*-------------------------------------------------------------------+ * Disable everything *-------------------------------------------------------------------*/ diff --git a/board/bf533-ezkit/bf533-ezkit.c b/board/bf533-ezkit/bf533-ezkit.c index 1dd4a3fe2..98ed6f81d 100644 --- a/board/bf533-ezkit/bf533-ezkit.c +++ b/board/bf533-ezkit/bf533-ezkit.c @@ -30,6 +30,8 @@ #include "psd4256.h" #endif +DECLARE_GLOBAL_DATA_PTR; + int checkboard(void) { #if (BFIN_CPU == ADSP_BF531) @@ -46,7 +48,6 @@ int checkboard(void) long int initdram(int board_type) { - DECLARE_GLOBAL_DATA_PTR; #ifdef DEBUG int brate; char *tmp = getenv("baudrate"); diff --git a/board/bf533-stamp/bf533-stamp.c b/board/bf533-stamp/bf533-stamp.c index b9dff9917..69e425bf9 100644 --- a/board/bf533-stamp/bf533-stamp.c +++ b/board/bf533-stamp/bf533-stamp.c @@ -30,6 +30,8 @@ #include #include "bf533-stamp.h" +DECLARE_GLOBAL_DATA_PTR; + #define STATUS_LED_OFF 0 #define STATUS_LED_ON 1 @@ -55,7 +57,6 @@ int checkboard(void) long int initdram(int board_type) { - DECLARE_GLOBAL_DATA_PTR; #ifdef DEBUG printf("SDRAM attributes:\n"); printf diff --git a/board/bf537-stamp/bf537-stamp.c b/board/bf537-stamp/bf537-stamp.c index 919cef688..b3d8bda9b 100644 --- a/board/bf537-stamp/bf537-stamp.c +++ b/board/bf537-stamp/bf537-stamp.c @@ -32,6 +32,8 @@ #include #include "ether_bf537.h" +DECLARE_GLOBAL_DATA_PTR; + #define POST_WORD_ADDR 0xFF903FFC /* @@ -132,7 +134,6 @@ void cf_outsw(unsigned short *addr, unsigned short *sect_buf, int words) long int initdram(int board_type) { - DECLARE_GLOBAL_DATA_PTR; #ifdef DEBUG int brate; char *tmp = getenv("baudrate"); diff --git a/board/bf561-ezkit/bf561-ezkit.c b/board/bf561-ezkit/bf561-ezkit.c index 989b0194c..2ff44a715 100644 --- a/board/bf561-ezkit/bf561-ezkit.c +++ b/board/bf561-ezkit/bf561-ezkit.c @@ -29,6 +29,8 @@ #include #include +DECLARE_GLOBAL_DATA_PTR; + int checkboard(void) { printf("CPU: ADSP BF561\n"); @@ -39,7 +41,6 @@ int checkboard(void) long int initdram(int board_type) { - DECLARE_GLOBAL_DATA_PTR; #ifdef DEBUG int brate; char *tmp = getenv("baudrate"); diff --git a/board/freescale/mpc8313erdb/sdram.c b/board/freescale/mpc8313erdb/sdram.c index e6e84107e..16ec4bbf5 100644 --- a/board/freescale/mpc8313erdb/sdram.c +++ b/board/freescale/mpc8313erdb/sdram.c @@ -33,10 +33,11 @@ #include +DECLARE_GLOBAL_DATA_PTR; + #ifndef CFG_8313ERDB_BROKEN_PMC static void resume_from_sleep(void) { - DECLARE_GLOBAL_DATA_PTR; u32 magic = *(u32 *)0; typedef void (*func_t)(void); diff --git a/board/lpc2292sodimm/lpc2292sodimm.c b/board/lpc2292sodimm/lpc2292sodimm.c index d212c6332..9c2d1af2f 100644 --- a/board/lpc2292sodimm/lpc2292sodimm.c +++ b/board/lpc2292sodimm/lpc2292sodimm.c @@ -28,8 +28,7 @@ #include #include -/* ------------------------------------------------------------------------- */ - +DECLARE_GLOBAL_DATA_PTR; /* * Miscelaneous platform dependent initialisations @@ -37,8 +36,6 @@ int board_init (void) { - DECLARE_GLOBAL_DATA_PTR; - /* Activate LED flasher */ IO_LEDFLSH = 0x40; @@ -53,8 +50,6 @@ int board_init (void) int dram_init (void) { - DECLARE_GLOBAL_DATA_PTR; - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; diff --git a/board/mpc7448hpc2/mpc7448hpc2.c b/board/mpc7448hpc2/mpc7448hpc2.c index 63c99de17..81846eba7 100644 --- a/board/mpc7448hpc2/mpc7448hpc2.c +++ b/board/mpc7448hpc2/mpc7448hpc2.c @@ -38,6 +38,8 @@ extern void ft_cpu_setup (void *blob, bd_t *bd); #undef DEBUG +DECLARE_GLOBAL_DATA_PTR; + extern void flush_data_cache (void); extern void invalidate_l1_instruction_cache (void); extern void tsi108_init_f (void); @@ -46,8 +48,6 @@ int display_mem_map (void); void after_reloc (ulong dest_addr) { - DECLARE_GLOBAL_DATA_PTR; - /* * Jump to the main U-Boot board init code */ diff --git a/board/mpc7448hpc2/tsi108_init.c b/board/mpc7448hpc2/tsi108_init.c index 8a7efef77..30ae17d87 100644 --- a/board/mpc7448hpc2/tsi108_init.c +++ b/board/mpc7448hpc2/tsi108_init.c @@ -33,6 +33,8 @@ #include #include +DECLARE_GLOBAL_DATA_PTR; + extern void mpicInit (int verbose); /* @@ -141,7 +143,6 @@ unsigned long get_board_bus_clk (void) int board_early_init_f (void) { - DECLARE_GLOBAL_DATA_PTR; ulong i; gd->mem_clk = 0; @@ -583,7 +584,6 @@ unsigned long get_l2cr (void) int misc_init_r (void) { - DECLARE_GLOBAL_DATA_PTR; #ifdef CFG_CLK_SPREAD /* Initialize Spread-Spectrum Clock generation */ ulong i; diff --git a/board/mpl/vcma9/cmd_vcma9.c b/board/mpl/vcma9/cmd_vcma9.c index 44b411255..227c49272 100644 --- a/board/mpl/vcma9/cmd_vcma9.c +++ b/board/mpl/vcma9/cmd_vcma9.c @@ -40,6 +40,8 @@ static uchar cs8900_chksum(ushort data) #endif +DECLARE_GLOBAL_DATA_PTR; + extern void print_vcma9_info(void); extern int vcma9_cantest(int); extern int vcma9_nandtest(void); @@ -53,8 +55,6 @@ extern int do_mplcommon(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); int do_vcma9(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { - DECLARE_GLOBAL_DATA_PTR; - if (strcmp(argv[1], "info") == 0) { print_vcma9_info(); diff --git a/board/sbc2410x/sbc2410x.c b/board/sbc2410x/sbc2410x.c index b4865e122..6c894a386 100644 --- a/board/sbc2410x/sbc2410x.c +++ b/board/sbc2410x/sbc2410x.c @@ -35,7 +35,7 @@ #include #endif -/* ------------------------------------------------------------------------- */ +DECLARE_GLOBAL_DATA_PTR; #define FCLK_SPEED 1 @@ -74,7 +74,6 @@ static inline void delay (unsigned long loops) int board_init (void) { - DECLARE_GLOBAL_DATA_PTR; S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER(); S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO(); @@ -128,8 +127,6 @@ int board_init (void) int dram_init (void) { - DECLARE_GLOBAL_DATA_PTR; - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; diff --git a/board/siemens/SMN42/smn42.c b/board/siemens/SMN42/smn42.c index cbfc76c46..52d1d7e5f 100644 --- a/board/siemens/SMN42/smn42.c +++ b/board/siemens/SMN42/smn42.c @@ -31,8 +31,7 @@ #include #include -/* ------------------------------------------------------------------------- */ - +DECLARE_GLOBAL_DATA_PTR; /* * Miscellaneous platform dependent initialisations @@ -40,8 +39,6 @@ int board_init (void) { - DECLARE_GLOBAL_DATA_PTR; - /* arch number MACH_TYPE_ARMADILLO - not official*/ gd->bd->bi_arch_number = 83; @@ -53,8 +50,6 @@ int board_init (void) int dram_init (void) { - DECLARE_GLOBAL_DATA_PTR; - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; diff --git a/board/tqm5200/tqm5200.c b/board/tqm5200/tqm5200.c index 21f67aa4e..29d6f0042 100644 --- a/board/tqm5200/tqm5200.c +++ b/board/tqm5200/tqm5200.c @@ -43,6 +43,8 @@ #include "mt48lc16m16a2-75.h" #endif +DECLARE_GLOBAL_DATA_PTR; + #ifdef CONFIG_PS2MULT void ps2mult_early_init(void); #endif @@ -477,8 +479,6 @@ int silent_boot (void) int board_early_init_f (void) { - DECLARE_GLOBAL_DATA_PTR; - if (silent_boot()) gd->flags |= GD_FLG_SILENT; diff --git a/cpu/arm720t/serial.c b/cpu/arm720t/serial.c index 15c54af08..27eb73ad8 100644 --- a/cpu/arm720t/serial.c +++ b/cpu/arm720t/serial.c @@ -129,8 +129,6 @@ serial_puts (const char *s) void serial_setbrg (void) { - DECLARE_GLOBAL_DATA_PTR; - unsigned short divisor = 0; switch (gd->baudrate) { diff --git a/cpu/bf533/serial.c b/cpu/bf533/serial.c index 6cab5daac..8ac6e3ff6 100644 --- a/cpu/bf533/serial.c +++ b/cpu/bf533/serial.c @@ -76,7 +76,6 @@ void calc_baud(void) void serial_setbrg(void) { int i; - DECLARE_GLOBAL_DATA_PTR; calc_baud(); diff --git a/cpu/bf537/i2c.c b/cpu/bf537/i2c.c index 3b0d026e0..0daba63b6 100644 --- a/cpu/bf537/i2c.c +++ b/cpu/bf537/i2c.c @@ -22,6 +22,8 @@ #include #include +DECLARE_GLOBAL_DATA_PTR; + #define bfin_read16(addr) ({ unsigned __v; \ __asm__ __volatile__ (\ "%0 = w[%1] (z);\n\t"\ @@ -68,7 +70,6 @@ #ifdef DEBUG_I2C #define PRINTD(fmt,args...) do { \ - DECLARE_GLOBAL_DATA_PTR; \ if (gd->have_console) \ printf(fmt ,##args); \ } while (0) diff --git a/cpu/bf537/serial.c b/cpu/bf537/serial.c index e04d08a0e..f7a2483ff 100644 --- a/cpu/bf537/serial.c +++ b/cpu/bf537/serial.c @@ -52,6 +52,8 @@ #include #include "serial.h" +DECLARE_GLOBAL_DATA_PTR; + unsigned long pll_div_fact; void calc_baud(void) @@ -74,7 +76,6 @@ void calc_baud(void) void serial_setbrg(void) { int i; - DECLARE_GLOBAL_DATA_PTR; calc_baud(); diff --git a/cpu/bf561/serial.c b/cpu/bf561/serial.c index 7f5c69536..bc5a4f572 100644 --- a/cpu/bf561/serial.c +++ b/cpu/bf561/serial.c @@ -52,6 +52,8 @@ #include "serial.h" #include +DECLARE_GLOBAL_DATA_PTR; + unsigned long pll_div_fact; void calc_baud(void) @@ -74,7 +76,6 @@ void calc_baud(void) void serial_setbrg(void) { int i; - DECLARE_GLOBAL_DATA_PTR; calc_baud(); diff --git a/cpu/mcf532x/cpu.c b/cpu/mcf532x/cpu.c index 520f5d693..2f62e956c 100644 --- a/cpu/mcf532x/cpu.c +++ b/cpu/mcf532x/cpu.c @@ -31,6 +31,8 @@ #include +DECLARE_GLOBAL_DATA_PTR; + int do_reset(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char *argv[]) { volatile wdog_t *wdp = (wdog_t *) (MMAP_WDOG); @@ -48,8 +50,6 @@ int do_reset(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char *argv[]) int checkcpu(void) { - DECLARE_GLOBAL_DATA_PTR; - volatile ccm_t *ccm = (ccm_t *) MMAP_CCM; u16 msk; u16 id = 0; diff --git a/cpu/mcf532x/speed.c b/cpu/mcf532x/speed.c index cf72609b4..001b9f42d 100644 --- a/cpu/mcf532x/speed.c +++ b/cpu/mcf532x/speed.c @@ -30,6 +30,8 @@ #include +DECLARE_GLOBAL_DATA_PTR; + /* PLL min/max specifications */ #define MAX_FVCO 500000 /* KHz */ #define MAX_FSYS 80000 /* KHz */ @@ -208,8 +210,6 @@ int clock_pll(int fsys, int flags) */ int get_clocks(void) { - DECLARE_GLOBAL_DATA_PTR; - gd->bus_clk = clock_pll(CFG_CLK / 1000, 0) * 1000; gd->cpu_clk = (gd->bus_clk * 3); return (0); diff --git a/cpu/mpc86xx/cpu_init.c b/cpu/mpc86xx/cpu_init.c index c8e466669..4f8956e0a 100644 --- a/cpu/mpc86xx/cpu_init.c +++ b/cpu/mpc86xx/cpu_init.c @@ -29,6 +29,8 @@ #include #include +DECLARE_GLOBAL_DATA_PTR; + /* * Breathe some life into the CPU... * @@ -38,7 +40,6 @@ void cpu_init_f(void) { - DECLARE_GLOBAL_DATA_PTR; volatile immap_t *immap = (immap_t *)CFG_IMMR; volatile ccsr_lbc_t *memctl = &immap->im_lbc; diff --git a/cpu/mpc86xx/speed.c b/cpu/mpc86xx/speed.c index 312ca1282..23161ca8c 100644 --- a/cpu/mpc86xx/speed.c +++ b/cpu/mpc86xx/speed.c @@ -29,6 +29,7 @@ #include #include +DECLARE_GLOBAL_DATA_PTR; void get_sys_info(sys_info_t *sysInfo) { @@ -96,7 +97,6 @@ void get_sys_info(sys_info_t *sysInfo) int get_clocks(void) { - DECLARE_GLOBAL_DATA_PTR; sys_info_t sys_info; get_sys_info(&sys_info); diff --git a/cpu/mpc86xx/traps.c b/cpu/mpc86xx/traps.c index c84bfbf6a..04c2e1331 100644 --- a/cpu/mpc86xx/traps.c +++ b/cpu/mpc86xx/traps.c @@ -34,6 +34,8 @@ #include #include +DECLARE_GLOBAL_DATA_PTR; + #if defined(CONFIG_CMD_KGDB) int (*debugger_exception_handler)(struct pt_regs *) = 0; #endif @@ -50,8 +52,6 @@ extern unsigned long search_exception_table(unsigned long); void print_backtrace(unsigned long *sp) { - DECLARE_GLOBAL_DATA_PTR; - int cnt = 0; unsigned long i; diff --git a/drivers/qe/qe.c b/drivers/qe/qe.c index 0f5232a72..7559e9222 100644 --- a/drivers/qe/qe.c +++ b/drivers/qe/qe.c @@ -30,6 +30,8 @@ qe_map_t *qe_immr = NULL; static qe_snum_t snums[QE_NUM_OF_SNUM]; +DECLARE_GLOBAL_DATA_PTR; + void qe_issue_cmd(uint cmd, uint sbc, u8 mcn, u32 cmd_data) { u32 cecr; @@ -51,8 +53,6 @@ void qe_issue_cmd(uint cmd, uint sbc, u8 mcn, u32 cmd_data) uint qe_muram_alloc(uint size, uint align) { - DECLARE_GLOBAL_DATA_PTR; - uint retloc; uint align_mask, off; uint savebase; @@ -158,8 +158,6 @@ void qe_put_snum(u8 snum) void qe_init(uint qe_base) { - DECLARE_GLOBAL_DATA_PTR; - /* Init the QE IMMR base */ qe_immr = (qe_map_t *)qe_base; @@ -204,7 +202,6 @@ void qe_assign_page(uint snum, uint para_ram_base) int qe_set_brg(uint brg, uint rate) { - DECLARE_GLOBAL_DATA_PTR; volatile uint *bp; u32 divisor; int div16 = 0; diff --git a/drivers/usbdcore_mpc8xx.c b/drivers/usbdcore_mpc8xx.c index e87284b17..d4c409656 100644 --- a/drivers/usbdcore_mpc8xx.c +++ b/drivers/usbdcore_mpc8xx.c @@ -64,6 +64,8 @@ #include "usbdcore_mpc8xx.h" #include "usbdcore_ep0.h" +DECLARE_GLOBAL_DATA_PTR; + #define ERR(fmt, args...)\ serial_printf("ERROR : [%s] %s:%d: "fmt,\ __FILE__,__FUNCTION__,__LINE__, ##args) @@ -1216,7 +1218,6 @@ static void mpc8xx_udc_clock_init (volatile immap_t * immr, #elif defined(CFG_USB_BRGCLK) /* This has been tested with brgclk == 50MHz */ - DECLARE_GLOBAL_DATA_PTR; int divisor = 0; if (gd->cpu_clk < 48000000L) { diff --git a/include/configs/atstk1002.h b/include/configs/atstk1002.h index e1d8f74c5..75b153e4a 100644 --- a/include/configs/atstk1002.h +++ b/include/configs/atstk1002.h @@ -183,10 +183,9 @@ #define CFG_LONGHELP 1 #define CFG_MEMTEST_START \ - ({ DECLARE_GLOBAL_DATA_PTR; gd->bd->bi_dram[0].start; }) + ({ gd->bd->bi_dram[0].start; }) #define CFG_MEMTEST_END \ ({ \ - DECLARE_GLOBAL_DATA_PTR; \ gd->bd->bi_dram[0].start + gd->bd->bi_dram[0].size; \ }) #define CFG_BAUDRATE_TABLE { 115200, 38400, 19200, 9600, 2400 } diff --git a/lib_blackfin/board.c b/lib_blackfin/board.c index 36a969e73..7c9990f8e 100644 --- a/lib_blackfin/board.c +++ b/lib_blackfin/board.c @@ -42,6 +42,8 @@ int post_flag; #endif +DECLARE_GLOBAL_DATA_PTR; + #ifndef CFG_NO_FLASH extern flash_info_t flash_info[]; #endif @@ -126,8 +128,6 @@ static void display_flash_config(ulong size) static int init_baudrate(void) { - DECLARE_GLOBAL_DATA_PTR; - char tmp[64]; int i = getenv_r("baudrate", tmp, sizeof(tmp)); gd->bd->bi_baudrate = gd->baudrate = (i > 0) @@ -139,7 +139,6 @@ static int init_baudrate(void) #ifdef DEBUG static void display_global_data(void) { - DECLARE_GLOBAL_DATA_PTR; bd_t *bd; bd = gd->bd; printf("--flags:%x\n", gd->flags); @@ -256,7 +255,6 @@ void init_cplbtables(void) void board_init_f(ulong bootflag) { - DECLARE_GLOBAL_DATA_PTR; ulong addr; bd_t *bd; int i; @@ -325,7 +323,6 @@ static int init_func_i2c(void) void board_init_r(gd_t * id, ulong dest_addr) { - DECLARE_GLOBAL_DATA_PTR; ulong size; extern void malloc_bin_reloc(void); char *s, *e; diff --git a/lib_blackfin/post.c b/lib_blackfin/post.c index 7c9478def..3c4d5c51d 100644 --- a/lib_blackfin/post.c +++ b/lib_blackfin/post.c @@ -32,14 +32,14 @@ #ifdef CONFIG_POST +DECLARE_GLOBAL_DATA_PTR; + #define POST_MAX_NUMBER 32 #define BOOTMODE_MAGIC 0xDEAD0000 int post_init_f(void) { - DECLARE_GLOBAL_DATA_PTR; - int res = 0; unsigned int i; @@ -62,7 +62,6 @@ int post_init_f(void) void post_bootmode_init(void) { - DECLARE_GLOBAL_DATA_PTR; int bootmode = post_bootmode_get(0); int newword; @@ -109,20 +108,17 @@ int post_bootmode_get(unsigned int *last_test) /* POST tests run before relocation only mark status bits .... */ static void post_log_mark_start(unsigned long testid) { - DECLARE_GLOBAL_DATA_PTR; gd->post_log_word |= (testid) << 16; } static void post_log_mark_succ(unsigned long testid) { - DECLARE_GLOBAL_DATA_PTR; gd->post_log_word |= testid; } /* ... and the messages are output once we are relocated */ void post_output_backlog(void) { - DECLARE_GLOBAL_DATA_PTR; int j; for (j = 0; j < post_list_size; j++) { @@ -372,8 +368,6 @@ int post_log(char *format, ...) void post_reloc(void) { - DECLARE_GLOBAL_DATA_PTR; - unsigned int i; /* From e21659e30660a1377c42af135a6114efe39801d9 Mon Sep 17 00:00:00 2001 From: Sam Sparks Date: Fri, 14 Sep 2007 11:14:42 -0600 Subject: [PATCH 241/259] Update MPC8349ITX*_config to place config.tmp in right place. MPC834ITX*_config does not store config.tmp at the correct locatation, causing MPC8349ITXGP to have the wrong TEXT_BASE. Signed-off-by: Sam Sparks Signed-off-by: Grant Likely --- Makefile | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/Makefile b/Makefile index c1c64462f..85885b166 100644 --- a/Makefile +++ b/Makefile @@ -1794,13 +1794,13 @@ MPC8349ITX_config \ MPC8349ITX_LOWBOOT_config \ MPC8349ITXGP_config: unconfig @mkdir -p $(obj)include - @mkdir -p $(obj)board/mpc8349itx + @mkdir -p $(obj)board/freescale/mpc8349itx @echo "#define CONFIG_$(subst _LOWBOOT,,$(@:_config=))" >> $(obj)include/config.h @if [ "$(findstring GP,$@)" ] ; then \ - echo "TEXT_BASE = 0xFE000000" >$(obj)board/mpc8349itx/config.tmp ; \ + echo "TEXT_BASE = 0xFE000000" >$(obj)board/freescale/mpc8349itx/config.tmp ; \ fi @if [ "$(findstring LOWBOOT,$@)" ] ; then \ - echo "TEXT_BASE = 0xFE000000" >$(obj)board/mpc8349itx/config.tmp ; \ + echo "TEXT_BASE = 0xFE000000" >$(obj)board/freescale/mpc8349itx/config.tmp ; \ fi @$(MKCONFIG) -a -n $(@:_config=) MPC8349ITX ppc mpc83xx mpc8349itx freescale From 314d5b6ce52a4ed19dd295d1364e246c5e605017 Mon Sep 17 00:00:00 2001 From: Liew Tsi Chung-r5aahp Date: Thu, 13 Sep 2007 16:04:05 -0700 Subject: [PATCH 242/259] ColdFire: Fix build error caused by pixis.c Moved the #include inside the #ifdef CONFIG_FSL_PIXIS. Signed-off-by: TsiChungLiew --- board/freescale/common/pixis.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/board/freescale/common/pixis.c b/board/freescale/common/pixis.c index ae4bef187..fd99a938c 100644 --- a/board/freescale/common/pixis.c +++ b/board/freescale/common/pixis.c @@ -25,10 +25,9 @@ #include #include #include -#include #ifdef CONFIG_FSL_PIXIS - +#include #include "pixis.h" From dcb88630290d2bcd803386dd4c2be73142994c4f Mon Sep 17 00:00:00 2001 From: Liew Tsi Chung-r5aahp Date: Thu, 13 Sep 2007 16:06:05 -0700 Subject: [PATCH 243/259] ColdFire: fix build error becasue of bad type of mii_init() Signed-off-by: TsiChungLiew --- board/freescale/m5235evb/mii.c | 2 +- board/freescale/m5329evb/mii.c | 2 +- board/freescale/m54455evb/mii.c | 2 +- board/m5271evb/mii.c | 2 +- board/m5272c3/mii.c | 2 +- board/m5282evb/mii.c | 2 +- 6 files changed, 6 insertions(+), 6 deletions(-) diff --git a/board/freescale/m5235evb/mii.c b/board/freescale/m5235evb/mii.c index 58fabdf32..1fd4d99c1 100644 --- a/board/freescale/m5235evb/mii.c +++ b/board/freescale/m5235evb/mii.c @@ -204,7 +204,7 @@ int mii_discover_phy(struct eth_device *dev) } #endif /* CFG_DISCOVER_PHY */ -int mii_init(void) __attribute__((weak,alias("__mii_init"))); +void mii_init(void) __attribute__((weak,alias("__mii_init"))); void __mii_init(void) { diff --git a/board/freescale/m5329evb/mii.c b/board/freescale/m5329evb/mii.c index 31f1510cc..8f6abf3ee 100644 --- a/board/freescale/m5329evb/mii.c +++ b/board/freescale/m5329evb/mii.c @@ -203,7 +203,7 @@ int mii_discover_phy(struct eth_device *dev) } #endif /* CFG_DISCOVER_PHY */ -int mii_init(void) __attribute__((weak,alias("__mii_init"))); +void mii_init(void) __attribute__((weak,alias("__mii_init"))); void __mii_init(void) { diff --git a/board/freescale/m54455evb/mii.c b/board/freescale/m54455evb/mii.c index c067183aa..7a59aa067 100644 --- a/board/freescale/m54455evb/mii.c +++ b/board/freescale/m54455evb/mii.c @@ -221,7 +221,7 @@ int mii_discover_phy(struct eth_device *dev) } #endif /* CFG_DISCOVER_PHY */ -int mii_init(void) __attribute__((weak,alias("__mii_init"))); +void mii_init(void) __attribute__((weak,alias("__mii_init"))); void __mii_init(void) { diff --git a/board/m5271evb/mii.c b/board/m5271evb/mii.c index f6c63c302..3830ce7f2 100644 --- a/board/m5271evb/mii.c +++ b/board/m5271evb/mii.c @@ -200,7 +200,7 @@ int mii_discover_phy(struct eth_device *dev) } #endif /* CFG_DISCOVER_PHY */ -int mii_init(void) __attribute__((weak,alias("__mii_init"))); +void mii_init(void) __attribute__((weak,alias("__mii_init"))); void __mii_init(void) { diff --git a/board/m5272c3/mii.c b/board/m5272c3/mii.c index fadcbb3ef..0ecc44ace 100644 --- a/board/m5272c3/mii.c +++ b/board/m5272c3/mii.c @@ -200,7 +200,7 @@ int mii_discover_phy(struct eth_device *dev) } #endif /* CFG_DISCOVER_PHY */ -int mii_init(void) __attribute__((weak,alias("__mii_init"))); +void mii_init(void) __attribute__((weak,alias("__mii_init"))); void __mii_init(void) { diff --git a/board/m5282evb/mii.c b/board/m5282evb/mii.c index ebd3ed938..d7c6d1f0e 100644 --- a/board/m5282evb/mii.c +++ b/board/m5282evb/mii.c @@ -201,7 +201,7 @@ int mii_discover_phy(struct eth_device *dev) } #endif /* CFG_DISCOVER_PHY */ -int mii_init(void) __attribute__((weak,alias("__mii_init"))); +void mii_init(void) __attribute__((weak,alias("__mii_init"))); void __mii_init(void) { From c750d2e6692a000a82f29de7bf24e3dc21239161 Mon Sep 17 00:00:00 2001 From: Matthias Fuchs Date: Wed, 12 Sep 2007 12:36:53 +0200 Subject: [PATCH 244/259] NAND: Add CFG_NAND_QUIET option This config option sets the default for the progress information output behavior that can also be configured through the 'quiet' environment variable. The legacy NAND code does not print the current progress info on the console. So this option is for backward compatibility for units that are in the field and where setting the quiet variable is not an option. With CFG_NAND_QUIET set to '1' the console progress info is turned off. This can still be overwritten through the environment variable. Signed-off-by: Matthias Fuchs --- common/cmd_nand.c | 4 ++++ include/configs/ASH405.h | 3 ++- include/configs/CMS700.h | 3 ++- include/configs/HH405.h | 3 ++- include/configs/HUB405.h | 3 ++- include/configs/PLU405.h | 3 ++- include/configs/VOH405.h | 3 ++- 7 files changed, 16 insertions(+), 6 deletions(-) diff --git a/common/cmd_nand.c b/common/cmd_nand.c index 254a7755f..aeb76e5fb 100644 --- a/common/cmd_nand.c +++ b/common/cmd_nand.c @@ -161,7 +161,11 @@ int do_nand(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) ulong addr, off, size; char *cmd, *s; nand_info_t *nand; +#ifdef CFG_NAND_QUIET + int quiet = CFG_NAND_QUIET; +#else int quiet = 0; +#endif const char *quiet_str = getenv("quiet"); /* at least two arguments please */ diff --git a/include/configs/ASH405.h b/include/configs/ASH405.h index 0718c8574..9adbba954 100644 --- a/include/configs/ASH405.h +++ b/include/configs/ASH405.h @@ -158,7 +158,8 @@ #define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */ #define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */ -#define CFG_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */ +#define CFG_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */ +#define CFG_NAND_QUIET 1 /*----------------------------------------------------------------------- * PCI stuff diff --git a/include/configs/CMS700.h b/include/configs/CMS700.h index 1fd2b5397..21cd9c1f2 100644 --- a/include/configs/CMS700.h +++ b/include/configs/CMS700.h @@ -165,7 +165,8 @@ #define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */ #define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */ -#define CFG_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */ +#define CFG_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */ +#define CFG_NAND_QUIET 1 /*----------------------------------------------------------------------- * PCI stuff diff --git a/include/configs/HH405.h b/include/configs/HH405.h index ea8e61a76..8967b3fc6 100644 --- a/include/configs/HH405.h +++ b/include/configs/HH405.h @@ -217,7 +217,8 @@ #define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */ #define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */ -#define CFG_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */ +#define CFG_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */ +#define CFG_NAND_QUIET 1 /*----------------------------------------------------------------------- * PCI stuff diff --git a/include/configs/HUB405.h b/include/configs/HUB405.h index ed669c51d..1ff710813 100644 --- a/include/configs/HUB405.h +++ b/include/configs/HUB405.h @@ -157,7 +157,8 @@ #define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */ #define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */ -#define CFG_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */ +#define CFG_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */ +#define CFG_NAND_QUIET 1 /*----------------------------------------------------------------------- * PCI stuff diff --git a/include/configs/PLU405.h b/include/configs/PLU405.h index 4acbcd5e1..652210c19 100644 --- a/include/configs/PLU405.h +++ b/include/configs/PLU405.h @@ -177,7 +177,8 @@ #define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */ #define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */ -#define CFG_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */ +#define CFG_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */ +#define CFG_NAND_QUIET 1 /*----------------------------------------------------------------------- * PCI stuff diff --git a/include/configs/VOH405.h b/include/configs/VOH405.h index 3880ec747..14848abe5 100644 --- a/include/configs/VOH405.h +++ b/include/configs/VOH405.h @@ -163,7 +163,8 @@ #define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */ #define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */ -#define CFG_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */ +#define CFG_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */ +#define CFG_NAND_QUIET 1 /*----------------------------------------------------------------------- * PCI stuff From 5bd7fe9aeb76906371f40b8fd07613f10922e3e7 Mon Sep 17 00:00:00 2001 From: Matthias Fuchs Date: Tue, 11 Sep 2007 17:04:00 +0200 Subject: [PATCH 245/259] Fix do_div() usage in nand process output Fix usage of do_div() in nand erase|read|write process output. The last patch to nand_util.c introduced do_div() instead of libgcc's implementation. But do_div() returns the quotient in its first macro parameter and not as result. Signed-off-by: Matthias Fuchs --- common/cmd_nand.c | 2 +- drivers/nand/nand_util.c | 21 ++++++++++++++++----- 2 files changed, 17 insertions(+), 6 deletions(-) diff --git a/common/cmd_nand.c b/common/cmd_nand.c index aeb76e5fb..1fdd7a67f 100644 --- a/common/cmd_nand.c +++ b/common/cmd_nand.c @@ -456,7 +456,7 @@ U_BOOT_CMD(nand, 5, 1, do_nand, "info - show available NAND devices\n" "nand device [dev] - show or set current device\n" "nand read[.jffs2] - addr off|partition size\n" - "nand write[.jffs2] - addr off|partiton size - read/write `size' bytes starting\n" + "nand write[.jffs2] - addr off|partition size - read/write `size' bytes starting\n" " at offset `off' to/from memory address `addr'\n" "nand erase [clean] [off size] - erase `size' bytes from\n" " offset `off' (entire device if not specified)\n" diff --git a/drivers/nand/nand_util.c b/drivers/nand/nand_util.c index cf05043c0..4fd4e166e 100644 --- a/drivers/nand/nand_util.c +++ b/drivers/nand/nand_util.c @@ -210,9 +210,12 @@ int nand_erase_opts(nand_info_t *meminfo, const nand_erase_options_t *opts) if (!opts->quiet) { unsigned long long n =(unsigned long long) - (erase.addr+meminfo->erasesize-opts->offset) - * 100; - int percent = (int)do_div(n, erase_length); + (erase.addr + meminfo->erasesize - opts->offset) + * 100; + int percent; + + do_div(n, erase_length); + percent = (int)n; /* output progress message only at whole percent * steps to reduce the number of messages printed @@ -478,7 +481,11 @@ int nand_write_opts(nand_info_t *meminfo, const nand_write_options_t *opts) if (!opts->quiet) { unsigned long long n = (unsigned long long) (opts->length-imglen) * 100; - int percent = (int)do_div(n, opts->length); + int percent; + + do_div(n, opts->length); + percent = (int)n; + /* output progress message only at whole percent * steps to reduce the number of messages printed * on (slow) serial consoles @@ -653,7 +660,11 @@ int nand_read_opts(nand_info_t *meminfo, const nand_read_options_t *opts) if (!opts->quiet) { unsigned long long n = (unsigned long long) (opts->length-imglen) * 100; - int percent = (int)do_div(n ,opts->length); + int percent; + + do_div(n, opts->length); + percent = (int)n; + /* output progress message only at whole percent * steps to reduce the number of messages printed * on (slow) serial consoles From cd2d1602c54cc6957bdef3872272a4b264893960 Mon Sep 17 00:00:00 2001 From: "urwithsughosh@gmail.com" Date: Mon, 10 Sep 2007 14:54:56 -0400 Subject: [PATCH 246/259] Typo fix in tsec.c Fixup for the break statement in wrong place. [Patch by urwithsughosh@gmail.com] Acked-by: Andy Fleming Signed-off-by: Wolfgang Denk --- drivers/tsec.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/tsec.c b/drivers/tsec.c index 6bca4dc0f..4ff3339c7 100644 --- a/drivers/tsec.c +++ b/drivers/tsec.c @@ -1262,10 +1262,10 @@ uint mii_parse_lxt971_sr2(uint mii_reg, struct tsec_private *priv) case MIIM_LXT971_SR2_100HDX: priv->speed = 100; priv->duplexity = 0; + break; default: priv->speed = 100; priv->duplexity = 1; - break; } } else { priv->speed = 0; From eb6da8050797c204c9d010548424186c7ce32fc1 Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Sun, 16 Sep 2007 02:39:35 +0200 Subject: [PATCH 247/259] TQM8xx/FPS8xx: adjust flash partitions for 2.6 ARCH=powerpc kernels Signed-off-by: Wolfgang Denk --- include/configs/FPS850L.h | 60 +++++++++++++++++++++++++++------------ include/configs/FPS860L.h | 46 +++++++++++++++++++++++------- include/configs/TQM823L.h | 5 ++-- include/configs/TQM823M.h | 5 ++-- include/configs/TQM850L.h | 5 ++-- include/configs/TQM850M.h | 5 ++-- include/configs/TQM855L.h | 5 ++-- include/configs/TQM855M.h | 5 ++-- include/configs/TQM860L.h | 5 ++-- include/configs/TQM860M.h | 5 ++-- include/configs/TQM862L.h | 5 ++-- include/configs/TQM862M.h | 5 ++-- include/configs/TQM866M.h | 5 ++-- 13 files changed, 111 insertions(+), 50 deletions(-) diff --git a/include/configs/FPS850L.h b/include/configs/FPS850L.h index 322158c7b..3b0ddb4ec 100644 --- a/include/configs/FPS850L.h +++ b/include/configs/FPS850L.h @@ -39,28 +39,44 @@ #undef CONFIG_8xx_CONS_SMC1 #define CONFIG_8xx_CONS_SMC2 1 /* Console is on SMC2 */ #undef CONFIG_8xx_CONS_NONE -#define CONFIG_BAUDRATE 19200 -#if 0 -#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ -#else -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ -#endif -#define CONFIG_BOOTCOMMAND "bootm 40020000" /* autoboot command */ +#define CONFIG_BAUDRATE 115200 -#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ +#define CONFIG_BOOTCOUNT_LIMIT + +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ #define CONFIG_BOARD_TYPES 1 /* support board types */ -#define CONFIG_BOOTARGS "root=/dev/nfs rw " \ - "nfsroot=10.0.0.2:/opt/eldk/ppc_8xx " \ - "nfsaddrs=10.0.0.99:10.0.0.2" +#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo" + +#undef CONFIG_BOOTARGS + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=${serverip}:${rootpath}\0" \ + "ramargs=setenv bootargs root=/dev/ram rw\0" \ + "addip=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:${netdev}:off panic=1\0" \ + "flash_nfs=run nfsargs addip;" \ + "bootm ${kernel_addr}\0" \ + "flash_self=run ramargs addip;" \ + "bootm ${kernel_addr} ${ramdisk_addr}\0" \ + "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ + "rootpath=/opt/eldk/ppc_8xx\0" \ + "bootfile=/tftpboot/fps850L/uImage\0" \ + "fdt_addr=40040000\0" \ + "kernel_addr=40060000\0" \ + "ramdisk_addr=40200000\0" \ + "" +#define CONFIG_BOOTCOMMAND "run flash_self" #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ #undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ #undef CONFIG_WATCHDOG /* watchdog disabled */ - /* * BOOTP options */ @@ -80,24 +96,32 @@ #define CONFIG_BOOTP_NTPSERVER #define CONFIG_BOOTP_TIMEOFFSET +#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ /* * Command line configuration. */ #include -#undef CONFIG_CMD_CONSOLE -#undef CONFIG_CMD_BDI -#undef CONFIG_CMD_LOADS -#undef CONFIG_CMD_LOADB -#undef CONFIG_CMD_CACHE +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_DATE +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_NFS +#define CONFIG_CMD_SNTP /* * Miscellaneous configurable options */ #define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ + +#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ +#define CFG_HUSH_PARSER 1 /* Use the HUSH parser */ +#ifdef CFG_HUSH_PARSER +#define CFG_PROMPT_HUSH_PS2 "> " +#endif + #if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else diff --git a/include/configs/FPS860L.h b/include/configs/FPS860L.h index f8698b570..6fec07540 100644 --- a/include/configs/FPS860L.h +++ b/include/configs/FPS860L.h @@ -40,18 +40,37 @@ #define CONFIG_8xx_CONS_SMC2 1 /* Console is on SMC2 */ #undef CONFIG_8xx_CONS_NONE #define CONFIG_BAUDRATE 115200 -#if 0 -#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ -#else + +#define CONFIG_BOOTCOUNT_LIMIT + #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ -#endif -#define CONFIG_BOOTCOMMAND "bootm 40040000" /* autoboot command */ #define CONFIG_BOARD_TYPES 1 /* support board types */ -#define CONFIG_BOOTARGS "root=/dev/nfs rw " \ - "nfsroot=10.0.0.2:/opt/eldk/ppc_8xx " \ - "nfsaddrs=10.0.0.99:10.0.0.2" +#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo" + +#undef CONFIG_BOOTARGS + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=${serverip}:${rootpath}\0" \ + "ramargs=setenv bootargs root=/dev/ram rw\0" \ + "addip=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:${netdev}:off panic=1\0" \ + "flash_nfs=run nfsargs addip;" \ + "bootm ${kernel_addr}\0" \ + "flash_self=run ramargs addip;" \ + "bootm ${kernel_addr} ${ramdisk_addr}\0" \ + "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ + "rootpath=/opt/eldk/ppc_8xx\0" \ + "bootfile=/tftpboot/fps850L/uImage\0" \ + "fdt_addr=40040000\0" \ + "kernel_addr=40060000\0" \ + "ramdisk_addr=40200000\0" \ + "" +#define CONFIG_BOOTCOMMAND "run flash_self" #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ #undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ @@ -79,11 +98,11 @@ #define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ - /* * Command line configuration. */ #include + #define CONFIG_CMD_ASKENV #define CONFIG_CMD_DATE #define CONFIG_CMD_DHCP @@ -95,7 +114,14 @@ * Miscellaneous configurable options */ #define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ + +#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ +#define CFG_HUSH_PARSER 1 /* Use the HUSH parser */ +#ifdef CFG_HUSH_PARSER +#define CFG_PROMPT_HUSH_PS2 "> " +#endif + #if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else diff --git a/include/configs/TQM823L.h b/include/configs/TQM823L.h index 2bdcf2cf9..384789b13 100644 --- a/include/configs/TQM823L.h +++ b/include/configs/TQM823L.h @@ -70,8 +70,9 @@ "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ "rootpath=/opt/eldk/ppc_8xx\0" \ "bootfile=/tftpboot/TQM823L/uImage\0" \ - "kernel_addr=40040000\0" \ - "ramdisk_addr=40100000\0" \ + "fdt_addr=40040000\0" \ + "kernel_addr=40060000\0" \ + "ramdisk_addr=40200000\0" \ "" #define CONFIG_BOOTCOMMAND "run flash_self" diff --git a/include/configs/TQM823M.h b/include/configs/TQM823M.h index 58bc5d3f9..47f416b49 100644 --- a/include/configs/TQM823M.h +++ b/include/configs/TQM823M.h @@ -70,8 +70,9 @@ "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ "rootpath=/opt/eldk/ppc_8xx\0" \ "bootfile=/tftpboot/TQM823M/uImage\0" \ - "kernel_addr=40080000\0" \ - "ramdisk_addr=40180000\0" \ + "fdt_addr=40080000\0" \ + "kernel_addr=400A0000\0" \ + "ramdisk_addr=40280000\0" \ "" #define CONFIG_BOOTCOMMAND "run flash_self" diff --git a/include/configs/TQM850L.h b/include/configs/TQM850L.h index 74b16c7cf..e4b0bd279 100644 --- a/include/configs/TQM850L.h +++ b/include/configs/TQM850L.h @@ -66,8 +66,9 @@ "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ "rootpath=/opt/eldk/ppc_8xx\0" \ "bootfile=/tftpboot/TQM850L/uImage\0" \ - "kernel_addr=40040000\0" \ - "ramdisk_addr=40100000\0" \ + "fdt_addr=40040000\0" \ + "kernel_addr=40060000\0" \ + "ramdisk_addr=40200000\0" \ "" #define CONFIG_BOOTCOMMAND "run flash_self" diff --git a/include/configs/TQM850M.h b/include/configs/TQM850M.h index e3936c330..f26c46e99 100644 --- a/include/configs/TQM850M.h +++ b/include/configs/TQM850M.h @@ -64,8 +64,9 @@ "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ "rootpath=/opt/eldk/ppc_8xx\0" \ "bootfile=/tftpboot/TQM850M/uImage\0" \ - "kernel_addr=40080000\0" \ - "ramdisk_addr=40180000\0" \ + "fdt_addr=40080000\0" \ + "kernel_addr=400A0000\0" \ + "ramdisk_addr=40280000\0" \ "" #define CONFIG_BOOTCOMMAND "run flash_self" diff --git a/include/configs/TQM855L.h b/include/configs/TQM855L.h index ae22b77d7..330c931cc 100644 --- a/include/configs/TQM855L.h +++ b/include/configs/TQM855L.h @@ -69,8 +69,9 @@ "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ "rootpath=/opt/eldk/ppc_8xx\0" \ "bootfile=/tftpboot/TQM855L/uImage\0" \ - "kernel_addr=40040000\0" \ - "ramdisk_addr=40100000\0" \ + "fdt_addr=40040000\0" \ + "kernel_addr=40060000\0" \ + "ramdisk_addr=40200000\0" \ "" #define CONFIG_BOOTCOMMAND "run flash_self" diff --git a/include/configs/TQM855M.h b/include/configs/TQM855M.h index 5d54f876c..77c2f114a 100644 --- a/include/configs/TQM855M.h +++ b/include/configs/TQM855M.h @@ -69,8 +69,9 @@ "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ "rootpath=/opt/eldk/ppc_8xx\0" \ "bootfile=/tftpboot/TQM855M/uImage\0" \ - "kernel_addr=40080000\0" \ - "ramdisk_addr=40180000\0" \ + "fdt_addr=40080000\0" \ + "kernel_addr=400A0000\0" \ + "ramdisk_addr=40280000\0" \ "" #define CONFIG_BOOTCOMMAND "run flash_self" diff --git a/include/configs/TQM860L.h b/include/configs/TQM860L.h index 40c0940d5..a903c2b34 100644 --- a/include/configs/TQM860L.h +++ b/include/configs/TQM860L.h @@ -69,8 +69,9 @@ "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ "rootpath=/opt/eldk/ppc_8xx\0" \ "bootfile=/tftpboot/TQM860L/uImage\0" \ - "kernel_addr=40040000\0" \ - "ramdisk_addr=40100000\0" \ + "fdt_addr=40040000\0" \ + "kernel_addr=40060000\0" \ + "ramdisk_addr=40200000\0" \ "" #define CONFIG_BOOTCOMMAND "run flash_self" diff --git a/include/configs/TQM860M.h b/include/configs/TQM860M.h index 481e3d0d5..b905a0a63 100644 --- a/include/configs/TQM860M.h +++ b/include/configs/TQM860M.h @@ -69,8 +69,9 @@ "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ "rootpath=/opt/eldk/ppc_8xx\0" \ "bootfile=/tftpboot/TQM860M/uImage\0" \ - "kernel_addr=40080000\0" \ - "ramdisk_addr=40180000\0" \ + "fdt_addr=40080000\0" \ + "kernel_addr=400A0000\0" \ + "ramdisk_addr=40280000\0" \ "" #define CONFIG_BOOTCOMMAND "run flash_self" diff --git a/include/configs/TQM862L.h b/include/configs/TQM862L.h index bb3b1cc54..d8ddf37fa 100644 --- a/include/configs/TQM862L.h +++ b/include/configs/TQM862L.h @@ -72,8 +72,9 @@ "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ "rootpath=/opt/eldk/ppc_8xx\0" \ "bootfile=/tftpboot/TQM862L/uImage\0" \ - "kernel_addr=40040000\0" \ - "ramdisk_addr=40100000\0" \ + "fdt_addr=40040000\0" \ + "kernel_addr=40060000\0" \ + "ramdisk_addr=40200000\0" \ "" #define CONFIG_BOOTCOMMAND "run flash_self" diff --git a/include/configs/TQM862M.h b/include/configs/TQM862M.h index d687d082c..50607f0e5 100644 --- a/include/configs/TQM862M.h +++ b/include/configs/TQM862M.h @@ -72,8 +72,9 @@ "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ "rootpath=/opt/eldk/ppc_8xx\0" \ "bootfile=/tftpboot/TQM862M/uImage\0" \ - "kernel_addr=40080000\0" \ - "ramdisk_addr=40180000\0" \ + "fdt_addr=40080000\0" \ + "kernel_addr=400A0000\0" \ + "ramdisk_addr=40280000\0" \ "" #define CONFIG_BOOTCOMMAND "run flash_self" diff --git a/include/configs/TQM866M.h b/include/configs/TQM866M.h index ff00c1330..ea310c423 100644 --- a/include/configs/TQM866M.h +++ b/include/configs/TQM866M.h @@ -81,8 +81,9 @@ "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ "rootpath=/opt/eldk/ppc_8xx\0" \ "bootfile=/tftpboot/TQM866M/uImage\0" \ - "kernel_addr=40080000\0" \ - "ramdisk_addr=40180000\0" \ + "fdt_addr=40080000\0" \ + "kernel_addr=400A0000\0" \ + "ramdisk_addr=40280000\0" \ "" #define CONFIG_BOOTCOMMAND "run flash_self" From 67c31036acaaaa992fc346cc89db0909a7e733c4 Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Sun, 16 Sep 2007 17:10:04 +0200 Subject: [PATCH 248/259] TQM8xx[LM]: Fix broken environment alignment. With recent toolchains, the environment sectors were no longer aligned to sector boundaries. The reason was a combination of two bugs: 1) common/environment.c assumed that CONFIG_TQM8xxL would be defined for all TQM8xxL and TQM8xxM boards. But "include/common.h", where this gets defined, is not included here (and cannot be included without causing lots of problems). Added a new #define CFG_USE_PPCENV for all boards which really want to put the environment is a ".ppcenv" section. 2) The linker scripts just include environment.o, silently assuming that the objects in that file are really in the order in which they are coded in the C file, i. e. "environment" first, then "redundand_environment", and "env_size" last. However, current toolchains (GCC-4.x) reorder the objects, causing the environment data not to start on a flash sector boundary: Instead of: we got: 40008000 T environment 40008000 T env_size 4000c000 T redundand_environment 40008004 T redundand_environment 40010000 T env_size 4000c004 T environment Note: this patch fixes just the first part, and cures the alignment problem by making sure that "env_size" gets placed correctly. However, we still have a potential issue because primary and redundant environment sectors are actually swapped, i. e. we have now: 40008000 T redundand_environment 4000c000 T environment 40010000 T env_size This shall be fixed in the next version. Signed-off-by: Wolfgang Denk --- board/fads/fads.h | 1 + common/environment.c | 13 +------------ include/configs/CATcenter.h | 2 ++ include/configs/FADS823.h | 1 + include/configs/FADS850SAR.h | 1 + include/configs/ICU862.h | 1 + include/configs/M5271EVB.h | 5 ++--- include/configs/PPChameleonEVB.h | 2 ++ include/configs/R360MPI.h | 1 + include/configs/RRvision.h | 2 ++ include/configs/TQM823L.h | 2 ++ include/configs/TQM823M.h | 2 ++ include/configs/TQM850L.h | 2 ++ include/configs/TQM850M.h | 2 ++ include/configs/TQM855L.h | 2 ++ include/configs/TQM855M.h | 2 ++ include/configs/TQM860L.h | 2 ++ include/configs/TQM860M.h | 2 ++ include/configs/TQM862L.h | 2 ++ include/configs/TQM862M.h | 2 ++ include/configs/TQM866M.h | 2 ++ include/configs/cmi_mpc5xx.h | 5 +++-- include/configs/hymod.h | 1 + include/configs/idmr.h | 2 ++ include/configs/trab.h | 2 ++ include/configs/virtlab2.h | 2 ++ 26 files changed, 46 insertions(+), 17 deletions(-) diff --git a/board/fads/fads.h b/board/fads/fads.h index a7fe2e901..dea8a0dc1 100644 --- a/board/fads/fads.h +++ b/board/fads/fads.h @@ -229,6 +229,7 @@ #define CFG_ENV_SECT_SIZE 0x40000 /* see README - env sector total size */ #define CFG_ENV_OFFSET CFG_ENV_SECT_SIZE #define CFG_ENV_SIZE 0x4000 /* Total Size of Environment */ +#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */ #define CFG_DIRECT_FLASH_TFTP diff --git a/common/environment.c b/common/environment.c index 1d425a730..24257f7c5 100644 --- a/common/environment.c +++ b/common/environment.c @@ -51,18 +51,7 @@ * a seperate section. Note that ENV_CRC is only defined when building * U-Boot itself. */ -#if (defined(CONFIG_CMI) || \ - defined(CONFIG_FADS) || \ - defined(CONFIG_HYMOD) || \ - defined(CONFIG_ICU862) || \ - defined(CONFIG_R360MPI) || \ - defined(CONFIG_TQM8xxL) || \ - defined(CONFIG_RRVISION) || \ - defined(CONFIG_TRAB) || \ - defined(CONFIG_PPCHAMELEONEVB) || \ - defined(CONFIG_M5271EVB) || \ - defined(CONFIG_IDMR) || \ - defined(CONFIG_NAND_U_BOOT)) && \ +#if (defined(CFG_USE_PPCENV) || defined(CONFIG_NAND_U_BOOT)) && \ defined(ENV_CRC) /* Environment embedded in U-Boot .ppcenv section */ /* XXX - This only works with GNU C */ # define __PPCENV__ __attribute__ ((section(".ppcenv"))) diff --git a/include/configs/CATcenter.h b/include/configs/CATcenter.h index 62a2eaa23..0321650f3 100644 --- a/include/configs/CATcenter.h +++ b/include/configs/CATcenter.h @@ -399,6 +399,8 @@ #define CFG_ENV_ADDR_REDUND 0xFFFFA000 #define CFG_ENV_SIZE_REDUND 0x2000 +#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */ + #define CFG_NVRAM_BASE_ADDR 0xF0000500 /* NVRAM base address */ #define CFG_NVRAM_SIZE 242 /* NVRAM size */ diff --git a/include/configs/FADS823.h b/include/configs/FADS823.h index a562b2fa4..f810af2ce 100644 --- a/include/configs/FADS823.h +++ b/include/configs/FADS823.h @@ -206,6 +206,7 @@ #define CFG_ENV_IS_IN_FLASH 1 #define CFG_ENV_OFFSET 0x00040000 /* Offset of Environment Sector */ #define CFG_ENV_SIZE 0x40000 /* Total Size of Environment Sector */ +#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */ /*----------------------------------------------------------------------- * Cache Configuration diff --git a/include/configs/FADS850SAR.h b/include/configs/FADS850SAR.h index c8ce25957..a09c0e039 100644 --- a/include/configs/FADS850SAR.h +++ b/include/configs/FADS850SAR.h @@ -156,6 +156,7 @@ #define CFG_ENV_IS_IN_FLASH 1 #define CFG_ENV_OFFSET 0x00040000 /* Offset of Environment Sector */ #define CFG_ENV_SIZE 0x40000 /* Total Size of Environment Sector */ +#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */ /*----------------------------------------------------------------------- * Cache Configuration diff --git a/include/configs/ICU862.h b/include/configs/ICU862.h index 27a5bc302..da54cef53 100644 --- a/include/configs/ICU862.h +++ b/include/configs/ICU862.h @@ -234,6 +234,7 @@ #define CFG_ENV_SECT_SIZE 0x40000 /* Total Size of Environment sector */ #define CFG_ENV_SIZE 0x4000 /* Used Size of Environment Sector */ +#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */ /*----------------------------------------------------------------------- * Cache Configuration diff --git a/include/configs/M5271EVB.h b/include/configs/M5271EVB.h index 0f97050f2..798ec0c7a 100644 --- a/include/configs/M5271EVB.h +++ b/include/configs/M5271EVB.h @@ -54,13 +54,12 @@ */ #ifndef CONFIG_MONITOR_IS_IN_RAM #define CFG_ENV_OFFSET 0x4000 -#define CFG_ENV_SECT_SIZE 0x2000 -#define CFG_ENV_IS_IN_FLASH 1 #else #define CFG_ENV_ADDR 0xffe04000 +#endif #define CFG_ENV_SECT_SIZE 0x2000 #define CFG_ENV_IS_IN_FLASH 1 -#endif +#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */ /* * BOOTP options diff --git a/include/configs/PPChameleonEVB.h b/include/configs/PPChameleonEVB.h index dd1decdcd..8a74c4f5c 100644 --- a/include/configs/PPChameleonEVB.h +++ b/include/configs/PPChameleonEVB.h @@ -429,6 +429,8 @@ #define CFG_ENV_ADDR_REDUND 0xFFFFA000 #define CFG_ENV_SIZE_REDUND 0x2000 +#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */ + #endif /* ENVIRONMENT_IN_EEPROM */ diff --git a/include/configs/R360MPI.h b/include/configs/R360MPI.h index 516ec643d..a98b4af29 100644 --- a/include/configs/R360MPI.h +++ b/include/configs/R360MPI.h @@ -233,6 +233,7 @@ #define CFG_ENV_OFFSET 0x40000 /* Offset of Environment */ #define CFG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment sector */ #define CFG_ENV_SIZE 0x4000 /* Used Size of Environment sector */ +#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */ /*----------------------------------------------------------------------- * Cache Configuration diff --git a/include/configs/RRvision.h b/include/configs/RRvision.h index 1e6e8c0aa..32e228545 100644 --- a/include/configs/RRvision.h +++ b/include/configs/RRvision.h @@ -235,6 +235,8 @@ #define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SIZE) #define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) +#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */ + /*----------------------------------------------------------------------- * Cache Configuration */ diff --git a/include/configs/TQM823L.h b/include/configs/TQM823L.h index 384789b13..7a3801026 100644 --- a/include/configs/TQM823L.h +++ b/include/configs/TQM823L.h @@ -206,6 +206,8 @@ #define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SIZE) #define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) +#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */ + /*----------------------------------------------------------------------- * Hardware Information Block */ diff --git a/include/configs/TQM823M.h b/include/configs/TQM823M.h index 47f416b49..e8b6a80b1 100644 --- a/include/configs/TQM823M.h +++ b/include/configs/TQM823M.h @@ -203,6 +203,8 @@ #define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SECT_SIZE) #define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) +#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */ + /*----------------------------------------------------------------------- * Hardware Information Block */ diff --git a/include/configs/TQM850L.h b/include/configs/TQM850L.h index e4b0bd279..beeca6343 100644 --- a/include/configs/TQM850L.h +++ b/include/configs/TQM850L.h @@ -193,6 +193,8 @@ #define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SIZE) #define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) +#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */ + /*----------------------------------------------------------------------- * Hardware Information Block */ diff --git a/include/configs/TQM850M.h b/include/configs/TQM850M.h index f26c46e99..d5609c1d4 100644 --- a/include/configs/TQM850M.h +++ b/include/configs/TQM850M.h @@ -192,6 +192,8 @@ #define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SECT_SIZE) #define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) +#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */ + /*----------------------------------------------------------------------- * Hardware Information Block */ diff --git a/include/configs/TQM855L.h b/include/configs/TQM855L.h index 330c931cc..e35b5b2ac 100644 --- a/include/configs/TQM855L.h +++ b/include/configs/TQM855L.h @@ -197,6 +197,8 @@ #define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SIZE) #define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) +#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */ + /*----------------------------------------------------------------------- * Hardware Information Block */ diff --git a/include/configs/TQM855M.h b/include/configs/TQM855M.h index 77c2f114a..cd5212eff 100644 --- a/include/configs/TQM855M.h +++ b/include/configs/TQM855M.h @@ -232,6 +232,8 @@ #define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SECT_SIZE) #define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) +#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */ + /*----------------------------------------------------------------------- * Hardware Information Block */ diff --git a/include/configs/TQM860L.h b/include/configs/TQM860L.h index a903c2b34..d5838dbf3 100644 --- a/include/configs/TQM860L.h +++ b/include/configs/TQM860L.h @@ -200,6 +200,8 @@ #define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SIZE) #define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) +#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */ + /*----------------------------------------------------------------------- * Hardware Information Block */ diff --git a/include/configs/TQM860M.h b/include/configs/TQM860M.h index b905a0a63..684b86f2e 100644 --- a/include/configs/TQM860M.h +++ b/include/configs/TQM860M.h @@ -199,6 +199,8 @@ #define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SECT_SIZE) #define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) +#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */ + /*----------------------------------------------------------------------- * Hardware Information Block */ diff --git a/include/configs/TQM862L.h b/include/configs/TQM862L.h index d8ddf37fa..f09d3d165 100644 --- a/include/configs/TQM862L.h +++ b/include/configs/TQM862L.h @@ -201,6 +201,8 @@ #define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SIZE) #define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) +#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */ + /*----------------------------------------------------------------------- * Hardware Information Block */ diff --git a/include/configs/TQM862M.h b/include/configs/TQM862M.h index 50607f0e5..039aa3af4 100644 --- a/include/configs/TQM862M.h +++ b/include/configs/TQM862M.h @@ -202,6 +202,8 @@ #define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SECT_SIZE) #define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) +#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */ + /*----------------------------------------------------------------------- * Hardware Information Block */ diff --git a/include/configs/TQM866M.h b/include/configs/TQM866M.h index ea310c423..0d778919a 100644 --- a/include/configs/TQM866M.h +++ b/include/configs/TQM866M.h @@ -242,6 +242,8 @@ #define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SECT_SIZE) #define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) +#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */ + /*----------------------------------------------------------------------- * Hardware Information Block */ diff --git a/include/configs/cmi_mpc5xx.h b/include/configs/cmi_mpc5xx.h index 85c2b96fe..a869364c6 100644 --- a/include/configs/cmi_mpc5xx.h +++ b/include/configs/cmi_mpc5xx.h @@ -171,8 +171,9 @@ #define CFG_ENV_IS_IN_FLASH 1 #ifdef CFG_ENV_IS_IN_FLASH -#define CFG_ENV_OFFSET 0x00020000 /* Environment starts at this adress */ -#define CFG_ENV_SIZE 0x00010000 /* Set whole sector as env */ +#define CFG_ENV_OFFSET 0x00020000 /* Environment starts at this adress */ +#define CFG_ENV_SIZE 0x00010000 /* Set whole sector as env */ +#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */ #endif /*----------------------------------------------------------------------- diff --git a/include/configs/hymod.h b/include/configs/hymod.h index 2f64ec238..2547afb3c 100644 --- a/include/configs/hymod.h +++ b/include/configs/hymod.h @@ -406,6 +406,7 @@ #define CFG_ENV_SIZE 0x40000 /* Total Size of Environment Sector */ #define CFG_ENV_SECT_SIZE 0x40000 /* see README - env sect real size */ #define CFG_ENV_ADDR (CFG_FLASH_BASE+CFG_MONITOR_LEN-CFG_ENV_SECT_SIZE) +#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */ /*----------------------------------------------------------------------- * Cache Configuration diff --git a/include/configs/idmr.h b/include/configs/idmr.h index 404e88a4f..3821ebcf0 100644 --- a/include/configs/idmr.h +++ b/include/configs/idmr.h @@ -125,6 +125,8 @@ #define CFG_ENV_IS_IN_FLASH #endif /* !CONFIG_MONITOR_IS_IN_RAM */ +#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */ + #define CFG_PROMPT "=> " #define CFG_LONGHELP /* undef to save memory */ diff --git a/include/configs/trab.h b/include/configs/trab.h index dbccea28a..b9088a89a 100644 --- a/include/configs/trab.h +++ b/include/configs/trab.h @@ -419,6 +419,8 @@ #define CFG_ENV_OFFSET_REDUND (CFG_ENV_ADDR+CFG_ENV_SECT_SIZE) #define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) +#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */ + /* Initial value of the on-board touch screen brightness */ #define CFG_BRIGHTNESS 0x20 diff --git a/include/configs/virtlab2.h b/include/configs/virtlab2.h index 561a8bc47..edae6f4b9 100644 --- a/include/configs/virtlab2.h +++ b/include/configs/virtlab2.h @@ -207,6 +207,8 @@ #define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SIZE) #define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) +#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */ + /*----------------------------------------------------------------------- * Hardware Information Block */ From 97213f32416ead885deafea86774e912ffd60ad0 Mon Sep 17 00:00:00 2001 From: David Saada Date: Mon, 17 Sep 2007 17:04:47 +0200 Subject: [PATCH 249/259] Description: Add NEC's PCI OHCI module ID to the USB OHCI driver Signed-off-by: David Saada --- drivers/usb_ohci.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/usb_ohci.c b/drivers/usb_ohci.c index d6b745fad..388827fd0 100644 --- a/drivers/usb_ohci.c +++ b/drivers/usb_ohci.c @@ -93,6 +93,7 @@ #ifdef CONFIG_PCI_OHCI static struct pci_device_id ohci_pci_ids[] = { {0x10b9, 0x5237}, /* ULI1575 PCI OHCI module ids */ + {0x1033, 0x0035}, /* NEC PCI OHCI module ids */ /* Please add supported PCI OHCI controller ids here */ {0, 0} }; From f8d3ca7b6fa322ac57e8e831f07dbeea039a9f35 Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Tue, 18 Sep 2007 17:40:27 +0200 Subject: [PATCH 250/259] MCC200: fix build warning The MCC200 board config file includes version.h for some customer- specific setting, which causes warnings with "make depend"; build version.h before depend. Signed-off-by: Wolfgang Denk --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index 85885b166..011f730e3 100644 --- a/Makefile +++ b/Makefile @@ -319,7 +319,7 @@ updater: env: $(MAKE) -C tools/env all || exit 1 -depend dep: +depend dep: version for dir in $(SUBDIRS) ; do $(MAKE) -C $$dir _depend ; done tags ctags: From 8a783a65851bc7421ab69f442261215e21b8891a Mon Sep 17 00:00:00 2001 From: Grant Likely Date: Tue, 18 Sep 2007 12:24:57 -0600 Subject: [PATCH 251/259] Bugfix: remove embedded null (\0) from CFG_BOOTFILE macro in TQM8540_config /bin/bash and /bin/dash (which /bin/sh is linked to on ubuntu) handle embedded nulls in a string differently. For example, the following statement: echo "this is a string\0" > afile Will produce the following with /bin/bash: "this is a string\0" But with /bin/dash, will produce: "this is a string Bug fixed by moving the embedded null out of the makefile and into the config header. Also renamed the macro to avoid usage colision with the same macro used by other board ports. Signed-off-by: Grant Likely --- Makefile | 2 +- include/configs/TQM85xx.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/Makefile b/Makefile index 85885b166..a87311ca1 100644 --- a/Makefile +++ b/Makefile @@ -1961,7 +1961,7 @@ TQM8560_config: unconfig echo "#define CONFIG_TQM$${CTYPE}">>$(obj)include/config.h; \ echo "#define CONFIG_HOSTNAME tqm$${CTYPE}">>$(obj)include/config.h; \ echo "#define CONFIG_BOARDNAME \"TQM$${CTYPE}\"">>$(obj)include/config.h; \ - echo "#define CFG_BOOTFILE \"bootfile=/tftpboot/tqm$${CTYPE}/uImage\0\"">>$(obj)include/config.h + echo "#define CFG_BOOTFILE_PATH \"/tftpboot/tqm$${CTYPE}/uImage\"">>$(obj)include/config.h @$(MKCONFIG) -a TQM85xx ppc mpc85xx tqm85xx ######################################################################### diff --git a/include/configs/TQM85xx.h b/include/configs/TQM85xx.h index 2f23c5049..6dbd3924b 100644 --- a/include/configs/TQM85xx.h +++ b/include/configs/TQM85xx.h @@ -449,7 +449,7 @@ #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ #define CONFIG_EXTRA_ENV_SETTINGS \ - CFG_BOOTFILE \ + "bootfile="CFG_BOOTFILE_PATH"\0" \ "netdev=eth0\0" \ "consdev=ttyS0\0" \ "nfsargs=setenv bootargs root=/dev/nfs rw " \ From 135e19bc2773ebca487e9a8371f67e1ba202313a Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Tue, 18 Sep 2007 21:36:35 +0200 Subject: [PATCH 252/259] Avoid compiler warning. Signed-off-by: Wolfgang Denk --- net/bootp.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/net/bootp.c b/net/bootp.c index be1ee332a..749d3e5e0 100644 --- a/net/bootp.c +++ b/net/bootp.c @@ -730,7 +730,7 @@ static void DhcpOptionsProcess (uchar * popt, Bootp_t *bp) break; #if defined(CONFIG_CMD_SNTP) && defined(CONFIG_BOOTP_TIMEOFFSET) case 2: /* Time offset */ - NetCopyLong (&NetTimeOffset, (ulong *) (popt + 2)); + NetCopyLong ((ulong *)&NetTimeOffset, (ulong *) (popt + 2)); NetTimeOffset = ntohl (NetTimeOffset); break; #endif From 66dcad3a9a53e0766d90e0084123bd8529522fb0 Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Thu, 20 Sep 2007 00:04:14 +0200 Subject: [PATCH 253/259] v1.3.0-rc2 Signed-off-by: Wolfgang Denk --- CHANGELOG | 366 ++++++++++++++++++++++++++++++++++++++++++++++++++++++ Makefile | 2 +- 2 files changed, 367 insertions(+), 1 deletion(-) diff --git a/CHANGELOG b/CHANGELOG index 671c836b7..82b314535 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -1,3 +1,369 @@ +commit 135e19bc2773ebca487e9a8371f67e1ba202313a +Author: Wolfgang Denk +Date: Tue Sep 18 21:36:35 2007 +0200 + + Avoid compiler warning. + + Signed-off-by: Wolfgang Denk + +commit 8a783a65851bc7421ab69f442261215e21b8891a +Author: Grant Likely +Date: Tue Sep 18 12:24:57 2007 -0600 + + Bugfix: remove embedded null (\0) from CFG_BOOTFILE macro in TQM8540_config + + /bin/bash and /bin/dash (which /bin/sh is linked to on ubuntu) handle embedded + nulls in a string differently. For example, the following statement: + echo "this is a string\0" > afile + Will produce the following with /bin/bash: + "this is a string\0" + But with /bin/dash, will produce: + "this is a string + + Bug fixed by moving the embedded null out of the makefile and into the + config header. Also renamed the macro to avoid usage colision with the same + macro used by other board ports. + + Signed-off-by: Grant Likely + +commit f8d3ca7b6fa322ac57e8e831f07dbeea039a9f35 +Author: Wolfgang Denk +Date: Tue Sep 18 17:40:27 2007 +0200 + + MCC200: fix build warning + + The MCC200 board config file includes version.h for some customer- + specific setting, which causes warnings with "make depend"; build + version.h before depend. + + Signed-off-by: Wolfgang Denk + +commit 67c31036acaaaa992fc346cc89db0909a7e733c4 +Author: Wolfgang Denk +Date: Sun Sep 16 17:10:04 2007 +0200 + + TQM8xx[LM]: Fix broken environment alignment. + + With recent toolchains, the environment sectors were no longer aligned to + sector boundaries. The reason was a combination of two bugs: + + 1) common/environment.c assumed that CONFIG_TQM8xxL would be defined + for all TQM8xxL and TQM8xxM boards. But "include/common.h", where + this gets defined, is not included here (and cannot be included + without causing lots of problems). + + Added a new #define CFG_USE_PPCENV for all boards which really + want to put the environment is a ".ppcenv" section. + + 2) The linker scripts just include environment.o, silently assuming + that the objects in that file are really in the order in which + they are coded in the C file, i. e. "environment" first, then + "redundand_environment", and "env_size" last. However, current + toolchains (GCC-4.x) reorder the objects, causing the environment + data not to start on a flash sector boundary: + + Instead of: we got: + + 40008000 T environment 40008000 T env_size + 4000c000 T redundand_environment 40008004 T redundand_environment + 40010000 T env_size 4000c004 T environment + + Note: this patch fixes just the first part, and cures the alignment + problem by making sure that "env_size" gets placed correctly. However, + we still have a potential issue because primary and redundant + environment sectors are actually swapped, i. e. we have now: + + 40008000 T redundand_environment + 4000c000 T environment + 40010000 T env_size + + This shall be fixed in the next version. + + Signed-off-by: Wolfgang Denk + +commit eb6da8050797c204c9d010548424186c7ce32fc1 +Author: Wolfgang Denk +Date: Sun Sep 16 02:39:35 2007 +0200 + + TQM8xx/FPS8xx: adjust flash partitions for 2.6 ARCH=powerpc kernels + + Signed-off-by: Wolfgang Denk + +commit cd2d1602c54cc6957bdef3872272a4b264893960 +Author: urwithsughosh@gmail.com +Date: Mon Sep 10 14:54:56 2007 -0400 + + Typo fix in tsec.c + + Fixup for the break statement in wrong place. + + [Patch by urwithsughosh@gmail.com] + Acked-by: Andy Fleming + Signed-off-by: Wolfgang Denk + +commit 5bd7fe9aeb76906371f40b8fd07613f10922e3e7 +Author: Matthias Fuchs +Date: Tue Sep 11 17:04:00 2007 +0200 + + Fix do_div() usage in nand process output + + Fix usage of do_div() in nand erase|read|write process output. + + The last patch to nand_util.c introduced do_div() instead of libgcc's + implementation. But do_div() returns the quotient in its first + macro parameter and not as result. + + Signed-off-by: Matthias Fuchs + +commit c750d2e6692a000a82f29de7bf24e3dc21239161 +Author: Matthias Fuchs +Date: Wed Sep 12 12:36:53 2007 +0200 + + NAND: Add CFG_NAND_QUIET option + + This config option sets the default for the progress information + output behavior that can also be configured through the 'quiet' + environment variable. + + The legacy NAND code does not print the current progress info + on the console. So this option is for backward compatibility for + units that are in the field and where setting the quiet variable + is not an option. With CFG_NAND_QUIET set to '1' the console + progress info is turned off. This can still be overwritten + through the environment variable. + + Signed-off-by: Matthias Fuchs + +commit dcb88630290d2bcd803386dd4c2be73142994c4f +Author: Liew Tsi Chung-r5aahp +Date: Thu Sep 13 16:06:05 2007 -0700 + + ColdFire: fix build error becasue of bad type of mii_init() + + Signed-off-by: TsiChungLiew + +commit 314d5b6ce52a4ed19dd295d1364e246c5e605017 +Author: Liew Tsi Chung-r5aahp +Date: Thu Sep 13 16:04:05 2007 -0700 + + ColdFire: Fix build error caused by pixis.c + + Moved the #include inside the #ifdef CONFIG_FSL_PIXIS. + + Signed-off-by: TsiChungLiew + +commit e21659e30660a1377c42af135a6114efe39801d9 +Author: Sam Sparks +Date: Fri Sep 14 11:14:42 2007 -0600 + + Update MPC8349ITX*_config to place config.tmp in right place. + + MPC834ITX*_config does not store config.tmp at the correct locatation, + causing MPC8349ITXGP to have the wrong TEXT_BASE. + + Signed-off-by: Sam Sparks + Signed-off-by: Grant Likely + +commit 1218abf1b5817a39a82399b4b928b00750575bda +Author: Wolfgang Denk +Date: Sat Sep 15 20:48:41 2007 +0200 + + Fix cases where DECLARE_GLOBAL_DATA_PTR was not declared as global + + Signed-off-by: Wolfgang Denk + +commit 66b3f24d665be678a9dbb125b1e84185400f63b5 +Author: Dirk Behme +Date: Sat Sep 15 11:55:42 2007 +0200 + + Make DECLARE_GLOBAL_DATA_PTR global for DaVinci + + As discussed in [1], DECLARE_GLOBAL_DATA_PTR has to be global and not + function local. + + Signed-off-by: Dirk Behme + + [1] http://article.gmane.org/gmane.comp.boot-loaders.u-boot/31805 + +commit 6e7b7b6ea1b6d04dbe96242eb6a0c1c664c98e8c +Author: Bartlomiej Sieka +Date: Thu Sep 13 18:21:48 2007 +0200 + + cm5200: Fix a typo introduced by afaac86fe2948ac84cd9a12bbed883b3c683e7d9 + + Signed-off-by: Marian Balakowicz + +commit f34024d4a328e6edd906456da98d2c537155c4f7 +Author: Wolfgang Denk +Date: Wed Sep 12 00:48:57 2007 +0200 + + Fix memory corruption problem on STX GP3 SSA Board. + + Signed-off-by: Wolfgang Denk + +commit 38ad82da0c1180ecdeb212a8f4245e945bcc546e +Author: Grzegorz Bernacki +Date: Tue Sep 11 15:42:11 2007 +0200 + + [GP3SSA] Add define CONFIG_MPC85XX_PCI2 in config file to allow u-boot to + scan on second pci bus. + + Signed-off-by: Grzegorz Bernacki + +commit 6c2f4f388e8181655ea8b69343ea00b68aa6e8d0 +Author: Grzegorz Bernacki +Date: Tue Sep 11 12:57:52 2007 +0200 + + [ppc4xx] Individual handling of sdram.c for bamboo_nand build + + Bamboo has a file sdram.c which needs special treatment when building in + separate directory. It has to be linked to build directory otherwise it is + not seen. + + Signed-off-by: Grzegorz Bernacki + +commit 38c1ef728d19950414a8ab1ccfc53767848fa346 +Author: Sean MCGOOGAN +Date: Mon Sep 10 16:55:59 2007 +0100 + + Allocate CPU Architecture Code for STMicroelectronics' ST200. + + Signed-off-by: Sean McGoogan + --------------------------------------------------- + +commit 754bac48156f8958d8f6a53a51eda88ab5758929 +Author: Wolfgang Denk +Date: Mon Sep 10 20:42:31 2007 +0200 + + Update version to match current state. + + Signed-off-by: Wolfgang Denk + +commit 7a888d6b3c32a126dbb504ef146bb4c26574ca7b +Author: Grzegorz Bernacki +Date: Mon Sep 10 17:39:08 2007 +0200 + + [MPC512x] Streamline frame handling in the FEC driver + + - convert frame size settings to be derived from a single base + - set frame size to the recommended default value + + Signed-off-by: Grzegorz Bernacki + +commit e251e00d0db4b36d1d2b7e38fec43a7296b529a2 +Author: Kyungmin Park +Date: Mon Sep 10 11:34:00 2007 +0900 + + Remove compiler warning: target CPU does not support interworking + + Signed-off-by: Kyungmin Park + +commit 1d9e31e04911a6bb7cc66dd91132c699101c32e2 +Author: Wolfgang Denk +Date: Sun Sep 9 21:21:33 2007 +0200 + + Fix compile error in spc1920 config. + + Signed-off-by: Markus Klotzbücher + Signed-off-by: Wolfgang Denk + +commit a7d7eca791a37f452c9da10fef4b31dd7aa9a622 +Author: Grant Likely +Date: Fri Sep 7 09:25:07 2007 -0600 + + Bugfix: make bootm+libfdt compile on boards with no flash + + Signed-off-by: Grant Likely + +commit 6efc1fc0b63e55f94c5bc61d8dd23c918e3bc778 +Author: Grzegorz Bernacki +Date: Fri Sep 7 18:35:37 2007 +0200 + + [PPC440SPe] PCIe environment settings for Katmai and Yucca + + - 'pciconfighost' is set by default in order to be able to scan bridges + behind the primary host/PCIe + + - 'pciscandelay' env variable is recognized to allow for user-controlled + delay before the PCIe bus enumeration; some peripheral devices require a + significant delay before they can be scanned (e.g. LSI8408E); without the + delay they are not detected + + Signed-off-by: Grzegorz Bernacki + +commit 7f1913938984ef6c6a46cb53e003719196d9c5de +Author: Grzegorz Bernacki +Date: Fri Sep 7 18:20:23 2007 +0200 + + [PPC440SPe] Improve PCIe configuration space access + + - correct configuration space mapping + - correct bus numbering + - better access to config space + + Prior to this patch, the 440SPe host/PCIe bridge was able to configure only the + first device on the first bus. We now allow to configure up to 16 buses; + also, scanning for devices behind the PCIe-PCIe bridge is supported, so + peripheral devices farther in hierarchy can be identified. + + Signed-off-by: Grzegorz Bernacki + +commit 15ee4734e4e08003d73d9ead3ca80e2a0672e427 +Author: Grzegorz Bernacki +Date: Fri Sep 7 17:46:18 2007 +0200 + + [PPC440SPe] Convert machine check exceptions handling + + Convert using fixup mechanism to suppressing MCK for the duration of config + read/write transaction: while fixups work fine with the case of a precise + exception, we identified a major drawback with this approach when there's + an imprecise case. In this scenario there is the following race condition: + the fixup is (by design) set to catch the instruction following the one + actually causing the exception; if an interrupt (e.g. decrementer) happens + between those two instructions, the ISR code is executed before the fixup + handler the machine check is no longer protected by the fixup handler as it + appears as within the ISR code. In consequence the fixup approach is being + phased out and replaced with explicit suppressing of MCK during a PCIe + config read/write cycle. + + Signed-off-by: Grzegorz Bernacki + +commit ff7640c9ead8806b5d827f2b29f9cb2632add729 +Author: Wolfgang Denk +Date: Fri Sep 7 17:43:36 2007 +0200 + + Fix typo in MAKEALL script. + + Signed-off-by: Wolfgang Denk + +commit 08e2e5fcd2e06670b62e1680a3934c0e55c72810 +Author: Grzegorz Bernacki +Date: Fri Sep 7 17:09:21 2007 +0200 + + [MPC512x] Proper handling of larger frames in the FEC driver + + When frame larger than local RX buffer is received, it is split and handled + by two buffer descriptors. Prior to this patch the FEC driver discarded + contents of a buffer descriptor without the 'LAST' bit set, so the first + part of the frame was lost in case of larger frames. This fix allows to + safely combine the two pieces into the whole frame. + + Signed-off-by: Grzegorz Bernacki + +commit 8d17979d0359492a822a0a409d26e3a3549b4cd4 +Author: Rafal Jaworowski +Date: Fri Sep 7 17:05:36 2007 +0200 + + [MPC512x] Correct fixup relocation + + Signed-off-by: Rafal Jaworowski + +commit a89cbbd27a60e6740772000fd0688ffba1c2576a +Author: Wolfgang Denk +Date: Fri Sep 7 01:21:25 2007 +0200 + + Update CHANGELOG, minor coding style cleanup. + commit 5e5803e119de3bebd76fc9a57baac0b5aeccc8a3 Author: stefano babic Date: Thu Aug 30 23:01:49 2007 +0200 diff --git a/Makefile b/Makefile index e74ff3613..8d500f534 100644 --- a/Makefile +++ b/Makefile @@ -24,7 +24,7 @@ VERSION = 1 PATCHLEVEL = 3 SUBLEVEL = 0 -EXTRAVERSION = -rc1 +EXTRAVERSION = -rc2 U_BOOT_VERSION = $(VERSION).$(PATCHLEVEL).$(SUBLEVEL)$(EXTRAVERSION) VERSION_FILE = $(obj)include/version_autogenerated.h From 0d38effc6e359e6b1b0c78d66e8bc1a4dc15a2ae Mon Sep 17 00:00:00 2001 From: Grant Likely Date: Tue, 25 Sep 2007 15:48:05 -0600 Subject: [PATCH 254/259] Fpga: fix incorrect test of CFG_FPGA_XILINX macro CFG_FPGA_XILINX is a bit value used to test against the value in CONFIG_FPGA. Testing for a value will always return TRUE. I don't think that is the intention in this code. Signed-off-by: Grant Likely --- common/cmd_fpga.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/common/cmd_fpga.c b/common/cmd_fpga.c index 3fc4fca9a..cce23ad70 100644 --- a/common/cmd_fpga.c +++ b/common/cmd_fpga.c @@ -60,6 +60,7 @@ static int fpga_get_op (char *opstr); /* Convert bitstream data and load into the fpga */ int fpga_loadbitstream(unsigned long dev, char* fpgadata, size_t size) { +#if (CONFIG_FPGA & CFG_FPGA_XILINX) unsigned int length; unsigned char* swapdata; unsigned int swapsize; @@ -72,7 +73,6 @@ int fpga_loadbitstream(unsigned long dev, char* fpgadata, size_t size) dataptr = (unsigned char *)fpgadata; -#if CFG_FPGA_XILINX /* skip the first bytes of the bitsteam, their meaning is unknown */ length = (*dataptr << 8) + *(dataptr+1); dataptr+=2; From 3e954beb614b5b190d7f4f4c3b641437a0132e35 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Tue, 11 Sep 2007 14:12:55 +0200 Subject: [PATCH 255/259] ppc4xx: lwmon5: Change GPIO 58 to default to low (watchdog test) Signed-off-by: Stefan Roese --- include/configs/lwmon5.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/configs/lwmon5.h b/include/configs/lwmon5.h index be483245b..a9db0862f 100644 --- a/include/configs/lwmon5.h +++ b/include/configs/lwmon5.h @@ -472,7 +472,7 @@ {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO55 Unselect via TraceSelect Bit */ \ {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO56 Unselect via TraceSelect Bit */ \ {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO57 Unselect via TraceSelect Bit */ \ -{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO58 Unselect via TraceSelect Bit */ \ +{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO58 Unselect via TraceSelect Bit */ \ {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO59 Unselect via TraceSelect Bit */ \ {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO60 Unselect via TraceSelect Bit */ \ {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO61 Unselect via TraceSelect Bit */ \ From 86ec86c04326c3913178a7679aa910de071da75d Mon Sep 17 00:00:00 2001 From: Jean-Christophe PLAGNIOL-VILLARD Date: Thu, 27 Sep 2007 23:27:47 +0200 Subject: [PATCH 256/259] Fix missing DECLARE_GLOBAL_DATA_PTR on CONFIG_LPC2292 in serial Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD --- cpu/arm720t/serial.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/cpu/arm720t/serial.c b/cpu/arm720t/serial.c index 27eb73ad8..1b0e147e1 100644 --- a/cpu/arm720t/serial.c +++ b/cpu/arm720t/serial.c @@ -125,6 +125,8 @@ serial_puts (const char *s) #elif defined(CONFIG_LPC2292) +DECLARE_GLOBAL_DATA_PTR; + #include void serial_setbrg (void) From 2db64784061bfc34f4ba70ef1d2fbe7133b55670 Mon Sep 17 00:00:00 2001 From: Grzegorz Bernacki Date: Mon, 1 Oct 2007 09:51:50 +0200 Subject: [PATCH 257/259] Program EPLD to force full duplex mode for PHY. EPLD forces modes of PHY operation. By default full duplex is turned off. This fix turns it on. Signed-off-by: Grzegorz Bernacki --- board/amcc/luan/luan.c | 17 ++++++++++++----- cpu/ppc4xx/4xx_enet.c | 12 ++++++++---- 2 files changed, 20 insertions(+), 9 deletions(-) diff --git a/board/amcc/luan/luan.c b/board/amcc/luan/luan.c index 7b16f8a39..1bd7efa0b 100644 --- a/board/amcc/luan/luan.c +++ b/board/amcc/luan/luan.c @@ -39,8 +39,6 @@ extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ ************************************************************************/ int board_early_init_f(void) { - volatile epld_t *x = (epld_t *) CFG_EPLD_BASE; - mtebc( pb0ap, 0x03800000 ); /* set chip selects */ mtebc( pb0cr, 0xffc58000 ); /* ebc0_b0cr, 4MB at 0xffc00000 CS0 */ mtebc( pb1ap, 0x03800000 ); @@ -66,8 +64,6 @@ int board_early_init_f(void) mtdcr( uic0sr, 0x00000000 ); /* clear all interrupts */ mtdcr( uic0sr, 0xffffffff ); - x->ethuart &= ~EPLD2_RESET_ETH_N; /* put Ethernet+PHY in reset */ - return 0; } @@ -79,7 +75,18 @@ int board_early_init_f(void) int misc_init_r(void) { volatile epld_t *x = (epld_t *) CFG_EPLD_BASE; - x->ethuart |= EPLD2_RESET_ETH_N; /* take Ethernet+PHY out of reset */ + + /* set modes of operation */ + x->ethuart |= EPLD2_ETH_MODE_10 | EPLD2_ETH_MODE_100 | + EPLD2_ETH_MODE_1000 | EPLD2_ETH_DUPLEX_MODE; + /* clear ETHERNET_AUTO_NEGO bit to turn on autonegotiation */ + x->ethuart &= ~EPLD2_ETH_AUTO_NEGO; + + /* put Ethernet+PHY in reset */ + x->ethuart &= ~EPLD2_RESET_ETH_N; + udelay(10000); + /* take Ethernet+PHY out of reset */ + x->ethuart |= EPLD2_RESET_ETH_N; return 0; } diff --git a/cpu/ppc4xx/4xx_enet.c b/cpu/ppc4xx/4xx_enet.c index cc8e7346d..4e9a05e5b 100644 --- a/cpu/ppc4xx/4xx_enet.c +++ b/cpu/ppc4xx/4xx_enet.c @@ -138,7 +138,8 @@ #define BI_PHYMODE_MII 7 #endif -#if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX) +#if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || \ + defined(CONFIG_440GRX) || defined(CONFIG_440SP) #define SDR0_MFR_ETH_CLK_SEL_V(n) ((0x01<<27) / (n+1)) #endif @@ -408,7 +409,8 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis) int ethgroup = -1; #endif #endif -#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || defined(CONFIG_440SPE) +#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ + defined(CONFIG_440SPE) || defined(CONFIG_440SP) unsigned long mfr; #endif @@ -500,7 +502,8 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis) __asm__ volatile ("eieio"); /* reset emac so we have access to the phy */ -#if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX) +#if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ + defined(CONFIG_440SP) /* provide clocks for EMAC internal loopback */ mfsdr (sdr_mfr, mfr); mfr |= SDR0_MFR_ETH_CLK_SEL_V(devnum); @@ -518,7 +521,8 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis) if (failsafe <= 0) printf("\nProblem resetting EMAC!\n"); -#if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX) +#if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ + defined(CONFIG_440SP) /* remove clocks for EMAC internal loopback */ mfsdr (sdr_mfr, mfr); mfr &= ~SDR0_MFR_ETH_CLK_SEL_V(devnum); From 87c1833a39e944db66385286fd5e28f9b3fcdd50 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Tue, 2 Oct 2007 11:44:19 +0200 Subject: [PATCH 258/259] ppc4xx: lwmon5: Remove watchdog for now, since not fully tested yet Signed-off-by: Stefan Roese --- include/configs/lwmon5.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/include/configs/lwmon5.h b/include/configs/lwmon5.h index 8ec4742c0..00c34d5d7 100644 --- a/include/configs/lwmon5.h +++ b/include/configs/lwmon5.h @@ -339,7 +339,12 @@ #define CFG_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */ #define CFG_PCI_SUBSYS_ID 0xcafe /* Whatever */ +#if 0 +/* + * ToDo: Watchdog is not test fully, so exclude it for now + */ #define CONFIG_HW_WATCHDOG 1 /* Use external HW-Watchdog */ +#endif /* * For booting Linux, the board info and command line data From 738815c0cc44aa329097f868dc1efc49ede9c5ba Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Tue, 2 Oct 2007 11:44:46 +0200 Subject: [PATCH 259/259] ppc4xx: Coding style cleanup Signed-off-by: Stefan Roese --- board/amcc/luan/luan.c | 2 +- cpu/ppc4xx/440spe_pcie.c | 10 +++++----- cpu/ppc4xx/4xx_enet.c | 14 +++++++------- 3 files changed, 13 insertions(+), 13 deletions(-) diff --git a/board/amcc/luan/luan.c b/board/amcc/luan/luan.c index 1bd7efa0b..0067ce0e7 100644 --- a/board/amcc/luan/luan.c +++ b/board/amcc/luan/luan.c @@ -81,7 +81,7 @@ int misc_init_r(void) EPLD2_ETH_MODE_1000 | EPLD2_ETH_DUPLEX_MODE; /* clear ETHERNET_AUTO_NEGO bit to turn on autonegotiation */ x->ethuart &= ~EPLD2_ETH_AUTO_NEGO; - + /* put Ethernet+PHY in reset */ x->ethuart &= ~EPLD2_RESET_ETH_N; udelay(10000); diff --git a/cpu/ppc4xx/440spe_pcie.c b/cpu/ppc4xx/440spe_pcie.c index 158f1c559..3eac0ae62 100644 --- a/cpu/ppc4xx/440spe_pcie.c +++ b/cpu/ppc4xx/440spe_pcie.c @@ -104,7 +104,7 @@ static int pcie_read_config(struct pci_controller *hose, unsigned int devfn, if ((!((PCI_FUNC(devfn) == 0) && (PCI_DEV(devfn) == 0))) && ((PCI_BUS(devfn) == 0) || (PCI_BUS(devfn) == 1))) return 0; - + address = pcie_get_base(hose, devfn); offset += devfn << 4; @@ -136,12 +136,12 @@ static int pcie_write_config(struct pci_controller *hose, unsigned int devfn, int offset, int len, u32 val) { u8 *address; - + /* * Bus numbers are relative to hose->first_busno */ devfn -= PCI_BDF(hose->first_busno, 0, 0); - + /* * Same constraints as in pcie_read_config(). */ @@ -151,7 +151,7 @@ static int pcie_write_config(struct pci_controller *hose, unsigned int devfn, if ((!((PCI_FUNC(devfn) == 0) && (PCI_DEV(devfn) == 0))) && ((PCI_BUS(devfn) == 0) || (PCI_BUS(devfn) == 1))) return 0; - + address = pcie_get_base(hose, devfn); offset += devfn << 4; @@ -926,7 +926,7 @@ void ppc440spe_setup_pcie_rootpoint(struct pci_controller *hose, int port) in_le16((u16 *)(mbase + PCI_COMMAND)) | PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); printf("PCIE:%d successfully set as rootpoint\n",port); - + /* Set Device and Vendor Id */ switch (port) { case 0: diff --git a/cpu/ppc4xx/4xx_enet.c b/cpu/ppc4xx/4xx_enet.c index 4e9a05e5b..71a9e372d 100644 --- a/cpu/ppc4xx/4xx_enet.c +++ b/cpu/ppc4xx/4xx_enet.c @@ -410,7 +410,7 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis) #endif #endif #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ - defined(CONFIG_440SPE) || defined(CONFIG_440SP) + defined(CONFIG_440SP) || defined(CONFIG_440SPE) unsigned long mfr; #endif @@ -502,8 +502,8 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis) __asm__ volatile ("eieio"); /* reset emac so we have access to the phy */ -#if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ - defined(CONFIG_440SP) +#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ + defined(CONFIG_440SP) || defined(CONFIG_440SPE) /* provide clocks for EMAC internal loopback */ mfsdr (sdr_mfr, mfr); mfr |= SDR0_MFR_ETH_CLK_SEL_V(devnum); @@ -521,8 +521,8 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis) if (failsafe <= 0) printf("\nProblem resetting EMAC!\n"); -#if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ - defined(CONFIG_440SP) +#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ + defined(CONFIG_440SP) || defined(CONFIG_440SPE) /* remove clocks for EMAC internal loopback */ mfsdr (sdr_mfr, mfr); mfr &= ~SDR0_MFR_ETH_CLK_SEL_V(devnum); @@ -924,8 +924,8 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis) /* set speed */ if (speed == _1000BASET) { -#if defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ - defined(CONFIG_440EPX) || defined(CONFIG_440GRX) +#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ + defined(CONFIG_440SP) || defined(CONFIG_440SPE) unsigned long pfc1; mfsdr (sdr_pfc1, pfc1);