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Coding style cleanup, update CHANGELOG

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Signed-off-by: Wolfgang Denk <wd@denx.de>
This commit is contained in:
Wolfgang Denk 2007-08-02 21:27:46 +02:00
parent 8993e54b6f
commit b1b54e3520
9 changed files with 151 additions and 104 deletions
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46
CHANGELOG
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@ -1,3 +1,49 @@
commit 8993e54b6f397973794f3d6f47d3b3c0c98dd4f6
Author: Rafal Jaworowski <raj@semihalf.com>
Date: Fri Jul 27 14:43:59 2007 +0200
[ADS5121] Support for the ADS5121 board
The following MPC5121e subsystems are supported:
- low-level CPU init
- NOR Boot Flash (common CFI driver)
- DDR SDRAM
- FEC
- I2C
- Watchdog
Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com>
Signed-off-by: Rafal Jaworowski <raj@semihalf.com>
Signed-off-by: Jan Wrobel <wrr@semihalf.com>
commit 1863cfb7b100ba0ee3401799457a01dc058745f8
Author: Rafal Jaworowski <raj@semihalf.com>
Date: Fri Jul 27 14:22:04 2007 +0200
[PPC] Remove unused MSR_USER definition
Signed-off-by: Rafal Jaworowski <raj@semihalf.com>
commit cc3023b9f95d7ac959a764471a65001062aecf41
Author: Rafal Jaworowski <raj@semihalf.com>
Date: Thu Jul 19 17:12:28 2007 +0200
Fix breakage of 8xx boards from recent commit.
This patch fixes the negative consequences for 8xx of the recent
"ppc4xx: Clean up 440 exceptions handling" commit.
Signed-off-by: Rafal Jaworowski <raj@semihalf.com>
commit 3a6cab844cf74f76639d795e0be8717e02c86af7
Author: Wolfgang Denk <wd@denx.de>
Date: Sat Jul 14 22:51:02 2007 +0200
Update CHANGELOG
Signed-off-by: Wolfgang Denk <wd@denx.de>
commit 011595307731a7a67a7445d107c279d031e8ab97 commit 011595307731a7a67a7445d107c279d031e8ab97
Author: Heiko Schocher <hs@pollux.denx.de> Author: Heiko Schocher <hs@pollux.denx.de>
Date: Sat Jul 14 01:06:58 2007 +0200 Date: Sat Jul 14 01:06:58 2007 +0200

4
board/ads5121/ads5121.c
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@ -114,7 +114,7 @@ long int fixed_sdram (void)
* According to MPC5121e RM, configuring local access windows should * According to MPC5121e RM, configuring local access windows should
* be followed by a dummy read of the config register that was * be followed by a dummy read of the config register that was
* modified last and an isync * modified last and an isync
*/ */
i = im->sysconf.ddrlaw.ar; i = im->sysconf.ddrlaw.ar;
__asm__ __volatile__ ("isync"); __asm__ __volatile__ ("isync");
@ -183,6 +183,6 @@ int checkboard (void)
uchar cpld_rev = *(vu_char *) (CFG_CPLD_BASE + 0x02); uchar cpld_rev = *(vu_char *) (CFG_CPLD_BASE + 0x02);
printf ("Board: ADS5121 rev. 0x%04x (CPLD rev. 0x%02x)\n", printf ("Board: ADS5121 rev. 0x%04x (CPLD rev. 0x%02x)\n",
brd_rev, cpld_rev); brd_rev, cpld_rev);
return 0; return 0;
} }

26
cpu/mpc512x/fec.c
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@ -77,20 +77,20 @@ static int mpc512x_fec_bd_init (mpc512x_fec_priv *fec)
* Trasmit BDs init * Trasmit BDs init
*/ */
for (ix = 0; ix < FEC_TBD_NUM; ix++) { for (ix = 0; ix < FEC_TBD_NUM; ix++) {
fec->bdBase->tbd[ix].status = 0; fec->bdBase->tbd[ix].status = 0;
} }
/* /*
* Have the last TBD to close the ring * Have the last TBD to close the ring
*/ */
fec->bdBase->tbd[ix - 1].status |= FEC_TBD_WRAP; fec->bdBase->tbd[ix - 1].status |= FEC_TBD_WRAP;
/* /*
* Initialize some indices * Initialize some indices
*/ */
fec->tbdIndex = 0; fec->tbdIndex = 0;
fec->usedTbdIndex = 0; fec->usedTbdIndex = 0;
fec->cleanTbdNum = FEC_TBD_NUM; fec->cleanTbdNum = FEC_TBD_NUM;
return 0; return 0;
} }
@ -346,7 +346,7 @@ int mpc512x_fec_init_phy (struct eth_device *dev, bd_t * bis)
#if (DEBUG & 0x2) #if (DEBUG & 0x2)
printf ("done.\n"); printf ("done.\n");
#endif #endif
} else { /* MII100 */ } else { /* MII100 */
/* /*
* Set the auto-negotiation advertisement register bits * Set the auto-negotiation advertisement register bits
*/ */

4
cpu/mpc512x/speed.c
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@ -85,8 +85,8 @@ int get_clocks (void)
csb_clk = sys_clk / 2; csb_clk = sys_clk / 2;
cpmf = (im->clk.spmr & SPMR_CPMF) >> SPMR_CPMF_SHIFT; cpmf = (im->clk.spmr & SPMR_CPMF) >> SPMR_CPMF_SHIFT;
core_clk = (csb_clk * cpmf_mult[cpmf][0]) / cpmf_mult[cpmf][1]; core_clk = (csb_clk * cpmf_mult[cpmf][0]) / cpmf_mult[cpmf][1];
ips_div = (im->clk.scfr[0] & SCFR1_IPS_DIV_MASK) >> SCFR1_IPS_DIV_SHIFT; ips_div = (im->clk.scfr[0] & SCFR1_IPS_DIV_MASK) >> SCFR1_IPS_DIV_SHIFT;
if (ips_div != 0) { if (ips_div != 0) {

16
cpu/mpc512x/start.S
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@ -208,8 +208,8 @@ boot_cold:
*/ */
/* Boot CS/CS0 window range */ /* Boot CS/CS0 window range */
lis r3, CFG_IMMR@h lis r3, CFG_IMMR@h
ori r3, r3, CFG_IMMR@l ori r3, r3, CFG_IMMR@l
lis r4, START_REG(CFG_FLASH_BASE) lis r4, START_REG(CFG_FLASH_BASE)
ori r4, r4, STOP_REG(CFG_FLASH_BASE, CFG_FLASH_SIZE) ori r4, r4, STOP_REG(CFG_FLASH_BASE, CFG_FLASH_SIZE)
@ -224,9 +224,9 @@ boot_cold:
/* /*
* According to MPC5121e RM, configuring local access windows should * According to MPC5121e RM, configuring local access windows should
* be followed by a dummy read of the config register that was * be followed by a dummy read of the config register that was
* modified last and an isync * modified last and an isync
*/ */
lwz r4, SRAMBAR(r3) lwz r4, SRAMBAR(r3)
isync isync
@ -235,11 +235,11 @@ boot_cold:
* config register so no params can be set for it * config register so no params can be set for it
*/ */
lis r3, (CFG_IMMR + LPC_OFFSET)@h lis r3, (CFG_IMMR + LPC_OFFSET)@h
ori r3, r3, (CFG_IMMR + LPC_OFFSET)@l ori r3, r3, (CFG_IMMR + LPC_OFFSET)@l
lis r4, CFG_CS0_CFG@h lis r4, CFG_CS0_CFG@h
ori r4, r4, CFG_CS0_CFG@l ori r4, r4, CFG_CS0_CFG@l
stw r4, CS0_CONFIG(r3) stw r4, CS0_CONFIG(r3)
/* Master enable all CS's */ /* Master enable all CS's */
lis r4, CS_CTRL_ME@h lis r4, CS_CTRL_ME@h

117
include/configs/ads5121.h
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@ -65,48 +65,49 @@
#define CFG_SDRAM_BASE CFG_DDR_BASE #define CFG_SDRAM_BASE CFG_DDR_BASE
/* DDR Controller Configuration /* DDR Controller Configuration
*
SYS_CFG: * SYS_CFG:
[31:31] MDDRC Soft Reset: Diabled * [31:31] MDDRC Soft Reset: Diabled
[30:30] DRAM CKE pin: Enabled * [30:30] DRAM CKE pin: Enabled
[29:29] DRAM CLK: Enabled * [29:29] DRAM CLK: Enabled
[28:28] Command Mode: Enabled (For initialization only) * [28:28] Command Mode: Enabled (For initialization only)
[27:25] DRAM Row Select: dram_row[15:0] = magenta_address[25:10] * [27:25] DRAM Row Select: dram_row[15:0] = magenta_address[25:10]
[24:21] DRAM Bank Select: dram_bank[1:0] = magenta_address[11:10] * [24:21] DRAM Bank Select: dram_bank[1:0] = magenta_address[11:10]
[20:19] Read Test: DON'T USE * [20:19] Read Test: DON'T USE
[18:18] Self Refresh: Enabled * [18:18] Self Refresh: Enabled
[17:17] 16bit Mode: Disabled * [17:17] 16bit Mode: Disabled
[16:13] Ready Delay: 2 * [16:13] Ready Delay: 2
[12:12] Half DQS Delay: Disabled * [12:12] Half DQS Delay: Disabled
[11:11] Quarter DQS Delay: Disabled * [11:11] Quarter DQS Delay: Disabled
[10:08] Write Delay: 2 * [10:08] Write Delay: 2
[07:07] Early ODT: Disabled * [07:07] Early ODT: Disabled
[06:06] On DIE Termination: Disabled * [06:06] On DIE Termination: Disabled
[05:05] FIFO Overflow Clear: DON'T USE here * [05:05] FIFO Overflow Clear: DON'T USE here
[04:04] FIFO Underflow Clear: DON'T USE here * [04:04] FIFO Underflow Clear: DON'T USE here
[03:03] FIFO Overflow Pending: DON'T USE here * [03:03] FIFO Overflow Pending: DON'T USE here
[02:02] FIFO Underlfow Pending: DON'T USE here * [02:02] FIFO Underlfow Pending: DON'T USE here
[01:01] FIFO Overlfow Enabled: Enabled * [01:01] FIFO Overlfow Enabled: Enabled
[00:00] FIFO Underflow Enabled: Enabled * [00:00] FIFO Underflow Enabled: Enabled
TIME_CFG0 * TIME_CFG0
[31:16] DRAM Refresh Time: 0 CSB clocks * [31:16] DRAM Refresh Time: 0 CSB clocks
[15:8] DRAM Command Time: 0 CSB clocks * [15:8] DRAM Command Time: 0 CSB clocks
[07:00] DRAM Precharge Time: 0 CSB clocks * [07:00] DRAM Precharge Time: 0 CSB clocks
TIME_CFG1 * TIME_CFG1
[31:26] DRAM tRFC: * [31:26] DRAM tRFC:
[25:21] DRAM tWR1: * [25:21] DRAM tWR1:
[20:17] DRAM tWRT1: * [20:17] DRAM tWRT1:
[16:11] DRAM tDRR: * [16:11] DRAM tDRR:
[10:05] DRAM tRC: * [10:05] DRAM tRC:
[04:00] DRAM tRAS: * [04:00] DRAM tRAS:
TIME_CFG2 * TIME_CFG2
[31:28] DRAM tRCD: * [31:28] DRAM tRCD:
[27:23] DRAM tFAW: * [27:23] DRAM tFAW:
[22:19] DRAM tRTW1: * [22:19] DRAM tRTW1:
[18:15] DRAM tCCD: * [18:15] DRAM tCCD:
[14:10] DRAM tRTP: * [14:10] DRAM tRTP:
[09:05] DRAM tRP: * [09:05] DRAM tRP:
[04:00] DRAM tRPA */ * [04:00] DRAM tRPA
*/
#define CFG_MDDRC_SYS_CFG 0xF8604200 #define CFG_MDDRC_SYS_CFG 0xF8604200
#define CFG_MDDRC_SYS_CFG_RUN 0xE8604200 #define CFG_MDDRC_SYS_CFG_RUN 0xE8604200
@ -276,7 +277,7 @@ SYS_CFG:
#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ #define CONFIG_COMMANDS (CONFIG_CMD_DFL \
| CFG_CMD_NET \ | CFG_CMD_NET \
| CFG_CMD_PING \ | CFG_CMD_PING \
| CFG_CMD_MII \ | CFG_CMD_MII \
| CFG_CMD_I2C) | CFG_CMD_I2C)
#endif #endif
@ -384,26 +385,26 @@ SYS_CFG:
"bootm\0" \ "bootm\0" \
"load=tftp 100000 /tftpboot/ads5121/u-boot.bin\0" \ "load=tftp 100000 /tftpboot/ads5121/u-boot.bin\0" \
"update=protect off fff00000 fff3ffff; " \ "update=protect off fff00000 fff3ffff; " \
"era fff00000 fff3ffff; cp.b 100000 fff00000 ${filesize}\0" \ "era fff00000 fff3ffff; cp.b 100000 fff00000 ${filesize}\0" \
"upd=run load;run update\0" \ "upd=run load;run update\0" \
"" ""
#define CONFIG_NFSBOOTCOMMAND \ #define CONFIG_NFSBOOTCOMMAND \
"setenv bootargs root=/dev/nfs rw " \ "setenv bootargs root=/dev/nfs rw " \
"nfsroot=$serverip:$rootpath " \ "nfsroot=$serverip:$rootpath " \
"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
"console=$consoledev,$baudrate $othbootargs;" \ "console=$consoledev,$baudrate $othbootargs;" \
"tftp $loadaddr $bootfile;" \ "tftp $loadaddr $bootfile;" \
"tftp $fdtaddr $fdtfile;" \ "tftp $fdtaddr $fdtfile;" \
"bootm $loadaddr - $fdtaddr" "bootm $loadaddr - $fdtaddr"
#define CONFIG_RAMBOOTCOMMAND \ #define CONFIG_RAMBOOTCOMMAND \
"setenv bootargs root=/dev/ram rw " \ "setenv bootargs root=/dev/ram rw " \
"console=$consoledev,$baudrate $othbootargs;" \ "console=$consoledev,$baudrate $othbootargs;" \
"tftp $ramdiskaddr $ramdiskfile;" \ "tftp $ramdiskaddr $ramdiskfile;" \
"tftp $loadaddr $bootfile;" \ "tftp $loadaddr $bootfile;" \
"tftp $fdtaddr $fdtfile;" \ "tftp $fdtaddr $fdtfile;" \
"bootm $loadaddr $ramdiskaddr $fdtaddr" "bootm $loadaddr $ramdiskaddr $fdtaddr"
#define CONFIG_BOOTCOMMAND "run flash_self" #define CONFIG_BOOTCOMMAND "run flash_self"