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Implement hard SPI driver on MPC8349EMDS

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This patch implements the fsl_spi driver on the MPC8349EMDS evaluation board.
This board has an ST M25P40 4Mbit EEPROM on its SPI bus

Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
This commit is contained in:
Ben Warren 2008-01-16 22:37:42 -05:00 committed by Kim Phillips
parent 04a9e1180a
commit 80ddd22626
2 changed files with 39 additions and 0 deletions
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29
board/freescale/mpc8349emds/mpc8349emds.c
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@ -27,6 +27,7 @@
#include <mpc83xx.h> #include <mpc83xx.h>
#include <asm/mpc8349_pci.h> #include <asm/mpc8349_pci.h>
#include <i2c.h> #include <i2c.h>
#include <spi.h>
#include <spd.h> #include <spd.h>
#include <miiphy.h> #include <miiphy.h>
#if defined(CONFIG_SPD_EEPROM) #if defined(CONFIG_SPD_EEPROM)
@ -251,6 +252,34 @@ void sdram_init(void)
} }
#endif #endif
/*
* The following are used to control the SPI chip selects for the SPI command.
*/
#ifdef CONFIG_HARD_SPI
#define SPI_CS_MASK 0x80000000
void spi_eeprom_chipsel(int cs)
{
volatile gpio83xx_t *iopd = &((immap_t *)CFG_IMMR)->gpio[0];
if(cs)
iopd->dat &= ~SPI_CS_MASK;
else
iopd->dat |= SPI_CS_MASK;
}
/*
* The SPI command uses this table of functions for controlling the SPI
* chip selects.
*/
spi_chipsel_type spi_chipsel[] = {
spi_eeprom_chipsel,
};
int spi_chipsel_cnt = sizeof(spi_chipsel) / sizeof(spi_chipsel[0]);
#endif /* CONFIG_HARD_SPI */
#if defined(CONFIG_OF_BOARD_SETUP) #if defined(CONFIG_OF_BOARD_SETUP)
void ft_board_setup(void *blob, bd_t *bd) void ft_board_setup(void *blob, bd_t *bd)
{ {

10
include/configs/MPC8349EMDS.h
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@ -355,6 +355,16 @@
#define CFG_I2C_OFFSET 0x3000 #define CFG_I2C_OFFSET 0x3000
#define CFG_I2C2_OFFSET 0x3100 #define CFG_I2C2_OFFSET 0x3100
/* SPI */
#define CONFIG_HARD_SPI /* SPI with hardware support*/
#undef CONFIG_SOFT_SPI /* SPI bit-banged */
#define CONFIG_FSL_SPI
/* GPIOs. Used as SPI chip selects */
#define CFG_GPIO1_PRELIM
#define CFG_GPIO1_DIR 0xC0000000 /* SPI CS on 0, LED on 1 */
#define CFG_GPIO1_DAT 0xC0000000 /* Both are active LOW */
/* TSEC */ /* TSEC */
#define CFG_TSEC1_OFFSET 0x24000 #define CFG_TSEC1_OFFSET 0x24000
#define CFG_TSEC1 (CFG_IMMR+CFG_TSEC1_OFFSET) #define CFG_TSEC1 (CFG_IMMR+CFG_TSEC1_OFFSET)