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ppc4xx: lwmon5: Change PHY reset sequence for PHY MDIO address latching

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Signed-off-by: Stefan Roese <sr@denx.de>
This commit is contained in:
Stefan Roese 2007-11-13 08:18:20 +01:00
parent 5c568d6a7f
commit 54fd6c93c2
1 changed files with 17 additions and 9 deletions
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26
board/lwmon5/lwmon5.c
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@ -96,6 +96,23 @@ int board_early_init_f(void)
gpio_write_bit(CFG_GPIO_FLASH_WP, 1); gpio_write_bit(CFG_GPIO_FLASH_WP, 1);
/*
* Reset PHY's:
* The PHY's need a 2nd reset pulse, since the MDIO address is latched
* upon reset, and with the first reset upon powerup, the addresses are
* not latched reliable, since the IRQ line is multiplexed with an
* MDIO address. A 2nd reset at this time will make sure, that the
* correct address is latched.
*/
gpio_write_bit(CFG_GPIO_PHY0_RST, 1);
gpio_write_bit(CFG_GPIO_PHY1_RST, 1);
udelay(1000);
gpio_write_bit(CFG_GPIO_PHY0_RST, 0);
gpio_write_bit(CFG_GPIO_PHY1_RST, 0);
udelay(1000);
gpio_write_bit(CFG_GPIO_PHY0_RST, 1);
gpio_write_bit(CFG_GPIO_PHY1_RST, 1);
return 0; return 0;
} }
@ -230,15 +247,6 @@ int misc_init_r(void)
/* Write lime controller memory parameters */ /* Write lime controller memory parameters */
out_be32((void *)CFG_LIME_MMR, CFG_LIME_MMR_VALUE); out_be32((void *)CFG_LIME_MMR, CFG_LIME_MMR_VALUE);
/*
* Reset PHY's
*/
gpio_write_bit(CFG_GPIO_PHY0_RST, 0);
gpio_write_bit(CFG_GPIO_PHY1_RST, 0);
udelay(100);
gpio_write_bit(CFG_GPIO_PHY0_RST, 1);
gpio_write_bit(CFG_GPIO_PHY1_RST, 1);
/* /*
* Init display controller * Init display controller
*/ */