From 3dd2db53ceb0dff80f25c2a07f83f29b907b403e Mon Sep 17 00:00:00 2001
From: Jon Loeliger <jdl@freescale.com>
Date: Tue, 16 Oct 2007 13:54:01 -0500
Subject: [PATCH 001/108] Initial mpc8610hpcd board files.

Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
Signed-off-by: Mahesh Jade <mahesh.jade@freescale.com>
Signed-off-by: Jason Jin <Jason.jin@freescale.com>
Signed-off-by: Jon Loeliger <jdl@freescale.com>
---
 board/freescale/mpc8610hpcd/Makefile      |  57 +++
 board/freescale/mpc8610hpcd/config.mk     |  25 ++
 board/freescale/mpc8610hpcd/init.S        | 147 +++++++
 board/freescale/mpc8610hpcd/mpc8610hpcd.c | 507 ++++++++++++++++++++++
 board/freescale/mpc8610hpcd/u-boot.lds    | 135 ++++++
 5 files changed, 871 insertions(+)
 create mode 100644 board/freescale/mpc8610hpcd/Makefile
 create mode 100644 board/freescale/mpc8610hpcd/config.mk
 create mode 100644 board/freescale/mpc8610hpcd/init.S
 create mode 100644 board/freescale/mpc8610hpcd/mpc8610hpcd.c
 create mode 100644 board/freescale/mpc8610hpcd/u-boot.lds

diff --git a/board/freescale/mpc8610hpcd/Makefile b/board/freescale/mpc8610hpcd/Makefile
new file mode 100644
index 000000000..6f5a5c16e
--- /dev/null
+++ b/board/freescale/mpc8610hpcd/Makefile
@@ -0,0 +1,57 @@
+# Copyright 2007 Freescale Semiconductor, Inc.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+ifneq ($(OBJTREE),$(SRCTREE))
+$(shell mkdir -p $(obj)../common)
+endif
+
+LIB	= $(obj)lib$(BOARD).a
+
+COBJS	:= $(BOARD).o \
+	../common/sys_eeprom.o \
+	../common/pixis.o
+
+SOBJS	:= init.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS)
+
+clean:
+	rm -f $(OBJS) $(SOBJS)
+
+.PHONY: distclean
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/freescale/mpc8610hpcd/config.mk b/board/freescale/mpc8610hpcd/config.mk
new file mode 100644
index 000000000..64ac4dcd7
--- /dev/null
+++ b/board/freescale/mpc8610hpcd/config.mk
@@ -0,0 +1,25 @@
+# Copyright 2007 Freescale Semiconductor.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+TEXT_BASE = 0xfff00000
+
+PLATFORM_CPPFLAGS += -DCONFIG_MPC86xx=1
+PLATFORM_CPPFLAGS += -DCONFIG_MPC8610=1 -maltivec -mabi=altivec -msoft-float -O2
diff --git a/board/freescale/mpc8610hpcd/init.S b/board/freescale/mpc8610hpcd/init.S
new file mode 100644
index 000000000..68797a812
--- /dev/null
+++ b/board/freescale/mpc8610hpcd/init.S
@@ -0,0 +1,147 @@
+/*
+ * Copyright 2007 Freescale Semiconductor.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * Version 2 as published by the Free Software Foundation.
+ */
+
+#include <ppc_asm.tmpl>
+#include <ppc_defs.h>
+#include <asm/cache.h>
+#include <asm/mmu.h>
+#include <config.h>
+#include <mpc86xx.h>
+
+#define LAWAR_TRGT_PCI1		0x00000000
+#define LAWAR_TRGT_PCIE1	0x00200000
+#define LAWAR_TRGT_PCIE2	0x00100000
+#define LAWAR_TRGT_LBC		0x00400000
+#define LAWAR_TRGT_DDR		0x00f00000
+
+#if !defined(CONFIG_SPD_EEPROM)
+#define LAWBAR1 ((CFG_DDR_SDRAM_BASE>>12) & 0xffffff)
+#define LAWAR1	(LAWAR_EN | LAWAR_TRGT_DDR | (LAWAR_SIZE & LAWAR_SIZE_512M))
+#else
+#define LAWBAR1 0
+#define LAWAR1	((LAWAR_TRGT_DDR | (LAWAR_SIZE & LAWAR_SIZE_512M)) & ~LAWAR_EN)
+#endif
+
+#define LAWBAR2 ((CFG_PCIE1_MEM_BASE>>12) & 0xffffff)
+#define LAWAR2	(LAWAR_EN | LAWAR_TRGT_PCIE1 | (LAWAR_SIZE & LAWAR_SIZE_256M))
+
+#define LAWBAR3 ((CFG_PCIE2_MEM_BASE>>12) & 0xffffff)
+#define LAWAR3	(LAWAR_EN | LAWAR_TRGT_PCIE2 | (LAWAR_SIZE & LAWAR_SIZE_256M))
+
+#define LAWBAR4 ((PIXIS_BASE>>12) & 0xffffff)
+#define LAWAR4	(LAWAR_EN | LAWAR_TRGT_LBC | (LAWAR_SIZE & LAWAR_SIZE_2M))
+
+#define LAWBAR5 ((CFG_PCIE1_IO_PHYS>>12) & 0xffffff)
+#define LAWAR5	(LAWAR_EN | LAWAR_TRGT_PCIE1 | (LAWAR_SIZE & LAWAR_SIZE_1M))
+
+#define LAWBAR6 ((CFG_PCIE2_IO_PHYS>>12) & 0xffffff)
+#define LAWAR6	(LAWAR_EN | LAWAR_TRGT_PCIE2 | (LAWAR_SIZE & LAWAR_SIZE_1M))
+
+#define LAWBAR7 ((CFG_FLASH_BASE >>12) & 0xffffff)
+#define LAWAR7	(LAWAR_EN | LAWAR_TRGT_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M))
+
+#define LAWBAR8 ((CFG_PCI1_MEM_PHYS>>12) & 0xffffff)
+#define LAWAR8	(LAWAR_EN | LAWAR_TRGT_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_256M))
+
+#define LAWBAR9 ((CFG_PCI1_IO_PHYS>>12) & 0xffffff)
+#define LAWAR9	(LAWAR_EN | LAWAR_TRGT_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_1M))
+
+
+	.section .bootpg, "ax"
+	.globl	law_entry
+law_entry:
+	lis	r7,CFG_CCSRBAR@h
+	ori	r7,r7,CFG_CCSRBAR@l
+
+	addi	r4,r7,0
+	addi	r5,r7,0
+
+	/* Skip LAWAR0, start at LAWAR1 */
+	lis	r6,LAWBAR1@h
+	ori	r6,r6,LAWBAR1@l
+	stwu	r6, 0xc28(r4)
+
+	lis	r6,LAWAR1@h
+	ori	r6,r6,LAWAR1@l
+	stwu	r6, 0xc30(r5)
+
+	/* LAWBAR2, LAWAR2 */
+	lis	r6,LAWBAR2@h
+	ori	r6,r6,LAWBAR2@l
+	stwu	r6, 0x20(r4)
+
+	lis	r6,LAWAR2@h
+	ori	r6,r6,LAWAR2@l
+	stwu	r6, 0x20(r5)
+
+	/* LAWBAR3, LAWAR3 */
+	lis	r6,LAWBAR3@h
+	ori	r6,r6,LAWBAR3@l
+	stwu	r6, 0x20(r4)
+
+	lis	r6,LAWAR3@h
+	ori	r6,r6,LAWAR3@l
+	stwu	r6, 0x20(r5)
+
+	/* LAWBAR4, LAWAR4 */
+	lis	r6,LAWBAR4@h
+	ori	r6,r6,LAWBAR4@l
+	stwu	r6, 0x20(r4)
+
+	lis	r6,LAWAR4@h
+	ori	r6,r6,LAWAR4@l
+	stwu	r6, 0x20(r5)
+	/* LAWBAR5, LAWAR5 */
+	lis	r6,LAWBAR5@h
+	ori	r6,r6,LAWBAR5@l
+	stwu	r6, 0x20(r4)
+
+	lis	r6,LAWAR5@h
+	ori	r6,r6,LAWAR5@l
+	stwu	r6, 0x20(r5)
+
+	/* LAWBAR6, LAWAR6 */
+	lis	r6,LAWBAR6@h
+	ori	r6,r6,LAWBAR6@l
+	stwu	r6, 0x20(r4)
+
+	lis	r6,LAWAR6@h
+	ori	r6,r6,LAWAR6@l
+	stwu	r6, 0x20(r5)
+
+	/* LAWBAR7, LAWAR7 */
+	lis	r6,LAWBAR7@h
+	ori	r6,r6,LAWBAR7@l
+	stwu	r6, 0x20(r4)
+
+	lis	r6,LAWAR7@h
+	ori	r6,r6,LAWAR7@l
+	stwu	r6, 0x20(r5)
+
+	/* LAWBAR8, LAWAR8 */
+	lis	r6,LAWBAR8@h
+	ori	r6,r6,LAWBAR8@l
+	stwu	r6, 0x20(r4)
+
+	lis	r6,LAWAR8@h
+	ori	r6,r6,LAWAR8@l
+	stwu	r6, 0x20(r5)
+
+	/* LAWBAR9, LAWAR9 */
+	lis	r6,LAWBAR9@h
+	ori	r6,r6,LAWBAR9@l
+	stwu	r6, 0x20(r4)
+
+	lis	r6,LAWAR9@h
+	ori	r6,r6,LAWAR9@l
+	stwu	r6, 0x20(r5)
+
+	blr
diff --git a/board/freescale/mpc8610hpcd/mpc8610hpcd.c b/board/freescale/mpc8610hpcd/mpc8610hpcd.c
new file mode 100644
index 000000000..63790ca9b
--- /dev/null
+++ b/board/freescale/mpc8610hpcd/mpc8610hpcd.c
@@ -0,0 +1,507 @@
+/*
+ * Copyright 2007 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#define DEBUG
+#include <common.h>
+#include <command.h>
+#include <pci.h>
+#include <asm/processor.h>
+#include <asm/immap_86xx.h>
+#include <asm/immap_fsl_pci.h>
+#include <spd.h>
+#include <asm/io.h>
+
+
+#if defined(CONFIG_OF_FLAT_TREE)
+#include <ft_build.h>
+extern void ft_cpu_setup(void *blob, bd_t *bd);
+#endif
+
+#include "../common/pixis.h"
+
+#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
+extern void ddr_enable_ecc(unsigned int dram_size);
+#endif
+
+#if defined(CONFIG_SPD_EEPROM)
+#include "spd_sdram.h"
+#endif
+
+void sdram_init(void);
+long int fixed_sdram(void);
+
+/* called before any console output */
+int board_early_init_f(void)
+{
+	volatile immap_t *immap = (immap_t *)CFG_IMMR;
+	volatile ccsr_gur_t *gur = &immap->im_gur;
+
+	gur->gpiocr |= 0x888a5500; /* DIU16, IR1, UART0, UART2 */
+
+	return 0;
+}
+
+int checkboard(void)
+{
+	volatile immap_t *immap = (immap_t *)CFG_IMMR;
+	volatile ccsr_lbc_t *memctl = &immap->im_lbc;
+	volatile ccsr_local_mcm_t *mcm = &immap->im_local_mcm;
+
+	puts("Board: MPC8610HPCD\n");
+
+	mcm->abcr |= 0x00010000; /* 0 */
+	mcm->hpmr3 = 0x80000008; /* 4c */
+	mcm->hpmr0 = 0;
+	mcm->hpmr1 = 0;
+	mcm->hpmr2 = 0;
+	mcm->hpmr4 = 0;
+	mcm->hpmr5 = 0;
+
+	return 0;
+}
+
+
+long int
+initdram(int board_type)
+{
+	long dram_size = 0;
+
+#if defined(CONFIG_SPD_EEPROM)
+	dram_size = spd_sdram();
+#else
+	dram_size = fixed_sdram();
+#endif
+
+#if defined(CFG_RAMBOOT)
+	puts(" DDR: ");
+	return dram_size;
+#endif
+
+#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
+	/*
+	 * Initialize and enable DDR ECC.
+	 */
+	ddr_enable_ecc(dram_size);
+#endif
+
+	puts(" DDR: ");
+	return dram_size;
+}
+
+
+#if defined(CFG_DRAM_TEST)
+int
+testdram(void)
+{
+	uint *pstart = (uint *) CFG_MEMTEST_START;
+	uint *pend = (uint *) CFG_MEMTEST_END;
+	uint *p;
+
+	puts("SDRAM test phase 1:\n");
+	for (p = pstart; p < pend; p++)
+		*p = 0xaaaaaaaa;
+
+	for (p = pstart; p < pend; p++) {
+		if (*p != 0xaaaaaaaa) {
+			printf("SDRAM test fails at: %08x\n", (uint) p);
+			return 1;
+		}
+	}
+
+	puts("SDRAM test phase 2:\n");
+	for (p = pstart; p < pend; p++)
+		*p = 0x55555555;
+
+	for (p = pstart; p < pend; p++) {
+		if (*p != 0x55555555) {
+			printf("SDRAM test fails at: %08x\n", (uint) p);
+			return 1;
+		}
+	}
+
+	puts("SDRAM test passed.\n");
+	return 0;
+}
+#endif
+
+
+#if !defined(CONFIG_SPD_EEPROM)
+/*
+ * Fixed sdram init -- doesn't use serial presence detect.
+ */
+
+long int fixed_sdram(void)
+{
+#if !defined(CFG_RAMBOOT)
+	volatile immap_t *immap = (immap_t *)CFG_IMMR;
+	volatile ccsr_ddr_t *ddr = &immap->im_ddr1;
+	uint d_init;
+
+	ddr->cs0_bnds = 0x0000001f;
+	ddr->cs0_config = 0x80010202;
+
+	ddr->ext_refrec = 0x00000000;
+	ddr->timing_cfg_0 = 0x00260802;
+	ddr->timing_cfg_1 = 0x3935d322;
+	ddr->timing_cfg_2 = 0x14904cc8;
+	ddr->sdram_mode_1 = 0x00480432;
+	ddr->sdram_mode_2 = 0x00000000;
+	ddr->sdram_interval = 0x06180fff; /* 0x06180100; */
+	ddr->sdram_data_init = 0xDEADBEEF;
+	ddr->sdram_clk_cntl = 0x03800000;
+	ddr->sdram_cfg_2 = 0x04400010;
+
+#if defined(CONFIG_DDR_ECC)
+	ddr->err_int_en = 0x0000000d;
+	ddr->err_disable = 0x00000000;
+	ddr->err_sbe = 0x00010000;
+#endif
+	asm("sync;isync");
+
+	udelay(500);
+
+	ddr->sdram_cfg_1 = 0xc3000000; /* 0xe3008000;*/
+
+
+#if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
+	d_init = 1;
+	debug("DDR - 1st controller: memory initializing\n");
+	/*
+	 * Poll until memory is initialized.
+	 * 512 Meg at 400 might hit this 200 times or so.
+	 */
+	while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0)
+		udelay(1000);
+
+	debug("DDR: memory initialized\n\n");
+	asm("sync; isync");
+	udelay(500);
+#endif
+
+	return 512 * 1024 * 1024;
+#endif
+	return CFG_SDRAM_SIZE * 1024 * 1024;
+}
+
+#endif
+
+#if defined(CONFIG_PCI)
+/*
+ * Initialize PCI Devices, report devices found.
+ */
+
+#ifndef CONFIG_PCI_PNP
+static struct pci_config_table pci_fsl86xxads_config_table[] = {
+	{PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
+	 PCI_IDSEL_NUMBER, PCI_ANY_ID,
+	 pci_cfgfunc_config_device, {PCI_ENET0_IOADDR,
+				 PCI_ENET0_MEMADDR,
+				 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER} },
+	{}
+};
+#endif
+
+
+static struct pci_controller pci1_hose = {
+#ifndef CONFIG_PCI_PNP
+config_table:pci_mpc86xxcts_config_table
+#endif
+};
+#endif /* CONFIG_PCI */
+
+#ifdef CONFIG_PCIE1
+static struct pci_controller pcie1_hose;
+#endif
+
+#ifdef CONFIG_PCIE2
+static struct pci_controller pcie2_hose;
+#endif
+
+int first_free_busno = 0;
+
+void pci_init_board(void)
+{
+	volatile immap_t *immap = (immap_t *) CFG_CCSRBAR;
+	volatile ccsr_gur_t *gur = &immap->im_gur;
+	uint devdisr = gur->devdisr;
+	uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
+	uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16;
+
+	printf( " pci_init_board: devdisr=%x, io_sel=%x, host_agent=%x\n",
+		devdisr, io_sel, host_agent);
+
+
+#ifdef CONFIG_PCIE1
+ {
+	volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE1_ADDR;
+	extern void fsl_pci_init(struct pci_controller *hose);
+	struct pci_controller *hose = &pcie1_hose;
+	int pcie_configured = (io_sel == 1) || (io_sel == 4);
+	int pcie_ep = (host_agent == 0) || (host_agent == 2) ||
+		(host_agent == 5);
+
+	if (pcie_configured && !(devdisr & MPC86xx_DEVDISR_PCIE1)) {
+		printf(" PCIe 1 connected to Uli as %s (base address %x)\n",
+			pcie_ep ? "End Point" : "Root Complex",
+			(uint)pci);
+		if (pci->pme_msg_det)
+			pci->pme_msg_det = 0xffffffff;
+
+		/* inbound */
+		pci_set_region(hose->regions + 0,
+			 CFG_PCI_MEMORY_BUS,
+			 CFG_PCI_MEMORY_PHYS,
+			 CFG_PCI_MEMORY_SIZE,
+			 PCI_REGION_MEM | PCI_REGION_MEMORY);
+
+		/* outbound memory */
+		pci_set_region(hose->regions + 1,
+			 CFG_PCIE1_MEM_BASE,
+			 CFG_PCIE1_MEM_PHYS,
+			 CFG_PCIE1_MEM_SIZE,
+			 PCI_REGION_MEM);
+
+		/* outbound io */
+		pci_set_region(hose->regions + 2,
+			 CFG_PCIE1_IO_BASE,
+			 CFG_PCIE1_IO_PHYS,
+			 CFG_PCIE1_IO_SIZE,
+			 PCI_REGION_IO);
+
+		hose->region_count = 3;
+
+		hose->first_busno = first_free_busno;
+		pci_setup_indirect(hose, (int)&pci->cfg_addr,
+				 (int)&pci->cfg_data);
+
+		fsl_pci_init(hose);
+
+		first_free_busno = hose->last_busno + 1;
+		printf(" PCI-Express 1 on bus %02x - %02x\n",
+			hose->first_busno, hose->last_busno);
+
+	} else
+		puts(" PCI-Express 1: Disabled\n");
+ }
+#else
+	puts("PCI-Express 1: Disabled\n");
+#endif /* CONFIG_PCIE1 */
+
+
+#ifdef CONFIG_PCIE2
+ {
+	volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE2_ADDR;
+	extern void fsl_pci_init(struct pci_controller *hose);
+	struct pci_controller *hose = &pcie2_hose;
+
+	int pcie_configured = (io_sel == 0) || (io_sel == 4);
+	int pcie_ep = (host_agent == 0) || (host_agent == 1) ||
+		(host_agent == 4);
+
+	if (pcie_configured && !(devdisr & MPC86xx_DEVDISR_PCIE2)) {
+		printf(" PCI-Express 2 connected to slot as %s" \
+			" (base address %x)\n",
+			pcie_ep ? "End Point" : "Root Complex",
+			(uint)pci);
+		if (pci->pme_msg_det)
+			pci->pme_msg_det = 0xffffffff;
+
+		/* inbound */
+		pci_set_region(hose->regions + 0,
+			 CFG_PCI_MEMORY_BUS,
+			 CFG_PCI_MEMORY_PHYS,
+			 CFG_PCI_MEMORY_SIZE,
+			 PCI_REGION_MEM | PCI_REGION_MEMORY);
+
+		/* outbound memory */
+		pci_set_region(hose->regions + 1,
+			 CFG_PCIE2_MEM_BASE,
+			 CFG_PCIE2_MEM_PHYS,
+			 CFG_PCIE2_MEM_SIZE,
+			 PCI_REGION_MEM);
+
+		/* outbound io */
+		pci_set_region(hose->regions + 2,
+			 CFG_PCIE2_IO_BASE,
+			 CFG_PCIE2_IO_PHYS,
+			 CFG_PCIE2_IO_SIZE,
+			 PCI_REGION_IO);
+
+		hose->region_count = 3;
+
+		hose->first_busno = first_free_busno;
+		pci_setup_indirect(hose, (int)&pci->cfg_addr,
+				 (int)&pci->cfg_data);
+
+		fsl_pci_init(hose);
+
+		first_free_busno = hose->last_busno + 1;
+		printf(" PCI-Express 2 on bus %02x - %02x\n",
+			hose->first_busno, hose->last_busno);
+	} else
+		puts(" PCI-Express 2: Disabled\n");
+ }
+#else
+	puts("PCI-Express 2: Disabled\n");
+#endif /* CONFIG_PCIE2 */
+
+
+#ifdef CONFIG_PCI1
+ {
+	volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCI1_ADDR;
+	extern void fsl_pci_init(struct pci_controller *hose);
+	struct pci_controller *hose = &pci1_hose;
+	int pci_agent = (host_agent >= 4) && (host_agent <= 6);
+
+	if ( !(devdisr & MPC86xx_DEVDISR_PCI1)) {
+		printf(" PCI connected to PCI slots as %s" \
+			" (base address %x)\n",
+			pci_agent ? "Agent" : "Host",
+			(uint)pci);
+
+		/* inbound */
+		pci_set_region(hose->regions + 0,
+			 CFG_PCI_MEMORY_BUS,
+			 CFG_PCI_MEMORY_PHYS,
+			 CFG_PCI_MEMORY_SIZE,
+			 PCI_REGION_MEM | PCI_REGION_MEMORY);
+
+		/* outbound memory */
+		pci_set_region(hose->regions + 1,
+			 CFG_PCI1_MEM_BASE,
+			 CFG_PCI1_MEM_PHYS,
+			 CFG_PCI1_MEM_SIZE,
+			 PCI_REGION_MEM);
+
+		/* outbound io */
+		pci_set_region(hose->regions + 2,
+			 CFG_PCI1_IO_BASE,
+			 CFG_PCI1_IO_PHYS,
+			 CFG_PCI1_IO_SIZE,
+			 PCI_REGION_IO);
+
+		hose->region_count = 3;
+
+		hose->first_busno = first_free_busno;
+		pci_setup_indirect(hose, (int) &pci->cfg_addr,
+				 (int) &pci->cfg_data);
+
+		fsl_pci_init(hose);
+
+		first_free_busno = hose->last_busno + 1;
+		printf(" PCI on bus %02x - %02x\n",
+			hose->first_busno, hose->last_busno);
+
+
+	} else
+		puts(" PCI: Disabled\n");
+ }
+#endif /* CONFIG_PCI1 */
+}
+
+#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP)
+void
+ft_board_setup(void *blob, bd_t *bd)
+{
+	u32 *p;
+	int len;
+
+	ft_cpu_setup(blob, bd);
+
+	p = ft_get_prop(blob, "/memory/reg", &len);
+	if (p != NULL) {
+		*p++ = cpu_to_be32(bd->bi_memstart);
+		*p = cpu_to_be32(bd->bi_memsize);
+	}
+
+#ifdef CONFIG_PCI1
+	p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@8000/bus-range", &len);
+	if (p != NULL) {
+		p[0] = 0;
+		p[1] = pci1_hose.last_busno - pci1_hose.first_busno;
+		debug("pci@8000 first_busno=%d last_busno=%d\n",p[0],p[1]);
+	}
+#endif
+#ifdef CONFIG_PCIE1
+	p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pcie@a000/bus-range", &len);
+	if (p != NULL) {
+		p[0] = 0;
+		p[1] = pcie1_hose.last_busno - pcie1_hose.first_busno;
+		debug("pcie@9000 first_busno=%d last_busno=%d\n",p[0],p[1]);
+	}
+#endif
+#ifdef CONFIG_PCIE2
+	p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pcie@9000/bus-range", &len);
+	if (p != NULL) {
+		p[0] = 0;
+		p[1] = pcie2_hose.last_busno - pcie2_hose.first_busno;
+		debug("pcie@9000 first_busno=%d last_busno=%d\n",p[0],p[1]);
+	}
+#endif
+
+}
+#endif
+
+/*
+ * get_board_sys_clk
+ * Reads the FPGA on board for CONFIG_SYS_CLK_FREQ
+ */
+
+unsigned long
+get_board_sys_clk(ulong dummy)
+{
+	u8 i, go_bit, rd_clks;
+	ulong val = 0;
+	ulong a;
+
+	a = PIXIS_BASE + PIXIS_SPD;
+	i = in8(a);
+	i &= 0x07;
+
+	switch (i) {
+	case 0:
+		val = 33333000;
+		break;
+	case 1:
+		val = 39999600;
+		break;
+	case 2:
+		val = 49999500;
+		break;
+	case 3:
+		val = 66666000;
+		break;
+	case 4:
+		val = 83332500;
+		break;
+	case 5:
+		val = 99999000;
+		break;
+	case 6:
+		val = 133332000;
+		break;
+	case 7:
+		val = 166665000;
+		break;
+	}
+
+	return val;
+}
diff --git a/board/freescale/mpc8610hpcd/u-boot.lds b/board/freescale/mpc8610hpcd/u-boot.lds
new file mode 100644
index 000000000..ae9c6c4a0
--- /dev/null
+++ b/board/freescale/mpc8610hpcd/u-boot.lds
@@ -0,0 +1,135 @@
+/*
+ * Copyright 2007 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+
+SECTIONS
+{
+
+  /* Read-only sections, merged into text segment: */
+  .interp : { *(.interp) }
+  .hash		 : { *(.hash)		}
+  .dynsym	 : { *(.dynsym)		}
+  .dynstr	 : { *(.dynstr)		}
+  .rel.text	 : { *(.rel.text)	}
+  .rela.text	 : { *(.rela.text)	}
+  .rel.data	 : { *(.rel.data)	}
+  .rela.data	 : { *(.rela.data)	}
+  .rel.rodata	 : { *(.rel.rodata)	}
+  .rela.rodata	 : { *(.rela.rodata)	}
+  .rel.got	 : { *(.rel.got)	}
+  .rela.got	 : { *(.rela.got)	}
+  .rel.ctors	 : { *(.rel.ctors)	}
+  .rela.ctors	 : { *(.rela.ctors)	}
+  .rel.dtors	 : { *(.rel.dtors)	}
+  .rela.dtors	 : { *(.rela.dtors)	}
+  .rel.bss	 : { *(.rel.bss)	}
+  .rela.bss	 : { *(.rela.bss)	}
+  .rel.plt	 : { *(.rel.plt)	}
+  .rela.plt	 : { *(.rela.plt)	}
+  .init		 : { *(.init)	}
+  .plt : { *(.plt) }
+  .text :
+  {
+    cpu/mpc86xx/start.o	(.text)
+    board/freescale/mpc8610hpcd/init.o (.bootpg)
+    cpu/mpc86xx/traps.o (.text)
+    cpu/mpc86xx/interrupts.o (.text)
+    cpu/mpc86xx/cpu_init.o (.text)
+    cpu/mpc86xx/cpu.o (.text)
+    cpu/mpc86xx/speed.o (.text)
+    common/dlmalloc.o (.text)
+    lib_generic/crc32.o (.text)
+    lib_ppc/extable.o (.text)
+    lib_generic/zlib.o (.text)
+    *(.text)
+    *(.fixup)
+    *(.got1)
+   }
+    _etext = .;
+    PROVIDE (etext = .);
+    .rodata    :
+   {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini	     : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+  __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+  .data	   :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss	     :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}

From 9553df86d3a319c3a1a7cde7e4edd6eeb5aa64c7 Mon Sep 17 00:00:00 2001
From: Jon Loeliger <jdl@freescale.com>
Date: Tue, 16 Oct 2007 15:26:51 -0500
Subject: [PATCH 002/108] Initial mpc8610hpcd cpu/, README and include/ files.

Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
Signed-off-by: Mahesh Jade <mahesh.jade@freescale.com>
Signed-off-by: Jason Jin <Jason.jin@freescale.com>
Signed-off-by: Jon Loeliger <jdl@freescale.com>
---
 cpu/mpc86xx/cpu.c             |  15 +-
 doc/README.mpc8610hpcd        |  67 ++++
 include/asm-ppc/processor.h   |   1 +
 include/configs/MPC8610HPCD.h | 660 ++++++++++++++++++++++++++++++++++
 4 files changed, 741 insertions(+), 2 deletions(-)
 create mode 100644 doc/README.mpc8610hpcd
 create mode 100644 include/configs/MPC8610HPCD.h

diff --git a/cpu/mpc86xx/cpu.c b/cpu/mpc86xx/cpu.c
index 9456471e8..bbc0cd600 100644
--- a/cpu/mpc86xx/cpu.c
+++ b/cpu/mpc86xx/cpu.c
@@ -41,6 +41,8 @@ checkcpu(void)
 	uint major, minor;
 	uint lcrr;		/* local bus clock ratio register */
 	uint clkdiv;		/* clock divider portion of lcrr */
+	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile ccsr_gur_t *gur = &immap->im_gur;
 
 	puts("Freescale PowerPC\n");
 
@@ -54,8 +56,14 @@ checkcpu(void)
 
 	switch (ver) {
 	case PVR_VER(PVR_86xx):
-		puts("E600");
-		break;
+	{
+		uint msscr0 = mfspr(MSSCR0);
+		printf("E600 Core %d", (msscr0 & 0x20) ? 1 : 0 );
+		if (gur->pordevsr & MPC86xx_PORDEVSR_CORE1TE)
+			puts("\n    Core1Translation Enabled");
+		debug(" (MSSCR0=%x, PORDEVSR=%x)", msscr0, gur->pordevsr);
+	}
+	break;
 	default:
 		puts("Unknown");
 		break;
@@ -76,6 +84,9 @@ checkcpu(void)
 		puts("8641");
 	    }
 	    break;
+	case SVR_8610:
+		puts("8610");
+		break;
 	default:
 		puts("Unknown");
 		break;
diff --git a/doc/README.mpc8610hpcd b/doc/README.mpc8610hpcd
new file mode 100644
index 000000000..949dcb265
--- /dev/null
+++ b/doc/README.mpc8610hpcd
@@ -0,0 +1,67 @@
+Freescale MPC8610HPCD board
+===========================
+
+
+Building U-Boot
+---------------
+
+    $ make MPC8610HPCD_config
+    Configuring for MPC8610HPCD board...
+
+    $ make
+
+
+Flashing U-Boot
+---------------
+The flash is 128M starting at 0xF800_0000.
+
+The alternate image is at 0xFBF0_0000
+The      boot image is at 0xFFF0_0000.
+
+
+To Flash U-Boot into the booting bank:
+
+	tftp 1000000 u-boot.bin
+	protect off all
+	erase fff00000 +$filesize
+	cp.b 1000000 fff00000 $filesize
+
+
+To Flash U-boot into the alternate bank
+
+	tftp 1000000 u-boot.bin
+	erase fbf00000 +$filesize
+	cp.b 1000000 fbf00000 $filesize
+
+
+pixis_reset command
+-------------------
+A new command, "pixis_reset", is introduced to reset mpc8610hpcd board
+using the FPGA sequencer.  When the board restarts, it has the option
+of using either the current or alternate flash bank as the boot
+image, with or without the watchdog timer enabled, and finally with
+or without frequency changes.
+
+Usage is;
+
+	pixis_reset
+	pixis_reset altbank
+	pixis_reset altbank wd
+	pixis_reset altbank cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>
+	pixis_reset cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>
+
+Examples;
+
+	/* reset to current bank, like "reset" command */
+	pixis_reset
+
+	/* reset board but use the to alternate flash bank */
+	pixis_reset altbank
+
+	/* reset board, use alternate flash bank with watchdog timer enabled*/
+	pixis_reset altbank wd
+
+	/* reset board to alternate bank with frequency changed.
+	 * 40 is SYSCLK, 2.5 is COREPLL ratio, 10 is MPXPLL ratio
+	 */
+	pixis-reset altbank cf 40 2.5 10
diff --git a/include/asm-ppc/processor.h b/include/asm-ppc/processor.h
index 0a160e251..07c1de05b 100644
--- a/include/asm-ppc/processor.h
+++ b/include/asm-ppc/processor.h
@@ -875,6 +875,7 @@
 #define SVR_8544_E	0x803C
 #define SVR_8548	0x8031
 #define SVR_8548_E	0x8039
+#define SVR_8610	0x80A0
 #define SVR_8641	0x8090
 #define SVR_8568_E	0x807D
 
diff --git a/include/configs/MPC8610HPCD.h b/include/configs/MPC8610HPCD.h
new file mode 100644
index 000000000..be3434a4c
--- /dev/null
+++ b/include/configs/MPC8610HPCD.h
@@ -0,0 +1,660 @@
+/*
+ * Copyright 2007 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * Version 2 as published by the Free Software Foundation.
+ */
+
+/*
+ * MPC8610HPCD board configuration file
+ *
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* High Level Configuration Options */
+#define CONFIG_MPC86xx		1	/* MPC86xx */
+#define CONFIG_MPC8610		1	/* MPC8610 specific */
+#define CONFIG_MPC8610HPCD	1	/* MPC8610HPCD board specific */
+#define CONFIG_NUM_CPUS		1	/* Number of CPUs in the system */
+#define CONFIG_LINUX_RESET_VEC	0x100	/* Reset vector used by Linux */
+
+#ifdef RUN_DIAG
+#define CFG_DIAG_ADDR		0xff800000
+#endif
+
+#define CFG_RESET_ADDRESS	0xfff00100
+
+#define CONFIG_PCI		1	/* Enable PCI/PCIE*/
+#define CONFIG_PCI1		1	/* PCI controler 1 */
+#define CONFIG_PCIE1		1	/* PCIe 1 connected to ULI bridge */
+#define CONFIG_PCIE2		1	/* PCIe 2 connected to slot */
+#define CONFIG_FSL_PCI_INIT	1	/* Use common FSL init code */
+
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_SPD_EEPROM		/* Use SPD for DDR */
+#undef CONFIG_DDR_DLL			/* possible DLL fix needed */
+#define CONFIG_DDR_2T_TIMING		/* Sets the 2T timing bit */
+#define CONFIG_DDR_ECC			/* only for ECC DDR module */
+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER	/* DDR controller or DMA? */
+#define CONFIG_MEM_INIT_VALUE		0xDeadBeef
+#define CONFIG_NUM_DDR_CONTROLLERS	1
+#define CONFIG_INTERRUPTS		/* enable pci, srio, ddr interrupts */
+
+#define CONFIG_ALTIVEC		1
+
+/*
+ * L2CR setup -- make sure this is right for your board!
+ */
+#define CFG_L2
+#define L2_INIT		0
+#define L2_ENABLE	(L2CR_L2E)
+
+#ifndef CONFIG_SYS_CLK_FREQ
+#define CONFIG_SYS_CLK_FREQ	get_board_sys_clk(0)
+#endif
+
+#define CONFIG_BOARD_EARLY_INIT_F	1	/* Call board_pre_init */
+
+#undef	CFG_DRAM_TEST			/* memory test, takes time */
+#define CFG_MEMTEST_START	0x00200000	/* memtest region */
+#define CFG_MEMTEST_END		0x00400000
+#define CFG_ALT_MEMTEST
+
+/*
+ * Base addresses -- Note these are effective addresses where the
+ * actual resources get mapped (not physical addresses)
+ */
+#define CFG_CCSRBAR_DEFAULT	0xff700000	/* CCSRBAR Default */
+#define CFG_CCSRBAR		0xe0000000	/* relocated CCSRBAR */
+#define CFG_IMMR		CFG_CCSRBAR	/* PQII uses CFG_IMMR */
+
+#define CFG_PCI1_ADDR		(CFG_CCSRBAR+0x8000)
+#define CFG_PCIE1_ADDR		(CFG_CCSRBAR+0xa000)
+#define CFG_PCIE2_ADDR		(CFG_CCSRBAR+0x9000)
+
+#define CFG_DIU_ADDR		(CFG_CCSRBAR+0x2c000)
+
+/*
+ * DDR Setup
+ */
+#define CFG_DDR_SDRAM_BASE	0x00000000	/* DDR is system memory*/
+#define CFG_SDRAM_BASE		CFG_DDR_SDRAM_BASE
+#define CONFIG_VERY_BIG_RAM
+
+#define MPC86xx_DDR_SDRAM_CLK_CNTL
+
+#if defined(CONFIG_SPD_EEPROM)
+/*
+ * Determine DDR configuration from I2C interface.
+ */
+#define SPD_EEPROM_ADDRESS1		0x51		/* DDR DIMM */
+#else
+/*
+ * Manually set up DDR1 parameters
+ */
+
+#define CFG_SDRAM_SIZE	256		/* DDR is 256MB */
+
+#if 0 /* TODO */
+#define CFG_DDR_CS0_BNDS	0x0000000F
+#define CFG_DDR_CS0_CONFIG	0x80010202	/* Enable, no interleaving */
+#define CFG_DDR_EXT_REFRESH	0x00000000
+#define CFG_DDR_TIMING_0	0x00260802
+#define CFG_DDR_TIMING_1	0x3935d322
+#define CFG_DDR_TIMING_2	0x14904cc8
+#define CFG_DDR_MODE_1		0x00480432
+#define CFG_DDR_MODE_2		0x00000000
+#define CFG_DDR_INTERVAL	0x06180100
+#define CFG_DDR_DATA_INIT	0xdeadbeef
+#define CFG_DDR_CLK_CTRL	0x03800000
+#define CFG_DDR_OCD_CTRL	0x00000000
+#define CFG_DDR_OCD_STATUS	0x00000000
+#define CFG_DDR_CONTROL		0xe3008000	/* Type = DDR2 */
+#define CFG_DDR_CONTROL2	0x04400010
+
+#define CFG_DDR_ERR_INT_EN	0x00000000
+#define CFG_DDR_ERR_DIS		0x00000000
+#define CFG_DDR_SBE		0x000f0000
+ /* Not used in fixed_sdram function */
+#define CFG_DDR_MODE		0x00000022
+#define CFG_DDR_CS1_BNDS	0x00000000
+#define CFG_DDR_CS2_BNDS	0x00000FFF	/* Not done */
+#define CFG_DDR_CS3_BNDS	0x00000FFF	/* Not done */
+#define CFG_DDR_CS4_BNDS	0x00000FFF	/* Not done */
+#define CFG_DDR_CS5_BNDS	0x00000FFF	/* Not done */
+#endif
+#endif
+
+#define CFG_ID_EEPROM
+#define ID_EEPROM_ADDR		0x57
+
+
+#define CFG_FLASH_BASE		0xf0000000 /* start of FLASH 128M */
+#define CFG_FLASH_BASE2		0xf8000000
+
+#define CFG_FLASH_BANKS_LIST {CFG_FLASH_BASE, CFG_FLASH_BASE2}
+
+#define CFG_BR0_PRELIM		0xf8001001 /* port size 16bit */
+#define CFG_OR0_PRELIM		0xf8006e65 /* 128MB NOR Flash*/
+
+#define CFG_BR1_PRELIM		0xf0001001 /* port size 16bit */
+#define CFG_OR1_PRELIM		0xf8006e65 /* 128MB Promjet */
+#if 0 /* TODO */
+#define CFG_BR2_PRELIM		0xf0000000
+#define CFG_OR2_PRELIM		0xf0000000 /* 256MB NAND Flash - bank 1 */
+#endif
+#define CFG_BR3_PRELIM		0xe8000801 /* port size 8bit */
+#define CFG_OR3_PRELIM		0xfff06ff7 /* 1MB PIXIS area*/
+
+
+#define PIXIS_BASE	0xe8000000	/* PIXIS registers */
+#define PIXIS_ID		0x0	/* Board ID at offset 0 */
+#define PIXIS_VER		0x1	/* Board version at offset 1 */
+#define PIXIS_PVER		0x2	/* PIXIS FPGA version at offset 2 */
+#define PIXIS_RST		0x4	/* PIXIS Reset Control register */
+#define PIXIS_AUX		0x6	/* PIXIS Auxiliary register; Scratch */
+#define PIXIS_SPD		0x7	/* Register for SYSCLK speed */
+#define PIXIS_VCTL		0x10	/* VELA Control Register */
+#define PIXIS_VCFGEN0		0x12	/* VELA Config Enable 0 */
+#define PIXIS_VCFGEN1		0x13	/* VELA Config Enable 1 */
+#define PIXIS_VBOOT		0x16	/* VELA VBOOT Register */
+#define PIXIS_VSPEED0		0x17	/* VELA VSpeed 0 */
+#define PIXIS_VSPEED1		0x18	/* VELA VSpeed 1 */
+#define PIXIS_VCLKH		0x19	/* VELA VCLKH register */
+#define PIXIS_VCLKL		0x1A	/* VELA VCLKL register */
+
+#define CFG_MAX_FLASH_BANKS	2		/* number of banks */
+#define CFG_MAX_FLASH_SECT	1024		/* sectors per device */
+
+#undef	CFG_FLASH_CHECKSUM
+#define CFG_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
+#define CFG_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
+#define CFG_MONITOR_BASE	TEXT_BASE	/* start of monitor */
+
+#define CFG_FLASH_CFI_DRIVER
+#define CFG_FLASH_CFI
+#define CFG_FLASH_EMPTY_INFO
+
+#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
+#define CFG_RAMBOOT
+#else
+#undef	CFG_RAMBOOT
+#endif
+
+#if defined(CFG_RAMBOOT)
+#undef CONFIG_SPD_EEPROM
+#define CFG_SDRAM_SIZE	256
+#endif
+
+#undef CONFIG_CLOCKS_IN_MHZ
+
+#define CONFIG_L1_INIT_RAM
+#define CFG_INIT_RAM_LOCK	1
+#ifndef CFG_INIT_RAM_LOCK
+#define CFG_INIT_RAM_ADDR	0xe4010000	/* Initial RAM address */
+#else
+#define CFG_INIT_RAM_ADDR	0xe4000000	/* Initial RAM address */
+#endif
+#define CFG_INIT_RAM_END	0x4000		/* End of used area in RAM */
+
+#define CFG_GBL_DATA_SIZE	128		/* num bytes initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+#define CFG_MONITOR_LEN		(512 * 1024)	/* Reserve 512 KB for Mon */
+#define CFG_MALLOC_LEN		(128 * 1024)	/* Reserved for malloc */
+
+/* Serial Port */
+#define CONFIG_CONS_INDEX	1
+#undef	CONFIG_SERIAL_SOFTWARE_FIFO
+#define CFG_NS16550
+#define CFG_NS16550_SERIAL
+#define CFG_NS16550_REG_SIZE	1
+#define CFG_NS16550_CLK		get_bus_freq(0)
+
+#define CFG_BAUDRATE_TABLE \
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
+
+#define CFG_NS16550_COM1	(CFG_CCSRBAR+0x4500)
+#define CFG_NS16550_COM2	(CFG_CCSRBAR+0x4600)
+
+/* Use the HUSH parser */
+#define CFG_HUSH_PARSER
+#ifdef	CFG_HUSH_PARSER
+#define CFG_PROMPT_HUSH_PS2 "> "
+#endif
+
+/*
+ * Pass open firmware flat tree to kernel
+ */
+#define CONFIG_OF_FLAT_TREE	1
+#define CONFIG_OF_BOARD_SETUP	1
+
+/* maximum size of the flat tree (8K) */
+#define OF_FLAT_TREE_MAX_SIZE	8192
+
+#define OF_CPU		"PowerPC,8610@0"
+#define OF_SOC		"soc@e0000000"
+#define OF_TBCLK	(bd->bi_busfreq / 4)
+#define OF_STDOUT_PATH	"/soc@e0000000/serial@4500"
+
+#define CFG_64BIT_VSPRINTF	1
+#define CFG_64BIT_STRTOUL	1
+
+/*
+ * I2C
+ */
+#define CONFIG_FSL_I2C		/* Use FSL common I2C driver */
+#define CONFIG_HARD_I2C		/* I2C with hardware support*/
+#undef	CONFIG_SOFT_I2C			/* I2C bit-banged */
+#define CFG_I2C_SPEED		400000	/* I2C speed and slave address */
+#define CFG_I2C_SLAVE		0x7F
+#define CFG_I2C_NOPROBES	{0x69}	/* Don't probe these addrs */
+#define CFG_I2C_OFFSET		0x3000
+
+/*
+ * General PCI
+ * Addresses are mapped 1-1.
+ */
+#define CFG_PCI1_MEM_BASE	0x80000000
+#define CFG_PCI1_MEM_PHYS	CFG_PCI1_MEM_BASE
+#define CFG_PCI1_MEM_SIZE	0x10000000	/* 256M */
+#define CFG_PCI1_IO_BASE	0x00000000
+#define CFG_PCI1_IO_PHYS	0xe1000000
+#define CFG_PCI1_IO_SIZE	0x00100000	/* 1M */
+
+/* PCI view of System Memory */
+#define CFG_PCI_MEMORY_BUS	0x00000000
+#define CFG_PCI_MEMORY_PHYS	0x00000000
+#define CFG_PCI_MEMORY_SIZE	0x80000000
+
+/* For RTL8139 */
+#define KSEG1ADDR(x)	({u32 _x = le32_to_cpu(*(u32 *)(x)); (&_x); })
+#define _IO_BASE		0x00000000
+
+/* controller 1, Base address 0xa000 */
+#define CFG_PCIE1_MEM_BASE	0xa0000000
+#define CFG_PCIE1_MEM_PHYS	CFG_PCIE1_MEM_BASE
+#define CFG_PCIE1_MEM_SIZE	0x10000000	/* 256M */
+#define CFG_PCIE1_IO_BASE	0x00000000
+#define CFG_PCIE1_IO_PHYS	0xe3000000
+#define CFG_PCIE1_IO_SIZE	0x00100000	/* 1M */
+
+/* controller 2, Base Address 0x9000 */
+#define CFG_PCIE2_MEM_BASE	0x90000000
+#define CFG_PCIE2_MEM_PHYS	CFG_PCIE2_MEM_BASE
+#define CFG_PCIE2_MEM_SIZE	0x10000000	/* 256M */
+#define CFG_PCIE2_IO_BASE	0x00000000	/* reuse mem LAW */
+#define CFG_PCIE2_IO_PHYS	0xe2000000
+#define CFG_PCIE2_IO_SIZE	0x00100000	/* 1M */
+
+
+#if defined(CONFIG_PCI)
+
+#define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
+
+#define CONFIG_NET_MULTI
+#define CONFIG_PCI_PNP		/* do pci plug-and-play */
+
+#if 0 /* TODO */
+/* enable onboard uli network support */
+#endif
+
+#define CONFIG_RTL8139
+#define CONFIG_SK98
+#define CONFIG_EEPRO100
+#define CONFIG_TULIP
+
+#if 0 /* TODO */
+/************************************************************
+ * USB support
+ ************************************************************/
+#define CONFIG_USB_OHCI		1
+#define CONFIG_USB_KEYBOARD	1
+#define CFG_DEVICE_DEREGISTER
+#define CFG_USB_INTERRUPT_POLL	1
+#endif
+
+#if !defined(CONFIG_PCI_PNP)
+#define PCI_ENET0_IOADDR	0xe0000000
+#define PCI_ENET0_MEMADDR	0xe0000000
+#define PCI_IDSEL_NUMBER	0x0c	/* slot0->3(IDSEL)=12->15 */
+#endif
+
+#define CONFIG_DOS_PARTITION
+#define CONFIG_SCSI_AHCI
+
+#ifdef CONFIG_SCSI_AHCI
+#define CONFIG_SATA_ULI5288
+#define CFG_SCSI_MAX_SCSI_ID	4
+#define CFG_SCSI_MAX_LUN	1
+#define CFG_SCSI_MAX_DEVICE	(CFG_SCSI_MAX_SCSI_ID * CFG_SCSI_MAX_LUN)
+#define CFG_SCSI_MAXDEVICE	CFG_SCSI_MAX_DEVICE
+#endif
+
+#endif	/* CONFIG_PCI */
+
+/*
+ * BAT0		2G	Cacheable, non-guarded
+ * 0x0000_0000	2G	DDR
+ */
+#define CFG_DBAT0L	(BATL_PP_RW | BATL_MEMCOHERENCE)
+#define CFG_DBAT0U	(BATU_BL_2G | BATU_VS | BATU_VP)
+#define CFG_IBAT0L	(BATL_PP_RW | BATL_MEMCOHERENCE )
+#define CFG_IBAT0U	CFG_DBAT0U
+
+/*
+ * BAT1		1G	Cache-inhibited, guarded
+ * 0x8000_0000	256M	PCI-1 Memory
+ * 0xa000_0000	256M	PCI-Express 1 Memory
+ * 0x9000_0000	256M	PCI-Express 2 Memory
+ */
+
+#define CFG_DBAT1L	(CFG_PCI1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT \
+			| BATL_GUARDEDSTORAGE)
+#define CFG_DBAT1U	(CFG_PCI1_MEM_PHYS | BATU_BL_1G | BATU_VS | BATU_VP)
+#define CFG_IBAT1L	(CFG_PCI1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CFG_IBAT1U	CFG_DBAT1U
+
+/*
+ * BAT2		32M	Cache-inhibited, guarded
+ * 0xe100_0000	1M	PCI-1 I/O
+ * 0xe200_0000	1M	PCI-Express 2 I/O
+ *
+ */
+
+#define CFG_DBAT2L	(CFG_PCI1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT \
+			| BATL_GUARDEDSTORAGE)
+#define CFG_DBAT2U	(CFG_PCI1_IO_PHYS | BATU_BL_32M | BATU_VS | BATU_VP)
+#define CFG_IBAT2L	(CFG_PCI1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CFG_IBAT2U	CFG_DBAT2U
+
+/*
+ * BAT3		1M	Cache-inhibited, guarded
+ * 0xe300_0000	1M	PCI-Express 1 I/O
+ *
+ */
+
+#define CFG_DBAT3L	(CFG_PCIE1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT \
+			| BATL_GUARDEDSTORAGE)
+#define CFG_DBAT3U	(CFG_PCIE1_IO_PHYS | BATU_BL_1M | BATU_VS | BATU_VP)
+#define CFG_IBAT3L	(CFG_PCIE1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CFG_IBAT3U	CFG_DBAT3U
+
+/*
+ * BAT4		4M	Cache-inhibited, guarded
+ * 0xe000_0000	4M	CCSR
+ */
+#define CFG_DBAT4L	(CFG_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT \
+			| BATL_GUARDEDSTORAGE)
+#define CFG_DBAT4U	(CFG_CCSRBAR | BATU_BL_1M | BATU_VS | BATU_VP)
+#define CFG_IBAT4L	(CFG_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CFG_IBAT4U	CFG_DBAT4U
+
+/*
+ * BAT5		128K	Cacheable, non-guarded
+ * 0xe400_0000	128K	Init RAM for stack in the CPU DCache (no backing memory)
+ */
+#define CFG_DBAT5L	(CFG_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
+#define CFG_DBAT5U	(CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
+#define CFG_IBAT5L	CFG_DBAT5L
+#define CFG_IBAT5U	CFG_DBAT5U
+
+/*
+ * BAT6		256M	Cache-inhibited, guarded
+ * 0xf000_0000	256M	FLASH
+ */
+#define CFG_DBAT6L	(CFG_FLASH_BASE	 | BATL_PP_RW | BATL_CACHEINHIBIT \
+			| BATL_GUARDEDSTORAGE)
+#define CFG_DBAT6U	(CFG_FLASH_BASE	 | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CFG_IBAT6L	(CFG_FLASH_BASE | BATL_PP_RW | BATL_MEMCOHERENCE)
+#define CFG_IBAT6U	CFG_DBAT6U
+
+/*
+ * BAT7		4M	Cache-inhibited, guarded
+ * 0xe800_0000	4M	PIXIS
+ */
+#define CFG_DBAT7L	(PIXIS_BASE | BATL_PP_RW | BATL_CACHEINHIBIT \
+			| BATL_GUARDEDSTORAGE)
+#define CFG_DBAT7U	(PIXIS_BASE | BATU_BL_1M | BATU_VS | BATU_VP)
+#define CFG_IBAT7L	(PIXIS_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CFG_IBAT7U	CFG_DBAT7U
+
+
+/*
+ * Environment
+ */
+#ifndef CFG_RAMBOOT
+#define CFG_ENV_IS_IN_FLASH	1
+#define CFG_ENV_ADDR		(CFG_MONITOR_BASE + CFG_MONITOR_LEN)
+#define CFG_ENV_SECT_SIZE	0x20000	/* 126k (one sector) for env */
+#define CFG_ENV_SIZE		0x2000
+#else
+#define CFG_ENV_IS_NOWHERE	1	/* Store ENV in memory only */
+#define CFG_ENV_ADDR		(CFG_MONITOR_BASE - 0x1000)
+#define CFG_ENV_SIZE		0x2000
+#endif
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
+#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
+
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MII
+
+#if defined(CFG_RAMBOOT)
+#undef CONFIG_CMD_ENV
+#endif
+
+#if defined(CONFIG_PCI)
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_SCSI
+#define CONFIG_CMD_EXT2
+#endif
+
+
+#undef CONFIG_WATCHDOG			/* watchdog disabled */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP			/* undef to save memory	*/
+#define CFG_LOAD_ADDR	0x2000000	/* default load address */
+#define CFG_PROMPT	"=> "		/* Monitor Command Prompt */
+
+#if defined(CONFIG_CMD_KGDB)
+#define CFG_CBSIZE	1024		/* Console I/O Buffer Size */
+#else
+#define CFG_CBSIZE	256		/* Console I/O Buffer Size */
+#endif
+
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS	16		/* max number of command args */
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size */
+#define CFG_HZ		1000		/* decrementer freq: 1ms ticks */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ	(8 << 20)	/* Initial Memory map for Linux*/
+
+/* Cache Configuration */
+#define CFG_DCACHE_SIZE		32768
+#define CFG_CACHELINE_SIZE	32
+#if defined(CONFIG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT	5	/*log base 2 of the above value*/
+#endif
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM	0x02		/* Software reboot */
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
+#endif
+
+/*
+ * Environment Configuration
+ */
+#define CONFIG_IPADDR		192.168.1.100
+
+#define CONFIG_HOSTNAME		unknown
+#define CONFIG_ROOTPATH		/opt/nfsroot
+#define CONFIG_BOOTFILE		uImage
+#define CONFIG_UBOOTPATH	8610hpcd/u-boot.bin
+
+#define CONFIG_SERVERIP		192.168.1.1
+#define CONFIG_GATEWAYIP	192.168.1.1
+#define CONFIG_NETMASK		255.255.255.0
+
+/* default location for tftp and bootm */
+#define CONFIG_LOADADDR		1000000
+
+#define CONFIG_BOOTDELAY 10	/* -1 disables auto-boot */
+#undef	CONFIG_BOOTARGS		/* the boot command will set bootargs */
+
+#define CONFIG_BAUDRATE	115200
+
+#if defined(CONFIG_PCI1)
+#define PCI_ENV \
+ "pcireg=md ${a}000 3; echo o;md ${a}c00 25; echo i; md ${a}da0 15;" \
+	"echo e;md ${a}e00 9\0" \
+ "pci1regs=setenv a e0008; run pcireg\0" \
+ "pcierr=md ${a}e00 8; pci d.b $b.0 7 1; pci d.w $b.0 1e 1;" \
+	"pci d.w $b.0 56 1\0" \
+ "pcierrc=mw ${a}e00 ffffffff; pci w.b $b.0 7 ff; pci w.w $b.0 1e ffff;" \
+	"pci w.w $b.0 56 ffff\0"	\
+ "pci1err=setenv a e0008; run pcierr\0"	\
+ "pci1errc=setenv a e0008; run pcierrc\0"
+#else
+#define	PCI_ENV ""
+#endif
+
+#if defined(CONFIG_PCIE1) || defined(CONFIG_PCIE2)
+#define PCIE_ENV \
+ "pciereg=md ${a}000 6; md ${a}020 4; md ${a}bf8 2; echo o;md ${a}c00 25;" \
+	"echo i; md ${a}da0 15; echo e;md ${a}e00 e; echo d; md ${a}f00 c\0" \
+ "pcie1regs=setenv a e000a; run pciereg\0"	\
+ "pcie2regs=setenv a e0009; run pciereg\0"	\
+ "pcieerr=md ${a}020 1; md ${a}e00; pci d.b $b.0 7 1; pci d.w $b.0 1e 1;"\
+	"pci d.w $b.0 56 1; pci d $b.0 104 1; pci d $b.0 110 1;"	\
+	"pci d $b.0 130 1\0" \
+ "pcieerrc=mw ${a}020 ffffffff; mw ${a}e00 ffffffff; pci w.b $b.0 7 ff;"\
+	"pci w.w $b.0 1e ffff; pci w.w $b.0 56 ffff; pci w $b.0 104 ffffffff;" \
+	"pci w $b.0 110 ffffffff; pci w $b.0 130 ffffffff\0"		\
+ "pciecfg=pci d $b.0 0 20; pci d $b.0 100 e; pci d $b.0 400 69\0"	\
+ "pcie1err=setenv a e000a; run pcieerr\0"	\
+ "pcie2err=setenv a e0009; run pcieerr\0"	\
+ "pcie1errc=setenv a e000a; run pcieerrc\0"	\
+ "pcie2errc=setenv a e0009; run pcieerrc\0"
+#else
+#define	PCIE_ENV ""
+#endif
+
+#define DMA_ENV \
+ "dma0=mw ${d}104 ffffffff;mw ${d}110 50000;mw ${d}114 $sad0;mw ${d}118 50000;"\
+	"mw ${d}120 $bc0;mw ${d}100 f03c404; mw ${d}11c $dad0; md ${d}100 9\0" \
+ "dma1=mw ${d}184 ffffffff;mw ${d}190 50000;mw ${d}194 $sad1;mw ${d}198 50000;"\
+	"mw ${d}1a0 $bc1;mw ${d}180 f03c404; mw ${d}19c $dad1; md ${d}180 9\0" \
+ "dma2=mw ${d}204 ffffffff;mw ${d}210 50000;mw ${d}214 $sad2;mw ${d}218 50000;"\
+	"mw ${d}220 $bc2;mw ${d}200 f03c404; mw ${d}21c $dad2; md ${d}200 9\0" \
+ "dma3=mw ${d}284 ffffffff;mw ${d}290 50000;mw ${d}294 $sad3;mw ${d}298 50000;"\
+	"mw ${d}2a0 $bc3;mw ${d}280 f03c404; mw ${d}29c $dad3; md ${d}280 9\0"
+
+
+#define	CONFIG_EXTRA_ENV_SETTINGS				\
+ "netdev=eth0\0"						\
+ "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0"				\
+ "tftpflash=tftpboot $loadaddr $uboot; "			\
+	"protect off " MK_STR(TEXT_BASE) " +$filesize; "	\
+	"erase " MK_STR(TEXT_BASE) " +$filesize; "		\
+	"cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; "	\
+	"protect on " MK_STR(TEXT_BASE) " +$filesize; "	\
+	"cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0"	\
+ "consoledev=ttyS0\0"						\
+ "ramdiskaddr=2000000\0"					\
+ "ramdiskfile=8610hpcd/ramdisk.uboot\0"				\
+ "dtbaddr=c00000\0"						\
+ "dtbfile=8610hpcd/mpc8610_hpcd.dtb\0"				\
+ "bdev=sda3\0"					\
+ "en-wd=mw.b f8100010 0x08; echo -expect:- 08; md.b f8100010 1\0" \
+ "dis-wd=mw.b f8100010 0x00; echo -expect:- 00; md.b f8100010 1\0" \
+ "maxcpus=1"	\
+ "eoi=mw e00400b0 0\0"						\
+ "iack=md e00400a0 1\0"						\
+ "ddrreg=md ${a}000 8; md ${a}080 8;md ${a}100 d; md ${a}140 4;" \
+	"md ${a}bf0 4; md ${a}e00 3; md ${a}e20 3; md ${a}e40 7;" \
+	"md ${a}f00 5\0" \
+ "ddr1regs=setenv a e0002; run ddrreg\0" \
+ "gureg=md ${a}000 2c; md ${a}0b0 1; md ${a}0c0 1; md ${a}800 1;" \
+	"md ${a}900 6; md ${a}a00 1; md ${a}b20 3; md ${a}e00 1;" \
+	"md ${a}e60 1; md ${a}ef0 1d\0" \
+ "guregs=setenv a e00e0; run gureg\0" \
+ "mcmreg=md ${a}000 1b; md ${a}bf8 2; md ${a}e00 5\0" \
+ "mcmregs=setenv a e0001; run mcmreg\0" \
+ "diuregs=md e002c000 1d\0" \
+ "dium=mw e002c01c\0" \
+ "diuerr=md e002c014 1\0" \
+ "othbootargs=debug\0" \
+ "pmregs=md e00e1000 2b\0" \
+ "lawregs=md e0000c08 4b\0" \
+ "lbcregs=md e0005000 36\0" \
+ "dma0regs=md e0021100 12\0" \
+ "dma1regs=md e0021180 12\0" \
+ "dma2regs=md e0021200 12\0" \
+ "dma3regs=md e0021280 12\0" \
+ PCI_ENV \
+ PCIE_ENV \
+ DMA_ENV
+
+#define CONFIG_NFSBOOTCOMMAND					\
+ "setenv bootargs root=/dev/nfs rw "				\
+	"nfsroot=$serverip:$rootpath "				\
+	"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
+	"console=$consoledev,$baudrate $othbootargs;"		\
+ "tftp $loadaddr $bootfile;"					\
+ "tftp $dtbaddr $dtbfile;"					\
+ "bootm $loadaddr - $dtbaddr"
+
+#define CONFIG_RAMBOOTCOMMAND \
+ "setenv bootargs root=/dev/ram rw "				\
+	"console=$consoledev,$baudrate $othbootargs;"		\
+ "tftp $ramdiskaddr $ramdiskfile;"				\
+ "tftp $loadaddr $bootfile;"					\
+ "tftp $dtbaddr $dtbfile;"					\
+ "bootm $loadaddr $ramdiskaddr $dtbaddr"
+
+#define CONFIG_BOOTCOMMAND		\
+ "setenv bootargs root=/dev/$bdev rw "	\
+	"console=$consoledev,$baudrate $othbootargs;"	\
+ "tftp $loadaddr $bootfile;"		\
+ "tftp $dtbaddr $dtbfile;"		\
+ "bootm $loadaddr - $dtbaddr"
+
+#endif	/* __CONFIG_H */

From 3c89d75409eb26639d36dfa11d4ee3d8b962dc3c Mon Sep 17 00:00:00 2001
From: Jon Loeliger <jdl@freescale.com>
Date: Tue, 16 Oct 2007 15:27:43 -0500
Subject: [PATCH 003/108] Initial mpc8610hpcd Makefile files.

Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
Signed-off-by: Mahesh Jade <mahesh.jade@freescale.com>
Signed-off-by: Jason Jin <Jason.jin@freescale.com>
Signed-off-by: Jon Loeliger <jdl@freescale.com>
---
 MAKEALL  | 1 +
 Makefile | 3 +++
 2 files changed, 4 insertions(+)

diff --git a/MAKEALL b/MAKEALL
index 2597d1fa3..9769c168a 100755
--- a/MAKEALL
+++ b/MAKEALL
@@ -340,6 +340,7 @@ LIST_85xx="		\
 #########################################################################
 
 LIST_86xx="		\
+	MPC8610HPCD	\
 	MPC8641HPCN	\
 	sbc8641d	\
 "
diff --git a/Makefile b/Makefile
index e1cea0d36..f34448792 100644
--- a/Makefile
+++ b/Makefile
@@ -1969,6 +1969,9 @@ TQM8560_config:		unconfig
 ## MPC86xx Systems
 #########################################################################
 
+MPC8610HPCD_config:	unconfig
+	@$(MKCONFIG) $(@:_config=) ppc mpc86xx mpc8610hpcd freescale
+
 MPC8641HPCN_config:    unconfig
 	@$(MKCONFIG) $(@:_config=) ppc mpc86xx mpc8641hpcn freescale
 

From 9c84709eedce9c680dd695984ab7d2328f4f04f5 Mon Sep 17 00:00:00 2001
From: Jon Loeliger <jdl@freescale.com>
Date: Thu, 1 Nov 2007 12:23:29 -0500
Subject: [PATCH 004/108] 86xx: Fix broken variable reference when #def
 DEBUGing.

Sometimes you can't reference the DDR2 controller variables.

Signed-off-by: Jon Loeliger <jdl@freescale.com>
---
 cpu/mpc86xx/spd_sdram.c | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/cpu/mpc86xx/spd_sdram.c b/cpu/mpc86xx/spd_sdram.c
index 059097f51..d57bcdf2c 100644
--- a/cpu/mpc86xx/spd_sdram.c
+++ b/cpu/mpc86xx/spd_sdram.c
@@ -1270,10 +1270,12 @@ spd_sdram(void)
 		debug("\nDDR: LAWBAR8=0x%08x\n", mcm->lawbar8);
 		debug("DDR: LAWAR8=0x%08x\n", mcm->lawar8);
 	}
+
+	debug("\nMemory size of DDR2 = 0x%08lx\n", memsize_ddr2);
+
 #endif /* CONFIG_NUM_DDR_CONTROLLERS > 1 */
 
-	debug("\nMemory sizes are DDR1 = 0x%08lx, DDR2 = 0x%08lx\n",
-	      memsize_ddr1, memsize_ddr2);
+	debug("\nMemory size of DDR1 = 0x%08lx\n", memsize_ddr1);
 
 	/*
 	 * If neither DDR controller is enabled return 0.

From a8318ec205c8e8794b5f9f1b8584abadb440e8ba Mon Sep 17 00:00:00 2001
From: Jason Jin <Jason.jin@freescale.com>
Date: Fri, 26 Oct 2007 18:32:00 +0800
Subject: [PATCH 005/108] make 8610 board use pixis reset

Signed-off-by: Jason Jin <Jason.jin@freescale.com>
---
 cpu/mpc86xx/cpu.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/cpu/mpc86xx/cpu.c b/cpu/mpc86xx/cpu.c
index bbc0cd600..11354d38d 100644
--- a/cpu/mpc86xx/cpu.c
+++ b/cpu/mpc86xx/cpu.c
@@ -131,7 +131,7 @@ checkcpu(void)
 static inline void
 soft_restart(unsigned long addr)
 {
-#ifndef CONFIG_MPC8641HPCN
+#if !defined(CONFIG_MPC8641HPCN) && !defined(CONFIG_MPC8610HPCD)
 
 	/*
 	 * SRR0 has system reset vector, SRR1 has default MSR value
@@ -159,7 +159,7 @@ soft_restart(unsigned long addr)
 void
 do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 {
-#ifndef CONFIG_MPC8641HPCN
+#if !defined(CONFIG_MPC8641HPCN) && !defined(CONFIG_MPC8610HPCD)
 
 #ifdef CFG_RESET_ADDRESS
 	ulong addr = CFG_RESET_ADDRESS;

From 9f23ca334a6f5f021ef9e9d0fad9da80d63b2d56 Mon Sep 17 00:00:00 2001
From: Jason Jin <Jason.jin@freescale.com>
Date: Mon, 29 Oct 2007 19:26:21 +0800
Subject: [PATCH 006/108] Unify pixis_reset altbank across board families

Basically, refactor the CFG_PIXIS_VBOOT_MASK values
into the separate board config files.

Signed-off-by: Jason Jin <Jason.jin@freescale.com>
Signed-off-by: Jon Loeliger <jdl@freescale.com>
---
 board/freescale/common/pixis.c | 5 ++++-
 include/configs/MPC8544DS.h    | 1 +
 include/configs/MPC8641HPCN.h  | 1 +
 3 files changed, 6 insertions(+), 1 deletion(-)

diff --git a/board/freescale/common/pixis.c b/board/freescale/common/pixis.c
index fd99a938c..45dcf4dab 100644
--- a/board/freescale/common/pixis.c
+++ b/board/freescale/common/pixis.c
@@ -207,13 +207,16 @@ void read_from_px_regs_altbank(int set)
 	out8(PIXIS_BASE + PIXIS_VCFGEN1, tmp);
 }
 
+#ifndef CFG_PIXIS_VBOOT_MASK
+#define CFG_PIXIS_VBOOT_MASK	0x40
+#endif
 
 void set_altbank(void)
 {
 	u8 tmp;
 
 	tmp = in8(PIXIS_BASE + PIXIS_VBOOT);
-	tmp ^= 0x40;
+	tmp ^= CFG_PIXIS_VBOOT_MASK;
 
 	out8(PIXIS_BASE + PIXIS_VBOOT, tmp);
 }
diff --git a/include/configs/MPC8544DS.h b/include/configs/MPC8544DS.h
index f580ccade..13e2a2c07 100644
--- a/include/configs/MPC8544DS.h
+++ b/include/configs/MPC8544DS.h
@@ -198,6 +198,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 #define PIXIS_VSPEED1		0x18	/* VELA VSpeed 1 */
 #define PIXIS_VCLKH		0x19	/* VELA VCLKH register */
 #define PIXIS_VCLKL		0x1A	/* VELA VCLKL register */
+#define CFG_PIXIS_VBOOT_MASK	0x40    /* Reset altbank mask*/
 
 
 /* define to use L1 as initial stack */
diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h
index aa6dbc47a..6f8724026 100644
--- a/include/configs/MPC8641HPCN.h
+++ b/include/configs/MPC8641HPCN.h
@@ -201,6 +201,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 #define PIXIS_VSPEED1		0x18	/* VELA VSpeed 1 */
 #define PIXIS_VCLKH		0x19	/* VELA VCLKH register */
 #define PIXIS_VCLKL		0x1A	/* VELA VCLKL register */
+#define CFG_PIXIS_VBOOT_MASK	0x40    /* Reset altbank mask*/
 
 #define CFG_MAX_FLASH_BANKS	2		/* number of banks */
 #define CFG_MAX_FLASH_SECT	128		/* sectors per device */

From f3bceaab230b4748d0afc4109b6837308f018b40 Mon Sep 17 00:00:00 2001
From: Jason Jin <Jason.jin@freescale.com>
Date: Fri, 26 Oct 2007 18:31:59 +0800
Subject: [PATCH 007/108] Fix the BAT definition of PCI IO on 8610 board

The address in the BAT register is aligned with the BAT size.
The original definition actually did not define BAT for PCIE2 IO.
This patch fix this.

Signed-off-by: Jason Jin <Jason.jin@freescale.com>
---
 include/configs/MPC8610HPCD.h | 16 +++++++---------
 1 file changed, 7 insertions(+), 9 deletions(-)

diff --git a/include/configs/MPC8610HPCD.h b/include/configs/MPC8610HPCD.h
index be3434a4c..8bbe447a6 100644
--- a/include/configs/MPC8610HPCD.h
+++ b/include/configs/MPC8610HPCD.h
@@ -361,28 +361,26 @@
 #define CFG_IBAT1U	CFG_DBAT1U
 
 /*
- * BAT2		32M	Cache-inhibited, guarded
+ * BAT2		16M	Cache-inhibited, guarded
  * 0xe100_0000	1M	PCI-1 I/O
- * 0xe200_0000	1M	PCI-Express 2 I/O
- *
  */
 
 #define CFG_DBAT2L	(CFG_PCI1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT \
 			| BATL_GUARDEDSTORAGE)
-#define CFG_DBAT2U	(CFG_PCI1_IO_PHYS | BATU_BL_32M | BATU_VS | BATU_VP)
+#define CFG_DBAT2U	(CFG_PCI1_IO_PHYS | BATU_BL_16M | BATU_VS | BATU_VP)
 #define CFG_IBAT2L	(CFG_PCI1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
 #define CFG_IBAT2U	CFG_DBAT2U
 
 /*
- * BAT3		1M	Cache-inhibited, guarded
+ * BAT3		32M	Cache-inhibited, guarded
+ * 0xe200_0000	1M	PCI-Express 2 I/O
  * 0xe300_0000	1M	PCI-Express 1 I/O
- *
  */
 
-#define CFG_DBAT3L	(CFG_PCIE1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT \
+#define CFG_DBAT3L	(CFG_PCIE2_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT \
 			| BATL_GUARDEDSTORAGE)
-#define CFG_DBAT3U	(CFG_PCIE1_IO_PHYS | BATU_BL_1M | BATU_VS | BATU_VP)
-#define CFG_IBAT3L	(CFG_PCIE1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CFG_DBAT3U	(CFG_PCIE2_IO_PHYS | BATU_BL_32M | BATU_VS | BATU_VP)
+#define CFG_IBAT3L	(CFG_PCIE2_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
 #define CFG_IBAT3U	CFG_DBAT3U
 
 /*

From 761421ccca80a9fb37b19c37aa61d46ef75e0647 Mon Sep 17 00:00:00 2001
From: Jason Jin <Jason.jin@freescale.com>
Date: Mon, 29 Oct 2007 19:26:21 +0800
Subject: [PATCH 008/108] 8610: Actually enable pixis_reset CONFIGs

Signed-off-by: Jason Jin <Jason.jin@freescale.com>
---
 include/configs/MPC8610HPCD.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/include/configs/MPC8610HPCD.h b/include/configs/MPC8610HPCD.h
index 8bbe447a6..8b6b117f3 100644
--- a/include/configs/MPC8610HPCD.h
+++ b/include/configs/MPC8610HPCD.h
@@ -151,6 +151,7 @@
 #define CFG_OR3_PRELIM		0xfff06ff7 /* 1MB PIXIS area*/
 
 
+#define CONFIG_FSL_PIXIS	1	/* use common PIXIS code */
 #define PIXIS_BASE	0xe8000000	/* PIXIS registers */
 #define PIXIS_ID		0x0	/* Board ID at offset 0 */
 #define PIXIS_VER		0x1	/* Board version at offset 1 */
@@ -166,6 +167,7 @@
 #define PIXIS_VSPEED1		0x18	/* VELA VSpeed 1 */
 #define PIXIS_VCLKH		0x19	/* VELA VCLKH register */
 #define PIXIS_VCLKL		0x1A	/* VELA VCLKL register */
+#define CFG_PIXIS_VBOOT_MASK	0x0C    /* Reset altbank mask*/
 
 #define CFG_MAX_FLASH_BANKS	2		/* number of banks */
 #define CFG_MAX_FLASH_SECT	1024		/* sectors per device */

From 1815338fbd1c0f94f8276d2891b99caa5a05f622 Mon Sep 17 00:00:00 2001
From: York Sun <yorksun@freescale.com>
Date: Mon, 29 Oct 2007 13:57:53 -0500
Subject: [PATCH 009/108] 8610: Make some extra debug environment variables
 conditional.

One may #define ENV_DEBUG to get them back again.

Signed-off-by: York Sun <yorksun@freescale.com>
---
 include/configs/MPC8610HPCD.h | 13 ++++++++++++-
 1 file changed, 12 insertions(+), 1 deletion(-)

diff --git a/include/configs/MPC8610HPCD.h b/include/configs/MPC8610HPCD.h
index 8b6b117f3..9fa42f32d 100644
--- a/include/configs/MPC8610HPCD.h
+++ b/include/configs/MPC8610HPCD.h
@@ -587,7 +587,7 @@
  "dma3=mw ${d}284 ffffffff;mw ${d}290 50000;mw ${d}294 $sad3;mw ${d}298 50000;"\
 	"mw ${d}2a0 $bc3;mw ${d}280 f03c404; mw ${d}29c $dad3; md ${d}280 9\0"
 
-
+#ifdef ENV_DEBUG
 #define	CONFIG_EXTRA_ENV_SETTINGS				\
  "netdev=eth0\0"						\
  "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0"				\
@@ -632,6 +632,17 @@
  PCI_ENV \
  PCIE_ENV \
  DMA_ENV
+#else
+#define CONFIG_EXTRA_ENV_SETTINGS                               \
+ "netdev=eth0\0"                                                \
+ "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0"                         \
+ "consoledev=ttyS0\0"                                           \
+ "ramdiskaddr=2000000\0"                                        \
+ "ramdiskfile=8610hpcd/ramdisk.uboot\0"                         \
+ "dtbaddr=c00000\0"                                             \
+ "dtbfile=8610hpcd/mpc8610_hpcd.dtb\0"                          \
+ "bdev=sda3\0"
+#endif
 
 #define CONFIG_NFSBOOTCOMMAND					\
  "setenv bootargs root=/dev/nfs rw "				\

From 52e5ddfecdda308f75782fae206b677b1810f5f9 Mon Sep 17 00:00:00 2001
From: York Sun <yorksun@freescale.com>
Date: Wed, 31 Oct 2007 10:43:59 -0500
Subject: [PATCH 010/108] FSL: Add a freescale bitmap logo.

This Freescale logo is a 340 x 128 x 4bpp BMP file
that can be displayed by the DIU Framebuffer driver.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Jon Loeliger <jdl@freescale.com>
---
 board/freescale/common/fsl_logo_bmp.c | 878 ++++++++++++++++++++++++++
 1 file changed, 878 insertions(+)
 create mode 100644 board/freescale/common/fsl_logo_bmp.c

diff --git a/board/freescale/common/fsl_logo_bmp.c b/board/freescale/common/fsl_logo_bmp.c
new file mode 100644
index 000000000..956dbee9d
--- /dev/null
+++ b/board/freescale/common/fsl_logo_bmp.c
@@ -0,0 +1,878 @@
+/*
+ * Copyright 2007 Freescale Semiconductor, Inc.
+ * York Sun <yorksun@freescale.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*---------------------------------------------------------------------------
+ * FSL_Logo_BMP --
+ *
+ * A 340x128x4bpp BMP logo.
+ *---------------------------------------------------------------------------
+ */
+unsigned int FSL_Logo_BMP[] = {
+0x424d765c,
+0x00000000,0x00007600,0x00002800,0x00006c01,0x00008000,0x00000100,0x04000000,
+0x0000005c,0x0000130b,0x0000130b,0x00001000,0x00000000,0x00000402,0x04000d91,
+0xbc000b51,0x67001536,0x9a000f2a,0x4b005050,0x50009090,0x90000c70,0x92002e2f,
+0x2e00cfcf,0xcf007c82,0x7c00fbfd,0xfb006f70,0x6f00b0b0,0xb00004bd,0xfa000542,
+0xf9000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0xa9996500,0x0000a999,
+0xa80000aa,0x400006a0,0x00086500,0x86500008,0x699da800,0x0000c999,0x68000056,
+0x5000006a,0x00000a99,0x9a0c6800,0x08699685,0xa5000086,0x99dc4000,0x05999800,
+0x08699dc0,0x0000a600,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x0000008b,0xbb99bbd4,0x004bbb99,0xbba0009b,0x50000bb4,0x0008b900,
+0x5b90005b,0xbb99bbc0,0x0009bb99,0xbb60005b,0xd00000bb,0x0004bbbb,0xbbb9ba00,
+0x4bbbbbbd,0xbd000cbb,0xb9bbb500,0x0cbbba00,0x5bbb9bbb,0x5000db50,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x0000006b,0x980006bd,
+0x006b9800,0x89ba006b,0x600009b5,0x0000bb00,0x4bb000bb,0xd00059bc,0x006b9800,
+0x89bd008b,0xb00000db,0x5006bb50,0x089bbd00,0x5bbc086b,0xb9000bb6,0x00059b50,
+0x0cbd0000,0xbb6000c9,0xb500dba0,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x0000009b,0xa00008bb,0x80bb5000,0x00bb805b,0xd00006ba,
+0x00009b50,0x09b405bb,0x000008bb,0x409bc000,0x049bc009,0xb000006b,0xa009b600,
+0x0009b900,0x5b900005,0xbb005bb0,0x00005bb0,0x08b90005,0xbb00000c,0xb900cbd0,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x0000005c,
+0x800008bb,0x80bb8000,0x0088008b,0x90000cbd,0x0000dbc0,0x0db505b9,0x0000006d,
+0x50bb8000,0x005b9009,0xb50000cb,0xd00bb500,0x0008bb00,0x8b900000,0x9b50cb90,
+0x000006d5,0x00bb000c,0xbd000000,0x9bc08b90,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00ca9bbb,0x00bb5585,0x8558500b,
+0xb00008b9,0x0000cbd0,0x06ba05bb,0x00000000,0x00bb5000,0x000bb806,0xba00008b,
+0x9009b500,0x00009b50,0x0bb00000,0xdbc05b90,0x00000000,0x009b500c,0xb9000000,
+0xcb900bb0,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0xdbbbbb68,0x009bbbbb,0xbbbbb009,0xb50000bb,0x00008b90,0x05b900bb,
+0x40000000,0x009bc000,0x0009bc0c,0xbd00000b,0xb009ba00,0x00006bc0,0x09b50000,
+0xcb608bb0,0x00000000,0x00dbc008,0xbb000000,0x8bb009b8,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000005,0xbb9c8000,0x00cb9555,
+0xc55bb406,0xba00009b,0x50000bb0,0x08bb009b,0xc0000000,0x00abd000,0x000dbc08,
+0xbb00000d,0xb50cb900,0x0000abd0,0x0dbc0000,0x8b9009b5,0x00000000,0x00cbd000,
+0xbb500000,0x8bb006b6,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x0000000c,0xbd000059,0xa08bb800,0x008bb00c,0xb90000db,0xa00009b8,
+0x009b40cb,0x90000089,0x900bb800,0x0009bc00,0xbb50000d,0xbc00bb50,0x0000db90,
+0x0cb60000,0x0bb00cb9,0x00000899,0x008b9000,0xab900000,0x8bb00cbb,0x80000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000008,0xb90000ab,
+0x900ab940,0x00ab9008,0xbb60009b,0xbc000bb8,0x009b5009,0xbd00006b,0xb00cbb80,
+0x005bb800,0xdb950009,0xba00cbb5,0x0005bbb0,0x08b90000,0x09b8009b,0xd00006b9,
+0x000bb000,0x09bd0000,0xdb9005bb,0x9c880000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0xdb96cdbb,0xc000db96,0xcdbbc000,0xbbb999bb,
+0x6b9dbbb4,0x006bc000,0x9b96cdbb,0xc0006bb6,0xc69bd000,0x6bbb9dbb,0xb50006bb,
+0x96db9bb8,0x00bb0000,0x0dbc0049,0xb9acdbbc,0x069bb995,0x089b9aad,0xbb5000bb,
+0xdbbb0000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x059bbb9c,0x00000c9b,0xbbbc0000,0xd98dbbb6,0x059bbb50,0x00596000,0x0c9bbb9c,
+0x0000089b,0xbbb60000,0xc96c9bbb,0x6000005d,0xbbb9cdbc,0x00998000,0x0c960000,
+0xa9bbb9c0,0x0a9bbb9a,0x000a9bbb,0x950000d9,0x8c9b5000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00008400,0x00000000,0x84000000,
+0x00004800,0x00048000,0x00000000,0x00048800,0x00000000,0x88000000,0x00000880,
+0x00000000,0x08800cb6,0x00000000,0x00000000,0x00488000,0x000ab600,0x00000488,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x000005b9,0x00000000,
+0x00000000,0x00000000,0x0005b900,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x000000bb,0x00000000,0x00000000,0x00000000,0x0000bb00,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x000a9c00,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x0000009b,
+0x80000000,0x00000000,0x00000000,0x0000cc00,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x000cbd00,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x000000db,0x50000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x0004c500,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x0000005c,0x50000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x008a66d6,0x6a580000,0x00000000,0x00000000,0x000008c6,
+0xd6d6a580,0x00000000,0x00000000,0x000008ca,0x6d6d6a58,0x00000000,0x00000000,
+0x00000004,0x5a6d6da5,0x80000000,0x00000000,0x00008c6d,0x66c50000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x005cad6d,0x6a580000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00033400,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000009,
+0x99d9999d,0x50000000,0x00a999d9,0x99960000,0x00000000,0x00000008,0xdbbbbbbb,
+0xbbbb9650,0x00000000,0x00000000,0x008dbbbb,0xbbbbbbb9,0x65000000,0x00000000,
+0x005dbbbb,0xbbbbbbbb,0x96800000,0x00000000,0x00000c9b,0xbbbbbbbb,0xb9640000,
+0x00000000,0x00c9bbbb,0xbbbbbd80,0x00c999d9,0x99980000,0x06999d99,0x99600000,
+0x00000008,0x6bbbbbbb,0xbbbb9d50,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x04ffff30,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000009,0xbbbbbbbb,0xd0000000,0x00cbbbbb,
+0xbbbb0000,0x00000000,0x000004db,0xbbbbbbbb,0xbbbbbbb9,0x50000000,0x00000000,
+0x06bbbbbb,0xbbbbbbbb,0xbb950000,0x00000000,0x59bbbbbb,0xbbbbbbbb,0xbbb95000,
+0x00000000,0x00059bbb,0xbbbbbbbb,0xbbbb6800,0x00000000,0x89bbbbbb,0xbbbbbbb9,
+0x806bbbbb,0xbbb40000,0x0abbbbbb,0xbbb00000,0x0000006b,0xbbbbbbbb,0xbbbbbbb9,
+0x50000000,0x00000000,0x00000000,0x00000000,0x00000004,0xffffffff,0x40000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x0000000d,0xbbbbbbbb,0x90000000,0x005bbbbb,0xbbbb8000,0x00000000,0x000089bb,
+0xbbbbbbbb,0xbbbbbbbb,0xbd800000,0x00000008,0x9bbbbbbb,0xbbbbbbbb,0xbbbb9800,
+0x0000000d,0xbbbbbbbb,0xbbbbbbbb,0xbbbbbd00,0x00000000,0x00cbbbbb,0xbbbbbbbb,
+0xbbbbbbc0,0x00000000,0xdbbbbbbb,0xbbbbbbbb,0xba6bbbbb,0xbbb80000,0x05bbbbbb,
+0xbbb40000,0x000009bb,0xbbbbbbbb,0xbbbbbbbb,0xb9800000,0x00000000,0x00000000,
+0x00000000,0x000004ff,0xffffffff,0xf3400000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x0000000a,0xbbbbbbbb,0xb0000000,
+0x008bbbbb,0xbbbbc000,0x00000000,0x0000bbbb,0xbbbbbbbb,0xbbbbbbbb,0xbb950000,
+0x00000009,0xbbbbbbbb,0xbbbbbbbb,0xbbbbbbc0,0x0000089b,0xbbbbbbbb,0xbbbbbbbb,
+0xbbbbbb98,0x00000000,0x0abbbbbb,0xbbbbbbbb,0xbbbbbbbd,0x4000000c,0xbbbbbbbb,
+0xbbbbbbbb,0xbb9bbbbb,0xbbb80000,0x08bbbbbb,0xbbb50000,0x00049bbb,0xbbbbbbbb,
+0xbbbbbbbb,0xbbbc0000,0x00000000,0x00000000,0x00000000,0x0004ffff,0xffffffff,
+0xfff30000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000005,0xbbbbbbbb,0xb8000000,0x0009bbbb,0xbbbb6000,0x00000000,
+0x0009bbbb,0xbbbbbbbb,0xbbbbbbbb,0xbbbbc000,0x000000db,0xbbbbbbbb,0xbbbbbbbb,
+0xbbbbbbb6,0x000089bb,0xbbbbbbbb,0xbbbbbbbb,0xbbbbbbbb,0x80000000,0x8bbbbbbb,
+0xbbbbbbbb,0xbbbbbbbb,0x95000009,0xbbbbbbbb,0xbbbbbbbb,0xbbbbbbbb,0xbbb50000,
+0x00bbbbbb,0xbbb60000,0x0006bbbb,0xbbbbbbbb,0xbbbbbbbb,0xbbbba000,0x00000000,
+0x00000000,0x00000000,0x043fffff,0xffffffff,0xfffff400,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0xbbbbbbbb,
+0xbc000000,0x000dbbbb,0xbbbb9000,0x00000000,0x005bbbbb,0xbbbbbbbb,0xbbbbbbbb,
+0xbbbbbc00,0x000008bb,0xbbbbbbbb,0xbbbbbbbb,0xbbbbbbbb,0x60009bbb,0xbbbbbbbb,
+0xbbbbbbbb,0xbbbbbbbb,0x90000000,0x9bbbbbbb,0xbbbbbbbb,0xbbbbbbbb,0xbb80000b,
+0xbbbbbbbb,0xbbbbbbbb,0xbbbbbbbb,0xbbbc0000,0x009bbbbb,0xbbbd0000,0x008bbbbb,
+0xbbbbbbbb,0xbbbbbbbb,0xbbbbbd00,0x00000000,0x00000000,0x00000000,0x003fffff,
+0xffffffff,0xfffffff0,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0xbbbbbbbb,0xb6000000,0x000abbbb,0xbbbbb000,
+0x00000000,0x009bbbbb,0xbbbbbb65,0x5569bbbb,0xbbbbbbc0,0x00000dbb,0xbbbbbbbb,
+0xb6c5569b,0xbbbbbbbb,0xba08bbbb,0xbbbbbbbb,0x96c55c6b,0xbbbbbbbb,0xb6000005,
+0xbbbbbbbb,0xbbbbbddd,0x9bbbbbbb,0xbbb8004b,0xbbbbbbbb,0xb9655cdb,0xbbbbbbbb,
+0xbbbd0000,0x006bbbbb,0xbbbb0000,0x00dbbbbb,0xbbbbbbdc,0x8c69bbbb,0xbbbbbbc0,
+0x00000000,0x00000000,0x00000000,0x0004ffff,0xffffffff,0xffffffff,0x30000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0xdbbbbbbb,0xb9000000,0x0005bbbb,0xbbbbb800,0x00000000,0x00bbbbbb,0xbbbbd000,
+0x0000cbbb,0xbbbbbbb8,0x00000bbb,0xbbbbbbb9,0x0000000c,0xbbbbbbbb,0xbb5006bb,
+0xbbbbbbd8,0x00000000,0x6bbbbbbb,0xbb400006,0xbbbbbbbb,0xbbb50000,0x08dbbbbb,
+0xbbb9000b,0xbbbbbbbb,0x94000008,0xdbbbbbbb,0xbbb90000,0x00cbbbbb,0xbbbb4000,
+0x00bbbbbb,0xbbbbd400,0x0000cbbb,0xbbbbbbb5,0x00000000,0x00000000,0x00000000,
+0x000004ff,0xffffffff,0xffffffff,0xff400000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x6bbbbbbb,0xbb000000,0x0008bbbb,
+0xbbbbb500,0x00000000,0x0cbbbbbb,0xbbb90000,0x000008bb,0xbbbbbb95,0x00008bbb,
+0xbbbbbb98,0x00000000,0x49bbbbbb,0xbbc0008d,0xbbbbb500,0x00000000,0x0dbbbbbb,
+0xbbc0000b,0xbbbbbbbb,0xbb800000,0x0005bbbb,0xbb98000b,0xbbbbbbbb,0xc0000000,
+0x06bbbbbb,0xbbbb0000,0x008bbbbb,0xbbbb5000,0x08bbbbbb,0xbbb98000,0x0000089b,
+0xbbbbbbbc,0x00000000,0x00000000,0x00000000,0x00000043,0xffffffff,0xffffffff,
+0xfff34000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x5bbbbbbb,0xbb800000,0x0000bbbb,0xbbbbb600,0x00000000,0x0abbbbbb,
+0xbbb50000,0x00000009,0xbbbbbc00,0x0000cbbb,0xbbbbbbc0,0x00000000,0x089bbbbb,
+0xa0000000,0xc9bb8000,0x00000000,0x05bbbbbb,0xbb90000b,0xbbbbbbbb,0xbc000000,
+0x00005bbb,0x95000009,0xbbbbbbbb,0x50000000,0x009bbbbb,0xbbbb5000,0x000bbbbb,
+0xbbbba000,0x0cbbbbbb,0xbbbc0000,0x00000049,0xbbbbba00,0x00000000,0x00000000,
+0x00000000,0x00000000,0x4fffffff,0xffffffff,0xfffff300,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x8bbbbbbb,0xbb500000,
+0x0000dbbb,0xbbbbb900,0x00000000,0x06bbbbbb,0xbbb00000,0x00000004,0xbbbc0000,
+0x0000abbb,0xbbbbbb40,0x00000000,0x0089bba0,0x00000000,0x00680000,0x00000000,
+0x0abbbbbb,0xbbb0008b,0xbbbbbbbb,0xb8000000,0x00000695,0x0000000c,0xbbbbbbbb,
+0xd0000000,0x008bbbbb,0xbbbbc000,0x0009bbbb,0xbbbbd000,0x0cbbbbbb,0xbbb40000,
+0x00000008,0x9bb60000,0x00000000,0x00000000,0x00000000,0x00000000,0x003fffff,
+0xffffffff,0xffff3400,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x0bbbbbbb,0xbb600000,0x00006bbb,0xbbbbb900,0x00000000,
+0x0dbbbbbb,0xbb900000,0x00000000,0x8c000000,0x00006bbb,0xbbbbbb00,0x00000000,
+0x0008a400,0x00000000,0x00000000,0x00000008,0x6bbbbbbb,0xbbb5005b,0xbbbbbbbb,
+0x90000000,0x00000000,0x00000008,0xbbbbbbbb,0xb8000000,0x000dbbbb,0xbbbb6000,
+0x000dbbbb,0xbbbb9000,0x0abbbbbb,0xbbb00000,0x00000000,0x06000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00003fff,0xffffffff,0xfff40000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x0dbbbbbb,
+0xbbd00000,0x00005bbb,0xbbbbbb80,0x00000000,0x06bbbbbb,0xbb900000,0x00000000,
+0x00000000,0x0000abbb,0xbbbbbb00,0x00000000,0x00000000,0x00000000,0x00000000,
+0x0005ad9b,0xbbbbbbbb,0xbbb5008b,0xbbbbbbbb,0x90000000,0x00000000,0x00000000,
+0xdbbbbbbb,0xb9500000,0x000cbbbb,0xbbbb9000,0x000cbbbb,0xbbbbb400,0x0cbbbbbb,
+0xbbb00000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x000004ff,0xffffffff,0xf4000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x06bbbbbb,0xbbb00000,0x00008bbb,0xbbbbbb50,
+0x00000000,0x06bbbbbb,0xbbb00000,0x00000000,0x00000000,0x0000cbbb,0xbbbbbb00,
+0x00000000,0x00000000,0x00000000,0x00000045,0xd9bbbbbb,0xbbbbbbbb,0xbbb5008b,
+0xbbbbbbbb,0x90000000,0x00000000,0x00000000,0x0bbbbbbb,0xbbb95400,0x0004bbbb,
+0xbbbbb000,0x0008bbbb,0xbbbbb800,0x0cbbbbbb,0xbbb00000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000004,0xfffffff4,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x0cbbbbbb,0xbbb80000,0x00000bbb,0xbbbbbb60,0x00000000,0x0cbbbbbb,0xbbbddddd,
+0xdddddddd,0xdddddddd,0xd8005bbb,0xbbbbbbdd,0xdddddddd,0xdddddddd,0xdddd8000,
+0x00008dbb,0xbbbbbbbb,0xbbbbbbbb,0xbbb4000b,0xbbbbbbbb,0x90000000,0x00000000,
+0x00000000,0x05bbbbbb,0xbbbbbb96,0x5000bbbb,0xbbbbb800,0x0000bbbb,0xbbbbba00,
+0x05bbbbbb,0xbbb9dddd,0xdddddddd,0xdddddddd,0xd8000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x43fff400,0x00000000,0x0007e140,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x08bbbbbb,0xbbb50000,0x000009bb,
+0xbbbbbbd0,0x00000000,0x08bbbbbb,0xbbbbbbbb,0xbbbbbbbb,0xbbbbbbbb,0xb8004bbb,
+0xbbbbbbbb,0xbbbbbbbb,0xbbbbbbbb,0xbbbbc000,0x0006bbbb,0xbbbbbbbb,0xbbbbbbbb,
+0xbbd0000b,0xbbbbbbbb,0xb0000000,0x00000000,0x00000000,0x00cbbbbb,0xbbbbbbbb,
+0xbb9c9bbb,0xbbbbbc00,0x00009bbb,0xbbbbbd00,0x00bbbbbb,0xbbbbbbbb,0xbbbbbbbb,
+0xbbbbbbbb,0xbc000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00440000,
+0x00000000,0x07eeeee2,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00bbbbbb,0xbbba0000,0x000006bb,0xbbbbbbb0,0x00000000,0x00bbbbbb,
+0xbbbbbbbb,0xbbbbbbbb,0xbbbbbbbb,0xbc000bbb,0xbbbbbbbb,0xbbbbbbbb,0xbbbbbbbb,
+0xbbbb6000,0x00dbbbbb,0xbbbbbbbb,0xbbbbbbbb,0xb980000d,0xbbbbbbbb,0xb0000000,
+0x00000000,0x00000000,0x00089bbb,0xbbbbbbbb,0xbbbbbbbb,0xbbbbb600,0x0000dbbb,
+0xbbbbb900,0x00bbbbbb,0xbbbbbbbb,0xbbbbbbbb,0xbbbbbbbb,0xb6000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000002,0xeeeeeeee,0x12000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x009bbbbb,0xbbbd0000,
+0x00000cbb,0xbbbbbbb0,0x00000000,0x009bbbbb,0xbbbbbbbb,0xbbbbbbbb,0xbbbbbbbb,
+0xb6000dbb,0xbbbbbbbb,0xbbbbbbbb,0xbbbbbbbb,0xbbbb6000,0x0cbbbbbb,0xbbbbbbbb,
+0xbbbbbbbb,0x94000006,0xbbbbbbbb,0xbc000000,0x00000000,0x00000000,0x00000cbb,
+0xbbbbbbbb,0xbbbbbbbb,0xbbbbb900,0x0000cbbb,0xbbbbbb00,0x006bbbbb,0xbbbbbbbb,
+0xbbbbbbbb,0xbbbbbbbb,0xb6000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x000002ee,0xeeeeeeee,0xee140000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x006bbbbb,0xbbb90000,0x000008bb,0xbbbbbbb5,0x00000000,
+0x00abbbbb,0xbbbbbbbb,0xbbbbbbbb,0xbbbbbbbb,0xb60005bb,0xbbbbbbbb,0xbbbbbbbb,
+0xbbbbbbbb,0xbbbb9000,0x09bbbbbb,0xbbbbbbbb,0xbbbbbb9c,0x00000008,0xbbbbbbbb,
+0xbd000000,0x00000000,0x00000000,0x00000005,0x9bbbbbbb,0xbbbbbbbb,0xbbbbbb00,
+0x00005bbb,0xbbbbbb80,0x00cbbbbb,0xbbbbbbbb,0xbbbbbbbb,0xbbbbbbbb,0xb9000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x0002eeee,0xeeeeeeee,
+0xeeee7000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00cbbbbb,
+0xbbbb8000,0x000000bb,0xbbbbbbb6,0x00000000,0x008bbbbb,0xbbbbbbbb,0xbbbbbbbb,
+0xbbbbbbbb,0xb60008bb,0xbbbbbbbb,0xbbbbbbbb,0xbbbbbbbb,0xbbbbd000,0x0bbbbbbb,
+0xbbbbbbbb,0xbbb96800,0x00000000,0xbbbbbbbb,0xbb000000,0x00000000,0x00000000,
+0x00000000,0x00cd9bbb,0xbbbbbbbb,0xbbbbbb80,0x00000bbb,0xbbbbbbc0,0x000bbbbb,
+0xbbbbbbbb,0xbbbbbbbb,0xbbbbbbbb,0xbd000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x001eeeee,0xeeeeeeee,0xeeeeee40,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x008bbbbb,0xbbbb5000,0x0000009b,0xbbbbbbbb,
+0x00000000,0x0009bbbb,0xbbbb5888,0x88888888,0xcbbbbbbb,0xbd0000db,0xbbbbbbbc,
+0x88888888,0x8885bbbb,0xbbbb9000,0x0bbbbbbb,0xbbbbbb96,0xc8000000,0x00000000,
+0x6bbbbbbb,0xbbc00000,0x00000000,0x00000000,0x00000000,0x0000045c,0x69bbbbbb,
+0xbbbbbbc0,0x000009bb,0xbbbbbb60,0x000dbbbb,0xbbbbc888,0x88888888,0x5bbbbbbb,
+0xb9000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x0047eeee,
+0xeeeeeeee,0xeeeeeee1,0x40000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x000bbbbb,0xbbbba000,0x000000db,0xbbbbbbbb,0xd0000000,0x000cbbbb,0xbbbb6000,
+0x00000000,0x8bbbbbbb,0xb600005b,0xbbbbbbbd,0x00000000,0x0008bbbb,0xbbbbd000,
+0x0bbbbbbb,0xbbb9c000,0x00000000,0x00000000,0x8bbbbbbb,0xbb900000,0x0000000d,
+0x50000000,0x00000000,0x00000000,0x00008dbb,0xbbbbbb60,0x00000dbb,0xbbbbbb90,
+0x0005bbbb,0xbbbbd000,0x00000000,0x8bbbbbbb,0xbd000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x000041ee,0xeeeeeeee,0xeeeeeeee,0xe2000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x0009bbbb,0xbbbbd000,0x000000cb,
+0xbbbbbbbb,0xb9500000,0x00009bbb,0xbbbbb800,0x00000000,0x5bbbbbbb,0xb6000009,
+0xbbbbbbbb,0x50000000,0x0008bbbb,0xbbbbd000,0x0dbbbbbb,0xbb980000,0x00000000,
+0x00000000,0x06bbbbbb,0xbbbd0000,0x0000004b,0xb9800000,0x00000000,0x00000000,
+0x00000cbb,0xbbbbbbd0,0x00000abb,0xbbbbbbb0,0x00009bbb,0xbbbbb500,0x00000000,
+0x8bbbbbbb,0xbd000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00043000,
+0x0000002e,0xeeeeeeee,0xeeeeeeee,0xee120000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x000dbbbb,0xbbbb9000,0x0000008b,0xbbbbbbbb,0xbbb9da58,0x0000cbbb,
+0xbbbbb980,0x00000000,0xdbbbbbbb,0xbc000005,0xbbbbbbbb,0xb0000000,0x0006bbbb,
+0xbbbba000,0x0cbbbbbb,0xbbd00000,0x000000cb,0x50000000,0x08bbbbbb,0xbbbb5000,
+0x0000006b,0xbbb60000,0x0006bbbb,0xbbbb6000,0x000008bb,0xbbbbbbb0,0x000005bb,
+0xbbbbbbb8,0x00005bbb,0xbbbbb980,0x00000000,0x6bbbbbbb,0xba000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x043fff30,0x00000000,0x1eeeeeee,0xeeeeeeee,
+0xeeee1400,0x00000000,0x00000000,0x00000000,0x00000000,0x000cbbbb,0xbbbbb000,
+0x0000000b,0xbbbbbbbb,0xbbbbbbbb,0xb50009bb,0xbbbbbb98,0x00000005,0xbbbbbbbb,
+0xb8000000,0xdbbbbbbb,0xbb800000,0x005bbbbb,0xbbbb5000,0x04bbbbbb,0xbbb00000,
+0x000006bb,0xbd800000,0x00cbbbbb,0xbbbbb600,0x00000cbb,0xbbbbb500,0x0005bbbb,
+0xbbbbb400,0x000000bb,0xbbbbbbb4,0x000004bb,0xbbbbbbbc,0x00000dbb,0xbbbbbb95,
+0x00000008,0xbbbbbbbb,0xb5000000,0x00000000,0x00000000,0x00000000,0x00000004,
+0x3fffffff,0x40000000,0x04eeeeee,0xeeeeeeee,0xeeeeee40,0x00000000,0x00000000,
+0x00000000,0x00000008,0x888cbbbb,0xbbbbbc88,0x88800009,0xbbbbbbbb,0xbbbbbbbb,
+0xba0008bb,0xbbbbbbbb,0x680008ab,0xbbbbbbbb,0x90000000,0x89bbbbbb,0xbbb68000,
+0x0cbbbbbb,0xbbbb0000,0x006bbbbb,0xbbb95000,0x0056bbbb,0xbbb60000,0x0009bbbb,
+0xbbbbbbb6,0x588c9bbb,0xbbbbbb90,0x0000bbbb,0xbbbbbd00,0x000005bb,0xbbbbbbb8,
+0x0000009b,0xbbbbbbb6,0x000000bb,0xbbbbbbbb,0x680000cb,0xbbbbbbbb,0xb0000000,
+0x00000000,0x00000000,0x00000000,0x0000043f,0xffffffff,0xf3000000,0x0002eeee,
+0xeeeeeeee,0xeeee7000,0x00000000,0x00000000,0x00000000,0x0000000b,0xbbbbbbbb,
+0xbbbbbbbb,0xbbb5000d,0xbbbbbbbb,0xbbbbbbbb,0xbd0000cb,0xbbbbbbbb,0xbb999bbb,
+0xbbbbbbbb,0x60000000,0x05bbbbbb,0xbbbbbb99,0xbbbbbbbb,0xbbbd0000,0x008bbbbb,
+0xbbbbbb99,0xbbbbbbbb,0xbbbb9c00,0x00009bbb,0xbbbbbbbb,0xbbbbbbbb,0xbbbbbb90,
+0x0000cbbb,0xbbbbbb98,0x000089bb,0xbbbbbbb8,0x0000009b,0xbbbbbbb9,0x0000005b,
+0xbbbbbbbb,0xbbb99bbb,0xbbbbbbbb,0xd0000000,0x00000000,0x00000000,0x00000000,
+0x00003fff,0xffffffff,0xfff30000,0x000001ee,0xeeeeeeee,0xee140000,0x00000000,
+0x00000000,0x00000000,0x00000009,0xbbbbbbbb,0xbbbbbbbb,0xbbbc000a,0xbbbbbbbb,
+0xbbbbbbbb,0xb9000006,0xbbbbbbbb,0xbbbbbbbb,0xbbbbbbbb,0x40000000,0x00abbbbb,
+0xbbbbbbbb,0xbbbbbbbb,0xbbb80000,0x0005bbbb,0xbbbbbbbb,0xbbbbbbbb,0xbbbbbbd0,
+0x00008bbb,0xbbbbbbbb,0xbbbbbbbb,0xbbbbbb50,0x000009bb,0xbbbbbbbb,0x9d99bbbb,
+0xbbbbbbb0,0x0000006b,0xbbbbbbbb,0x00000005,0xbbbbbbbb,0xbbbbbbbb,0xbbbbbbbb,
+0x80000000,0x00000000,0x00000000,0x00000000,0x003fffff,0xffffffff,0xfffff400,
+0x00000041,0xeeeeeeee,0x14000000,0x00000000,0x00000000,0x00000000,0x00000006,
+0xbbbbbbbb,0xbbbbbbbb,0xbbb60008,0xbbbbbbbb,0xbbbbbbbb,0xbb000000,0x6bbbbbbb,
+0xbbbbbbbb,0xbbbbbbbc,0x00000000,0x000abbbb,0xbbbbbbbb,0xbbbbbbbb,0xbb600000,
+0x00005bbb,0xbbbbbbbb,0xbbbbbbbb,0xbbbbbb50,0x0000049b,0xbbbbbbbb,0xbbbbbbbb,
+0xbbbbbd00,0x000008bb,0xbbbbbbbb,0xbbbbbbbb,0xbbbbbb90,0x0000005b,0xbbbbbbbb,
+0x80000000,0x5bbbbbbb,0xbbbbbbbb,0xbbbbbbb6,0x00005050,0x50500000,0x00000000,
+0x00000000,0x04ffffff,0xffffffff,0xffffff30,0x00000000,0x2eeeee14,0x00000000,
+0x00004400,0x00000000,0x00000000,0x0000000c,0xbbbbbbbb,0xbbbbbbbb,0xbbb90000,
+0xbbbbbbbb,0xbdbbbbbb,0xbb500000,0x05bbbbbb,0xbbbbbbbb,0xbbbbbb90,0x00000000,
+0x00005bbb,0xbbbbbbbb,0xbbbbbbbb,0xb9000000,0x000005bb,0xbbbbbbbb,0xbbbbbbbb,
+0xbbbb9000,0x0000000d,0xbbbbbbbb,0xbbbbbbbb,0xbbbb9000,0x0000005b,0xbbbbbbbb,
+0xbbbbbbbb,0xbbbbbb50,0x0000008b,0xbbbbbbbb,0x50000000,0x05bbbbbb,0xbbbbbbbb,
+0xbbbbbb90,0x0008c068,0x98d00000,0x00000000,0x00000000,0x0004ffff,0xffffffff,
+0xffffffff,0x30000000,0x047e1400,0x00000000,0x0043ff34,0x00000000,0x00000000,
+0x00000008,0xbbbbbbbb,0xbbbbbbbb,0xbbbb0000,0x9bbbbbbb,0xb60a9bbb,0xbbc00000,
+0x008dbbbb,0xbbbbbbbb,0xbbbbbd00,0x00000000,0x000000db,0xbbbbbbbb,0xbbbbbbbb,
+0xd8000000,0x0000008d,0xbbbbbbbb,0xbbbbbbbb,0xbb950000,0x00000000,0x59bbbbbb,
+0xbbbbbbbb,0xbbbd0000,0x00000004,0xdbbbbbbb,0xbbbbbbbb,0xbbbbbc00,0x00000009,
+0xbbbbbbbb,0x60000000,0x000dbbbb,0xbbbbbbbb,0xbbbbbd00,0x0008a06a,0xccd00000,
+0x00000000,0x00000000,0x000003ff,0xffffffff,0xffffffff,0xff400000,0x00040000,
+0x00000000,0x03ffffff,0x30000000,0x00000000,0x00000000,0xdddddbbb,0xbbbbbb9d,
+0xdddd8000,0xdbbbbbbb,0xb90005db,0xbb600000,0x00005dbb,0xbbbbbbbb,0xbbb95000,
+0x00000000,0x00000008,0xdbbbbbbb,0xbbbbbb9c,0x00000000,0x00000000,0x59bbbbbb,
+0xbbbbbbbb,0x95000000,0x00000000,0x00c9bbbb,0xbbbbbbbb,0xb9500000,0x00000000,
+0x059bbbbb,0xbbbbbbbb,0xbbb95000,0x00000009,0xbbbbbbbb,0xd0000000,0x00008dbb,
+0xbbbbbbbb,0xbbb9a000,0x0008a0dd,0x06d00000,0x00000000,0x00000000,0x00000043,
+0xffffffff,0xffffffff,0xfff34000,0x00000000,0x00000043,0xffffffff,0xff400000,
+0x00000000,0x00000000,0x000009bb,0xbbbbbbd0,0x00000000,0x8c5555c5,0x55000000,
+0x85500000,0x0000008c,0xd9bbbbbb,0x9d500000,0x00000000,0x00000000,0x00cd9bbb,
+0xbbb9d500,0x00000000,0x00000000,0x004cd9bb,0xbbbb9dc0,0x00000000,0x00000000,
+0x00005cdb,0xbbbbbb9a,0x50000000,0x00000000,0x0008cdbb,0xbbbbbbb9,0xda800000,
+0x00000006,0xbbbbbbbb,0xb0000000,0x0000000c,0xd9bbbbbb,0x9dc00000,0x0086dc6c,
+0x0cd00000,0x00000000,0x00000000,0x00000000,0x4fffffff,0xffffffff,0xfffff300,
+0x00000000,0x000003ff,0xffffffff,0xffff0000,0x00000000,0x00000000,0x00000dbb,
+0xbbbbbb90,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00008840,
+0x00000000,0x00000000,0x00000000,0x00000008,0x84000000,0x00000000,0x00000000,
+0x00000000,0x88400000,0x00000000,0x00000000,0x00000000,0x08880000,0x00000000,
+0x00000000,0x00000000,0x08888000,0x00000000,0x0000000c,0xbbbbbbbb,0xb8000000,
+0x00000000,0x00008880,0x00000000,0x00888480,0x00800000,0x00000000,0x00000000,
+0x00000000,0x003fffff,0xffffffff,0xfffff400,0x00000000,0x0003ffff,0xffffffff,
+0xfffff300,0x00000000,0x00000000,0x00000abb,0xbbbbbbb8,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000008,0xbbbbbbbb,0xb5000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00043fff,0xffffffff,
+0xfff30000,0x00000000,0x003fffff,0xffffffff,0xfffffff4,0x00000000,0x00000000,
+0x000005bb,0xbbbbbbbb,0x58040000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0xbbbbbbbb,
+0xba000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x000004ff,0xffffffff,0xf3000000,0x00000000,0x00003fff,
+0xffffffff,0xffffffff,0x30000000,0x00000000,0x000000bb,0xbbbbbbbb,0xbbbbb500,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0xdbbbbbbb,0xbd000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000003,
+0xfffffff3,0x00000000,0x00000000,0x000004ff,0xffffffff,0xffffffff,0xff300000,
+0x00000000,0x000000db,0xbbbbbbbb,0xbbbbba00,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x6bbbbbbb,0xb9000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x43fff340,0x00000000,0x00021100,
+0x00000003,0xffffffff,0xffffffff,0xffff4000,0x00000000,0x0000008b,0xbbbbbbbb,
+0xbbbbbd00,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0xcbbbbbbb,0xbb800000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00430000,0x00000000,0x021eeee2,0x00000000,0x03ffffff,0xffffffff,
+0xfffff300,0x00000000,0x0000000d,0xbbbbbbbb,0xbbbbb900,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x8bbbbbbb,0xbb500000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000004,
+0x1eeeeeee,0x14000000,0x004fffff,0xffffffff,0xffffff30,0x00000000,0x00000000,
+0x9bbbbbbb,0xbbbbbb00,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x0bbbbbbb,0xbba00000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x0000041e,0xeeeeeeee,0xee100000,0x00003fff,
+0xffffffff,0xffff3000,0x00000000,0x00000000,0x0dbbbbbb,0xbbbbbb50,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x09bbbbbb,0xbbd00000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00047eee,0xeeeeeeee,0xeeee2000,0x0000003f,0xffffffff,0xff300000,0x00000000,
+0x00000000,0x0059bbbb,0xbbbbbbc0,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x06bbbbbb,
+0xbb900000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x007eeeee,0xeeeeeeee,0xeeeee140,
+0x00000004,0xffffffff,0x30000000,0x00000000,0x00000000,0x00004c66,0xd66a5800,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00808480,0x84800000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
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+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x041ee700,0x00000000,0x0003ff30,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
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+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00040000,0x00000000,0x04ffffff,0x40000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
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+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000004,
+0xffffffff,0xff400000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x000004ff,0xffffffff,0xfff30000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
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+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x0004ffff,0xffffffff,0xfffff400,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x004fffff,0xffffffff,0xfffffff4,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
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+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00043fff,0xffffffff,0xffffffff,0x30000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x000004ff,0xffffffff,
+0xffffffff,0xff400000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00047700,0x00000003,0xffffffff,0xffffffff,0xffff4000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x001eeee4,0x00000000,
+0x4fffffff,0xffffffff,0xfffff300,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x7eeeeeee,0x14000000,0x004fffff,0xffffffff,0xffffff30,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x0000007e,0xeeeeeeee,
+0xee200000,0x00003fff,0xffffffff,0xffff3400,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00002eee,0xeeeeeeee,0xeeee4000,0x000004ff,0xffffffff,
+0xfff40000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x002eeeee,
+0xeeeeeeee,0xeeeee140,0x00000004,0xffffffff,0xf4000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x0041eeee,0xeeeeeeee,0xeeeeeee7,0x00000000,
+0x43fffff4,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00002eee,0xeeeeeeee,0xeeeeeeee,0x12000000,0x004ff400,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00004000,0x0000007e,0xeeeeeeee,0xeeeeeeee,
+0xee100000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x004fff40,0x00000004,0x1eeeeeee,0xeeeeeeee,0xeeee7000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x4ffffff3,0x00000000,0x02eeeeee,
+0xeeeeeeee,0xeeeeee40,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000043,0xffffffff,0xf3000000,0x0001eeee,0xeeeeeeee,0xeeeee200,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x000043ff,0xffffffff,0xfff40000,
+0x00004eee,0xeeeeeeee,0xeee70000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x0043ffff,0xffffffff,0xffff3400,0x0000002e,0xeeeeeeee,0xe7400000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00ffffff,0xffffffff,
+0xffffff30,0x00000000,0x1eeeeee7,0x40000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x0003ffff,0xffffffff,0xffffffff,0x40000000,0x04eee140,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x000003ff,
+0xffffffff,0xffffffff,0xf3000000,0x00024000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x0000004f,0xffffffff,0xffffffff,0xfff30000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x3fffffff,0xffffffff,0xfffff400,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00ffffff,0xffffffff,
+0xfffff300,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x0004ffff,0xffffffff,0xffff3000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x000003ff,
+0xffffffff,0xff400000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x0000004f,0xffffffff,0x30000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x4fffff30,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x003f3000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x0000babe
+};

From a877880c6949e948bd63cd6ea4e216573d2f53dd Mon Sep 17 00:00:00 2001
From: York Sun <yorksun@freescale.com>
Date: Mon, 29 Oct 2007 13:58:39 -0500
Subject: [PATCH 011/108] 8610: Add 8610 DIU display driver

1280x1024 and 1024x768 @ 32 bpp are supported now.
DVI, Single-link LVDS, Double-link LVDS are all supported.

Environmental variable "monitor" is used to specify monitor port.

A new command "diufb" is introduced to reinitialize monitor
and display a BMP file in the memory. So far, 1-bit, 4-bit,
8-bit and 24-bit BMP formats are supported.

    diufb init
        - initialize the diu driver
    Enable the port specified in the environmental variable "monitor"

    diufb addr
        - display bmp file in memory.
    The bmp image should be no bigger than the resolution, 1280x1024
    for DVI and double-link LVDS, 1024x768 for single-link LVDS.

Note, this driver allocate memory but doesn't free it after use
It is written on purpose -- to avoid a failure of reallocation
due to memory fragement.

ECC of DDR is disabled for DIU performance. L2 data cache is also disabled.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Jon loeliger <jdl@freescale.com>
---
 board/freescale/common/Makefile               |   4 +-
 board/freescale/common/fsl_diu_fb.c           | 656 ++++++++++++++++++
 board/freescale/common/fsl_diu_fb.h           |  35 +
 board/freescale/mpc8610hpcd/Makefile          |   4 +-
 board/freescale/mpc8610hpcd/mpc8610hpcd.c     |  45 +-
 board/freescale/mpc8610hpcd/mpc8610hpcd_diu.c | 105 +++
 include/configs/MPC8610HPCD.h                 |  19 +-
 7 files changed, 858 insertions(+), 10 deletions(-)
 create mode 100644 board/freescale/common/fsl_diu_fb.c
 create mode 100644 board/freescale/common/fsl_diu_fb.h
 create mode 100644 board/freescale/mpc8610hpcd/mpc8610hpcd_diu.c

diff --git a/board/freescale/common/Makefile b/board/freescale/common/Makefile
index 44f613e41..9cee9f19b 100644
--- a/board/freescale/common/Makefile
+++ b/board/freescale/common/Makefile
@@ -31,7 +31,9 @@ LIB	= $(obj)lib$(VENDOR).a
 
 COBJS	:= sys_eeprom.o	\
 	   pixis.o	\
-	   pq-mds-pib.o
+	   pq-mds-pib.o \
+	   fsl_logo_bmp.o \
+	   fsl_diu_fb.o
 
 SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS))
diff --git a/board/freescale/common/fsl_diu_fb.c b/board/freescale/common/fsl_diu_fb.c
new file mode 100644
index 000000000..a9999d393
--- /dev/null
+++ b/board/freescale/common/fsl_diu_fb.c
@@ -0,0 +1,656 @@
+/*
+ * Copyright 2007 Freescale Semiconductor, Inc.
+ * York Sun <yorksun@freescale.com>
+ *
+ * FSL DIU Framebuffer driver
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#include <common.h>
+#include <i2c.h>
+#include <malloc.h>
+
+#ifdef CONFIG_FSL_DIU_FB
+
+#include "fsl_diu_fb.h"
+
+
+#ifdef DEBUG
+#define DPRINTF(fmt, args...) printf("%s: " fmt,__FUNCTION__,## args)
+#else
+#define DPRINTF(fmt, args...)
+#endif
+
+struct fb_var_screeninfo {
+	unsigned int xres;		/* visible resolution		*/
+	unsigned int yres;
+
+	unsigned int bits_per_pixel;	/* guess what			*/
+
+	/* Timing: All values in pixclocks, except pixclock (of course) */
+	unsigned int pixclock;		/* pixel clock in ps (pico seconds) */
+	unsigned int left_margin;	/* time from sync to picture	*/
+	unsigned int right_margin;	/* time from picture to sync	*/
+	unsigned int upper_margin;	/* time from sync to picture	*/
+	unsigned int lower_margin;
+	unsigned int hsync_len;		/* length of horizontal sync	*/
+	unsigned int vsync_len;		/* length of vertical sync	*/
+	unsigned int sync;		/* see FB_SYNC_*		*/
+	unsigned int vmode;		/* see FB_VMODE_*		*/
+	unsigned int rotate;		/* angle we rotate counter clockwise */
+};
+
+struct fb_info {
+	struct fb_var_screeninfo var;	/* Current var */
+	unsigned long smem_start;	/* Start of frame buffer mem */
+					/* (physical address) */
+	unsigned int smem_len;		/* Length of frame buffer mem */
+	unsigned int type;		/* see FB_TYPE_*		*/
+	unsigned int line_length;	/* length of a line in bytes    */
+
+	char *screen_base;
+	unsigned long screen_size;
+	int logo_height;
+	unsigned int logo_size;
+};
+
+struct fb_videomode {
+	const char *name;	/* optional */
+	unsigned int refresh;		/* optional */
+	unsigned int xres;
+	unsigned int yres;
+	unsigned int pixclock;
+	unsigned int left_margin;
+	unsigned int right_margin;
+	unsigned int upper_margin;
+	unsigned int lower_margin;
+	unsigned int hsync_len;
+	unsigned int vsync_len;
+	unsigned int sync;
+	unsigned int vmode;
+	unsigned int flag;
+};
+
+#define FB_SYNC_VERT_HIGH_ACT	2	/* vertical sync high active	*/
+#define FB_SYNC_COMP_HIGH_ACT	8	/* composite sync high active   */
+#define FB_VMODE_NONINTERLACED  0	/* non interlaced */
+
+/*
+ * These parameters give default parameters
+ * for video output 1024x768,
+ * FIXME - change timing to proper amounts
+ * hsync 31.5kHz, vsync 60Hz
+ */
+static struct fb_videomode fsl_diu_mode_1024 = {
+	.refresh	= 60,
+	.xres		= 1024,
+	.yres		= 768,
+	.pixclock	= 15385,
+	.left_margin	= 160,
+	.right_margin	= 24,
+	.upper_margin	= 29,
+	.lower_margin	= 3,
+	.hsync_len	= 136,
+	.vsync_len	= 6,
+	.sync		= FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
+	.vmode		= FB_VMODE_NONINTERLACED
+};
+
+static struct fb_videomode fsl_diu_mode_1280 = {
+	.name		= "1280x1024-60",
+	.refresh	= 60,
+	.xres		= 1280,
+	.yres		= 1024,
+	.pixclock	= 9375,
+	.left_margin	= 38,
+	.right_margin	= 128,
+	.upper_margin	= 2,
+	.lower_margin	= 7,
+	.hsync_len	= 216,
+	.vsync_len	= 37,
+	.sync		= FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
+	.vmode		= FB_VMODE_NONINTERLACED
+};
+
+/*
+ * These are the fields of area descriptor(in DDR memory) for every plane
+ */
+struct diu_ad {
+	/* Word 0(32-bit) in DDR memory */
+	unsigned int pix_fmt; /* hard coding pixel format */
+	/* Word 1(32-bit) in DDR memory */
+	unsigned int addr;
+	/* Word 2(32-bit) in DDR memory */
+	unsigned int src_size_g_alpha;
+	/* Word 3(32-bit) in DDR memory */
+	unsigned int aoi_size;
+	/* Word 4(32-bit) in DDR memory */
+	unsigned int offset_xyi;
+	/* Word 5(32-bit) in DDR memory */
+	unsigned int offset_xyd;
+	/* Word 6(32-bit) in DDR memory */
+	unsigned int ckmax_r:8;
+	unsigned int ckmax_g:8;
+	unsigned int ckmax_b:8;
+	unsigned int res9:8;
+	/* Word 7(32-bit) in DDR memory */
+	unsigned int ckmin_r:8;
+	unsigned int ckmin_g:8;
+	unsigned int ckmin_b:8;
+	unsigned int res10:8;
+	/* Word 8(32-bit) in DDR memory */
+	unsigned int next_ad;
+	/* Word 9(32-bit) in DDR memory, just for 64-bit aligned */
+	unsigned int res1;
+	unsigned int res2;
+	unsigned int res3;
+}__attribute__ ((packed));
+
+/*
+ * DIU register map
+ */
+struct diu {
+	unsigned int desc[3];
+	unsigned int gamma;
+	unsigned int pallete;
+	unsigned int cursor;
+	unsigned int curs_pos;
+	unsigned int diu_mode;
+	unsigned int bgnd;
+	unsigned int bgnd_wb;
+	unsigned int disp_size;
+	unsigned int wb_size;
+	unsigned int wb_mem_addr;
+	unsigned int hsyn_para;
+	unsigned int vsyn_para;
+	unsigned int syn_pol;
+	unsigned int thresholds;
+	unsigned int int_status;
+	unsigned int int_mask;
+	unsigned int colorbar[8];
+	unsigned int filling;
+	unsigned int plut;
+} __attribute__ ((packed));
+
+struct diu_hw {
+	struct diu *diu_reg;
+	volatile unsigned int mode;		/* DIU operation mode */
+};
+
+struct diu_addr {
+	unsigned char  *  paddr;	/* Virtual address */
+	unsigned int 	   offset;
+};
+
+#define FSL_DIU_BASE_OFFSET	0x2C000	/* Offset of Display Interface Unit */
+
+/*
+ * Modes of operation of DIU
+ */
+#define MFB_MODE0	0	/* DIU off */
+#define MFB_MODE1	1	/* All three planes output to display */
+#define MFB_MODE2	2	/* Plane 1 to display,
+				 * planes 2+3 written back to memory */
+#define MFB_MODE3	3	/* All three planes written back to memory */
+#define MFB_MODE4	4	/* Color bar generation */
+
+#define MAX_CURS		32
+
+
+
+static struct fb_info fsl_fb_info;
+static struct diu_addr gamma, cursor;
+static struct diu_ad fsl_diu_fb_ad __attribute__ ((aligned(32)));
+static struct diu_ad dummy_ad __attribute__ ((aligned(32)));
+static unsigned char *dummy_fb;
+static struct diu_hw dr = {
+	.mode = MFB_MODE1,
+};
+
+int fb_enabled = 0;
+int fb_initialized = 0;
+const int default_xres = 1280;
+const int default_pixel_format = 0x88882317;
+
+static int map_video_memory(struct fb_info *info, unsigned long bytes_align);
+static void enable_lcdc(void);
+static void disable_lcdc(void);
+static int fsl_diu_enable_panel(struct fb_info *info);
+static int fsl_diu_disable_panel(struct fb_info *info);
+static int allocate_buf(struct diu_addr *buf, u32 size, u32 bytes_align);
+static u32 get_busfreq(void);
+
+
+int fsl_diu_init(int xres,
+		 unsigned int pixel_format,
+		 int gamma_fix,
+		 unsigned char *splash_bmp)
+{
+	struct fb_videomode *fsl_diu_mode_db;
+	struct diu_ad *ad = &fsl_diu_fb_ad;
+	struct diu *hw;
+	struct fb_info *info = &fsl_fb_info;
+	struct fb_var_screeninfo *var = &info->var;
+	volatile immap_t *immap = (immap_t *)CFG_IMMR;
+	volatile ccsr_gur_t *gur = &immap->im_gur;
+	volatile unsigned int *guts_clkdvdr = &gur->clkdvdr;
+	unsigned char *gamma_table_base;
+	unsigned int i, j;
+	unsigned long speed_ccb, temp, pixval;
+
+	DPRINTF("Enter fsl_diu_init\n");
+	dr.diu_reg = (struct diu *) (CFG_IMMR + FSL_DIU_BASE_OFFSET);
+	hw = (struct diu *) dr.diu_reg;
+
+	disable_lcdc();
+
+	if (xres == 1280) {
+		fsl_diu_mode_db = &fsl_diu_mode_1280;
+	} else {
+		fsl_diu_mode_db = &fsl_diu_mode_1024;
+	}
+
+	if (0 == fb_initialized) {
+		allocate_buf(&gamma, 768, 32);
+		DPRINTF("gamma is allocated @ 0x%x\n",
+			(unsigned int)gamma.paddr);
+		allocate_buf(&cursor, MAX_CURS * MAX_CURS * 2, 32);
+		DPRINTF("curosr is allocated @ 0x%x\n",
+			(unsigned int)cursor.paddr);
+
+		/* create a dummy fb and dummy ad */
+		dummy_fb = malloc(64);
+		if (NULL == dummy_fb) {
+			printf("Cannot allocate dummy fb\n");
+			return -1;
+		}
+		dummy_ad.addr = cpu_to_le32((unsigned int)dummy_fb);
+		dummy_ad.pix_fmt = 0x88882317;
+		dummy_ad.src_size_g_alpha = 0x04400000;	/* alpha = 0 */
+		dummy_ad.aoi_size = 0x02000400;
+		dummy_ad.offset_xyi = 0;
+		dummy_ad.offset_xyd = 0;
+		dummy_ad.next_ad = 0;
+		/* Memory allocation for framebuffer */
+		if (map_video_memory(info, 32)) {
+			printf("Unable to allocate fb memory 1\n");
+			return -1;
+		}
+	} else {
+		memset(info->screen_base, 0, info->smem_len);
+	}
+
+	dr.diu_reg->desc[0] = (unsigned int) &dummy_ad;
+	dr.diu_reg->desc[1] = (unsigned int) &dummy_ad;
+	dr.diu_reg->desc[2] = (unsigned int) &dummy_ad;
+	DPRINTF("dummy dr.diu_reg->desc[0] = 0x%x\n", dr.diu_reg->desc[0]);
+	DPRINTF("dummy desc[0] = 0x%x\n", hw->desc[0]);
+
+	/* read mode info */
+	var->xres = fsl_diu_mode_db->xres;
+	var->yres = fsl_diu_mode_db->yres;
+	var->bits_per_pixel = 32;
+	var->pixclock = fsl_diu_mode_db->pixclock;
+	var->left_margin = fsl_diu_mode_db->left_margin;
+	var->right_margin = fsl_diu_mode_db->right_margin;
+	var->upper_margin = fsl_diu_mode_db->upper_margin;
+	var->lower_margin = fsl_diu_mode_db->lower_margin;
+	var->hsync_len = fsl_diu_mode_db->hsync_len;
+	var->vsync_len = fsl_diu_mode_db->vsync_len;
+	var->sync = fsl_diu_mode_db->sync;
+	var->vmode = fsl_diu_mode_db->vmode;
+	info->line_length = var->xres * var->bits_per_pixel / 8;
+	info->logo_size = 0;
+	info->logo_height = 0;
+
+	ad->pix_fmt = pixel_format;
+	ad->addr    = cpu_to_le32((unsigned int)info->screen_base);
+	ad->src_size_g_alpha
+			= cpu_to_le32((var->yres << 12) | var->xres);
+	/* fix me. AOI should not be greater than display size */
+	ad->aoi_size 	= cpu_to_le32(( var->yres << 16) |  var->xres);
+	ad->offset_xyi = 0;
+	ad->offset_xyd = 0;
+
+	/* Disable chroma keying function */
+	ad->ckmax_r = 0;
+	ad->ckmax_g = 0;
+	ad->ckmax_b = 0;
+
+	ad->ckmin_r = 255;
+	ad->ckmin_g = 255;
+	ad->ckmin_b = 255;
+
+	gamma_table_base = gamma.paddr;
+	DPRINTF("gamma_table_base is allocated @ 0x%x\n",
+		(unsigned int)gamma_table_base);
+
+	/* Prep for DIU init  - gamma table */
+
+	for (i = 0; i <= 2; i++)
+		for (j = 0; j <= 255; j++)
+			*gamma_table_base++ = j;
+
+	if (gamma_fix == 1) {	/* fix the gamma */
+		DPRINTF("Fix gamma table\n");
+		gamma_table_base = gamma.paddr;
+		for (i = 0; i < 256*3; i++) {
+			gamma_table_base[i] = (gamma_table_base[i] << 2)
+				| ((gamma_table_base[i] >> 6) & 0x03);
+		}
+	}
+
+	DPRINTF("update-lcdc: HW - %p\n Disabling DIU\n", hw);
+
+	/* Program DIU registers */
+
+	hw->gamma = (unsigned int) gamma.paddr;
+	hw->cursor= (unsigned int) cursor.paddr;
+	hw->bgnd = 0x007F7F7F;				/* BGND */
+	hw->bgnd_wb = 0; 				/* BGND_WB */
+	hw->disp_size = var->yres << 16 | var->xres;	/* DISP SIZE */
+	hw->wb_size = 0;				/* WB SIZE */
+	hw->wb_mem_addr = 0;				/* WB MEM ADDR */
+	hw->hsyn_para = var->left_margin << 22 |	/* BP_H */
+			var->hsync_len << 11   |	/* PW_H */
+			var->right_margin;		/* FP_H */
+	hw->vsyn_para = var->upper_margin << 22 |	/* BP_V */
+			var->vsync_len << 11    |	/* PW_V  */
+			var->lower_margin;		/* FP_V  */
+
+	/* Pixel Clock configuration */
+	DPRINTF("DIU: Bus Frequency = %d\n", get_busfreq());
+	speed_ccb = get_busfreq();
+
+	DPRINTF("DIU pixclock in ps - %d\n", var->pixclock);
+	temp = 1;
+	temp *= 1000000000;
+	temp /= var->pixclock;
+	temp *= 1000;
+	pixval = speed_ccb / temp;
+	DPRINTF("DIU pixval = %lu\n", pixval);
+
+	hw->syn_pol = 0;			/* SYNC SIGNALS POLARITY */
+	hw->thresholds = 0x00037800;		/* The Thresholds */
+	hw->int_status = 0;			/* INTERRUPT STATUS */
+	hw->int_mask = 0;			/* INT MASK */
+	hw->plut = 0x01F5F666;
+
+	/* Modify PXCLK in GUTS CLKDVDR */
+	DPRINTF("DIU: Current value of CLKDVDR = 0x%08x\n", *guts_clkdvdr);
+	temp = *guts_clkdvdr & 0x2000FFFF;
+	*guts_clkdvdr = temp;				/* turn off clock */
+	*guts_clkdvdr = temp | 0x80000000 | ((pixval & 0x1F) << 16);
+	DPRINTF("DIU: Modified value of CLKDVDR = 0x%08x\n", *guts_clkdvdr);
+
+	fb_initialized = 1;
+
+	if (splash_bmp) {
+		info->logo_height = fsl_diu_display_bmp(splash_bmp, 0, 0, 0);
+		info->logo_size = info->logo_height * info->line_length;
+		DPRINTF("logo height %d, logo_size 0x%x\n",
+			info->logo_height,info->logo_size);
+	}
+
+	/* Enable the DIU */
+	fsl_diu_enable_panel(info);
+	enable_lcdc();
+
+	return 0;
+}
+
+char *fsl_fb_open(struct fb_info **info)
+{
+	*info = &fsl_fb_info;
+	return (char *) ((unsigned int)(*info)->screen_base
+			 + (*info)->logo_size);
+}
+
+void fsl_diu_close(void)
+{
+	struct fb_info *info = &fsl_fb_info;
+	fsl_diu_disable_panel(info);
+}
+
+static int fsl_diu_enable_panel(struct fb_info *info)
+{
+	struct diu *hw = dr.diu_reg;
+	struct diu_ad *ad = &fsl_diu_fb_ad;
+
+	DPRINTF("Entered: enable_panel\n");
+	if (hw->desc[0] != (unsigned int)ad)
+		hw->desc[0] = (unsigned int)ad;
+	DPRINTF("desc[0] = 0x%x\n", hw->desc[0]);
+	return 0;
+}
+
+static int fsl_diu_disable_panel(struct fb_info *info)
+{
+	struct diu *hw = dr.diu_reg;
+
+	DPRINTF("Entered: disable_panel\n");
+	if (hw->desc[0] != (unsigned int)&dummy_ad)
+		hw->desc[0] = (unsigned int)&dummy_ad;
+	return 0;
+}
+
+static int map_video_memory(struct fb_info *info, unsigned long bytes_align)
+{
+	unsigned long offset;
+	unsigned long mask;
+
+	DPRINTF("Entered: map_video_memory\n");
+	/* allocate maximum 1280*1024 with 32bpp */
+	info->smem_len = 1280 * 4 *1024 + bytes_align;
+	DPRINTF("MAP_VIDEO_MEMORY: smem_len = %d\n", info->smem_len);
+	info->screen_base = malloc(info->smem_len);
+	if (info->screen_base == NULL) {
+		printf("Unable to allocate fb memory\n");
+		return -1;
+	}
+	info->smem_start = (unsigned int) info->screen_base;
+	mask = bytes_align - 1;
+	offset = (unsigned long)info->screen_base & mask;
+	if (offset) {
+		info->screen_base += offset;
+		info->smem_len = info->smem_len - (bytes_align - offset);
+	} else
+		info->smem_len = info->smem_len - bytes_align;
+
+	info->screen_size = info->smem_len;
+
+	DPRINTF("Allocated fb @ 0x%08lx, size=%d.\n",
+		info->smem_start, info->smem_len);
+
+	return 0;
+}
+
+static void enable_lcdc(void)
+{
+	struct diu *hw = dr.diu_reg;
+
+	DPRINTF("Entered: enable_lcdc, fb_enabled = %d\n", fb_enabled);
+	if (!fb_enabled) {
+		hw->diu_mode = dr.mode;
+		fb_enabled++;
+	}
+	DPRINTF("diu_mode = %d\n", hw->diu_mode);
+}
+
+static void disable_lcdc(void)
+{
+	struct diu *hw = dr.diu_reg;
+
+	DPRINTF("Entered: disable_lcdc, fb_enabled = %d\n", fb_enabled);
+	if (fb_enabled) {
+		hw->diu_mode = 0;
+		fb_enabled = 0;
+	}
+}
+
+static u32 get_busfreq(void)
+{
+	u32 fs_busfreq = 0;
+
+	fs_busfreq = get_bus_freq(0);
+	return fs_busfreq;
+}
+
+/*
+ * Align to 64-bit(8-byte), 32-byte, etc.
+ */
+static int allocate_buf(struct diu_addr *buf, u32 size, u32 bytes_align)
+{
+	u32 offset, ssize;
+	u32 mask;
+
+	DPRINTF("Entered: allocate_buf\n");
+	ssize = size + bytes_align;
+	buf->paddr = malloc(ssize);
+	if (!buf->paddr)
+		return -1;
+
+	memset(buf->paddr, 0, ssize);
+	mask = bytes_align - 1;
+	offset = (u32)buf->paddr & mask;
+	if (offset) {
+		buf->offset = bytes_align - offset;
+		buf->paddr = (unsigned char *) ((u32)buf->paddr + offset);
+	} else
+		buf->offset = 0;
+	return 0;
+}
+
+int fsl_diu_display_bmp(unsigned char *bmp,
+			int xoffset,
+			int yoffset,
+			int transpar)
+{
+	struct fb_info *info = &fsl_fb_info;
+	unsigned char r, g, b;
+	unsigned int *fb_t, val;
+	unsigned char *bitmap;
+	unsigned int palette[256];
+	int width, height, bpp, ncolors, raster, offset, x, y, i, k, cpp;
+
+	if (!bmp) {
+		printf("Must supply a bitmap address\n");
+		return 0;
+	}
+
+	raster = bmp[10] + (bmp[11] << 8) + (bmp[12] << 16) + (bmp[13] << 24);
+	width  = (bmp[21] << 24) | (bmp[20] << 16) | (bmp[19] << 8) | bmp[18];
+	height = (bmp[25] << 24) | (bmp[24] << 16) | (bmp[23] << 8) | bmp[22];
+	bpp  = (bmp[29] <<  8) | (bmp[28]);
+	ncolors = bmp[46] + (bmp[47] << 8) + (bmp[48] << 16) + (bmp[49] << 24);
+	bitmap   = bmp + raster;
+	cpp = info->var.bits_per_pixel / 8;
+
+	DPRINTF("bmp = 0x%08x\n", (unsigned int)bmp);
+	DPRINTF("bitmap = 0x%08x\n", (unsigned int)bitmap);
+	DPRINTF("width = %d\n", width);
+	DPRINTF("height = %d\n", height);
+	DPRINTF("bpp = %d\n", bpp);
+	DPRINTF("ncolors = %d\n", ncolors);
+
+	DPRINTF("xres = %d\n", info->var.xres);
+	DPRINTF("yres = %d\n", info->var.yres);
+	DPRINTF("Screen_base = 0x%x\n", (unsigned int)info->screen_base);
+
+	if (((width+xoffset) > info->var.xres) ||
+	    ((height+yoffset) > info->var.yres)) {
+		printf("bitmap is out of range, image too large or too much offset\n");
+		return 0;
+	}
+	if (bpp < 24) {
+		for (i = 0, offset = 54; i < ncolors; i++, offset += 4)
+			palette[i] = (bmp[offset+2] << 16)
+				+ (bmp[offset+1] << 8) + bmp[offset];
+	}
+
+	switch (bpp) {
+	case 1:
+		for (y = height - 1; y >= 0; y--) {
+			fb_t = (unsigned int *) ((unsigned int)info->screen_base + (((y+yoffset) * info->var.xres) + xoffset)*cpp);
+			for (x = 0; x < width; x += 8) {
+				b = *bitmap++;
+				for (k = 0; k < 8; k++) {
+					if (b & 0x80)
+						*fb_t = palette[1];
+					else
+						*fb_t = palette[0];
+					b = b << 1;
+				}
+			}
+			for (i = (width / 2) % 4; i > 0; i--)
+				bitmap++;
+		}
+		break;
+	case 4:
+		for (y = height - 1; y >= 0; y--) {
+			fb_t = (unsigned int *) ((unsigned int)info->screen_base + (((y+yoffset) * info->var.xres) + xoffset)*cpp);
+			for (x = 0; x < width; x += 2) {
+				b = *bitmap++;
+				r = (b >> 4) & 0x0F;
+				g =  b & 0x0F;
+				*fb_t++ = palette[r];
+				*fb_t++ = palette[g];
+			}
+			for (i = (width / 2) % 4; i > 0; i--)
+				bitmap++;
+		}
+		break;
+	case 8:
+		for (y = height - 1; y >= 0; y--) {
+			fb_t = (unsigned int *) ((unsigned int)info->screen_base + (((y+yoffset) * info->var.xres) + xoffset)*cpp);
+			for (x = 0; x < width; x++) {
+				*fb_t++ = palette[ *bitmap++ ];
+			}
+			for (i = (width / 2) % 4; i > 0; i--)
+				bitmap++;
+		}
+		break;
+	case 24:
+		for (y = height - 1; y >= 0; y--) {
+			fb_t = (unsigned int *) ((unsigned int)info->screen_base + (((y+yoffset) * info->var.xres) + xoffset)*cpp);
+			for (x = 0; x < width; x++) {
+				b = *bitmap++;
+				g = *bitmap++;
+				r = *bitmap++;
+				val = (r << 16) + (g << 8) + b;
+				*fb_t++ = val;
+			}
+			for (; (x % 4) != 0; x++)	/* 4-byte alignment */
+				bitmap++;
+		}
+		break;
+	}
+
+	return height;
+}
+
+void fsl_diu_clear_screen(void)
+{
+	struct fb_info *info = &fsl_fb_info;
+
+	memset(info->screen_base, 0, info->smem_len);
+}
+#endif /* CONFIG_FSL_DIU_FB */
diff --git a/board/freescale/common/fsl_diu_fb.h b/board/freescale/common/fsl_diu_fb.h
new file mode 100644
index 000000000..9ddd4c0a5
--- /dev/null
+++ b/board/freescale/common/fsl_diu_fb.h
@@ -0,0 +1,35 @@
+/*
+ * Copyright 2007 Freescale Semiconductor, Inc.
+ * York Sun <yorksun@freescale.com>
+ *
+ * FSL DIU Framebuffer driver
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+extern int fsl_diu_init(int xres,
+			unsigned int pixel_format,
+			int gamma_fix,
+			unsigned char *splash_bmp);
+extern void fsl_diu_clear_screen(void);
+extern int fsl_diu_display_bmp(unsigned char *bmp,
+			       int xoffset,
+			       int yoffset,
+			       int transpar);
diff --git a/board/freescale/mpc8610hpcd/Makefile b/board/freescale/mpc8610hpcd/Makefile
index 6f5a5c16e..76087c12a 100644
--- a/board/freescale/mpc8610hpcd/Makefile
+++ b/board/freescale/mpc8610hpcd/Makefile
@@ -29,7 +29,9 @@ LIB	= $(obj)lib$(BOARD).a
 
 COBJS	:= $(BOARD).o \
 	../common/sys_eeprom.o \
-	../common/pixis.o
+	../common/pixis.o \
+	mpc8610hpcd_diu.o \
+	../common/fsl_diu_fb.o
 
 SOBJS	:= init.o
 
diff --git a/board/freescale/mpc8610hpcd/mpc8610hpcd.c b/board/freescale/mpc8610hpcd/mpc8610hpcd.c
index 63790ca9b..617881ad0 100644
--- a/board/freescale/mpc8610hpcd/mpc8610hpcd.c
+++ b/board/freescale/mpc8610hpcd/mpc8610hpcd.c
@@ -54,7 +54,47 @@ int board_early_init_f(void)
 	volatile immap_t *immap = (immap_t *)CFG_IMMR;
 	volatile ccsr_gur_t *gur = &immap->im_gur;
 
-	gur->gpiocr |= 0x888a5500; /* DIU16, IR1, UART0, UART2 */
+	gur->gpiocr |= 0x88aa5500; /* DIU16, IR1, UART0, UART2 */
+
+	return 0;
+}
+
+int misc_init_r(void)
+{
+	u8 tmp_val, version;
+
+	/*Do not use 8259PIC*/
+	tmp_val = in8(PIXIS_BASE + PIXIS_BRDCFG0);
+	out8(PIXIS_BASE + PIXIS_BRDCFG0, tmp_val | 0x80);
+
+	/*For FPGA V7 or higher, set the IRQMAPSEL to 0 to use MAP0 interrupt*/
+	version = in8(PIXIS_BASE + PIXIS_PVER);
+	if(version >= 0x07) {
+		tmp_val = in8(PIXIS_BASE + PIXIS_BRDCFG0);
+		out8(PIXIS_BASE + PIXIS_BRDCFG0, tmp_val & 0xbf);
+	}
+
+	/* Using this for DIU init before the driver in linux takes over
+	 *  Enable the TFP410 Encoder (I2C address 0x38)
+	 */
+
+	tmp_val = 0xBF;
+	i2c_write(0x38, 0x08, 1, &tmp_val, sizeof(tmp_val));
+	/* Verify if enabled */
+	tmp_val = 0;
+	i2c_read(0x38, 0x08, 1, &tmp_val, sizeof(tmp_val));
+	debug("DVI Encoder Read: 0x%02lx\n",tmp_val);
+
+	tmp_val = 0x10;
+	i2c_write(0x38, 0x0A, 1, &tmp_val, sizeof(tmp_val));
+	/* Verify if enabled */
+	tmp_val = 0;
+	i2c_read(0x38, 0x0A, 1, &tmp_val, sizeof(tmp_val));
+	debug("DVI Encoder Read: 0x%02lx\n",tmp_val);
+
+#ifdef CONFIG_FSL_DIU_FB
+	mpc8610hpcd_diu_init();
+#endif
 
 	return 0;
 }
@@ -62,7 +102,6 @@ int board_early_init_f(void)
 int checkboard(void)
 {
 	volatile immap_t *immap = (immap_t *)CFG_IMMR;
-	volatile ccsr_lbc_t *memctl = &immap->im_lbc;
 	volatile ccsr_local_mcm_t *mcm = &immap->im_local_mcm;
 
 	puts("Board: MPC8610HPCD\n");
@@ -468,7 +507,7 @@ ft_board_setup(void *blob, bd_t *bd)
 unsigned long
 get_board_sys_clk(ulong dummy)
 {
-	u8 i, go_bit, rd_clks;
+	u8 i;
 	ulong val = 0;
 	ulong a;
 
diff --git a/board/freescale/mpc8610hpcd/mpc8610hpcd_diu.c b/board/freescale/mpc8610hpcd/mpc8610hpcd_diu.c
new file mode 100644
index 000000000..444937678
--- /dev/null
+++ b/board/freescale/mpc8610hpcd/mpc8610hpcd_diu.c
@@ -0,0 +1,105 @@
+/*
+ * Copyright 2007 Freescale Semiconductor, Inc.
+ * York Sun <yorksun@freescale.com>
+ *
+ * FSL DIU Framebuffer driver
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/io.h>
+
+#ifdef CONFIG_FSL_DIU_FB
+
+#include "../common/pixis.h"
+#include "../common/fsl_diu_fb.h"
+
+
+extern unsigned int FSL_Logo_BMP[];
+
+
+void mpc8610hpcd_diu_init(void)
+{
+	char *monitor_port;
+	int xres, gamma_fix;
+	unsigned int pixel_format;
+	unsigned char tmp_val;
+
+	tmp_val = in8(PIXIS_BASE + PIXIS_BRDCFG0);
+	monitor_port = getenv ("monitor");
+
+	if (!strncmp(monitor_port, "0", 1)) {	/* 0 - DVI */
+		xres = 1280;
+		pixel_format = 0x88882317;
+		gamma_fix = 0;
+		out8(PIXIS_BASE + PIXIS_BRDCFG0, tmp_val | 0x08);
+
+	} else if (!strncmp(monitor_port, "1", 1)) { /* 1 - Single link LVDS */
+		xres = 1024;
+		pixel_format = 0x88883316;
+		gamma_fix = 0;
+		out8(PIXIS_BASE + PIXIS_BRDCFG0, (tmp_val & 0xf7) | 0x10);
+
+	} else if (!strncmp(monitor_port, "2", 1)) { /* 2 - Double link LVDS */
+		xres = 1280;
+		pixel_format = 0x88883316;
+		gamma_fix = 1;
+		out8(PIXIS_BASE + PIXIS_BRDCFG0, tmp_val & 0xe7);
+
+	} else {	/* DVI */
+		xres = 1280;
+		pixel_format = 0x88882317;
+		gamma_fix = 0;
+		out8(PIXIS_BASE + PIXIS_BRDCFG0, tmp_val | 0x08);
+	}
+
+	fsl_diu_init(xres, pixel_format, gamma_fix,
+		     (unsigned char *)FSL_Logo_BMP);
+}
+
+int mpc8610diu_init_show_bmp(cmd_tbl_t *cmdtp,
+			     int flag, int argc, char *argv[])
+{
+	unsigned int addr;
+
+	if (argc < 2) {
+		printf ("Usage:\n%s\n", cmdtp->usage);
+		return 1;
+	}
+
+	if (!strncmp(argv[1],"init",4)) {
+		mpc8610hpcd_diu_init();
+	} else {
+		addr = simple_strtoul(argv[1], NULL, 16);
+		fsl_diu_clear_screen();
+		fsl_diu_display_bmp((unsigned char *)addr, 0, 0, 0);
+	}
+
+	return 0;
+}
+
+U_BOOT_CMD(
+	diufb, CFG_MAXARGS, 1, mpc8610diu_init_show_bmp,
+	"diufb init | addr - Init or Display BMP file\n",
+	"init\n    - initialize DIU\n"
+	"addr\n    - display bmp at address 'addr'\n"
+	);
+#endif /* CONFIG_FSL_DIU_FB */
diff --git a/include/configs/MPC8610HPCD.h b/include/configs/MPC8610HPCD.h
index 9fa42f32d..00c94ef47 100644
--- a/include/configs/MPC8610HPCD.h
+++ b/include/configs/MPC8610HPCD.h
@@ -21,6 +21,7 @@
 #define CONFIG_NUM_CPUS		1	/* Number of CPUs in the system */
 #define CONFIG_LINUX_RESET_VEC	0x100	/* Reset vector used by Linux */
 
+#define CONFIG_FSL_DIU_FB	1	/* FSL DIU */
 #ifdef RUN_DIAG
 #define CFG_DIAG_ADDR		0xff800000
 #endif
@@ -38,7 +39,7 @@
 #define CONFIG_SPD_EEPROM		/* Use SPD for DDR */
 #undef CONFIG_DDR_DLL			/* possible DLL fix needed */
 #define CONFIG_DDR_2T_TIMING		/* Sets the 2T timing bit */
-#define CONFIG_DDR_ECC			/* only for ECC DDR module */
+#undef  CONFIG_DDR_ECC			/* only for ECC DDR module */
 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER	/* DDR controller or DMA? */
 #define CONFIG_MEM_INIT_VALUE		0xDeadBeef
 #define CONFIG_NUM_DDR_CONTROLLERS	1
@@ -51,13 +52,14 @@
  */
 #define CFG_L2
 #define L2_INIT		0
-#define L2_ENABLE	(L2CR_L2E)
+#define L2_ENABLE	(L2CR_L2E |0x00100000 )
 
 #ifndef CONFIG_SYS_CLK_FREQ
 #define CONFIG_SYS_CLK_FREQ	get_board_sys_clk(0)
 #endif
 
 #define CONFIG_BOARD_EARLY_INIT_F	1	/* Call board_pre_init */
+#define CONFIG_MISC_INIT_R		1
 
 #undef	CFG_DRAM_TEST			/* memory test, takes time */
 #define CFG_MEMTEST_START	0x00200000	/* memtest region */
@@ -159,6 +161,7 @@
 #define PIXIS_RST		0x4	/* PIXIS Reset Control register */
 #define PIXIS_AUX		0x6	/* PIXIS Auxiliary register; Scratch */
 #define PIXIS_SPD		0x7	/* Register for SYSCLK speed */
+#define PIXIS_BRDCFG0		0x8	/* PIXIS Board Configuration Register0*/
 #define PIXIS_VCTL		0x10	/* VELA Control Register */
 #define PIXIS_VCFGEN0		0x12	/* VELA Config Enable 0 */
 #define PIXIS_VCFGEN1		0x13	/* VELA Config Enable 1 */
@@ -208,7 +211,7 @@
 #define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
 
 #define CFG_MONITOR_LEN		(512 * 1024)	/* Reserve 512 KB for Mon */
-#define CFG_MALLOC_LEN		(128 * 1024)	/* Reserved for malloc */
+#define CFG_MALLOC_LEN		(6 * 1024 * 1024)	/* Reserved for malloc */
 
 /* Serial Port */
 #define CONFIG_CONS_INDEX	1
@@ -474,6 +477,9 @@
 
 #undef CONFIG_WATCHDOG			/* watchdog disabled */
 
+/*DIU Configuration*/
+#define DIU_CONNECT_TO_DVI		/* DIU controller connects to DVI encoder*/
+
 /*
  * Miscellaneous configurable options
  */
@@ -621,7 +627,8 @@
  "diuregs=md e002c000 1d\0" \
  "dium=mw e002c01c\0" \
  "diuerr=md e002c014 1\0" \
- "othbootargs=debug\0" \
+ "othbootargs=diufb=15M video=fslfb:1280x1024-32@60,monitor=0 debug\0" \
+ "monitor=0-DVI\0" \
  "pmregs=md e00e1000 2b\0" \
  "lawregs=md e0000c08 4b\0" \
  "lbcregs=md e0005000 36\0" \
@@ -641,7 +648,9 @@
  "ramdiskfile=8610hpcd/ramdisk.uboot\0"                         \
  "dtbaddr=c00000\0"                                             \
  "dtbfile=8610hpcd/mpc8610_hpcd.dtb\0"                          \
- "bdev=sda3\0"
+ "bdev=sda3\0"							\
+ "othbootargs=diufb=15M video=fslfb:1280x1024-32@60,monitor=0\0"\
+ "monitor=0-DVI\0"
 #endif
 
 #define CONFIG_NFSBOOTCOMMAND					\

From 070ba56115b4da63b46e974287fa4550d4023386 Mon Sep 17 00:00:00 2001
From: York Sun <yorksun@freescale.com>
Date: Wed, 31 Oct 2007 14:59:04 -0500
Subject: [PATCH 012/108] 8610: Add console frame buffer support to FSL 8610
 DIU driver.

Add cfb console support to FSL 8610 DIU driver.
Inspect board version from PIXIS to obtain correct pixel format.

Use #define CONFIG_VIDEO in config file to enable fb console.

To switch monitor, set monitor variable to
0 - DVI, 1 - Single link LVDS, 2 - Double link LVDS
followed by "diufb init".

Preserve logo bitmap at the top of the fb console.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Jon Loeliger <jdl@freescale.com>
---
 board/freescale/mpc8610hpcd/mpc8610hpcd_diu.c | 78 ++++++++++++++++++-
 include/configs/MPC8610HPCD.h                 | 20 ++++-
 2 files changed, 91 insertions(+), 7 deletions(-)

diff --git a/board/freescale/mpc8610hpcd/mpc8610hpcd_diu.c b/board/freescale/mpc8610hpcd/mpc8610hpcd_diu.c
index 444937678..b70637f94 100644
--- a/board/freescale/mpc8610hpcd/mpc8610hpcd_diu.c
+++ b/board/freescale/mpc8610hpcd/mpc8610hpcd_diu.c
@@ -32,40 +32,55 @@
 #include "../common/pixis.h"
 #include "../common/fsl_diu_fb.h"
 
+#if defined(CONFIG_VIDEO) || defined(CONFIG_CFB_CONSOLE)
+#include <devices.h>
+#include <video_fb.h>
+#endif
 
 extern unsigned int FSL_Logo_BMP[];
 
+static int xres, yres;
+
 
 void mpc8610hpcd_diu_init(void)
 {
 	char *monitor_port;
-	int xres, gamma_fix;
+	int gamma_fix;
 	unsigned int pixel_format;
 	unsigned char tmp_val;
+	unsigned char pixis_arch;
 
 	tmp_val = in8(PIXIS_BASE + PIXIS_BRDCFG0);
-	monitor_port = getenv ("monitor");
+	pixis_arch = in8(PIXIS_BASE + PIXIS_VER);
 
+	monitor_port = getenv("monitor");
 	if (!strncmp(monitor_port, "0", 1)) {	/* 0 - DVI */
 		xres = 1280;
-		pixel_format = 0x88882317;
+		yres = 1024;
+		if (pixis_arch == 0x01)
+			pixel_format = 0x88882317;
+		else
+			pixel_format = 0x88883316;
 		gamma_fix = 0;
 		out8(PIXIS_BASE + PIXIS_BRDCFG0, tmp_val | 0x08);
 
 	} else if (!strncmp(monitor_port, "1", 1)) { /* 1 - Single link LVDS */
 		xres = 1024;
+		yres = 768;
 		pixel_format = 0x88883316;
 		gamma_fix = 0;
 		out8(PIXIS_BASE + PIXIS_BRDCFG0, (tmp_val & 0xf7) | 0x10);
 
 	} else if (!strncmp(monitor_port, "2", 1)) { /* 2 - Double link LVDS */
 		xres = 1280;
+		yres = 1024;
 		pixel_format = 0x88883316;
 		gamma_fix = 1;
 		out8(PIXIS_BASE + PIXIS_BRDCFG0, tmp_val & 0xe7);
 
 	} else {	/* DVI */
 		xres = 1280;
+		yres = 1024;
 		pixel_format = 0x88882317;
 		gamma_fix = 0;
 		out8(PIXIS_BASE + PIXIS_BRDCFG0, tmp_val | 0x08);
@@ -86,7 +101,12 @@ int mpc8610diu_init_show_bmp(cmd_tbl_t *cmdtp,
 	}
 
 	if (!strncmp(argv[1],"init",4)) {
+#if defined(CONFIG_VIDEO) || defined(CONFIG_CFB_CONSOLE)
+		fsl_diu_clear_screen();
+		drv_video_init();
+#else
 		mpc8610hpcd_diu_init();
+#endif
 	} else {
 		addr = simple_strtoul(argv[1], NULL, 16);
 		fsl_diu_clear_screen();
@@ -102,4 +122,56 @@ U_BOOT_CMD(
 	"init\n    - initialize DIU\n"
 	"addr\n    - display bmp at address 'addr'\n"
 	);
+
+
+#if defined(CONFIG_VIDEO) || defined(CONFIG_CFB_CONSOLE)
+
+/*
+ * The Graphic Device
+ */
+GraphicDevice ctfb;
+void *video_hw_init(void)
+{
+	GraphicDevice *pGD = (GraphicDevice *) &ctfb;
+	struct fb_info *info;
+
+	mpc8610hpcd_diu_init();
+
+	/* fill in Graphic device struct */
+	sprintf(pGD->modeIdent,
+		"%dx%dx%d %ldkHz %ldHz",
+		xres, yres, 32, 64, 60);
+
+	pGD->frameAdrs = (unsigned int)fsl_fb_open(&info);
+	pGD->winSizeX = xres;
+	pGD->winSizeY = yres - info->logo_height;
+	pGD->plnSizeX = pGD->winSizeX;
+	pGD->plnSizeY = pGD->winSizeY;
+
+	pGD->gdfBytesPP = 4;
+	pGD->gdfIndex = GDF_32BIT_X888RGB;
+
+	pGD->isaBase = 0;
+	pGD->pciBase = 0;
+	pGD->memSize = info->screen_size - info->logo_size;
+
+	/* Cursor Start Address */
+	pGD->dprBase = 0;
+	pGD->vprBase = 0;
+	pGD->cprBase = 0;
+
+	return (void *)pGD;
+}
+
+void video_set_lut (unsigned int index,	/* color number */
+		    unsigned char r,	/* red */
+		    unsigned char g,	/* green */
+		    unsigned char b	/* blue */
+		    )
+{
+	return;
+}
+
+#endif /* defined(CONFIG_VIDEO) || defined(CONFIG_CFB_CONSOLE) */
+
 #endif /* CONFIG_FSL_DIU_FB */
diff --git a/include/configs/MPC8610HPCD.h b/include/configs/MPC8610HPCD.h
index 00c94ef47..f5d9c098c 100644
--- a/include/configs/MPC8610HPCD.h
+++ b/include/configs/MPC8610HPCD.h
@@ -22,6 +22,15 @@
 #define CONFIG_LINUX_RESET_VEC	0x100	/* Reset vector used by Linux */
 
 #define CONFIG_FSL_DIU_FB	1	/* FSL DIU */
+
+/* video */
+#undef CONFIG_VIDEO
+
+#if defined(CONFIG_VIDEO)
+#define CONFIG_CFB_CONSOLE
+#define CONFIG_VGA_AS_SINGLE_DEVICE
+#endif
+
 #ifdef RUN_DIAG
 #define CFG_DIAG_ADDR		0xff800000
 #endif
@@ -314,15 +323,17 @@
 #define CONFIG_EEPRO100
 #define CONFIG_TULIP
 
-#if 0 /* TODO */
 /************************************************************
  * USB support
  ************************************************************/
-#define CONFIG_USB_OHCI		1
+#define CONFIG_PCI_OHCI		1
+#define CONFIG_USB_OHCI_NEW		1
 #define CONFIG_USB_KEYBOARD	1
 #define CFG_DEVICE_DEREGISTER
-#define CFG_USB_INTERRUPT_POLL	1
-#endif
+#define CFG_USB_EVENT_POLL	1
+#define CFG_USB_OHCI_SLOT_NAME 	"ohci_pci"
+#define CFG_USB_OHCI_MAX_ROOT_PORTS 15
+#define CFG_OHCI_SWAP_REG_ACCESS	1
 
 #if !defined(CONFIG_PCI_PNP)
 #define PCI_ENET0_IOADDR	0xe0000000
@@ -472,6 +483,7 @@
 #define CONFIG_CMD_PCI
 #define CONFIG_CMD_SCSI
 #define CONFIG_CMD_EXT2
+#define CONFIG_CMD_USB
 #endif
 
 

From 5ca9881aad8c413ac2a82868a5e3719178254502 Mon Sep 17 00:00:00 2001
From: Peter Pearse <peter.pearse@arm.com>
Date: Fri, 9 Nov 2007 15:24:26 +0000
Subject: [PATCH 013/108] Add apollon board support Signed-off-by: Kyungmin
 Park <kyungmin.park@samsung.com>

---
 MAKEALL                                 |   1 +
 Makefile                                |   5 +-
 board/apollon/Makefile                  |  48 ++
 board/apollon/apollon.c                 | 608 ++++++++++++++++++++++++
 board/apollon/config.mk                 |  25 +
 board/apollon/lowlevel_init.S           | 337 +++++++++++++
 board/apollon/mem.c                     | 228 +++++++++
 board/apollon/mem.h                     | 170 +++++++
 board/apollon/sys_info.c                | 408 ++++++++++++++++
 board/apollon/u-boot.lds                |  64 +++
 include/asm-arm/arch-arm1136/mux.h      |   2 +
 include/asm-arm/arch-arm1136/omap2420.h |  33 +-
 include/asm-arm/mach-types.h            |  13 +
 include/configs/apollon.h               | 238 ++++++++++
 14 files changed, 2175 insertions(+), 5 deletions(-)
 create mode 100644 board/apollon/Makefile
 create mode 100644 board/apollon/apollon.c
 create mode 100644 board/apollon/config.mk
 create mode 100644 board/apollon/lowlevel_init.S
 create mode 100644 board/apollon/mem.c
 create mode 100644 board/apollon/mem.h
 create mode 100644 board/apollon/sys_info.c
 create mode 100644 board/apollon/u-boot.lds
 create mode 100644 include/configs/apollon.h

diff --git a/MAKEALL b/MAKEALL
index 20e81370f..52f3cd347 100755
--- a/MAKEALL
+++ b/MAKEALL
@@ -476,6 +476,7 @@ LIST_ARM10="		\
 LIST_ARM11="		\
 	cp1136		\
 	omap2420h4	\
+	apollon		\
 "
 
 #########################################################################
diff --git a/Makefile b/Makefile
index c0821d87a..e2a367eaf 100644
--- a/Makefile
+++ b/Makefile
@@ -2376,9 +2376,12 @@ zylonite_config :
 #########################################################################
 ## ARM1136 Systems
 #########################################################################
-omap2420h4_config :    unconfig
+omap2420h4_config	: unconfig
 	@$(MKCONFIG) $(@:_config=) arm arm1136 omap2420h4
 
+apollon_config		: unconfig
+	@$(MKCONFIG) $(@:_config=) arm arm1136 apollon
+
 #========================================================================
 # i386
 #========================================================================
diff --git a/board/apollon/Makefile b/board/apollon/Makefile
new file mode 100644
index 000000000..5348f2d30
--- /dev/null
+++ b/board/apollon/Makefile
@@ -0,0 +1,48 @@
+#
+# (C) Copyright 2000, 2001, 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).a
+
+COBJS	:= apollon.o mem.o sys_info.o
+SOBJS	:= lowlevel_init.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
diff --git a/board/apollon/apollon.c b/board/apollon/apollon.c
new file mode 100644
index 000000000..e2c627725
--- /dev/null
+++ b/board/apollon/apollon.c
@@ -0,0 +1,608 @@
+/*
+ * (C) Copyright 2005-2007
+ * Samsung Electronics.
+ * Kyungmin Park <kyungmin.park@samsung.com>
+ *
+ * Derived from omap2420
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <asm/arch/omap2420.h>
+#include <asm/io.h>
+#include <asm/arch/bits.h>
+#include <asm/arch/mux.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/sys_info.h>
+#include <asm/arch/mem.h>
+#include <i2c.h>
+#include <asm/mach-types.h>
+
+void wait_for_command_complete(unsigned int wd_base);
+
+/*******************************************************
+ * Routine: delay
+ * Description: spinning delay to use before udelay works
+******************************************************/
+static inline void delay(unsigned long loops) {
+	__asm__ volatile ("1:\n" "subs %0, %1, #1\n"
+			  "bne 1b":"=r" (loops):"0"(loops)); }
+
+/*****************************************
+ * Routine: board_init
+ * Description: Early hardware init.
+ *****************************************/
+int board_init(void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	gpmc_init();		/* in SRAM or SDRM, finish GPMC */
+
+	gd->bd->bi_arch_number = 919;
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = (OMAP2420_SDRC_CS0 + 0x100);
+
+	return 0;
+}
+
+/**********************************************************
+ * Routine: s_init
+ * Description: Does early system init of muxing and clocks.
+ * - Called path is with sram stack.
+ **********************************************************/
+void s_init(void)
+{
+
+	watchdog_init();
+	set_muxconf_regs();
+	delay(100);
+
+	peripheral_enable();
+	icache_enable();
+}
+
+/*******************************************************
+ * Routine: misc_init_r
+ * Description: Init ethernet (done here so udelay works)
+********************************************************/
+int misc_init_r(void)
+{
+	ether_init();		/* better done here so timers are init'ed */
+	return (0);
+}
+
+/****************************************
+ * Routine: watchdog_init
+ * Description: Shut down watch dogs
+ *****************************************/
+void watchdog_init(void)
+{
+	/* There are 4 watch dogs.  1 secure, and 3 general purpose.
+	 * The ROM takes care of the secure one. Of the 3 GP ones,
+	 * 1 can reset us directly, the other 2 only generate MPU interrupts.
+	 */
+	__raw_writel(WD_UNLOCK1, WD2_BASE + WSPR);
+	wait_for_command_complete(WD2_BASE);
+	__raw_writel(WD_UNLOCK2, WD2_BASE + WSPR);
+
+#define MPU_WD_CLOCKED 1
+#if MPU_WD_CLOCKED		/* value 0x10 stick on aptix, BIT4 polarity seems oppsite */
+	__raw_writel(WD_UNLOCK1, WD3_BASE + WSPR);
+	wait_for_command_complete(WD3_BASE);
+	__raw_writel(WD_UNLOCK2, WD3_BASE + WSPR);
+
+	__raw_writel(WD_UNLOCK1, WD4_BASE + WSPR);
+	wait_for_command_complete(WD4_BASE);
+	__raw_writel(WD_UNLOCK2, WD4_BASE + WSPR); 
+#endif 
+}
+
+/******************************************************
+ * Routine: wait_for_command_complete
+ * Description: Wait for posting to finish on watchdog
+******************************************************/
+void wait_for_command_complete(unsigned int wd_base) {
+	int pending = 1;
+	do {
+		pending = __raw_readl(wd_base + WWPS);
+	} while (pending);
+}
+
+/*******************************************************************
+ * Routine:ether_init
+ * Description: take the Ethernet controller out of reset and wait
+ *  		   for the EEPROM load to complete.
+ ******************************************************************/
+void ether_init(void)
+{
+#ifdef CONFIG_DRIVER_LAN91C96
+	int cnt = 20;
+
+	__raw_writeb(0x03, OMAP2420_CTRL_BASE + 0x0f2);	/*protect->gpio74 */
+
+	__raw_writew(0x0, LAN_RESET_REGISTER);
+	do {
+		__raw_writew(0x1, LAN_RESET_REGISTER);
+		udelay(100);
+		if (cnt == 0) {
+			printf("1. eth reset err\n");
+			goto eth_reset_err_out;
+		}
+		--cnt;
+	} while (__raw_readw(LAN_RESET_REGISTER) != 0x1);
+
+	cnt = 20;
+
+	do {
+		__raw_writew(0x0, LAN_RESET_REGISTER);
+		udelay(100);
+		if (cnt == 0) {
+			printf("2. eth reset err\n");
+			goto eth_reset_err_out;
+		}
+		--cnt;
+	} while (__raw_readw(LAN_RESET_REGISTER) != 0x0000);
+	udelay(1000);
+
+	*((volatile unsigned char *)ETH_CONTROL_REG) &= ~0x01;
+	udelay(1000);
+
+eth_reset_err_out:
+	return;
+#endif
+}
+
+/**********************************************
+ * Routine: dram_init
+ * Description: sets uboots idea of sdram size
+**********************************************/
+int dram_init(void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+	unsigned int size0 = 0, size1 = 0;
+	u32 mtype, btype, rev = 0, cpu = 0;
+#define NOT_EARLY 0
+
+	btype = get_board_type();
+	mtype = get_mem_type();
+	rev = get_cpu_rev();
+	cpu = get_cpu_type();
+
+	display_board_info(btype);
+
+	if ((mtype == DDR_COMBO) || (mtype == DDR_STACKED)) {
+		printf("ddr combo\n");
+		do_sdrc_init(SDRC_CS1_OSET, NOT_EARLY);	/* init other chip select */
+	}
+
+	size0 = get_sdr_cs_size(SDRC_CS0_OSET);
+	size1 = get_sdr_cs_size(SDRC_CS1_OSET);
+
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = size0;
+#if CONFIG_NR_DRAM_BANKS > 1
+	gd->bd->bi_dram[1].start = PHYS_SDRAM_1 + size0;
+	gd->bd->bi_dram[1].size = size1;
+#endif
+
+	return 0;
+}
+
+/**********************************************************
+ * Routine: set_muxconf_regs
+ * Description: Setting up the configuration Mux registers
+ *              specific to the hardware
+ *********************************************************/
+void set_muxconf_regs(void)
+{
+	muxSetupSDRC();
+	muxSetupGPMC();
+	muxSetupUsb0();		/* USB Device */
+	muxSetupUsbHost();	/* USB Host */
+	muxSetupUART1();
+	muxSetupLCD();
+	muxSetupMMCSD();
+	muxSetupTouchScreen();
+}
+
+/*****************************************************************
+ * Routine: peripheral_enable
+ * Description: Enable the clks & power for perifs (GPT2, UART1,...)
+******************************************************************/
+void peripheral_enable(void)
+{
+	unsigned int v, if_clks = 0, func_clks = 0;
+
+	/* Enable GP2 timer. */
+	if_clks |= BIT4 | BIT3;
+	func_clks |= BIT4 | BIT3;
+	v = __raw_readl(CM_CLKSEL2_CORE) | 0x4 | 0x2;	/* Sys_clk input OMAP2420_GPT2 */
+	__raw_writel(v, CM_CLKSEL2_CORE);
+	__raw_writel(0x1, CM_CLKSEL_WKUP);
+
+#ifdef CFG_NS16550
+	/* Enable UART1 clock */
+	func_clks |= BIT21;
+	if_clks |= BIT21;
+#endif
+	v = __raw_readl(CM_ICLKEN1_CORE) | if_clks;	/* Interface clocks on */
+	__raw_writel(v, CM_ICLKEN1_CORE);
+	v = __raw_readl(CM_FCLKEN1_CORE) | func_clks;	/* Functional Clocks on */
+	__raw_writel(v, CM_FCLKEN1_CORE);
+	delay(1000);
+
+#ifndef KERNEL_UPDATED
+	{
+#define V1 0xffffffff
+#define V2 0x00000007
+
+		__raw_writel(V1, CM_FCLKEN1_CORE);
+		__raw_writel(V2, CM_FCLKEN2_CORE);
+		__raw_writel(V1, CM_ICLKEN1_CORE);
+		__raw_writel(V1, CM_ICLKEN2_CORE);
+	}
+#endif
+}
+
+/****************************************
+ * Routine: muxSetupUsb0 (ostboot)
+ * Description: Setup usb muxing
+ *****************************************/
+void muxSetupUsb0(void)
+{
+	volatile uint8 *MuxConfigReg;
+
+	MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_USB0_PUEN;
+	*MuxConfigReg &= (uint8) (~0x1F);
+
+	MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_USB0_VP;
+	*MuxConfigReg &= (uint8) (~0x1F);
+
+	MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_USB0_VM;
+	*MuxConfigReg &= (uint8) (~0x1F);
+
+	MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_USB0_RCV;
+	*MuxConfigReg &= (uint8) (~0x1F);
+
+	MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_USB0_TXEN;
+	*MuxConfigReg &= (uint8) (~0x1F);
+
+	MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_USB0_SE0;
+	*MuxConfigReg &= (uint8) (~0x1F);
+
+	MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_USB0_DAT;
+	*MuxConfigReg &= (uint8) (~0x1F);
+}
+
+#define CONTROL_PADCONF_USB1_RCV	((volatile uint8 *)0x480000EB)
+#define CONTROL_PADCONF_USB1_TXEN	((volatile uint8 *)0x480000EC)
+#define CONTROL_PADCONF_GPIO69		((volatile uint8 *)0x480000ED)
+#define CONTROL_PADCONF_GPIO70		((volatile uint8 *)0x480000EE)
+
+#define CONTROL_PADCONF_GPIO102		((volatile uint8 *)0x48000116)
+#define CONTROL_PADCONF_GPIO103		((volatile uint8 *)0x48000117)
+#define CONTROL_PADCONF_GPIO104		((volatile uint8 *)0x48000118)
+#define CONTROL_PADCONF_GPIO105		((volatile uint8 *)0x48000119)
+/****************************************
+ * Routine: muxSetupUSBHost (ostboot)
+ * Description: Setup USB Host muxing
+ *****************************************/
+void muxSetupUsbHost(void)
+{
+	volatile uint8 *MuxConfigReg;
+
+	/* V19 */
+	MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_USB1_RCV;
+	*MuxConfigReg = 1;
+	/* W20 */
+	MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_USB1_TXEN;
+	*MuxConfigReg = 1;
+	/* N14 */
+	MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_GPIO69;
+	*MuxConfigReg = 3;
+	/* P15 */
+	MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_GPIO70;
+	*MuxConfigReg = 3;
+
+	/* L18 */
+	MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_GPIO102;
+	*MuxConfigReg = 3;
+	/* L19 */
+	MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_GPIO103;
+	*MuxConfigReg = 3;
+	/* K15 */
+	MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_GPIO104;
+	*MuxConfigReg = 3;
+	/* K14 */
+	MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_GPIO105;
+	*MuxConfigReg = 3;
+}
+
+/****************************************
+ * Routine: muxSetupUART1 (ostboot)
+ * Description: Set up uart1 muxing
+ *****************************************/
+void muxSetupUART1(void)
+{
+	volatile unsigned char *MuxConfigReg;
+
+	/* UART1_CTS pin configuration, PIN = D21 */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_UART1_CTS;
+	*MuxConfigReg = 0x00;	/* Mode = 0, PUPD=Disabled */
+
+	/* UART1_RTS pin configuration, PIN = H21 */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_UART1_RTS;
+	*MuxConfigReg = 0x00;	/* Mode = 0, PUPD=Disabled */
+
+	/* UART1_TX pin configuration, PIN = L20 */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_UART1_TX;
+	*MuxConfigReg = 0x00;	/* Mode = 0, PUPD=Disabled */
+
+	/* UART1_RX pin configuration, PIN = T21 */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_UART1_RX;
+	*MuxConfigReg = 0x00;	/* Mode = 0, PUPD=Disabled */
+}
+
+/****************************************
+ * Routine: muxSetupLCD (ostboot)
+ * Description: Setup lcd muxing
+ *****************************************/
+void muxSetupLCD(void)
+{
+	volatile unsigned char *MuxConfigReg;
+
+	/* LCD_D0 pin configuration, PIN = Y7 */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D0;
+	*MuxConfigReg = 0x00;	/* Mode = 0, PUPD=Disabled */
+
+	/* LCD_D1 pin configuration, PIN = P10 */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D1;
+	*MuxConfigReg = 0x00;	/* Mode = 0, PUPD=Disabled */
+
+	/* LCD_D2 pin configuration, PIN = V8 */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D2;
+	*MuxConfigReg = 0x00;	/* Mode = 0, PUPD=Disabled */
+
+	/* LCD_D3 pin configuration, PIN = Y8 */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D3;
+	*MuxConfigReg = 0x00;	/* Mode = 0, PUPD=Disabled */
+
+	/* LCD_D4 pin configuration, PIN = W8 */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D4;
+	*MuxConfigReg = 0x00;	/* Mode = 0, PUPD=Disabled */
+
+	/* LCD_D5 pin configuration, PIN = R10 */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D5;
+	*MuxConfigReg = 0x00;	/* Mode = 0, PUPD=Disabled */
+
+	/* LCD_D6 pin configuration, PIN = Y9 */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D6;
+	*MuxConfigReg = 0x00;	/* Mode = 0, PUPD=Disabled */
+
+	/* LCD_D7 pin configuration, PIN = V9 */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D7;
+	*MuxConfigReg = 0x00;	/* Mode = 0, PUPD=Disabled */
+
+	/* LCD_D8 pin configuration, PIN = W9 */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D8;
+	*MuxConfigReg = 0x00;	/* Mode = 0, PUPD=Disabled */
+
+	/* LCD_D9 pin configuration, PIN = P11 */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D9;
+	*MuxConfigReg = 0x00;	/* Mode = 0, PUPD=Disabled */
+
+	/* LCD_D10 pin configuration, PIN = V10 */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D10;
+	*MuxConfigReg = 0x00;	/* Mode = 0, PUPD=Disabled */
+
+	/* LCD_D11 pin configuration, PIN = Y10 */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D11;
+	*MuxConfigReg = 0x00;	/* Mode = 0, PUPD=Disabled */
+
+	/* LCD_D12 pin configuration, PIN = W10 */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D12;
+	*MuxConfigReg = 0x00;	/* Mode = 0, PUPD=Disabled */
+
+	/* LCD_D13 pin configuration, PIN = R11 */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D13;
+	*MuxConfigReg = 0x00;	/* Mode = 0, PUPD=Disabled */
+
+	/* LCD_D14 pin configuration, PIN = V11 */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D14;
+	*MuxConfigReg = 0x00;	/* Mode = 0, PUPD=Disabled */
+
+	/* LCD_D15 pin configuration, PIN = W11 */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D15;
+	*MuxConfigReg = 0x00;	/* Mode = 0, PUPD=Disabled */
+
+	/* LCD_D16 pin configuration, PIN = P12 */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D16;
+	*MuxConfigReg = 0x00;	/* Mode = 0, PUPD=Disabled */
+
+	/* LCD_D17 pin configuration, PIN = R12 */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D17;
+	*MuxConfigReg = 0x00;	/* Mode = 0, PUPD=Disabled */
+
+	/* LCD_PCLK pin configuration, PIN = W6 */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_PCLK;
+	*MuxConfigReg = 0x00;	/* Mode = 0, PUPD=Disabled */
+
+	/* LCD_VSYNC pin configuration, PIN = V7 */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_VSYNC;
+	*MuxConfigReg = 0x00;	/* Mode = 0, PUPD=Disabled */
+
+	/* LCD_HSYNC pin configuration, PIN = Y6 */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_HSYNC;
+	*MuxConfigReg = 0x00;	/* Mode = 0, PUPD=Disabled */
+
+	/* LCD_ACBIAS pin configuration, PIN = W7 */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_ACBIAS;
+	*MuxConfigReg = 0x00;	/* Mode = 0, PUPD=Disabled */
+}
+
+/****************************************
+ * Routine: muxSetupMMCSD (ostboot)
+ * Description: set up MMC muxing
+ *****************************************/
+void muxSetupMMCSD(void)
+{
+	volatile unsigned char *MuxConfigReg;
+
+	/* SDMMC_CLKI pin configuration, PIN = H15 */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_CLKI;
+	*MuxConfigReg = 0x00;	/* Mode = 0, PUPD=Disabled */
+
+	/* SDMMC_CLKO pin configuration, PIN = G19 */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_CLKO;
+	*MuxConfigReg = 0x00;	/* Mode = 0, PUPD=Disabled */
+
+	/* SDMMC_CMD pin configuration, PIN = H18 */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_CMD;
+	*MuxConfigReg = 0x00;	/* Mode = 0, PUPD=Disabled */
+	/* External pull-ups are present. */
+	/* *MuxConfigReg |= 0x18 ; #/ PullUDEnable=Enabled, PullTypeSel=PU */
+
+	/* SDMMC_DAT0 pin configuration, PIN = F20 */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT0;
+	*MuxConfigReg = 0x00;	/* Mode = 0, PUPD=Disabled */
+	/* External pull-ups are present. */
+	/* *MuxConfigReg |= 0x18 ; #/ PullUDEnable=Enabled, PullTypeSel=PU */
+
+	/* SDMMC_DAT1 pin configuration, PIN = H14 */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT1;
+	*MuxConfigReg = 0x00;	/* Mode = 0, PUPD=Disabled */
+	/* External pull-ups are present. */
+	/* *MuxConfigReg |= 0x18 ; #/ PullUDEnable=Enabled, PullTypeSel=PU */
+
+	/* SDMMC_DAT2 pin configuration, PIN = E19 */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT2;
+	*MuxConfigReg = 0x00;	/* Mode = 0, PUPD=Disabled */
+	/* External pull-ups are present. */
+	/* *MuxConfigReg |= 0x18 ; #/ PullUDEnable=Enabled, PullTypeSel=PU */
+
+	/* SDMMC_DAT3 pin configuration, PIN = D19 */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT3;
+	*MuxConfigReg = 0x00;	/* Mode = 0, PUPD=Disabled */
+	/* External pull-ups are present. */
+	/* *MuxConfigReg |= 0x18 ; #/ PullUDEnable=Enabled, PullTypeSel=PU */
+
+	/* SDMMC_DDIR0 pin configuration, PIN = F19 */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT_DIR0;
+	*MuxConfigReg = 0x00;	/* Mode = 0, PUPD=Disabled */
+
+	/* SDMMC_DDIR1 pin configuration, PIN = E20 */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT_DIR1;
+	*MuxConfigReg = 0x00;	/* Mode = 0, PUPD=Disabled */
+
+	/* SDMMC_DDIR2 pin configuration, PIN = F18 */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT_DIR2;
+	*MuxConfigReg = 0x00;	/* Mode = 0, PUPD=Disabled */
+
+	/* SDMMC_DDIR3 pin configuration, PIN = E18 */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT_DIR3;
+	*MuxConfigReg = 0x00;	/* Mode = 0, PUPD=Disabled */
+
+	/* SDMMC_CDIR pin configuration, PIN = G18 */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_CMD_DIR;
+	*MuxConfigReg = 0x00;	/* Mode = 0, PUPD=Disabled */
+}
+
+/******************************************
+ * Routine: muxSetupTouchScreen (ostboot)
+ * Description: Set up touch screen muxing
+*******************************************/
+void muxSetupTouchScreen(void)
+{
+	volatile unsigned char *MuxConfigReg;
+
+	/* SPI1_CLK pin configuration, PIN = U18 */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_SPI1_CLK;
+	*MuxConfigReg = 0x00;	/* Mode = 0, PUPD=Disabled */
+
+	/* SPI1_MOSI pin configuration, PIN = V20 */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_SPI1_SIMO;
+	*MuxConfigReg = 0x00;	/* Mode = 0, PUPD=Disabled */
+
+	/* SPI1_MISO pin configuration, PIN = T18 */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_SPI1_SOMI;
+	*MuxConfigReg = 0x00;	/* Mode = 0, PUPD=Disabled */
+
+	/* SPI1_nCS0 pin configuration, PIN = U19 */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_SPI1_NCS0;
+	*MuxConfigReg = 0x00;	/* Mode = 0, PUPD=Disabled */
+
+#define CONTROL_PADCONF_GPIO85	CONTROL_PADCONF_SPI1_NCS1
+
+	/* PEN_IRQ pin configuration, PIN = N15 */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_GPIO85;
+	*MuxConfigReg = 0x03;	/* Mode = 3, PUPD=Disabled */
+}
+
+/***************************************************************
+ * Routine: muxSetupGPMC (ostboot)
+ * Description: Configures balls which cam up in protected mode
+***************************************************************/
+void muxSetupGPMC(void)
+{
+	volatile uint8 *MuxConfigReg;
+	volatile unsigned int *MCR = (volatile unsigned int *)0x4800008C;
+
+	/* gpmc_io_dir */
+	*MCR = 0x19000000;
+
+	/* NOR FLASH CS0 */
+	/* signal - Gpmc_clk;
+		pin - J4; offset - 0x0088; mode - 0; Byte-3  Pull/up - N/A */
+	MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_GPMC_D2_BYTE3;
+	*MuxConfigReg = 0x00;
+
+	/* MPDB(Multi Port Debug Port) CS1 */
+	/* signal - gpmc_ncs1;
+		pin - N8; offset - 0x008C; mode - 0; Byte-1 Pull/up - N/A */
+	MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_GPMC_NCS0_BYTE1;
+	*MuxConfigReg = 0x00;
+
+	/* signal - Gpmc_ncs2;
+		pin - E2; offset - 0x008C; mode - 0; Byte-2 Pull/up - N/A */
+	MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_GPMC_NCS0_BYTE2;
+	*MuxConfigReg = 0x00;
+
+	/* signal - Gpmc_ncs3;
+		pin - N2; offset - 0x008C; mode - 0; Byte-3 Pull/up - N/A */
+	MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_GPMC_NCS0_BYTE3;
+	*MuxConfigReg = 0x00;
+
+	MuxConfigReg = (volatile uint8 *)((volatile unsigned char *)0x48000090);
+	*MuxConfigReg = 0x00;
+	MuxConfigReg = (volatile uint8 *)((volatile unsigned char *)0x48000091);
+	*MuxConfigReg = 0x00;
+	MuxConfigReg = (volatile uint8 *)((volatile unsigned char *)0x48000092);
+	*MuxConfigReg = 0x00;
+	MuxConfigReg = (volatile uint8 *)((volatile unsigned char *)0x48000093);
+	*MuxConfigReg = 0x00;
+}
+
+/****************************************************************
+ * Routine: muxSetupSDRC (ostboot)
+ * Description: Configures balls which come up in protected mode
+****************************************************************/
+void muxSetupSDRC(void)
+{
+	/* It's set by IPL */
+}
diff --git a/board/apollon/config.mk b/board/apollon/config.mk
new file mode 100644
index 000000000..417b954a7
--- /dev/null
+++ b/board/apollon/config.mk
@@ -0,0 +1,25 @@
+#
+# (C) Copyright 2005-2007
+# Samsung Electronics
+#
+# Samsung December board with OMAP2420 (ARM1136) cpu
+# see http://www.ti.com/ for more information on Texas Instruments
+#
+# December has 1 bank of 128MB mDDR-SDRAM on CS0
+# December has 1 bank of  00MB mDDR-SDRAM on CS1
+# Physical Address:
+# 8000'0000 (bank0)
+# A000/0000 (bank1) ES2 will be configurable
+# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000
+# (mem base + reserved)
+# For use with external or internal boots.
+TEXT_BASE = 0x80e80000
+
+# Used with full SRAM boot.
+# This is either with a GP system or a signed boot image.
+# easiest, and safest way to go if you can.
+#TEXT_BASE = 0x40270000
+
+# Handy to get symbols to debug ROM version.
+#TEXT_BASE = 0x0
+#TEXT_BASE = 0x08000000
diff --git a/board/apollon/lowlevel_init.S b/board/apollon/lowlevel_init.S
new file mode 100644
index 000000000..76762599b
--- /dev/null
+++ b/board/apollon/lowlevel_init.S
@@ -0,0 +1,337 @@
+/*
+ * Board specific setup info
+ *
+ * (C) Copyright 2005-2007
+ * Samsung Electronics,
+ * Kyungmin Park <kyungmin.park@samsung.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+#include <asm/arch/omap2420.h>
+#include <asm/arch/mem.h>
+#include <asm/arch/clocks.h>
+#include "mem.h"
+
+#define APOLLON_CS0_BASE        0x00000000
+
+#ifdef PRCM_CONFIG_I
+# define SDRC_ACTIM_CTRLA_0_VAL  0x7BA35907
+# define SDRC_ACTIM_CTRLB_0_VAL  0x00000013
+# define SDRC_RFR_CTRL_0_VAL     0x00044C01
+#elif defined(PRCM_CONFIG_II)
+# define SDRC_ACTIM_CTRLA_0_VAL  0x4A59B485
+# define SDRC_ACTIM_CTRLB_0_VAL  0x0000000C
+# define SDRC_RFR_CTRL_0_VAL     0x00030001
+#endif
+
+#define SDRAM_BASE_ADDRESS	0x80008000
+
+_TEXT_BASE:
+	.word	TEXT_BASE	/* sdram load addr from config.mk */
+
+.globl lowlevel_init
+lowlevel_init:
+
+#ifdef CFG_NOR_BOOT
+	/* Check running in SDRAM */
+	mov	r0, pc, lsr #28
+	cmp	r0, #8
+	beq	prcm_setup
+	
+flash_setup:
+	/* In Flash */
+	ldr	r0, =WD2_BASE
+	ldr	r1, =WD_UNLOCK1
+	str	r1, [r0, #WSPR]
+
+	ldr	r1, =WD_UNLOCK2
+	str	r1, [r0, #WSPR]
+
+        /* Pin muxing for SDRC */
+        mov     r1, #0x00
+        ldr     r0, =0x480000A1         /* ball C12, mode 0 */
+        strb    r1, [r0]
+
+        ldr     r0, =0x48000032         /* ball D11, mode 0 */
+        strb    r1, [r0]
+
+        ldr     r0, =0x480000A3         /* ball B13, mode 0 */
+        strb    r1, [r0]
+
+        /* SDRC setting */
+        ldr     r0, =OMAP2420_SDRC_BASE
+        ldr     r1, =0x00000010
+        str     r1, [r0, #0x10]
+
+        ldr     r1, =0x00000100
+        str     r1, [r0, #0x44]
+
+        /* SDRC CS0 configuration */
+        ldr     r1, =0x00d04011
+        str     r1, [r0, #0x80]
+
+        ldr     r1, =SDRC_ACTIM_CTRLA_0_VAL
+        str     r1, [r0, #0x9C]
+
+        ldr     r1, =SDRC_ACTIM_CTRLB_0_VAL
+        str     r1, [r0, #0xA0]
+
+        ldr     r1, =SDRC_RFR_CTRL_0_VAL
+        str     r1, [r0, #0xA4]
+
+        ldr     r1, =0x00000041
+        str     r1, [r0, #0x70]
+
+        /* Manual command sequence */
+        ldr     r1, =0x00000007
+        str     r1, [r0, #0xA8]
+
+        ldr     r1, =0x00000000
+        str     r1, [r0, #0xA8]
+
+        ldr     r1, =0x00000001
+        str     r1, [r0, #0xA8]
+
+        ldr     r1, =0x00000002
+        str     r1, [r0, #0xA8]
+        str     r1, [r0, #0xA8]
+
+        /*
+         * CS0 SDRC Mode register
+         *   Burst length = 4 - DDR memory
+         *   Serial mode
+         *   CAS latency = 3
+         */
+        ldr     r1, =0x00000032
+        str     r1, [r0, #0x84]
+
+        /* Note: You MUST set EMR values */
+        /* EMR1 & EMR2 */
+        ldr     r1, =0x00000000
+        str     r1, [r0, #0x88]
+        str     r1, [r0, #0x8C]
+
+#ifdef OLD_SDRC_DLLA_CTRL
+        /* SDRC_DLLA_CTRL */
+        ldr     r1, =0x00007306
+        str     r1, [r0, #0x60]
+
+        ldr     r1, =0x00007303
+        str     r1, [r0, #0x60]
+#else
+        /* SDRC_DLLA_CTRL */
+        ldr     r1, =0x00000506
+        str     r1, [r0, #0x60]
+
+        ldr     r1, =0x00000503
+        str     r1, [r0, #0x60]
+#endif
+
+#ifdef __BROKEN_FEATURE__
+        /* SDRC_DLLB_CTRL */
+        ldr     r1, =0x00000506
+        str     r1, [r0, #0x68]
+
+        ldr     r1, =0x00000503
+        str     r1, [r0, #0x68]
+#endif
+
+        /* little delay after init */
+        mov     r2, #0x1800
+1:
+        subs    r2, r2, #0x1
+        bne     1b
+
+	/* Setup base address */
+	ldr	r0, =0x00000000		/* NOR address */
+	ldr	r1, =SDRAM_BASE_ADDRESS	/* SDRAM address */
+	ldr	r2, =0x20000		/* Size: 128KB */
+
+copy_loop:
+	ldmia	r0!, {r3-r10}
+	stmia	r1!, {r3-r10}
+	cmp	r0, r2
+	ble	copy_loop
+
+	ldr	r1, =SDRAM_BASE_ADDRESS
+	mov	lr, pc
+	mov	pc, r1
+#endif
+
+prcm_setup:
+        ldr     r0, =OMAP2420_CM_BASE
+        ldr     r1, [r0, #0x544]        /* CLKSEL2_PLL */
+        bic     r1, r1, #0x03
+        orr     r1, r1, #0x02
+        str     r1, [r0, #0x544]
+
+        ldr     r1, [r0, #0x500]
+        bic     r1, r1, #0x03
+        orr     r1, r1, #0x01
+        str     r1, [r0, #0x500]
+
+        ldr     r1, [r0, #0x140]
+        bic     r1, r1, #0x1f
+        orr     r1, r1, #0x02
+        str     r1, [r0, #0x140]
+
+#ifdef PRCM_CONFIG_I
+	ldr	r1, =0x000003C3
+#else
+	ldr	r1, =0x00000343
+#endif
+	str	r1, [r0, #0x840]
+
+	ldr	r1, =0x00000002
+	str	r1, [r0, #0x340]
+	
+        ldr     r1, =CM_CLKSEL1_CORE
+#ifdef PRCM_CONFIG_I
+	ldr     r2, =0x08300C44
+#else
+	ldr     r2, =0x04600C26
+#endif
+        str     r2, [r1]
+	
+        ldr     r0, =OMAP2420_CM_BASE
+        ldr     r1, [r0, #0x084]
+        and     r1, r1, #0x01
+        cmp     r1, #0x01
+        bne     clkvalid
+
+        b       .
+
+clkvalid:
+        mov     r1, #0x01
+        str     r1, [r0, #0x080]
+
+waitvalid:
+        ldr     r1, [r0, #0x084]
+        and     r1, r1, #0x01
+        cmp     r1, #0x00
+        bne     waitvalid
+
+        ldr     r0, =CM_CLKSEL1_PLL
+#ifdef PRCM_CONFIG_I
+        ldr     r1, =0x01837100
+#else
+        ldr     r1, =0x01832100
+#endif
+        str     r1, [r0]
+
+        ldr     r0, =PRCM_CLKCFG_CTRL
+        mov     r1, #0x01
+        str     r1, [r0]
+        mov     r6, #0x50
+loop1:
+        subs    r6, r6, #0x01
+        cmp     r6, #0x01
+        bne     loop1
+
+        ldr     r0, =CM_CLKEN_PLL
+	mov	r1, #0x0f
+        str     r1, [r0]
+
+        mov     r6, #0x100
+loop2:
+        subs    r6, r6, #0x01
+        cmp     r6, #0x01
+        bne     loop2
+
+	ldr	r0, =0x48008200
+	ldr	r1, =0xbfffffff
+	str	r1, [r0]
+
+	ldr	r0, =0x48008210
+	ldr	r1, =0xfffffff9
+	str	r1, [r0]
+
+	ldr	r0, =0x4806a004
+	ldr	r1, =0x00
+	strb	r1, [r0]
+
+	ldr	r0, =0x4806a020
+	ldr	r1, =0x07
+	strb	r1, [r0]
+
+	ldr	r0, =0x4806a00c
+	ldr	r1, =0x83
+	strb	r1, [r0]
+
+	ldr	r0, =0x4806a000
+	ldr	r1, =0x1a
+	strb	r1, [r0]
+
+	ldr	r0, =0x4806a004
+	ldr	r1, =0x00
+	strb	r1, [r0]
+
+	ldr	r0, =0x4806a00c
+	ldr	r1, =0x03
+	strb	r1, [r0]
+
+	ldr	r0, =0x4806a010
+	ldr	r1, =0x03
+	strb	r1, [r0]
+
+	ldr	r0, =0x4806a008
+	ldr	r1, =0x04
+	strb	r1, [r0]
+
+	ldr	r0, =0x4806a020
+	ldr	r1, =0x00
+	strb	r1, [r0]
+
+#if 0
+	ldr	r0, =0x4806a000
+	mov	r1, #'u'
+	strb	r1, [r0]
+#endif
+
+#if 0
+	/* LED0 OFF */
+	ldr	r3, =0x480000E5
+	mov	r4, #0x0b
+	strb	r4, [r3]
+#endif
+
+	ldr	sp,	SRAM_STACK
+	str	ip,	[sp]	/* stash old link register */
+	mov	ip,	lr	/* save link reg across call */
+	bl	s_init		/* go setup pll,mux,memory */
+	ldr	ip,	[sp]	/* restore save ip */
+	mov	lr,	ip	/* restore link reg */
+
+	/* map interrupt controller */
+	ldr	r0,	VAL_INTH_SETUP
+	mcr	p15, 0, r0, c15, c2, 4
+
+	/* back to arch calling code */
+	mov	pc,	lr
+
+	/* the literal pools origin */
+	.ltorg
+
+VAL_INTH_SETUP:
+	.word PERIFERAL_PORT_BASE
+SRAM_STACK:
+	.word LOW_LEVEL_SRAM_STACK
diff --git a/board/apollon/mem.c b/board/apollon/mem.c
new file mode 100644
index 000000000..8154d1181
--- /dev/null
+++ b/board/apollon/mem.c
@@ -0,0 +1,228 @@
+/*
+ * (C) Copyright 2005-2007
+ * Samsung Electronics,
+ * Kyungmin Park <kyungmin.park@samsung.com>
+ *
+ * Derived from omap2420
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/omap2420.h>
+#include <asm/io.h>
+#include <asm/arch/bits.h>
+#include <asm/arch/mux.h>
+#include <asm/arch/mem.h>
+#include <asm/arch/clocks.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/sys_info.h>
+
+#include "mem.h"
+
+/************************************************************
+ * sdelay() - simple spin loop.  Will be constant time as
+ *  its generally used in 12MHz bypass conditions only.  This
+ *  is necessary until timers are accessible.
+ *
+ *  not inline to increase chances its in cache when called
+*************************************************************/
+void sdelay(unsigned long loops)
+{
+	__asm__ volatile ("1:\n" "subs %0, %1, #1\n"
+			  "bne 1b":"=r" (loops):"0"(loops));
+}
+
+/*****************************************************************************
+ * prcm_init() - inits clocks for PRCM as defined in clocks.h
+ * (config II default). Called from SRAM, or Flash (using temp SRAM stack).
+ *****************************************************************************/
+void prcm_init(void)
+{
+}
+
+/**************************************************************************
+ * make_cs1_contiguous() - for es2 and above remap cs1 behind cs0 to allow
+ *  command line mem=xyz use all memory with out discontigious support
+ *  compiled in.  Could do it at the ATAG, but there really is two banks...
+ * Called as part of 2nd phase DDR init.
+ **************************************************************************/
+void make_cs1_contiguous(void)
+{
+	u32 size, a_add_low, a_add_high;
+
+	size = get_sdr_cs_size(SDRC_CS0_OSET);
+	size /= SZ_32M;		/* find size to offset CS1 */
+	a_add_high = (size & 3) << 8;	/* set up low field */
+	a_add_low = (size & 0x3C) >> 2;	/* set up high field */
+	__raw_writel((a_add_high | a_add_low), SDRC_CS_CFG);
+}
+
+/********************************************************
+ *  mem_ok() - test used to see if timings are correct
+ *             for a part. Helps in gussing which part
+ *             we are currently using.
+ *******************************************************/
+u32 mem_ok(void)
+{
+	u32 val1, val2;
+	u32 pattern = 0x12345678;
+
+	__raw_writel(0x0, OMAP2420_SDRC_CS0 + 0x400);	/* clear pos A */
+	__raw_writel(pattern, OMAP2420_SDRC_CS0);	/* pattern to pos B */
+	__raw_writel(0x0, OMAP2420_SDRC_CS0 + 4);	/* remove pattern off the bus */
+	val1 = __raw_readl(OMAP2420_SDRC_CS0 + 0x400);	/* get pos A value */
+	val2 = __raw_readl(OMAP2420_SDRC_CS0);	/* get val2 */
+
+	if ((val1 != 0) || (val2 != pattern))	/* see if pos A value changed */
+		return (0);
+	else
+		return (1);
+}
+
+/********************************************************
+ *  sdrc_init() - init the sdrc chip selects CS0 and CS1
+ *  - early init routines, called from flash or
+ *  SRAM.
+ *******************************************************/
+void sdrc_init(void)
+{
+#define EARLY_INIT 1
+	/* only init up first bank here */
+	do_sdrc_init(SDRC_CS0_OSET, EARLY_INIT);
+}
+
+/*************************************************************************
+ * do_sdrc_init(): initialize the SDRAM for use.
+ *  -called from low level code with stack only.
+ *  -code sets up SDRAM timing and muxing for 2422 or 2420.
+ *  -optimal settings can be placed here, or redone after i2c
+ *      inspection of board info
+ *
+ *  This is a bit ugly, but should handle all memory moduels
+ *   used with the APOLLON. The first time though this code from s_init()
+ *   we configure the first chip select.  Later on we come back and
+ *   will configure the 2nd chip select if it exists.
+ *
+ **************************************************************************/
+void do_sdrc_init(u32 offset, u32 early)
+{
+}
+
+/*****************************************************
+ * gpmc_init(): init gpmc bus
+ * Init GPMC for x16, MuxMode (SDRAM in x32).
+ * This code can only be executed from SRAM or SDRAM.
+ *****************************************************/
+void gpmc_init(void)
+{
+	u32 mux = 0, mtype, mwidth, rev, tval;
+
+	rev = get_cpu_rev();
+	if (rev == CPU_2420_2422_ES1)
+		tval = 1;
+	else
+		tval = 0;	/* disable bit switched meaning */
+
+	/* global settings */
+	__raw_writel(0x10, GPMC_SYSCONFIG);	/* smart idle */
+	__raw_writel(0x0, GPMC_IRQENABLE);	/* isr's sources masked */
+	__raw_writel(tval, GPMC_TIMEOUT_CONTROL);	/* timeout disable */
+#ifdef CFG_NAND_BOOT
+	__raw_writel(0x001, GPMC_CONFIG);	/* set nWP, disable limited addr */
+#else
+	__raw_writel(0x111, GPMC_CONFIG);	/* set nWP, disable limited addr */
+#endif
+
+	/* discover bus connection from sysboot */
+	if (is_gpmc_muxed() == GPMC_MUXED)
+		mux = BIT9;
+	mtype = get_gpmc0_type();
+	mwidth = get_gpmc0_width();
+
+	/* setup cs0 */
+	__raw_writel(0x0, GPMC_CONFIG7_0);	/* disable current map */
+	sdelay(1000);
+
+#ifdef CFG_NOR_BOOT
+	__raw_writel(APOLLON_24XX_GPMC_CONFIG1_3, GPMC_CONFIG1_0);
+	__raw_writel(APOLLON_24XX_GPMC_CONFIG2_3, GPMC_CONFIG2_0);
+	__raw_writel(APOLLON_24XX_GPMC_CONFIG3_3, GPMC_CONFIG3_0);
+	__raw_writel(APOLLON_24XX_GPMC_CONFIG4_3, GPMC_CONFIG4_0);
+	__raw_writel(APOLLON_24XX_GPMC_CONFIG5_3, GPMC_CONFIG5_0);
+	__raw_writel(APOLLON_24XX_GPMC_CONFIG6_3, GPMC_CONFIG6_0);
+	__raw_writel(APOLLON_24XX_GPMC_CONFIG7_3, GPMC_CONFIG7_0); #else
+	__raw_writel(APOLLON_24XX_GPMC_CONFIG1_0 | mux | mtype | mwidth,
+		     GPMC_CONFIG1_0);
+	__raw_writel(APOLLON_24XX_GPMC_CONFIG2_0, GPMC_CONFIG2_0);
+	__raw_writel(APOLLON_24XX_GPMC_CONFIG3_0, GPMC_CONFIG3_0);
+	__raw_writel(APOLLON_24XX_GPMC_CONFIG4_0, GPMC_CONFIG4_0);
+	__raw_writel(APOLLON_24XX_GPMC_CONFIG5_0, GPMC_CONFIG5_0);
+	__raw_writel(APOLLON_24XX_GPMC_CONFIG6_0, GPMC_CONFIG6_0);
+	/* enable new mapping */
+	__raw_writel(APOLLON_24XX_GPMC_CONFIG7_0, GPMC_CONFIG7_0);
+#endif
+	sdelay(2000);
+
+	/* setup cs1 */
+	__raw_writel(0, GPMC_CONFIG7_1);	/* disable any mapping */
+	sdelay(1000);
+
+	__raw_writel(APOLLON_24XX_GPMC_CONFIG1_1, GPMC_CONFIG1_1);
+	__raw_writel(APOLLON_24XX_GPMC_CONFIG2_1, GPMC_CONFIG2_1);
+	__raw_writel(APOLLON_24XX_GPMC_CONFIG3_1, GPMC_CONFIG3_1);
+	__raw_writel(APOLLON_24XX_GPMC_CONFIG4_1, GPMC_CONFIG4_1);
+	__raw_writel(APOLLON_24XX_GPMC_CONFIG5_1, GPMC_CONFIG5_1);
+	__raw_writel(APOLLON_24XX_GPMC_CONFIG6_1, GPMC_CONFIG6_1);
+	__raw_writel(APOLLON_24XX_GPMC_CONFIG7_1, GPMC_CONFIG7_1);
+	sdelay(2000);
+
+	/* setup cs2 */
+	__raw_writel(APOLLON_24XX_GPMC_CONFIG1_0 | mux | mtype | mwidth,
+		     GPMC_CONFIG1_2);
+	/* It's same as cs 0 */
+	__raw_writel(APOLLON_24XX_GPMC_CONFIG2_0, GPMC_CONFIG2_2);
+	__raw_writel(APOLLON_24XX_GPMC_CONFIG3_0, GPMC_CONFIG3_2);
+	__raw_writel(APOLLON_24XX_GPMC_CONFIG4_0, GPMC_CONFIG4_2);
+	__raw_writel(APOLLON_24XX_GPMC_CONFIG5_0, GPMC_CONFIG5_2);
+	__raw_writel(APOLLON_24XX_GPMC_CONFIG6_0, GPMC_CONFIG6_2);
+#ifdef CFG_NOR_BOOT
+	__raw_writel(APOLLON_24XX_GPMC_CONFIG7_0, GPMC_CONFIG7_2);
+#else
+	__raw_writel(APOLLON_24XX_GPMC_CONFIG7_2, GPMC_CONFIG7_2);
+#endif
+
+#ifndef CFG_NOR_BOOT
+	/* setup cs3 */
+	__raw_writel(0, GPMC_CONFIG7_3);	/* disable any mapping */
+	sdelay(1000);
+
+	__raw_writel(APOLLON_24XX_GPMC_CONFIG1_3, GPMC_CONFIG1_3);
+	__raw_writel(APOLLON_24XX_GPMC_CONFIG2_3, GPMC_CONFIG2_3);
+	__raw_writel(APOLLON_24XX_GPMC_CONFIG3_3, GPMC_CONFIG3_3);
+	__raw_writel(APOLLON_24XX_GPMC_CONFIG4_3, GPMC_CONFIG4_3);
+	__raw_writel(APOLLON_24XX_GPMC_CONFIG5_3, GPMC_CONFIG5_3);
+	__raw_writel(APOLLON_24XX_GPMC_CONFIG6_3, GPMC_CONFIG6_3);
+	__raw_writel(APOLLON_24XX_GPMC_CONFIG7_3, GPMC_CONFIG7_3);
+#endif
+
+#ifndef ASYNC_NOR
+	__raw_writew(0xaa, (APOLLON_CS3_BASE + 0xaaa));
+	__raw_writew(0x55, (APOLLON_CS3_BASE + 0x554));
+	__raw_writew(0xc0, (APOLLON_CS3_BASE | SYNC_NOR_VALUE));
+#endif
+	sdelay(2000);
+}
diff --git a/board/apollon/mem.h b/board/apollon/mem.h
new file mode 100644
index 000000000..aed7e1d64
--- /dev/null
+++ b/board/apollon/mem.h
@@ -0,0 +1,170 @@
+/*
+ * (C) Copyright 2005-2007
+ * Samsung Electronics,
+ * Kyungmin Park <kyungmin.park@samsung.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _APOLLON_OMAP24XX_MEM_H_
+#define _APOLLON_OMAP24XX_MEM_H_
+
+/* Slower full frequency range default timings for x32 operation*/
+#define APOLLON_2420_SDRC_SHARING		0x00000100
+#define APOLLON_2420_SDRC_MDCFG_0_DDR		0x00d04011
+#define APOLLON_2420_SDRC_MR_0_DDR		0x00000032
+
+/* optimized timings good for current shipping parts */
+#define APOLLON_242X_SDRC_ACTIM_CTRLA_0_100MHz	0x4A59B485
+#define APOLLON_242X_SDRC_ACTIM_CTRLB_0_100MHz	0x0000000C
+
+#define APOLLON_242X_SDRC_ACTIM_CTRLA_0_166MHz	0x7BA35907
+#define APOLLON_242X_SDRC_ACTIM_CTRLB_0_166MHz	0x00000013
+
+#define APOLLON_242X_SDRC_RFR_CTRL_100MHz	0x00030001
+#define APOLLON_242X_SDRC_RFR_CTRL_166MHz	0x00044C01
+
+#define APOLLON_242x_SDRC_DLLAB_CTRL_100MHz	0x00007306
+#define APOLLON_242x_SDRC_DLLAB_CTRL_166MHz	0x00000506
+
+#ifdef PRCM_CONFIG_I
+# define APOLLON_2420_SDRC_ACTIM_CTRLA_0	APOLLON_242X_SDRC_ACTIM_CTRLA_0_166MHz
+# define APOLLON_2420_SDRC_ACTIM_CTRLB_0	APOLLON_242X_SDRC_ACTIM_CTRLB_0_166MHz
+# define APOLLON_2420_SDRC_RFR_CTRL		APOLLON_242X_SDRC_RFR_CTRL_166MHz
+# define APOLLON_2420_SDRC_DLLAB_CTRL		APOLLON_242x_SDRC_DLLAB_CTRL_166MHz
+#elif PRCM_CONFIG_II
+# define APOLLON_2420_SDRC_ACTIM_CTRLA_0	APOLLON_242X_SDRC_ACTIM_CTRLA_0_100MHz
+# define APOLLON_2420_SDRC_ACTIM_CTRLB_0	APOLLON_242X_SDRC_ACTIM_CTRLB_0_100MHz
+# define APOLLON_2420_SDRC_RFR_CTRL		APOLLON_242X_SDRC_RFR_CTRL_100MHz
+# define APOLLON_2420_SDRC_DLLAB_CTRL		APOLLON_242x_SDRC_DLLAB_CTRL_100MHz
+#endif
+
+/* GPMC settings */
+#ifdef PRCM_CONFIG_I		/* L3 at 165MHz */
+/* CS0: OneNAND */
+# define APOLLON_24XX_GPMC_CONFIG1_0	0x00000001
+# define APOLLON_24XX_GPMC_CONFIG2_0	0x000c1000
+# define APOLLON_24XX_GPMC_CONFIG3_0	0x00030400
+# define APOLLON_24XX_GPMC_CONFIG4_0	0x0b841006
+# define APOLLON_24XX_GPMC_CONFIG5_0	0x020f0c11
+# define APOLLON_24XX_GPMC_CONFIG6_0	0x00000000
+# define APOLLON_24XX_GPMC_CONFIG7_0	(0x00000e40|(APOLLON_CS0_BASE >> 24))
+
+/* CS1: Ethernet */
+# define APOLLON_24XX_GPMC_CONFIG1_1	0x00011200
+# define APOLLON_24XX_GPMC_CONFIG2_1	0x001F1F01
+# define APOLLON_24XX_GPMC_CONFIG3_1	0x00080803
+# define APOLLON_24XX_GPMC_CONFIG4_1	0x1C0b1C0a
+# define APOLLON_24XX_GPMC_CONFIG5_1	0x041F1F1F
+# define APOLLON_24XX_GPMC_CONFIG6_1	0x000004C4
+# define APOLLON_24XX_GPMC_CONFIG7_1	(0x00000F40|(APOLLON_CS1_BASE >> 24))
+
+/* CS2: OneNAND */
+/* It's same as CS0 */
+# define APOLLON_24XX_GPMC_CONFIG7_2	(0x00000e40|(APOLLON_CS2_BASE >> 24))
+
+/* CS3: NOR */
+#ifdef ASYNC_NOR
+# define APOLLON_24XX_GPMC_CONFIG1_3	0x00021201
+# define APOLLON_24XX_GPMC_CONFIG2_3	0x00121601
+# define APOLLON_24XX_GPMC_CONFIG3_3	0x00040401
+# define APOLLON_24XX_GPMC_CONFIG4_3	0x12061605
+# define APOLLON_24XX_GPMC_CONFIG5_3	0x01151317
+#else
+# define SYNC_NOR_VALUE			0x24aaa
+# define APOLLON_24XX_GPMC_CONFIG1_3	0xe5011211
+# define APOLLON_24XX_GPMC_CONFIG2_3	0x00090b01
+# define APOLLON_24XX_GPMC_CONFIG3_3	0x00020201
+# define APOLLON_24XX_GPMC_CONFIG4_3	0x09030b03
+# define APOLLON_24XX_GPMC_CONFIG5_3	0x010a0a0c
+#endif /* ASYNC_NOR */
+# define APOLLON_24XX_GPMC_CONFIG6_3	0x00000000
+# define APOLLON_24XX_GPMC_CONFIG7_3	(0x00000e40|(APOLLON_CS3_BASE >> 24))
+#endif /* endif PRCM_CONFIG_I */
+
+#ifdef PRCM_CONFIG_II		/* L3 at 100MHz */
+/* CS0: OneNAND */
+# define APOLLON_24XX_GPMC_CONFIG1_0	0x00000001
+# define APOLLON_24XX_GPMC_CONFIG2_0	0x00081080
+# define APOLLON_24XX_GPMC_CONFIG3_0	0x00030300
+# define APOLLON_24XX_GPMC_CONFIG4_0	0x08041004
+# define APOLLON_24XX_GPMC_CONFIG5_0	0x020b0910
+# define APOLLON_24XX_GPMC_CONFIG6_0	0x00000000
+# define APOLLON_24XX_GPMC_CONFIG7_0	(0x00000C40|(APOLLON_CS0_BASE >> 24))
+
+/* CS1: ethernet */
+# define APOLLON_24XX_GPMC_CONFIG1_1	0x00401203
+# define APOLLON_24XX_GPMC_CONFIG2_1	0x001F1F01
+# define APOLLON_24XX_GPMC_CONFIG3_1	0x00080803
+# define APOLLON_24XX_GPMC_CONFIG4_1	0x1C091C09
+# define APOLLON_24XX_GPMC_CONFIG5_1	0x041F1F1F
+# define APOLLON_24XX_GPMC_CONFIG6_1	0x000004C4
+# define APOLLON_24XX_GPMC_CONFIG7_1	(0x00000F40|(APOLLON_CS1_BASE >> 24))
+
+/* CS2: OneNAND */
+/* It's same as CS0 */
+# define APOLLON_24XX_GPMC_CONFIG7_2	(0x00000e40|(APOLLON_CS2_BASE >> 24))
+
+/* CS3: NOR */
+#define ASYNC_NOR
+#ifdef ASYNC_NOR
+# define APOLLON_24XX_GPMC_CONFIG1_3	0x00021201
+# define APOLLON_24XX_GPMC_CONFIG2_3	0x00121601
+# define APOLLON_24XX_GPMC_CONFIG3_3	0x00040401
+# define APOLLON_24XX_GPMC_CONFIG4_3	0x12061605
+# define APOLLON_24XX_GPMC_CONFIG5_3	0x01151317
+#else
+# define SYNC_NOR_VALUE			0x24aaa
+# define APOLLON_24XX_GPMC_CONFIG1_3	0xe1001202
+# define APOLLON_24XX_GPMC_CONFIG2_3	0x00151501
+# define APOLLON_24XX_GPMC_CONFIG3_3	0x00050501
+# define APOLLON_24XX_GPMC_CONFIG4_3	0x0e070e07
+# define APOLLON_24XX_GPMC_CONFIG5_3	0x01131F1F
+#endif /* ASYNC_NOR */
+# define APOLLON_24XX_GPMC_CONFIG6_3	0x00000000
+# define APOLLON_24XX_GPMC_CONFIG7_3	(0x00000C40|(APOLLON_CS3_BASE >> 24))
+#endif /* endif PRCM_CONFIG_II */
+
+#ifdef PRCM_CONFIG_III		/* L3 at 133MHz */
+# ifdef CFG_NAND_BOOT
+#  define APOLLON_24XX_GPMC_CONFIG1_0   0x0
+#  define APOLLON_24XX_GPMC_CONFIG2_0   0x00141400
+#  define APOLLON_24XX_GPMC_CONFIG3_0   0x00141400
+#  define APOLLON_24XX_GPMC_CONFIG4_0   0x0F010F01
+#  define APOLLON_24XX_GPMC_CONFIG5_0   0x010C1414
+#  define APOLLON_24XX_GPMC_CONFIG6_0   0x00000A80
+# else /* NOR boot */
+#  define APOLLON_24XX_GPMC_CONFIG1_0   0x3
+#  define APOLLON_24XX_GPMC_CONFIG2_0   0x00151501
+#  define APOLLON_24XX_GPMC_CONFIG3_0   0x00060602
+#  define APOLLON_24XX_GPMC_CONFIG4_0   0x10081008
+#  define APOLLON_24XX_GPMC_CONFIG5_0   0x01131F1F
+#  define APOLLON_24XX_GPMC_CONFIG6_0   0x000004c4
+# endif	/* endif CFG_NAND_BOOT */
+# define APOLLON_24XX_GPMC_CONFIG7_0	(0x00000C40|(APOLLON_CS0_BASE >> 24))
+# define APOLLON_24XX_GPMC_CONFIG1_1	0x00011000
+# define APOLLON_24XX_GPMC_CONFIG2_1	0x001f1f01
+# define APOLLON_24XX_GPMC_CONFIG3_1	0x00080803
+# define APOLLON_24XX_GPMC_CONFIG4_1	0x1C091C09
+# define APOLLON_24XX_GPMC_CONFIG5_1	0x041f1F1F
+# define APOLLON_24XX_GPMC_CONFIG6_1	0x000004C4
+# define APOLLON_24XX_GPMC_CONFIG7_1	(0x00000F40|(APOLLON_CS1_BASE >> 24))
+#endif /* endif CFG_PRCM_III */
+
+#endif /* endif _APOLLON_OMAP24XX_MEM_H_ */
diff --git a/board/apollon/sys_info.c b/board/apollon/sys_info.c
new file mode 100644
index 000000000..60c35b458
--- /dev/null
+++ b/board/apollon/sys_info.c
@@ -0,0 +1,408 @@
+/*
+ * (C) Copyright 2005-2007
+ * Samsung Electronics,
+ * Kyungmin Park <kyungmin.park@samsung.com>
+ *
+ * Derived from omap2420
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/omap2420.h>
+#include <asm/io.h>
+#include <asm/arch/bits.h>
+#include <asm/arch/mem.h>	/* get mem tables */
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/sys_info.h>
+#include <i2c.h>
+
+/**************************************************************************
+ * get_prod_id() - get id info from chips
+ ***************************************************************************/
+static u32 get_prod_id(void)
+{
+	u32 p;
+	p = __raw_readl(PRODUCTION_ID);	/* get production ID */
+	return ((p & CPU_242X_PID_MASK) >> 16);
+}
+/**************************************************************************
+ * get_cpu_type() - low level get cpu type
+ * - no C globals yet.
+ * - just looking to say if this is a 2422 or 2420 or ...
+ * - to start with we will look at switch settings..
+ * - 2422 id's same as 2420 for ES1 will rely on H4 board characteristics
+ *   (mux for 2420, non-mux for 2422).
+ ***************************************************************************/
+u32 get_cpu_type(void)
+{
+	u32 v;
+
+	switch (get_prod_id()) {
+	case 1:;		/* 2420 */
+	case 2:
+		return (CPU_2420);
+		break;		/* 2420 pop */
+	case 4:
+		return (CPU_2422);
+		break;
+	case 8:
+		return (CPU_2423);
+		break;
+	default:
+		break;		/* early 2420/2422's unmarked */
+	}
+
+	v = __raw_readl(TAP_IDCODE_REG);
+	v &= CPU_24XX_ID_MASK;
+	if (v == CPU_2420_CHIPID) {	/* currently 2420 and 2422 have same id */
+		if (is_gpmc_muxed() == GPMC_MUXED)	/* if mux'ed */
+			return (CPU_2420);
+		else
+			return (CPU_2422);
+	} else
+		return (CPU_2420);	/* don't know, say 2420 */
+}
+
+/******************************************
+ * get_cpu_rev(void) - extract version info
+ ******************************************/
+u32 get_cpu_rev(void)
+{
+	u32 v;
+	v = __raw_readl(TAP_IDCODE_REG);
+	v = v >> 28;
+	return (v + 1);		/* currently 2422 and 2420 match up */
+}
+
+/****************************************************
+ * is_mem_sdr() - return 1 if mem type in use is SDR
+ ****************************************************/
+u32 is_mem_sdr(void)
+{
+	volatile u32 *burst = (volatile u32 *)(SDRC_MR_0 + SDRC_CS0_OSET);
+	if (*burst == H4_2420_SDRC_MR_0_SDR)
+		return (1);
+	return (0);
+}
+
+/***********************************************************
+ * get_mem_type() - identify type of mDDR part used.
+ * 2422 uses stacked DDR, 2 parts CS0/CS1.
+ * 2420 may have 1 or 2, no good way to know...only init 1...
+ * when eeprom data is up we can select 1 more.
+ *************************************************************/
+u32 get_mem_type(void)
+{
+	u32 cpu, sdr = is_mem_sdr();
+
+	cpu = get_cpu_type();
+	if (cpu == CPU_2422 || cpu == CPU_2423)
+		return (DDR_STACKED);
+
+	if (get_prod_id() == 0x2)
+		return (XDR_POP);
+
+	if (get_board_type() == BOARD_H4_MENELAUS)
+		if (sdr)
+			return (SDR_DISCRETE);
+		else
+			return (DDR_COMBO);
+	else if (sdr)		/* SDP + SDR kit */
+		return (SDR_DISCRETE);
+	else
+		return (DDR_DISCRETE);	/* origional SDP */
+}
+
+/**********************************************************************
+ *
+ * get_cs0_size() - get size of chip select 0/1
+ ************************************************************************/
+u32 get_sdr_cs_size(u32 offset)
+{
+	u32 size;
+	size = __raw_readl(SDRC_MCFG_0 + offset) >> 8;	/* get ram size field */
+	size &= 0x2FF;		/* remove unwanted bits */
+	size *= SZ_2M;		/* find size in MB */
+	return (size);
+}
+
+/**********************************************************************
+ *
+ * get_board_type() - get board type based on current production stats.
+ *  --- NOTE: 2 I2C EEPROMs will someday be populated with proper info.
+ *      when they are available we can get info from there.  This should
+ *      be correct of all known boards up until today.
+ ************************************************************************/
+u32 get_board_type(void)
+{
+#if 0
+	if (i2c_probe(I2C_MENELAUS) == 0)
+		return (BOARD_H4_MENELAUS);
+	else
+#endif
+		return (BOARD_H4_SDP);
+}
+
+/******************************************************************
+ * get_sysboot_value() - get init word settings (dip switch on h4)
+******************************************************************/
+inline u32 get_sysboot_value(void)
+{
+	return (0x00000FFF & __raw_readl(CONTROL_STATUS));
+}
+
+/***************************************************************************
+ *  get_gpmc0_base() - Return current address hardware will be
+ *     fetching from. The below effectively gives what is correct, its a bit
+ *   mis-leading compared to the TRM.  For the most general case the mask
+ *   needs to be also taken into account this does work in practice.
+ *   - for u-boot we currently map:
+ *       -- 0 to nothing,
+ *       -- 4 to flash
+ *       -- 8 to enent
+ *       -- c to wifi
+ ***************************************************************************/
+u32 get_gpmc0_base(void)
+{
+	u32 b;
+
+	b = __raw_readl(GPMC_CONFIG7_0);
+	b &= 0x1F;		/* keep base [5:0] */
+	b = b << 24;		/* ret 0x0b000000 */
+	return (b);
+}
+
+/*****************************************************************
+ *  is_gpmc_muxed() - tells if address/data lines are multiplexed
+ *****************************************************************/
+u32 is_gpmc_muxed(void)
+{
+	u32 mux;
+	mux = get_sysboot_value();
+	if ((mux & (BIT0 | BIT1 | BIT2 | BIT3)) == (BIT0 | BIT2 | BIT3))
+		return (GPMC_MUXED);	/* NAND Boot mode */
+	if (mux & BIT1)		/* if mux'ed */
+		return (GPMC_MUXED);
+	else
+		return (GPMC_NONMUXED);
+}
+
+/************************************************************************
+ *  get_gpmc0_type() - read sysboot lines to see type of memory attached
+ ************************************************************************/
+u32 get_gpmc0_type(void)
+{
+	u32 type;
+	type = get_sysboot_value();
+	if ((type & (BIT3 | BIT2)) == (BIT3 | BIT2))
+		return (TYPE_NAND);
+	else
+		return (TYPE_NOR);
+}
+
+/*******************************************************************
+ * get_gpmc0_width() - See if bus is in x8 or x16 (mainly for nand)
+ *******************************************************************/
+u32 get_gpmc0_width(void)
+{
+	u32 width;
+	width = get_sysboot_value();
+	if ((width & 0xF) == (BIT3 | BIT2))
+		return (WIDTH_8BIT);
+	else
+		return (WIDTH_16BIT);
+}
+
+/*********************************************************************
+ * wait_on_value() - common routine to allow waiting for changes in
+ *   volatile regs.
+ *********************************************************************/
+u32 wait_on_value(u32 read_bit_mask, u32 match_value, u32 read_addr,
+u32 bound) {
+	u32 i = 0, val;
+	do {
+		++i;
+		val = __raw_readl(read_addr) & read_bit_mask;
+		if (val == match_value)
+			return (1);
+		if (i == bound)
+			return (0);
+	} while (1);
+}
+
+/*********************************************************************
+ *  display_board_info() - print banner with board info.
+ *********************************************************************/
+void display_board_info(u32 btype)
+{
+	char cpu_2420[] = "2420";	/* cpu type */
+	char cpu_2422[] = "2422";
+	char cpu_2423[] = "2423";
+	char db_men[] = "Menelaus";	/* board type */
+	char db_ip[] = "IP";
+	char mem_sdr[] = "mSDR";	/* memory type */
+	char mem_ddr[] = "mDDR";
+	char t_tst[] = "TST";	/* security level */
+	char t_emu[] = "EMU";
+	char t_hs[] = "HS";
+	char t_gp[] = "GP";
+	char unk[] = "?";
+
+	char *cpu_s, *db_s, *mem_s, *sec_s;
+	u32 cpu, rev, sec;
+
+	rev = get_cpu_rev();
+	cpu = get_cpu_type();
+	sec = get_device_type();
+
+	if (is_mem_sdr())
+		mem_s = mem_sdr;
+	else
+		mem_s = mem_ddr;
+
+	if (cpu == CPU_2423)
+		cpu_s = cpu_2423;
+	else if (cpu == CPU_2422)
+		cpu_s = cpu_2422;
+	else
+		cpu_s = cpu_2420;
+
+	if (btype == BOARD_H4_MENELAUS)
+		db_s = db_men;
+	else
+		db_s = db_ip;
+
+	switch (sec) {
+	case TST_DEVICE:
+		sec_s = t_tst;
+		break;
+	case EMU_DEVICE:
+		sec_s = t_emu;
+		break;
+	case HS_DEVICE:
+		sec_s = t_hs;
+		break;
+	case GP_DEVICE:
+		sec_s = t_gp;
+		break;
+	default:
+		sec_s = unk;
+	}
+
+	printf("OMAP%s-%s revision %d\n", cpu_s, sec_s, rev - 1);
+	printf("Samsung Apollon SDP Base Board + %s \n", mem_s); }
+
+/*************************************************************************
+ * get_board_rev() - setup to pass kernel board revision information
+ *          0 = 242x IP platform (first 2xx boards)
+ *          1 = 242x Menelaus platfrom.
+ *************************************************************************/
+u32 get_board_rev(void)
+{
+	u32 rev = 0;
+	u32 btype = get_board_type();
+
+	if (btype == BOARD_H4_MENELAUS) {
+		rev = 1;
+	}
+	return (rev);
+}
+
+/********************************************************
+ *  get_base(); get upper addr of current execution
+ *******************************************************/
+u32 get_base(void)
+{
+	u32 val;
+	__asm__ __volatile__("mov %0, pc \n":"=r"(val)::"memory");
+	val &= 0xF0000000;
+	val >>= 28;
+	return (val);
+}
+
+/********************************************************
+ *  get_base2(); get 2upper addr of current execution
+ *******************************************************/
+u32 get_base2(void)
+{
+	u32 val;
+	__asm__ __volatile__("mov %0, pc \n":"=r"(val)::"memory");
+	val &= 0xFF000000;
+	val >>= 24;
+	return (val);
+}
+
+/********************************************************
+ *  running_in_flash() - tell if currently running in
+ *   flash.
+ *******************************************************/
+u32 running_in_flash(void)
+{
+	if (get_base() < 4)
+		return (1);	/* in flash */
+	return (0);		/* running in SRAM or SDRAM */
+}
+
+/********************************************************
+ *  running_in_sram() - tell if currently running in
+ *   sram.
+ *******************************************************/
+u32 running_in_sram(void)
+{
+	if (get_base() == 4)
+		return (1);	/* in SRAM */
+	return (0);		/* running in FLASH or SDRAM */
+}
+
+/********************************************************
+ *  running_in_sdram() - tell if currently running in
+ *   flash.
+ *******************************************************/
+u32 running_in_sdram(void)
+{
+	if (get_base() > 4)
+		return (1);	/* in sdram */
+	return (0);		/* running in SRAM or FLASH */
+}
+
+/*************************************************************
+ *  running_from_internal_boot() - am I a signed NOR image.
+ *************************************************************/
+u32 running_from_internal_boot(void)
+{
+	u32 v, base;
+
+	v = get_sysboot_value() & BIT3;
+	base = get_base2();
+	/* if running at mask rom flash address and
+	 * sysboot3 says this was an internal boot
+	 */
+	if ((base == 0x08) && v)
+		return (1);
+	else
+		return (0);
+}
+
+/*************************************************************
+ *  get_device_type(): tell if GP/HS/EMU/TST
+ *************************************************************/
+u32 get_device_type(void)
+{
+	int mode;
+	mode = __raw_readl(CONTROL_STATUS) & (BIT10 | BIT9 | BIT8);
+	return (mode >>= 8);
+}
diff --git a/board/apollon/u-boot.lds b/board/apollon/u-boot.lds
new file mode 100644
index 000000000..686d86b76
--- /dev/null
+++ b/board/apollon/u-boot.lds
@@ -0,0 +1,64 @@
+/*
+ *
+ * Copyright (C) 2005-2007 Samsung Electronics
+ * Kyungin Park <kyugnmin.park@samsung.com>
+ *
+ * January 2004 - Changed to support H4 device
+ * Copyright (c) 2004 Texas Instruments
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text	 :
+	{
+		cpu/arm1136/start.o	(.text)
+		*(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(.rodata) }
+
+	. = ALIGN(4);
+	.data : { *(.data) }
+
+	. = ALIGN(4);
+	.got : { *(.got) }
+
+	. = .;
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+	__bss_start = .;
+	.bss : { *(.bss) }
+	_end = .;
+}
+
diff --git a/include/asm-arm/arch-arm1136/mux.h b/include/asm-arm/arch-arm1136/mux.h
index 67c841908..8bcd7a368 100644
--- a/include/asm-arm/arch-arm1136/mux.h
+++ b/include/asm-arm/arch-arm1136/mux.h
@@ -28,6 +28,7 @@ typedef  unsigned int uint32;
 void muxSetupSDRC(void);
 void muxSetupGPMC(void);
 void muxSetupUsb0(void);
+void muxSetupUsbHost(void);
 void muxSetupUart3(void);
 void muxSetupI2C1(void);
 void muxSetupUART1(void);
@@ -70,6 +71,7 @@ void muxSetupHDQ(void);
 #define CONTROL_PADCONF_SPI1_SIMO       ((volatile unsigned char *)0x48000100)
 #define CONTROL_PADCONF_SPI1_SOMI       ((volatile unsigned char *)0x48000101)
 #define CONTROL_PADCONF_SPI1_NCS0       ((volatile unsigned char *)0x48000102)
+#define CONTROL_PADCONF_SPI1_NCS1       ((volatile unsigned char *)0x48000103)
 
 #define CONTROL_PADCONF_MCBSP1_FSR      ((volatile unsigned char *)0x4800010B)
 
diff --git a/include/asm-arm/arch-arm1136/omap2420.h b/include/asm-arm/arch-arm1136/omap2420.h
index d833035a4..0c11beccf 100644
--- a/include/asm-arm/arch-arm1136/omap2420.h
+++ b/include/asm-arm/arch-arm1136/omap2420.h
@@ -77,6 +77,20 @@
 #define GPMC_CONFIG5_1        (OMAP2420_GPMC_BASE+0xA0)
 #define GPMC_CONFIG6_1        (OMAP2420_GPMC_BASE+0xA4)
 #define GPMC_CONFIG7_1	      (OMAP2420_GPMC_BASE+0xA8)
+#define GPMC_CONFIG1_2        (OMAP2420_GPMC_BASE+0xC0)
+#define GPMC_CONFIG2_2        (OMAP2420_GPMC_BASE+0xC4)
+#define GPMC_CONFIG3_2        (OMAP2420_GPMC_BASE+0xC8)
+#define GPMC_CONFIG4_2        (OMAP2420_GPMC_BASE+0xCC)
+#define GPMC_CONFIG5_2        (OMAP2420_GPMC_BASE+0xD0)
+#define GPMC_CONFIG6_2        (OMAP2420_GPMC_BASE+0xD4)
+#define GPMC_CONFIG7_2        (OMAP2420_GPMC_BASE+0xD8)
+#define GPMC_CONFIG1_3        (OMAP2420_GPMC_BASE+0xF0)
+#define GPMC_CONFIG2_3        (OMAP2420_GPMC_BASE+0xF4)
+#define GPMC_CONFIG3_3        (OMAP2420_GPMC_BASE+0xF8)
+#define GPMC_CONFIG4_3        (OMAP2420_GPMC_BASE+0xFC)
+#define GPMC_CONFIG5_3        (OMAP2420_GPMC_BASE+0x100)
+#define GPMC_CONFIG6_3        (OMAP2420_GPMC_BASE+0x104)
+#define GPMC_CONFIG7_3	      (OMAP2420_GPMC_BASE+0x108)
 
 /* SMS */
 #define OMAP2420_SMS_BASE 0x68008000
@@ -209,13 +223,24 @@
 #define SRAM_OFFSET2          0x0000F800
 #define SRAM_VECT_CODE       (SRAM_OFFSET0|SRAM_OFFSET1|SRAM_OFFSET2)
 
-#define LOW_LEVEL_SRAM_STACK  0x4020FFFC
-
-#define PERIFERAL_PORT_BASE   0x480FE003
-
 /* FPGA on Debug board.*/
 #define ETH_CONTROL_REG       (H4_CS1_BASE+0x30b)
 #define LAN_RESET_REGISTER    (H4_CS1_BASE+0x1c)
 #endif  /* endif CONFIG_2420H4 */
 
+#if defined(CONFIG_APOLLON)
+#define APOLLON_CS0_BASE	0x00000000	/* OneNAND */
+#define APOLLON_CS1_BASE	0x08000000	/* ethernet */
+#define APOLLON_CS2_BASE	0x10000000	/* OneNAND */
+#define APOLLON_CS3_BASE	0x18000000	/* NOR */
+
+#define ETH_CONTROL_REG		(APOLLON_CS1_BASE + 0x30b)
+#define LAN_RESET_REGISTER	(APOLLON_CS1_BASE + 0x1c)
+#endif	/* endif CONFIG_APOLLON */
+
+/* Common */
+#define LOW_LEVEL_SRAM_STACK  0x4020FFFC
+
+#define PERIFERAL_PORT_BASE   0x480FE003
+
 #endif
diff --git a/include/asm-arm/mach-types.h b/include/asm-arm/mach-types.h
index f6a5b4f16..ab19047d0 100644
--- a/include/asm-arm/mach-types.h
+++ b/include/asm-arm/mach-types.h
@@ -737,6 +737,7 @@ extern unsigned int __machine_arch_type;
 #define MACH_TYPE_CB3RUFC              726
 #define MACH_TYPE_MP2USB               727
 #define MACH_TYPE_AT91SAM9261EK        848
+#define MACH_TYPE_OMAP_APOLLON         919
 #define MACH_TYPE_PDNB3               1002
 #define MACH_TYPE_AT91SAM9260EK       1099
 #define MACH_TYPE_AT91RM9200DF        1119
@@ -6826,6 +6827,18 @@ extern unsigned int __machine_arch_type;
 # define machine_is_omap_h4()	(0)
 #endif
 
+#ifdef CONFIG_MACH_OMAP_APOLLON
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_OMAP_APOLLON
+# endif
+# define machine_is_omap_apollon()	(machine_arch_type == MACH_TYPE_OMAP_APOLLON)
+#else
+# define machine_is_omap_apollon()	(0)
+#endif
+
 #ifdef CONFIG_MACH_N10
 # ifdef machine_arch_type
 #  undef machine_arch_type
diff --git a/include/configs/apollon.h b/include/configs/apollon.h
new file mode 100644
index 000000000..578153c8b
--- /dev/null
+++ b/include/configs/apollon.h
@@ -0,0 +1,238 @@
+/*
+ * (C) Copyright 2005-2007
+ * Samsung Electronics,
+ * Kyungmin Park <kyungmin.park@samsung.com>
+ *
+ * Configuration settings for the 2420 Samsung Apollon board.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_ARM1136		1 /* This is an arm1136 CPU core */
+#define CONFIG_OMAP		1 /* in a TI OMAP core */
+#define CONFIG_OMAP2420		1 /* which is in a 2420 */
+#define CONFIG_OMAP2420_APOLLON	1
+#define CONFIG_APOLLON		1
+#define CONFIG_APOLLON_PLUS	1 /* If you have apollon plus 1.x */
+
+/* Clock config to target*/
+#define PRCM_CONFIG_I		1
+//#define PRCM_CONFIG_II	1
+
+/* Boot method */
+/* uncomment if you use NOR boot */
+//#define CFG_NOR_BOOT		1
+
+/* uncomment if you use NOR on CS3 */
+//#define CFG_USE_NOR		1
+
+#ifdef CFG_NOR_BOOT
+#undef CFG_USE_NOR
+#define CFG_USE_NOR		1
+#endif
+
+#include <asm/arch/omap2420.h>	/* get chip and board defs */
+
+#define	V_SCLK	12000000
+
+/* input clock of PLL */
+/* the OMAP2420 H4 has 12MHz, 13MHz, or 19.2Mhz crystal input */
+#define	CONFIG_SYS_CLK_FREQ	V_SCLK
+
+#undef	CONFIG_USE_IRQ	/* no support for IRQs */
+#define	CONFIG_MISC_INIT_R
+
+#define	CONFIG_CMDLINE_TAG	1	/* enable passing of ATAGs */
+#define	CONFIG_SETUP_MEMORY_TAGS	1
+#define	CONFIG_INITRD_TAG	1
+#define	CONFIG_REVISION_TAG	1
+
+/*
+ * Size of malloc() pool
+ */
+#define	CFG_ENV_SIZE SZ_128K	/* Total Size of Environment Sector */
+#define	CFG_MALLOC_LEN	(CFG_ENV_SIZE + SZ_128K)
+#define	CFG_GBL_DATA_SIZE	128	/* bytes reserved for initial data */
+
+/*
+ * Hardware drivers
+ */
+
+/*
+ * SMC91c96 Etherent
+ */
+#define	CONFIG_DRIVER_LAN91C96
+#define	CONFIG_LAN91C96_BASE	(APOLLON_CS1_BASE+0x300)
+#define	CONFIG_LAN91C96_EXT_PHY
+
+/*
+ * NS16550 Configuration
+ */
+#define	V_NS16550_CLK	(48000000)	/* 48MHz (APLL96/2) */
+
+#define	CFG_NS16550
+#define	CFG_NS16550_SERIAL
+#define	CFG_NS16550_REG_SIZE	(-4)
+#define	CFG_NS16550_CLK	V_NS16550_CLK	/* 3MHz (1.5MHz*2) */
+#define	CFG_NS16550_COM1	OMAP2420_UART1
+
+/*
+ * select serial console configuration
+ */
+#define	CONFIG_SERIAL1	1	/* UART1 on H4 */
+
+ /*
+ * I2C configuration
+ */
+#define	CONFIG_HARD_I2C
+#define	CFG_I2C_SPEED	100000
+#define	CFG_I2C_SLAVE	1
+#define	CONFIG_DRIVER_OMAP24XX_I2C
+
+/* allow to overwrite serial and ethaddr */ 
+#define	CONFIG_ENV_OVERWRITE
+#define	CONFIG_CONS_INDEX	1
+#define	CONFIG_BAUDRATE		115200
+#define	CFG_BAUDRATE_TABLE	{9600, 19200, 38400, 57600, 115200}
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ 
+#include	<config_cmd_default.h>
+
+#define	CONFIG_CMD_DHCP
+#define	CONFIG_CMD_DIAG
+#define	CONFIG_CMD_ONENAND
+
+#undef	CONFIG_CMD_AUTOSCRIPT
+
+#ifndef	CFG_USE_NOR
+# undef	CONFIG_CMD_FLASH
+# undef	CONFIG_CMD_IMLS
+#endif
+
+#define	CONFIG_BOOTP_MASK	CONFIG_BOOTP_DEFAULT
+
+#define	CONFIG_BOOTDELAY	1
+
+#define	CONFIG_NETMASK	255.255.255.0
+#define	CONFIG_IPADDR	192.168.116.25
+#define	CONFIG_SERVERIP	192.168.116.1
+#define	CONFIG_BOOTFILE	"uImage"
+#define	CONFIG_ETHADDR	00:0E:99:00:24:20
+
+#ifdef	CONFIG_APOLLON_PLUS
+# define	CONFIG_BOOTARGS "root=/dev/nfs rw mem=64M console=ttyS0,115200n8 ip=192.168.116.25:192.168.116.1:192.168.116.1:255.255.255.0:apollon:eth0:off nfsroot=/tftpboot/nfsroot profile=2"
+#else
+# define	CONFIG_BOOTARGS "root=/dev/nfs rw mem=128M console=ttyS0,115200n8 ip=192.168.116.25:192.168.116.1:192.168.116.1:255.255.255.0:apollon:eth0:off nfsroot=/tftpboot/nfsroot profile=2"
+#endif
+
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"Image=tftp 0x80008000 Image\; go 0x80008000\0"			\
+	"zImage=tftp 0x80180000 zImage\; go 0x80180000\0"		\
+	"uImage=tftp 0x80180000 uImage\; bootm 0x80180000\0"		\
+	"uboot=tftp 0x80008000 u-boot.bin\; go 0x80008000\0"		\
+	"xloader=tftp 0x80180000 x-load.bin\; cp.w 0x80180000 0x00000400 0x1000\; go 0x00000400\0"	\
+	"syncmode50=mw.w 0x1e442 0xc0c4\; mw 0x6800a060 0xe30d1201\0"	\
+	"syncmode=mw.w 0x1e442 0xe0f4\; mw 0x6800a060 0xe30d1201\0"	\
+	"norboot=cp32 0x18040000 0x80008000 0x200000\; go 0x80008000\0"	\
+	"oneboot=onenand read 0x80008000 0x40000 0x200000\; go 0x80008000\0"\
+	"onesyncboot=run syncmode oneboot\0"				\
+	"bootcmd=run uboot\0"
+
+/*
+ * Miscellaneous configurable options
+ */
+#define	V_PROMPT	"Apollon # "
+
+#define	CFG_LONGHELP	/* undef to save memory */
+#define	CFG_PROMPT	V_PROMPT
+#define	CFG_CBSIZE	256	/* Console I/O Buffer Size */
+/* Print Buffer Size */
+#define	CFG_PBSIZE	(CFG_CBSIZE+sizeof(CFG_PROMPT)+16)
+#define	CFG_MAXARGS	16	/* max number of command args */
+#define	CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size */
+
+#define	CFG_MEMTEST_START 	(OMAP2420_SDRC_CS0)	/* memtest works on */
+#define	CFG_MEMTEST_END		(OMAP2420_SDRC_CS0+SZ_31M)
+
+#undef	CFG_CLKS_IN_HZ	/* everything, incl board info, in Hz */
+
+#define	CFG_LOAD_ADDR	(OMAP2420_SDRC_CS0)	/* default load address */
+
+/* The 2420 has 12 GP timers, they can be driven by the SysClk (12/13/19.2) 
+ * or by 32KHz clk, or from external sig. This rate is divided by a local 
+ * divisor.
+ */
+#define	V_PVT	7	/* use with 12MHz/128 */
+
+#define	CFG_TIMERBASE	OMAP2420_GPT2
+#define	CFG_PVT	V_PVT	/* 2^(pvt+1) */
+#define	CFG_HZ		((CONFIG_SYS_CLK_FREQ)/(2 << CFG_PVT))
+
+/*-----------------------------------------------------------------------
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below 
+ */
+#define	CONFIG_STACKSIZE SZ_128K	/* regular stack */
+#ifdef	CONFIG_USE_IRQ
+# define	CONFIG_STACKSIZE_IRQ SZ_4K	/* IRQ stack */
+# define	CONFIG_STACKSIZE_FIQ SZ_4K	/* FIQ stack */
+#endif
+
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+#define	CONFIG_NR_DRAM_BANKS	1	/* CS1 may or may not be populated */
+#define	PHYS_SDRAM_1		OMAP2420_SDRC_CS0
+#define	PHYS_SDRAM_1_SIZE	SZ_128M
+#define	PHYS_SDRAM_2		OMAP2420_SDRC_CS1
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+#ifdef	CFG_USE_NOR
+/* OneNAND boot, NOR has CS3, But NOR has CS0 when NOR boot */
+# define	CFG_FLASH_BASE		0x18000000
+# define	CFG_MAX_FLASH_BANKS	1
+# define	CFG_MAX_FLASH_SECT	1024
+/*-----------------------------------------------------------------------
+
+ * CFI FLASH driver setup
+ */
+# define	CFG_FLASH_CFI	1	/* Flash memory is CFI compliant */
+# define	CFG_FLASH_CFI_DRIVER	1	/* Use drivers/cfi_flash.c */
+//#define CFG_FLASH_USE_BUFFER_WRITE 1 /* Use buffered writes (~10x faster) */
+# define	CFG_FLASH_PROTECTION	1	/* Use h/w sector protection*/
+
+#else	/* !CFG_USE_NOR */
+# define	CFG_NO_FLASH	1
+#endif	/* CFG_USE_NOR */
+
+/* OneNAND boot, OneNAND has CS0, NOR boot ONeNAND has CS2 */
+#define	CFG_ONENAND_BASE	0x00000000
+#define	CFG_ENV_IS_IN_ONENAND	1
+#define CFG_ENV_ADDR		0x00020000
+
+#endif /* __CONFIG_H */

From 1d8a49eca1c7bdc8db1c47a92f9014a29ead03ae Mon Sep 17 00:00:00 2001
From: Roy Zang <tie-fei.zang@freescale.com>
Date: Thu, 13 Sep 2007 18:52:28 +0800
Subject: [PATCH 014/108] Enable ULi1575 Ethernet support in 8610HPCD config

Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Acked-by: Jon Loeliger <jdl@freescale.com>
---
 include/configs/MPC8610HPCD.h | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/include/configs/MPC8610HPCD.h b/include/configs/MPC8610HPCD.h
index f5d9c098c..ef1310f60 100644
--- a/include/configs/MPC8610HPCD.h
+++ b/include/configs/MPC8610HPCD.h
@@ -312,16 +312,16 @@
 #define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
 
 #define CONFIG_NET_MULTI
+#define CONFIG_CMD_NET
 #define CONFIG_PCI_PNP		/* do pci plug-and-play */
 
-#if 0 /* TODO */
-/* enable onboard uli network support */
-#endif
-
 #define CONFIG_RTL8139
 #define CONFIG_SK98
 #define CONFIG_EEPRO100
 #define CONFIG_TULIP
+#ifdef CONFIG_TULIP
+#define CONFIG_ETHADDR   00:E0:0C:00:00:01
+#endif
 
 /************************************************************
  * USB support

From 2db916e14410e3ec1738508c7bf4dfeb2b299ae7 Mon Sep 17 00:00:00 2001
From: Peter Pearse <peter.pearse@arm.com>
Date: Thu, 15 Nov 2007 08:45:13 +0000
Subject: [PATCH 015/108] Correction patch

---
 board/apollon/apollon.c            | 468 ++++++++++-------------------
 board/apollon/lowlevel_init.S      |  18 +-
 board/apollon/mem.c                |  43 +--
 board/apollon/mem.h                |  16 +-
 board/apollon/sys_info.c           |  31 +-
 board/apollon/u-boot.lds           |   3 +-
 include/asm-arm/arch-arm1136/mux.h |  18 +-
 7 files changed, 239 insertions(+), 358 deletions(-)

diff --git a/board/apollon/apollon.c b/board/apollon/apollon.c
index e2c627725..064d143ae 100644
--- a/board/apollon/apollon.c
+++ b/board/apollon/apollon.c
@@ -31,18 +31,32 @@
 #include <asm/arch/sys_proto.h>
 #include <asm/arch/sys_info.h>
 #include <asm/arch/mem.h>
-#include <i2c.h>
 #include <asm/mach-types.h>
 
 void wait_for_command_complete(unsigned int wd_base);
 
+DECLARE_GLOBAL_DATA_PTR;
+
+#define write_config_reg(reg, value)					\
+do {									\
+	writeb(value, reg);						\
+} while (0)
+
+#define mask_config_reg(reg, mask)					\
+do {									\
+	char value = readb(reg) & ~(mask);				\
+	writeb(value, reg);						\
+} while (0)
+
 /*******************************************************
  * Routine: delay
  * Description: spinning delay to use before udelay works
-******************************************************/
-static inline void delay(unsigned long loops) {
-	__asm__ volatile ("1:\n" "subs %0, %1, #1\n"
-			  "bne 1b":"=r" (loops):"0"(loops)); }
+ ******************************************************/
+static inline void delay(unsigned long loops)
+{
+	__asm__("1:\n" "subs %0, %1, #1\n"
+		  "bne 1b":"=r" (loops):"0"(loops));
+}
 
 /*****************************************
  * Routine: board_init
@@ -50,8 +64,6 @@ static inline void delay(unsigned long loops) {
  *****************************************/
 int board_init(void)
 {
-	DECLARE_GLOBAL_DATA_PTR;
-
 	gpmc_init();		/* in SRAM or SDRM, finish GPMC */
 
 	gd->bd->bi_arch_number = 919;
@@ -68,7 +80,6 @@ int board_init(void)
  **********************************************************/
 void s_init(void)
 {
-
 	watchdog_init();
 	set_muxconf_regs();
 	delay(100);
@@ -80,7 +91,7 @@ void s_init(void)
 /*******************************************************
  * Routine: misc_init_r
  * Description: Init ethernet (done here so udelay works)
-********************************************************/
+ ********************************************************/
 int misc_init_r(void)
 {
 	ether_init();		/* better done here so timers are init'ed */
@@ -102,22 +113,24 @@ void watchdog_init(void)
 	__raw_writel(WD_UNLOCK2, WD2_BASE + WSPR);
 
 #define MPU_WD_CLOCKED 1
-#if MPU_WD_CLOCKED		/* value 0x10 stick on aptix, BIT4 polarity seems oppsite */
+#if MPU_WD_CLOCKED
+	/* value 0x10 stick on aptix, BIT4 polarity seems oppsite */
 	__raw_writel(WD_UNLOCK1, WD3_BASE + WSPR);
 	wait_for_command_complete(WD3_BASE);
 	__raw_writel(WD_UNLOCK2, WD3_BASE + WSPR);
 
 	__raw_writel(WD_UNLOCK1, WD4_BASE + WSPR);
 	wait_for_command_complete(WD4_BASE);
-	__raw_writel(WD_UNLOCK2, WD4_BASE + WSPR); 
-#endif 
+	__raw_writel(WD_UNLOCK2, WD4_BASE + WSPR);
+#endif
 }
 
 /******************************************************
  * Routine: wait_for_command_complete
  * Description: Wait for posting to finish on watchdog
-******************************************************/
-void wait_for_command_complete(unsigned int wd_base) {
+ ******************************************************/
+void wait_for_command_complete(unsigned int wd_base)
+{
 	int pending = 1;
 	do {
 		pending = __raw_readl(wd_base + WWPS);
@@ -160,7 +173,7 @@ void ether_init(void)
 	} while (__raw_readw(LAN_RESET_REGISTER) != 0x0000);
 	udelay(1000);
 
-	*((volatile unsigned char *)ETH_CONTROL_REG) &= ~0x01;
+	mask_config_reg(ETH_CONTROL_REG, 0x01);
 	udelay(1000);
 
 eth_reset_err_out:
@@ -171,10 +184,9 @@ eth_reset_err_out:
 /**********************************************
  * Routine: dram_init
  * Description: sets uboots idea of sdram size
-**********************************************/
+ **********************************************/
 int dram_init(void)
 {
-	DECLARE_GLOBAL_DATA_PTR;
 	unsigned int size0 = 0, size1 = 0;
 	u32 mtype, btype, rev = 0, cpu = 0;
 #define NOT_EARLY 0
@@ -187,8 +199,8 @@ int dram_init(void)
 	display_board_info(btype);
 
 	if ((mtype == DDR_COMBO) || (mtype == DDR_STACKED)) {
-		printf("ddr combo\n");
-		do_sdrc_init(SDRC_CS1_OSET, NOT_EARLY);	/* init other chip select */
+		/* init other chip select */
+		do_sdrc_init(SDRC_CS1_OSET, NOT_EARLY);
 	}
 
 	size0 = get_sdr_cs_size(SDRC_CS0_OSET);
@@ -224,7 +236,7 @@ void set_muxconf_regs(void)
 /*****************************************************************
  * Routine: peripheral_enable
  * Description: Enable the clks & power for perifs (GPT2, UART1,...)
-******************************************************************/
+ ******************************************************************/
 void peripheral_enable(void)
 {
 	unsigned int v, if_clks = 0, func_clks = 0;
@@ -232,7 +244,8 @@ void peripheral_enable(void)
 	/* Enable GP2 timer. */
 	if_clks |= BIT4 | BIT3;
 	func_clks |= BIT4 | BIT3;
-	v = __raw_readl(CM_CLKSEL2_CORE) | 0x4 | 0x2;	/* Sys_clk input OMAP2420_GPT2 */
+	/* Sys_clk input OMAP2420_GPT2 */
+	v = __raw_readl(CM_CLKSEL2_CORE) | 0x4 | 0x2;
 	__raw_writel(v, CM_CLKSEL2_CORE);
 	__raw_writel(0x1, CM_CLKSEL_WKUP);
 
@@ -241,9 +254,11 @@ void peripheral_enable(void)
 	func_clks |= BIT21;
 	if_clks |= BIT21;
 #endif
-	v = __raw_readl(CM_ICLKEN1_CORE) | if_clks;	/* Interface clocks on */
+	/* Interface clocks on */
+	v = __raw_readl(CM_ICLKEN1_CORE) | if_clks;
 	__raw_writel(v, CM_ICLKEN1_CORE);
-	v = __raw_readl(CM_FCLKEN1_CORE) | func_clks;	/* Functional Clocks on */
+	/* Functional Clocks on */
+	v = __raw_readl(CM_FCLKEN1_CORE) | func_clks;
 	__raw_writel(v, CM_FCLKEN1_CORE);
 	delay(1000);
 
@@ -261,199 +276,110 @@ void peripheral_enable(void)
 }
 
 /****************************************
- * Routine: muxSetupUsb0 (ostboot)
+ * Routine: muxSetupUsb0   (ostboot)
  * Description: Setup usb muxing
  *****************************************/
 void muxSetupUsb0(void)
 {
-	volatile uint8 *MuxConfigReg;
-
-	MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_USB0_PUEN;
-	*MuxConfigReg &= (uint8) (~0x1F);
-
-	MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_USB0_VP;
-	*MuxConfigReg &= (uint8) (~0x1F);
-
-	MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_USB0_VM;
-	*MuxConfigReg &= (uint8) (~0x1F);
-
-	MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_USB0_RCV;
-	*MuxConfigReg &= (uint8) (~0x1F);
-
-	MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_USB0_TXEN;
-	*MuxConfigReg &= (uint8) (~0x1F);
-
-	MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_USB0_SE0;
-	*MuxConfigReg &= (uint8) (~0x1F);
-
-	MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_USB0_DAT;
-	*MuxConfigReg &= (uint8) (~0x1F);
+	mask_config_reg(CONTROL_PADCONF_USB0_PUEN, 0x1f);
+	mask_config_reg(CONTROL_PADCONF_USB0_VP, 0x1f);
+	mask_config_reg(CONTROL_PADCONF_USB0_VM, 0x1f);
+	mask_config_reg(CONTROL_PADCONF_USB0_RCV, 0x1f);
+	mask_config_reg(CONTROL_PADCONF_USB0_TXEN, 0x1f);
+	mask_config_reg(CONTROL_PADCONF_USB0_SE0, 0x1f);
+	mask_config_reg(CONTROL_PADCONF_USB0_DAT, 0x1f);
 }
 
-#define CONTROL_PADCONF_USB1_RCV	((volatile uint8 *)0x480000EB)
-#define CONTROL_PADCONF_USB1_TXEN	((volatile uint8 *)0x480000EC)
-#define CONTROL_PADCONF_GPIO69		((volatile uint8 *)0x480000ED)
-#define CONTROL_PADCONF_GPIO70		((volatile uint8 *)0x480000EE)
-
-#define CONTROL_PADCONF_GPIO102		((volatile uint8 *)0x48000116)
-#define CONTROL_PADCONF_GPIO103		((volatile uint8 *)0x48000117)
-#define CONTROL_PADCONF_GPIO104		((volatile uint8 *)0x48000118)
-#define CONTROL_PADCONF_GPIO105		((volatile uint8 *)0x48000119)
 /****************************************
- * Routine: muxSetupUSBHost (ostboot)
+ * Routine: muxSetupUSBHost   (ostboot)
  * Description: Setup USB Host muxing
  *****************************************/
 void muxSetupUsbHost(void)
 {
-	volatile uint8 *MuxConfigReg;
-
 	/* V19 */
-	MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_USB1_RCV;
-	*MuxConfigReg = 1;
+	write_config_reg(CONTROL_PADCONF_USB1_RCV, 1);
 	/* W20 */
-	MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_USB1_TXEN;
-	*MuxConfigReg = 1;
+	write_config_reg(CONTROL_PADCONF_USB1_TXEN, 1);
 	/* N14 */
-	MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_GPIO69;
-	*MuxConfigReg = 3;
+	write_config_reg(CONTROL_PADCONF_GPIO69, 3);
 	/* P15 */
-	MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_GPIO70;
-	*MuxConfigReg = 3;
-
+	write_config_reg(CONTROL_PADCONF_GPIO70, 3);
 	/* L18 */
-	MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_GPIO102;
-	*MuxConfigReg = 3;
+	write_config_reg(CONTROL_PADCONF_GPIO102, 3);
 	/* L19 */
-	MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_GPIO103;
-	*MuxConfigReg = 3;
+	write_config_reg(CONTROL_PADCONF_GPIO103, 3);
 	/* K15 */
-	MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_GPIO104;
-	*MuxConfigReg = 3;
+	write_config_reg(CONTROL_PADCONF_GPIO104, 3);
 	/* K14 */
-	MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_GPIO105;
-	*MuxConfigReg = 3;
+	write_config_reg(CONTROL_PADCONF_GPIO105, 3);
 }
 
 /****************************************
- * Routine: muxSetupUART1 (ostboot)
+ * Routine: muxSetupUART1  (ostboot)
  * Description: Set up uart1 muxing
  *****************************************/
 void muxSetupUART1(void)
 {
-	volatile unsigned char *MuxConfigReg;
-
-	/* UART1_CTS pin configuration, PIN = D21 */
-	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_UART1_CTS;
-	*MuxConfigReg = 0x00;	/* Mode = 0, PUPD=Disabled */
-
-	/* UART1_RTS pin configuration, PIN = H21 */
-	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_UART1_RTS;
-	*MuxConfigReg = 0x00;	/* Mode = 0, PUPD=Disabled */
-
-	/* UART1_TX pin configuration, PIN = L20 */
-	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_UART1_TX;
-	*MuxConfigReg = 0x00;	/* Mode = 0, PUPD=Disabled */
-
-	/* UART1_RX pin configuration, PIN = T21 */
-	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_UART1_RX;
-	*MuxConfigReg = 0x00;	/* Mode = 0, PUPD=Disabled */
+	/* UART1_CTS pin configuration, PIN = D21, Mode = 0, PUPD=Disabled */
+	write_config_reg(CONTROL_PADCONF_UART1_CTS, 0);
+	/* UART1_RTS pin configuration, PIN = H21, Mode = 0, PUPD=Disabled */
+	write_config_reg(CONTROL_PADCONF_UART1_RTS, 0);
+	/* UART1_TX pin configuration, PIN = L20, Mode = 0, PUPD=Disabled */
+	write_config_reg(CONTROL_PADCONF_UART1_TX, 0);
+	/* UART1_RX pin configuration, PIN = T21, Mode = 0, PUPD=Disabled */
+	write_config_reg(CONTROL_PADCONF_UART1_RX, 0);
 }
 
 /****************************************
- * Routine: muxSetupLCD (ostboot)
+ * Routine: muxSetupLCD   (ostboot)
  * Description: Setup lcd muxing
  *****************************************/
 void muxSetupLCD(void)
 {
-	volatile unsigned char *MuxConfigReg;
-
-	/* LCD_D0 pin configuration, PIN = Y7 */
-	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D0;
-	*MuxConfigReg = 0x00;	/* Mode = 0, PUPD=Disabled */
-
-	/* LCD_D1 pin configuration, PIN = P10 */
-	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D1;
-	*MuxConfigReg = 0x00;	/* Mode = 0, PUPD=Disabled */
-
-	/* LCD_D2 pin configuration, PIN = V8 */
-	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D2;
-	*MuxConfigReg = 0x00;	/* Mode = 0, PUPD=Disabled */
-
-	/* LCD_D3 pin configuration, PIN = Y8 */
-	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D3;
-	*MuxConfigReg = 0x00;	/* Mode = 0, PUPD=Disabled */
-
-	/* LCD_D4 pin configuration, PIN = W8 */
-	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D4;
-	*MuxConfigReg = 0x00;	/* Mode = 0, PUPD=Disabled */
-
-	/* LCD_D5 pin configuration, PIN = R10 */
-	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D5;
-	*MuxConfigReg = 0x00;	/* Mode = 0, PUPD=Disabled */
-
-	/* LCD_D6 pin configuration, PIN = Y9 */
-	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D6;
-	*MuxConfigReg = 0x00;	/* Mode = 0, PUPD=Disabled */
-
-	/* LCD_D7 pin configuration, PIN = V9 */
-	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D7;
-	*MuxConfigReg = 0x00;	/* Mode = 0, PUPD=Disabled */
-
-	/* LCD_D8 pin configuration, PIN = W9 */
-	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D8;
-	*MuxConfigReg = 0x00;	/* Mode = 0, PUPD=Disabled */
-
-	/* LCD_D9 pin configuration, PIN = P11 */
-	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D9;
-	*MuxConfigReg = 0x00;	/* Mode = 0, PUPD=Disabled */
-
-	/* LCD_D10 pin configuration, PIN = V10 */
-	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D10;
-	*MuxConfigReg = 0x00;	/* Mode = 0, PUPD=Disabled */
-
-	/* LCD_D11 pin configuration, PIN = Y10 */
-	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D11;
-	*MuxConfigReg = 0x00;	/* Mode = 0, PUPD=Disabled */
-
-	/* LCD_D12 pin configuration, PIN = W10 */
-	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D12;
-	*MuxConfigReg = 0x00;	/* Mode = 0, PUPD=Disabled */
-
-	/* LCD_D13 pin configuration, PIN = R11 */
-	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D13;
-	*MuxConfigReg = 0x00;	/* Mode = 0, PUPD=Disabled */
-
-	/* LCD_D14 pin configuration, PIN = V11 */
-	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D14;
-	*MuxConfigReg = 0x00;	/* Mode = 0, PUPD=Disabled */
-
-	/* LCD_D15 pin configuration, PIN = W11 */
-	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D15;
-	*MuxConfigReg = 0x00;	/* Mode = 0, PUPD=Disabled */
-
-	/* LCD_D16 pin configuration, PIN = P12 */
-	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D16;
-	*MuxConfigReg = 0x00;	/* Mode = 0, PUPD=Disabled */
-
-	/* LCD_D17 pin configuration, PIN = R12 */
-	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D17;
-	*MuxConfigReg = 0x00;	/* Mode = 0, PUPD=Disabled */
-
-	/* LCD_PCLK pin configuration, PIN = W6 */
-	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_PCLK;
-	*MuxConfigReg = 0x00;	/* Mode = 0, PUPD=Disabled */
-
-	/* LCD_VSYNC pin configuration, PIN = V7 */
-	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_VSYNC;
-	*MuxConfigReg = 0x00;	/* Mode = 0, PUPD=Disabled */
-
-	/* LCD_HSYNC pin configuration, PIN = Y6 */
-	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_HSYNC;
-	*MuxConfigReg = 0x00;	/* Mode = 0, PUPD=Disabled */
-
-	/* LCD_ACBIAS pin configuration, PIN = W7 */
-	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_ACBIAS;
-	*MuxConfigReg = 0x00;	/* Mode = 0, PUPD=Disabled */
+	/* LCD_D0 pin configuration, PIN = Y7, Mode = 0, PUPD=Disabled */
+	write_config_reg(CONTROL_PADCONF_DSS_D0, 0);
+	/* LCD_D1 pin configuration, PIN = P10 , Mode = 0, PUPD=Disabled */
+	write_config_reg(CONTROL_PADCONF_DSS_D1, 0);
+	/* LCD_D2 pin configuration, PIN = V8, Mode = 0, PUPD=Disabled */
+	write_config_reg(CONTROL_PADCONF_DSS_D2, 0);
+	/* LCD_D3 pin configuration, PIN = Y8, Mode = 0, PUPD=Disabled */
+	write_config_reg(CONTROL_PADCONF_DSS_D3, 0);
+	/* LCD_D4 pin configuration, PIN = W8, Mode = 0, PUPD=Disabled */
+	write_config_reg(CONTROL_PADCONF_DSS_D4, 0);
+	/* LCD_D5 pin configuration, PIN = R10, Mode = 0, PUPD=Disabled */
+	write_config_reg(CONTROL_PADCONF_DSS_D5, 0);
+	/* LCD_D6 pin configuration, PIN = Y9, Mode = 0, PUPD=Disabled */
+	write_config_reg(CONTROL_PADCONF_DSS_D6, 0);
+	/* LCD_D7 pin configuration, PIN = V9, Mode = 0, PUPD=Disabled */
+	write_config_reg(CONTROL_PADCONF_DSS_D7, 0);
+	/* LCD_D8 pin configuration, PIN = W9, Mode = 0, PUPD=Disabled */
+	write_config_reg(CONTROL_PADCONF_DSS_D8, 0);
+	/* LCD_D9 pin configuration, PIN = P11, Mode = 0, PUPD=Disabled */
+	write_config_reg(CONTROL_PADCONF_DSS_D9, 0);
+	/* LCD_D10 pin configuration, PIN = V10, Mode = 0, PUPD=Disabled */
+	write_config_reg(CONTROL_PADCONF_DSS_D10, 0);
+	/* LCD_D11 pin configuration, PIN = Y10, Mode = 0, PUPD=Disabled */
+	write_config_reg(CONTROL_PADCONF_DSS_D11, 0);
+	/* LCD_D12 pin configuration, PIN = W10, Mode = 0, PUPD=Disabled */
+	write_config_reg(CONTROL_PADCONF_DSS_D12, 0);
+	/* LCD_D13 pin configuration, PIN = R11, Mode = 0, PUPD=Disabled */
+	write_config_reg(CONTROL_PADCONF_DSS_D13, 0);
+	/* LCD_D14 pin configuration, PIN = V11, Mode = 0, PUPD=Disabled */
+	write_config_reg(CONTROL_PADCONF_DSS_D14, 0);
+	/* LCD_D15 pin configuration, PIN = W11, Mode = 0, PUPD=Disabled */
+	write_config_reg(CONTROL_PADCONF_DSS_D15, 0);
+	/* LCD_D16 pin configuration, PIN = P12, Mode = 0, PUPD=Disabled */
+	write_config_reg(CONTROL_PADCONF_DSS_D16, 0);
+	/* LCD_D17 pin configuration, PIN = R12, Mode = 0, PUPD=Disabled */
+	write_config_reg(CONTROL_PADCONF_DSS_D17, 0);
+	/* LCD_PCLK pin configuration, PIN = W6, Mode = 0, PUPD=Disabled */
+	write_config_reg(CONTROL_PADCONF_DSS_PCLK, 0);
+	/* LCD_VSYNC pin configuration, PIN = V7, Mode = 0, PUPD=Disabled */
+	write_config_reg(CONTROL_PADCONF_DSS_VSYNC, 0);
+	/* LCD_HSYNC pin configuration, PIN = Y6, Mode = 0, PUPD=Disabled */
+	write_config_reg(CONTROL_PADCONF_DSS_HSYNC, 0);
+	/* LCD_ACBIAS pin configuration, PIN = W7, Mode = 0, PUPD=Disabled */
+	write_config_reg(CONTROL_PADCONF_DSS_ACBIAS, 0);
 }
 
 /****************************************
@@ -462,146 +388,84 @@ void muxSetupLCD(void)
  *****************************************/
 void muxSetupMMCSD(void)
 {
-	volatile unsigned char *MuxConfigReg;
-
-	/* SDMMC_CLKI pin configuration, PIN = H15 */
-	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_CLKI;
-	*MuxConfigReg = 0x00;	/* Mode = 0, PUPD=Disabled */
-
-	/* SDMMC_CLKO pin configuration, PIN = G19 */
-	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_CLKO;
-	*MuxConfigReg = 0x00;	/* Mode = 0, PUPD=Disabled */
-
-	/* SDMMC_CMD pin configuration, PIN = H18 */
-	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_CMD;
-	*MuxConfigReg = 0x00;	/* Mode = 0, PUPD=Disabled */
-	/* External pull-ups are present. */
-	/* *MuxConfigReg |= 0x18 ; #/ PullUDEnable=Enabled, PullTypeSel=PU */
-
-	/* SDMMC_DAT0 pin configuration, PIN = F20 */
-	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT0;
-	*MuxConfigReg = 0x00;	/* Mode = 0, PUPD=Disabled */
-	/* External pull-ups are present. */
-	/* *MuxConfigReg |= 0x18 ; #/ PullUDEnable=Enabled, PullTypeSel=PU */
-
-	/* SDMMC_DAT1 pin configuration, PIN = H14 */
-	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT1;
-	*MuxConfigReg = 0x00;	/* Mode = 0, PUPD=Disabled */
-	/* External pull-ups are present. */
-	/* *MuxConfigReg |= 0x18 ; #/ PullUDEnable=Enabled, PullTypeSel=PU */
-
-	/* SDMMC_DAT2 pin configuration, PIN = E19 */
-	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT2;
-	*MuxConfigReg = 0x00;	/* Mode = 0, PUPD=Disabled */
-	/* External pull-ups are present. */
-	/* *MuxConfigReg |= 0x18 ; #/ PullUDEnable=Enabled, PullTypeSel=PU */
-
-	/* SDMMC_DAT3 pin configuration, PIN = D19 */
-	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT3;
-	*MuxConfigReg = 0x00;	/* Mode = 0, PUPD=Disabled */
-	/* External pull-ups are present. */
-	/* *MuxConfigReg |= 0x18 ; #/ PullUDEnable=Enabled, PullTypeSel=PU */
-
-	/* SDMMC_DDIR0 pin configuration, PIN = F19 */
-	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT_DIR0;
-	*MuxConfigReg = 0x00;	/* Mode = 0, PUPD=Disabled */
-
-	/* SDMMC_DDIR1 pin configuration, PIN = E20 */
-	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT_DIR1;
-	*MuxConfigReg = 0x00;	/* Mode = 0, PUPD=Disabled */
-
-	/* SDMMC_DDIR2 pin configuration, PIN = F18 */
-	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT_DIR2;
-	*MuxConfigReg = 0x00;	/* Mode = 0, PUPD=Disabled */
-
-	/* SDMMC_DDIR3 pin configuration, PIN = E18 */
-	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT_DIR3;
-	*MuxConfigReg = 0x00;	/* Mode = 0, PUPD=Disabled */
-
-	/* SDMMC_CDIR pin configuration, PIN = G18 */
-	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_CMD_DIR;
-	*MuxConfigReg = 0x00;	/* Mode = 0, PUPD=Disabled */
+	/* SDMMC_CLKI pin configuration,  PIN = H15, Mode = 0, PUPD=Disabled */
+	write_config_reg(CONTROL_PADCONF_MMC_CLKI, 0);
+	/* SDMMC_CLKO pin configuration,  PIN = G19, Mode = 0, PUPD=Disabled */
+	write_config_reg(CONTROL_PADCONF_MMC_CLKO, 0);
+	/* SDMMC_CMD pin configuration,   PIN = H18, Mode = 0, PUPD=Disabled */
+	write_config_reg(CONTROL_PADCONF_MMC_CMD, 0);
+	/* SDMMC_DAT0 pin configuration,  PIN = F20, Mode = 0, PUPD=Disabled */
+	write_config_reg(CONTROL_PADCONF_MMC_DAT0, 0);
+	/* SDMMC_DAT1 pin configuration,  PIN = H14, Mode = 0, PUPD=Disabled */
+	write_config_reg(CONTROL_PADCONF_MMC_DAT1, 0);
+	/* SDMMC_DAT2 pin configuration,  PIN = E19, Mode = 0, PUPD=Disabled */
+	write_config_reg(CONTROL_PADCONF_MMC_DAT2, 0);
+	/* SDMMC_DAT3 pin configuration,  PIN = D19, Mode = 0, PUPD=Disabled */
+	write_config_reg(CONTROL_PADCONF_MMC_DAT3, 0);
+	/* SDMMC_DDIR0 pin configuration, PIN = F19, Mode = 0, PUPD=Disabled */
+	write_config_reg(CONTROL_PADCONF_MMC_DAT_DIR0, 0);
+	/* SDMMC_DDIR1 pin configuration, PIN = E20, Mode = 0, PUPD=Disabled */
+	write_config_reg(CONTROL_PADCONF_MMC_DAT_DIR1, 0);
+	/* SDMMC_DDIR2 pin configuration, PIN = F18, Mode = 0, PUPD=Disabled */
+	write_config_reg(CONTROL_PADCONF_MMC_DAT_DIR2, 0);
+	/* SDMMC_DDIR3 pin configuration, PIN = E18, Mode = 0, PUPD=Disabled */
+	write_config_reg(CONTROL_PADCONF_MMC_DAT_DIR3, 0);
+	/* SDMMC_CDIR pin configuration,  PIN = G18, Mode = 0, PUPD=Disabled */
+	write_config_reg(CONTROL_PADCONF_MMC_CMD_DIR, 0);
 }
 
 /******************************************
  * Routine: muxSetupTouchScreen (ostboot)
- * Description: Set up touch screen muxing
-*******************************************/
+ * Description:  Set up touch screen muxing
+ *******************************************/
 void muxSetupTouchScreen(void)
 {
-	volatile unsigned char *MuxConfigReg;
-
-	/* SPI1_CLK pin configuration, PIN = U18 */
-	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_SPI1_CLK;
-	*MuxConfigReg = 0x00;	/* Mode = 0, PUPD=Disabled */
-
-	/* SPI1_MOSI pin configuration, PIN = V20 */
-	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_SPI1_SIMO;
-	*MuxConfigReg = 0x00;	/* Mode = 0, PUPD=Disabled */
-
-	/* SPI1_MISO pin configuration, PIN = T18 */
-	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_SPI1_SOMI;
-	*MuxConfigReg = 0x00;	/* Mode = 0, PUPD=Disabled */
-
-	/* SPI1_nCS0 pin configuration, PIN = U19 */
-	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_SPI1_NCS0;
-	*MuxConfigReg = 0x00;	/* Mode = 0, PUPD=Disabled */
-
+	/* SPI1_CLK pin configuration,  PIN = U18, Mode = 0, PUPD=Disabled */
+	write_config_reg(CONTROL_PADCONF_SPI1_CLK, 0);
+	/* SPI1_MOSI pin configuration, PIN = V20, Mode = 0, PUPD=Disabled */
+	write_config_reg(CONTROL_PADCONF_SPI1_SIMO, 0);
+	/* SPI1_MISO pin configuration, PIN = T18, Mode = 0, PUPD=Disabled */
+	write_config_reg(CONTROL_PADCONF_SPI1_SOMI, 0);
+	/* SPI1_nCS0 pin configuration, PIN = U19, Mode = 0, PUPD=Disabled */
+	write_config_reg(CONTROL_PADCONF_SPI1_NCS0, 0);
 #define CONTROL_PADCONF_GPIO85	CONTROL_PADCONF_SPI1_NCS1
-
-	/* PEN_IRQ pin configuration, PIN = N15 */
-	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_GPIO85;
-	*MuxConfigReg = 0x03;	/* Mode = 3, PUPD=Disabled */
+	/* PEN_IRQ pin configuration,   PIN = N15, Mode = 3, PUPD=Disabled */
+	write_config_reg(CONTROL_PADCONF_GPIO85, 3);
 }
 
 /***************************************************************
  * Routine: muxSetupGPMC (ostboot)
  * Description: Configures balls which cam up in protected mode
-***************************************************************/
+ ***************************************************************/
 void muxSetupGPMC(void)
 {
-	volatile uint8 *MuxConfigReg;
-	volatile unsigned int *MCR = (volatile unsigned int *)0x4800008C;
-
-	/* gpmc_io_dir */
-	*MCR = 0x19000000;
+	/* gpmc_io_dir, MCR */
+	writel(0x4800008C, 0x19000000);
 
 	/* NOR FLASH CS0 */
-	/* signal - Gpmc_clk;
-		pin - J4; offset - 0x0088; mode - 0; Byte-3  Pull/up - N/A */
-	MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_GPMC_D2_BYTE3;
-	*MuxConfigReg = 0x00;
-
+	/* signal - Gpmc_clk; pin - J4; offset - 0x0088; mode 0; Byte-3 */
+	write_config_reg(CONTROL_PADCONF_GPMC_D2_BYTE3, 0);
 	/* MPDB(Multi Port Debug Port) CS1 */
-	/* signal - gpmc_ncs1;
-		pin - N8; offset - 0x008C; mode - 0; Byte-1 Pull/up - N/A */
-	MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_GPMC_NCS0_BYTE1;
-	*MuxConfigReg = 0x00;
-
-	/* signal - Gpmc_ncs2;
-		pin - E2; offset - 0x008C; mode - 0; Byte-2 Pull/up - N/A */
-	MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_GPMC_NCS0_BYTE2;
-	*MuxConfigReg = 0x00;
-
-	/* signal - Gpmc_ncs3;
-		pin - N2; offset - 0x008C; mode - 0; Byte-3 Pull/up - N/A */
-	MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_GPMC_NCS0_BYTE3;
-	*MuxConfigReg = 0x00;
-
-	MuxConfigReg = (volatile uint8 *)((volatile unsigned char *)0x48000090);
-	*MuxConfigReg = 0x00;
-	MuxConfigReg = (volatile uint8 *)((volatile unsigned char *)0x48000091);
-	*MuxConfigReg = 0x00;
-	MuxConfigReg = (volatile uint8 *)((volatile unsigned char *)0x48000092);
-	*MuxConfigReg = 0x00;
-	MuxConfigReg = (volatile uint8 *)((volatile unsigned char *)0x48000093);
-	*MuxConfigReg = 0x00;
+	/* signal - gpmc_ncs1; pin - N8; offset - 0x008D; mode 0; Byte-1 */
+	write_config_reg(CONTROL_PADCONF_GPMC_NCS0_BYTE1, 0);
+	/* signal - Gpmc_ncs2; pin - E2; offset - 0x008E; mode 0; Byte-2 */
+	write_config_reg(CONTROL_PADCONF_GPMC_NCS0_BYTE2, 0);
+	/* signal - Gpmc_ncs3; pin - N2; offset - 0x008F; mode 0; Byte-3 */
+	write_config_reg(CONTROL_PADCONF_GPMC_NCS0_BYTE3, 0);
+	/* signal - Gpmc_ncs4; pin - ??; offset - 0x0090; mode 0; Byte-4 */
+	write_config_reg(CONTROL_PADCONF_GPMC_NCS0_BYTE4, 0);
+	/* signal - Gpmc_ncs5; pin - ??; offset - 0x0091; mode 0; Byte-5 */
+	write_config_reg(CONTROL_PADCONF_GPMC_NCS0_BYTE5, 0);
+	/* signal - Gpmc_ncs6; pin - ??; offset - 0x0092; mode 0; Byte-6 */
+	write_config_reg(CONTROL_PADCONF_GPMC_NCS0_BYTE6, 0);
+	/* signal - Gpmc_ncs7; pin - ??; offset - 0x0093; mode 0; Byte-7 */
+	write_config_reg(CONTROL_PADCONF_GPMC_NCS0_BYTE7, 0);
 }
 
 /****************************************************************
- * Routine: muxSetupSDRC (ostboot)
+ * Routine: muxSetupSDRC  (ostboot)
  * Description: Configures balls which come up in protected mode
-****************************************************************/
+ ****************************************************************/
 void muxSetupSDRC(void)
 {
 	/* It's set by IPL */
diff --git a/board/apollon/lowlevel_init.S b/board/apollon/lowlevel_init.S
index 76762599b..f254428c9 100644
--- a/board/apollon/lowlevel_init.S
+++ b/board/apollon/lowlevel_init.S
@@ -34,13 +34,13 @@
 #define APOLLON_CS0_BASE        0x00000000
 
 #ifdef PRCM_CONFIG_I
-# define SDRC_ACTIM_CTRLA_0_VAL  0x7BA35907
-# define SDRC_ACTIM_CTRLB_0_VAL  0x00000013
-# define SDRC_RFR_CTRL_0_VAL     0x00044C01
+#define SDRC_ACTIM_CTRLA_0_VAL  0x7BA35907
+#define SDRC_ACTIM_CTRLB_0_VAL  0x00000013
+#define SDRC_RFR_CTRL_0_VAL     0x00044C01
 #elif defined(PRCM_CONFIG_II)
-# define SDRC_ACTIM_CTRLA_0_VAL  0x4A59B485
-# define SDRC_ACTIM_CTRLB_0_VAL  0x0000000C
-# define SDRC_RFR_CTRL_0_VAL     0x00030001
+#define SDRC_ACTIM_CTRLA_0_VAL  0x4A59B485
+#define SDRC_ACTIM_CTRLB_0_VAL  0x0000000C
+#define SDRC_RFR_CTRL_0_VAL     0x00030001
 #endif
 
 #define SDRAM_BASE_ADDRESS	0x80008000
@@ -56,7 +56,7 @@ lowlevel_init:
 	mov	r0, pc, lsr #28
 	cmp	r0, #8
 	beq	prcm_setup
-	
+
 flash_setup:
 	/* In Flash */
 	ldr	r0, =WD2_BASE
@@ -203,7 +203,7 @@ prcm_setup:
 
 	ldr	r1, =0x00000002
 	str	r1, [r0, #0x340]
-	
+
         ldr     r1, =CM_CLKSEL1_CORE
 #ifdef PRCM_CONFIG_I
 	ldr     r2, =0x08300C44
@@ -211,7 +211,7 @@ prcm_setup:
 	ldr     r2, =0x04600C26
 #endif
         str     r2, [r1]
-	
+
         ldr     r0, =OMAP2420_CM_BASE
         ldr     r1, [r0, #0x084]
         and     r1, r1, #0x01
diff --git a/board/apollon/mem.c b/board/apollon/mem.c
index 8154d1181..c0edca56e 100644
--- a/board/apollon/mem.c
+++ b/board/apollon/mem.c
@@ -39,20 +39,19 @@
  *  is necessary until timers are accessible.
  *
  *  not inline to increase chances its in cache when called
-*************************************************************/
+ *************************************************************/
 void sdelay(unsigned long loops)
 {
-	__asm__ volatile ("1:\n" "subs %0, %1, #1\n"
-			  "bne 1b":"=r" (loops):"0"(loops));
+	__asm__("1:\n" "subs %0, %1, #1\n"
+		  "bne 1b":"=r" (loops):"0"(loops));
 }
 
-/*****************************************************************************
+/********************************************************************
  * prcm_init() - inits clocks for PRCM as defined in clocks.h
- * (config II default). Called from SRAM, or Flash (using temp SRAM stack).
- *****************************************************************************/
-void prcm_init(void)
-{
-}
+ * (config II default).
+ *   -- called from SRAM, or Flash (using temp SRAM stack).
+ ********************************************************************/
+void prcm_init(void) { }
 
 /**************************************************************************
  * make_cs1_contiguous() - for es2 and above remap cs1 behind cs0 to allow
@@ -69,6 +68,7 @@ void make_cs1_contiguous(void)
 	a_add_high = (size & 3) << 8;	/* set up low field */
 	a_add_low = (size & 0x3C) >> 2;	/* set up high field */
 	__raw_writel((a_add_high | a_add_low), SDRC_CS_CFG);
+
 }
 
 /********************************************************
@@ -81,13 +81,18 @@ u32 mem_ok(void)
 	u32 val1, val2;
 	u32 pattern = 0x12345678;
 
-	__raw_writel(0x0, OMAP2420_SDRC_CS0 + 0x400);	/* clear pos A */
-	__raw_writel(pattern, OMAP2420_SDRC_CS0);	/* pattern to pos B */
-	__raw_writel(0x0, OMAP2420_SDRC_CS0 + 4);	/* remove pattern off the bus */
-	val1 = __raw_readl(OMAP2420_SDRC_CS0 + 0x400);	/* get pos A value */
+	/* clear pos A */
+	__raw_writel(0x0, OMAP2420_SDRC_CS0 + 0x400);
+	/* pattern to pos B */
+	__raw_writel(pattern, OMAP2420_SDRC_CS0);
+	/* remove pattern off the bus */
+	__raw_writel(0x0, OMAP2420_SDRC_CS0 + 4);
+	/* get pos A value */
+	val1 = __raw_readl(OMAP2420_SDRC_CS0 + 0x400);
 	val2 = __raw_readl(OMAP2420_SDRC_CS0);	/* get val2 */
 
-	if ((val1 != 0) || (val2 != pattern))	/* see if pos A value changed */
+	/* see if pos A value changed */
+	if ((val1 != 0) || (val2 != pattern))
 		return (0);
 	else
 		return (1);
@@ -142,9 +147,11 @@ void gpmc_init(void)
 	__raw_writel(0x0, GPMC_IRQENABLE);	/* isr's sources masked */
 	__raw_writel(tval, GPMC_TIMEOUT_CONTROL);	/* timeout disable */
 #ifdef CFG_NAND_BOOT
-	__raw_writel(0x001, GPMC_CONFIG);	/* set nWP, disable limited addr */
+	/* set nWP, disable limited addr */
+	__raw_writel(0x001, GPMC_CONFIG);
 #else
-	__raw_writel(0x111, GPMC_CONFIG);	/* set nWP, disable limited addr */
+	/* set nWP, disable limited addr */
+	__raw_writel(0x111, GPMC_CONFIG);
 #endif
 
 	/* discover bus connection from sysboot */
@@ -164,7 +171,8 @@ void gpmc_init(void)
 	__raw_writel(APOLLON_24XX_GPMC_CONFIG4_3, GPMC_CONFIG4_0);
 	__raw_writel(APOLLON_24XX_GPMC_CONFIG5_3, GPMC_CONFIG5_0);
 	__raw_writel(APOLLON_24XX_GPMC_CONFIG6_3, GPMC_CONFIG6_0);
-	__raw_writel(APOLLON_24XX_GPMC_CONFIG7_3, GPMC_CONFIG7_0); #else
+	__raw_writel(APOLLON_24XX_GPMC_CONFIG7_3, GPMC_CONFIG7_0);
+#else
 	__raw_writel(APOLLON_24XX_GPMC_CONFIG1_0 | mux | mtype | mwidth,
 		     GPMC_CONFIG1_0);
 	__raw_writel(APOLLON_24XX_GPMC_CONFIG2_0, GPMC_CONFIG2_0);
@@ -172,7 +180,6 @@ void gpmc_init(void)
 	__raw_writel(APOLLON_24XX_GPMC_CONFIG4_0, GPMC_CONFIG4_0);
 	__raw_writel(APOLLON_24XX_GPMC_CONFIG5_0, GPMC_CONFIG5_0);
 	__raw_writel(APOLLON_24XX_GPMC_CONFIG6_0, GPMC_CONFIG6_0);
-	/* enable new mapping */
 	__raw_writel(APOLLON_24XX_GPMC_CONFIG7_0, GPMC_CONFIG7_0);
 #endif
 	sdelay(2000);
diff --git a/board/apollon/mem.h b/board/apollon/mem.h
index aed7e1d64..5bc96faa9 100644
--- a/board/apollon/mem.h
+++ b/board/apollon/mem.h
@@ -44,15 +44,15 @@
 #define APOLLON_242x_SDRC_DLLAB_CTRL_166MHz	0x00000506
 
 #ifdef PRCM_CONFIG_I
-# define APOLLON_2420_SDRC_ACTIM_CTRLA_0	APOLLON_242X_SDRC_ACTIM_CTRLA_0_166MHz
-# define APOLLON_2420_SDRC_ACTIM_CTRLB_0	APOLLON_242X_SDRC_ACTIM_CTRLB_0_166MHz
-# define APOLLON_2420_SDRC_RFR_CTRL		APOLLON_242X_SDRC_RFR_CTRL_166MHz
-# define APOLLON_2420_SDRC_DLLAB_CTRL		APOLLON_242x_SDRC_DLLAB_CTRL_166MHz
+#define APOLLON_2420_SDRC_ACTIM_CTRLA_0	APOLLON_242X_SDRC_ACTIM_CTRLA_0_166MHz
+#define APOLLON_2420_SDRC_ACTIM_CTRLB_0	APOLLON_242X_SDRC_ACTIM_CTRLB_0_166MHz
+#define APOLLON_2420_SDRC_RFR_CTRL	APOLLON_242X_SDRC_RFR_CTRL_166MHz
+#define APOLLON_2420_SDRC_DLLAB_CTRL	APOLLON_242x_SDRC_DLLAB_CTRL_166MHz
 #elif PRCM_CONFIG_II
-# define APOLLON_2420_SDRC_ACTIM_CTRLA_0	APOLLON_242X_SDRC_ACTIM_CTRLA_0_100MHz
-# define APOLLON_2420_SDRC_ACTIM_CTRLB_0	APOLLON_242X_SDRC_ACTIM_CTRLB_0_100MHz
-# define APOLLON_2420_SDRC_RFR_CTRL		APOLLON_242X_SDRC_RFR_CTRL_100MHz
-# define APOLLON_2420_SDRC_DLLAB_CTRL		APOLLON_242x_SDRC_DLLAB_CTRL_100MHz
+#define APOLLON_2420_SDRC_ACTIM_CTRLA_0	APOLLON_242X_SDRC_ACTIM_CTRLA_0_100MHz
+#define APOLLON_2420_SDRC_ACTIM_CTRLB_0	APOLLON_242X_SDRC_ACTIM_CTRLB_0_100MHz
+#define APOLLON_2420_SDRC_RFR_CTRL	APOLLON_242X_SDRC_RFR_CTRL_100MHz
+#define APOLLON_2420_SDRC_DLLAB_CTRL	APOLLON_242x_SDRC_DLLAB_CTRL_100MHz
 #endif
 
 /* GPMC settings */
diff --git a/board/apollon/sys_info.c b/board/apollon/sys_info.c
index 60c35b458..26ac9a2c8 100644
--- a/board/apollon/sys_info.c
+++ b/board/apollon/sys_info.c
@@ -39,6 +39,7 @@ static u32 get_prod_id(void)
 	p = __raw_readl(PRODUCTION_ID);	/* get production ID */
 	return ((p & CPU_242X_PID_MASK) >> 16);
 }
+
 /**************************************************************************
  * get_cpu_type() - low level get cpu type
  * - no C globals yet.
@@ -68,7 +69,8 @@ u32 get_cpu_type(void)
 
 	v = __raw_readl(TAP_IDCODE_REG);
 	v &= CPU_24XX_ID_MASK;
-	if (v == CPU_2420_CHIPID) {	/* currently 2420 and 2422 have same id */
+	/* currently 2420 and 2422 have same id */
+	if (v == CPU_2420_CHIPID) {
 		if (is_gpmc_muxed() == GPMC_MUXED)	/* if mux'ed */
 			return (CPU_2420);
 		else
@@ -127,8 +129,7 @@ u32 get_mem_type(void)
 		return (DDR_DISCRETE);	/* origional SDP */
 }
 
-/**********************************************************************
- *
+/***********************************************************************
  * get_cs0_size() - get size of chip select 0/1
  ************************************************************************/
 u32 get_sdr_cs_size(u32 offset)
@@ -140,8 +141,7 @@ u32 get_sdr_cs_size(u32 offset)
 	return (size);
 }
 
-/**********************************************************************
- *
+/***********************************************************************
  * get_board_type() - get board type based on current production stats.
  *  --- NOTE: 2 I2C EEPROMs will someday be populated with proper info.
  *      when they are available we can get info from there.  This should
@@ -149,17 +149,12 @@ u32 get_sdr_cs_size(u32 offset)
  ************************************************************************/
 u32 get_board_type(void)
 {
-#if 0
-	if (i2c_probe(I2C_MENELAUS) == 0)
-		return (BOARD_H4_MENELAUS);
-	else
-#endif
-		return (BOARD_H4_SDP);
+	return (BOARD_H4_SDP);
 }
 
 /******************************************************************
  * get_sysboot_value() - get init word settings (dip switch on h4)
-******************************************************************/
+ ******************************************************************/
 inline u32 get_sysboot_value(void)
 {
 	return (0x00000FFF & __raw_readl(CONTROL_STATUS));
@@ -175,7 +170,7 @@ inline u32 get_sysboot_value(void)
  *       -- 4 to flash
  *       -- 8 to enent
  *       -- c to wifi
- ***************************************************************************/
+ ****************************************************************************/
 u32 get_gpmc0_base(void)
 {
 	u32 b;
@@ -231,8 +226,8 @@ u32 get_gpmc0_width(void)
  * wait_on_value() - common routine to allow waiting for changes in
  *   volatile regs.
  *********************************************************************/
-u32 wait_on_value(u32 read_bit_mask, u32 match_value, u32 read_addr,
-u32 bound) {
+u32 wait_on_value(u32 read_bit_mask, u32 match_value, u32 read_addr, u32 bound)
+{
 	u32 i = 0, val;
 	do {
 		++i;
@@ -304,7 +299,8 @@ void display_board_info(u32 btype)
 	}
 
 	printf("OMAP%s-%s revision %d\n", cpu_s, sec_s, rev - 1);
-	printf("Samsung Apollon SDP Base Board + %s \n", mem_s); }
+	printf("Samsung Apollon SDP Base Board + %s \n", mem_s);
+}
 
 /*************************************************************************
  * get_board_rev() - setup to pass kernel board revision information
@@ -316,9 +312,8 @@ u32 get_board_rev(void)
 	u32 rev = 0;
 	u32 btype = get_board_type();
 
-	if (btype == BOARD_H4_MENELAUS) {
+	if (btype == BOARD_H4_MENELAUS)
 		rev = 1;
-	}
 	return (rev);
 }
 
diff --git a/board/apollon/u-boot.lds b/board/apollon/u-boot.lds
index 686d86b76..c67cd3cda 100644
--- a/board/apollon/u-boot.lds
+++ b/board/apollon/u-boot.lds
@@ -36,7 +36,7 @@ SECTIONS
 	. = 0x00000000;
 
 	. = ALIGN(4);
-	.text	 :
+	.text	:
 	{
 		cpu/arm1136/start.o	(.text)
 		*(.text)
@@ -61,4 +61,3 @@ SECTIONS
 	.bss : { *(.bss) }
 	_end = .;
 }
-
diff --git a/include/asm-arm/arch-arm1136/mux.h b/include/asm-arm/arch-arm1136/mux.h
index 8bcd7a368..4fdb9c635 100644
--- a/include/asm-arm/arch-arm1136/mux.h
+++ b/include/asm-arm/arch-arm1136/mux.h
@@ -54,6 +54,10 @@ void muxSetupHDQ(void);
 #define CONTROL_PADCONF_GPMC_NCS0_BYTE1	((volatile unsigned char *)0x4800008D)
 #define CONTROL_PADCONF_GPMC_NCS0_BYTE2	((volatile unsigned char *)0x4800008E)
 #define CONTROL_PADCONF_GPMC_NCS0_BYTE3	((volatile unsigned char *)0x4800008F)
+#define CONTROL_PADCONF_GPMC_NCS0_BYTE4	(0x48000090)
+#define CONTROL_PADCONF_GPMC_NCS0_BYTE5	(0x48000091)
+#define CONTROL_PADCONF_GPMC_NCS0_BYTE6	(0x48000092)
+#define CONTROL_PADCONF_GPMC_NCS0_BYTE7	(0x48000093)
 
 /* Pin Muxing registers used for SDRC */
 #define CONTROL_PADCONF_SDRC_NCS0_BYTE0 ((volatile unsigned char *)0x480000A0)
@@ -71,7 +75,7 @@ void muxSetupHDQ(void);
 #define CONTROL_PADCONF_SPI1_SIMO       ((volatile unsigned char *)0x48000100)
 #define CONTROL_PADCONF_SPI1_SOMI       ((volatile unsigned char *)0x48000101)
 #define CONTROL_PADCONF_SPI1_NCS0       ((volatile unsigned char *)0x48000102)
-#define CONTROL_PADCONF_SPI1_NCS1       ((volatile unsigned char *)0x48000103)
+#define CONTROL_PADCONF_SPI1_NCS1       (0x48000103)
 
 #define CONTROL_PADCONF_MCBSP1_FSR      ((volatile unsigned char *)0x4800010B)
 
@@ -153,8 +157,20 @@ void muxSetupHDQ(void);
 #define CONTROL_PADCONF_USB0_SE0		((volatile uint8 *)0x48000122)
 #define CONTROL_PADCONF_USB0_DAT		((volatile uint8 *)0x48000123)
 
+/* Pin Muxing registres used for USB1. */
+#define CONTROL_PADCONF_USB1_RCV	(0x480000EB)
+#define CONTROL_PADCONF_USB1_TXEN	(0x480000EC)
+
 /* Pin Muxing registers used for UART3/IRDA */
 #define CONTROL_PADCONF_UART3_TX_IRTX	((volatile uint8 *)0x48000118)
 #define CONTROL_PADCONF_UART3_RX_IRRX	((volatile uint8 *)0x48000119)
 
+/* Pin Muxing registers used for GPIO */
+#define CONTROL_PADCONF_GPIO69		(0x480000ED)
+#define CONTROL_PADCONF_GPIO70		(0x480000EE)
+#define CONTROL_PADCONF_GPIO102		(0x48000116)
+#define CONTROL_PADCONF_GPIO103		(0x48000117)
+#define CONTROL_PADCONF_GPIO104		(0x48000118)
+#define CONTROL_PADCONF_GPIO105		(0x48000119)
+
 #endif

From 2ae64f5135e51bb18753884d1265b99e89b5aedd Mon Sep 17 00:00:00 2001
From: Peter Pearse <peter.pearse@arm.com>
Date: Thu, 15 Nov 2007 08:58:00 +0000
Subject: [PATCH 016/108] Remove warnings re CONFIG_EXTRA_ENV_SETTINGS Remove
 warnings re onenand_read() & write()

---
 common/env_onenand.c      |  4 ++--
 include/configs/apollon.h | 18 +++++++++---------
 2 files changed, 11 insertions(+), 11 deletions(-)
 mode change 100644 => 100755 include/configs/apollon.h

diff --git a/common/env_onenand.c b/common/env_onenand.c
index 66107f91f..5888f75d8 100644
--- a/common/env_onenand.c
+++ b/common/env_onenand.c
@@ -64,7 +64,7 @@ void env_relocate_spec(void)
 	DECLARE_GLOBAL_DATA_PTR;
 	unsigned long env_addr;
 	int use_default = 0;
-	int retlen;
+	size_t retlen;
 
 	env_addr = CFG_ENV_ADDR;
 	env_addr -= (unsigned long)onenand_chip.base;
@@ -96,7 +96,7 @@ int saveenv(void)
 {
 	unsigned long env_addr = CFG_ENV_ADDR;
 	struct erase_info instr;
-	int retlen;
+	size_t retlen;
 
 	instr.len = CFG_ENV_SIZE;
 	instr.addr = env_addr;
diff --git a/include/configs/apollon.h b/include/configs/apollon.h
old mode 100644
new mode 100755
index 578153c8b..7727bc3e2
--- a/include/configs/apollon.h
+++ b/include/configs/apollon.h
@@ -148,15 +148,15 @@
 #endif
 
 #define	CONFIG_EXTRA_ENV_SETTINGS					\
-	"Image=tftp 0x80008000 Image\; go 0x80008000\0"			\
-	"zImage=tftp 0x80180000 zImage\; go 0x80180000\0"		\
-	"uImage=tftp 0x80180000 uImage\; bootm 0x80180000\0"		\
-	"uboot=tftp 0x80008000 u-boot.bin\; go 0x80008000\0"		\
-	"xloader=tftp 0x80180000 x-load.bin\; cp.w 0x80180000 0x00000400 0x1000\; go 0x00000400\0"	\
-	"syncmode50=mw.w 0x1e442 0xc0c4\; mw 0x6800a060 0xe30d1201\0"	\
-	"syncmode=mw.w 0x1e442 0xe0f4\; mw 0x6800a060 0xe30d1201\0"	\
-	"norboot=cp32 0x18040000 0x80008000 0x200000\; go 0x80008000\0"	\
-	"oneboot=onenand read 0x80008000 0x40000 0x200000\; go 0x80008000\0"\
+	"Image=tftp 0x80008000 Image; go 0x80008000\0"			\
+	"zImage=tftp 0x80180000 zImage; go 0x80180000\0"		\
+	"uImage=tftp 0x80180000 uImage; bootm 0x80180000\0"		\
+	"uboot=tftp 0x80008000 u-boot.bin; go 0x80008000\0"		\
+	"xloader=tftp 0x80180000 x-load.bin; cp.w 0x80180000 0x00000400 0x1000; go 0x00000400\0"	\
+	"syncmode50=mw.w 0x1e442 0xc0c4; mw 0x6800a060 0xe30d1201\0"	\
+	"syncmode=mw.w 0x1e442 0xe0f4; mw 0x6800a060 0xe30d1201\0"	\
+	"norboot=cp32 0x18040000 0x80008000 0x200000; go 0x80008000\0"	\
+	"oneboot=onenand read 0x80008000 0x40000 0x200000; go 0x80008000\0"\
 	"onesyncboot=run syncmode oneboot\0"				\
 	"bootcmd=run uboot\0"
 

From f23cb34c367bb27585a4fdb8a75277370e7d0596 Mon Sep 17 00:00:00 2001
From: Marian Balakowicz <m8@semihalf.com>
Date: Thu, 15 Nov 2007 13:24:43 +0100
Subject: [PATCH 017/108] [INKA4x0] NG hardware: platform code update

- Cleanup compile warnings.
- Add missing '\0' in default environment.
- Increase CFG_MONITOR_LEN to 256 KiB.
- Add required CFG_USE_PPCENV.

Signed-off-by: Marian Balakowicz <m8@semihalf.com>
---
 board/inka4x0/inka4x0.c   | 8 ++++----
 include/configs/inka4x0.h | 5 +++--
 2 files changed, 7 insertions(+), 6 deletions(-)

diff --git a/board/inka4x0/inka4x0.c b/board/inka4x0/inka4x0.c
index 478a331b4..c80fc3ba5 100644
--- a/board/inka4x0/inka4x0.c
+++ b/board/inka4x0/inka4x0.c
@@ -88,7 +88,7 @@ long int initdram (int board_type)
 {
 	ulong dramsize = 0;
 #ifndef CFG_RAMBOOT
-	ulong test1, test2;
+	long test1, test2;
 
 	/* setup SDRAM chip selects */
 	*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001c; /* 512MB at 0x0 */
@@ -108,9 +108,9 @@ long int initdram (int board_type)
 
 	/* find RAM size using SDRAM CS0 only */
 	sdram_start(0);
-	test1 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x20000000);
+	test1 = get_ram_size((long *)CFG_SDRAM_BASE, 0x20000000);
 	sdram_start(1);
-	test2 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x20000000);
+	test2 = get_ram_size((long *)CFG_SDRAM_BASE, 0x20000000);
 	if (test1 > test2) {
 		sdram_start(0);
 		dramsize = test1;
@@ -175,7 +175,7 @@ void flash_preinit(void)
 
 int misc_init_f (void)
 {
-	uchar tmp[10];
+	char tmp[10];
 	int i, br;
 
 	i = getenv_r("brightness", tmp, sizeof(tmp));
diff --git a/include/configs/inka4x0.h b/include/configs/inka4x0.h
index 0fac28fad..af8fb21e2 100644
--- a/include/configs/inka4x0.h
+++ b/include/configs/inka4x0.h
@@ -142,7 +142,7 @@
 		"cp.l 100000 f0000b28 1\0"				\
 	"ideargs=setenv bootargs root=/dev/hda1 rw\0"			\
 	"ide_boot=ext2load ide 0:1 200000 uImage;"			\
-		"run ideargs addip addcons enable_disp;bootm"		\
+		"run ideargs addip addcons enable_disp;bootm\0"		\
 	"brightness=255\0"						\
 	""
 
@@ -174,6 +174,7 @@
 #define CFG_ENV_SIZE		0x2000
 #define CFG_ENV_SECT_SIZE	0x2000
 #define CONFIG_ENV_OVERWRITE	1
+#define CFG_USE_PPCENV			/* Environment embedded in sect .ppcenv */
 
 /*
  * Memory map
@@ -203,7 +204,7 @@
 #   define CFG_RAMBOOT		1
 #endif
 
-#define CFG_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor	*/
+#define CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
 #define CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
 #define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
 

From 5fb6d7191e206cdde0e23140fd8111caed93a595 Mon Sep 17 00:00:00 2001
From: Marian Balakowicz <m8@semihalf.com>
Date: Thu, 15 Nov 2007 13:29:55 +0100
Subject: [PATCH 018/108] [INKA4x0] NG hardware: SDRAM support

Add support for three new DDR chips that may  be present on a NG
INKA4x0 hardware: HYB25D512160BF-5, K4H511638C-7CB3, T46V32M16BN-6IT.

Cleanup board/inka4x0/mt48lc16m16a2-75.h file.

Signed-off-by: Marian Balakowicz <m8@semihalf.com>
---
 board/inka4x0/hyb25d512160bf-5.h | 32 ++++++++++++++++++++++++++++++++
 board/inka4x0/inka4x0.c          | 12 ++++++++++--
 board/inka4x0/k4h511638c.h       | 32 ++++++++++++++++++++++++++++++++
 board/inka4x0/mt46v16m16-75.h    |  7 +------
 board/inka4x0/mt46v32m16-75.h    | 32 ++++++++++++++++++++++++++++++++
 board/inka4x0/mt48lc16m16a2-75.h | 19 +------------------
 include/configs/inka4x0.h        |  9 ++++++++-
 7 files changed, 116 insertions(+), 27 deletions(-)
 create mode 100644 board/inka4x0/hyb25d512160bf-5.h
 create mode 100644 board/inka4x0/k4h511638c.h
 create mode 100644 board/inka4x0/mt46v32m16-75.h

diff --git a/board/inka4x0/hyb25d512160bf-5.h b/board/inka4x0/hyb25d512160bf-5.h
new file mode 100644
index 000000000..7eb1f5015
--- /dev/null
+++ b/board/inka4x0/hyb25d512160bf-5.h
@@ -0,0 +1,32 @@
+/*
+ * Copyright (C) 2007 Semihalf
+ * Written by Marian Balakowicz <m8@semihalf.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#define SDRAM_DDR	1		/* is DDR */
+
+/* Settings for XLB = 132 MHz */
+#define SDRAM_MODE	0x018D0000
+#define SDRAM_EMODE	0x40090000
+#define SDRAM_CONTROL	0x714F0F00
+#define SDRAM_CONFIG1	0x73711930
+#define SDRAM_CONFIG2	0x46770000
+#define SDRAM_TAPDELAY	0x10000000
diff --git a/board/inka4x0/inka4x0.c b/board/inka4x0/inka4x0.c
index c80fc3ba5..5157f7d81 100644
--- a/board/inka4x0/inka4x0.c
+++ b/board/inka4x0/inka4x0.c
@@ -31,10 +31,18 @@
 #include <mpc5xxx.h>
 #include <pci.h>
 
-#if defined(CONFIG_MPC5200_DDR)
+#if defined(CONFIG_DDR_MT46V16M16)
 #include "mt46v16m16-75.h"
-#else
+#elif defined(CONFIG_SDR_MT48LC16M16A2)
 #include "mt48lc16m16a2-75.h"
+#elif defined(CONFIG_DDR_MT46V32M16)
+#include "mt46v32m16.h"
+#elif defined(CONFIG_DDR_HYB25D512160BF)
+#include "hyb25d512160bf.h"
+#elif defined(CONFIG_DDR_K4H511638C)
+#include "k4h511638c.h"
+#else
+#error "INKA4x0 SDRAM: invalid chip type specified!"
 #endif
 
 #ifndef CFG_RAMBOOT
diff --git a/board/inka4x0/k4h511638c.h b/board/inka4x0/k4h511638c.h
new file mode 100644
index 000000000..70cc40521
--- /dev/null
+++ b/board/inka4x0/k4h511638c.h
@@ -0,0 +1,32 @@
+/*
+ * Copyright (C) 2007 Semihalf
+ * Written by Marian Balakowicz <m8@semihalf.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#define SDRAM_DDR	1		/* is DDR */
+
+/* Settings for XLB = 132 MHz */
+#define SDRAM_MODE	0x018D0000
+#define SDRAM_EMODE	0x40090000
+#define SDRAM_CONTROL	0x714F0F00
+#define SDRAM_CONFIG1	0x73722930
+#define SDRAM_CONFIG2	0x46770000
+#define SDRAM_TAPDELAY	0x10000000
diff --git a/board/inka4x0/mt46v16m16-75.h b/board/inka4x0/mt46v16m16-75.h
index f650faaa1..a78e50e7c 100644
--- a/board/inka4x0/mt46v16m16-75.h
+++ b/board/inka4x0/mt46v16m16-75.h
@@ -23,15 +23,10 @@
 
 #define SDRAM_DDR	1		/* is DDR */
 
-#if defined(CONFIG_MPC5200)
 /* Settings for XLB = 132 MHz */
 #define SDRAM_MODE	0x018D0000
 #define SDRAM_EMODE	0x40090000
-#define SDRAM_CONTROL	0x714f0f00
+#define SDRAM_CONTROL	0x714F0F00
 #define SDRAM_CONFIG1	0x73722930
 #define SDRAM_CONFIG2	0x47770000
 #define SDRAM_TAPDELAY	0x10000000
-
-#else
-#error CONFIG_MPC5200 not defined
-#endif
diff --git a/board/inka4x0/mt46v32m16-75.h b/board/inka4x0/mt46v32m16-75.h
new file mode 100644
index 000000000..7eb1f5015
--- /dev/null
+++ b/board/inka4x0/mt46v32m16-75.h
@@ -0,0 +1,32 @@
+/*
+ * Copyright (C) 2007 Semihalf
+ * Written by Marian Balakowicz <m8@semihalf.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#define SDRAM_DDR	1		/* is DDR */
+
+/* Settings for XLB = 132 MHz */
+#define SDRAM_MODE	0x018D0000
+#define SDRAM_EMODE	0x40090000
+#define SDRAM_CONTROL	0x714F0F00
+#define SDRAM_CONFIG1	0x73711930
+#define SDRAM_CONFIG2	0x46770000
+#define SDRAM_TAPDELAY	0x10000000
diff --git a/board/inka4x0/mt48lc16m16a2-75.h b/board/inka4x0/mt48lc16m16a2-75.h
index 13a97ac46..15477259c 100644
--- a/board/inka4x0/mt48lc16m16a2-75.h
+++ b/board/inka4x0/mt48lc16m16a2-75.h
@@ -21,27 +21,10 @@
  * MA 02111-1307 USA
  */
 
-#define SDRAM_DDR	1		/* is SDR */
+#define SDRAM_DDR	0		/* is SDR */
 
-#if defined(CONFIG_MPC5200)
 /* Settings for XLB = 132 MHz */
 #define SDRAM_MODE	0x00CD0000
-/* #define SDRAM_MODE	0x008D0000 */ /* CAS latency 2 */
 #define SDRAM_CONTROL	0x504F0000
 #define SDRAM_CONFIG1	0xD2322800
-/* #define SDRAM_CONFIG1	0xD2222800 */ /* CAS latency 2 */
-/*#define SDRAM_CONFIG1	0xD7322800 */ /* SDRAM controller bug workaround */
 #define SDRAM_CONFIG2	0x8AD70000
-/*#define SDRAM_CONFIG2	0xDDD70000 */ /* SDRAM controller bug workaround */
-
-#elif defined(CONFIG_MGT5100)
-/* Settings for XLB = 66 MHz */
-#define SDRAM_MODE	0x008D0000
-#define SDRAM_CONTROL	0x504F0000
-#define SDRAM_CONFIG1	0xC2222600
-#define SDRAM_CONFIG2	0x88B70004
-#define SDRAM_ADDRSEL	0x02000000
-
-#else
-#error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined
-#endif
diff --git a/include/configs/inka4x0.h b/include/configs/inka4x0.h
index af8fb21e2..1617cd49a 100644
--- a/include/configs/inka4x0.h
+++ b/include/configs/inka4x0.h
@@ -183,7 +183,14 @@
 #define CFG_SDRAM_BASE		0x00000000
 #define CFG_DEFAULT_MBAR	0x80000000
 
-#define CONFIG_MPC5200_DDR
+/*
+ * SDRAM controller configuration
+ */
+#undef CONFIG_SDR_MT48LC16M16A2
+#undef CONFIG_DDR_MT46V16M16
+#undef CONFIG_DDR_MT46V32M16
+#undef CONFIG_DDR_HYB25D512160BF
+#define CONFIG_DDR_K4H511638C
 
 /* Use ON-Chip SRAM until RAM will be available */
 #define CFG_INIT_RAM_ADDR	MPC5XXX_SRAM

From 5e71c51d74c963d3174060c078dcacf13bdd02ef Mon Sep 17 00:00:00 2001
From: Marian Balakowicz <m8@semihalf.com>
Date: Thu, 15 Nov 2007 13:37:28 +0100
Subject: [PATCH 019/108] [INKA4x0] NG hardware: flash support

Disabled and remove inka4x0 custom flash driver, use CFI flash
driver instead.

Signed-off-by: Marian Balakowicz <m8@semihalf.com>
---
 board/inka4x0/Makefile    |   2 +-
 board/inka4x0/flash.c     | 432 --------------------------------------
 include/configs/inka4x0.h |  19 +-
 3 files changed, 10 insertions(+), 443 deletions(-)
 delete mode 100644 board/inka4x0/flash.c

diff --git a/board/inka4x0/Makefile b/board/inka4x0/Makefile
index 8aa7e7c8e..ddfd2ef8a 100644
--- a/board/inka4x0/Makefile
+++ b/board/inka4x0/Makefile
@@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
 
 LIB	= $(obj)lib$(BOARD).a
 
-COBJS	:= $(BOARD).o flash.o
+COBJS	:= $(BOARD).o
 
 SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS))
diff --git a/board/inka4x0/flash.c b/board/inka4x0/flash.c
deleted file mode 100644
index b13865530..000000000
--- a/board/inka4x0/flash.c
+++ /dev/null
@@ -1,432 +0,0 @@
-/*
- * (C) Copyright 2003-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * (C) Copyright 2004
- * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-
-flash_info_t	flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
-
-/*
- * CPU to flash interface is 8-bit, so make declaration accordingly
- */
-typedef unsigned char FLASH_PORT_WIDTH;
-typedef volatile unsigned char FLASH_PORT_WIDTHV;
-
-#define FPW	FLASH_PORT_WIDTH
-#define FPWV	FLASH_PORT_WIDTHV
-
-#define FLASH_CYCLE1	0x0555
-#define FLASH_CYCLE2	0x02aa
-
-/*-----------------------------------------------------------------------
- * Functions
- */
-static ulong flash_get_size(FPWV *addr, flash_info_t *info);
-static void flash_reset(flash_info_t *info);
-static int write_word_amd(flash_info_t *info, FPWV *dest, FPW data);
-static flash_info_t *flash_get_info(ulong base);
-
-/*-----------------------------------------------------------------------
- * flash_init()
- *
- * sets up flash_info and returns size of FLASH (bytes)
- */
-unsigned long flash_init (void)
-{
-	unsigned long size = 0;
-	extern void flash_preinit(void);
-	ulong flashbase = CFG_FLASH_BASE;
-
-	flash_preinit();
-
-	/* Init: no FLASHes known */
-	memset(&flash_info[0], 0, sizeof(flash_info_t));
-
-	flash_info[0].size =
-		flash_get_size((FPW *)flashbase, &flash_info[0]);
-
-	size = flash_info[0].size;
-
-#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
-	/* monitor protection ON by default */
-	flash_protect(FLAG_PROTECT_SET,
-		      CFG_MONITOR_BASE,
-		      CFG_MONITOR_BASE+monitor_flash_len-1,
-		      flash_get_info(CFG_MONITOR_BASE));
-#endif
-
-#ifdef	CFG_ENV_IS_IN_FLASH
-	/* ENV protection ON by default */
-	flash_protect(FLAG_PROTECT_SET,
-		      CFG_ENV_ADDR,
-		      CFG_ENV_ADDR+CFG_ENV_SIZE-1,
-		      flash_get_info(CFG_ENV_ADDR));
-#endif
-
-	return size ? size : 1;
-}
-
-/*-----------------------------------------------------------------------
- */
-static void flash_reset(flash_info_t *info)
-{
-	FPWV *base = (FPWV *)(info->start[0]);
-
-	/* Put FLASH back in read mode */
-	if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL)
-		*base = (FPW)0x00FF00FF;	/* Intel Read Mode */
-	else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD)
-		*base = (FPW)0x00F000F0;	/* AMD Read Mode */
-}
-
-/*-----------------------------------------------------------------------
- */
-
-static flash_info_t *flash_get_info(ulong base)
-{
-	int i;
-	flash_info_t * info;
-
-	for (i = 0; i < CFG_MAX_FLASH_BANKS; i ++) {
-		info = & flash_info[i];
-		if (info->size && info->start[0] <= base &&
-		    base <= info->start[0] + info->size - 1)
-			break;
-	}
-
-	return i == CFG_MAX_FLASH_BANKS ? 0 : info;
-}
-
-/*-----------------------------------------------------------------------
- */
-
-void flash_print_info (flash_info_t *info)
-{
-	int i;
-
-	if (info->flash_id == FLASH_UNKNOWN) {
-		printf ("missing or unknown FLASH type\n");
-		return;
-	}
-
-	switch (info->flash_id & FLASH_VENDMASK) {
-	case FLASH_MAN_AMD:	printf ("AMD ");		break;
-	case FLASH_MAN_BM:	printf ("BRIGHT MICRO ");	break;
-	case FLASH_MAN_FUJ:	printf ("FUJITSU ");		break;
-	case FLASH_MAN_SST:	printf ("SST ");		break;
-	case FLASH_MAN_STM:	printf ("STM ");		break;
-	case FLASH_MAN_INTEL:	printf ("INTEL ");		break;
-	default:		printf ("Unknown Vendor ");	break;
-	}
-
-	switch (info->flash_id & FLASH_TYPEMASK) {
-	case FLASH_AM116DB:
-		printf ("AM29LV116DB (16Mbit, bottom boot sect)\n");
-		break;
-	case FLASH_AMLV128U:
-		printf ("AM29LV128ML (128Mbit, uniform sector size)\n");
-		break;
-	case FLASH_AM160B:
-		printf ("AM29LV160B (16 Mbit, bottom boot sect)\n");
-		break;
-	default:
-		printf ("Unknown Chip Type\n");
-		break;
-	}
-
-	printf ("  Size: %ld MB in %d Sectors\n",
-		info->size >> 20,
-		info->sector_count);
-
-	printf ("  Sector Start Addresses:");
-
-	for (i=0; i<info->sector_count; ++i) {
-		if ((i % 5) == 0) {
-			printf ("\n   ");
-		}
-		printf (" %08lX%s",
-			info->start[i],
-			info->protect[i] ? " (RO)" : "     ");
-	}
-	printf ("\n");
-	return;
-}
-
-/*-----------------------------------------------------------------------
- */
-
-/*
- * The following code cannot be run from FLASH!
- */
-
-ulong flash_get_size (FPWV *addr, flash_info_t *info)
-{
-	int i;
-	ulong base = (ulong)addr;
-
-	/* Write auto select command: read Manufacturer ID */
-	/* Write auto select command sequence and test FLASH answer */
-	addr[FLASH_CYCLE1] = (FPW)0x00AA00AA;	/* for AMD, Intel ignores this */
-	addr[FLASH_CYCLE2] = (FPW)0x00550055;	/* for AMD, Intel ignores this */
-	addr[FLASH_CYCLE1] = (FPW)0x00900090;	/* selects Intel or AMD */
-
-	/* The manufacturer codes are only 1 byte, so just use 1 byte.
-	 * This works for any bus width and any FLASH device width.
-	 */
-	udelay(100);
-	switch (addr[0] & 0xff) {
-
-	case (uchar)AMD_MANUFACT:
-		debug ("Manufacturer: AMD (Spansion)\n");
-		info->flash_id = FLASH_MAN_AMD;
-		break;
-
-	case (uchar)INTEL_MANUFACT:
-		debug ("Manufacturer: Intel (not supported yet)\n");
-		info->flash_id = FLASH_MAN_INTEL;
-		break;
-
-	default:
-		info->flash_id = FLASH_UNKNOWN;
-		info->sector_count = 0;
-		info->size = 0;
-		break;
-	}
-
-	/* Check 16 bits or 32 bits of ID so work on 32 or 16 bit bus. */
-	if (info->flash_id != FLASH_UNKNOWN) switch ((FPW)addr[1]) {
-
-	case (uchar)AMD_ID_LV116DB:
-		debug ("Chip: AM29LV116DB\n");
-		info->flash_id += FLASH_AM116DB;
-		info->sector_count = 35;
-		info->size = 0x00200000;
-		/*
-		 * The first 4 sectors are 16 kB, 8 kB, 8 kB and 32 kB, all
-		 * the other ones are 64 kB
-		 */
-		info->start[0] = base + 0x00000000;
-		info->start[1] = base + 0x00004000;
-		info->start[2] = base + 0x00006000;
-		info->start[3] = base + 0x00008000;
-		for( i = 4; i < info->sector_count; i++ )
-			info->start[i] =
-				base + (i * (64 << 10)) - 0x00030000;
-		break;          /* => 2 MB */
-
-	case (FPW)AMD_ID_LV160B:
-		debug ("Chip: AM29LV160MB\n");
-		info->flash_id += FLASH_AM160B;
-		info->sector_count = 35;
-		info->size = 0x00400000;
-		/*
-		 * The first 4 sectors are 16 kB, 8 kB, 8 kB and 32 kB, all
-		 * the other ones are 64 kB
-		 */
-		info->start[0] = base + 0x00000000;
-		info->start[1] = base + 0x00008000;
-		info->start[2] = base + 0x0000C000;
-		info->start[3] = base + 0x00010000;
-		for( i = 4; i < info->sector_count; i++ )
-			info->start[i] =
-				base + (i * 2 * (64 << 10)) - 0x00060000;
-		break;		/* => 4 MB */
-
-	default:
-		info->flash_id = FLASH_UNKNOWN;
-		info->sector_count = 0;
-		info->size = 0;
-	}
-
-	/* Put FLASH back in read mode */
-	flash_reset(info);
-
-	return (info->size);
-}
-
-/*-----------------------------------------------------------------------
- */
-
-int	flash_erase (flash_info_t *info, int s_first, int s_last)
-{
-	FPWV *addr = (FPWV*)(info->start[0]);
-	int flag, prot, sect, l_sect;
-	ulong start, now, last;
-
-	debug ("flash_erase: first: %d last: %d\n", s_first, s_last);
-
-	if ((s_first < 0) || (s_first > s_last)) {
-		if (info->flash_id == FLASH_UNKNOWN) {
-			printf ("- missing\n");
-		} else {
-			printf ("- no sectors to erase\n");
-		}
-		return 1;
-	}
-
-	if ((info->flash_id == FLASH_UNKNOWN) ||
-	    (info->flash_id > FLASH_AMD_COMP)) {
-		printf ("Can't erase unknown flash type %08lx - aborted\n",
-			info->flash_id);
-		return 1;
-	}
-
-	prot = 0;
-	for (sect=s_first; sect<=s_last; ++sect) {
-		if (info->protect[sect]) {
-			prot++;
-		}
-	}
-
-	if (prot) {
-		printf ("- Warning: %d protected sectors will not be erased!\n",
-			prot);
-	} else {
-		printf ("\n");
-	}
-
-	l_sect = -1;
-
-	/* Disable interrupts which might cause a timeout here */
-	flag = disable_interrupts();
-
-	addr[0x0555] = (FPW)0x00AA00AA;
-	addr[0x02AA] = (FPW)0x00550055;
-	addr[0x0555] = (FPW)0x00800080;
-	addr[0x0555] = (FPW)0x00AA00AA;
-	addr[0x02AA] = (FPW)0x00550055;
-
-	/* Start erase on unprotected sectors */
-	for (sect = s_first; sect<=s_last; sect++) {
-		if (info->protect[sect] == 0) {	/* not protected */
-			addr = (FPWV*)(info->start[sect]);
-			addr[0] = (FPW)0x00300030;
-			l_sect = sect;
-		}
-	}
-
-	/* re-enable interrupts if necessary */
-	if (flag)
-		enable_interrupts();
-
-	/* wait at least 80us - let's wait 1 ms */
-	udelay (1000);
-
-	/*
-	 * We wait for the last triggered sector
-	 */
-	if (l_sect < 0)
-		goto DONE;
-
-	start = get_timer (0);
-	last  = start;
-	addr = (FPWV*)(info->start[l_sect]);
-	while ((addr[0] & (FPW)0x00800080) != (FPW)0x00800080) {
-		if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
-			printf ("Timeout\n");
-			return 1;
-		}
-		/* show that we're waiting */
-		if ((now - last) > 1000) {	/* every second */
-			putc ('.');
-			last = now;
-		}
-	}
-
-DONE:
-	/* reset to read mode */
-	addr = (FPWV*)info->start[0];
-	addr[0] = (FPW)0x00F000F0;	/* reset bank */
-
-	printf (" done\n");
-	return 0;
-}
-
-/*-----------------------------------------------------------------------
- * Copy memory to flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-
-int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
-{
-	int i, rc = 0;
-
-	for (i = 0; i < cnt; i++)
-		if ((rc = write_word_amd(info, (FPW *)(addr+i), src[i])) != 0) {
-			return (rc);
-		}
-
-	return rc;
-}
-
-/*-----------------------------------------------------------------------
- * Write a word to Flash for AMD FLASH
- * A word is 16 or 32 bits, whichever the bus width of the flash bank
- * (not an individual chip) is.
- *
- * returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-static int write_word_amd (flash_info_t *info, FPWV *dest, FPW data)
-{
-	ulong start;
-	int flag;
-	FPWV *base;		/* first address in flash bank	*/
-
-	/* Check if Flash is (sufficiently) erased */
-	if ((*dest & data) != data) {
-		return (2);
-	}
-
-	base = (FPWV *)(info->start[0]);
-
-	/* Disable interrupts which might cause a timeout here */
-	flag = disable_interrupts();
-
-	base[FLASH_CYCLE1] = (FPW)0x00AA00AA;	/* unlock */
-	base[FLASH_CYCLE2] = (FPW)0x00550055;	/* unlock */
-	base[FLASH_CYCLE1] = (FPW)0x00A000A0;	/* selects program mode */
-
-	*dest = data;		/* start programming the data	*/
-
-	/* re-enable interrupts if necessary */
-	if (flag)
-		enable_interrupts();
-
-	start = get_timer (0);
-
-	/* data polling for D7 */
-	while ((*dest & (FPW)0x00800080) != (data & (FPW)0x00800080)) {
-		if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
-			*dest = (FPW)0x00F000F0;	/* reset bank */
-			return (1);
-		}
-	}
-	return (0);
-}
diff --git a/include/configs/inka4x0.h b/include/configs/inka4x0.h
index 1617cd49a..206007d88 100644
--- a/include/configs/inka4x0.h
+++ b/include/configs/inka4x0.h
@@ -156,21 +156,20 @@
 /*
  * Flash configuration
  */
-#define CFG_FLASH_BASE		0xFFE00000
-
-#define CFG_FLASH_SIZE		0x00200000 /* 2 MByte */
-#define CFG_MAX_FLASH_SECT	35	/* max num of sects on one chip */
-
-#define CFG_ENV_ADDR		(CFG_FLASH_BASE + 0x4000) /* second sector */
-#define CFG_MAX_FLASH_BANKS	1	/* max num of flash banks
-					   (= chip selects) */
-#define CFG_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)	*/
+#define CFG_FLASH_CFI		1	/* Flash is CFI conformant */
+#define CFG_FLASH_CFI_DRIVER	1
+#define CFG_FLASH_BASE		0xffe00000
+#define CFG_FLASH_SIZE		0x00200000
+#define CFG_MAX_FLASH_BANKS	1	/* max num of memory banks */
+#define CFG_FLASH_BANKS_LIST	{ CFG_FLASH_BASE }
+#define CFG_MAX_FLASH_SECT	128	/* max num of sects on one chip */
+#define CFG_FLASH_USE_BUFFER_WRITE 1	/* use buffered writes (20x faster) */
 
 /*
  * Environment settings
  */
 #define CFG_ENV_IS_IN_FLASH	1
+#define CFG_ENV_ADDR		(CFG_FLASH_BASE + 0x4000)
 #define CFG_ENV_SIZE		0x2000
 #define CFG_ENV_SECT_SIZE	0x2000
 #define CONFIG_ENV_OVERWRITE	1

From 74f89faa9d1e77ed947e628d3effaa513fe05d05 Mon Sep 17 00:00:00 2001
From: Jon Loeliger <jdl@freescale.com>
Date: Tue, 20 Nov 2007 15:00:53 -0600
Subject: [PATCH 020/108] Move 8610 DIU interface structure definitions to
 header file.

These two structures are still needed during the
initialization and setup of the DIU hardware.
So move them to the fsl_diu_fb.h file for now.
Official "blah".

Noticed-by: York Sun <yorksun@freescale.com>
Signed-off-by: Jon Loeliger <jdl@freescale.com>
---
 board/freescale/common/fsl_diu_fb.c | 32 ---------------------------
 board/freescale/common/fsl_diu_fb.h | 34 +++++++++++++++++++++++++++++
 2 files changed, 34 insertions(+), 32 deletions(-)

diff --git a/board/freescale/common/fsl_diu_fb.c b/board/freescale/common/fsl_diu_fb.c
index a9999d393..c1dc48c62 100644
--- a/board/freescale/common/fsl_diu_fb.c
+++ b/board/freescale/common/fsl_diu_fb.c
@@ -39,38 +39,6 @@
 #define DPRINTF(fmt, args...)
 #endif
 
-struct fb_var_screeninfo {
-	unsigned int xres;		/* visible resolution		*/
-	unsigned int yres;
-
-	unsigned int bits_per_pixel;	/* guess what			*/
-
-	/* Timing: All values in pixclocks, except pixclock (of course) */
-	unsigned int pixclock;		/* pixel clock in ps (pico seconds) */
-	unsigned int left_margin;	/* time from sync to picture	*/
-	unsigned int right_margin;	/* time from picture to sync	*/
-	unsigned int upper_margin;	/* time from sync to picture	*/
-	unsigned int lower_margin;
-	unsigned int hsync_len;		/* length of horizontal sync	*/
-	unsigned int vsync_len;		/* length of vertical sync	*/
-	unsigned int sync;		/* see FB_SYNC_*		*/
-	unsigned int vmode;		/* see FB_VMODE_*		*/
-	unsigned int rotate;		/* angle we rotate counter clockwise */
-};
-
-struct fb_info {
-	struct fb_var_screeninfo var;	/* Current var */
-	unsigned long smem_start;	/* Start of frame buffer mem */
-					/* (physical address) */
-	unsigned int smem_len;		/* Length of frame buffer mem */
-	unsigned int type;		/* see FB_TYPE_*		*/
-	unsigned int line_length;	/* length of a line in bytes    */
-
-	char *screen_base;
-	unsigned long screen_size;
-	int logo_height;
-	unsigned int logo_size;
-};
 
 struct fb_videomode {
 	const char *name;	/* optional */
diff --git a/board/freescale/common/fsl_diu_fb.h b/board/freescale/common/fsl_diu_fb.h
index 9ddd4c0a5..6deba3275 100644
--- a/board/freescale/common/fsl_diu_fb.h
+++ b/board/freescale/common/fsl_diu_fb.h
@@ -23,7 +23,41 @@
  * MA 02111-1307 USA
  */
 
+struct fb_var_screeninfo {
+	unsigned int xres;		/* visible resolution		*/
+	unsigned int yres;
 
+	unsigned int bits_per_pixel;	/* guess what			*/
+
+	/* Timing: All values in pixclocks, except pixclock (of course) */
+	unsigned int pixclock;		/* pixel clock in ps (pico seconds) */
+	unsigned int left_margin;	/* time from sync to picture	*/
+	unsigned int right_margin;	/* time from picture to sync	*/
+	unsigned int upper_margin;	/* time from sync to picture	*/
+	unsigned int lower_margin;
+	unsigned int hsync_len;		/* length of horizontal sync	*/
+	unsigned int vsync_len;		/* length of vertical sync	*/
+	unsigned int sync;		/* see FB_SYNC_*		*/
+	unsigned int vmode;		/* see FB_VMODE_*		*/
+	unsigned int rotate;		/* angle we rotate counter clockwise */
+};
+
+struct fb_info {
+	struct fb_var_screeninfo var;	/* Current var */
+	unsigned long smem_start;	/* Start of frame buffer mem */
+					/* (physical address) */
+	unsigned int smem_len;		/* Length of frame buffer mem */
+	unsigned int type;		/* see FB_TYPE_*		*/
+	unsigned int line_length;	/* length of a line in bytes    */
+
+	char *screen_base;
+	unsigned long screen_size;
+	int logo_height;
+	unsigned int logo_size;
+};
+
+
+extern char *fsl_fb_open(struct fb_info **info);
 extern int fsl_diu_init(int xres,
 			unsigned int pixel_format,
 			int gamma_fix,

From 68b88999da87ab88e71e1306192905be3450198e Mon Sep 17 00:00:00 2001
From: Jon Loeliger <jdl@freescale.com>
Date: Tue, 20 Nov 2007 15:02:26 -0600
Subject: [PATCH 021/108] 8610HPCD: Enable the 8610 Display Interface Unit

Signed-off-by: Jon Loeliger <jdl@freescale.com>
---
 include/configs/MPC8610HPCD.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/include/configs/MPC8610HPCD.h b/include/configs/MPC8610HPCD.h
index ef1310f60..55df5aa10 100644
--- a/include/configs/MPC8610HPCD.h
+++ b/include/configs/MPC8610HPCD.h
@@ -24,7 +24,7 @@
 #define CONFIG_FSL_DIU_FB	1	/* FSL DIU */
 
 /* video */
-#undef CONFIG_VIDEO
+#define CONFIG_VIDEO
 
 #if defined(CONFIG_VIDEO)
 #define CONFIG_CFB_CONSOLE

From ea9f7395ec362584e5e4f266bd0b0c4422cf6a4c Mon Sep 17 00:00:00 2001
From: Jon Loeliger <jdl@freescale.com>
Date: Wed, 28 Nov 2007 14:47:18 -0600
Subject: [PATCH 022/108] Convert MPC8641HPCN to use libfdt.

Assumes the presence of the aliases node in the DTS to
locate the ethernet, pci and serial nodes for fixups.

Use consistent fdtaddr and fdtfile in environment variables.

Signed-off-by: Jon Loeliger <jdl@freescale.com>
---
 board/freescale/mpc8641hpcn/mpc8641hpcn.c | 60 +++++++++++++----------
 include/configs/MPC8641HPCN.h             | 21 ++++----
 2 files changed, 43 insertions(+), 38 deletions(-)

diff --git a/board/freescale/mpc8641hpcn/mpc8641hpcn.c b/board/freescale/mpc8641hpcn/mpc8641hpcn.c
index 931be9f37..827878939 100644
--- a/board/freescale/mpc8641hpcn/mpc8641hpcn.c
+++ b/board/freescale/mpc8641hpcn/mpc8641hpcn.c
@@ -27,11 +27,8 @@
 #include <asm/immap_fsl_pci.h>
 #include <spd.h>
 #include <asm/io.h>
-
-#if defined(CONFIG_OF_FLAT_TREE)
-#include <ft_build.h>
-extern void ft_cpu_setup(void *blob, bd_t *bd);
-#endif
+#include <libfdt.h>
+#include <fdt_support.h>
 
 #include "../common/pixis.h"
 
@@ -324,36 +321,47 @@ void pci_init_board(void)
 
 }
 
-#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP)
+#if defined(CONFIG_OF_BOARD_SETUP)
 void
 ft_board_setup(void *blob, bd_t *bd)
 {
-	u32 *p;
-	int len;
+	int node, tmp[2];
+	const char *path;
 
-	ft_cpu_setup(blob, bd);
+	fdt_fixup_ethernet(blob, bd);
 
-	p = ft_get_prop(blob, "/memory/reg", &len);
-	if (p != NULL) {
-		*p++ = cpu_to_be32(bd->bi_memstart);
-		*p = cpu_to_be32(bd->bi_memsize);
-	}
+	do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
+			     "timebase-frequency", bd->bi_busfreq / 4, 1);
+	do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
+			     "bus-frequency", bd->bi_busfreq, 1);
+	do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
+			     "clock-frequency", bd->bi_intfreq, 1);
+	do_fixup_by_prop_u32(blob, "device_type", "soc", 4,
+			     "bus-frequency", bd->bi_busfreq, 1);
+
+	do_fixup_by_compat_u32(blob, "ns16550",
+			       "clock-frequency", bd->bi_busfreq, 1);
+
+	fdt_fixup_memory(blob, bd->bi_memstart, bd->bi_memsize);
+
+	node = fdt_path_offset(blob, "/aliases");
+	tmp[0] = 0;
+	if (node >= 0) {
 #ifdef CONFIG_PCI1
-	p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pcie@8000/bus-range", &len);
-	if (p != NULL) {
-		p[0] = 0;
-		p[1] = pci1_hose.last_busno - pci1_hose.first_busno;
-		debug("PCI@8000 first_busno=%d last_busno=%d\n",p[0],p[1]);
-	}
+		path = fdt_getprop(blob, node, "pci0", NULL);
+		if (path) {
+			tmp[1] = pci1_hose.last_busno - pci1_hose.first_busno;
+			do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
+		}
 #endif
 #ifdef CONFIG_PCI2
-	p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pcie@9000/bus-range", &len);
-	if (p != NULL) {
-		p[0] = 0;
-		p[1] = pci2_hose.last_busno - pci2_hose.first_busno;
-		debug("PCI@9000 first_busno=%d last_busno=%d\n",p[0],p[1]);
-	}
+		path = fdt_getprop(blob, node, "pci1", NULL);
+		if (path) {
+			tmp[1] = pci2_hose.last_busno - pci2_hose.first_busno;
+			do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
+		}
 #endif
+	}
 }
 #endif
 
diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h
index 6f8724026..0fc65213c 100644
--- a/include/configs/MPC8641HPCN.h
+++ b/include/configs/MPC8641HPCN.h
@@ -267,13 +267,10 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 /*
  * Pass open firmware flat tree to kernel
  */
-#define CONFIG_OF_FLAT_TREE	1
-#define CONFIG_OF_BOARD_SETUP	1
+#define CONFIG_OF_LIBFDT		1
+#define CONFIG_OF_BOARD_SETUP		1
+#define CONFIG_OF_STDOUT_VIA_ALIAS	1
 
-#define OF_CPU		"PowerPC,8641@0"
-#define OF_SOC		"soc8641@f8000000"
-#define OF_TBCLK	(bd->bi_busfreq / 4)
-#define OF_STDOUT_PATH	"/soc8641@f8000000/serial@4500"
 
 #define CFG_64BIT_VSPRINTF	1
 #define CFG_64BIT_STRTOUL	1
@@ -645,8 +642,8 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
    "consoledev=ttyS0\0"                                                 \
    "ramdiskaddr=2000000\0"						\
    "ramdiskfile=your.ramdisk.u-boot\0"                                  \
-   "dtbaddr=c00000\0"						\
-   "dtbfile=mpc8641_hpcn.dtb\0"                                  \
+   "fdtaddr=c00000\0"						\
+   "fdtfile=mpc8641_hpcn.dtb\0"                                  \
    "en-wd=mw.b f8100010 0x08; echo -expect:- 08; md.b f8100010 1\0" \
    "dis-wd=mw.b f8100010 0x00; echo -expect:- 00; md.b f8100010 1\0" \
    "maxcpus=2"
@@ -658,16 +655,16 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
       "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
       "console=$consoledev,$baudrate $othbootargs;"                     \
    "tftp $loadaddr $bootfile;"                                          \
-   "tftp $dtbaddr $dtbfile;"                                          \
-   "bootm $loadaddr - $dtbaddr"
+   "tftp $fdtaddr $fdtfile;"                                          \
+   "bootm $loadaddr - $fdtaddr"
 
 #define CONFIG_RAMBOOTCOMMAND \
    "setenv bootargs root=/dev/ram rw "                                  \
       "console=$consoledev,$baudrate $othbootargs;"                     \
    "tftp $ramdiskaddr $ramdiskfile;"                                    \
    "tftp $loadaddr $bootfile;"                                          \
-   "tftp $dtbaddr $dtbfile;"                                          \
-   "bootm $loadaddr $ramdiskaddr $dtbaddr"
+   "tftp $fdtaddr $fdtfile;"                                          \
+   "bootm $loadaddr $ramdiskaddr $fdtaddr"
 
 #define CONFIG_BOOTCOMMAND  CONFIG_NFSBOOTCOMMAND
 

From 61d3421bdea090bd0399b14c3e10a3bebcc8d5ff Mon Sep 17 00:00:00 2001
From: Jon Loeliger <jdl@freescale.com>
Date: Tue, 4 Dec 2007 10:53:34 -0600
Subject: [PATCH 023/108] Don't slam #undef DEBUG in the 8641HPCN config file.

Doing so prevents it from being individually set
and useful in other files.

Signed-off-by: Jon Loeliger <jdl@freescale.com>
---
 include/configs/MPC8641HPCN.h | 1 -
 1 file changed, 1 deletion(-)

diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h
index 0fc65213c..575bbae43 100644
--- a/include/configs/MPC8641HPCN.h
+++ b/include/configs/MPC8641HPCN.h
@@ -38,7 +38,6 @@
 #define CONFIG_MPC8641HPCN	1	/* MPC8641HPCN board specific */
 #define CONFIG_NUM_CPUS         2       /* Number of CPUs in the system */
 #define CONFIG_LINUX_RESET_VEC  0x100   /* Reset vector used by Linux */
-#undef DEBUG
 
 #ifdef RUN_DIAG
 #define CFG_DIAG_ADDR        0xff800000

From 5c740711f0ea5b51414b341b71597c4a0751be74 Mon Sep 17 00:00:00 2001
From: Jon Loeliger <jdl@freescale.com>
Date: Thu, 3 Jan 2008 10:41:04 -0600
Subject: [PATCH 024/108] 8610: Move include of config.h earlier.

Include config.h earlier in the set of #includes
so as to avoid a incidental and duplicate definition
of CFG_CACHELINE_SIZE.

Signed-off-by: Jon Loeliger
---
 board/freescale/mpc8610hpcd/init.S | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/board/freescale/mpc8610hpcd/init.S b/board/freescale/mpc8610hpcd/init.S
index 68797a812..4d811e137 100644
--- a/board/freescale/mpc8610hpcd/init.S
+++ b/board/freescale/mpc8610hpcd/init.S
@@ -9,11 +9,11 @@
  * Version 2 as published by the Free Software Foundation.
  */
 
+#include <config.h>
 #include <ppc_asm.tmpl>
 #include <ppc_defs.h>
 #include <asm/cache.h>
 #include <asm/mmu.h>
-#include <config.h>
 #include <mpc86xx.h>
 
 #define LAWAR_TRGT_PCI1		0x00000000

From f85b60710571b37293d2233933b76e2aa3db5635 Mon Sep 17 00:00:00 2001
From: Rafal Jaworowski <raj@semihalf.com>
Date: Thu, 27 Dec 2007 18:19:02 +0100
Subject: [PATCH 025/108] Introduce new eth_receive routine

The purpose of this routine is receiving a single network frame, outside of
U-Boot's NetLoop(). Exporting it to standalone programs that run on top of
U-Boot will let them utilise networking facilities. For sending a raw frame
the already existing eth_send() can be used.

The direct consumer of this routine is the newly introduced API layer for
external applications (enabled with CONFIG_API).

Signed-off-by: Rafal Jaworowski <raj@semihalf.com>
Signed-off-by: Piotr Kruszynski <ppk@semihalf.com>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
---
 include/net.h |  3 +++
 net/eth.c     | 58 +++++++++++++++++++++++++++++++++++++++++++++++++++
 net/net.c     | 10 +++++++++
 3 files changed, 71 insertions(+)

diff --git a/include/net.h b/include/net.h
index 603452ab3..f6decdca8 100644
--- a/include/net.h
+++ b/include/net.h
@@ -122,6 +122,9 @@ extern void eth_set_enetaddr(int num, char* a);	/* Set new MAC address		*/
 
 extern int eth_init(bd_t *bis);			/* Initialize the device	*/
 extern int eth_send(volatile void *packet, int length);	   /* Send a packet	*/
+#ifdef CONFIG_API
+extern int eth_receive(volatile void *packet, int length); /* Receive a packet	*/
+#endif
 extern int eth_rx(void);			/* Check for received packets	*/
 extern void eth_halt(void);			/* stop SCC			*/
 extern char *eth_get_name(void);		/* get name of current device	*/
diff --git a/net/eth.c b/net/eth.c
index 1b56a356c..4657f7970 100644
--- a/net/eth.c
+++ b/net/eth.c
@@ -62,6 +62,17 @@ extern int bfin_EMAC_initialize(bd_t *);
 extern int atstk1000_eth_initialize(bd_t *);
 extern int mcffec_initialize(bd_t*);
 
+#ifdef CONFIG_API
+extern void (*push_packet)(volatile void *, int);
+
+static struct {
+	uchar data[PKTSIZE];
+	int length;
+} eth_rcv_bufs[PKTBUFSRX];
+
+static unsigned int eth_rcv_current = 0, eth_rcv_last = 0;
+#endif
+
 static struct eth_device *eth_devices, *eth_current;
 
 struct eth_device *eth_get_dev(void)
@@ -457,6 +468,53 @@ int eth_rx(void)
 	return eth_current->recv(eth_current);
 }
 
+#ifdef CONFIG_API
+static void eth_save_packet(volatile void *packet, int length)
+{
+	volatile char *p = packet;
+	int i;
+
+	if ((eth_rcv_last+1) % PKTBUFSRX == eth_rcv_current)
+		return;
+
+	if (PKTSIZE < length)
+		return;
+
+	for (i = 0; i < length; i++)
+		eth_rcv_bufs[eth_rcv_last].data[i] = p[i];
+
+	eth_rcv_bufs[eth_rcv_last].length = length;
+	eth_rcv_last = (eth_rcv_last + 1) % PKTBUFSRX;
+}
+
+int eth_receive(volatile void *packet, int length)
+{
+	volatile char *p = packet;
+	void *pp = push_packet;
+	int i;
+
+	if (eth_rcv_current == eth_rcv_last) {
+		push_packet = eth_save_packet;
+		eth_rx();
+		push_packet = pp;
+
+		if (eth_rcv_current == eth_rcv_last)
+			return -1;
+	}
+
+	if (length < eth_rcv_bufs[eth_rcv_current].length)
+		return -1;
+
+	length = eth_rcv_bufs[eth_rcv_current].length;
+
+	for (i = 0; i < length; i++)
+		p[i] = eth_rcv_bufs[eth_rcv_current].data[i];
+
+	eth_rcv_current = (eth_rcv_current + 1) % PKTBUFSRX;
+	return length;
+}
+#endif /* CONFIG_API */
+
 void eth_try_another(int first_restart)
 {
 	static struct eth_device *first_failed = NULL;
diff --git a/net/net.c b/net/net.c
index c719bc4c0..cac3e09d9 100644
--- a/net/net.c
+++ b/net/net.c
@@ -137,6 +137,9 @@ uchar		NetBcastAddr[6] =	/* Ethernet bcast address		*/
 			{ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
 uchar		NetEtherNullAddr[6] =
 			{ 0, 0, 0, 0, 0, 0 };
+#ifdef CONFIG_API
+void		(*push_packet)(volatile void *, int len) = 0;
+#endif
 #if defined(CONFIG_CMD_CDP)
 uchar		NetCDPAddr[6] =		/* Ethernet bcast address		*/
 			{ 0x01, 0x00, 0x0c, 0xcc, 0xcc, 0xcc };
@@ -1161,6 +1164,13 @@ NetReceive(volatile uchar * inpkt, int len)
 	if (len < ETHER_HDR_SIZE)
 		return;
 
+#ifdef CONFIG_API
+	if (push_packet) {
+		(*push_packet)(inpkt, len);
+		return;
+	}
+#endif
+
 #if defined(CONFIG_CMD_CDP)
 	/* keep track if packet is CDP */
 	iscdp = memcmp(et->et_dest, NetCDPAddr, 6) == 0;

From 5ca2d0953e4579a80810966cca2077e20d912c97 Mon Sep 17 00:00:00 2001
From: Shinya Kuribayashi <shinya.kuribayashi@necel.com>
Date: Mon, 19 Nov 2007 20:27:04 +0900
Subject: [PATCH 026/108] net/eth.c: Fix env_enetaddr signed overflow

Assigning the output of simple_strtoul(CB:A9:87:65:43:21) to `char', we are
warned as below:

  U-Boot 1.2.0 (Aug 30 2007 - 08:27:37)

  DRAM:  256 MB
  Flash: 32 MB
  In:    serial
  Out:   serial
  Err:   serial
  Net:   NEC-Candy
  Warning: NEC-Candy MAC addresses don't match:
  Address in SROM is         00:00:4C:80:92:A2
  Address in environment is  FFFFFFCB:FFFFFFA9:FFFFFF87:65:43:21

This patch changes env_enetaddr type from `char' to `unsigned char'.

Cc: Masaki Ishikawa <ishikawa-masaki@cnt.mxe.nes.nec.co.jp>
Signed-off-by: Shinya Kuribayashi <shinya.kuribayashi@necel.com>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
---
 net/eth.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/net/eth.c b/net/eth.c
index 4657f7970..425f29edb 100644
--- a/net/eth.c
+++ b/net/eth.c
@@ -149,7 +149,8 @@ int eth_register(struct eth_device* dev)
 
 int eth_initialize(bd_t *bis)
 {
-	char enetvar[32], env_enetaddr[6];
+	char enetvar[32];
+	unsigned char env_enetaddr[6];
 	int i, eth_number = 0;
 	char *tmp, *end;
 

From 505be87a65e4f87ad7d8da1d57ea4dcd487d7e32 Mon Sep 17 00:00:00 2001
From: Upakul Barkakaty <upakul@gmail.com>
Date: Thu, 29 Nov 2007 12:16:13 +0530
Subject: [PATCH 027/108] NET: Proper return code handling in eth_init()
 function in file eth.c

This patch modifies the return code handling in the eth_init()
function, to be compatible with the handling of the return codes in
the other network stack files. It now returns a 0 on Success and -1 on
error.

Signed-off-by: Upakul Barkakaty <upakul.barkakaty@conexant.com>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
---
 net/eth.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/net/eth.c b/net/eth.c
index 425f29edb..3373a0525 100644
--- a/net/eth.c
+++ b/net/eth.c
@@ -424,23 +424,23 @@ int eth_init(bd_t *bis)
 	struct eth_device* old_current;
 
 	if (!eth_current)
-		return 0;
+		return -1;
 
 	old_current = eth_current;
 	do {
 		debug ("Trying %s\n", eth_current->name);
 
-		if (eth_current->init(eth_current, bis)) {
+		if (!eth_current->init(eth_current,bis)) {
 			eth_current->state = ETH_STATE_ACTIVE;
 
-			return 1;
+			return 0;
 		}
 		debug  ("FAIL\n");
 
 		eth_try_another(0);
 	} while (old_current != eth_current);
 
-	return 0;
+	return -1;
 }
 
 void eth_halt(void)

From 8b0c5c127690335758100c25eaec2b84db97c101 Mon Sep 17 00:00:00 2001
From: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
Date: Thu, 27 Dec 2007 16:58:41 +0100
Subject: [PATCH 028/108] net: Add CONFIG_NET_DO_NOT_TRY_ANOTHER option

When CONFIG_NET_DO_NOT_TRY_ANOTHER is defined U-Boot's
networking stack does not automatically switch to
another interface. This patch does not touch the default
behavior.

Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
---
 net/net.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/net/net.c b/net/net.c
index cac3e09d9..44feee229 100644
--- a/net/net.c
+++ b/net/net.c
@@ -596,7 +596,9 @@ void NetStartAgain (void)
 	NetSetHandler (startAgainHandler);
 #else	/* !CONFIG_NET_MULTI*/
 	eth_halt ();
+#if !defined(CONFIG_NET_DO_NOT_TRY_ANOTHER)
 	eth_try_another (!NetRestarted);
+#endif
 	eth_init (gd->bd);
 	if (NetRestartWrap) {
 		NetRestartWrap = 0;

From ce3902e1765bbfb07cf5bbe98be9a68e3009996a Mon Sep 17 00:00:00 2001
From: Larry Johnson <lrj@arlinx.com>
Date: Sun, 30 Dec 2007 01:00:50 -0500
Subject: [PATCH 029/108] PPC4xx: Use common code for Sequoia board SDRAM
 support

Signed-off-by: Larry Johnson <lrj@acm.org>
---
 board/amcc/sequoia/sdram.c | 344 +------------------------------------
 1 file changed, 6 insertions(+), 338 deletions(-)

diff --git a/board/amcc/sequoia/sdram.c b/board/amcc/sequoia/sdram.c
index 78e2cb42a..5e93f6c7a 100644
--- a/board/amcc/sequoia/sdram.c
+++ b/board/amcc/sequoia/sdram.c
@@ -33,343 +33,11 @@
 #include <asm/io.h>
 #include <ppc440.h>
 
-#include "sdram.h"
-
-#if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) || \
-	defined(CONFIG_DDR_DATA_EYE)
 /*-----------------------------------------------------------------------------+
- * wait_for_dlllock.
- +----------------------------------------------------------------------------*/
-static int wait_for_dlllock(void)
-{
-	unsigned long val;
-	int wait = 0;
-
-	/* -----------------------------------------------------------+
-	 * Wait for the DCC master delay line to finish calibration
-	 * ----------------------------------------------------------*/
-	mtdcr(ddrcfga, DDR0_17);
-	val = DDR0_17_DLLLOCKREG_UNLOCKED;
-
-	while (wait != 0xffff) {
-		val = mfdcr(ddrcfgd);
-		if ((val & DDR0_17_DLLLOCKREG_MASK) == DDR0_17_DLLLOCKREG_LOCKED)
-			/* dlllockreg bit on */
-			return 0;
-		else
-			wait++;
-	}
-	debug("0x%04x: DDR0_17 Value (dlllockreg bit): 0x%08x\n", wait, val);
-	debug("Waiting for dlllockreg bit to raise\n");
-
-	return -1;
-}
-#endif
-
-#if defined(CONFIG_DDR_DATA_EYE)
-/*-----------------------------------------------------------------------------+
- * wait_for_dram_init_complete.
- +----------------------------------------------------------------------------*/
-int wait_for_dram_init_complete(void)
-{
-	unsigned long val;
-	int wait = 0;
-
-	/* --------------------------------------------------------------+
-	 * Wait for 'DRAM initialization complete' bit in status register
-	 * -------------------------------------------------------------*/
-	mtdcr(ddrcfga, DDR0_00);
-
-	while (wait != 0xffff) {
-		val = mfdcr(ddrcfgd);
-		if ((val & DDR0_00_INT_STATUS_BIT6) == DDR0_00_INT_STATUS_BIT6)
-			/* 'DRAM initialization complete' bit */
-			return 0;
-		else
-			wait++;
-	}
-
-	debug("DRAM initialization complete bit in status register did not rise\n");
-
-	return -1;
-}
-
-#define NUM_TRIES 64
-#define NUM_READS 10
-
-/*-----------------------------------------------------------------------------+
- * denali_core_search_data_eye.
- +----------------------------------------------------------------------------*/
-void denali_core_search_data_eye(unsigned long memory_size)
-{
-	int k, j;
-	u32 val;
-	u32 wr_dqs_shift, dqs_out_shift, dll_dqs_delay_X;
-	u32 max_passing_cases = 0, wr_dqs_shift_with_max_passing_cases = 0;
-	u32 passing_cases = 0, dll_dqs_delay_X_sw_val = 0;
-	u32 dll_dqs_delay_X_start_window = 0, dll_dqs_delay_X_end_window = 0;
-	volatile u32 *ram_pointer;
-	u32 test[NUM_TRIES] = {
-		0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
-		0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
-		0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
-		0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
-		0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
-		0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
-		0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
-		0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
-		0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
-		0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
-		0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
-		0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
-		0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
-		0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
-		0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55,
-		0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55 };
-
-	ram_pointer = (volatile u32 *)(CFG_SDRAM_BASE);
-
-	for (wr_dqs_shift = 64; wr_dqs_shift < 96; wr_dqs_shift++) {
-		/*for (wr_dqs_shift=1; wr_dqs_shift<96; wr_dqs_shift++) {*/
-
-		/* -----------------------------------------------------------+
-		 * De-assert 'start' parameter.
-		 * ----------------------------------------------------------*/
-		mtdcr(ddrcfga, DDR0_02);
-		val = (mfdcr(ddrcfgd) & ~DDR0_02_START_MASK) | DDR0_02_START_OFF;
-		mtdcr(ddrcfgd, val);
-
-		/* -----------------------------------------------------------+
-		 * Set 'wr_dqs_shift'
-		 * ----------------------------------------------------------*/
-		mtdcr(ddrcfga, DDR0_09);
-		val = (mfdcr(ddrcfgd) & ~DDR0_09_WR_DQS_SHIFT_MASK)
-			| DDR0_09_WR_DQS_SHIFT_ENCODE(wr_dqs_shift);
-		mtdcr(ddrcfgd, val);
-
-		/* -----------------------------------------------------------+
-		 * Set 'dqs_out_shift' = wr_dqs_shift + 32
-		 * ----------------------------------------------------------*/
-		dqs_out_shift = wr_dqs_shift + 32;
-		mtdcr(ddrcfga, DDR0_22);
-		val = (mfdcr(ddrcfgd) & ~DDR0_22_DQS_OUT_SHIFT_MASK)
-			| DDR0_22_DQS_OUT_SHIFT_ENCODE(dqs_out_shift);
-		mtdcr(ddrcfgd, val);
-
-		passing_cases = 0;
-
-		for (dll_dqs_delay_X = 1; dll_dqs_delay_X < 64; dll_dqs_delay_X++) {
-			/*for (dll_dqs_delay_X=1; dll_dqs_delay_X<128; dll_dqs_delay_X++) {*/
-			/* -----------------------------------------------------------+
-			 * Set 'dll_dqs_delay_X'.
-			 * ----------------------------------------------------------*/
-			/* dll_dqs_delay_0 */
-			mtdcr(ddrcfga, DDR0_17);
-			val = (mfdcr(ddrcfgd) & ~DDR0_17_DLL_DQS_DELAY_0_MASK)
-				| DDR0_17_DLL_DQS_DELAY_0_ENCODE(dll_dqs_delay_X);
-			mtdcr(ddrcfgd, val);
-			/* dll_dqs_delay_1 to dll_dqs_delay_4 */
-			mtdcr(ddrcfga, DDR0_18);
-			val = (mfdcr(ddrcfgd) & ~DDR0_18_DLL_DQS_DELAY_X_MASK)
-				| DDR0_18_DLL_DQS_DELAY_4_ENCODE(dll_dqs_delay_X)
-				| DDR0_18_DLL_DQS_DELAY_3_ENCODE(dll_dqs_delay_X)
-				| DDR0_18_DLL_DQS_DELAY_2_ENCODE(dll_dqs_delay_X)
-				| DDR0_18_DLL_DQS_DELAY_1_ENCODE(dll_dqs_delay_X);
-			mtdcr(ddrcfgd, val);
-			/* dll_dqs_delay_5 to dll_dqs_delay_8 */
-			mtdcr(ddrcfga, DDR0_19);
-			val = (mfdcr(ddrcfgd) & ~DDR0_19_DLL_DQS_DELAY_X_MASK)
-				| DDR0_19_DLL_DQS_DELAY_8_ENCODE(dll_dqs_delay_X)
-				| DDR0_19_DLL_DQS_DELAY_7_ENCODE(dll_dqs_delay_X)
-				| DDR0_19_DLL_DQS_DELAY_6_ENCODE(dll_dqs_delay_X)
-				| DDR0_19_DLL_DQS_DELAY_5_ENCODE(dll_dqs_delay_X);
-			mtdcr(ddrcfgd, val);
-
-			ppcMsync();
-			ppcMbar();
-
-			/* -----------------------------------------------------------+
-			 * Assert 'start' parameter.
-			 * ----------------------------------------------------------*/
-			mtdcr(ddrcfga, DDR0_02);
-			val = (mfdcr(ddrcfgd) & ~DDR0_02_START_MASK) | DDR0_02_START_ON;
-			mtdcr(ddrcfgd, val);
-
-			ppcMsync();
-			ppcMbar();
-
-			/* -----------------------------------------------------------+
-			 * Wait for the DCC master delay line to finish calibration
-			 * ----------------------------------------------------------*/
-			if (wait_for_dlllock() != 0) {
-				printf("dlllock did not occur !!!\n");
-				printf("denali_core_search_data_eye!!!\n");
-				printf("wr_dqs_shift = %d - dll_dqs_delay_X = %d\n",
-				       wr_dqs_shift, dll_dqs_delay_X);
-				hang();
-			}
-			ppcMsync();
-			ppcMbar();
-
-			if (wait_for_dram_init_complete() != 0) {
-				printf("dram init complete did not occur !!!\n");
-				printf("denali_core_search_data_eye!!!\n");
-				printf("wr_dqs_shift = %d - dll_dqs_delay_X = %d\n",
-				       wr_dqs_shift, dll_dqs_delay_X);
-				hang();
-			}
-			udelay(100);  /* wait 100us to ensure init is really completed !!! */
-
-			/* write values */
-			for (j=0; j<NUM_TRIES; j++) {
-				ram_pointer[j] = test[j];
-
-				/* clear any cache at ram location */
-				__asm__("dcbf 0,%0": :"r" (&ram_pointer[j]));
-			}
-
-			/* read values back */
-			for (j=0; j<NUM_TRIES; j++) {
-				for (k=0; k<NUM_READS; k++) {
-					/* clear any cache at ram location */
-					__asm__("dcbf 0,%0": :"r" (&ram_pointer[j]));
-
-					if (ram_pointer[j] != test[j])
-						break;
-				}
-
-				/* read error */
-				if (k != NUM_READS)
-					break;
-			}
-
-			/* See if the dll_dqs_delay_X value passed.*/
-			if (j < NUM_TRIES) {
-				/* Failed */
-				passing_cases = 0;
-				/* break; */
-			} else {
-				/* Passed */
-				if (passing_cases == 0)
-					dll_dqs_delay_X_sw_val = dll_dqs_delay_X;
-				passing_cases++;
-				if (passing_cases >= max_passing_cases) {
-					max_passing_cases = passing_cases;
-					wr_dqs_shift_with_max_passing_cases = wr_dqs_shift;
-					dll_dqs_delay_X_start_window = dll_dqs_delay_X_sw_val;
-					dll_dqs_delay_X_end_window = dll_dqs_delay_X;
-				}
-			}
-
-			/* -----------------------------------------------------------+
-			 * De-assert 'start' parameter.
-			 * ----------------------------------------------------------*/
-			mtdcr(ddrcfga, DDR0_02);
-			val = (mfdcr(ddrcfgd) & ~DDR0_02_START_MASK) | DDR0_02_START_OFF;
-			mtdcr(ddrcfgd, val);
-
-		} /* for (dll_dqs_delay_X=0; dll_dqs_delay_X<128; dll_dqs_delay_X++) */
-
-	} /* for (wr_dqs_shift=0; wr_dqs_shift<96; wr_dqs_shift++) */
-
-	/* -----------------------------------------------------------+
-	 * Largest passing window is now detected.
-	 * ----------------------------------------------------------*/
-
-	/* Compute dll_dqs_delay_X value */
-	dll_dqs_delay_X = (dll_dqs_delay_X_end_window + dll_dqs_delay_X_start_window) / 2;
-	wr_dqs_shift = wr_dqs_shift_with_max_passing_cases;
-
-	debug("DQS calibration - Window detected:\n");
-	debug("max_passing_cases = %d\n", max_passing_cases);
-	debug("wr_dqs_shift      = %d\n", wr_dqs_shift);
-	debug("dll_dqs_delay_X   = %d\n", dll_dqs_delay_X);
-	debug("dll_dqs_delay_X window = %d - %d\n",
-	       dll_dqs_delay_X_start_window, dll_dqs_delay_X_end_window);
-
-	/* -----------------------------------------------------------+
-	 * De-assert 'start' parameter.
-	 * ----------------------------------------------------------*/
-	mtdcr(ddrcfga, DDR0_02);
-	val = (mfdcr(ddrcfgd) & ~DDR0_02_START_MASK) | DDR0_02_START_OFF;
-	mtdcr(ddrcfgd, val);
-
-	/* -----------------------------------------------------------+
-	 * Set 'wr_dqs_shift'
-	 * ----------------------------------------------------------*/
-	mtdcr(ddrcfga, DDR0_09);
-	val = (mfdcr(ddrcfgd) & ~DDR0_09_WR_DQS_SHIFT_MASK)
-		| DDR0_09_WR_DQS_SHIFT_ENCODE(wr_dqs_shift);
-	mtdcr(ddrcfgd, val);
-	debug("DDR0_09=0x%08lx\n", val);
-
-	/* -----------------------------------------------------------+
-	 * Set 'dqs_out_shift' = wr_dqs_shift + 32
-	 * ----------------------------------------------------------*/
-	dqs_out_shift = wr_dqs_shift + 32;
-	mtdcr(ddrcfga, DDR0_22);
-	val = (mfdcr(ddrcfgd) & ~DDR0_22_DQS_OUT_SHIFT_MASK)
-		| DDR0_22_DQS_OUT_SHIFT_ENCODE(dqs_out_shift);
-	mtdcr(ddrcfgd, val);
-	debug("DDR0_22=0x%08lx\n", val);
-
-	/* -----------------------------------------------------------+
-	 * Set 'dll_dqs_delay_X'.
-	 * ----------------------------------------------------------*/
-	/* dll_dqs_delay_0 */
-	mtdcr(ddrcfga, DDR0_17);
-	val = (mfdcr(ddrcfgd) & ~DDR0_17_DLL_DQS_DELAY_0_MASK)
-		| DDR0_17_DLL_DQS_DELAY_0_ENCODE(dll_dqs_delay_X);
-	mtdcr(ddrcfgd, val);
-	debug("DDR0_17=0x%08lx\n", val);
-
-	/* dll_dqs_delay_1 to dll_dqs_delay_4 */
-	mtdcr(ddrcfga, DDR0_18);
-	val = (mfdcr(ddrcfgd) & ~DDR0_18_DLL_DQS_DELAY_X_MASK)
-		| DDR0_18_DLL_DQS_DELAY_4_ENCODE(dll_dqs_delay_X)
-		| DDR0_18_DLL_DQS_DELAY_3_ENCODE(dll_dqs_delay_X)
-		| DDR0_18_DLL_DQS_DELAY_2_ENCODE(dll_dqs_delay_X)
-		| DDR0_18_DLL_DQS_DELAY_1_ENCODE(dll_dqs_delay_X);
-	mtdcr(ddrcfgd, val);
-	debug("DDR0_18=0x%08lx\n", val);
-
-	/* dll_dqs_delay_5 to dll_dqs_delay_8 */
-	mtdcr(ddrcfga, DDR0_19);
-	val = (mfdcr(ddrcfgd) & ~DDR0_19_DLL_DQS_DELAY_X_MASK)
-		| DDR0_19_DLL_DQS_DELAY_8_ENCODE(dll_dqs_delay_X)
-		| DDR0_19_DLL_DQS_DELAY_7_ENCODE(dll_dqs_delay_X)
-		| DDR0_19_DLL_DQS_DELAY_6_ENCODE(dll_dqs_delay_X)
-		| DDR0_19_DLL_DQS_DELAY_5_ENCODE(dll_dqs_delay_X);
-	mtdcr(ddrcfgd, val);
-	debug("DDR0_19=0x%08lx\n", val);
-
-	/* -----------------------------------------------------------+
-	 * Assert 'start' parameter.
-	 * ----------------------------------------------------------*/
-	mtdcr(ddrcfga, DDR0_02);
-	val = (mfdcr(ddrcfgd) & ~DDR0_02_START_MASK) | DDR0_02_START_ON;
-	mtdcr(ddrcfgd, val);
-
-	ppcMsync();
-	ppcMbar();
-
-	/* -----------------------------------------------------------+
-	 * Wait for the DCC master delay line to finish calibration
-	 * ----------------------------------------------------------*/
-	if (wait_for_dlllock() != 0) {
-		printf("dlllock did not occur !!!\n");
-		hang();
-	}
-	ppcMsync();
-	ppcMbar();
-
-	if (wait_for_dram_init_complete() != 0) {
-		printf("dram init complete did not occur !!!\n");
-		hang();
-	}
-	udelay(100);  /* wait 100us to ensure init is really completed !!! */
-}
-#endif /* CONFIG_DDR_DATA_EYE */
+ * Prototypes
+ *-----------------------------------------------------------------------------*/
+extern int denali_wait_for_dlllock(void);
+extern void denali_core_search_data_eye(void);
 
 #if defined(CONFIG_NAND_SPL)
 /* Using cpu/ppc4xx/speed.c to calculate the bus frequency is too big
@@ -428,14 +96,14 @@ long int initdram (int board_type)
 	mtsdram(DDR0_44, 0x00000003);
 	mtsdram(DDR0_02, 0x00000001);
 
-	wait_for_dlllock();
+	denali_wait_for_dlllock();
 #endif /* #ifndef CONFIG_NAND_U_BOOT */
 
 #ifdef CONFIG_DDR_DATA_EYE
 	/* -----------------------------------------------------------+
 	 * Perform data eye search if requested.
 	 * ----------------------------------------------------------*/
-	denali_core_search_data_eye(CFG_MBYTES_SDRAM << 20);
+	denali_core_search_data_eye();
 #endif
 
 	return (CFG_MBYTES_SDRAM << 20);

From 62cc3951ab72135d9c101f1845b794e63a0fa189 Mon Sep 17 00:00:00 2001
From: Larry Johnson <lrj@arlinx.com>
Date: Sun, 30 Dec 2007 01:01:14 -0500
Subject: [PATCH 030/108] PPC4xx: Remove sdram.h from board/amcc/sequoia

These definitions are now in "include/ppc440.h".

Signed-off-by: Larry Johnson <lrj@acm.org>
---
 board/amcc/sequoia/sdram.h | 505 -------------------------------------
 1 file changed, 505 deletions(-)
 delete mode 100644 board/amcc/sequoia/sdram.h

diff --git a/board/amcc/sequoia/sdram.h b/board/amcc/sequoia/sdram.h
deleted file mode 100644
index 6a7bf01ef..000000000
--- a/board/amcc/sequoia/sdram.h
+++ /dev/null
@@ -1,505 +0,0 @@
-/*
- * (C) Copyright 2006
- * Sylvie Gohl,             AMCC/IBM, gohl.sylvie@fr.ibm.com
- * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
- * Thierry Roman,           AMCC/IBM, thierry_roman@fr.ibm.com
- * Alain Saurel,            AMCC/IBM, alain.saurel@fr.ibm.com
- * Robert Snyder,           AMCC/IBM, rob.snyder@fr.ibm.com
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef _SPD_SDRAM_DENALI_H_
-#define _SPD_SDRAM_DENALI_H_
-
-#define ppcMsync	sync
-#define ppcMbar		eieio
-
-/* General definitions */
-#define MAX_SPD_BYTE        128         /* highest SPD byte # to read */
-#define DENALI_REG_NUMBER   45          /* 45 Regs in PPC440EPx Denali Core */
-#define SUPPORTED_DIMMS_NB  7           /* Number of supported DIMM modules types */
-#define SDRAM_NONE          0           /* No DIMM detected in Slot */
-#define MAXRANKS            2           /* 2 ranks maximum */
-
-/* Supported PLB Frequencies */
-#define PLB_FREQ_133MHZ     133333333
-#define PLB_FREQ_152MHZ     152000000
-#define PLB_FREQ_160MHZ     160000000
-#define PLB_FREQ_166MHZ     166666666
-
-/* Denali Core Registers */
-#define SDRAM_DCR_BASE 0x10
-
-#define DDR_DCR_BASE 0x10
-#define ddrcfga  (DDR_DCR_BASE+0x0)   /* DDR configuration address reg */
-#define ddrcfgd  (DDR_DCR_BASE+0x1)   /* DDR configuration data reg    */
-
-/*-----------------------------------------------------------------------------+
-  | Values for ddrcfga register - indirect addressing of these regs
-  +-----------------------------------------------------------------------------*/
-
-#define DDR0_00                         0x00
-#define DDR0_00_INT_ACK_MASK              0x7F000000 /* Write only */
-#define DDR0_00_INT_ACK_ALL               0x7F000000
-#define DDR0_00_INT_ACK_ENCODE(n)           ((((unsigned long)(n))&0x7F)<<24)
-#define DDR0_00_INT_ACK_DECODE(n)           ((((unsigned long)(n))>>24)&0x7F)
-/* Status */
-#define DDR0_00_INT_STATUS_MASK           0x00FF0000 /* Read only */
-/* Bit0. A single access outside the defined PHYSICAL memory space detected. */
-#define DDR0_00_INT_STATUS_BIT0           0x00010000
-/* Bit1. Multiple accesses outside the defined PHYSICAL memory space detected. */
-#define DDR0_00_INT_STATUS_BIT1           0x00020000
-/* Bit2. Single correctable ECC event detected */
-#define DDR0_00_INT_STATUS_BIT2           0x00040000
-/* Bit3. Multiple correctable ECC events detected. */
-#define DDR0_00_INT_STATUS_BIT3           0x00080000
-/* Bit4. Single uncorrectable ECC event detected. */
-#define DDR0_00_INT_STATUS_BIT4           0x00100000
-/* Bit5. Multiple uncorrectable ECC events detected. */
-#define DDR0_00_INT_STATUS_BIT5           0x00200000
-/* Bit6. DRAM initialization complete. */
-#define DDR0_00_INT_STATUS_BIT6           0x00400000
-/* Bit7. Logical OR of all lower bits. */
-#define DDR0_00_INT_STATUS_BIT7           0x00800000
-
-#define DDR0_00_INT_STATUS_ENCODE(n)        ((((unsigned long)(n))&0xFF)<<16)
-#define DDR0_00_INT_STATUS_DECODE(n)        ((((unsigned long)(n))>>16)&0xFF)
-#define DDR0_00_DLL_INCREMENT_MASK        0x00007F00
-#define DDR0_00_DLL_INCREMENT_ENCODE(n)     ((((unsigned long)(n))&0x7F)<<8)
-#define DDR0_00_DLL_INCREMENT_DECODE(n)     ((((unsigned long)(n))>>8)&0x7F)
-#define DDR0_00_DLL_START_POINT_MASK      0x0000007F
-#define DDR0_00_DLL_START_POINT_ENCODE(n)   ((((unsigned long)(n))&0x7F)<<0)
-#define DDR0_00_DLL_START_POINT_DECODE(n)   ((((unsigned long)(n))>>0)&0x7F)
-
-
-#define DDR0_01                         0x01
-#define DDR0_01_PLB0_DB_CS_LOWER_MASK     0x1F000000
-#define DDR0_01_PLB0_DB_CS_LOWER_ENCODE(n)  ((((unsigned long)(n))&0x1F)<<24)
-#define DDR0_01_PLB0_DB_CS_LOWER_DECODE(n)  ((((unsigned long)(n))>>24)&0x1F)
-#define DDR0_01_PLB0_DB_CS_UPPER_MASK     0x001F0000
-#define DDR0_01_PLB0_DB_CS_UPPER_ENCODE(n)  ((((unsigned long)(n))&0x1F)<<16)
-#define DDR0_01_PLB0_DB_CS_UPPER_DECODE(n)  ((((unsigned long)(n))>>16)&0x1F)
-#define DDR0_01_OUT_OF_RANGE_TYPE_MASK    0x00000700 /* Read only */
-#define DDR0_01_OUT_OF_RANGE_TYPE_ENCODE(n)               ((((unsigned long)(n))&0x7)<<8)
-#define DDR0_01_OUT_OF_RANGE_TYPE_DECODE(n)               ((((unsigned long)(n))>>8)&0x7)
-#define DDR0_01_INT_MASK_MASK             0x000000FF
-#define DDR0_01_INT_MASK_ENCODE(n)          ((((unsigned long)(n))&0xFF)<<0)
-#define DDR0_01_INT_MASK_DECODE(n)          ((((unsigned long)(n))>>0)&0xFF)
-#define DDR0_01_INT_MASK_ALL_ON           0x000000FF
-#define DDR0_01_INT_MASK_ALL_OFF          0x00000000
-
-#define DDR0_02                         0x02
-#define DDR0_02_MAX_CS_REG_MASK           0x02000000 /* Read only */
-#define DDR0_02_MAX_CS_REG_ENCODE(n)        ((((unsigned long)(n))&0x2)<<24)
-#define DDR0_02_MAX_CS_REG_DECODE(n)        ((((unsigned long)(n))>>24)&0x2)
-#define DDR0_02_MAX_COL_REG_MASK          0x000F0000 /* Read only */
-#define DDR0_02_MAX_COL_REG_ENCODE(n)       ((((unsigned long)(n))&0xF)<<16)
-#define DDR0_02_MAX_COL_REG_DECODE(n)       ((((unsigned long)(n))>>16)&0xF)
-#define DDR0_02_MAX_ROW_REG_MASK          0x00000F00 /* Read only */
-#define DDR0_02_MAX_ROW_REG_ENCODE(n)       ((((unsigned long)(n))&0xF)<<8)
-#define DDR0_02_MAX_ROW_REG_DECODE(n)       ((((unsigned long)(n))>>8)&0xF)
-#define DDR0_02_START_MASK                0x00000001
-#define DDR0_02_START_ENCODE(n)             ((((unsigned long)(n))&0x1)<<0)
-#define DDR0_02_START_DECODE(n)             ((((unsigned long)(n))>>0)&0x1)
-#define DDR0_02_START_OFF                 0x00000000
-#define DDR0_02_START_ON                  0x00000001
-
-#define DDR0_03                         0x03
-#define DDR0_03_BSTLEN_MASK               0x07000000
-#define DDR0_03_BSTLEN_ENCODE(n)            ((((unsigned long)(n))&0x7)<<24)
-#define DDR0_03_BSTLEN_DECODE(n)            ((((unsigned long)(n))>>24)&0x7)
-#define DDR0_03_CASLAT_MASK               0x00070000
-#define DDR0_03_CASLAT_ENCODE(n)            ((((unsigned long)(n))&0x7)<<16)
-#define DDR0_03_CASLAT_DECODE(n)            ((((unsigned long)(n))>>16)&0x7)
-#define DDR0_03_CASLAT_LIN_MASK           0x00000F00
-#define DDR0_03_CASLAT_LIN_ENCODE(n)        ((((unsigned long)(n))&0xF)<<8)
-#define DDR0_03_CASLAT_LIN_DECODE(n)        ((((unsigned long)(n))>>8)&0xF)
-#define DDR0_03_INITAREF_MASK             0x0000000F
-#define DDR0_03_INITAREF_ENCODE(n)          ((((unsigned long)(n))&0xF)<<0)
-#define DDR0_03_INITAREF_DECODE(n)          ((((unsigned long)(n))>>0)&0xF)
-
-#define DDR0_04                         0x04
-#define DDR0_04_TRC_MASK                  0x1F000000
-#define DDR0_04_TRC_ENCODE(n)               ((((unsigned long)(n))&0x1F)<<24)
-#define DDR0_04_TRC_DECODE(n)               ((((unsigned long)(n))>>24)&0x1F)
-#define DDR0_04_TRRD_MASK                 0x00070000
-#define DDR0_04_TRRD_ENCODE(n)              ((((unsigned long)(n))&0x7)<<16)
-#define DDR0_04_TRRD_DECODE(n)              ((((unsigned long)(n))>>16)&0x7)
-#define DDR0_04_TRTP_MASK                 0x00000700
-#define DDR0_04_TRTP_ENCODE(n)              ((((unsigned long)(n))&0x7)<<8)
-#define DDR0_04_TRTP_DECODE(n)              ((((unsigned long)(n))>>8)&0x7)
-
-#define DDR0_05                         0x05
-#define DDR0_05_TMRD_MASK                 0x1F000000
-#define DDR0_05_TMRD_ENCODE(n)              ((((unsigned long)(n))&0x1F)<<24)
-#define DDR0_05_TMRD_DECODE(n)              ((((unsigned long)(n))>>24)&0x1F)
-#define DDR0_05_TEMRS_MASK                0x00070000
-#define DDR0_05_TEMRS_ENCODE(n)             ((((unsigned long)(n))&0x7)<<16)
-#define DDR0_05_TEMRS_DECODE(n)             ((((unsigned long)(n))>>16)&0x7)
-#define DDR0_05_TRP_MASK                  0x00000F00
-#define DDR0_05_TRP_ENCODE(n)               ((((unsigned long)(n))&0xF)<<8)
-#define DDR0_05_TRP_DECODE(n)               ((((unsigned long)(n))>>8)&0xF)
-#define DDR0_05_TRAS_MIN_MASK             0x000000FF
-#define DDR0_05_TRAS_MIN_ENCODE(n)          ((((unsigned long)(n))&0xFF)<<0)
-#define DDR0_05_TRAS_MIN_DECODE(n)          ((((unsigned long)(n))>>0)&0xFF)
-
-#define DDR0_06                         0x06
-#define DDR0_06_WRITEINTERP_MASK          0x01000000
-#define DDR0_06_WRITEINTERP_ENCODE(n)       ((((unsigned long)(n))&0x1)<<24)
-#define DDR0_06_WRITEINTERP_DECODE(n)       ((((unsigned long)(n))>>24)&0x1)
-#define DDR0_06_TWTR_MASK                 0x00070000
-#define DDR0_06_TWTR_ENCODE(n)              ((((unsigned long)(n))&0x7)<<16)
-#define DDR0_06_TWTR_DECODE(n)              ((((unsigned long)(n))>>16)&0x7)
-#define DDR0_06_TDLL_MASK                 0x0000FF00
-#define DDR0_06_TDLL_ENCODE(n)              ((((unsigned long)(n))&0xFF)<<8)
-#define DDR0_06_TDLL_DECODE(n)              ((((unsigned long)(n))>>8)&0xFF)
-#define DDR0_06_TRFC_MASK                 0x0000007F
-#define DDR0_06_TRFC_ENCODE(n)              ((((unsigned long)(n))&0x7F)<<0)
-#define DDR0_06_TRFC_DECODE(n)              ((((unsigned long)(n))>>0)&0x7F)
-
-#define DDR0_07                         0x07
-#define DDR0_07_NO_CMD_INIT_MASK          0x01000000
-#define DDR0_07_NO_CMD_INIT_ENCODE(n)       ((((unsigned long)(n))&0x1)<<24)
-#define DDR0_07_NO_CMD_INIT_DECODE(n)       ((((unsigned long)(n))>>24)&0x1)
-#define DDR0_07_TFAW_MASK                 0x001F0000
-#define DDR0_07_TFAW_ENCODE(n)              ((((unsigned long)(n))&0x1F)<<16)
-#define DDR0_07_TFAW_DECODE(n)              ((((unsigned long)(n))>>16)&0x1F)
-#define DDR0_07_AUTO_REFRESH_MODE_MASK    0x00000100
-#define DDR0_07_AUTO_REFRESH_MODE_ENCODE(n) ((((unsigned long)(n))&0x1)<<8)
-#define DDR0_07_AUTO_REFRESH_MODE_DECODE(n) ((((unsigned long)(n))>>8)&0x1)
-#define DDR0_07_AREFRESH_MASK             0x00000001
-#define DDR0_07_AREFRESH_ENCODE(n)          ((((unsigned long)(n))&0x1)<<0)
-#define DDR0_07_AREFRESH_DECODE(n)          ((((unsigned long)(n))>>0)&0x1)
-
-#define DDR0_08                         0x08
-#define DDR0_08_WRLAT_MASK                0x07000000
-#define DDR0_08_WRLAT_ENCODE(n)             ((((unsigned long)(n))&0x7)<<24)
-#define DDR0_08_WRLAT_DECODE(n)             ((((unsigned long)(n))>>24)&0x7)
-#define DDR0_08_TCPD_MASK                 0x00FF0000
-#define DDR0_08_TCPD_ENCODE(n)              ((((unsigned long)(n))&0xFF)<<16)
-#define DDR0_08_TCPD_DECODE(n)              ((((unsigned long)(n))>>16)&0xFF)
-#define DDR0_08_DQS_N_EN_MASK             0x00000100
-#define DDR0_08_DQS_N_EN_ENCODE(n)          ((((unsigned long)(n))&0x1)<<8)
-#define DDR0_08_DQS_N_EN_DECODE(n)          ((((unsigned long)(n))>>8)&0x1)
-#define DDR0_08_DDRII_SDRAM_MODE_MASK     0x00000001
-#define DDR0_08_DDRII_ENCODE(n)             ((((unsigned long)(n))&0x1)<<0)
-#define DDR0_08_DDRII_DECODE(n)             ((((unsigned long)(n))>>0)&0x1)
-
-#define DDR0_09                         0x09
-#define DDR0_09_OCD_ADJUST_PDN_CS_0_MASK  0x1F000000
-#define DDR0_09_OCD_ADJUST_PDN_CS_0_ENCODE(n) ((((unsigned long)(n))&0x1F)<<24)
-#define DDR0_09_OCD_ADJUST_PDN_CS_0_DECODE(n) ((((unsigned long)(n))>>24)&0x1F)
-#define DDR0_09_RTT_0_MASK                0x00030000
-#define DDR0_09_RTT_0_ENCODE(n)             ((((unsigned long)(n))&0x3)<<16)
-#define DDR0_09_RTT_0_DECODE(n)             ((((unsigned long)(n))>>16)&0x3)
-#define DDR0_09_WR_DQS_SHIFT_BYPASS_MASK  0x00007F00
-#define DDR0_09_WR_DQS_SHIFT_BYPASS_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8)
-#define DDR0_09_WR_DQS_SHIFT_BYPASS_DECODE(n) ((((unsigned long)(n))>>8)&0x7F)
-#define DDR0_09_WR_DQS_SHIFT_MASK         0x0000007F
-#define DDR0_09_WR_DQS_SHIFT_ENCODE(n)      ((((unsigned long)(n))&0x7F)<<0)
-#define DDR0_09_WR_DQS_SHIFT_DECODE(n)      ((((unsigned long)(n))>>0)&0x7F)
-
-#define DDR0_10                         0x0A
-#define DDR0_10_WRITE_MODEREG_MASK        0x00010000 /* Write only */
-#define DDR0_10_WRITE_MODEREG_ENCODE(n)     ((((unsigned long)(n))&0x1)<<16)
-#define DDR0_10_WRITE_MODEREG_DECODE(n)     ((((unsigned long)(n))>>16)&0x1)
-#define DDR0_10_CS_MAP_MASK               0x00000300
-#define DDR0_10_CS_MAP_NO_MEM             0x00000000
-#define DDR0_10_CS_MAP_RANK0_INSTALLED    0x00000100
-#define DDR0_10_CS_MAP_RANK1_INSTALLED    0x00000200
-#define DDR0_10_CS_MAP_ENCODE(n)            ((((unsigned long)(n))&0x3)<<8)
-#define DDR0_10_CS_MAP_DECODE(n)            ((((unsigned long)(n))>>8)&0x3)
-#define DDR0_10_OCD_ADJUST_PUP_CS_0_MASK  0x0000001F
-#define DDR0_10_OCD_ADJUST_PUP_CS_0_ENCODE(n) ((((unsigned long)(n))&0x1F)<<0)
-#define DDR0_10_OCD_ADJUST_PUP_CS_0_DECODE(n) ((((unsigned long)(n))>>0)&0x1F)
-
-#define DDR0_11                         0x0B
-#define DDR0_11_SREFRESH_MASK             0x01000000
-#define DDR0_11_SREFRESH_ENCODE(n)          ((((unsigned long)(n))&0x1)<<24)
-#define DDR0_11_SREFRESH_DECODE(n)          ((((unsigned long)(n))>>24)&0x1F)
-#define DDR0_11_TXSNR_MASK                0x00FF0000
-#define DDR0_11_TXSNR_ENCODE(n)             ((((unsigned long)(n))&0xFF)<<16)
-#define DDR0_11_TXSNR_DECODE(n)             ((((unsigned long)(n))>>16)&0xFF)
-#define DDR0_11_TXSR_MASK                 0x0000FF00
-#define DDR0_11_TXSR_ENCODE(n)              ((((unsigned long)(n))&0xFF)<<8)
-#define DDR0_11_TXSR_DECODE(n)              ((((unsigned long)(n))>>8)&0xFF)
-
-#define DDR0_12                         0x0C
-#define DDR0_12_TCKE_MASK                 0x0000007
-#define DDR0_12_TCKE_ENCODE(n)              ((((unsigned long)(n))&0x7)<<0)
-#define DDR0_12_TCKE_DECODE(n)              ((((unsigned long)(n))>>0)&0x7)
-
-#define DDR0_13                         0x0D
-
-#define DDR0_14                         0x0E
-#define DDR0_14_DLL_BYPASS_MODE_MASK      0x01000000
-#define DDR0_14_DLL_BYPASS_MODE_ENCODE(n)   ((((unsigned long)(n))&0x1)<<24)
-#define DDR0_14_DLL_BYPASS_MODE_DECODE(n)   ((((unsigned long)(n))>>24)&0x1)
-#define DDR0_14_REDUC_MASK                0x00010000
-#define DDR0_14_REDUC_64BITS              0x00000000
-#define DDR0_14_REDUC_32BITS              0x00010000
-#define DDR0_14_REDUC_ENCODE(n)             ((((unsigned long)(n))&0x1)<<16)
-#define DDR0_14_REDUC_DECODE(n)             ((((unsigned long)(n))>>16)&0x1)
-#define DDR0_14_REG_DIMM_ENABLE_MASK      0x00000100
-#define DDR0_14_REG_DIMM_ENABLE_ENCODE(n)   ((((unsigned long)(n))&0x1)<<8)
-#define DDR0_14_REG_DIMM_ENABLE_DECODE(n)   ((((unsigned long)(n))>>8)&0x1)
-
-#define DDR0_15                         0x0F
-
-#define DDR0_16                         0x10
-
-#define DDR0_17                         0x11
-#define DDR0_17_DLL_DQS_DELAY_0_MASK      0x7F000000
-#define DDR0_17_DLL_DQS_DELAY_0_ENCODE(n)   ((((unsigned long)(n))&0x7F)<<24)
-#define DDR0_17_DLL_DQS_DELAY_0_DECODE(n)   ((((unsigned long)(n))>>24)&0x7F)
-#define DDR0_17_DLLLOCKREG_MASK           0x00010000 /* Read only */
-#define DDR0_17_DLLLOCKREG_LOCKED         0x00010000
-#define DDR0_17_DLLLOCKREG_UNLOCKED       0x00000000
-#define DDR0_17_DLLLOCKREG_ENCODE(n)        ((((unsigned long)(n))&0x1)<<16)
-#define DDR0_17_DLLLOCKREG_DECODE(n)        ((((unsigned long)(n))>>16)&0x1)
-#define DDR0_17_DLL_LOCK_MASK             0x00007F00 /* Read only */
-#define DDR0_17_DLL_LOCK_ENCODE(n)          ((((unsigned long)(n))&0x7F)<<8)
-#define DDR0_17_DLL_LOCK_DECODE(n)          ((((unsigned long)(n))>>8)&0x7F)
-
-#define DDR0_18                         0x12
-#define DDR0_18_DLL_DQS_DELAY_X_MASK      0x7F7F7F7F
-#define DDR0_18_DLL_DQS_DELAY_4_MASK      0x7F000000
-#define DDR0_18_DLL_DQS_DELAY_4_ENCODE(n)   ((((unsigned long)(n))&0x7F)<<24)
-#define DDR0_18_DLL_DQS_DELAY_4_DECODE(n)   ((((unsigned long)(n))>>24)&0x7F)
-#define DDR0_18_DLL_DQS_DELAY_3_MASK      0x007F0000
-#define DDR0_18_DLL_DQS_DELAY_3_ENCODE(n)   ((((unsigned long)(n))&0x7F)<<16)
-#define DDR0_18_DLL_DQS_DELAY_3_DECODE(n)   ((((unsigned long)(n))>>16)&0x7F)
-#define DDR0_18_DLL_DQS_DELAY_2_MASK      0x00007F00
-#define DDR0_18_DLL_DQS_DELAY_2_ENCODE(n)   ((((unsigned long)(n))&0x7F)<<8)
-#define DDR0_18_DLL_DQS_DELAY_2_DECODE(n)   ((((unsigned long)(n))>>8)&0x7F)
-#define DDR0_18_DLL_DQS_DELAY_1_MASK      0x0000007F
-#define DDR0_18_DLL_DQS_DELAY_1_ENCODE(n)   ((((unsigned long)(n))&0x7F)<<0)
-#define DDR0_18_DLL_DQS_DELAY_1_DECODE(n)   ((((unsigned long)(n))>>0)&0x7F)
-
-#define DDR0_19                         0x13
-#define DDR0_19_DLL_DQS_DELAY_X_MASK      0x7F7F7F7F
-#define DDR0_19_DLL_DQS_DELAY_8_MASK      0x7F000000
-#define DDR0_19_DLL_DQS_DELAY_8_ENCODE(n)   ((((unsigned long)(n))&0x7F)<<24)
-#define DDR0_19_DLL_DQS_DELAY_8_DECODE(n)   ((((unsigned long)(n))>>24)&0x7F)
-#define DDR0_19_DLL_DQS_DELAY_7_MASK      0x007F0000
-#define DDR0_19_DLL_DQS_DELAY_7_ENCODE(n)   ((((unsigned long)(n))&0x7F)<<16)
-#define DDR0_19_DLL_DQS_DELAY_7_DECODE(n)   ((((unsigned long)(n))>>16)&0x7F)
-#define DDR0_19_DLL_DQS_DELAY_6_MASK      0x00007F00
-#define DDR0_19_DLL_DQS_DELAY_6_ENCODE(n)   ((((unsigned long)(n))&0x7F)<<8)
-#define DDR0_19_DLL_DQS_DELAY_6_DECODE(n)   ((((unsigned long)(n))>>8)&0x7F)
-#define DDR0_19_DLL_DQS_DELAY_5_MASK      0x0000007F
-#define DDR0_19_DLL_DQS_DELAY_5_ENCODE(n)   ((((unsigned long)(n))&0x7F)<<0)
-#define DDR0_19_DLL_DQS_DELAY_5_DECODE(n)   ((((unsigned long)(n))>>0)&0x7F)
-
-#define DDR0_20                         0x14
-#define DDR0_20_DLL_DQS_BYPASS_3_MASK      0x7F000000
-#define DDR0_20_DLL_DQS_BYPASS_3_ENCODE(n)   ((((unsigned long)(n))&0x7F)<<24)
-#define DDR0_20_DLL_DQS_BYPASS_3_DECODE(n)   ((((unsigned long)(n))>>24)&0x7F)
-#define DDR0_20_DLL_DQS_BYPASS_2_MASK      0x007F0000
-#define DDR0_20_DLL_DQS_BYPASS_2_ENCODE(n)   ((((unsigned long)(n))&0x7F)<<16)
-#define DDR0_20_DLL_DQS_BYPASS_2_DECODE(n)   ((((unsigned long)(n))>>16)&0x7F)
-#define DDR0_20_DLL_DQS_BYPASS_1_MASK      0x00007F00
-#define DDR0_20_DLL_DQS_BYPASS_1_ENCODE(n)   ((((unsigned long)(n))&0x7F)<<8)
-#define DDR0_20_DLL_DQS_BYPASS_1_DECODE(n)   ((((unsigned long)(n))>>8)&0x7F)
-#define DDR0_20_DLL_DQS_BYPASS_0_MASK      0x0000007F
-#define DDR0_20_DLL_DQS_BYPASS_0_ENCODE(n)   ((((unsigned long)(n))&0x7F)<<0)
-#define DDR0_20_DLL_DQS_BYPASS_0_DECODE(n)   ((((unsigned long)(n))>>0)&0x7F)
-
-#define DDR0_21                         0x15
-#define DDR0_21_DLL_DQS_BYPASS_7_MASK      0x7F000000
-#define DDR0_21_DLL_DQS_BYPASS_7_ENCODE(n)   ((((unsigned long)(n))&0x7F)<<24)
-#define DDR0_21_DLL_DQS_BYPASS_7_DECODE(n)   ((((unsigned long)(n))>>24)&0x7F)
-#define DDR0_21_DLL_DQS_BYPASS_6_MASK      0x007F0000
-#define DDR0_21_DLL_DQS_BYPASS_6_ENCODE(n)   ((((unsigned long)(n))&0x7F)<<16)
-#define DDR0_21_DLL_DQS_BYPASS_6_DECODE(n)   ((((unsigned long)(n))>>16)&0x7F)
-#define DDR0_21_DLL_DQS_BYPASS_5_MASK      0x00007F00
-#define DDR0_21_DLL_DQS_BYPASS_5_ENCODE(n)   ((((unsigned long)(n))&0x7F)<<8)
-#define DDR0_21_DLL_DQS_BYPASS_5_DECODE(n)   ((((unsigned long)(n))>>8)&0x7F)
-#define DDR0_21_DLL_DQS_BYPASS_4_MASK      0x0000007F
-#define DDR0_21_DLL_DQS_BYPASS_4_ENCODE(n)   ((((unsigned long)(n))&0x7F)<<0)
-#define DDR0_21_DLL_DQS_BYPASS_4_DECODE(n)   ((((unsigned long)(n))>>0)&0x7F)
-
-#define DDR0_22                         0x16
-/* ECC */
-#define DDR0_22_CTRL_RAW_MASK             0x03000000
-#define DDR0_22_CTRL_RAW_ECC_DISABLE      0x00000000 /* ECC not being used */
-#define DDR0_22_CTRL_RAW_ECC_CHECK_ONLY   0x01000000 /* ECC checking is on, but no attempts to correct*/
-#define DDR0_22_CTRL_RAW_NO_ECC_RAM       0x02000000 /* No ECC RAM storage available */
-#define DDR0_22_CTRL_RAW_ECC_ENABLE       0x03000000 /* ECC checking and correcting on */
-#define DDR0_22_CTRL_RAW_ENCODE(n)          ((((unsigned long)(n))&0x3)<<24)
-#define DDR0_22_CTRL_RAW_DECODE(n)          ((((unsigned long)(n))>>24)&0x3)
-
-#define DDR0_22_DQS_OUT_SHIFT_BYPASS_MASK 0x007F0000
-#define DDR0_22_DQS_OUT_SHIFT_BYPASS_ENCODE(n) ((((unsigned long)(n))&0x7F)<<16)
-#define DDR0_22_DQS_OUT_SHIFT_BYPASS_DECODE(n) ((((unsigned long)(n))>>16)&0x7F)
-#define DDR0_22_DQS_OUT_SHIFT_MASK        0x00007F00
-#define DDR0_22_DQS_OUT_SHIFT_ENCODE(n)     ((((unsigned long)(n))&0x7F)<<8)
-#define DDR0_22_DQS_OUT_SHIFT_DECODE(n)     ((((unsigned long)(n))>>8)&0x7F)
-#define DDR0_22_DLL_DQS_BYPASS_8_MASK     0x0000007F
-#define DDR0_22_DLL_DQS_BYPASS_8_ENCODE(n)  ((((unsigned long)(n))&0x7F)<<0)
-#define DDR0_22_DLL_DQS_BYPASS_8_DECODE(n)  ((((unsigned long)(n))>>0)&0x7F)
-
-
-#define DDR0_23                         0x17
-#define DDR0_23_ODT_RD_MAP_CS0_MASK       0x03000000
-#define DDR0_23_ODT_RD_MAP_CS0_ENCODE(n)   ((((unsigned long)(n))&0x3)<<24)
-#define DDR0_23_ODT_RD_MAP_CS0_DECODE(n)   ((((unsigned long)(n))>>24)&0x3)
-#define DDR0_23_ECC_C_SYND_MASK           0x00FF0000 /* Read only */
-#define DDR0_23_ECC_C_SYND_ENCODE(n)        ((((unsigned long)(n))&0xFF)<<16)
-#define DDR0_23_ECC_C_SYND_DECODE(n)        ((((unsigned long)(n))>>16)&0xFF)
-#define DDR0_23_ECC_U_SYND_MASK           0x0000FF00 /* Read only */
-#define DDR0_23_ECC_U_SYND_ENCODE(n)        ((((unsigned long)(n))&0xFF)<<8)
-#define DDR0_23_ECC_U_SYND_DECODE(n)        ((((unsigned long)(n))>>8)&0xFF)
-#define DDR0_23_FWC_MASK                  0x00000001 /* Write only */
-#define DDR0_23_FWC_ENCODE(n)               ((((unsigned long)(n))&0x1)<<0)
-#define DDR0_23_FWC_DECODE(n)               ((((unsigned long)(n))>>0)&0x1)
-
-#define DDR0_24                         0x18
-#define DDR0_24_RTT_PAD_TERMINATION_MASK  0x03000000
-#define DDR0_24_RTT_PAD_TERMINATION_ENCODE(n) ((((unsigned long)(n))&0x3)<<24)
-#define DDR0_24_RTT_PAD_TERMINATION_DECODE(n) ((((unsigned long)(n))>>24)&0x3)
-#define DDR0_24_ODT_WR_MAP_CS1_MASK       0x00030000
-#define DDR0_24_ODT_WR_MAP_CS1_ENCODE(n)    ((((unsigned long)(n))&0x3)<<16)
-#define DDR0_24_ODT_WR_MAP_CS1_DECODE(n)    ((((unsigned long)(n))>>16)&0x3)
-#define DDR0_24_ODT_RD_MAP_CS1_MASK       0x00000300
-#define DDR0_24_ODT_RD_MAP_CS1_ENCODE(n)    ((((unsigned long)(n))&0x3)<<8)
-#define DDR0_24_ODT_RD_MAP_CS1_DECODE(n)    ((((unsigned long)(n))>>8)&0x3)
-#define DDR0_24_ODT_WR_MAP_CS0_MASK       0x00000003
-#define DDR0_24_ODT_WR_MAP_CS0_ENCODE(n)    ((((unsigned long)(n))&0x3)<<0)
-#define DDR0_24_ODT_WR_MAP_CS0_DECODE(n)    ((((unsigned long)(n))>>0)&0x3)
-
-#define DDR0_25                         0x19
-#define DDR0_25_VERSION_MASK              0xFFFF0000 /* Read only */
-#define DDR0_25_VERSION_ENCODE(n)           ((((unsigned long)(n))&0xFFFF)<<16)
-#define DDR0_25_VERSION_DECODE(n)           ((((unsigned long)(n))>>16)&0xFFFF)
-#define DDR0_25_OUT_OF_RANGE_LENGTH_MASK  0x000003FF /* Read only */
-#define DDR0_25_OUT_OF_RANGE_LENGTH_ENCODE(n) ((((unsigned long)(n))&0x3FF)<<0)
-#define DDR0_25_OUT_OF_RANGE_LENGTH_DECODE(n) ((((unsigned long)(n))>>0)&0x3FF)
-
-#define DDR0_26                         0x1A
-#define DDR0_26_TRAS_MAX_MASK             0xFFFF0000
-#define DDR0_26_TRAS_MAX_ENCODE(n)          ((((unsigned long)(n))&0xFFFF)<<16)
-#define DDR0_26_TRAS_MAX_DECODE(n)          ((((unsigned long)(n))>>16)&0xFFFF)
-#define DDR0_26_TREF_MASK                 0x00003FFF
-#define DDR0_26_TREF_ENCODE(n)              ((((unsigned long)(n))&0x3FFF)<<0)
-#define DDR0_26_TREF_DECODE(n)              ((((unsigned long)(n))>>0)&0x3FFF)
-
-#define DDR0_27                         0x1B
-#define DDR0_27_EMRS_DATA_MASK            0x3FFF0000
-#define DDR0_27_EMRS_DATA_ENCODE(n)         ((((unsigned long)(n))&0x3FFF)<<16)
-#define DDR0_27_EMRS_DATA_DECODE(n)         ((((unsigned long)(n))>>16)&0x3FFF)
-#define DDR0_27_TINIT_MASK                0x0000FFFF
-#define DDR0_27_TINIT_ENCODE(n)             ((((unsigned long)(n))&0xFFFF)<<0)
-#define DDR0_27_TINIT_DECODE(n)             ((((unsigned long)(n))>>0)&0xFFFF)
-
-#define DDR0_28                         0x1C
-#define DDR0_28_EMRS3_DATA_MASK           0x3FFF0000
-#define DDR0_28_EMRS3_DATA_ENCODE(n)        ((((unsigned long)(n))&0x3FFF)<<16)
-#define DDR0_28_EMRS3_DATA_DECODE(n)        ((((unsigned long)(n))>>16)&0x3FFF)
-#define DDR0_28_EMRS2_DATA_MASK           0x00003FFF
-#define DDR0_28_EMRS2_DATA_ENCODE(n)        ((((unsigned long)(n))&0x3FFF)<<0)
-#define DDR0_28_EMRS2_DATA_DECODE(n)        ((((unsigned long)(n))>>0)&0x3FFF)
-
-#define DDR0_29                         0x1D
-
-#define DDR0_30                         0x1E
-
-#define DDR0_31                         0x1F
-#define DDR0_31_XOR_CHECK_BITS_MASK       0x0000FFFF
-#define DDR0_31_XOR_CHECK_BITS_ENCODE(n)    ((((unsigned long)(n))&0xFFFF)<<0)
-#define DDR0_31_XOR_CHECK_BITS_DECODE(n)    ((((unsigned long)(n))>>0)&0xFFFF)
-
-#define DDR0_32                         0x20
-#define DDR0_32_OUT_OF_RANGE_ADDR_MASK    0xFFFFFFFF /* Read only */
-#define DDR0_32_OUT_OF_RANGE_ADDR_ENCODE(n) ((((unsigned long)(n))&0xFFFFFFFF)<<0)
-#define DDR0_32_OUT_OF_RANGE_ADDR_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFFFFFF)
-
-#define DDR0_33                         0x21
-#define DDR0_33_OUT_OF_RANGE_ADDR_MASK    0x00000001 /* Read only */
-#define DDR0_33_OUT_OF_RANGE_ADDR_ENCODE(n) ((((unsigned long)(n))&0x1)<<0)
-#define DDR0_33_OUT_OF_RANGE_ADDR_DECODE(n)               ((((unsigned long)(n))>>0)&0x1)
-
-#define DDR0_34                         0x22
-#define DDR0_34_ECC_U_ADDR_MASK           0xFFFFFFFF /* Read only */
-#define DDR0_34_ECC_U_ADDR_ENCODE(n)        ((((unsigned long)(n))&0xFFFFFFFF)<<0)
-#define DDR0_34_ECC_U_ADDR_DECODE(n)        ((((unsigned long)(n))>>0)&0xFFFFFFFF)
-
-#define DDR0_35                         0x23
-#define DDR0_35_ECC_U_ADDR_MASK           0x00000001 /* Read only */
-#define DDR0_35_ECC_U_ADDR_ENCODE(n)        ((((unsigned long)(n))&0x1)<<0)
-#define DDR0_35_ECC_U_ADDR_DECODE(n)        ((((unsigned long)(n))>>0)&0x1)
-
-#define DDR0_36                         0x24
-#define DDR0_36_ECC_U_DATA_MASK           0xFFFFFFFF /* Read only */
-#define DDR0_36_ECC_U_DATA_ENCODE(n)        ((((unsigned long)(n))&0xFFFFFFFF)<<0)
-#define DDR0_36_ECC_U_DATA_DECODE(n)        ((((unsigned long)(n))>>0)&0xFFFFFFFF)
-
-#define DDR0_37                         0x25
-#define DDR0_37_ECC_U_DATA_MASK           0xFFFFFFFF /* Read only */
-#define DDR0_37_ECC_U_DATA_ENCODE(n)        ((((unsigned long)(n))&0xFFFFFFFF)<<0)
-#define DDR0_37_ECC_U_DATA_DECODE(n)        ((((unsigned long)(n))>>0)&0xFFFFFFFF)
-
-#define DDR0_38                         0x26
-#define DDR0_38_ECC_C_ADDR_MASK           0xFFFFFFFF /* Read only */
-#define DDR0_38_ECC_C_ADDR_ENCODE(n)        ((((unsigned long)(n))&0xFFFFFFFF)<<0)
-#define DDR0_38_ECC_C_ADDR_DECODE(n)        ((((unsigned long)(n))>>0)&0xFFFFFFFF)
-
-#define DDR0_39                         0x27
-#define DDR0_39_ECC_C_ADDR_MASK           0x00000001 /* Read only */
-#define DDR0_39_ECC_C_ADDR_ENCODE(n)        ((((unsigned long)(n))&0x1)<<0)
-#define DDR0_39_ECC_C_ADDR_DECODE(n)        ((((unsigned long)(n))>>0)&0x1)
-
-#define DDR0_40                         0x28
-#define DDR0_40_ECC_C_DATA_MASK           0xFFFFFFFF /* Read only */
-#define DDR0_40_ECC_C_DATA_ENCODE(n)        ((((unsigned long)(n))&0xFFFFFFFF)<<0)
-#define DDR0_40_ECC_C_DATA_DECODE(n)        ((((unsigned long)(n))>>0)&0xFFFFFFFF)
-
-#define DDR0_41                         0x29
-#define DDR0_41_ECC_C_DATA_MASK           0xFFFFFFFF /* Read only */
-#define DDR0_41_ECC_C_DATA_ENCODE(n)        ((((unsigned long)(n))&0xFFFFFFFF)<<0)
-#define DDR0_41_ECC_C_DATA_DECODE(n)        ((((unsigned long)(n))>>0)&0xFFFFFFFF)
-
-#define DDR0_42                         0x2A
-#define DDR0_42_ADDR_PINS_MASK            0x07000000
-#define DDR0_42_ADDR_PINS_ENCODE(n)         ((((unsigned long)(n))&0x7)<<24)
-#define DDR0_42_ADDR_PINS_DECODE(n)         ((((unsigned long)(n))>>24)&0x7)
-#define DDR0_42_CASLAT_LIN_GATE_MASK      0x0000000F
-#define DDR0_42_CASLAT_LIN_GATE_ENCODE(n)   ((((unsigned long)(n))&0xF)<<0)
-#define DDR0_42_CASLAT_LIN_GATE_DECODE(n)   ((((unsigned long)(n))>>0)&0xF)
-
-#define DDR0_43                         0x2B
-#define DDR0_43_TWR_MASK                  0x07000000
-#define DDR0_43_TWR_ENCODE(n)               ((((unsigned long)(n))&0x7)<<24)
-#define DDR0_43_TWR_DECODE(n)               ((((unsigned long)(n))>>24)&0x7)
-#define DDR0_43_APREBIT_MASK              0x000F0000
-#define DDR0_43_APREBIT_ENCODE(n)           ((((unsigned long)(n))&0xF)<<16)
-#define DDR0_43_APREBIT_DECODE(n)           ((((unsigned long)(n))>>16)&0xF)
-#define DDR0_43_COLUMN_SIZE_MASK          0x00000700
-#define DDR0_43_COLUMN_SIZE_ENCODE(n)       ((((unsigned long)(n))&0x7)<<8)
-#define DDR0_43_COLUMN_SIZE_DECODE(n)       ((((unsigned long)(n))>>8)&0x7)
-#define DDR0_43_EIGHT_BANK_MODE_MASK      0x00000001
-#define DDR0_43_EIGHT_BANK_MODE_8_BANKS     0x00000001
-#define DDR0_43_EIGHT_BANK_MODE_4_BANKS     0x00000000
-#define DDR0_43_EIGHT_BANK_MODE_ENCODE(n)   ((((unsigned long)(n))&0x1)<<0)
-#define DDR0_43_EIGHT_BANK_MODE_DECODE(n)   ((((unsigned long)(n))>>0)&0x1)
-
-#define DDR0_44                         0x2C
-#define DDR0_44_TRCD_MASK                 0x000000FF
-#define DDR0_44_TRCD_ENCODE(n)              ((((unsigned long)(n))&0xFF)<<0)
-#define DDR0_44_TRCD_DECODE(n)              ((((unsigned long)(n))>>0)&0xFF)
-
-#endif /* _SPD_SDRAM_DENALI_H_ */

From ef16fccf96e55eab93fe25d03ebe2e9b56e5332b Mon Sep 17 00:00:00 2001
From: Larry Johnson <lrj@arlinx.com>
Date: Sun, 30 Dec 2007 01:01:32 -0500
Subject: [PATCH 031/108] PPC4xx: Use common code for LWMON5 board SDRAM
 support

This patch also modifies the functionality of the code so that the data-eye
search is now done with with the cache disabled.

Signed-off-by: Larry Johnson <lrj@acm.org>
---
 board/lwmon5/sdram.c | 357 +++----------------------------------------
 1 file changed, 20 insertions(+), 337 deletions(-)

diff --git a/board/lwmon5/sdram.c b/board/lwmon5/sdram.c
index 399da8ae6..affaeff1a 100644
--- a/board/lwmon5/sdram.c
+++ b/board/lwmon5/sdram.c
@@ -36,8 +36,6 @@
 #include <asm/io.h>
 #include <ppc440.h>
 
-#include "sdram.h"
-
 /*
  * This DDR2 setup code can dynamically setup the TLB entries for the DDR2 memory
  * region. Right now the cache should still be disabled in U-Boot because of the
@@ -54,8 +52,13 @@
 #define MY_TLB_WORD2_I_ENABLE	TLB_WORD2_I_ENABLE	/* disable caching on SDRAM */
 #endif
 
-void dcbz_area(u32 start_address, u32 num_bytes);
-void dflush(void);
+/*-----------------------------------------------------------------------------+
+ * Prototypes
+ *-----------------------------------------------------------------------------*/
+extern int denali_wait_for_dlllock(void);
+extern void denali_core_search_data_eye(void);
+extern void dcbz_area(u32 start_address, u32 num_bytes);
+extern void dflush(void);
 
 static u32 is_ecc_enabled(void)
 {
@@ -87,330 +90,6 @@ void board_add_ram_info(int use_default)
 	printf(", CL%d)", val);
 }
 
-static int wait_for_dlllock(void)
-{
-	u32 val;
-	int wait = 0;
-
-	/*
-	 * Wait for the DCC master delay line to finish calibration
-	 */
-	mtdcr(ddrcfga, DDR0_17);
-	val = DDR0_17_DLLLOCKREG_UNLOCKED;
-
-	while (wait != 0xffff) {
-		val = mfdcr(ddrcfgd);
-		if ((val & DDR0_17_DLLLOCKREG_MASK) == DDR0_17_DLLLOCKREG_LOCKED)
-			/* dlllockreg bit on */
-			return 0;
-		else
-			wait++;
-	}
-	debug("0x%04x: DDR0_17 Value (dlllockreg bit): 0x%08x\n", wait, val);
-	debug("Waiting for dlllockreg bit to raise\n");
-
-	return -1;
-}
-
-#if defined(CONFIG_DDR_DATA_EYE)
-int wait_for_dram_init_complete(void)
-{
-	u32 val;
-	int wait = 0;
-
-	/*
-	 * Wait for 'DRAM initialization complete' bit in status register
-	 */
-	mtdcr(ddrcfga, DDR0_00);
-
-	while (wait != 0xffff) {
-		val = mfdcr(ddrcfgd);
-		if ((val & DDR0_00_INT_STATUS_BIT6) == DDR0_00_INT_STATUS_BIT6)
-			/* 'DRAM initialization complete' bit */
-			return 0;
-		else
-			wait++;
-	}
-
-	debug("DRAM initialization complete bit in status register did not rise\n");
-
-	return -1;
-}
-
-#define NUM_TRIES 64
-#define NUM_READS 10
-
-void denali_core_search_data_eye(u32 start_addr, u32 memory_size)
-{
-	int k, j;
-	u32 val;
-	u32 wr_dqs_shift, dqs_out_shift, dll_dqs_delay_X;
-	u32 max_passing_cases = 0, wr_dqs_shift_with_max_passing_cases = 0;
-	u32 passing_cases = 0, dll_dqs_delay_X_sw_val = 0;
-	u32 dll_dqs_delay_X_start_window = 0, dll_dqs_delay_X_end_window = 0;
-	volatile u32 *ram_pointer;
-	u32 test[NUM_TRIES] = {
-		0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
-		0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
-		0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
-		0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
-		0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
-		0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
-		0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
-		0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
-		0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
-		0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
-		0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
-		0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
-		0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
-		0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
-		0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55,
-		0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55 };
-
-	ram_pointer = (volatile u32 *)start_addr;
-
-	for (wr_dqs_shift = 64; wr_dqs_shift < 96; wr_dqs_shift++) {
-		/*for (wr_dqs_shift=1; wr_dqs_shift<96; wr_dqs_shift++) {*/
-
-		/*
-		 * De-assert 'start' parameter.
-		 */
-		mtdcr(ddrcfga, DDR0_02);
-		val = (mfdcr(ddrcfgd) & ~DDR0_02_START_MASK) | DDR0_02_START_OFF;
-		mtdcr(ddrcfgd, val);
-
-		/*
-		 * Set 'wr_dqs_shift'
-		 */
-		mtdcr(ddrcfga, DDR0_09);
-		val = (mfdcr(ddrcfgd) & ~DDR0_09_WR_DQS_SHIFT_MASK)
-			| DDR0_09_WR_DQS_SHIFT_ENCODE(wr_dqs_shift);
-		mtdcr(ddrcfgd, val);
-
-		/*
-		 * Set 'dqs_out_shift' = wr_dqs_shift + 32
-		 */
-		dqs_out_shift = wr_dqs_shift + 32;
-		mtdcr(ddrcfga, DDR0_22);
-		val = (mfdcr(ddrcfgd) & ~DDR0_22_DQS_OUT_SHIFT_MASK)
-			| DDR0_22_DQS_OUT_SHIFT_ENCODE(dqs_out_shift);
-		mtdcr(ddrcfgd, val);
-
-		passing_cases = 0;
-
-		for (dll_dqs_delay_X = 1; dll_dqs_delay_X < 64; dll_dqs_delay_X++) {
-			/*for (dll_dqs_delay_X=1; dll_dqs_delay_X<128; dll_dqs_delay_X++) {*/
-			/*
-			 * Set 'dll_dqs_delay_X'.
-			 */
-			/* dll_dqs_delay_0 */
-			mtdcr(ddrcfga, DDR0_17);
-			val = (mfdcr(ddrcfgd) & ~DDR0_17_DLL_DQS_DELAY_0_MASK)
-				| DDR0_17_DLL_DQS_DELAY_0_ENCODE(dll_dqs_delay_X);
-			mtdcr(ddrcfgd, val);
-			/* dll_dqs_delay_1 to dll_dqs_delay_4 */
-			mtdcr(ddrcfga, DDR0_18);
-			val = (mfdcr(ddrcfgd) & ~DDR0_18_DLL_DQS_DELAY_X_MASK)
-				| DDR0_18_DLL_DQS_DELAY_4_ENCODE(dll_dqs_delay_X)
-				| DDR0_18_DLL_DQS_DELAY_3_ENCODE(dll_dqs_delay_X)
-				| DDR0_18_DLL_DQS_DELAY_2_ENCODE(dll_dqs_delay_X)
-				| DDR0_18_DLL_DQS_DELAY_1_ENCODE(dll_dqs_delay_X);
-			mtdcr(ddrcfgd, val);
-			/* dll_dqs_delay_5 to dll_dqs_delay_8 */
-			mtdcr(ddrcfga, DDR0_19);
-			val = (mfdcr(ddrcfgd) & ~DDR0_19_DLL_DQS_DELAY_X_MASK)
-				| DDR0_19_DLL_DQS_DELAY_8_ENCODE(dll_dqs_delay_X)
-				| DDR0_19_DLL_DQS_DELAY_7_ENCODE(dll_dqs_delay_X)
-				| DDR0_19_DLL_DQS_DELAY_6_ENCODE(dll_dqs_delay_X)
-				| DDR0_19_DLL_DQS_DELAY_5_ENCODE(dll_dqs_delay_X);
-			mtdcr(ddrcfgd, val);
-
-			ppcMsync();
-			ppcMbar();
-
-			/*
-			 * Assert 'start' parameter.
-			 */
-			mtdcr(ddrcfga, DDR0_02);
-			val = (mfdcr(ddrcfgd) & ~DDR0_02_START_MASK) | DDR0_02_START_ON;
-			mtdcr(ddrcfgd, val);
-
-			ppcMsync();
-			ppcMbar();
-
-			/*
-			 * Wait for the DCC master delay line to finish calibration
-			 */
-			if (wait_for_dlllock() != 0) {
-				printf("dlllock did not occur !!!\n");
-				printf("denali_core_search_data_eye!!!\n");
-				printf("wr_dqs_shift = %d - dll_dqs_delay_X = %d\n",
-				       wr_dqs_shift, dll_dqs_delay_X);
-				hang();
-			}
-			ppcMsync();
-			ppcMbar();
-
-			if (wait_for_dram_init_complete() != 0) {
-				printf("dram init complete did not occur !!!\n");
-				printf("denali_core_search_data_eye!!!\n");
-				printf("wr_dqs_shift = %d - dll_dqs_delay_X = %d\n",
-				       wr_dqs_shift, dll_dqs_delay_X);
-				hang();
-			}
-			udelay(100);  /* wait 100us to ensure init is really completed !!! */
-
-			/* write values */
-			for (j=0; j<NUM_TRIES; j++) {
-				ram_pointer[j] = test[j];
-
-				/* clear any cache at ram location */
-				__asm__("dcbf 0,%0": :"r" (&ram_pointer[j]));
-			}
-
-			/* read values back */
-			for (j=0; j<NUM_TRIES; j++) {
-				for (k=0; k<NUM_READS; k++) {
-					/* clear any cache at ram location */
-					__asm__("dcbf 0,%0": :"r" (&ram_pointer[j]));
-
-					if (ram_pointer[j] != test[j])
-						break;
-				}
-
-				/* read error */
-				if (k != NUM_READS)
-					break;
-			}
-
-			/* See if the dll_dqs_delay_X value passed.*/
-			if (j < NUM_TRIES) {
-				/* Failed */
-				passing_cases = 0;
-				/* break; */
-			} else {
-				/* Passed */
-				if (passing_cases == 0)
-					dll_dqs_delay_X_sw_val = dll_dqs_delay_X;
-				passing_cases++;
-				if (passing_cases >= max_passing_cases) {
-					max_passing_cases = passing_cases;
-					wr_dqs_shift_with_max_passing_cases = wr_dqs_shift;
-					dll_dqs_delay_X_start_window = dll_dqs_delay_X_sw_val;
-					dll_dqs_delay_X_end_window = dll_dqs_delay_X;
-				}
-			}
-
-			/*
-			 * De-assert 'start' parameter.
-			 */
-			mtdcr(ddrcfga, DDR0_02);
-			val = (mfdcr(ddrcfgd) & ~DDR0_02_START_MASK) | DDR0_02_START_OFF;
-			mtdcr(ddrcfgd, val);
-
-		} /* for (dll_dqs_delay_X=0; dll_dqs_delay_X<128; dll_dqs_delay_X++) */
-
-	} /* for (wr_dqs_shift=0; wr_dqs_shift<96; wr_dqs_shift++) */
-
-	/*
-	 * Largest passing window is now detected.
-	 */
-
-	/* Compute dll_dqs_delay_X value */
-	dll_dqs_delay_X = (dll_dqs_delay_X_end_window + dll_dqs_delay_X_start_window) / 2;
-	wr_dqs_shift = wr_dqs_shift_with_max_passing_cases;
-
-	debug("DQS calibration - Window detected:\n");
-	debug("max_passing_cases = %d\n", max_passing_cases);
-	debug("wr_dqs_shift	 = %d\n", wr_dqs_shift);
-	debug("dll_dqs_delay_X	 = %d\n", dll_dqs_delay_X);
-	debug("dll_dqs_delay_X window = %d - %d\n",
-	      dll_dqs_delay_X_start_window, dll_dqs_delay_X_end_window);
-
-	/*
-	 * De-assert 'start' parameter.
-	 */
-	mtdcr(ddrcfga, DDR0_02);
-	val = (mfdcr(ddrcfgd) & ~DDR0_02_START_MASK) | DDR0_02_START_OFF;
-	mtdcr(ddrcfgd, val);
-
-	/*
-	 * Set 'wr_dqs_shift'
-	 */
-	mtdcr(ddrcfga, DDR0_09);
-	val = (mfdcr(ddrcfgd) & ~DDR0_09_WR_DQS_SHIFT_MASK)
-		| DDR0_09_WR_DQS_SHIFT_ENCODE(wr_dqs_shift);
-	mtdcr(ddrcfgd, val);
-	debug("DDR0_09=0x%08lx\n", val);
-
-	/*
-	 * Set 'dqs_out_shift' = wr_dqs_shift + 32
-	 */
-	dqs_out_shift = wr_dqs_shift + 32;
-	mtdcr(ddrcfga, DDR0_22);
-	val = (mfdcr(ddrcfgd) & ~DDR0_22_DQS_OUT_SHIFT_MASK)
-		| DDR0_22_DQS_OUT_SHIFT_ENCODE(dqs_out_shift);
-	mtdcr(ddrcfgd, val);
-	debug("DDR0_22=0x%08lx\n", val);
-
-	/*
-	 * Set 'dll_dqs_delay_X'.
-	 */
-	/* dll_dqs_delay_0 */
-	mtdcr(ddrcfga, DDR0_17);
-	val = (mfdcr(ddrcfgd) & ~DDR0_17_DLL_DQS_DELAY_0_MASK)
-		| DDR0_17_DLL_DQS_DELAY_0_ENCODE(dll_dqs_delay_X);
-	mtdcr(ddrcfgd, val);
-	debug("DDR0_17=0x%08lx\n", val);
-
-	/* dll_dqs_delay_1 to dll_dqs_delay_4 */
-	mtdcr(ddrcfga, DDR0_18);
-	val = (mfdcr(ddrcfgd) & ~DDR0_18_DLL_DQS_DELAY_X_MASK)
-		| DDR0_18_DLL_DQS_DELAY_4_ENCODE(dll_dqs_delay_X)
-		| DDR0_18_DLL_DQS_DELAY_3_ENCODE(dll_dqs_delay_X)
-		| DDR0_18_DLL_DQS_DELAY_2_ENCODE(dll_dqs_delay_X)
-		| DDR0_18_DLL_DQS_DELAY_1_ENCODE(dll_dqs_delay_X);
-	mtdcr(ddrcfgd, val);
-	debug("DDR0_18=0x%08lx\n", val);
-
-	/* dll_dqs_delay_5 to dll_dqs_delay_8 */
-	mtdcr(ddrcfga, DDR0_19);
-	val = (mfdcr(ddrcfgd) & ~DDR0_19_DLL_DQS_DELAY_X_MASK)
-		| DDR0_19_DLL_DQS_DELAY_8_ENCODE(dll_dqs_delay_X)
-		| DDR0_19_DLL_DQS_DELAY_7_ENCODE(dll_dqs_delay_X)
-		| DDR0_19_DLL_DQS_DELAY_6_ENCODE(dll_dqs_delay_X)
-		| DDR0_19_DLL_DQS_DELAY_5_ENCODE(dll_dqs_delay_X);
-	mtdcr(ddrcfgd, val);
-	debug("DDR0_19=0x%08lx\n", val);
-
-	/*
-	 * Assert 'start' parameter.
-	 */
-	mtdcr(ddrcfga, DDR0_02);
-	val = (mfdcr(ddrcfgd) & ~DDR0_02_START_MASK) | DDR0_02_START_ON;
-	mtdcr(ddrcfgd, val);
-
-	ppcMsync();
-	ppcMbar();
-
-	/*
-	 * Wait for the DCC master delay line to finish calibration
-	 */
-	if (wait_for_dlllock() != 0) {
-		printf("dlllock did not occur !!!\n");
-		hang();
-	}
-	ppcMsync();
-	ppcMbar();
-
-	if (wait_for_dram_init_complete() != 0) {
-		printf("dram init complete did not occur !!!\n");
-		hang();
-	}
-	udelay(100);  /* wait 100us to ensure init is really completed !!! */
-}
-#endif /* CONFIG_DDR_DATA_EYE */
-
 #ifdef CONFIG_DDR_ECC
 static void wait_ddr_idle(void)
 {
@@ -610,12 +289,23 @@ long int initdram (int board_type)
 	mtsdram(DDR0_02, 0x00000001); /* Activate the denali core */
 #endif
 
-	wait_for_dlllock();
+	denali_wait_for_dlllock();
+
+#if defined(CONFIG_DDR_DATA_EYE)
+	/* -----------------------------------------------------------+
+	 * Perform data eye search if requested.
+	 * ----------------------------------------------------------*/
+	program_tlb(0, CFG_SDRAM_BASE, CFG_MBYTES_SDRAM << 20,
+		    TLB_WORD2_I_ENABLE);
+	denali_core_search_data_eye();
+	remove_tlb(CFG_SDRAM_BASE, CFG_MBYTES_SDRAM << 20);
+#endif
 
 	/*
 	 * Program tlb entries for this size (dynamic)
 	 */
-	program_tlb(0, 0, CFG_MBYTES_SDRAM << 20, MY_TLB_WORD2_I_ENABLE);
+	program_tlb(0, CFG_SDRAM_BASE, CFG_MBYTES_SDRAM << 20,
+		    MY_TLB_WORD2_I_ENABLE);
 
 	/*
 	 * Setup 2nd TLB with same physical address but different virtual address
@@ -623,13 +313,6 @@ long int initdram (int board_type)
 	 */
 	program_tlb(0, CFG_DDR_CACHED_ADDR, CFG_MBYTES_SDRAM << 20, 0);
 
-#ifdef CONFIG_DDR_DATA_EYE
-	/*
-	 * Perform data eye search if requested.
-	 */
-	denali_core_search_data_eye(CFG_DDR_CACHED_ADDR, CFG_MBYTES_SDRAM << 20);
-#endif
-
 #ifdef CONFIG_DDR_ECC
 	/*
 	 * If ECC is enabled, initialize the parity bits.

From 196404cdc1de495d6182e84731c200fc5748df15 Mon Sep 17 00:00:00 2001
From: Larry Johnson <lrj@arlinx.com>
Date: Sun, 30 Dec 2007 01:01:54 -0500
Subject: [PATCH 032/108] PPC4xx: Remove sdram.h from board/lwmon5

These definitions are now in "include/ppc440.h".

Signed-off-by: Larry Johnson <lrj@acm.org>
---
 board/lwmon5/sdram.h | 505 -------------------------------------------
 1 file changed, 505 deletions(-)
 delete mode 100644 board/lwmon5/sdram.h

diff --git a/board/lwmon5/sdram.h b/board/lwmon5/sdram.h
deleted file mode 100644
index 6a7bf01ef..000000000
--- a/board/lwmon5/sdram.h
+++ /dev/null
@@ -1,505 +0,0 @@
-/*
- * (C) Copyright 2006
- * Sylvie Gohl,             AMCC/IBM, gohl.sylvie@fr.ibm.com
- * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
- * Thierry Roman,           AMCC/IBM, thierry_roman@fr.ibm.com
- * Alain Saurel,            AMCC/IBM, alain.saurel@fr.ibm.com
- * Robert Snyder,           AMCC/IBM, rob.snyder@fr.ibm.com
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef _SPD_SDRAM_DENALI_H_
-#define _SPD_SDRAM_DENALI_H_
-
-#define ppcMsync	sync
-#define ppcMbar		eieio
-
-/* General definitions */
-#define MAX_SPD_BYTE        128         /* highest SPD byte # to read */
-#define DENALI_REG_NUMBER   45          /* 45 Regs in PPC440EPx Denali Core */
-#define SUPPORTED_DIMMS_NB  7           /* Number of supported DIMM modules types */
-#define SDRAM_NONE          0           /* No DIMM detected in Slot */
-#define MAXRANKS            2           /* 2 ranks maximum */
-
-/* Supported PLB Frequencies */
-#define PLB_FREQ_133MHZ     133333333
-#define PLB_FREQ_152MHZ     152000000
-#define PLB_FREQ_160MHZ     160000000
-#define PLB_FREQ_166MHZ     166666666
-
-/* Denali Core Registers */
-#define SDRAM_DCR_BASE 0x10
-
-#define DDR_DCR_BASE 0x10
-#define ddrcfga  (DDR_DCR_BASE+0x0)   /* DDR configuration address reg */
-#define ddrcfgd  (DDR_DCR_BASE+0x1)   /* DDR configuration data reg    */
-
-/*-----------------------------------------------------------------------------+
-  | Values for ddrcfga register - indirect addressing of these regs
-  +-----------------------------------------------------------------------------*/
-
-#define DDR0_00                         0x00
-#define DDR0_00_INT_ACK_MASK              0x7F000000 /* Write only */
-#define DDR0_00_INT_ACK_ALL               0x7F000000
-#define DDR0_00_INT_ACK_ENCODE(n)           ((((unsigned long)(n))&0x7F)<<24)
-#define DDR0_00_INT_ACK_DECODE(n)           ((((unsigned long)(n))>>24)&0x7F)
-/* Status */
-#define DDR0_00_INT_STATUS_MASK           0x00FF0000 /* Read only */
-/* Bit0. A single access outside the defined PHYSICAL memory space detected. */
-#define DDR0_00_INT_STATUS_BIT0           0x00010000
-/* Bit1. Multiple accesses outside the defined PHYSICAL memory space detected. */
-#define DDR0_00_INT_STATUS_BIT1           0x00020000
-/* Bit2. Single correctable ECC event detected */
-#define DDR0_00_INT_STATUS_BIT2           0x00040000
-/* Bit3. Multiple correctable ECC events detected. */
-#define DDR0_00_INT_STATUS_BIT3           0x00080000
-/* Bit4. Single uncorrectable ECC event detected. */
-#define DDR0_00_INT_STATUS_BIT4           0x00100000
-/* Bit5. Multiple uncorrectable ECC events detected. */
-#define DDR0_00_INT_STATUS_BIT5           0x00200000
-/* Bit6. DRAM initialization complete. */
-#define DDR0_00_INT_STATUS_BIT6           0x00400000
-/* Bit7. Logical OR of all lower bits. */
-#define DDR0_00_INT_STATUS_BIT7           0x00800000
-
-#define DDR0_00_INT_STATUS_ENCODE(n)        ((((unsigned long)(n))&0xFF)<<16)
-#define DDR0_00_INT_STATUS_DECODE(n)        ((((unsigned long)(n))>>16)&0xFF)
-#define DDR0_00_DLL_INCREMENT_MASK        0x00007F00
-#define DDR0_00_DLL_INCREMENT_ENCODE(n)     ((((unsigned long)(n))&0x7F)<<8)
-#define DDR0_00_DLL_INCREMENT_DECODE(n)     ((((unsigned long)(n))>>8)&0x7F)
-#define DDR0_00_DLL_START_POINT_MASK      0x0000007F
-#define DDR0_00_DLL_START_POINT_ENCODE(n)   ((((unsigned long)(n))&0x7F)<<0)
-#define DDR0_00_DLL_START_POINT_DECODE(n)   ((((unsigned long)(n))>>0)&0x7F)
-
-
-#define DDR0_01                         0x01
-#define DDR0_01_PLB0_DB_CS_LOWER_MASK     0x1F000000
-#define DDR0_01_PLB0_DB_CS_LOWER_ENCODE(n)  ((((unsigned long)(n))&0x1F)<<24)
-#define DDR0_01_PLB0_DB_CS_LOWER_DECODE(n)  ((((unsigned long)(n))>>24)&0x1F)
-#define DDR0_01_PLB0_DB_CS_UPPER_MASK     0x001F0000
-#define DDR0_01_PLB0_DB_CS_UPPER_ENCODE(n)  ((((unsigned long)(n))&0x1F)<<16)
-#define DDR0_01_PLB0_DB_CS_UPPER_DECODE(n)  ((((unsigned long)(n))>>16)&0x1F)
-#define DDR0_01_OUT_OF_RANGE_TYPE_MASK    0x00000700 /* Read only */
-#define DDR0_01_OUT_OF_RANGE_TYPE_ENCODE(n)               ((((unsigned long)(n))&0x7)<<8)
-#define DDR0_01_OUT_OF_RANGE_TYPE_DECODE(n)               ((((unsigned long)(n))>>8)&0x7)
-#define DDR0_01_INT_MASK_MASK             0x000000FF
-#define DDR0_01_INT_MASK_ENCODE(n)          ((((unsigned long)(n))&0xFF)<<0)
-#define DDR0_01_INT_MASK_DECODE(n)          ((((unsigned long)(n))>>0)&0xFF)
-#define DDR0_01_INT_MASK_ALL_ON           0x000000FF
-#define DDR0_01_INT_MASK_ALL_OFF          0x00000000
-
-#define DDR0_02                         0x02
-#define DDR0_02_MAX_CS_REG_MASK           0x02000000 /* Read only */
-#define DDR0_02_MAX_CS_REG_ENCODE(n)        ((((unsigned long)(n))&0x2)<<24)
-#define DDR0_02_MAX_CS_REG_DECODE(n)        ((((unsigned long)(n))>>24)&0x2)
-#define DDR0_02_MAX_COL_REG_MASK          0x000F0000 /* Read only */
-#define DDR0_02_MAX_COL_REG_ENCODE(n)       ((((unsigned long)(n))&0xF)<<16)
-#define DDR0_02_MAX_COL_REG_DECODE(n)       ((((unsigned long)(n))>>16)&0xF)
-#define DDR0_02_MAX_ROW_REG_MASK          0x00000F00 /* Read only */
-#define DDR0_02_MAX_ROW_REG_ENCODE(n)       ((((unsigned long)(n))&0xF)<<8)
-#define DDR0_02_MAX_ROW_REG_DECODE(n)       ((((unsigned long)(n))>>8)&0xF)
-#define DDR0_02_START_MASK                0x00000001
-#define DDR0_02_START_ENCODE(n)             ((((unsigned long)(n))&0x1)<<0)
-#define DDR0_02_START_DECODE(n)             ((((unsigned long)(n))>>0)&0x1)
-#define DDR0_02_START_OFF                 0x00000000
-#define DDR0_02_START_ON                  0x00000001
-
-#define DDR0_03                         0x03
-#define DDR0_03_BSTLEN_MASK               0x07000000
-#define DDR0_03_BSTLEN_ENCODE(n)            ((((unsigned long)(n))&0x7)<<24)
-#define DDR0_03_BSTLEN_DECODE(n)            ((((unsigned long)(n))>>24)&0x7)
-#define DDR0_03_CASLAT_MASK               0x00070000
-#define DDR0_03_CASLAT_ENCODE(n)            ((((unsigned long)(n))&0x7)<<16)
-#define DDR0_03_CASLAT_DECODE(n)            ((((unsigned long)(n))>>16)&0x7)
-#define DDR0_03_CASLAT_LIN_MASK           0x00000F00
-#define DDR0_03_CASLAT_LIN_ENCODE(n)        ((((unsigned long)(n))&0xF)<<8)
-#define DDR0_03_CASLAT_LIN_DECODE(n)        ((((unsigned long)(n))>>8)&0xF)
-#define DDR0_03_INITAREF_MASK             0x0000000F
-#define DDR0_03_INITAREF_ENCODE(n)          ((((unsigned long)(n))&0xF)<<0)
-#define DDR0_03_INITAREF_DECODE(n)          ((((unsigned long)(n))>>0)&0xF)
-
-#define DDR0_04                         0x04
-#define DDR0_04_TRC_MASK                  0x1F000000
-#define DDR0_04_TRC_ENCODE(n)               ((((unsigned long)(n))&0x1F)<<24)
-#define DDR0_04_TRC_DECODE(n)               ((((unsigned long)(n))>>24)&0x1F)
-#define DDR0_04_TRRD_MASK                 0x00070000
-#define DDR0_04_TRRD_ENCODE(n)              ((((unsigned long)(n))&0x7)<<16)
-#define DDR0_04_TRRD_DECODE(n)              ((((unsigned long)(n))>>16)&0x7)
-#define DDR0_04_TRTP_MASK                 0x00000700
-#define DDR0_04_TRTP_ENCODE(n)              ((((unsigned long)(n))&0x7)<<8)
-#define DDR0_04_TRTP_DECODE(n)              ((((unsigned long)(n))>>8)&0x7)
-
-#define DDR0_05                         0x05
-#define DDR0_05_TMRD_MASK                 0x1F000000
-#define DDR0_05_TMRD_ENCODE(n)              ((((unsigned long)(n))&0x1F)<<24)
-#define DDR0_05_TMRD_DECODE(n)              ((((unsigned long)(n))>>24)&0x1F)
-#define DDR0_05_TEMRS_MASK                0x00070000
-#define DDR0_05_TEMRS_ENCODE(n)             ((((unsigned long)(n))&0x7)<<16)
-#define DDR0_05_TEMRS_DECODE(n)             ((((unsigned long)(n))>>16)&0x7)
-#define DDR0_05_TRP_MASK                  0x00000F00
-#define DDR0_05_TRP_ENCODE(n)               ((((unsigned long)(n))&0xF)<<8)
-#define DDR0_05_TRP_DECODE(n)               ((((unsigned long)(n))>>8)&0xF)
-#define DDR0_05_TRAS_MIN_MASK             0x000000FF
-#define DDR0_05_TRAS_MIN_ENCODE(n)          ((((unsigned long)(n))&0xFF)<<0)
-#define DDR0_05_TRAS_MIN_DECODE(n)          ((((unsigned long)(n))>>0)&0xFF)
-
-#define DDR0_06                         0x06
-#define DDR0_06_WRITEINTERP_MASK          0x01000000
-#define DDR0_06_WRITEINTERP_ENCODE(n)       ((((unsigned long)(n))&0x1)<<24)
-#define DDR0_06_WRITEINTERP_DECODE(n)       ((((unsigned long)(n))>>24)&0x1)
-#define DDR0_06_TWTR_MASK                 0x00070000
-#define DDR0_06_TWTR_ENCODE(n)              ((((unsigned long)(n))&0x7)<<16)
-#define DDR0_06_TWTR_DECODE(n)              ((((unsigned long)(n))>>16)&0x7)
-#define DDR0_06_TDLL_MASK                 0x0000FF00
-#define DDR0_06_TDLL_ENCODE(n)              ((((unsigned long)(n))&0xFF)<<8)
-#define DDR0_06_TDLL_DECODE(n)              ((((unsigned long)(n))>>8)&0xFF)
-#define DDR0_06_TRFC_MASK                 0x0000007F
-#define DDR0_06_TRFC_ENCODE(n)              ((((unsigned long)(n))&0x7F)<<0)
-#define DDR0_06_TRFC_DECODE(n)              ((((unsigned long)(n))>>0)&0x7F)
-
-#define DDR0_07                         0x07
-#define DDR0_07_NO_CMD_INIT_MASK          0x01000000
-#define DDR0_07_NO_CMD_INIT_ENCODE(n)       ((((unsigned long)(n))&0x1)<<24)
-#define DDR0_07_NO_CMD_INIT_DECODE(n)       ((((unsigned long)(n))>>24)&0x1)
-#define DDR0_07_TFAW_MASK                 0x001F0000
-#define DDR0_07_TFAW_ENCODE(n)              ((((unsigned long)(n))&0x1F)<<16)
-#define DDR0_07_TFAW_DECODE(n)              ((((unsigned long)(n))>>16)&0x1F)
-#define DDR0_07_AUTO_REFRESH_MODE_MASK    0x00000100
-#define DDR0_07_AUTO_REFRESH_MODE_ENCODE(n) ((((unsigned long)(n))&0x1)<<8)
-#define DDR0_07_AUTO_REFRESH_MODE_DECODE(n) ((((unsigned long)(n))>>8)&0x1)
-#define DDR0_07_AREFRESH_MASK             0x00000001
-#define DDR0_07_AREFRESH_ENCODE(n)          ((((unsigned long)(n))&0x1)<<0)
-#define DDR0_07_AREFRESH_DECODE(n)          ((((unsigned long)(n))>>0)&0x1)
-
-#define DDR0_08                         0x08
-#define DDR0_08_WRLAT_MASK                0x07000000
-#define DDR0_08_WRLAT_ENCODE(n)             ((((unsigned long)(n))&0x7)<<24)
-#define DDR0_08_WRLAT_DECODE(n)             ((((unsigned long)(n))>>24)&0x7)
-#define DDR0_08_TCPD_MASK                 0x00FF0000
-#define DDR0_08_TCPD_ENCODE(n)              ((((unsigned long)(n))&0xFF)<<16)
-#define DDR0_08_TCPD_DECODE(n)              ((((unsigned long)(n))>>16)&0xFF)
-#define DDR0_08_DQS_N_EN_MASK             0x00000100
-#define DDR0_08_DQS_N_EN_ENCODE(n)          ((((unsigned long)(n))&0x1)<<8)
-#define DDR0_08_DQS_N_EN_DECODE(n)          ((((unsigned long)(n))>>8)&0x1)
-#define DDR0_08_DDRII_SDRAM_MODE_MASK     0x00000001
-#define DDR0_08_DDRII_ENCODE(n)             ((((unsigned long)(n))&0x1)<<0)
-#define DDR0_08_DDRII_DECODE(n)             ((((unsigned long)(n))>>0)&0x1)
-
-#define DDR0_09                         0x09
-#define DDR0_09_OCD_ADJUST_PDN_CS_0_MASK  0x1F000000
-#define DDR0_09_OCD_ADJUST_PDN_CS_0_ENCODE(n) ((((unsigned long)(n))&0x1F)<<24)
-#define DDR0_09_OCD_ADJUST_PDN_CS_0_DECODE(n) ((((unsigned long)(n))>>24)&0x1F)
-#define DDR0_09_RTT_0_MASK                0x00030000
-#define DDR0_09_RTT_0_ENCODE(n)             ((((unsigned long)(n))&0x3)<<16)
-#define DDR0_09_RTT_0_DECODE(n)             ((((unsigned long)(n))>>16)&0x3)
-#define DDR0_09_WR_DQS_SHIFT_BYPASS_MASK  0x00007F00
-#define DDR0_09_WR_DQS_SHIFT_BYPASS_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8)
-#define DDR0_09_WR_DQS_SHIFT_BYPASS_DECODE(n) ((((unsigned long)(n))>>8)&0x7F)
-#define DDR0_09_WR_DQS_SHIFT_MASK         0x0000007F
-#define DDR0_09_WR_DQS_SHIFT_ENCODE(n)      ((((unsigned long)(n))&0x7F)<<0)
-#define DDR0_09_WR_DQS_SHIFT_DECODE(n)      ((((unsigned long)(n))>>0)&0x7F)
-
-#define DDR0_10                         0x0A
-#define DDR0_10_WRITE_MODEREG_MASK        0x00010000 /* Write only */
-#define DDR0_10_WRITE_MODEREG_ENCODE(n)     ((((unsigned long)(n))&0x1)<<16)
-#define DDR0_10_WRITE_MODEREG_DECODE(n)     ((((unsigned long)(n))>>16)&0x1)
-#define DDR0_10_CS_MAP_MASK               0x00000300
-#define DDR0_10_CS_MAP_NO_MEM             0x00000000
-#define DDR0_10_CS_MAP_RANK0_INSTALLED    0x00000100
-#define DDR0_10_CS_MAP_RANK1_INSTALLED    0x00000200
-#define DDR0_10_CS_MAP_ENCODE(n)            ((((unsigned long)(n))&0x3)<<8)
-#define DDR0_10_CS_MAP_DECODE(n)            ((((unsigned long)(n))>>8)&0x3)
-#define DDR0_10_OCD_ADJUST_PUP_CS_0_MASK  0x0000001F
-#define DDR0_10_OCD_ADJUST_PUP_CS_0_ENCODE(n) ((((unsigned long)(n))&0x1F)<<0)
-#define DDR0_10_OCD_ADJUST_PUP_CS_0_DECODE(n) ((((unsigned long)(n))>>0)&0x1F)
-
-#define DDR0_11                         0x0B
-#define DDR0_11_SREFRESH_MASK             0x01000000
-#define DDR0_11_SREFRESH_ENCODE(n)          ((((unsigned long)(n))&0x1)<<24)
-#define DDR0_11_SREFRESH_DECODE(n)          ((((unsigned long)(n))>>24)&0x1F)
-#define DDR0_11_TXSNR_MASK                0x00FF0000
-#define DDR0_11_TXSNR_ENCODE(n)             ((((unsigned long)(n))&0xFF)<<16)
-#define DDR0_11_TXSNR_DECODE(n)             ((((unsigned long)(n))>>16)&0xFF)
-#define DDR0_11_TXSR_MASK                 0x0000FF00
-#define DDR0_11_TXSR_ENCODE(n)              ((((unsigned long)(n))&0xFF)<<8)
-#define DDR0_11_TXSR_DECODE(n)              ((((unsigned long)(n))>>8)&0xFF)
-
-#define DDR0_12                         0x0C
-#define DDR0_12_TCKE_MASK                 0x0000007
-#define DDR0_12_TCKE_ENCODE(n)              ((((unsigned long)(n))&0x7)<<0)
-#define DDR0_12_TCKE_DECODE(n)              ((((unsigned long)(n))>>0)&0x7)
-
-#define DDR0_13                         0x0D
-
-#define DDR0_14                         0x0E
-#define DDR0_14_DLL_BYPASS_MODE_MASK      0x01000000
-#define DDR0_14_DLL_BYPASS_MODE_ENCODE(n)   ((((unsigned long)(n))&0x1)<<24)
-#define DDR0_14_DLL_BYPASS_MODE_DECODE(n)   ((((unsigned long)(n))>>24)&0x1)
-#define DDR0_14_REDUC_MASK                0x00010000
-#define DDR0_14_REDUC_64BITS              0x00000000
-#define DDR0_14_REDUC_32BITS              0x00010000
-#define DDR0_14_REDUC_ENCODE(n)             ((((unsigned long)(n))&0x1)<<16)
-#define DDR0_14_REDUC_DECODE(n)             ((((unsigned long)(n))>>16)&0x1)
-#define DDR0_14_REG_DIMM_ENABLE_MASK      0x00000100
-#define DDR0_14_REG_DIMM_ENABLE_ENCODE(n)   ((((unsigned long)(n))&0x1)<<8)
-#define DDR0_14_REG_DIMM_ENABLE_DECODE(n)   ((((unsigned long)(n))>>8)&0x1)
-
-#define DDR0_15                         0x0F
-
-#define DDR0_16                         0x10
-
-#define DDR0_17                         0x11
-#define DDR0_17_DLL_DQS_DELAY_0_MASK      0x7F000000
-#define DDR0_17_DLL_DQS_DELAY_0_ENCODE(n)   ((((unsigned long)(n))&0x7F)<<24)
-#define DDR0_17_DLL_DQS_DELAY_0_DECODE(n)   ((((unsigned long)(n))>>24)&0x7F)
-#define DDR0_17_DLLLOCKREG_MASK           0x00010000 /* Read only */
-#define DDR0_17_DLLLOCKREG_LOCKED         0x00010000
-#define DDR0_17_DLLLOCKREG_UNLOCKED       0x00000000
-#define DDR0_17_DLLLOCKREG_ENCODE(n)        ((((unsigned long)(n))&0x1)<<16)
-#define DDR0_17_DLLLOCKREG_DECODE(n)        ((((unsigned long)(n))>>16)&0x1)
-#define DDR0_17_DLL_LOCK_MASK             0x00007F00 /* Read only */
-#define DDR0_17_DLL_LOCK_ENCODE(n)          ((((unsigned long)(n))&0x7F)<<8)
-#define DDR0_17_DLL_LOCK_DECODE(n)          ((((unsigned long)(n))>>8)&0x7F)
-
-#define DDR0_18                         0x12
-#define DDR0_18_DLL_DQS_DELAY_X_MASK      0x7F7F7F7F
-#define DDR0_18_DLL_DQS_DELAY_4_MASK      0x7F000000
-#define DDR0_18_DLL_DQS_DELAY_4_ENCODE(n)   ((((unsigned long)(n))&0x7F)<<24)
-#define DDR0_18_DLL_DQS_DELAY_4_DECODE(n)   ((((unsigned long)(n))>>24)&0x7F)
-#define DDR0_18_DLL_DQS_DELAY_3_MASK      0x007F0000
-#define DDR0_18_DLL_DQS_DELAY_3_ENCODE(n)   ((((unsigned long)(n))&0x7F)<<16)
-#define DDR0_18_DLL_DQS_DELAY_3_DECODE(n)   ((((unsigned long)(n))>>16)&0x7F)
-#define DDR0_18_DLL_DQS_DELAY_2_MASK      0x00007F00
-#define DDR0_18_DLL_DQS_DELAY_2_ENCODE(n)   ((((unsigned long)(n))&0x7F)<<8)
-#define DDR0_18_DLL_DQS_DELAY_2_DECODE(n)   ((((unsigned long)(n))>>8)&0x7F)
-#define DDR0_18_DLL_DQS_DELAY_1_MASK      0x0000007F
-#define DDR0_18_DLL_DQS_DELAY_1_ENCODE(n)   ((((unsigned long)(n))&0x7F)<<0)
-#define DDR0_18_DLL_DQS_DELAY_1_DECODE(n)   ((((unsigned long)(n))>>0)&0x7F)
-
-#define DDR0_19                         0x13
-#define DDR0_19_DLL_DQS_DELAY_X_MASK      0x7F7F7F7F
-#define DDR0_19_DLL_DQS_DELAY_8_MASK      0x7F000000
-#define DDR0_19_DLL_DQS_DELAY_8_ENCODE(n)   ((((unsigned long)(n))&0x7F)<<24)
-#define DDR0_19_DLL_DQS_DELAY_8_DECODE(n)   ((((unsigned long)(n))>>24)&0x7F)
-#define DDR0_19_DLL_DQS_DELAY_7_MASK      0x007F0000
-#define DDR0_19_DLL_DQS_DELAY_7_ENCODE(n)   ((((unsigned long)(n))&0x7F)<<16)
-#define DDR0_19_DLL_DQS_DELAY_7_DECODE(n)   ((((unsigned long)(n))>>16)&0x7F)
-#define DDR0_19_DLL_DQS_DELAY_6_MASK      0x00007F00
-#define DDR0_19_DLL_DQS_DELAY_6_ENCODE(n)   ((((unsigned long)(n))&0x7F)<<8)
-#define DDR0_19_DLL_DQS_DELAY_6_DECODE(n)   ((((unsigned long)(n))>>8)&0x7F)
-#define DDR0_19_DLL_DQS_DELAY_5_MASK      0x0000007F
-#define DDR0_19_DLL_DQS_DELAY_5_ENCODE(n)   ((((unsigned long)(n))&0x7F)<<0)
-#define DDR0_19_DLL_DQS_DELAY_5_DECODE(n)   ((((unsigned long)(n))>>0)&0x7F)
-
-#define DDR0_20                         0x14
-#define DDR0_20_DLL_DQS_BYPASS_3_MASK      0x7F000000
-#define DDR0_20_DLL_DQS_BYPASS_3_ENCODE(n)   ((((unsigned long)(n))&0x7F)<<24)
-#define DDR0_20_DLL_DQS_BYPASS_3_DECODE(n)   ((((unsigned long)(n))>>24)&0x7F)
-#define DDR0_20_DLL_DQS_BYPASS_2_MASK      0x007F0000
-#define DDR0_20_DLL_DQS_BYPASS_2_ENCODE(n)   ((((unsigned long)(n))&0x7F)<<16)
-#define DDR0_20_DLL_DQS_BYPASS_2_DECODE(n)   ((((unsigned long)(n))>>16)&0x7F)
-#define DDR0_20_DLL_DQS_BYPASS_1_MASK      0x00007F00
-#define DDR0_20_DLL_DQS_BYPASS_1_ENCODE(n)   ((((unsigned long)(n))&0x7F)<<8)
-#define DDR0_20_DLL_DQS_BYPASS_1_DECODE(n)   ((((unsigned long)(n))>>8)&0x7F)
-#define DDR0_20_DLL_DQS_BYPASS_0_MASK      0x0000007F
-#define DDR0_20_DLL_DQS_BYPASS_0_ENCODE(n)   ((((unsigned long)(n))&0x7F)<<0)
-#define DDR0_20_DLL_DQS_BYPASS_0_DECODE(n)   ((((unsigned long)(n))>>0)&0x7F)
-
-#define DDR0_21                         0x15
-#define DDR0_21_DLL_DQS_BYPASS_7_MASK      0x7F000000
-#define DDR0_21_DLL_DQS_BYPASS_7_ENCODE(n)   ((((unsigned long)(n))&0x7F)<<24)
-#define DDR0_21_DLL_DQS_BYPASS_7_DECODE(n)   ((((unsigned long)(n))>>24)&0x7F)
-#define DDR0_21_DLL_DQS_BYPASS_6_MASK      0x007F0000
-#define DDR0_21_DLL_DQS_BYPASS_6_ENCODE(n)   ((((unsigned long)(n))&0x7F)<<16)
-#define DDR0_21_DLL_DQS_BYPASS_6_DECODE(n)   ((((unsigned long)(n))>>16)&0x7F)
-#define DDR0_21_DLL_DQS_BYPASS_5_MASK      0x00007F00
-#define DDR0_21_DLL_DQS_BYPASS_5_ENCODE(n)   ((((unsigned long)(n))&0x7F)<<8)
-#define DDR0_21_DLL_DQS_BYPASS_5_DECODE(n)   ((((unsigned long)(n))>>8)&0x7F)
-#define DDR0_21_DLL_DQS_BYPASS_4_MASK      0x0000007F
-#define DDR0_21_DLL_DQS_BYPASS_4_ENCODE(n)   ((((unsigned long)(n))&0x7F)<<0)
-#define DDR0_21_DLL_DQS_BYPASS_4_DECODE(n)   ((((unsigned long)(n))>>0)&0x7F)
-
-#define DDR0_22                         0x16
-/* ECC */
-#define DDR0_22_CTRL_RAW_MASK             0x03000000
-#define DDR0_22_CTRL_RAW_ECC_DISABLE      0x00000000 /* ECC not being used */
-#define DDR0_22_CTRL_RAW_ECC_CHECK_ONLY   0x01000000 /* ECC checking is on, but no attempts to correct*/
-#define DDR0_22_CTRL_RAW_NO_ECC_RAM       0x02000000 /* No ECC RAM storage available */
-#define DDR0_22_CTRL_RAW_ECC_ENABLE       0x03000000 /* ECC checking and correcting on */
-#define DDR0_22_CTRL_RAW_ENCODE(n)          ((((unsigned long)(n))&0x3)<<24)
-#define DDR0_22_CTRL_RAW_DECODE(n)          ((((unsigned long)(n))>>24)&0x3)
-
-#define DDR0_22_DQS_OUT_SHIFT_BYPASS_MASK 0x007F0000
-#define DDR0_22_DQS_OUT_SHIFT_BYPASS_ENCODE(n) ((((unsigned long)(n))&0x7F)<<16)
-#define DDR0_22_DQS_OUT_SHIFT_BYPASS_DECODE(n) ((((unsigned long)(n))>>16)&0x7F)
-#define DDR0_22_DQS_OUT_SHIFT_MASK        0x00007F00
-#define DDR0_22_DQS_OUT_SHIFT_ENCODE(n)     ((((unsigned long)(n))&0x7F)<<8)
-#define DDR0_22_DQS_OUT_SHIFT_DECODE(n)     ((((unsigned long)(n))>>8)&0x7F)
-#define DDR0_22_DLL_DQS_BYPASS_8_MASK     0x0000007F
-#define DDR0_22_DLL_DQS_BYPASS_8_ENCODE(n)  ((((unsigned long)(n))&0x7F)<<0)
-#define DDR0_22_DLL_DQS_BYPASS_8_DECODE(n)  ((((unsigned long)(n))>>0)&0x7F)
-
-
-#define DDR0_23                         0x17
-#define DDR0_23_ODT_RD_MAP_CS0_MASK       0x03000000
-#define DDR0_23_ODT_RD_MAP_CS0_ENCODE(n)   ((((unsigned long)(n))&0x3)<<24)
-#define DDR0_23_ODT_RD_MAP_CS0_DECODE(n)   ((((unsigned long)(n))>>24)&0x3)
-#define DDR0_23_ECC_C_SYND_MASK           0x00FF0000 /* Read only */
-#define DDR0_23_ECC_C_SYND_ENCODE(n)        ((((unsigned long)(n))&0xFF)<<16)
-#define DDR0_23_ECC_C_SYND_DECODE(n)        ((((unsigned long)(n))>>16)&0xFF)
-#define DDR0_23_ECC_U_SYND_MASK           0x0000FF00 /* Read only */
-#define DDR0_23_ECC_U_SYND_ENCODE(n)        ((((unsigned long)(n))&0xFF)<<8)
-#define DDR0_23_ECC_U_SYND_DECODE(n)        ((((unsigned long)(n))>>8)&0xFF)
-#define DDR0_23_FWC_MASK                  0x00000001 /* Write only */
-#define DDR0_23_FWC_ENCODE(n)               ((((unsigned long)(n))&0x1)<<0)
-#define DDR0_23_FWC_DECODE(n)               ((((unsigned long)(n))>>0)&0x1)
-
-#define DDR0_24                         0x18
-#define DDR0_24_RTT_PAD_TERMINATION_MASK  0x03000000
-#define DDR0_24_RTT_PAD_TERMINATION_ENCODE(n) ((((unsigned long)(n))&0x3)<<24)
-#define DDR0_24_RTT_PAD_TERMINATION_DECODE(n) ((((unsigned long)(n))>>24)&0x3)
-#define DDR0_24_ODT_WR_MAP_CS1_MASK       0x00030000
-#define DDR0_24_ODT_WR_MAP_CS1_ENCODE(n)    ((((unsigned long)(n))&0x3)<<16)
-#define DDR0_24_ODT_WR_MAP_CS1_DECODE(n)    ((((unsigned long)(n))>>16)&0x3)
-#define DDR0_24_ODT_RD_MAP_CS1_MASK       0x00000300
-#define DDR0_24_ODT_RD_MAP_CS1_ENCODE(n)    ((((unsigned long)(n))&0x3)<<8)
-#define DDR0_24_ODT_RD_MAP_CS1_DECODE(n)    ((((unsigned long)(n))>>8)&0x3)
-#define DDR0_24_ODT_WR_MAP_CS0_MASK       0x00000003
-#define DDR0_24_ODT_WR_MAP_CS0_ENCODE(n)    ((((unsigned long)(n))&0x3)<<0)
-#define DDR0_24_ODT_WR_MAP_CS0_DECODE(n)    ((((unsigned long)(n))>>0)&0x3)
-
-#define DDR0_25                         0x19
-#define DDR0_25_VERSION_MASK              0xFFFF0000 /* Read only */
-#define DDR0_25_VERSION_ENCODE(n)           ((((unsigned long)(n))&0xFFFF)<<16)
-#define DDR0_25_VERSION_DECODE(n)           ((((unsigned long)(n))>>16)&0xFFFF)
-#define DDR0_25_OUT_OF_RANGE_LENGTH_MASK  0x000003FF /* Read only */
-#define DDR0_25_OUT_OF_RANGE_LENGTH_ENCODE(n) ((((unsigned long)(n))&0x3FF)<<0)
-#define DDR0_25_OUT_OF_RANGE_LENGTH_DECODE(n) ((((unsigned long)(n))>>0)&0x3FF)
-
-#define DDR0_26                         0x1A
-#define DDR0_26_TRAS_MAX_MASK             0xFFFF0000
-#define DDR0_26_TRAS_MAX_ENCODE(n)          ((((unsigned long)(n))&0xFFFF)<<16)
-#define DDR0_26_TRAS_MAX_DECODE(n)          ((((unsigned long)(n))>>16)&0xFFFF)
-#define DDR0_26_TREF_MASK                 0x00003FFF
-#define DDR0_26_TREF_ENCODE(n)              ((((unsigned long)(n))&0x3FFF)<<0)
-#define DDR0_26_TREF_DECODE(n)              ((((unsigned long)(n))>>0)&0x3FFF)
-
-#define DDR0_27                         0x1B
-#define DDR0_27_EMRS_DATA_MASK            0x3FFF0000
-#define DDR0_27_EMRS_DATA_ENCODE(n)         ((((unsigned long)(n))&0x3FFF)<<16)
-#define DDR0_27_EMRS_DATA_DECODE(n)         ((((unsigned long)(n))>>16)&0x3FFF)
-#define DDR0_27_TINIT_MASK                0x0000FFFF
-#define DDR0_27_TINIT_ENCODE(n)             ((((unsigned long)(n))&0xFFFF)<<0)
-#define DDR0_27_TINIT_DECODE(n)             ((((unsigned long)(n))>>0)&0xFFFF)
-
-#define DDR0_28                         0x1C
-#define DDR0_28_EMRS3_DATA_MASK           0x3FFF0000
-#define DDR0_28_EMRS3_DATA_ENCODE(n)        ((((unsigned long)(n))&0x3FFF)<<16)
-#define DDR0_28_EMRS3_DATA_DECODE(n)        ((((unsigned long)(n))>>16)&0x3FFF)
-#define DDR0_28_EMRS2_DATA_MASK           0x00003FFF
-#define DDR0_28_EMRS2_DATA_ENCODE(n)        ((((unsigned long)(n))&0x3FFF)<<0)
-#define DDR0_28_EMRS2_DATA_DECODE(n)        ((((unsigned long)(n))>>0)&0x3FFF)
-
-#define DDR0_29                         0x1D
-
-#define DDR0_30                         0x1E
-
-#define DDR0_31                         0x1F
-#define DDR0_31_XOR_CHECK_BITS_MASK       0x0000FFFF
-#define DDR0_31_XOR_CHECK_BITS_ENCODE(n)    ((((unsigned long)(n))&0xFFFF)<<0)
-#define DDR0_31_XOR_CHECK_BITS_DECODE(n)    ((((unsigned long)(n))>>0)&0xFFFF)
-
-#define DDR0_32                         0x20
-#define DDR0_32_OUT_OF_RANGE_ADDR_MASK    0xFFFFFFFF /* Read only */
-#define DDR0_32_OUT_OF_RANGE_ADDR_ENCODE(n) ((((unsigned long)(n))&0xFFFFFFFF)<<0)
-#define DDR0_32_OUT_OF_RANGE_ADDR_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFFFFFF)
-
-#define DDR0_33                         0x21
-#define DDR0_33_OUT_OF_RANGE_ADDR_MASK    0x00000001 /* Read only */
-#define DDR0_33_OUT_OF_RANGE_ADDR_ENCODE(n) ((((unsigned long)(n))&0x1)<<0)
-#define DDR0_33_OUT_OF_RANGE_ADDR_DECODE(n)               ((((unsigned long)(n))>>0)&0x1)
-
-#define DDR0_34                         0x22
-#define DDR0_34_ECC_U_ADDR_MASK           0xFFFFFFFF /* Read only */
-#define DDR0_34_ECC_U_ADDR_ENCODE(n)        ((((unsigned long)(n))&0xFFFFFFFF)<<0)
-#define DDR0_34_ECC_U_ADDR_DECODE(n)        ((((unsigned long)(n))>>0)&0xFFFFFFFF)
-
-#define DDR0_35                         0x23
-#define DDR0_35_ECC_U_ADDR_MASK           0x00000001 /* Read only */
-#define DDR0_35_ECC_U_ADDR_ENCODE(n)        ((((unsigned long)(n))&0x1)<<0)
-#define DDR0_35_ECC_U_ADDR_DECODE(n)        ((((unsigned long)(n))>>0)&0x1)
-
-#define DDR0_36                         0x24
-#define DDR0_36_ECC_U_DATA_MASK           0xFFFFFFFF /* Read only */
-#define DDR0_36_ECC_U_DATA_ENCODE(n)        ((((unsigned long)(n))&0xFFFFFFFF)<<0)
-#define DDR0_36_ECC_U_DATA_DECODE(n)        ((((unsigned long)(n))>>0)&0xFFFFFFFF)
-
-#define DDR0_37                         0x25
-#define DDR0_37_ECC_U_DATA_MASK           0xFFFFFFFF /* Read only */
-#define DDR0_37_ECC_U_DATA_ENCODE(n)        ((((unsigned long)(n))&0xFFFFFFFF)<<0)
-#define DDR0_37_ECC_U_DATA_DECODE(n)        ((((unsigned long)(n))>>0)&0xFFFFFFFF)
-
-#define DDR0_38                         0x26
-#define DDR0_38_ECC_C_ADDR_MASK           0xFFFFFFFF /* Read only */
-#define DDR0_38_ECC_C_ADDR_ENCODE(n)        ((((unsigned long)(n))&0xFFFFFFFF)<<0)
-#define DDR0_38_ECC_C_ADDR_DECODE(n)        ((((unsigned long)(n))>>0)&0xFFFFFFFF)
-
-#define DDR0_39                         0x27
-#define DDR0_39_ECC_C_ADDR_MASK           0x00000001 /* Read only */
-#define DDR0_39_ECC_C_ADDR_ENCODE(n)        ((((unsigned long)(n))&0x1)<<0)
-#define DDR0_39_ECC_C_ADDR_DECODE(n)        ((((unsigned long)(n))>>0)&0x1)
-
-#define DDR0_40                         0x28
-#define DDR0_40_ECC_C_DATA_MASK           0xFFFFFFFF /* Read only */
-#define DDR0_40_ECC_C_DATA_ENCODE(n)        ((((unsigned long)(n))&0xFFFFFFFF)<<0)
-#define DDR0_40_ECC_C_DATA_DECODE(n)        ((((unsigned long)(n))>>0)&0xFFFFFFFF)
-
-#define DDR0_41                         0x29
-#define DDR0_41_ECC_C_DATA_MASK           0xFFFFFFFF /* Read only */
-#define DDR0_41_ECC_C_DATA_ENCODE(n)        ((((unsigned long)(n))&0xFFFFFFFF)<<0)
-#define DDR0_41_ECC_C_DATA_DECODE(n)        ((((unsigned long)(n))>>0)&0xFFFFFFFF)
-
-#define DDR0_42                         0x2A
-#define DDR0_42_ADDR_PINS_MASK            0x07000000
-#define DDR0_42_ADDR_PINS_ENCODE(n)         ((((unsigned long)(n))&0x7)<<24)
-#define DDR0_42_ADDR_PINS_DECODE(n)         ((((unsigned long)(n))>>24)&0x7)
-#define DDR0_42_CASLAT_LIN_GATE_MASK      0x0000000F
-#define DDR0_42_CASLAT_LIN_GATE_ENCODE(n)   ((((unsigned long)(n))&0xF)<<0)
-#define DDR0_42_CASLAT_LIN_GATE_DECODE(n)   ((((unsigned long)(n))>>0)&0xF)
-
-#define DDR0_43                         0x2B
-#define DDR0_43_TWR_MASK                  0x07000000
-#define DDR0_43_TWR_ENCODE(n)               ((((unsigned long)(n))&0x7)<<24)
-#define DDR0_43_TWR_DECODE(n)               ((((unsigned long)(n))>>24)&0x7)
-#define DDR0_43_APREBIT_MASK              0x000F0000
-#define DDR0_43_APREBIT_ENCODE(n)           ((((unsigned long)(n))&0xF)<<16)
-#define DDR0_43_APREBIT_DECODE(n)           ((((unsigned long)(n))>>16)&0xF)
-#define DDR0_43_COLUMN_SIZE_MASK          0x00000700
-#define DDR0_43_COLUMN_SIZE_ENCODE(n)       ((((unsigned long)(n))&0x7)<<8)
-#define DDR0_43_COLUMN_SIZE_DECODE(n)       ((((unsigned long)(n))>>8)&0x7)
-#define DDR0_43_EIGHT_BANK_MODE_MASK      0x00000001
-#define DDR0_43_EIGHT_BANK_MODE_8_BANKS     0x00000001
-#define DDR0_43_EIGHT_BANK_MODE_4_BANKS     0x00000000
-#define DDR0_43_EIGHT_BANK_MODE_ENCODE(n)   ((((unsigned long)(n))&0x1)<<0)
-#define DDR0_43_EIGHT_BANK_MODE_DECODE(n)   ((((unsigned long)(n))>>0)&0x1)
-
-#define DDR0_44                         0x2C
-#define DDR0_44_TRCD_MASK                 0x000000FF
-#define DDR0_44_TRCD_ENCODE(n)              ((((unsigned long)(n))&0xFF)<<0)
-#define DDR0_44_TRCD_DECODE(n)              ((((unsigned long)(n))>>0)&0xFF)
-
-#endif /* _SPD_SDRAM_DENALI_H_ */

From 5ab884b254ca2e707ab50545cd705f30108cf491 Mon Sep 17 00:00:00 2001
From: "Lawrence R. Johnson" <lrj@acm.org>
Date: Thu, 3 Jan 2008 18:54:00 -0500
Subject: [PATCH 033/108] ppc4xx: Add functionality to GPIO support

This patch makes two additions to GPIO support:

First, it adds function gpio_read_in_bit() to read the a bit from the
GPIO Input Register (GPIOx_IR) in the same way that function
gpio_read_out_bit() reads a bit from the GPIO Output Register
(GPIOx_OR).

Second, it modifies function gpio_set_chip_configuration() to provide
an additional option for configuring the GPIO from the
"CFG_4xx_GPIO_TABLE".

According to the 440EPx User's Manual, when an alternate output is used,
the three-state control is configured in one of two ways, depending on
the particular output.  The first option is to select the corresponding
alternate three-state control in the GPIOx_TRSH/L registers.  The second
option is to select the GPIO Three-State Control Register (GPIOx_TCR) in
the GPIOx_TRSH/L registers, and set the corresponding bit in the
GPIOx_TCR register to enable the output.  For example, the Manual
specifies configuring the GPIO00 Alternate 1 Signal (PreAddr07) to use
the alternate three-state control (first option), and specifies
configuring the GPIO32 Alternate 1 Signal (USB2OM0) with the output
enabled in the GPIOx_TCR register (second option).

Currently, gpio_set_chip_configuration() configures all alternate signal
outputs to use the first option.  This patch allow the second option to
be selected by setting the "out_val" element in the table entry to
"GPIO_OUT_1".  The first option is used when the "out_val" element is
set to "GPIO_OUT_0".  Because "out_val" is not currently used when an
alternate signal is selected, and because all current GPIO tables set
"out_val" to "GPIO_OUT_0" for all alternate signals, this patch should
not change any existing configurations.

Signed-off-by: Larry Johnson <lrj@acm.org>
---
 cpu/ppc4xx/gpio.c      | 63 +++++++++++++++++++++++++++---------------
 include/asm-ppc/gpio.h |  1 +
 2 files changed, 41 insertions(+), 23 deletions(-)

diff --git a/cpu/ppc4xx/gpio.c b/cpu/ppc4xx/gpio.c
index 7b09a2f7d..37d3fa8ef 100644
--- a/cpu/ppc4xx/gpio.c
+++ b/cpu/ppc4xx/gpio.c
@@ -27,7 +27,7 @@
 #include <asm/gpio.h>
 
 #if defined(CFG_4xx_GPIO_TABLE)
-gpio_param_s gpio_tab[GPIO_GROUP_MAX][GPIO_MAX] = CFG_4xx_GPIO_TABLE;
+gpio_param_s const gpio_tab[GPIO_GROUP_MAX][GPIO_MAX] = CFG_4xx_GPIO_TABLE;
 #endif
 
 #if defined(GPIO0_OSRL)
@@ -120,6 +120,18 @@ int gpio_read_out_bit(int pin)
 	return (in_be32((void *)GPIO0_OR + offs) & GPIO_VAL(pin) ? 1 : 0);
 }
 
+int gpio_read_in_bit(int pin)
+{
+	u32 offs = 0;
+
+	if (pin >= GPIO_MAX) {
+		offs = 0x100;
+		pin -= GPIO_MAX;
+	}
+
+	return (in_be32((void *)GPIO0_IR + offs) & GPIO_VAL(pin) ? 1 : 0);
+}
+
 #if defined(CFG_4xx_GPIO_TABLE)
 void gpio_set_chip_configuration(void)
 {
@@ -171,6 +183,8 @@ void gpio_set_chip_configuration(void)
 			if ((gpio_tab[gpio_core][i].in_out == GPIO_OUT) ||
 			    (gpio_tab[gpio_core][i].in_out == GPIO_BI)) {
 
+				u32 gpio_alt_sel = 0;
+
 				switch (gpio_tab[gpio_core][i].alt_nb) {
 				case GPIO_SEL:
 					/*
@@ -199,37 +213,40 @@ void gpio_set_chip_configuration(void)
 					break;
 
 				case GPIO_ALT1:
-					reg = in_be32((void *)GPIO_OS(core_add+offs))
-						& ~(GPIO_MASK >> (j*2));
-					reg = reg | (GPIO_ALT1_SEL >> (j*2));
-					out_be32((void *)GPIO_OS(core_add+offs), reg);
-					reg = in_be32((void *)GPIO_TS(core_add+offs))
-						& ~(GPIO_MASK >> (j*2));
-					reg = reg | (GPIO_ALT1_SEL >> (j*2));
-					out_be32((void *)GPIO_TS(core_add+offs), reg);
+					gpio_alt_sel = GPIO_ALT1_SEL;
 					break;
 
 				case GPIO_ALT2:
-					reg = in_be32((void *)GPIO_OS(core_add+offs))
-						& ~(GPIO_MASK >> (j*2));
-					reg = reg | (GPIO_ALT2_SEL >> (j*2));
-					out_be32((void *)GPIO_OS(core_add+offs), reg);
-					reg = in_be32((void *)GPIO_TS(core_add+offs))
-						& ~(GPIO_MASK >> (j*2));
-					reg = reg | (GPIO_ALT2_SEL >> (j*2));
-					out_be32((void *)GPIO_TS(core_add+offs), reg);
+					gpio_alt_sel = GPIO_ALT2_SEL;
 					break;
 
 				case GPIO_ALT3:
+					gpio_alt_sel = GPIO_ALT3_SEL;
+					break;
+				}
+
+				if (0 != gpio_alt_sel) {
 					reg = in_be32((void *)GPIO_OS(core_add+offs))
 						& ~(GPIO_MASK >> (j*2));
-					reg = reg | (GPIO_ALT3_SEL >> (j*2));
+					reg = reg | (gpio_alt_sel >> (j*2));
 					out_be32((void *)GPIO_OS(core_add+offs), reg);
-					reg = in_be32((void *)GPIO_TS(core_add+offs))
-						& ~(GPIO_MASK >> (j*2));
-					reg = reg | (GPIO_ALT3_SEL >> (j*2));
-					out_be32((void *)GPIO_TS(core_add+offs), reg);
-					break;
+
+					if (gpio_tab[gpio_core][i].out_val == GPIO_OUT_1) {
+						reg = in_be32((void *)GPIO_TCR(core_add))
+							| (0x80000000 >> (i));
+						out_be32((void *)GPIO_TCR(core_add), reg);
+						reg = in_be32((void *)GPIO_TS(core_add+offs))
+							& ~(GPIO_MASK >> (j*2));
+						out_be32((void *)GPIO_TS(core_add+offs), reg);
+					} else {
+						reg = in_be32((void *)GPIO_TCR(core_add))
+							& ~(0x80000000 >> (i));
+						out_be32((void *)GPIO_TCR(core_add), reg);
+						reg = in_be32((void *)GPIO_TS(core_add+offs))
+							& ~(GPIO_MASK >> (j*2));
+						reg = reg | (gpio_alt_sel >> (j*2));
+						out_be32((void *)GPIO_TS(core_add+offs), reg);
+					}
 				}
 			}
 		}
diff --git a/include/asm-ppc/gpio.h b/include/asm-ppc/gpio.h
index d0c3eba88..c3a4a88d5 100644
--- a/include/asm-ppc/gpio.h
+++ b/include/asm-ppc/gpio.h
@@ -88,6 +88,7 @@ typedef struct {
 void gpio_config(int pin, int in_out, int gpio_alt, int out_val);
 void gpio_write_bit(int pin, int val);
 int gpio_read_out_bit(int pin);
+int gpio_read_in_bit(int pin);
 void gpio_set_chip_configuration(void);
 
 #endif /* __ASM_PPC_GPIO_H */

From b05e8bf58be9d8956fdfde3d8c8e87c140414663 Mon Sep 17 00:00:00 2001
From: "Lawrence R. Johnson" <lrj@acm.org>
Date: Fri, 4 Jan 2008 02:11:56 -0500
Subject: [PATCH 034/108] ppc4xx: Use CFG_4xx_GPIO_TABLE to configure Sequoia
 board

Note: this patch changes the configuration of some GPIO registers:

   Register      Old Value   New Value
---------------  ----------  ----------
DCR GPIO0_TCR    0x0000000F  0x0000F0CF
DCR GPIO0_TSRH   0x55005000  0x00000000
DCR GPIO1_TCR    0xC2000000  0xE2000000
DCR GPIO1_TSRL   0x0C000000  0x00200000
DCR GPIO1_ISR2L  0x00050000  0x00110000

Signed-off-by: Larry Johnson <lrj@acm.org>
---
 board/amcc/sequoia/sequoia.c | 31 +--------------
 include/configs/sequoia.h    | 77 ++++++++++++++++++++++++++++++++++++
 2 files changed, 78 insertions(+), 30 deletions(-)

diff --git a/board/amcc/sequoia/sequoia.c b/board/amcc/sequoia/sequoia.c
index 37b4f31b9..2268bc06b 100644
--- a/board/amcc/sequoia/sequoia.c
+++ b/board/amcc/sequoia/sequoia.c
@@ -26,6 +26,7 @@
 #include <libfdt.h>
 #include <fdt_support.h>
 #include <ppc440.h>
+#include <asm/gpio.h>
 #include <asm/processor.h>
 #include <asm/io.h>
 
@@ -44,36 +45,6 @@ int board_early_init_f(void)
 	mtdcr(ebccfga, xbcfg);
 	mtdcr(ebccfgd, 0xb8400000);
 
-	/*--------------------------------------------------------------------
-	 * Setup the GPIO pins
-	 *-------------------------------------------------------------------*/
-	/* test-only: take GPIO init from pcs440ep ???? in config file */
-	out_be32((u32 *) GPIO0_OR, 0x00000000);
-	out_be32((u32 *) GPIO0_TCR, 0x0000000f);
-	out_be32((u32 *) GPIO0_OSRL, 0x50015400);
-	out_be32((u32 *) GPIO0_OSRH, 0x550050aa);
-	out_be32((u32 *) GPIO0_TSRL, 0x50015400);
-	out_be32((u32 *) GPIO0_TSRH, 0x55005000);
-	out_be32((u32 *) GPIO0_ISR1L, 0x50000000);
-	out_be32((u32 *) GPIO0_ISR1H, 0x00000000);
-	out_be32((u32 *) GPIO0_ISR2L, 0x00000000);
-	out_be32((u32 *) GPIO0_ISR2H, 0x00000100);
-	out_be32((u32 *) GPIO0_ISR3L, 0x00000000);
-	out_be32((u32 *) GPIO0_ISR3H, 0x00000000);
-
-	out_be32((u32 *) GPIO1_OR, 0x00000000);
-	out_be32((u32 *) GPIO1_TCR, 0xc2000000);
-	out_be32((u32 *) GPIO1_OSRL, 0x5c280000);
-	out_be32((u32 *) GPIO1_OSRH, 0x00000000);
-	out_be32((u32 *) GPIO1_TSRL, 0x0c000000);
-	out_be32((u32 *) GPIO1_TSRH, 0x00000000);
-	out_be32((u32 *) GPIO1_ISR1L, 0x00005550);
-	out_be32((u32 *) GPIO1_ISR1H, 0x00000000);
-	out_be32((u32 *) GPIO1_ISR2L, 0x00050000);
-	out_be32((u32 *) GPIO1_ISR2H, 0x00000000);
-	out_be32((u32 *) GPIO1_ISR3L, 0x01400000);
-	out_be32((u32 *) GPIO1_ISR3H, 0x00000000);
-
 	/*--------------------------------------------------------------------
 	 * Setup the interrupt controller polarities, triggers, etc.
 	 *-------------------------------------------------------------------*/
diff --git a/include/configs/sequoia.h b/include/configs/sequoia.h
index 1f72b5488..8929134b5 100644
--- a/include/configs/sequoia.h
+++ b/include/configs/sequoia.h
@@ -476,6 +476,83 @@
 #define CFG_NAND_BASE		(CFG_NAND_ADDR + CFG_NAND_CS)
 #define CFG_NAND_SELECT_DEVICE  1	/* nand driver supports mutipl. chips	*/
 
+/*-----------------------------------------------------------------------
+ * PPC440 GPIO Configuration
+ */
+/* test-only: take GPIO init from pcs440ep ???? in config file */
+#define CFG_4xx_GPIO_TABLE { /*	  Out		  GPIO	Alternate1	Alternate2	Alternate3 */ \
+{											\
+/* GPIO Core 0 */									\
+{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO0	EBC_ADDR(7)	DMA_REQ(2)	*/	\
+{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO1	EBC_ADDR(6)	DMA_ACK(2)	*/	\
+{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO2	EBC_ADDR(5)	DMA_EOT/TC(2)	*/	\
+{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO3	EBC_ADDR(4)	DMA_REQ(3)	*/	\
+{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO4	EBC_ADDR(3)	DMA_ACK(3)	*/	\
+{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO5	EBC_ADDR(2)	DMA_EOT/TC(3)	*/	\
+{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO6	EBC_CS_N(1)			*/	\
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO7	EBC_CS_N(2)			*/	\
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO8	EBC_CS_N(3)			*/	\
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO9	EBC_CS_N(4)			*/	\
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO10 EBC_CS_N(5)			*/	\
+{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO11 EBC_BUS_ERR			*/	\
+{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO12				*/	\
+{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO13				*/	\
+{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO14				*/	\
+{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO15				*/	\
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO16 GMCTxD(4)			*/	\
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO17 GMCTxD(5)			*/	\
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO18 GMCTxD(6)			*/	\
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO19 GMCTxD(7)			*/	\
+{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO20 RejectPkt0			*/	\
+{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO21 RejectPkt1			*/	\
+{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO22				*/	\
+{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO23 SCPD0				*/	\
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO24 GMCTxD(2)			*/	\
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO25 GMCTxD(3)			*/	\
+{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO26				*/	\
+{GPIO0_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO27 EXT_EBC_REQ	USB2D_RXERROR	*/	\
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO28		USB2D_TXVALID	*/	\
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO29 EBC_EXT_HDLA	USB2D_PAD_SUSPNDM */	\
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO30 EBC_EXT_ACK	USB2D_XCVRSELECT*/	\
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO31 EBC_EXR_BUSREQ	USB2D_TERMSELECT*/	\
+},											\
+{											\
+/* GPIO Core 1 */									\
+{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO32 USB2D_OPMODE0	EBC_DATA(2)	*/	\
+{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO33 USB2D_OPMODE1	EBC_DATA(3)	*/	\
+{GPIO1_BASE, GPIO_OUT, GPIO_ALT3, GPIO_OUT_1}, /* GPIO34 UART0_DCD_N	UART1_DSR_CTS_N	UART2_SOUT*/ \
+{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO35 UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN*/ \
+{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO36 UART0_8PIN_CTS_N EBC_DATA(0)	UART3_SIN*/ \
+{GPIO1_BASE, GPIO_BI , GPIO_ALT2, GPIO_OUT_0}, /* GPIO37 UART0_RTS_N	EBC_DATA(1)	UART3_SOUT*/ \
+{GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO38 UART0_DTR_N	UART1_SOUT	*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO39 UART0_RI_N	UART1_SIN	*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO40 UIC_IRQ(0)			*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO41 UIC_IRQ(1)			*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO42 UIC_IRQ(2)			*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO43 UIC_IRQ(3)			*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO44 UIC_IRQ(4)	DMA_ACK(1)	*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO45 UIC_IRQ(6)	DMA_EOT/TC(1)	*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO46 UIC_IRQ(7)	DMA_REQ(0)	*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO47 UIC_IRQ(8)	DMA_ACK(0)	*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO48 UIC_IRQ(9)	DMA_EOT/TC(0)	*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO49  Unselect via TraceSelect Bit	*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO50  Unselect via TraceSelect Bit	*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO51  Unselect via TraceSelect Bit	*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO52  Unselect via TraceSelect Bit	*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO53  Unselect via TraceSelect Bit	*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO54  Unselect via TraceSelect Bit	*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO55  Unselect via TraceSelect Bit	*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO56  Unselect via TraceSelect Bit	*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO57  Unselect via TraceSelect Bit	*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO58  Unselect via TraceSelect Bit	*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO59  Unselect via TraceSelect Bit	*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO60  Unselect via TraceSelect Bit	*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO61  Unselect via TraceSelect Bit	*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO62  Unselect via TraceSelect Bit	*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO63  Unselect via TraceSelect Bit	*/	\
+}											\
+}
+
 /*
  * Internal Definitions
  *

From 0ddd969aec532bd7eae30fc09590488a3aaa629a Mon Sep 17 00:00:00 2001
From: "Lawrence R. Johnson" <lrj@acm.org>
Date: Thu, 3 Jan 2008 15:02:02 -0500
Subject: [PATCH 035/108] ppc4xx: Use CFG_4xx_GPIO_TABLE to configure Korat
 board

Signed-off-by: Larry Johnson <lrj@acm.org>
---
 board/korat/korat.c     | 117 +++---------------------------
 include/configs/korat.h | 153 +++++++++++++++++++++++++++++++++++++++-
 2 files changed, 161 insertions(+), 109 deletions(-)

diff --git a/board/korat/korat.c b/board/korat/korat.c
index 7cb9ee11f..199c1ff9d 100644
--- a/board/korat/korat.c
+++ b/board/korat/korat.c
@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2007
+ * (C) Copyright 2007-2008
  * Larry Johnson, lrj@acm.org
  *
  * (C) Copyright 2006
@@ -26,6 +26,7 @@
  */
 
 #include <common.h>
+#include <asm/gpio.h>
 #include <asm/processor.h>
 #include <asm-ppc/io.h>
 #include <i2c.h>
@@ -40,109 +41,12 @@ ulong flash_get_size(ulong base, int banknum);
 int board_early_init_f(void)
 {
 	u32 sdr0_pfc1, sdr0_pfc2;
-	u32 gpio0_ir;
 	u32 reg;
 	int eth;
 
 	mtdcr(ebccfga, xbcfg);
 	mtdcr(ebccfgd, 0xb8400000);
 
-	/*--------------------------------------------------------------------
-	 * Setup the GPIO pins
-	 *
-	 * Korat GPIO usage:
-	 *
-	 *                   Init.
-	 * Pin    Source I/O value Function
-	 * ------ ------ --- ----- ---------------------------------
-	 * GPIO00  Alt1  I/O   x   PerAddr07
-	 * GPIO01  Alt1  I/O   x   PerAddr06
-	 * GPIO02  Alt1  I/O   x   PerAddr05
-	 * GPIO03  GPIO   x    x   GPIO03 to expansion bus connector
-	 * GPIO04  GPIO   x    x   GPIO04 to expansion bus connector
-	 * GPIO05  GPIO   x    x   GPIO05 to expansion bus connector
-	 * GPIO06  Alt1   O    x   PerCS1 (2nd NOR flash)
-	 * GPIO07  Alt1   O    x   PerCS2 (CPLD)
-	 * GPIO08  Alt1   O    x   PerCS3 to expansion bus connector
-	 * GPIO09  Alt1   O    x   PerCS4 to expansion bus connector
-	 * GPIO10  Alt1   O    x   PerCS5 to expansion bus connector
-	 * GPIO11  Alt1   I    x   PerErr
-	 * GPIO12  GPIO   O    0   ATMega !Reset
-	 * GPIO13  GPIO   O    1   SPI Atmega !SS
-	 * GPIO14  GPIO   O    1   Write protect EEPROM #1 (0xA8)
-	 * GPIO15  GPIO   O    0   CPU Run LED !On
-	 * GPIO16  Alt1   O    x   GMC1TxD0
-	 * GPIO17  Alt1   O    x   GMC1TxD1
-	 * GPIO18  Alt1   O    x   GMC1TxD2
-	 * GPIO19  Alt1   O    x   GMC1TxD3
-	 * GPIO20  Alt1   O    x   RejectPkt0
-	 * GPIO21  Alt1   O    x   RejectPkt1
-	 * GPIO22  GPIO   I    x   PGOOD_DDR
-	 * GPIO23  Alt1   O    x   SCPD0
-	 * GPIO24  Alt1   O    x   GMC0TxD2
-	 * GPIO25  Alt1   O    x   GMC0TxD3
-	 * GPIO26  GPIO? I/O   x   IIC0SDA (selected in SDR0_PFC4)
-	 * GPIO27  GPIO   O    0   PHY #0 1000BASE-X
-	 * GPIO28  GPIO   O    0   PHY #1 1000BASE-X
-	 * GPIO29  GPIO   I    x   Test jumper !Present
-	 * GPIO30  GPIO   I    x   SFP module #0 !Present
-	 * GPIO31  GPIO   I    x   SFP module #1 !Present
-	 *
-	 * GPIO32  GPIO   O    1   SFP module #0 Tx !Enable
-	 * GPIO33  GPIO   O    1   SFP module #1 Tx !Enable
-	 * GPIO34  Alt2   I    x   !UART1_CTS
-	 * GPIO35  Alt2   O    x   !UART1_RTS
-	 * GPIO36  Alt1   I    x   !UART0_CTS
-	 * GPIO37  Alt1   O    x   !UART0_RTS
-	 * GPIO38  Alt2   O    x   UART1_Tx
-	 * GPIO39  Alt2   I    x   UART1_Rx
-	 * GPIO40  Alt1   I    x   IRQ0 (Ethernet 0)
-	 * GPIO41  Alt1   I    x   IRQ1 (Ethernet 1)
-	 * GPIO42  Alt1   I    x   IRQ2 (PCI interrupt)
-	 * GPIO43  Alt1   I    x   IRQ3 (System Alert from CPLD)
-	 * GPIO44  xxxx   x    x   (grounded through pulldown)
-	 * GPIO45  GPIO   O    0   PHY #0 Enable
-	 * GPIO46  GPIO   O    0   PHY #1 Enable
-	 * GPIO47  GPIO   I    x   Reset switch !Pressed
-	 * GPIO48  GPIO   I    x   Shutdown switch !Pressed
-	 * GPIO49  xxxx   x    x   (reserved for trace port)
-	 *   .      .     .    .               .
-	 *   .      .     .    .               .
-	 *   .      .     .    .               .
-	 * GPIO63  xxxx   x    x   (reserved for trace port)
-	 *-------------------------------------------------------------------*/
-
-	out_be32((u32 *) GPIO0_OR, 0x00060000);
-	out_be32((u32 *) GPIO1_OR, 0xC0000000);
-
-	out_be32((u32 *) GPIO0_OSRL, 0x54055400);
-	out_be32((u32 *) GPIO0_OSRH, 0x55015000);
-	out_be32((u32 *) GPIO1_OSRL, 0x02180000);
-	out_be32((u32 *) GPIO1_OSRH, 0x00000000);
-
-	out_be32((u32 *) GPIO0_TSRL, 0x54055500);
-	out_be32((u32 *) GPIO0_TSRH, 0x00015000);
-	out_be32((u32 *) GPIO1_TSRL, 0x00000000);
-	out_be32((u32 *) GPIO1_TSRH, 0x00000000);
-
-	out_be32((u32 *) GPIO0_TCR, 0x000FF0D8);
-	out_be32((u32 *) GPIO1_TCR, 0xD6060000);
-
-	out_be32((u32 *) GPIO0_ISR1L, 0x54000100);
-	out_be32((u32 *) GPIO0_ISR1H, 0x00500000);
-	out_be32((u32 *) GPIO1_ISR1L, 0x00405500);
-	out_be32((u32 *) GPIO1_ISR1H, 0x00000000);
-
-	out_be32((u32 *) GPIO0_ISR2L, 0x00000000);
-	out_be32((u32 *) GPIO0_ISR2H, 0x00000000);
-	out_be32((u32 *) GPIO1_ISR2L, 0x04010000);
-	out_be32((u32 *) GPIO1_ISR2H, 0x00000000);
-
-	out_be32((u32 *) GPIO0_ISR3L, 0x00000000);
-	out_be32((u32 *) GPIO0_ISR3H, 0x00000000);
-	out_be32((u32 *) GPIO1_ISR3L, 0x00000000);
-	out_be32((u32 *) GPIO1_ISR3H, 0x00000000);
-
 	/*--------------------------------------------------------------------
 	 * Setup the interrupt controller polarities, triggers, etc.
 	 *-------------------------------------------------------------------*/
@@ -176,9 +80,8 @@ int board_early_init_f(void)
 	/* Configure the two Ethernet PHYs.  For each PHY, configure for fiber
 	 * if the SFP module is present, and for copper if it is not present.
 	 */
-	gpio0_ir = in_be32((u32 *) GPIO0_IR);
 	for (eth = 0; eth < 2; ++eth) {
-		if (gpio0_ir & (0x00000001 << (1 - eth))) {
+		if (gpio_read_in_bit(CFG_GPIO_SFP0_PRESENT_ + eth)) {
 			/* SFP module not present: configure PHY for copper. */
 			/* Set PHY to autonegotate 10 MB, 100MB, or 1 GB */
 			out_8((u8 *) CFG_CPLD_BASE + 0x06,
@@ -187,14 +90,13 @@ int board_early_init_f(void)
 		} else {
 			/* SFP module present: configure PHY for fiber and
 			   enable output */
-			out_be32((u32 *) GPIO0_OR, in_be32((u32 *) GPIO0_OR) |
-				 (0x00000001 << (4 - eth)));
-			out_be32((u32 *) GPIO1_OR, in_be32((u32 *) GPIO1_OR) &
-				 ~(0x00000001 << (31 - eth)));
+			gpio_write_bit(CFG_GPIO_PHY0_FIBER_SEL + eth, 1);
+			gpio_write_bit(CFG_GPIO_SFP0_TX_EN_ + eth, 0);
 		}
 	}
 	/* enable Ethernet: set GPIO45 and GPIO46 to 1 */
-	out_be32((u32 *) GPIO1_OR, in_be32((u32 *) GPIO1_OR) | 0x00060000);
+	gpio_write_bit(CFG_GPIO_PHY0_EN, 1);
+	gpio_write_bit(CFG_GPIO_PHY1_EN, 1);
 
 	/* select Ethernet pins */
 	mfsdr(SDR0_PFC1, sdr0_pfc1);
@@ -525,20 +427,19 @@ int checkboard(void)
 {
 	char const *const s = getenv("serial#");
 	u8 const rev = in_8((u8 *) CFG_CPLD_BASE + 0);
-	u32 const gpio0_or = in_be32((u32 *) GPIO0_OR);
 
 	printf("Board: Korat, Rev. %X", rev);
 	if (s != NULL)
 		printf(", serial# %s", s);
 
 	printf(", Ethernet PHY 0: ");
-	if (gpio0_or & 0x00000010)
+	if (gpio_read_out_bit(CFG_GPIO_PHY0_FIBER_SEL))
 		printf("fiber");
 	else
 		printf("copper");
 
 	printf(", PHY 1: ");
-	if (gpio0_or & 0x00000008)
+	if (gpio_read_out_bit(CFG_GPIO_PHY1_FIBER_SEL))
 		printf("fiber");
 	else
 		printf("copper");
diff --git a/include/configs/korat.h b/include/configs/korat.h
index 1ea7d4894..7d0640bbc 100644
--- a/include/configs/korat.h
+++ b/include/configs/korat.h
@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2007
+ * (C) Copyright 2007-2008
  * Larry Johnson, lrj@acm.org
  *
  * (C) Copyright 2006-2007
@@ -361,6 +361,157 @@
 #define CFG_EBC_PB2AP		0x04017300
 #define CFG_EBC_PB2CR		(CFG_CPLD_BASE | 0x00038000)
 
+/*-----------------------------------------------------------------------
+ * GPIO Setup
+ *
+ * Korat GPIO usage:
+ *
+ *                   Init.
+ * Pin    Source I/O value Function
+ * ------ ------ --- ----- ---------------------------------
+ * GPIO00  Alt1  I/O   x   PerAddr07
+ * GPIO01  Alt1  I/O   x   PerAddr06
+ * GPIO02  Alt1  I/O   x   PerAddr05
+ * GPIO03  GPIO   x    x   GPIO03 to expansion bus connector
+ * GPIO04  GPIO   x    x   GPIO04 to expansion bus connector
+ * GPIO05  GPIO   x    x   GPIO05 to expansion bus connector
+ * GPIO06  Alt1   O    x   PerCS1 (2nd NOR flash)
+ * GPIO07  Alt1   O    x   PerCS2 (CPLD)
+ * GPIO08  Alt1   O    x   PerCS3 to expansion bus connector
+ * GPIO09  Alt1   O    x   PerCS4 to expansion bus connector
+ * GPIO10  Alt1   O    x   PerCS5 to expansion bus connector
+ * GPIO11  Alt1   I    x   PerErr
+ * GPIO12  GPIO   O    0   ATMega !Reset
+ * GPIO13  GPIO   O    1   SPI Atmega !SS
+ * GPIO14  GPIO   O    1   Write protect EEPROM #1 (0xA8)
+ * GPIO15  GPIO   O    0   CPU Run LED !On
+ * GPIO16  Alt1   O    x   GMC1TxD0
+ * GPIO17  Alt1   O    x   GMC1TxD1
+ * GPIO18  Alt1   O    x   GMC1TxD2
+ * GPIO19  Alt1   O    x   GMC1TxD3
+ * GPIO20  Alt1   I    x   RejectPkt0
+ * GPIO21  Alt1   I    x   RejectPkt1
+ * GPIO22  GPIO   I    x   PGOOD_DDR
+ * GPIO23  Alt1   O    x   SCPD0
+ * GPIO24  Alt1   O    x   GMC0TxD2
+ * GPIO25  Alt1   O    x   GMC0TxD3
+ * GPIO26  GPIO? I/O   x   IIC0SDA (selected in SDR0_PFC4)
+ * GPIO27  GPIO   O    0   PHY #0 1000BASE-X select
+ * GPIO28  GPIO   O    0   PHY #1 1000BASE-X select
+ * GPIO29  GPIO   I    x   Test jumper !Present
+ * GPIO30  GPIO   I    x   SFP module #0 !Present
+ * GPIO31  GPIO   I    x   SFP module #1 !Present
+ *
+ * GPIO32  GPIO   O    1   SFP module #0 Tx !Enable
+ * GPIO33  GPIO   O    1   SFP module #1 Tx !Enable
+ * GPIO34  Alt2   I    x   !UART1_CTS
+ * GPIO35  Alt2   O    x   !UART1_RTS
+ * GPIO36  Alt1   I    x   !UART0_CTS
+ * GPIO37  Alt1   O    x   !UART0_RTS
+ * GPIO38  Alt2   O    x   UART1_Tx
+ * GPIO39  Alt2   I    x   UART1_Rx
+ * GPIO40  Alt1   I    x   IRQ0 (Ethernet 0)
+ * GPIO41  Alt1   I    x   IRQ1 (Ethernet 1)
+ * GPIO42  Alt1   I    x   IRQ2 (PCI interrupt)
+ * GPIO43  Alt1   I    x   IRQ3 (System Alert from CPLD)
+ * GPIO44  xxxx   x    x   (grounded through pulldown)
+ * GPIO45  GPIO   O    0   PHY #0 Enable
+ * GPIO46  GPIO   O    0   PHY #1 Enable
+ * GPIO47  GPIO   I    x   Reset switch !Pressed
+ * GPIO48  GPIO   I    x   Shutdown switch !Pressed
+ * GPIO49  xxxx   x    x   (reserved for trace port)
+ *   .      .     .    .               .
+ *   .      .     .    .               .
+ *   .      .     .    .               .
+ * GPIO63  xxxx   x    x   (reserved for trace port)
+*----------------------------------------------------------------------*/
+
+#define CFG_GPIO_ATMEGA_SS_	13
+#define CFG_GPIO_PHY0_FIBER_SEL	27
+#define CFG_GPIO_PHY1_FIBER_SEL	28
+#define CFG_GPIO_SFP0_PRESENT_	30
+#define CFG_GPIO_SFP1_PRESENT_	31
+#define CFG_GPIO_SFP0_TX_EN_	32
+#define CFG_GPIO_SFP1_TX_EN_	33
+#define CFG_GPIO_PHY0_EN	45
+#define CFG_GPIO_PHY1_EN	46
+
+/*-----------------------------------------------------------------------
+ * PPC440 GPIO Configuration
+ */
+#define CFG_4xx_GPIO_TABLE { /*	  Out		  GPIO	Alternate1	Alternate2	Alternate3 */ \
+{											\
+/* GPIO Core 0 */									\
+{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO0	EBC_ADDR(7)	DMA_REQ(2)	*/	\
+{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO1	EBC_ADDR(6)	DMA_ACK(2)	*/	\
+{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO2	EBC_ADDR(5)	DMA_EOT/TC(2)	*/	\
+{GPIO0_BASE, GPIO_DIS, GPIO_SEL , GPIO_OUT_0}, /* GPIO3	EBC_ADDR(4)	DMA_REQ(3)	*/	\
+{GPIO0_BASE, GPIO_DIS, GPIO_SEL , GPIO_OUT_0}, /* GPIO4	EBC_ADDR(3)	DMA_ACK(3)	*/	\
+{GPIO0_BASE, GPIO_DIS, GPIO_SEL , GPIO_OUT_0}, /* GPIO5	EBC_ADDR(2)	DMA_EOT/TC(3)	*/	\
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO6	EBC_CS_N(1)			*/	\
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO7	EBC_CS_N(2)			*/	\
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO8	EBC_CS_N(3)			*/	\
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO9	EBC_CS_N(4)			*/	\
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO10 EBC_CS_N(5)			*/	\
+{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO11 EBC_BUS_ERR			*/	\
+{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO12				*/	\
+{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO13				*/	\
+{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO14				*/	\
+{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO15				*/	\
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO16 GMCTxD(4)			*/	\
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO17 GMCTxD(5)			*/	\
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO18 GMCTxD(6)			*/	\
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO19 GMCTxD(7)			*/	\
+{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO20 RejectPkt0			*/	\
+{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO21 RejectPkt1			*/	\
+{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO22				*/	\
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO23 SCPD0				*/	\
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO24 GMCTxD(2)			*/	\
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO25 GMCTxD(3)			*/	\
+{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO26				*/	\
+{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO27 EXT_EBC_REQ	USB2D_RXERROR	*/	\
+{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO28		USB2D_TXVALID	*/	\
+{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO29 EBC_EXT_HDLA	USB2D_PAD_SUSPNDM */	\
+{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO30 EBC_EXT_ACK	USB2D_XCVRSELECT*/	\
+{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO31 EBC_EXR_BUSREQ	USB2D_TERMSELECT*/	\
+},											\
+{											\
+/* GPIO Core 1 */									\
+{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO32 USB2D_OPMODE0	EBC_DATA(2)	*/	\
+{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO33 USB2D_OPMODE1	EBC_DATA(3)	*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO34 UART0_DCD_N	UART1_DSR_CTS_N	UART2_SOUT*/ \
+{GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO35 UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN*/ \
+{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO36 UART0_8PIN_CTS_N EBC_DATA(0)	UART3_SIN*/ \
+{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO37 UART0_RTS_N	EBC_DATA(1)	UART3_SOUT*/ \
+{GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO38 UART0_DTR_N	UART1_SOUT	*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO39 UART0_RI_N	UART1_SIN	*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO40 UIC_IRQ(0)			*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO41 UIC_IRQ(1)			*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO42 UIC_IRQ(2)			*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO43 UIC_IRQ(3)			*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO44 UIC_IRQ(4)	DMA_ACK(1)	*/	\
+{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO45 UIC_IRQ(6)	DMA_EOT/TC(1)	*/	\
+{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO46 UIC_IRQ(7)	DMA_REQ(0)	*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO47 UIC_IRQ(8)	DMA_ACK(0)	*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO48 UIC_IRQ(9)	DMA_EOT/TC(0)	*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO49  Unselect via TraceSelect Bit	*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO50  Unselect via TraceSelect Bit	*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO51  Unselect via TraceSelect Bit	*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO52  Unselect via TraceSelect Bit	*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO53  Unselect via TraceSelect Bit	*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO54  Unselect via TraceSelect Bit	*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO55  Unselect via TraceSelect Bit	*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO56  Unselect via TraceSelect Bit	*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO57  Unselect via TraceSelect Bit	*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO58  Unselect via TraceSelect Bit	*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO59  Unselect via TraceSelect Bit	*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO60  Unselect via TraceSelect Bit	*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO61  Unselect via TraceSelect Bit	*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO62  Unselect via TraceSelect Bit	*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO63  Unselect via TraceSelect Bit	*/	\
+}											\
+}
+
 /*
  * Internal Definitions
  *

From fe9c26b330a21ce73e52b5bd347d725cb81e3cfb Mon Sep 17 00:00:00 2001
From: Stefan Roese <sr@denx.de>
Date: Fri, 4 Jan 2008 12:00:01 +0100
Subject: [PATCH 036/108] ppc4xx: Fix Sequoia NAND booting target

The Sequoia NAND booting target now uses the recently extracted
cpu/ppc4xx/denali_data_eye.c file too.

Signed-off-by: Stefan Roese <sr@denx.de>
---
 nand_spl/board/amcc/sequoia/Makefile | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/nand_spl/board/amcc/sequoia/Makefile b/nand_spl/board/amcc/sequoia/Makefile
index 78bf071f5..dfa0ce39e 100644
--- a/nand_spl/board/amcc/sequoia/Makefile
+++ b/nand_spl/board/amcc/sequoia/Makefile
@@ -30,7 +30,7 @@ AFLAGS	+= -DCONFIG_NAND_SPL
 CFLAGS	+= -DCONFIG_NAND_SPL
 
 SOBJS	= start.o init.o resetvec.o
-COBJS	= nand_boot.o nand_ecc.o ndfc.o sdram.o
+COBJS	= denali_data_eye.o nand_boot.o nand_ecc.o ndfc.o sdram.o
 
 SRCS	:= $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c))
 OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
@@ -57,6 +57,10 @@ $(nandobj)u-boot-spl:	$(OBJS)
 # create symbolic links for common files
 
 # from cpu directory
+$(obj)denali_data_eye.c:
+	@rm -f $(obj)denali_data_eye.c
+	ln -s $(SRCTREE)/cpu/ppc4xx/denali_data_eye.c $(obj)denali_data_eye.c
+
 $(obj)ndfc.c:
 	@rm -f $(obj)ndfc.c
 	ln -s $(SRCTREE)/cpu/ppc4xx/ndfc.c $(obj)ndfc.c

From 9ac6b6f3d3f1b072d89268b2efe47e95e6659489 Mon Sep 17 00:00:00 2001
From: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
Date: Wed, 2 Jan 2008 12:05:14 +0100
Subject: [PATCH 037/108] ppc4xx: More cleanup for esd's LCD code

Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
---
 board/esd/common/lcd.c | 38 ++++++++++++++++++--------------------
 1 file changed, 18 insertions(+), 20 deletions(-)

diff --git a/board/esd/common/lcd.c b/board/esd/common/lcd.c
index 4116838b2..ed50def48 100644
--- a/board/esd/common/lcd.c
+++ b/board/esd/common/lcd.c
@@ -37,41 +37,41 @@ int lcd_depth;
 unsigned char *glob_lcd_reg;
 unsigned char *glob_lcd_mem;
 
-#ifdef CFG_LCD_ENDIAN
+#if defined(CFG_LCD_ENDIAN)
 void lcd_setup(int lcd, int config)
 {
 	if (lcd == 0) {
 		/*
 		 * Set endianess and reset lcd controller 0 (small)
 		 */
-		out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_LCD0_RST); /* set reset to low */
+		out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~CFG_LCD0_RST); /* set reset to low */
 		udelay(10); /* wait 10us */
 		if (config == 1)
-			out32(GPIO0_OR, in32(GPIO0_OR) | CFG_LCD_ENDIAN); /* big-endian */
+			out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CFG_LCD_ENDIAN); /* big-endian */
 		else
-			out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_LCD_ENDIAN); /* little-endian */
+			out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~CFG_LCD_ENDIAN); /* little-endian */
 		udelay(10); /* wait 10us */
-		out32(GPIO0_OR, in32(GPIO0_OR) | CFG_LCD0_RST); /* set reset to high */
+		out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CFG_LCD0_RST); /* set reset to high */
 	} else {
 		/*
 		 * Set endianess and reset lcd controller 1 (big)
 		 */
-		out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_LCD1_RST); /* set reset to low */
+		out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~CFG_LCD1_RST); /* set reset to low */
 		udelay(10); /* wait 10us */
 		if (config == 1)
-			out32(GPIO0_OR, in32(GPIO0_OR) | CFG_LCD_ENDIAN); /* big-endian */
+			out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CFG_LCD_ENDIAN); /* big-endian */
 		else
-			out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_LCD_ENDIAN); /* little-endian */
+			out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~CFG_LCD_ENDIAN); /* little-endian */
 		udelay(10); /* wait 10us */
-		out32(GPIO0_OR, in32(GPIO0_OR) | CFG_LCD1_RST); /* set reset to high */
+		out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CFG_LCD1_RST); /* set reset to high */
 	}
 
 	/*
 	 * CFG_LCD_ENDIAN may also be FPGA_RESET, so set inactive
 	 */
-	out32(GPIO0_OR, in32(GPIO0_OR) | CFG_LCD_ENDIAN); /* set reset high again */
+	out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CFG_LCD_ENDIAN); /* set reset high again */
 }
-#endif /* #ifdef CFG_LCD_ENDIAN */
+#endif /* CFG_LCD_ENDIAN */
 
 
 void lcd_bmp(uchar *logo_bmp)
@@ -93,7 +93,6 @@ void lcd_bmp(uchar *logo_bmp)
 	 * Check for bmp mark 'BM'
 	 */
 	if (*(ushort *)logo_bmp != 0x424d) {
-
 		/*
 		 * Decompress bmp image
 		 */
@@ -160,7 +159,7 @@ void lcd_bmp(uchar *logo_bmp)
 	 */
 	if ((colors <= 256) && (lcd_depth <= 8)) {
 		ptr = (unsigned char *)(dst + 14 + 40);
-		for (i=0; i<colors; i++) {
+		for (i = 0; i < colors; i++) {
 			b = *ptr++;
 			g = *ptr++;
 			r = *ptr++;
@@ -175,11 +174,11 @@ void lcd_bmp(uchar *logo_bmp)
 	ptr = glob_lcd_mem;
 	ptr2 = (ushort *)glob_lcd_mem;
 	header_size = 14 + 40 + 4*colors;          /* skip bmp header */
-	for (y=0; y<height; y++) {
+	for (y = 0; y < height; y++) {
 		bmp = &dst[(height-1-y)*line_size + header_size];
 		if (lcd_depth == 16) {
 			if (bpp == 24) {
-				for (x=0; x<width; x++) {
+				for (x = 0; x < width; x++) {
 					/*
 					 * Generate epson 16bpp fb-format from 24bpp image
 					 */
@@ -190,7 +189,7 @@ void lcd_bmp(uchar *logo_bmp)
 					*ptr2++ = val;
 				}
 			} else if (bpp == 8) {
-				for (x=0; x<line_size; x++) {
+				for (x = 0; x < line_size; x++) {
 					/* query rgb value from palette */
 					ptr = (unsigned char *)(dst + 14 + 40) ;
 					ptr += (*bmp++) << 2;
@@ -202,9 +201,8 @@ void lcd_bmp(uchar *logo_bmp)
 				}
 			}
 		} else {
-			for (x=0; x<line_size; x++) {
+			for (x = 0; x < line_size; x++)
 				*ptr++ = *bmp++;
-			}
 		}
 	}
 
@@ -254,7 +252,7 @@ void lcd_init(uchar *lcd_reg, uchar *lcd_mem, S1D_REGS *regs, int reg_count,
 		palette_value = 0x17;
 		lcd_depth = 8;
 		puts("LCD:   S1D13704");
-	      } else if (in_8(&lcd_reg[0x10000]) == 0x24) {
+	} else if (in_8(&lcd_reg[0x10000]) == 0x24) {
 		/*
 		 * Small epson detected (705)
 		 */
@@ -296,7 +294,7 @@ void lcd_init(uchar *lcd_reg, uchar *lcd_mem, S1D_REGS *regs, int reg_count,
 	lcd_bmp(logo_bmp);
 }
 
-#ifdef CONFIG_VIDEO_SM501
+#if defined(CONFIG_VIDEO_SM501)
 int do_esdbmp(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 {
 	ulong addr;

From 34065a2ce0d8972f2ec6652076014ab243d2ce8a Mon Sep 17 00:00:00 2001
From: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
Date: Wed, 2 Jan 2008 16:48:34 +0100
Subject: [PATCH 038/108] ppc4xx: use common denali core defines and data eye
 search code for PMC440

Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
---
 board/esd/pmc440/sdram.c | 342 +--------------------------------------
 1 file changed, 4 insertions(+), 338 deletions(-)

diff --git a/board/esd/pmc440/sdram.c b/board/esd/pmc440/sdram.c
index 78e2cb42a..7f92d3772 100644
--- a/board/esd/pmc440/sdram.c
+++ b/board/esd/pmc440/sdram.c
@@ -33,343 +33,9 @@
 #include <asm/io.h>
 #include <ppc440.h>
 
-#include "sdram.h"
+extern int denali_wait_for_dlllock(void);
+extern void denali_core_search_data_eye(void);
 
-#if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) || \
-	defined(CONFIG_DDR_DATA_EYE)
-/*-----------------------------------------------------------------------------+
- * wait_for_dlllock.
- +----------------------------------------------------------------------------*/
-static int wait_for_dlllock(void)
-{
-	unsigned long val;
-	int wait = 0;
-
-	/* -----------------------------------------------------------+
-	 * Wait for the DCC master delay line to finish calibration
-	 * ----------------------------------------------------------*/
-	mtdcr(ddrcfga, DDR0_17);
-	val = DDR0_17_DLLLOCKREG_UNLOCKED;
-
-	while (wait != 0xffff) {
-		val = mfdcr(ddrcfgd);
-		if ((val & DDR0_17_DLLLOCKREG_MASK) == DDR0_17_DLLLOCKREG_LOCKED)
-			/* dlllockreg bit on */
-			return 0;
-		else
-			wait++;
-	}
-	debug("0x%04x: DDR0_17 Value (dlllockreg bit): 0x%08x\n", wait, val);
-	debug("Waiting for dlllockreg bit to raise\n");
-
-	return -1;
-}
-#endif
-
-#if defined(CONFIG_DDR_DATA_EYE)
-/*-----------------------------------------------------------------------------+
- * wait_for_dram_init_complete.
- +----------------------------------------------------------------------------*/
-int wait_for_dram_init_complete(void)
-{
-	unsigned long val;
-	int wait = 0;
-
-	/* --------------------------------------------------------------+
-	 * Wait for 'DRAM initialization complete' bit in status register
-	 * -------------------------------------------------------------*/
-	mtdcr(ddrcfga, DDR0_00);
-
-	while (wait != 0xffff) {
-		val = mfdcr(ddrcfgd);
-		if ((val & DDR0_00_INT_STATUS_BIT6) == DDR0_00_INT_STATUS_BIT6)
-			/* 'DRAM initialization complete' bit */
-			return 0;
-		else
-			wait++;
-	}
-
-	debug("DRAM initialization complete bit in status register did not rise\n");
-
-	return -1;
-}
-
-#define NUM_TRIES 64
-#define NUM_READS 10
-
-/*-----------------------------------------------------------------------------+
- * denali_core_search_data_eye.
- +----------------------------------------------------------------------------*/
-void denali_core_search_data_eye(unsigned long memory_size)
-{
-	int k, j;
-	u32 val;
-	u32 wr_dqs_shift, dqs_out_shift, dll_dqs_delay_X;
-	u32 max_passing_cases = 0, wr_dqs_shift_with_max_passing_cases = 0;
-	u32 passing_cases = 0, dll_dqs_delay_X_sw_val = 0;
-	u32 dll_dqs_delay_X_start_window = 0, dll_dqs_delay_X_end_window = 0;
-	volatile u32 *ram_pointer;
-	u32 test[NUM_TRIES] = {
-		0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
-		0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
-		0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
-		0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
-		0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
-		0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
-		0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
-		0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
-		0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
-		0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
-		0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
-		0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
-		0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
-		0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
-		0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55,
-		0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55 };
-
-	ram_pointer = (volatile u32 *)(CFG_SDRAM_BASE);
-
-	for (wr_dqs_shift = 64; wr_dqs_shift < 96; wr_dqs_shift++) {
-		/*for (wr_dqs_shift=1; wr_dqs_shift<96; wr_dqs_shift++) {*/
-
-		/* -----------------------------------------------------------+
-		 * De-assert 'start' parameter.
-		 * ----------------------------------------------------------*/
-		mtdcr(ddrcfga, DDR0_02);
-		val = (mfdcr(ddrcfgd) & ~DDR0_02_START_MASK) | DDR0_02_START_OFF;
-		mtdcr(ddrcfgd, val);
-
-		/* -----------------------------------------------------------+
-		 * Set 'wr_dqs_shift'
-		 * ----------------------------------------------------------*/
-		mtdcr(ddrcfga, DDR0_09);
-		val = (mfdcr(ddrcfgd) & ~DDR0_09_WR_DQS_SHIFT_MASK)
-			| DDR0_09_WR_DQS_SHIFT_ENCODE(wr_dqs_shift);
-		mtdcr(ddrcfgd, val);
-
-		/* -----------------------------------------------------------+
-		 * Set 'dqs_out_shift' = wr_dqs_shift + 32
-		 * ----------------------------------------------------------*/
-		dqs_out_shift = wr_dqs_shift + 32;
-		mtdcr(ddrcfga, DDR0_22);
-		val = (mfdcr(ddrcfgd) & ~DDR0_22_DQS_OUT_SHIFT_MASK)
-			| DDR0_22_DQS_OUT_SHIFT_ENCODE(dqs_out_shift);
-		mtdcr(ddrcfgd, val);
-
-		passing_cases = 0;
-
-		for (dll_dqs_delay_X = 1; dll_dqs_delay_X < 64; dll_dqs_delay_X++) {
-			/*for (dll_dqs_delay_X=1; dll_dqs_delay_X<128; dll_dqs_delay_X++) {*/
-			/* -----------------------------------------------------------+
-			 * Set 'dll_dqs_delay_X'.
-			 * ----------------------------------------------------------*/
-			/* dll_dqs_delay_0 */
-			mtdcr(ddrcfga, DDR0_17);
-			val = (mfdcr(ddrcfgd) & ~DDR0_17_DLL_DQS_DELAY_0_MASK)
-				| DDR0_17_DLL_DQS_DELAY_0_ENCODE(dll_dqs_delay_X);
-			mtdcr(ddrcfgd, val);
-			/* dll_dqs_delay_1 to dll_dqs_delay_4 */
-			mtdcr(ddrcfga, DDR0_18);
-			val = (mfdcr(ddrcfgd) & ~DDR0_18_DLL_DQS_DELAY_X_MASK)
-				| DDR0_18_DLL_DQS_DELAY_4_ENCODE(dll_dqs_delay_X)
-				| DDR0_18_DLL_DQS_DELAY_3_ENCODE(dll_dqs_delay_X)
-				| DDR0_18_DLL_DQS_DELAY_2_ENCODE(dll_dqs_delay_X)
-				| DDR0_18_DLL_DQS_DELAY_1_ENCODE(dll_dqs_delay_X);
-			mtdcr(ddrcfgd, val);
-			/* dll_dqs_delay_5 to dll_dqs_delay_8 */
-			mtdcr(ddrcfga, DDR0_19);
-			val = (mfdcr(ddrcfgd) & ~DDR0_19_DLL_DQS_DELAY_X_MASK)
-				| DDR0_19_DLL_DQS_DELAY_8_ENCODE(dll_dqs_delay_X)
-				| DDR0_19_DLL_DQS_DELAY_7_ENCODE(dll_dqs_delay_X)
-				| DDR0_19_DLL_DQS_DELAY_6_ENCODE(dll_dqs_delay_X)
-				| DDR0_19_DLL_DQS_DELAY_5_ENCODE(dll_dqs_delay_X);
-			mtdcr(ddrcfgd, val);
-
-			ppcMsync();
-			ppcMbar();
-
-			/* -----------------------------------------------------------+
-			 * Assert 'start' parameter.
-			 * ----------------------------------------------------------*/
-			mtdcr(ddrcfga, DDR0_02);
-			val = (mfdcr(ddrcfgd) & ~DDR0_02_START_MASK) | DDR0_02_START_ON;
-			mtdcr(ddrcfgd, val);
-
-			ppcMsync();
-			ppcMbar();
-
-			/* -----------------------------------------------------------+
-			 * Wait for the DCC master delay line to finish calibration
-			 * ----------------------------------------------------------*/
-			if (wait_for_dlllock() != 0) {
-				printf("dlllock did not occur !!!\n");
-				printf("denali_core_search_data_eye!!!\n");
-				printf("wr_dqs_shift = %d - dll_dqs_delay_X = %d\n",
-				       wr_dqs_shift, dll_dqs_delay_X);
-				hang();
-			}
-			ppcMsync();
-			ppcMbar();
-
-			if (wait_for_dram_init_complete() != 0) {
-				printf("dram init complete did not occur !!!\n");
-				printf("denali_core_search_data_eye!!!\n");
-				printf("wr_dqs_shift = %d - dll_dqs_delay_X = %d\n",
-				       wr_dqs_shift, dll_dqs_delay_X);
-				hang();
-			}
-			udelay(100);  /* wait 100us to ensure init is really completed !!! */
-
-			/* write values */
-			for (j=0; j<NUM_TRIES; j++) {
-				ram_pointer[j] = test[j];
-
-				/* clear any cache at ram location */
-				__asm__("dcbf 0,%0": :"r" (&ram_pointer[j]));
-			}
-
-			/* read values back */
-			for (j=0; j<NUM_TRIES; j++) {
-				for (k=0; k<NUM_READS; k++) {
-					/* clear any cache at ram location */
-					__asm__("dcbf 0,%0": :"r" (&ram_pointer[j]));
-
-					if (ram_pointer[j] != test[j])
-						break;
-				}
-
-				/* read error */
-				if (k != NUM_READS)
-					break;
-			}
-
-			/* See if the dll_dqs_delay_X value passed.*/
-			if (j < NUM_TRIES) {
-				/* Failed */
-				passing_cases = 0;
-				/* break; */
-			} else {
-				/* Passed */
-				if (passing_cases == 0)
-					dll_dqs_delay_X_sw_val = dll_dqs_delay_X;
-				passing_cases++;
-				if (passing_cases >= max_passing_cases) {
-					max_passing_cases = passing_cases;
-					wr_dqs_shift_with_max_passing_cases = wr_dqs_shift;
-					dll_dqs_delay_X_start_window = dll_dqs_delay_X_sw_val;
-					dll_dqs_delay_X_end_window = dll_dqs_delay_X;
-				}
-			}
-
-			/* -----------------------------------------------------------+
-			 * De-assert 'start' parameter.
-			 * ----------------------------------------------------------*/
-			mtdcr(ddrcfga, DDR0_02);
-			val = (mfdcr(ddrcfgd) & ~DDR0_02_START_MASK) | DDR0_02_START_OFF;
-			mtdcr(ddrcfgd, val);
-
-		} /* for (dll_dqs_delay_X=0; dll_dqs_delay_X<128; dll_dqs_delay_X++) */
-
-	} /* for (wr_dqs_shift=0; wr_dqs_shift<96; wr_dqs_shift++) */
-
-	/* -----------------------------------------------------------+
-	 * Largest passing window is now detected.
-	 * ----------------------------------------------------------*/
-
-	/* Compute dll_dqs_delay_X value */
-	dll_dqs_delay_X = (dll_dqs_delay_X_end_window + dll_dqs_delay_X_start_window) / 2;
-	wr_dqs_shift = wr_dqs_shift_with_max_passing_cases;
-
-	debug("DQS calibration - Window detected:\n");
-	debug("max_passing_cases = %d\n", max_passing_cases);
-	debug("wr_dqs_shift      = %d\n", wr_dqs_shift);
-	debug("dll_dqs_delay_X   = %d\n", dll_dqs_delay_X);
-	debug("dll_dqs_delay_X window = %d - %d\n",
-	       dll_dqs_delay_X_start_window, dll_dqs_delay_X_end_window);
-
-	/* -----------------------------------------------------------+
-	 * De-assert 'start' parameter.
-	 * ----------------------------------------------------------*/
-	mtdcr(ddrcfga, DDR0_02);
-	val = (mfdcr(ddrcfgd) & ~DDR0_02_START_MASK) | DDR0_02_START_OFF;
-	mtdcr(ddrcfgd, val);
-
-	/* -----------------------------------------------------------+
-	 * Set 'wr_dqs_shift'
-	 * ----------------------------------------------------------*/
-	mtdcr(ddrcfga, DDR0_09);
-	val = (mfdcr(ddrcfgd) & ~DDR0_09_WR_DQS_SHIFT_MASK)
-		| DDR0_09_WR_DQS_SHIFT_ENCODE(wr_dqs_shift);
-	mtdcr(ddrcfgd, val);
-	debug("DDR0_09=0x%08lx\n", val);
-
-	/* -----------------------------------------------------------+
-	 * Set 'dqs_out_shift' = wr_dqs_shift + 32
-	 * ----------------------------------------------------------*/
-	dqs_out_shift = wr_dqs_shift + 32;
-	mtdcr(ddrcfga, DDR0_22);
-	val = (mfdcr(ddrcfgd) & ~DDR0_22_DQS_OUT_SHIFT_MASK)
-		| DDR0_22_DQS_OUT_SHIFT_ENCODE(dqs_out_shift);
-	mtdcr(ddrcfgd, val);
-	debug("DDR0_22=0x%08lx\n", val);
-
-	/* -----------------------------------------------------------+
-	 * Set 'dll_dqs_delay_X'.
-	 * ----------------------------------------------------------*/
-	/* dll_dqs_delay_0 */
-	mtdcr(ddrcfga, DDR0_17);
-	val = (mfdcr(ddrcfgd) & ~DDR0_17_DLL_DQS_DELAY_0_MASK)
-		| DDR0_17_DLL_DQS_DELAY_0_ENCODE(dll_dqs_delay_X);
-	mtdcr(ddrcfgd, val);
-	debug("DDR0_17=0x%08lx\n", val);
-
-	/* dll_dqs_delay_1 to dll_dqs_delay_4 */
-	mtdcr(ddrcfga, DDR0_18);
-	val = (mfdcr(ddrcfgd) & ~DDR0_18_DLL_DQS_DELAY_X_MASK)
-		| DDR0_18_DLL_DQS_DELAY_4_ENCODE(dll_dqs_delay_X)
-		| DDR0_18_DLL_DQS_DELAY_3_ENCODE(dll_dqs_delay_X)
-		| DDR0_18_DLL_DQS_DELAY_2_ENCODE(dll_dqs_delay_X)
-		| DDR0_18_DLL_DQS_DELAY_1_ENCODE(dll_dqs_delay_X);
-	mtdcr(ddrcfgd, val);
-	debug("DDR0_18=0x%08lx\n", val);
-
-	/* dll_dqs_delay_5 to dll_dqs_delay_8 */
-	mtdcr(ddrcfga, DDR0_19);
-	val = (mfdcr(ddrcfgd) & ~DDR0_19_DLL_DQS_DELAY_X_MASK)
-		| DDR0_19_DLL_DQS_DELAY_8_ENCODE(dll_dqs_delay_X)
-		| DDR0_19_DLL_DQS_DELAY_7_ENCODE(dll_dqs_delay_X)
-		| DDR0_19_DLL_DQS_DELAY_6_ENCODE(dll_dqs_delay_X)
-		| DDR0_19_DLL_DQS_DELAY_5_ENCODE(dll_dqs_delay_X);
-	mtdcr(ddrcfgd, val);
-	debug("DDR0_19=0x%08lx\n", val);
-
-	/* -----------------------------------------------------------+
-	 * Assert 'start' parameter.
-	 * ----------------------------------------------------------*/
-	mtdcr(ddrcfga, DDR0_02);
-	val = (mfdcr(ddrcfgd) & ~DDR0_02_START_MASK) | DDR0_02_START_ON;
-	mtdcr(ddrcfgd, val);
-
-	ppcMsync();
-	ppcMbar();
-
-	/* -----------------------------------------------------------+
-	 * Wait for the DCC master delay line to finish calibration
-	 * ----------------------------------------------------------*/
-	if (wait_for_dlllock() != 0) {
-		printf("dlllock did not occur !!!\n");
-		hang();
-	}
-	ppcMsync();
-	ppcMbar();
-
-	if (wait_for_dram_init_complete() != 0) {
-		printf("dram init complete did not occur !!!\n");
-		hang();
-	}
-	udelay(100);  /* wait 100us to ensure init is really completed !!! */
-}
-#endif /* CONFIG_DDR_DATA_EYE */
 
 #if defined(CONFIG_NAND_SPL)
 /* Using cpu/ppc4xx/speed.c to calculate the bus frequency is too big
@@ -428,14 +94,14 @@ long int initdram (int board_type)
 	mtsdram(DDR0_44, 0x00000003);
 	mtsdram(DDR0_02, 0x00000001);
 
-	wait_for_dlllock();
+	denali_wait_for_dlllock();
 #endif /* #ifndef CONFIG_NAND_U_BOOT */
 
 #ifdef CONFIG_DDR_DATA_EYE
 	/* -----------------------------------------------------------+
 	 * Perform data eye search if requested.
 	 * ----------------------------------------------------------*/
-	denali_core_search_data_eye(CFG_MBYTES_SDRAM << 20);
+	denali_core_search_data_eye();
 #endif
 
 	return (CFG_MBYTES_SDRAM << 20);

From 49db47b8ae6afff2b898be312948ff501357dc80 Mon Sep 17 00:00:00 2001
From: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
Date: Wed, 2 Jan 2008 16:48:42 +0100
Subject: [PATCH 039/108] ppc4xx: Remove sdram.h from PMC440 board

Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
---
 board/esd/pmc440/sdram.h | 505 ---------------------------------------
 1 file changed, 505 deletions(-)
 delete mode 100644 board/esd/pmc440/sdram.h

diff --git a/board/esd/pmc440/sdram.h b/board/esd/pmc440/sdram.h
deleted file mode 100644
index 7f847aa2a..000000000
--- a/board/esd/pmc440/sdram.h
+++ /dev/null
@@ -1,505 +0,0 @@
-/*
- * (C) Copyright 2006
- * Sylvie Gohl,             AMCC/IBM, gohl.sylvie@fr.ibm.com
- * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
- * Thierry Roman,           AMCC/IBM, thierry_roman@fr.ibm.com
- * Alain Saurel,            AMCC/IBM, alain.saurel@fr.ibm.com
- * Robert Snyder,           AMCC/IBM, rob.snyder@fr.ibm.com
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef _SPD_SDRAM_DENALI_H_
-#define _SPD_SDRAM_DENALI_H_
-
-#define ppcMsync	sync
-#define ppcMbar		eieio
-
-/* General definitions */
-#define MAX_SPD_BYTE        128         /* highest SPD byte # to read */
-#define DENALI_REG_NUMBER   45          /* 45 Regs in PPC440EPx Denali Core */
-#define SUPPORTED_DIMMS_NB  7           /* Number of supported DIMM modules types */
-#define SDRAM_NONE          0           /* No DIMM detected in Slot */
-#define MAXRANKS            2           /* 2 ranks maximum */
-
-/* Supported PLB Frequencies */
-#define PLB_FREQ_133MHZ     133333333
-#define PLB_FREQ_152MHZ     152000000
-#define PLB_FREQ_160MHZ     160000000
-#define PLB_FREQ_166MHZ     166666666
-
-/* Denali Core Registers */
-#define SDRAM_DCR_BASE 0x10
-
-#define DDR_DCR_BASE 0x10
-#define ddrcfga  (DDR_DCR_BASE+0x0)   /* DDR configuration address reg */
-#define ddrcfgd  (DDR_DCR_BASE+0x1)   /* DDR configuration data reg    */
-
-/*-----------------------------------------------------------------------------+
-  | Values for ddrcfga register - indirect addressing of these regs
-  +-----------------------------------------------------------------------------*/
-
-#define DDR0_00                         0x00
-#define DDR0_00_INT_ACK_MASK              0x7F000000 /* Write only */
-#define DDR0_00_INT_ACK_ALL               0x7F000000
-#define DDR0_00_INT_ACK_ENCODE(n)           ((((unsigned long)(n))&0x7F)<<24)
-#define DDR0_00_INT_ACK_DECODE(n)           ((((unsigned long)(n))>>24)&0x7F)
-/* Status */
-#define DDR0_00_INT_STATUS_MASK           0x00FF0000 /* Read only */
-/* Bit0. A single access outside the defined PHYSICAL memory space detected. */
-#define DDR0_00_INT_STATUS_BIT0           0x00010000
-/* Bit1. Multiple accesses outside the defined PHYSICAL memory space detected. */
-#define DDR0_00_INT_STATUS_BIT1           0x00020000
-/* Bit2. Single correctable ECC event detected */
-#define DDR0_00_INT_STATUS_BIT2           0x00040000
-/* Bit3. Multiple correctable ECC events detected. */
-#define DDR0_00_INT_STATUS_BIT3           0x00080000
-/* Bit4. Single uncorrectable ECC event detected. */
-#define DDR0_00_INT_STATUS_BIT4           0x00100000
-/* Bit5. Multiple uncorrectable ECC events detected. */
-#define DDR0_00_INT_STATUS_BIT5           0x00200000
-/* Bit6. DRAM initialization complete. */
-#define DDR0_00_INT_STATUS_BIT6           0x00400000
-/* Bit7. Logical OR of all lower bits. */
-#define DDR0_00_INT_STATUS_BIT7           0x00800000
-
-#define DDR0_00_INT_STATUS_ENCODE(n)        ((((unsigned long)(n))&0xFF)<<16)
-#define DDR0_00_INT_STATUS_DECODE(n)        ((((unsigned long)(n))>>16)&0xFF)
-#define DDR0_00_DLL_INCREMENT_MASK        0x00007F00
-#define DDR0_00_DLL_INCREMENT_ENCODE(n)     ((((unsigned long)(n))&0x7F)<<8)
-#define DDR0_00_DLL_INCREMENT_DECODE(n)     ((((unsigned long)(n))>>8)&0x7F)
-#define DDR0_00_DLL_START_POINT_MASK      0x0000007F
-#define DDR0_00_DLL_START_POINT_ENCODE(n)   ((((unsigned long)(n))&0x7F)<<0)
-#define DDR0_00_DLL_START_POINT_DECODE(n)   ((((unsigned long)(n))>>0)&0x7F)
-
-
-#define DDR0_01                         0x01
-#define DDR0_01_PLB0_DB_CS_LOWER_MASK     0x1F000000
-#define DDR0_01_PLB0_DB_CS_LOWER_ENCODE(n)  ((((unsigned long)(n))&0x1F)<<24)
-#define DDR0_01_PLB0_DB_CS_LOWER_DECODE(n)  ((((unsigned long)(n))>>24)&0x1F)
-#define DDR0_01_PLB0_DB_CS_UPPER_MASK     0x001F0000
-#define DDR0_01_PLB0_DB_CS_UPPER_ENCODE(n)  ((((unsigned long)(n))&0x1F)<<16)
-#define DDR0_01_PLB0_DB_CS_UPPER_DECODE(n)  ((((unsigned long)(n))>>16)&0x1F)
-#define DDR0_01_OUT_OF_RANGE_TYPE_MASK    0x00000700 /* Read only */
-#define DDR0_01_OUT_OF_RANGE_TYPE_ENCODE(n)               ((((unsigned long)(n))&0x7)<<8)
-#define DDR0_01_OUT_OF_RANGE_TYPE_DECODE(n)               ((((unsigned long)(n))>>8)&0x7)
-#define DDR0_01_INT_MASK_MASK             0x000000FF
-#define DDR0_01_INT_MASK_ENCODE(n)          ((((unsigned long)(n))&0xFF)<<0)
-#define DDR0_01_INT_MASK_DECODE(n)          ((((unsigned long)(n))>>0)&0xFF)
-#define DDR0_01_INT_MASK_ALL_ON           0x000000FF
-#define DDR0_01_INT_MASK_ALL_OFF          0x00000000
-
-#define DDR0_02                         0x02
-#define DDR0_02_MAX_CS_REG_MASK           0x02000000 /* Read only */
-#define DDR0_02_MAX_CS_REG_ENCODE(n)        ((((unsigned long)(n))&0x2)<<24)
-#define DDR0_02_MAX_CS_REG_DECODE(n)        ((((unsigned long)(n))>>24)&0x2)
-#define DDR0_02_MAX_COL_REG_MASK          0x000F0000 /* Read only */
-#define DDR0_02_MAX_COL_REG_ENCODE(n)       ((((unsigned long)(n))&0xF)<<16)
-#define DDR0_02_MAX_COL_REG_DECODE(n)       ((((unsigned long)(n))>>16)&0xF)
-#define DDR0_02_MAX_ROW_REG_MASK          0x00000F00 /* Read only */
-#define DDR0_02_MAX_ROW_REG_ENCODE(n)       ((((unsigned long)(n))&0xF)<<8)
-#define DDR0_02_MAX_ROW_REG_DECODE(n)       ((((unsigned long)(n))>>8)&0xF)
-#define DDR0_02_START_MASK                0x00000001
-#define DDR0_02_START_ENCODE(n)             ((((unsigned long)(n))&0x1)<<0)
-#define DDR0_02_START_DECODE(n)             ((((unsigned long)(n))>>0)&0x1)
-#define DDR0_02_START_OFF                 0x00000000
-#define DDR0_02_START_ON                  0x00000001
-
-#define DDR0_03                         0x03
-#define DDR0_03_BSTLEN_MASK               0x07000000
-#define DDR0_03_BSTLEN_ENCODE(n)            ((((unsigned long)(n))&0x7)<<24)
-#define DDR0_03_BSTLEN_DECODE(n)            ((((unsigned long)(n))>>24)&0x7)
-#define DDR0_03_CASLAT_MASK               0x00070000
-#define DDR0_03_CASLAT_ENCODE(n)            ((((unsigned long)(n))&0x7)<<16)
-#define DDR0_03_CASLAT_DECODE(n)            ((((unsigned long)(n))>>16)&0x7)
-#define DDR0_03_CASLAT_LIN_MASK           0x00000F00
-#define DDR0_03_CASLAT_LIN_ENCODE(n)        ((((unsigned long)(n))&0xF)<<8)
-#define DDR0_03_CASLAT_LIN_DECODE(n)        ((((unsigned long)(n))>>8)&0xF)
-#define DDR0_03_INITAREF_MASK             0x0000000F
-#define DDR0_03_INITAREF_ENCODE(n)          ((((unsigned long)(n))&0xF)<<0)
-#define DDR0_03_INITAREF_DECODE(n)          ((((unsigned long)(n))>>0)&0xF)
-
-#define DDR0_04                         0x04
-#define DDR0_04_TRC_MASK                  0x1F000000
-#define DDR0_04_TRC_ENCODE(n)               ((((unsigned long)(n))&0x1F)<<24)
-#define DDR0_04_TRC_DECODE(n)               ((((unsigned long)(n))>>24)&0x1F)
-#define DDR0_04_TRRD_MASK                 0x00070000
-#define DDR0_04_TRRD_ENCODE(n)              ((((unsigned long)(n))&0x7)<<16)
-#define DDR0_04_TRRD_DECODE(n)              ((((unsigned long)(n))>>16)&0x7)
-#define DDR0_04_TRTP_MASK                 0x00000700
-#define DDR0_04_TRTP_ENCODE(n)              ((((unsigned long)(n))&0x7)<<8)
-#define DDR0_04_TRTP_DECODE(n)              ((((unsigned long)(n))>>8)&0x7)
-
-#define DDR0_05                         0x05
-#define DDR0_05_TMRD_MASK                 0x1F000000
-#define DDR0_05_TMRD_ENCODE(n)              ((((unsigned long)(n))&0x1F)<<24)
-#define DDR0_05_TMRD_DECODE(n)              ((((unsigned long)(n))>>24)&0x1F)
-#define DDR0_05_TEMRS_MASK                0x00070000
-#define DDR0_05_TEMRS_ENCODE(n)             ((((unsigned long)(n))&0x7)<<16)
-#define DDR0_05_TEMRS_DECODE(n)             ((((unsigned long)(n))>>16)&0x7)
-#define DDR0_05_TRP_MASK                  0x00000F00
-#define DDR0_05_TRP_ENCODE(n)               ((((unsigned long)(n))&0xF)<<8)
-#define DDR0_05_TRP_DECODE(n)               ((((unsigned long)(n))>>8)&0xF)
-#define DDR0_05_TRAS_MIN_MASK             0x000000FF
-#define DDR0_05_TRAS_MIN_ENCODE(n)          ((((unsigned long)(n))&0xFF)<<0)
-#define DDR0_05_TRAS_MIN_DECODE(n)          ((((unsigned long)(n))>>0)&0xFF)
-
-#define DDR0_06                         0x06
-#define DDR0_06_WRITEINTERP_MASK          0x01000000
-#define DDR0_06_WRITEINTERP_ENCODE(n)       ((((unsigned long)(n))&0x1)<<24)
-#define DDR0_06_WRITEINTERP_DECODE(n)       ((((unsigned long)(n))>>24)&0x1)
-#define DDR0_06_TWTR_MASK                 0x00070000
-#define DDR0_06_TWTR_ENCODE(n)              ((((unsigned long)(n))&0x7)<<16)
-#define DDR0_06_TWTR_DECODE(n)              ((((unsigned long)(n))>>16)&0x7)
-#define DDR0_06_TDLL_MASK                 0x0000FF00
-#define DDR0_06_TDLL_ENCODE(n)              ((((unsigned long)(n))&0xFF)<<8)
-#define DDR0_06_TDLL_DECODE(n)              ((((unsigned long)(n))>>8)&0xFF)
-#define DDR0_06_TRFC_MASK                 0x0000007F
-#define DDR0_06_TRFC_ENCODE(n)              ((((unsigned long)(n))&0x7F)<<0)
-#define DDR0_06_TRFC_DECODE(n)              ((((unsigned long)(n))>>0)&0x7F)
-
-#define DDR0_07                         0x07
-#define DDR0_07_NO_CMD_INIT_MASK          0x01000000
-#define DDR0_07_NO_CMD_INIT_ENCODE(n)       ((((unsigned long)(n))&0x1)<<24)
-#define DDR0_07_NO_CMD_INIT_DECODE(n)       ((((unsigned long)(n))>>24)&0x1)
-#define DDR0_07_TFAW_MASK                 0x001F0000
-#define DDR0_07_TFAW_ENCODE(n)              ((((unsigned long)(n))&0x1F)<<16)
-#define DDR0_07_TFAW_DECODE(n)              ((((unsigned long)(n))>>16)&0x1F)
-#define DDR0_07_AUTO_REFRESH_MODE_MASK    0x00000100
-#define DDR0_07_AUTO_REFRESH_MODE_ENCODE(n) ((((unsigned long)(n))&0x1)<<8)
-#define DDR0_07_AUTO_REFRESH_MODE_DECODE(n) ((((unsigned long)(n))>>8)&0x1)
-#define DDR0_07_AREFRESH_MASK             0x00000001
-#define DDR0_07_AREFRESH_ENCODE(n)          ((((unsigned long)(n))&0x1)<<0)
-#define DDR0_07_AREFRESH_DECODE(n)          ((((unsigned long)(n))>>0)&0x1)
-
-#define DDR0_08                         0x08
-#define DDR0_08_WRLAT_MASK                0x07000000
-#define DDR0_08_WRLAT_ENCODE(n)             ((((unsigned long)(n))&0x7)<<24)
-#define DDR0_08_WRLAT_DECODE(n)             ((((unsigned long)(n))>>24)&0x7)
-#define DDR0_08_TCPD_MASK                 0x00FF0000
-#define DDR0_08_TCPD_ENCODE(n)              ((((unsigned long)(n))&0xFF)<<16)
-#define DDR0_08_TCPD_DECODE(n)              ((((unsigned long)(n))>>16)&0xFF)
-#define DDR0_08_DQS_N_EN_MASK             0x00000100
-#define DDR0_08_DQS_N_EN_ENCODE(n)          ((((unsigned long)(n))&0x1)<<8)
-#define DDR0_08_DQS_N_EN_DECODE(n)          ((((unsigned long)(n))>>8)&0x1)
-#define DDR0_08_DDRII_SDRAM_MODE_MASK     0x00000001
-#define DDR0_08_DDRII_ENCODE(n)             ((((unsigned long)(n))&0x1)<<0)
-#define DDR0_08_DDRII_DECODE(n)             ((((unsigned long)(n))>>0)&0x1)
-
-#define DDR0_09                         0x09
-#define DDR0_09_OCD_ADJUST_PDN_CS_0_MASK  0x1F000000
-#define DDR0_09_OCD_ADJUST_PDN_CS_0_ENCODE(n) ((((unsigned long)(n))&0x1F)<<24)
-#define DDR0_09_OCD_ADJUST_PDN_CS_0_DECODE(n) ((((unsigned long)(n))>>24)&0x1F)
-#define DDR0_09_RTT_0_MASK                0x00030000
-#define DDR0_09_RTT_0_ENCODE(n)             ((((unsigned long)(n))&0x3)<<16)
-#define DDR0_09_RTT_0_DECODE(n)             ((((unsigned long)(n))>>16)&0x3)
-#define DDR0_09_WR_DQS_SHIFT_BYPASS_MASK  0x00007F00
-#define DDR0_09_WR_DQS_SHIFT_BYPASS_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8)
-#define DDR0_09_WR_DQS_SHIFT_BYPASS_DECODE(n) ((((unsigned long)(n))>>8)&0x7F)
-#define DDR0_09_WR_DQS_SHIFT_MASK         0x0000007F
-#define DDR0_09_WR_DQS_SHIFT_ENCODE(n)      ((((unsigned long)(n))&0x7F)<<0)
-#define DDR0_09_WR_DQS_SHIFT_DECODE(n)      ((((unsigned long)(n))>>0)&0x7F)
-
-#define DDR0_10                         0x0A
-#define DDR0_10_WRITE_MODEREG_MASK        0x00010000 /* Write only */
-#define DDR0_10_WRITE_MODEREG_ENCODE(n)     ((((unsigned long)(n))&0x1)<<16)
-#define DDR0_10_WRITE_MODEREG_DECODE(n)     ((((unsigned long)(n))>>16)&0x1)
-#define DDR0_10_CS_MAP_MASK               0x00000300
-#define DDR0_10_CS_MAP_NO_MEM             0x00000000
-#define DDR0_10_CS_MAP_RANK0_INSTALLED    0x00000100
-#define DDR0_10_CS_MAP_RANK1_INSTALLED    0x00000200
-#define DDR0_10_CS_MAP_ENCODE(n)            ((((unsigned long)(n))&0x3)<<8)
-#define DDR0_10_CS_MAP_DECODE(n)            ((((unsigned long)(n))>>8)&0x3)
-#define DDR0_10_OCD_ADJUST_PUP_CS_0_MASK  0x0000001F
-#define DDR0_10_OCD_ADJUST_PUP_CS_0_ENCODE(n) ((((unsigned long)(n))&0x1F)<<0)
-#define DDR0_10_OCD_ADJUST_PUP_CS_0_DECODE(n) ((((unsigned long)(n))>>0)&0x1F)
-
-#define DDR0_11                         0x0B
-#define DDR0_11_SREFRESH_MASK             0x01000000
-#define DDR0_11_SREFRESH_ENCODE(n)          ((((unsigned long)(n))&0x1)<<24)
-#define DDR0_11_SREFRESH_DECODE(n)          ((((unsigned long)(n))>>24)&0x1F)
-#define DDR0_11_TXSNR_MASK                0x00FF0000
-#define DDR0_11_TXSNR_ENCODE(n)             ((((unsigned long)(n))&0xFF)<<16)
-#define DDR0_11_TXSNR_DECODE(n)             ((((unsigned long)(n))>>16)&0xFF)
-#define DDR0_11_TXSR_MASK                 0x0000FF00
-#define DDR0_11_TXSR_ENCODE(n)              ((((unsigned long)(n))&0xFF)<<8)
-#define DDR0_11_TXSR_DECODE(n)              ((((unsigned long)(n))>>8)&0xFF)
-
-#define DDR0_12                         0x0C
-#define DDR0_12_TCKE_MASK                 0x0000007
-#define DDR0_12_TCKE_ENCODE(n)              ((((unsigned long)(n))&0x7)<<0)
-#define DDR0_12_TCKE_DECODE(n)              ((((unsigned long)(n))>>0)&0x7)
-
-#define DDR0_13                         0x0D
-
-#define DDR0_14                         0x0E
-#define DDR0_14_DLL_BYPASS_MODE_MASK      0x01000000
-#define DDR0_14_DLL_BYPASS_MODE_ENCODE(n)   ((((unsigned long)(n))&0x1)<<24)
-#define DDR0_14_DLL_BYPASS_MODE_DECODE(n)   ((((unsigned long)(n))>>24)&0x1)
-#define DDR0_14_REDUC_MASK                0x00010000
-#define DDR0_14_REDUC_64BITS              0x00000000
-#define DDR0_14_REDUC_32BITS              0x00010000
-#define DDR0_14_REDUC_ENCODE(n)             ((((unsigned long)(n))&0x1)<<16)
-#define DDR0_14_REDUC_DECODE(n)             ((((unsigned long)(n))>>16)&0x1)
-#define DDR0_14_REG_DIMM_ENABLE_MASK      0x00000100
-#define DDR0_14_REG_DIMM_ENABLE_ENCODE(n)   ((((unsigned long)(n))&0x1)<<8)
-#define DDR0_14_REG_DIMM_ENABLE_DECODE(n)   ((((unsigned long)(n))>>8)&0x1)
-
-#define DDR0_15                         0x0F
-
-#define DDR0_16                         0x10
-
-#define DDR0_17                         0x11
-#define DDR0_17_DLL_DQS_DELAY_0_MASK      0x7F000000
-#define DDR0_17_DLL_DQS_DELAY_0_ENCODE(n)   ((((unsigned long)(n))&0x7F)<<24)
-#define DDR0_17_DLL_DQS_DELAY_0_DECODE(n)   ((((unsigned long)(n))>>24)&0x7F)
-#define DDR0_17_DLLLOCKREG_MASK           0x00010000 /* Read only */
-#define DDR0_17_DLLLOCKREG_LOCKED         0x00010000
-#define DDR0_17_DLLLOCKREG_UNLOCKED       0x00000000
-#define DDR0_17_DLLLOCKREG_ENCODE(n)        ((((unsigned long)(n))&0x1)<<16)
-#define DDR0_17_DLLLOCKREG_DECODE(n)        ((((unsigned long)(n))>>16)&0x1)
-#define DDR0_17_DLL_LOCK_MASK             0x00007F00 /* Read only */
-#define DDR0_17_DLL_LOCK_ENCODE(n)          ((((unsigned long)(n))&0x7F)<<8)
-#define DDR0_17_DLL_LOCK_DECODE(n)          ((((unsigned long)(n))>>8)&0x7F)
-
-#define DDR0_18                         0x12
-#define DDR0_18_DLL_DQS_DELAY_X_MASK      0x7F7F7F7F
-#define DDR0_18_DLL_DQS_DELAY_4_MASK      0x7F000000
-#define DDR0_18_DLL_DQS_DELAY_4_ENCODE(n)   ((((unsigned long)(n))&0x7F)<<24)
-#define DDR0_18_DLL_DQS_DELAY_4_DECODE(n)   ((((unsigned long)(n))>>24)&0x7F)
-#define DDR0_18_DLL_DQS_DELAY_3_MASK      0x007F0000
-#define DDR0_18_DLL_DQS_DELAY_3_ENCODE(n)   ((((unsigned long)(n))&0x7F)<<16)
-#define DDR0_18_DLL_DQS_DELAY_3_DECODE(n)   ((((unsigned long)(n))>>16)&0x7F)
-#define DDR0_18_DLL_DQS_DELAY_2_MASK      0x00007F00
-#define DDR0_18_DLL_DQS_DELAY_2_ENCODE(n)   ((((unsigned long)(n))&0x7F)<<8)
-#define DDR0_18_DLL_DQS_DELAY_2_DECODE(n)   ((((unsigned long)(n))>>8)&0x7F)
-#define DDR0_18_DLL_DQS_DELAY_1_MASK      0x0000007F
-#define DDR0_18_DLL_DQS_DELAY_1_ENCODE(n)   ((((unsigned long)(n))&0x7F)<<0)
-#define DDR0_18_DLL_DQS_DELAY_1_DECODE(n)   ((((unsigned long)(n))>>0)&0x7F)
-
-#define DDR0_19                         0x13
-#define DDR0_19_DLL_DQS_DELAY_X_MASK      0x7F7F7F7F
-#define DDR0_19_DLL_DQS_DELAY_8_MASK      0x7F000000
-#define DDR0_19_DLL_DQS_DELAY_8_ENCODE(n)   ((((unsigned long)(n))&0x7F)<<24)
-#define DDR0_19_DLL_DQS_DELAY_8_DECODE(n)   ((((unsigned long)(n))>>24)&0x7F)
-#define DDR0_19_DLL_DQS_DELAY_7_MASK      0x007F0000
-#define DDR0_19_DLL_DQS_DELAY_7_ENCODE(n)   ((((unsigned long)(n))&0x7F)<<16)
-#define DDR0_19_DLL_DQS_DELAY_7_DECODE(n)   ((((unsigned long)(n))>>16)&0x7F)
-#define DDR0_19_DLL_DQS_DELAY_6_MASK      0x00007F00
-#define DDR0_19_DLL_DQS_DELAY_6_ENCODE(n)   ((((unsigned long)(n))&0x7F)<<8)
-#define DDR0_19_DLL_DQS_DELAY_6_DECODE(n)   ((((unsigned long)(n))>>8)&0x7F)
-#define DDR0_19_DLL_DQS_DELAY_5_MASK      0x0000007F
-#define DDR0_19_DLL_DQS_DELAY_5_ENCODE(n)   ((((unsigned long)(n))&0x7F)<<0)
-#define DDR0_19_DLL_DQS_DELAY_5_DECODE(n)   ((((unsigned long)(n))>>0)&0x7F)
-
-#define DDR0_20                         0x14
-#define DDR0_20_DLL_DQS_BYPASS_3_MASK      0x7F000000
-#define DDR0_20_DLL_DQS_BYPASS_3_ENCODE(n)   ((((unsigned long)(n))&0x7F)<<24)
-#define DDR0_20_DLL_DQS_BYPASS_3_DECODE(n)   ((((unsigned long)(n))>>24)&0x7F)
-#define DDR0_20_DLL_DQS_BYPASS_2_MASK      0x007F0000
-#define DDR0_20_DLL_DQS_BYPASS_2_ENCODE(n)   ((((unsigned long)(n))&0x7F)<<16)
-#define DDR0_20_DLL_DQS_BYPASS_2_DECODE(n)   ((((unsigned long)(n))>>16)&0x7F)
-#define DDR0_20_DLL_DQS_BYPASS_1_MASK      0x00007F00
-#define DDR0_20_DLL_DQS_BYPASS_1_ENCODE(n)   ((((unsigned long)(n))&0x7F)<<8)
-#define DDR0_20_DLL_DQS_BYPASS_1_DECODE(n)   ((((unsigned long)(n))>>8)&0x7F)
-#define DDR0_20_DLL_DQS_BYPASS_0_MASK      0x0000007F
-#define DDR0_20_DLL_DQS_BYPASS_0_ENCODE(n)   ((((unsigned long)(n))&0x7F)<<0)
-#define DDR0_20_DLL_DQS_BYPASS_0_DECODE(n)   ((((unsigned long)(n))>>0)&0x7F)
-
-#define DDR0_21                         0x15
-#define DDR0_21_DLL_DQS_BYPASS_7_MASK      0x7F000000
-#define DDR0_21_DLL_DQS_BYPASS_7_ENCODE(n)   ((((unsigned long)(n))&0x7F)<<24)
-#define DDR0_21_DLL_DQS_BYPASS_7_DECODE(n)   ((((unsigned long)(n))>>24)&0x7F)
-#define DDR0_21_DLL_DQS_BYPASS_6_MASK      0x007F0000
-#define DDR0_21_DLL_DQS_BYPASS_6_ENCODE(n)   ((((unsigned long)(n))&0x7F)<<16)
-#define DDR0_21_DLL_DQS_BYPASS_6_DECODE(n)   ((((unsigned long)(n))>>16)&0x7F)
-#define DDR0_21_DLL_DQS_BYPASS_5_MASK      0x00007F00
-#define DDR0_21_DLL_DQS_BYPASS_5_ENCODE(n)   ((((unsigned long)(n))&0x7F)<<8)
-#define DDR0_21_DLL_DQS_BYPASS_5_DECODE(n)   ((((unsigned long)(n))>>8)&0x7F)
-#define DDR0_21_DLL_DQS_BYPASS_4_MASK      0x0000007F
-#define DDR0_21_DLL_DQS_BYPASS_4_ENCODE(n)   ((((unsigned long)(n))&0x7F)<<0)
-#define DDR0_21_DLL_DQS_BYPASS_4_DECODE(n)   ((((unsigned long)(n))>>0)&0x7F)
-
-#define DDR0_22                         0x16
-/* ECC */
-#define DDR0_22_CTRL_RAW_MASK             0x03000000
-#define DDR0_22_CTRL_RAW_ECC_DISABLE      0x00000000 /* ECC not being used */
-#define DDR0_22_CTRL_RAW_ECC_CHECK_ONLY   0x01000000 /* ECC checking is on, but no attempts to correct*/
-#define DDR0_22_CTRL_RAW_NO_ECC_RAM       0x02000000 /* No ECC RAM storage available */
-#define DDR0_22_CTRL_RAW_ECC_ENABLE       0x03000000 /* ECC checking and correcting on */
-#define DDR0_22_CTRL_RAW_ENCODE(n)          ((((unsigned long)(n))&0x3)<<24)
-#define DDR0_22_CTRL_RAW_DECODE(n)          ((((unsigned long)(n))>>24)&0x3)
-
-#define DDR0_22_DQS_OUT_SHIFT_BYPASS_MASK 0x007F0000
-#define DDR0_22_DQS_OUT_SHIFT_BYPASS_ENCODE(n) ((((unsigned long)(n))&0x7F)<<16)
-#define DDR0_22_DQS_OUT_SHIFT_BYPASS_DECODE(n) ((((unsigned long)(n))>>16)&0x7F)
-#define DDR0_22_DQS_OUT_SHIFT_MASK        0x00007F00
-#define DDR0_22_DQS_OUT_SHIFT_ENCODE(n)     ((((unsigned long)(n))&0x7F)<<8)
-#define DDR0_22_DQS_OUT_SHIFT_DECODE(n)     ((((unsigned long)(n))>>8)&0x7F)
-#define DDR0_22_DLL_DQS_BYPASS_8_MASK     0x0000007F
-#define DDR0_22_DLL_DQS_BYPASS_8_ENCODE(n)  ((((unsigned long)(n))&0x7F)<<0)
-#define DDR0_22_DLL_DQS_BYPASS_8_DECODE(n)  ((((unsigned long)(n))>>0)&0x7F)
-
-
-#define DDR0_23                         0x17
-#define DDR0_23_ODT_RD_MAP_CS0_MASK       0x03000000
-#define DDR0_23_ODT_RD_MAP_CS0_ENCODE(n)   ((((unsigned long)(n))&0x3)<<24)
-#define DDR0_23_ODT_RD_MAP_CS0_DECODE(n)   ((((unsigned long)(n))>>24)&0x3)
-#define DDR0_23_ECC_C_SYND_MASK           0x00FF0000 /* Read only */
-#define DDR0_23_ECC_C_SYND_ENCODE(n)        ((((unsigned long)(n))&0xFF)<<16)
-#define DDR0_23_ECC_C_SYND_DECODE(n)        ((((unsigned long)(n))>>16)&0xFF)
-#define DDR0_23_ECC_U_SYND_MASK           0x0000FF00 /* Read only */
-#define DDR0_23_ECC_U_SYND_ENCODE(n)        ((((unsigned long)(n))&0xFF)<<8)
-#define DDR0_23_ECC_U_SYND_DECODE(n)        ((((unsigned long)(n))>>8)&0xFF)
-#define DDR0_23_FWC_MASK                  0x00000001 /* Write only */
-#define DDR0_23_FWC_ENCODE(n)               ((((unsigned long)(n))&0x1)<<0)
-#define DDR0_23_FWC_DECODE(n)               ((((unsigned long)(n))>>0)&0x1)
-
-#define DDR0_24                         0x18
-#define DDR0_24_RTT_PAD_TERMINATION_MASK  0x03000000
-#define DDR0_24_RTT_PAD_TERMINATION_ENCODE(n) ((((unsigned long)(n))&0x3)<<24)
-#define DDR0_24_RTT_PAD_TERMINATION_DECODE(n) ((((unsigned long)(n))>>24)&0x3)
-#define DDR0_24_ODT_WR_MAP_CS1_MASK       0x00030000
-#define DDR0_24_ODT_WR_MAP_CS1_ENCODE(n)    ((((unsigned long)(n))&0x3)<<16)
-#define DDR0_24_ODT_WR_MAP_CS1_DECODE(n)    ((((unsigned long)(n))>>16)&0x3)
-#define DDR0_24_ODT_RD_MAP_CS1_MASK       0x00000300
-#define DDR0_24_ODT_RD_MAP_CS1_ENCODE(n)    ((((unsigned long)(n))&0x3)<<8)
-#define DDR0_24_ODT_RD_MAP_CS1_DECODE(n)    ((((unsigned long)(n))>>8)&0x3)
-#define DDR0_24_ODT_WR_MAP_CS0_MASK       0x00000003
-#define DDR0_24_ODT_WR_MAP_CS0_ENCODE(n)    ((((unsigned long)(n))&0x3)<<0)
-#define DDR0_24_ODT_WR_MAP_CS0_DECODE(n)    ((((unsigned long)(n))>>0)&0x3)
-
-#define DDR0_25                         0x19
-#define DDR0_25_VERSION_MASK              0xFFFF0000 /* Read only */
-#define DDR0_25_VERSION_ENCODE(n)           ((((unsigned long)(n))&0xFFFF)<<16)
-#define DDR0_25_VERSION_DECODE(n)           ((((unsigned long)(n))>>16)&0xFFFF)
-#define DDR0_25_OUT_OF_RANGE_LENGTH_MASK  0x000003FF /* Read only */
-#define DDR0_25_OUT_OF_RANGE_LENGTH_ENCODE(n) ((((unsigned long)(n))&0x3FF)<<0)
-#define DDR0_25_OUT_OF_RANGE_LENGTH_DECODE(n) ((((unsigned long)(n))>>0)&0x3FF)
-
-#define DDR0_26                         0x1A
-#define DDR0_26_TRAS_MAX_MASK             0xFFFF0000
-#define DDR0_26_TRAS_MAX_ENCODE(n)          ((((unsigned long)(n))&0xFFFF)<<16)
-#define DDR0_26_TRAS_MAX_DECODE(n)          ((((unsigned long)(n))>>16)&0xFFFF)
-#define DDR0_26_TREF_MASK                 0x00003FFF
-#define DDR0_26_TREF_ENCODE(n)              ((((unsigned long)(n))&0x3FF)<<0)
-#define DDR0_26_TREF_DECODE(n)              ((((unsigned long)(n))>>0)&0x3FF)
-
-#define DDR0_27                         0x1B
-#define DDR0_27_EMRS_DATA_MASK            0x3FFF0000
-#define DDR0_27_EMRS_DATA_ENCODE(n)         ((((unsigned long)(n))&0x3FFF)<<16)
-#define DDR0_27_EMRS_DATA_DECODE(n)         ((((unsigned long)(n))>>16)&0x3FFF)
-#define DDR0_27_TINIT_MASK                0x0000FFFF
-#define DDR0_27_TINIT_ENCODE(n)             ((((unsigned long)(n))&0xFFFF)<<0)
-#define DDR0_27_TINIT_DECODE(n)             ((((unsigned long)(n))>>0)&0xFFFF)
-
-#define DDR0_28                         0x1C
-#define DDR0_28_EMRS3_DATA_MASK           0x3FFF0000
-#define DDR0_28_EMRS3_DATA_ENCODE(n)        ((((unsigned long)(n))&0x3FFF)<<16)
-#define DDR0_28_EMRS3_DATA_DECODE(n)        ((((unsigned long)(n))>>16)&0x3FFF)
-#define DDR0_28_EMRS2_DATA_MASK           0x00003FFF
-#define DDR0_28_EMRS2_DATA_ENCODE(n)        ((((unsigned long)(n))&0x3FFF)<<0)
-#define DDR0_28_EMRS2_DATA_DECODE(n)        ((((unsigned long)(n))>>0)&0x3FFF)
-
-#define DDR0_29                         0x1D
-
-#define DDR0_30                         0x1E
-
-#define DDR0_31                         0x1F
-#define DDR0_31_XOR_CHECK_BITS_MASK       0x0000FFFF
-#define DDR0_31_XOR_CHECK_BITS_ENCODE(n)    ((((unsigned long)(n))&0xFFFF)<<0)
-#define DDR0_31_XOR_CHECK_BITS_DECODE(n)    ((((unsigned long)(n))>>0)&0xFFFF)
-
-#define DDR0_32                         0x20
-#define DDR0_32_OUT_OF_RANGE_ADDR_MASK    0xFFFFFFFF /* Read only */
-#define DDR0_32_OUT_OF_RANGE_ADDR_ENCODE(n) ((((unsigned long)(n))&0xFFFFFFFF)<<0)
-#define DDR0_32_OUT_OF_RANGE_ADDR_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFFFFFF)
-
-#define DDR0_33                         0x21
-#define DDR0_33_OUT_OF_RANGE_ADDR_MASK    0x00000001 /* Read only */
-#define DDR0_33_OUT_OF_RANGE_ADDR_ENCODE(n) ((((unsigned long)(n))&0x1)<<0)
-#define DDR0_33_OUT_OF_RANGE_ADDR_DECODE(n)               ((((unsigned long)(n))>>0)&0x1)
-
-#define DDR0_34                         0x22
-#define DDR0_34_ECC_U_ADDR_MASK           0xFFFFFFFF /* Read only */
-#define DDR0_34_ECC_U_ADDR_ENCODE(n)        ((((unsigned long)(n))&0xFFFFFFFF)<<0)
-#define DDR0_34_ECC_U_ADDR_DECODE(n)        ((((unsigned long)(n))>>0)&0xFFFFFFFF)
-
-#define DDR0_35                         0x23
-#define DDR0_35_ECC_U_ADDR_MASK           0x00000001 /* Read only */
-#define DDR0_35_ECC_U_ADDR_ENCODE(n)        ((((unsigned long)(n))&0x1)<<0)
-#define DDR0_35_ECC_U_ADDR_DECODE(n)        ((((unsigned long)(n))>>0)&0x1)
-
-#define DDR0_36                         0x24
-#define DDR0_36_ECC_U_DATA_MASK           0xFFFFFFFF /* Read only */
-#define DDR0_36_ECC_U_DATA_ENCODE(n)        ((((unsigned long)(n))&0xFFFFFFFF)<<0)
-#define DDR0_36_ECC_U_DATA_DECODE(n)        ((((unsigned long)(n))>>0)&0xFFFFFFFF)
-
-#define DDR0_37                         0x25
-#define DDR0_37_ECC_U_DATA_MASK           0xFFFFFFFF /* Read only */
-#define DDR0_37_ECC_U_DATA_ENCODE(n)        ((((unsigned long)(n))&0xFFFFFFFF)<<0)
-#define DDR0_37_ECC_U_DATA_DECODE(n)        ((((unsigned long)(n))>>0)&0xFFFFFFFF)
-
-#define DDR0_38                         0x26
-#define DDR0_38_ECC_C_ADDR_MASK           0xFFFFFFFF /* Read only */
-#define DDR0_38_ECC_C_ADDR_ENCODE(n)        ((((unsigned long)(n))&0xFFFFFFFF)<<0)
-#define DDR0_38_ECC_C_ADDR_DECODE(n)        ((((unsigned long)(n))>>0)&0xFFFFFFFF)
-
-#define DDR0_39                         0x27
-#define DDR0_39_ECC_C_ADDR_MASK           0x00000001 /* Read only */
-#define DDR0_39_ECC_C_ADDR_ENCODE(n)        ((((unsigned long)(n))&0x1)<<0)
-#define DDR0_39_ECC_C_ADDR_DECODE(n)        ((((unsigned long)(n))>>0)&0x1)
-
-#define DDR0_40                         0x28
-#define DDR0_40_ECC_C_DATA_MASK           0xFFFFFFFF /* Read only */
-#define DDR0_40_ECC_C_DATA_ENCODE(n)        ((((unsigned long)(n))&0xFFFFFFFF)<<0)
-#define DDR0_40_ECC_C_DATA_DECODE(n)        ((((unsigned long)(n))>>0)&0xFFFFFFFF)
-
-#define DDR0_41                         0x29
-#define DDR0_41_ECC_C_DATA_MASK           0xFFFFFFFF /* Read only */
-#define DDR0_41_ECC_C_DATA_ENCODE(n)        ((((unsigned long)(n))&0xFFFFFFFF)<<0)
-#define DDR0_41_ECC_C_DATA_DECODE(n)        ((((unsigned long)(n))>>0)&0xFFFFFFFF)
-
-#define DDR0_42                         0x2A
-#define DDR0_42_ADDR_PINS_MASK            0x07000000
-#define DDR0_42_ADDR_PINS_ENCODE(n)         ((((unsigned long)(n))&0x7)<<24)
-#define DDR0_42_ADDR_PINS_DECODE(n)         ((((unsigned long)(n))>>24)&0x7)
-#define DDR0_42_CASLAT_LIN_GATE_MASK      0x0000000F
-#define DDR0_42_CASLAT_LIN_GATE_ENCODE(n)   ((((unsigned long)(n))&0xF)<<0)
-#define DDR0_42_CASLAT_LIN_GATE_DECODE(n)   ((((unsigned long)(n))>>0)&0xF)
-
-#define DDR0_43                         0x2B
-#define DDR0_43_TWR_MASK                  0x07000000
-#define DDR0_43_TWR_ENCODE(n)               ((((unsigned long)(n))&0x7)<<24)
-#define DDR0_43_TWR_DECODE(n)               ((((unsigned long)(n))>>24)&0x7)
-#define DDR0_43_APREBIT_MASK              0x000F0000
-#define DDR0_43_APREBIT_ENCODE(n)           ((((unsigned long)(n))&0xF)<<16)
-#define DDR0_43_APREBIT_DECODE(n)           ((((unsigned long)(n))>>16)&0xF)
-#define DDR0_43_COLUMN_SIZE_MASK          0x00000700
-#define DDR0_43_COLUMN_SIZE_ENCODE(n)       ((((unsigned long)(n))&0x7)<<8)
-#define DDR0_43_COLUMN_SIZE_DECODE(n)       ((((unsigned long)(n))>>8)&0x7)
-#define DDR0_43_EIGHT_BANK_MODE_MASK      0x00000001
-#define DDR0_43_EIGHT_BANK_MODE_8_BANKS     0x00000001
-#define DDR0_43_EIGHT_BANK_MODE_4_BANKS     0x00000000
-#define DDR0_43_EIGHT_BANK_MODE_ENCODE(n)   ((((unsigned long)(n))&0x1)<<0)
-#define DDR0_43_EIGHT_BANK_MODE_DECODE(n)   ((((unsigned long)(n))>>0)&0x1)
-
-#define DDR0_44                         0x2C
-#define DDR0_44_TRCD_MASK                 0x000000FF
-#define DDR0_44_TRCD_ENCODE(n)              ((((unsigned long)(n))&0xFF)<<0)
-#define DDR0_44_TRCD_DECODE(n)              ((((unsigned long)(n))>>0)&0xFF)
-
-#endif /* _SPD_SDRAM_DENALI_H_ */

From 845c6c95dbfe6c915ce68a0a115852fa17932fb4 Mon Sep 17 00:00:00 2001
From: Stefan Roese <sr@denx.de>
Date: Sat, 5 Jan 2008 09:12:41 +0100
Subject: [PATCH 040/108] ppc4xx: Update Katmai/44x_spd_ddr2.c code for optimal
 DDR2 setup

On Katmai the complete auto-calibration somehow doesn't seem to
produce the best results, meaning optimal values for RQFD/RFFD.
This was discovered by GDA using a high bandwidth scope,
analyzing the DDR2 signals. GDA provided a fixed value for RQFD,
so now on Katmai "only" RFFD is auto-calibrated.

This patch also adds RDCC calibration as mentioned on page 7 of
the AMCC PowerPC440SP/SPe DDR2 application note:
"DDR1/DDR2 Initialization Sequence and Dynamic Tuning"

Signed-off-by: Stefan Roese <sr@denx.de>
---
 board/amcc/katmai/katmai.c | 14 +++++++++-
 cpu/ppc4xx/44x_spd_ddr2.c  | 52 +++++++++++++++++++++++++++-----------
 include/configs/katmai.h   |  1 +
 include/ppc440.h           | 12 +++++++--
 4 files changed, 61 insertions(+), 18 deletions(-)

diff --git a/board/amcc/katmai/katmai.c b/board/amcc/katmai/katmai.c
index 25c9a22fe..e41caaf34 100644
--- a/board/amcc/katmai/katmai.c
+++ b/board/amcc/katmai/katmai.c
@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2007
+ * (C) Copyright 2007-2008
  * Stefan Roese, DENX Software Engineering, sr@denx.de.
  *
  * See file CREDITS for list of people who contributed to this
@@ -246,6 +246,18 @@ int checkboard (void)
 	return 0;
 }
 
+/*
+ * Override the default functions in cpu/ppc4xx/44x_spd_ddr2.c with
+ * board specific values.
+ */
+u32 ddr_wrdtr(u32 default_val) {
+	return (SDRAM_WRDTR_LLWP_1_CYC | SDRAM_WRDTR_WTR_180_DEG_ADV | 0x823);
+}
+
+u32 ddr_clktr(u32 default_val) {
+	return (SDRAM_CLKTR_CLKP_90_DEG_ADV);
+}
+
 #if defined(CFG_DRAM_TEST)
 int testdram (void)
 {
diff --git a/cpu/ppc4xx/44x_spd_ddr2.c b/cpu/ppc4xx/44x_spd_ddr2.c
index e19929437..2475ed95e 100644
--- a/cpu/ppc4xx/44x_spd_ddr2.c
+++ b/cpu/ppc4xx/44x_spd_ddr2.c
@@ -3,7 +3,7 @@
  * This SPD SDRAM detection code supports AMCC PPC44x cpu's with a
  * DDR2 controller (non Denali Core). Those are 440SP/SPe.
  *
- * (C) Copyright 2007
+ * (C) Copyright 2007-2008
  * Stefan Roese, DENX Software Engineering, sr@denx.de.
  *
  * COPYRIGHT   AMCC   CORPORATION 2004
@@ -2409,17 +2409,10 @@ static void program_DQS_calibration(unsigned long *dimm_populated,
 	 * Read sample cycle auto-update enable
 	 *-----------------------------------------------------------------*/
 
-	/*
-	 * Modified for the Katmai platform:  with some DIMMs, the DDR2
-	 * controller automatically selects the T2 read cycle, but this
-	 * proves unreliable.  Go ahead and force the DDR2 controller
-	 * to use the T4 sample and disable the automatic update of the
-	 * RDSS field.
-	 */
 	mfsdram(SDRAM_RDCC, val);
 	mtsdram(SDRAM_RDCC,
 		(val & ~(SDRAM_RDCC_RDSS_MASK | SDRAM_RDCC_RSAE_MASK))
-		| (SDRAM_RDCC_RDSS_T4 | SDRAM_RDCC_RSAE_DISABLE));
+		| SDRAM_RDCC_RSAE_ENABLE);
 
 	/*------------------------------------------------------------------
 	 * Program RQDC register
@@ -2512,10 +2505,7 @@ static void DQS_calibration_process(void)
 {
 	unsigned long rfdc_reg;
 	unsigned long rffd;
-	unsigned long rqdc_reg;
-	unsigned long rqfd;
 	unsigned long val;
-	long rqfd_average;
 	long rffd_average;
 	long max_start;
 	long min_end;
@@ -2533,10 +2523,14 @@ static void DQS_calibration_process(void)
 	long max_end;
 	unsigned char fail_found;
 	unsigned char pass_found;
+#if !defined(CONFIG_DDR_RQDC_FIXED)
+	u32 rqdc_reg;
+	u32 rqfd;
 	u32 rqfd_start;
+	u32 rqfd_average;
+	int loopi = 0;
 	char str[] = "Auto calibration -";
 	char slash[] = "\\|/-\\|/-";
-	int loopi = 0;
 
 	/*------------------------------------------------------------------
 	 * Test to determine the best read clock delay tuning bits.
@@ -2571,6 +2565,16 @@ calibration_loop:
 	mfsdram(SDRAM_RQDC, rqdc_reg);
 	mtsdram(SDRAM_RQDC, (rqdc_reg & ~SDRAM_RQDC_RQFD_MASK) |
 		SDRAM_RQDC_RQFD_ENCODE(rqfd_start));
+#else /* CONFIG_DDR_RQDC_FIXED */
+	/*
+	 * On Katmai the complete auto-calibration somehow doesn't seem to
+	 * produce the best results, meaning optimal values for RQFD/RFFD.
+	 * This was discovered by GDA using a high bandwidth scope,
+	 * analyzing the DDR2 signals. GDA provided a fixed value for RQFD,
+	 * so now on Katmai "only" RFFD is auto-calibrated.
+	 */
+	mtsdram(SDRAM_RQDC, CONFIG_DDR_RQDC_FIXED);
+#endif /* CONFIG_DDR_RQDC_FIXED */
 
 	max_start = 0;
 	min_end = 0;
@@ -2655,6 +2659,7 @@ calibration_loop:
 	/* now fix RFDC[RFFD] found and find RQDC[RQFD] */
 	mtsdram(SDRAM_RFDC, rfdc_reg | SDRAM_RFDC_RFFD_ENCODE(rffd_average));
 
+#if !defined(CONFIG_DDR_RQDC_FIXED)
 	max_pass_length = 0;
 	max_start = 0;
 	max_end = 0;
@@ -2727,8 +2732,6 @@ calibration_loop:
 		spd_ddr_init_hang ();
 	}
 
-	blank_string(strlen(str));
-
 	if (rqfd_average < 0)
 		rqfd_average = 0;
 
@@ -2739,12 +2742,31 @@ calibration_loop:
 		(rqdc_reg & ~SDRAM_RQDC_RQFD_MASK) |
 		SDRAM_RQDC_RQFD_ENCODE(rqfd_average));
 
+	blank_string(strlen(str));
+#endif /* CONFIG_DDR_RQDC_FIXED */
+
+	/*
+	 * Now complete RDSS configuration as mentioned on page 7 of the AMCC
+	 * PowerPC440SP/SPe DDR2 application note:
+	 * "DDR1/DDR2 Initialization Sequence and Dynamic Tuning"
+	 */
+	mfsdram(SDRAM_RTSR, val);
+	if ((val & SDRAM_RTSR_TRK1SM_MASK) == SDRAM_RTSR_TRK1SM_ATPLS1) {
+		mfsdram(SDRAM_RDCC, val);
+		if ((val & SDRAM_RDCC_RDSS_MASK) != SDRAM_RDCC_RDSS_T4) {
+			val += 0x40000000;
+			mtsdram(SDRAM_RDCC, val);
+		}
+	}
+
 	mfsdram(SDRAM_DLCR, val);
 	debug("%s[%d] DLCR: 0x%08X\n", __FUNCTION__, __LINE__, val);
 	mfsdram(SDRAM_RQDC, val);
 	debug("%s[%d] RQDC: 0x%08X\n", __FUNCTION__, __LINE__, val);
 	mfsdram(SDRAM_RFDC, val);
 	debug("%s[%d] RFDC: 0x%08X\n", __FUNCTION__, __LINE__, val);
+	mfsdram(SDRAM_RDCC, val);
+	debug("%s[%d] RDCC: 0x%08X\n", __FUNCTION__, __LINE__, val);
 }
 #else /* calibration test with hardvalues */
 /*-----------------------------------------------------------------------------+
diff --git a/include/configs/katmai.h b/include/configs/katmai.h
index 0aa4f2dcc..78c794a05 100644
--- a/include/configs/katmai.h
+++ b/include/configs/katmai.h
@@ -111,6 +111,7 @@
 #define CONFIG_SPD_EEPROM	1	/* Use SPD EEPROM for setup	*/
 #define SPD_EEPROM_ADDRESS	{0x51, 0x52}	/* SPD i2c spd addresses*/
 #define CONFIG_DDR_ECC		1	/* with ECC support		*/
+#define CONFIG_DDR_RQDC_FIXED	0x80000038 /* optimal value found by GDA*/
 #undef  CONFIG_STRESS
 
 /*-----------------------------------------------------------------------
diff --git a/include/ppc440.h b/include/ppc440.h
index 90e56b098..bfd1e1033 100644
--- a/include/ppc440.h
+++ b/include/ppc440.h
@@ -492,6 +492,7 @@
 #define SDRAM_ECCCR	0x98	/* ECC error status                          */
 #define SDRAM_CID	0xA4	/* core ID                                   */
 #define SDRAM_RID	0xA8	/* revision ID                               */
+#define SDRAM_RTSR	0xB1	/* run time status tracking                  */
 
 /*-----------------------------------------------------------------------------+
 |  Memory Controller Status
@@ -605,8 +606,8 @@
 #define SDRAM_RFDC_ARSE_ENABLE		0x00000000
 #define SDRAM_RFDC_RFOS_MASK		0x007F0000
 #define SDRAM_RFDC_RFOS_ENCODE(n)	((((unsigned long)(n))&0x7F)<<16)
-#define SDRAM_RFDC_RFFD_MASK		0x000003FF
-#define SDRAM_RFDC_RFFD_ENCODE(n)	((((unsigned long)(n))&0x3FF)<<0)
+#define SDRAM_RFDC_RFFD_MASK		0x000007FF
+#define SDRAM_RFDC_RFFD_ENCODE(n)	((((unsigned long)(n))&0x7FF)<<0)
 
 #define SDRAM_RFDC_RFFD_MAX		0x7FF
 
@@ -690,6 +691,7 @@
 #define SDRAM_CLKTR_CLKP_MASK		0xC0000000
 #define SDRAM_CLKTR_CLKP_0_DEG		0x00000000
 #define SDRAM_CLKTR_CLKP_180_DEG_ADV	0x80000000
+#define SDRAM_CLKTR_CLKP_90_DEG_ADV	0x40000000
 
 /*-----------------------------------------------------------------------------+
 |  SDRAM Write Timing Register
@@ -790,6 +792,12 @@
 #define SDRAM_BXCF_M_BE_DISABLE		0x00000000	/* Memory Bank Enable	*/
 #define SDRAM_BXCF_M_BE_ENABLE		0x00000001	/* Memory Bank Enable	*/
 
+#define SDRAM_RTSR_TRK1SM_MASK		0xC0000000	/* Tracking State Mach 1*/
+#define SDRAM_RTSR_TRK1SM_ATBASE	0x00000000	/* atbase state		*/
+#define SDRAM_RTSR_TRK1SM_MISSED	0x40000000	/* missed state		*/
+#define SDRAM_RTSR_TRK1SM_ATPLS1	0x80000000	/* atpls1 state		*/
+#define SDRAM_RTSR_TRK1SM_RESET		0xC0000000	/* reset  state		*/
+
 #define SDR0_MFR_FIXD			0x10000000	/* Workaround for PCI/DMA */
 #endif /* CONFIG_440SPE */
 

From 5ba576c01602fd328800a427964c36a0a05c5dce Mon Sep 17 00:00:00 2001
From: Stefan Roese <sr@denx.de>
Date: Sat, 5 Jan 2008 09:13:46 +0100
Subject: [PATCH 041/108] ppc4xx: Remove unused CONFIG_ECC_ERROR_RESET from
 44x_spd_ddr2.c

Signed-off-by: Stefan Roese <sr@denx.de>
---
 cpu/ppc4xx/44x_spd_ddr2.c | 44 ---------------------------------------
 1 file changed, 44 deletions(-)

diff --git a/cpu/ppc4xx/44x_spd_ddr2.c b/cpu/ppc4xx/44x_spd_ddr2.c
index 2475ed95e..3ac2cdcf7 100644
--- a/cpu/ppc4xx/44x_spd_ddr2.c
+++ b/cpu/ppc4xx/44x_spd_ddr2.c
@@ -111,8 +111,6 @@
 #define NUMMEMWORDS	8
 #define NUMLOOPS	64		/* memory test loops */
 
-#undef CONFIG_ECC_ERROR_RESET		/* test-only: see description below, at check_ecc() */
-
 /*
  * This DDR2 setup code can dynamically setup the TLB entries for the DDR2 memory
  * region. Right now the cache should still be disabled in U-Boot because of the
@@ -2268,39 +2266,6 @@ static void program_ecc(unsigned long *dimm_populated,
 	return;
 }
 
-#ifdef CONFIG_ECC_ERROR_RESET
-/*
- * Check for ECC errors and reset board upon any error here
- *
- * On the Katmai 440SPe eval board, from time to time, the first
- * lword write access after DDR2 initializazion with ECC checking
- * enabled, leads to an ECC error. I couldn't find a configuration
- * without this happening. On my board with the current setup it
- * happens about 1 from 10 times.
- *
- * The ECC modules used for testing are:
- * - Kingston ValueRAM KVR667D2E5/512 (tested with 1 and 2 DIMM's)
- *
- * This has to get fixed for the Katmai and tested for the other
- * board (440SP/440SPe) that will eventually use this code in the
- * future.
- *
- * 2007-03-01, sr
- */
-static void check_ecc(void)
-{
-	u32 val;
-
-	mfsdram(SDRAM_ECCCR, val);
-	if (val != 0) {
-		printf("\nECC error: MCIF0_ECCES=%08lx MQ0_ESL=%08lx address=%08lx\n",
-		       val, mfdcr(0x4c), mfdcr(0x4e));
-		printf("ECC error occured, resetting board...\n");
-		do_reset(NULL, 0, 0, NULL);
-	}
-}
-#endif
-
 static void wait_ddr_idle(void)
 {
 	u32 val;
@@ -2375,15 +2340,6 @@ static void program_ecc_addr(unsigned long start_address,
 		sync();
 		eieio();
 		wait_ddr_idle();
-
-#ifdef CONFIG_ECC_ERROR_RESET
-		/*
-		 * One write to 0 is enough to trigger this ECC error
-		 * (see description above)
-		 */
-		out_be32(0, 0x12345678);
-		check_ecc();
-#endif
 	}
 }
 #endif

From e05329516a13616b53240cd85b739217c2bf87f1 Mon Sep 17 00:00:00 2001
From: Larry Johnson <lrj@acm.org>
Date: Fri, 4 Jan 2008 13:27:02 -0500
Subject: [PATCH 042/108] ppc4xx: Remove weak binding from common Denali
 data-eye search code

Now that there are no board-specific versions of
"denali_core_search_data_eye()", the weak binding on the common version
can be removed.

Signed-off-by: Larry Johnson <lrj@acm.org>
---
 cpu/ppc4xx/denali_data_eye.c | 7 -------
 1 file changed, 7 deletions(-)

diff --git a/cpu/ppc4xx/denali_data_eye.c b/cpu/ppc4xx/denali_data_eye.c
index 6c949a0fe..967e61bd4 100644
--- a/cpu/ppc4xx/denali_data_eye.c
+++ b/cpu/ppc4xx/denali_data_eye.c
@@ -99,14 +99,7 @@ static int wait_for_dram_init_complete(void)
 /*-----------------------------------------------------------------------------+
  * denali_core_search_data_eye.
  +----------------------------------------------------------------------------*/
-/*
- * Avoid conflict with implementations of denali_core_search_data_eye in board-
- * specific code.
- */
 void denali_core_search_data_eye(void)
-    __attribute__ ((weak, alias("__denali_core_search_data_eye")));
-
-void __denali_core_search_data_eye(void)
 {
 	int k, j;
 	u32 val;

From b2893e1fcb28fad8c8b317104df8cee0142c7631 Mon Sep 17 00:00:00 2001
From: Timur Tabi <timur@freescale.com>
Date: Mon, 5 Nov 2007 09:34:06 -0600
Subject: [PATCH 043/108] 83xx: fix CFG_ENV_ADDR and CFG_ENV_SECT_SIZE
 definitions

Fix the definitions of CFG_ENV_ADDR and CFG_ENV_SECT_SIZE for all of the
currently-defined 83xx boards.  This change guarantees that the environment
will be located on the first flash sector after the U-Boot image.

Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
---
 include/configs/MPC8313ERDB.h | 3 ++-
 include/configs/MPC8323ERDB.h | 5 +++--
 include/configs/MPC832XEMDS.h | 5 +++--
 include/configs/MPC8349EMDS.h | 2 +-
 include/configs/MPC8349ITX.h  | 3 ++-
 include/configs/MPC8360EMDS.h | 5 +++--
 6 files changed, 14 insertions(+), 9 deletions(-)

diff --git a/include/configs/MPC8313ERDB.h b/include/configs/MPC8313ERDB.h
index 6568fe13b..0c3bc16c9 100644
--- a/include/configs/MPC8313ERDB.h
+++ b/include/configs/MPC8313ERDB.h
@@ -178,6 +178,7 @@
 #define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 #define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
 
+/* CFG_MONITOR_LEN must be a multiple of CFG_ENV_SECT_SIZE */
 #define CFG_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB for Mon */
 #define CFG_MALLOC_LEN		(512 * 1024)	/* Reserved for malloc */
 
@@ -326,7 +327,7 @@
  */
 #ifndef CFG_RAMBOOT
 	#define CFG_ENV_IS_IN_FLASH	1
-	#define CFG_ENV_ADDR		(CFG_MONITOR_BASE + 0x40000)
+	#define CFG_ENV_ADDR		(CFG_MONITOR_BASE + CFG_MONITOR_LEN)
 	#define CFG_ENV_SECT_SIZE	0x10000	/* 64K(one sector) for env */
 	#define CFG_ENV_SIZE		0x2000
 
diff --git a/include/configs/MPC8323ERDB.h b/include/configs/MPC8323ERDB.h
index 376973b94..558f94bb7 100644
--- a/include/configs/MPC8323ERDB.h
+++ b/include/configs/MPC8323ERDB.h
@@ -116,6 +116,7 @@
 #undef  CFG_RAMBOOT
 #endif
 
+/* CFG_MONITOR_LEN must be a multiple of CFG_ENV_SECT_SIZE */
 #define CFG_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB for Mon */
 #define CFG_MALLOC_LEN		(128 * 1024)	/* Reserved for malloc */
 
@@ -354,8 +355,8 @@
  */
 #ifndef CFG_RAMBOOT
 	#define CFG_ENV_IS_IN_FLASH	1
-	#define CFG_ENV_ADDR		(CFG_MONITOR_BASE + 0x40000)
-	#define CFG_ENV_SECT_SIZE	0x40000	/* 256K(one sector) for env */
+	#define CFG_ENV_ADDR		(CFG_MONITOR_BASE + CFG_MONITOR_LEN)
+	#define CFG_ENV_SECT_SIZE	0x20000
 	#define CFG_ENV_SIZE		0x2000
 #else
 	#define CFG_NO_FLASH		1	/* Flash is not usable now */
diff --git a/include/configs/MPC832XEMDS.h b/include/configs/MPC832XEMDS.h
index c9c6d88cf..5345fc62f 100644
--- a/include/configs/MPC832XEMDS.h
+++ b/include/configs/MPC832XEMDS.h
@@ -145,6 +145,7 @@
 #undef  CFG_RAMBOOT
 #endif
 
+/* CFG_MONITOR_LEN must be a multiple of CFG_ENV_SECT_SIZE */
 #define CFG_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB for Mon */
 #define CFG_MALLOC_LEN		(128 * 1024)	/* Reserved for malloc */
 
@@ -410,8 +411,8 @@
  */
 #ifndef CFG_RAMBOOT
 	#define CFG_ENV_IS_IN_FLASH	1
-	#define CFG_ENV_ADDR		(CFG_MONITOR_BASE + 0x40000)
-	#define CFG_ENV_SECT_SIZE	0x40000	/* 256K(one sector) for env */
+	#define CFG_ENV_ADDR		(CFG_MONITOR_BASE + CFG_MONITOR_LEN)
+	#define CFG_ENV_SECT_SIZE	0x20000
 	#define CFG_ENV_SIZE		0x2000
 #else
 	#define CFG_NO_FLASH		1	/* Flash is not usable now */
diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h
index 92555bac4..7d5b17b50 100644
--- a/include/configs/MPC8349EMDS.h
+++ b/include/configs/MPC8349EMDS.h
@@ -456,7 +456,7 @@
  */
 #ifndef CFG_RAMBOOT
 	#define CFG_ENV_IS_IN_FLASH	1
-	#define CFG_ENV_ADDR		(CFG_MONITOR_BASE + 0x40000)
+	#define CFG_ENV_ADDR		(CFG_MONITOR_BASE + CFG_MONITOR_LEN)
 	#define CFG_ENV_SECT_SIZE	0x20000	/* 128K(one sector) for env */
 	#define CFG_ENV_SIZE		0x2000
 
diff --git a/include/configs/MPC8349ITX.h b/include/configs/MPC8349ITX.h
index 54cab528b..2a2e753c8 100644
--- a/include/configs/MPC8349ITX.h
+++ b/include/configs/MPC8349ITX.h
@@ -261,6 +261,7 @@ boards, we say we have two, but don't display a message if we find only one. */
 #define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 #define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
 
+/* CFG_MONITOR_LEN must be a multiple of CFG_ENV_SECT_SIZE */
 #define CFG_MONITOR_LEN		(256 * 1024) /* Reserve 256 kB for Mon */
 #define CFG_MALLOC_LEN		(128 * 1024) /* Reserved for malloc */
 
@@ -404,8 +405,8 @@ boards, we say we have two, but don't display a message if we find only one. */
 
 #ifndef CFG_RAMBOOT
   #define CFG_ENV_IS_IN_FLASH
+  #define CFG_ENV_ADDR		(CFG_MONITOR_BASE + CFG_MONITOR_LEN)
   #define CFG_ENV_SECT_SIZE	0x10000 /* 64K (one sector) for environment */
-  #define CFG_ENV_ADDR		(CFG_MONITOR_BASE + (4 * CFG_ENV_SECT_SIZE))
   #define CFG_ENV_SIZE		0x2000
 #else
   #define CFG_NO_FLASH		/* Flash is not usable now */
diff --git a/include/configs/MPC8360EMDS.h b/include/configs/MPC8360EMDS.h
index 41f062ce7..8098951c5 100644
--- a/include/configs/MPC8360EMDS.h
+++ b/include/configs/MPC8360EMDS.h
@@ -170,6 +170,7 @@
 #undef	CFG_RAMBOOT
 #endif
 
+/* CFG_MONITOR_LEN must be a multiple of CFG_ENV_SECT_SIZE */
 #define CFG_MONITOR_LEN		(256 * 1024) /* Reserve 256 kB for Mon */
 #define CFG_MALLOC_LEN		(128 * 1024) /* Reserved for malloc */
 
@@ -443,8 +444,8 @@
 
 #ifndef CFG_RAMBOOT
 	#define CFG_ENV_IS_IN_FLASH	1
-	#define CFG_ENV_ADDR		(CFG_MONITOR_BASE + 0x40000)
-	#define CFG_ENV_SECT_SIZE	0x40000 /* 256K(one sector) for env */
+	#define CFG_ENV_ADDR		(CFG_MONITOR_BASE + CFG_MONITOR_LEN)
+	#define CFG_ENV_SECT_SIZE	0x20000
 	#define CFG_ENV_SIZE		0x2000
 #else
 	#define CFG_NO_FLASH		1	/* Flash is not usable now */

From 651d96f7e4c84adcdb98ef07ec878c20326e3359 Mon Sep 17 00:00:00 2001
From: Anton Vorontsov <avorontsov@ru.mvista.com>
Date: Wed, 14 Nov 2007 18:54:53 +0300
Subject: [PATCH 044/108] MPC8360E-MDS: configure and enable second UART

Despite user manual, BCSR9.7 is negated (high) on HRST, so
UART2 is disabled. Fix that and configure QE pins properly.

Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
---
 board/freescale/mpc8360emds/mpc8360emds.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/board/freescale/mpc8360emds/mpc8360emds.c b/board/freescale/mpc8360emds/mpc8360emds.c
index e050cd439..538a556c6 100644
--- a/board/freescale/mpc8360emds/mpc8360emds.c
+++ b/board/freescale/mpc8360emds/mpc8360emds.c
@@ -87,6 +87,11 @@ const qe_iop_conf_t qe_iop_conf_tab[] = {
 	{0,  1, 3, 0, 2}, /* MDIO */
 	{0,  2, 1, 0, 1}, /* MDC */
 
+	{5,  0, 1, 0, 2}, /* UART2_SOUT */
+	{5,  1, 2, 0, 3}, /* UART2_CTS */
+	{5,  2, 1, 0, 1}, /* UART2_RTS */
+	{5,  3, 2, 0, 2}, /* UART2_SIN */
+
 	{0,  0, 0, 0, QE_IOP_TAB_END}, /* END of table */
 };
 
@@ -106,6 +111,9 @@ int board_early_init_f(void)
 	    immr->sysconf.spridr == SPR_8360E_REV21)
 		bcsr[0xe] = 0x30;
 
+	/* Enable second UART */
+	bcsr[0x9] &= ~0x01;
+
 	return 0;
 }
 

From 03051c3d35c9981ceaa059005660e699f3eacf1c Mon Sep 17 00:00:00 2001
From: Dave Liu <r63238@freescale.com>
Date: Tue, 18 Sep 2007 12:36:11 +0800
Subject: [PATCH 045/108] mpc83xx: Add the support of MPC837x SoC

The MPC837x SoC including e300c4 core and new IP blocks,
such as SDHC, PCI Express and SATA controller.

Signed-off-by: Dave Liu <daveliu@freescale.com>
---
 cpu/mpc83xx/cpu.c             |  24 ++++-
 cpu/mpc83xx/speed.c           | 169 +++++++++++++++++++++++++++------
 include/asm-ppc/global_data.h |  10 +-
 include/asm-ppc/immap_83xx.h  |  84 +++++++++++++++-
 include/mpc83xx.h             | 174 ++++++++++++++++++++++++++++++----
 5 files changed, 407 insertions(+), 54 deletions(-)

diff --git a/cpu/mpc83xx/cpu.c b/cpu/mpc83xx/cpu.c
index f1ea17d5a..98236ef50 100644
--- a/cpu/mpc83xx/cpu.c
+++ b/cpu/mpc83xx/cpu.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2004-2006 Freescale Semiconductor, Inc.
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
  *
  * See file CREDITS for list of people who contributed to this
  * project.
@@ -65,6 +65,10 @@ int checkcpu(void)
 			printf("e300c3, ");
 			break;
 
+		case PVR_E300C4:
+			printf("e300c4, ");
+			break;
+
 		default:
 			printf("Unknown core, ");
 	}
@@ -149,6 +153,24 @@ int checkcpu(void)
 	case SPR_8313E_REV10:
 		puts("MPC8313E, ");
 		break;
+	case SPR_8379E_REV10:
+		puts("MPC8379E, ");
+		break;
+	case SPR_8379_REV10:
+		puts("MPC8379, ");
+		break;
+	case SPR_8378E_REV10:
+		puts("MPC8378E, ");
+		break;
+	case SPR_8378_REV10:
+		puts("MPC8378, ");
+		break;
+	case SPR_8377E_REV10:
+		puts("MPC8377E, ");
+		break;
+	case SPR_8377_REV10:
+		puts("MPC8377, ");
+		break;
 	default:
 		printf("Rev: Unknown revision number:%08x\n"
 			"Warning: Unsupported cpu revision!\n",spridr);
diff --git a/cpu/mpc83xx/speed.c b/cpu/mpc83xx/speed.c
index cba57fadb..23dfb3041 100644
--- a/cpu/mpc83xx/speed.c
+++ b/cpu/mpc83xx/speed.c
@@ -2,7 +2,7 @@
  * (C) Copyright 2000-2002
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  *
- * Copyright (C) 2004-2006 Freescale Semiconductor, Inc.
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
  *
  * See file CREDITS for list of people who contributed to this
  * project.
@@ -100,7 +100,7 @@ int get_clocks(void)
 	u32 lcrr;
 
 	u32 csb_clk;
-#if defined(CONFIG_MPC834X) || defined(CONFIG_MPC831X)
+#if defined(CONFIG_MPC834X) || defined(CONFIG_MPC831X) || defined(CONFIG_MPC837X)
 	u32 tsec1_clk;
 	u32 tsec2_clk;
 	u32 usbdr_clk;
@@ -112,6 +112,9 @@ int get_clocks(void)
 	u32 i2c1_clk;
 #if !defined(CONFIG_MPC832X)
 	u32 i2c2_clk;
+#endif
+#if defined(CONFIG_MPC837X)
+	u32 sdhc_clk;
 #endif
 	u32 enc_clk;
 	u32 lbiu_clk;
@@ -126,6 +129,11 @@ int get_clocks(void)
 	u32 qe_clk;
 	u32 brg_clk;
 #endif
+#if defined(CONFIG_MPC837X)
+	u32 pciexp1_clk;
+	u32 pciexp2_clk;
+	u32 sata_clk;
+#endif
 
 	if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
 		return -1;
@@ -151,7 +159,7 @@ int get_clocks(void)
 
 	sccr = im->clk.sccr;
 
-#if defined(CONFIG_MPC834X) || defined(CONFIG_MPC831X)
+#if defined(CONFIG_MPC834X) || defined(CONFIG_MPC831X) || defined(CONFIG_MPC837X)
 	switch ((sccr & SCCR_TSEC1CM) >> SCCR_TSEC1CM_SHIFT) {
 	case 0:
 		tsec1_clk = 0;
@@ -167,7 +175,7 @@ int get_clocks(void)
 		break;
 	default:
 		/* unkown SCCR_TSEC1CM value */
-		return -4;
+		return -2;
 	}
 
 	switch ((sccr & SCCR_USBDRCM) >> SCCR_USBDRCM_SHIFT) {
@@ -185,11 +193,11 @@ int get_clocks(void)
 		break;
 	default:
 		/* unkown SCCR_USBDRCM value */
-		return -8;
+		return -3;
 	}
 #endif
 
-#if defined(CONFIG_MPC834X)
+#if defined(CONFIG_MPC834X) || defined(CONFIG_MPC837X)
 	switch ((sccr & SCCR_TSEC2CM) >> SCCR_TSEC2CM_SHIFT) {
 	case 0:
 		tsec2_clk = 0;
@@ -205,11 +213,18 @@ int get_clocks(void)
 		break;
 	default:
 		/* unkown SCCR_TSEC2CM value */
-		return -5;
+		return -4;
 	}
+#elif defined(CONFIG_MPC831X)
+	tsec2_clk = tsec1_clk;
 
-	i2c1_clk = tsec2_clk;
+	if (!(sccr & SCCR_TSEC1ON))
+		tsec1_clk = 0;
+	if (!(sccr & SCCR_TSEC2ON))
+		tsec2_clk = 0;
+#endif
 
+#if defined(CONFIG_MPC834X)
 	switch ((sccr & SCCR_USBMPHCM) >> SCCR_USBMPHCM_SHIFT) {
 	case 0:
 		usbmph_clk = 0;
@@ -225,7 +240,7 @@ int get_clocks(void)
 		break;
 	default:
 		/* unkown SCCR_USBMPHCM value */
-		return -7;
+		return -5;
 	}
 
 	if (usbmph_clk != 0 && usbdr_clk != 0 && usbmph_clk != usbdr_clk) {
@@ -233,24 +248,9 @@ int get_clocks(void)
 		 * USB DR clock is not disabled then
 		 * USB MPH & USB DR must have the same rate
 		 */
-		return -9;
+		return -6;
 	}
-#elif defined(CONFIG_MPC831X)
-	tsec2_clk = tsec1_clk;
-
-	if (!(sccr & SCCR_TSEC1ON))
-		tsec1_clk = 0;
-	if (!(sccr & SCCR_TSEC2ON))
-		tsec2_clk = 0;
 #endif
-
-#if !defined(CONFIG_MPC834X)
-	i2c1_clk = csb_clk;
-#endif
-#if !defined(CONFIG_MPC832X)
-	i2c2_clk = csb_clk;	/* i2c-2 clk is equal to csb clk */
-#endif
-
 	switch ((sccr & SCCR_ENCCM) >> SCCR_ENCCM_SHIFT) {
 	case 0:
 		enc_clk = 0;
@@ -266,9 +266,102 @@ int get_clocks(void)
 		break;
 	default:
 		/* unkown SCCR_ENCCM value */
-		return -6;
+		return -7;
 	}
 
+#if defined(CONFIG_MPC837X)
+	switch ((sccr & SCCR_SDHCCM) >> SCCR_SDHCCM_SHIFT) {
+	case 0:
+		sdhc_clk = 0;
+		break;
+	case 1:
+		sdhc_clk = csb_clk;
+		break;
+	case 2:
+		sdhc_clk = csb_clk / 2;
+		break;
+	case 3:
+		sdhc_clk = csb_clk / 3;
+		break;
+	default:
+		/* unkown SCCR_SDHCCM value */
+		return -8;
+	}
+#endif
+
+#if defined(CONFIG_MPC834X)
+	i2c1_clk = tsec2_clk;
+#elif defined(CONFIG_MPC8360)
+	i2c1_clk = csb_clk;
+#elif defined(CONFIG_MPC832X)
+	i2c1_clk = enc_clk;
+#elif defined(CONFIG_MPC831X)
+	i2c1_clk = enc_clk;
+#elif defined(CONFIG_MPC837X)
+	i2c1_clk = sdhc_clk;
+#endif
+#if !defined(CONFIG_MPC832X)
+	i2c2_clk = csb_clk; /* i2c-2 clk is equal to csb clk */
+#endif
+
+#if defined(CONFIG_MPC837X)
+	switch ((sccr & SCCR_PCIEXP1CM) >> SCCR_PCIEXP1CM_SHIFT) {
+	case 0:
+		pciexp1_clk = 0;
+		break;
+	case 1:
+		pciexp1_clk = csb_clk;
+		break;
+	case 2:
+		pciexp1_clk = csb_clk / 2;
+		break;
+	case 3:
+		pciexp1_clk = csb_clk / 3;
+		break;
+	default:
+		/* unkown SCCR_PCIEXP1CM value */
+		return -9;
+	}
+
+	switch ((sccr & SCCR_PCIEXP2CM) >> SCCR_PCIEXP2CM_SHIFT) {
+	case 0:
+		pciexp2_clk = 0;
+		break;
+	case 1:
+		pciexp2_clk = csb_clk;
+		break;
+	case 2:
+		pciexp2_clk = csb_clk / 2;
+		break;
+	case 3:
+		pciexp2_clk = csb_clk / 3;
+		break;
+	default:
+		/* unkown SCCR_PCIEXP2CM value */
+		return -10;
+	}
+#endif
+
+#if defined(CONFIG_MPC837X)
+	switch ((sccr & SCCR_SATA1CM) >> SCCR_SATA1CM_SHIFT) {
+	case 0:
+		sata_clk = 0;
+		break;
+	case 1:
+		sata_clk = csb_clk;
+		break;
+	case 2:
+		sata_clk = csb_clk / 2;
+		break;
+	case 3:
+		sata_clk = csb_clk / 3;
+		break;
+	default:
+		/* unkown SCCR_SATA1CM value */
+		return -11;
+	}
+#endif
+
 	lbiu_clk = csb_clk *
 	           (1 + ((im->reset.rcwl & HRCWL_LBIUCM) >> HRCWL_LBIUCM_SHIFT));
 	lcrr = (im->lbus.lcrr & LCRR_CLKDIV) >> LCRR_CLKDIV_SHIFT;
@@ -280,7 +373,7 @@ int get_clocks(void)
 		break;
 	default:
 		/* unknown lcrr */
-		return -10;
+		return -12;
 	}
 
 	ddr_clk = csb_clk *
@@ -316,7 +409,7 @@ int get_clocks(void)
 		break;
 	default:
 		/* unkown core to csb ratio */
-		return -12;
+		return -13;
 	}
 
 #if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832X)
@@ -327,13 +420,16 @@ int get_clocks(void)
 #endif
 
 	gd->csb_clk = csb_clk;
-#if defined(CONFIG_MPC834X) || defined(CONFIG_MPC831X)
+#if defined(CONFIG_MPC834X) || defined(CONFIG_MPC831X) || defined(CONFIG_MPC837X)
 	gd->tsec1_clk = tsec1_clk;
 	gd->tsec2_clk = tsec2_clk;
 	gd->usbdr_clk = usbdr_clk;
 #endif
 #if defined(CONFIG_MPC834X)
 	gd->usbmph_clk = usbmph_clk;
+#endif
+#if defined(CONFIG_MPC837X)
+	gd->sdhc_clk = sdhc_clk;
 #endif
 	gd->core_clk = core_clk;
 	gd->i2c1_clk = i2c1_clk;
@@ -350,6 +446,11 @@ int get_clocks(void)
 #if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832X)
 	gd->qe_clk = qe_clk;
 	gd->brg_clk = brg_clk;
+#endif
+#if defined(CONFIG_MPC837X)
+	gd->pciexp1_clk = pciexp1_clk;
+	gd->pciexp2_clk = pciexp2_clk;
+	gd->sata_clk = sata_clk;
 #endif
 	gd->pci_clk = pci_sync_in;
 	gd->cpu_clk = gd->core_clk;
@@ -387,13 +488,21 @@ int do_clocks (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
 #if !defined(CONFIG_MPC832X)
 	printf("  I2C2:                %4d MHz\n", gd->i2c2_clk / 1000000);
 #endif
-#if defined(CONFIG_MPC834X) || defined(CONFIG_MPC831X)
+#if defined(CONFIG_MPC837X)
+	printf("  SDHC:                %4d MHz\n", gd->sdhc_clk / 1000000);
+#endif
+#if defined(CONFIG_MPC834X) || defined(CONFIG_MPC831X) || defined(CONFIG_MPC837X)
 	printf("  TSEC1:               %4d MHz\n", gd->tsec1_clk / 1000000);
 	printf("  TSEC2:               %4d MHz\n", gd->tsec2_clk / 1000000);
 	printf("  USB DR:              %4d MHz\n", gd->usbdr_clk / 1000000);
 #endif
 #if defined(CONFIG_MPC834X)
 	printf("  USB MPH:             %4d MHz\n", gd->usbmph_clk / 1000000);
+#endif
+#if defined(CONFIG_MPC837X)
+	printf("  PCIEXP1:             %4d MHz\n", gd->pciexp1_clk / 1000000);
+	printf("  PCIEXP2:             %4d MHz\n", gd->pciexp2_clk / 1000000);
+	printf("  SATA:                %4d MHz\n", gd->sata_clk / 1000000);
 #endif
 	return 0;
 }
diff --git a/include/asm-ppc/global_data.h b/include/asm-ppc/global_data.h
index 05aee7494..6ce072f66 100644
--- a/include/asm-ppc/global_data.h
+++ b/include/asm-ppc/global_data.h
@@ -55,7 +55,7 @@ typedef	struct	global_data {
 #if defined(CONFIG_MPC83XX)
 	/* There are other clocks in the MPC83XX */
 	u32 csb_clk;
-#if defined (CONFIG_MPC834X) || defined(CONFIG_MPC831X)
+#if defined(CONFIG_MPC834X) || defined(CONFIG_MPC831X) || defined(CONFIG_MPC837X)
 	u32 tsec1_clk;
 	u32 tsec2_clk;
 	u32 usbdr_clk;
@@ -63,6 +63,9 @@ typedef	struct	global_data {
 #if defined (CONFIG_MPC834X)
 	u32 usbmph_clk;
 #endif /* CONFIG_MPC834X */
+#if defined(CONFIG_MPC837X)
+	u32 sdhc_clk;
+#endif
 	u32 core_clk;
 	u32 i2c1_clk;
 	u32 i2c2_clk;
@@ -71,6 +74,11 @@ typedef	struct	global_data {
 	u32 lclk_clk;
 	u32 ddr_clk;
 	u32 pci_clk;
+#if defined(CONFIG_MPC837X)
+	u32 pciexp1_clk;
+	u32 pciexp2_clk;
+	u32 sata_clk;
+#endif
 #if defined(CONFIG_MPC8360)
 	u32  ddr_sec_clk;
 #endif /* CONFIG_MPC8360 */
diff --git a/include/asm-ppc/immap_83xx.h b/include/asm-ppc/immap_83xx.h
index 0de93385f..75171115b 100644
--- a/include/asm-ppc/immap_83xx.h
+++ b/include/asm-ppc/immap_83xx.h
@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2004-2006 Freescale Semiconductor, Inc.
+ * (C) Copyright 2004-2007 Freescale Semiconductor, Inc.
  *
  * MPC83xx Internal Memory Map
  *
@@ -63,7 +63,8 @@ typedef struct sysconf83xx {
 	u8 res6[0x0C];
 	u32 ddrcdr;		/* DDR Control Driver Register */
 	u32 ddrdsr;		/* DDR Debug Status Register */
-	u8 res7[0xD0];
+	u32 obir;		/* Output Buffer Impedance Register */
+	u8 res7[0xCC];
 } sysconf83xx_t;
 
 /*
@@ -553,6 +554,41 @@ typedef struct security83xx {
 	u8 fixme[0x10000];
 } security83xx_t;
 
+/*
+ *  PCI Express
+ */
+typedef struct pex83xx {
+	u8 fixme[0x1000];
+} pex83xx_t;
+
+/*
+ * SATA
+ */
+typedef struct sata83xx {
+	u8 fixme[0x1000];
+} sata83xx_t;
+
+/*
+ * eSDHC
+ */
+typedef struct sdhc83xx {
+	u8 fixme[0x1000];
+} sdhc83xx_t;
+
+/*
+ * SerDes
+ */
+typedef struct serdes83xx {
+	u8 fixme[0x100];
+} serdes83xx_t;
+
+/*
+ * On Chip ROM
+ */
+typedef struct rom83xx {
+	u8 mem[0x10000];
+} rom83xx_t;
+
 #if defined(CONFIG_MPC834X)
 typedef struct immap {
 	sysconf83xx_t		sysconf;	/* System configuration */
@@ -625,6 +661,50 @@ typedef struct immap {
 	u8			res7[0xC0000];
 } immap_t;
 
+#elif defined(CONFIG_MPC837X)
+typedef struct immap {
+	sysconf83xx_t		sysconf;	/* System configuration */
+	wdt83xx_t		wdt;		/* Watch Dog Timer (WDT) Registers */
+	rtclk83xx_t		rtc;		/* Real Time Clock Module Registers */
+	rtclk83xx_t		pit;		/* Periodic Interval Timer */
+	gtm83xx_t		gtm[2];		/* Global Timers Module */
+	ipic83xx_t		ipic;		/* Integrated Programmable Interrupt Controller */
+	arbiter83xx_t		arbiter;	/* System Arbiter Registers */
+	reset83xx_t		reset;		/* Reset Module */
+	clk83xx_t		clk;		/* System Clock Module */
+	pmc83xx_t		pmc;		/* Power Management Control Module */
+	gpio83xx_t		gpio[2];	/* General purpose I/O module */
+	u8			res0[0x1200];
+	ddr83xx_t		ddr;		/* DDR Memory Controller Memory */
+	fsl_i2c_t		i2c[2];		/* I2C Controllers */
+	u8			res1[0x1300];
+	duart83xx_t		duart[2];	/* DUART */
+	u8			res2[0x900];
+	lbus83xx_t		lbus;		/* Local Bus Controller Registers */
+	u8			res3[0x1000];
+	spi83xx_t		spi;		/* Serial Peripheral Interface */
+	dma83xx_t		dma;		/* DMA */
+	pciconf83xx_t		pci_conf[1];	/* PCI Software Configuration Registers */
+	u8			res4[0x80];
+	ios83xx_t		ios;		/* Sequencer */
+	pcictrl83xx_t		pci_ctrl[1];	/* PCI Controller Control and Status Registers */
+	u8			res5[0xa00];
+	pex83xx_t		pciexp[2];	/* PCI Express Controller */
+	u8			res6[0xd000];
+	sata83xx_t		sata[4];	/* SATA Controller */
+	u8			res7[0x7000];
+	usb83xx_t		usb[1];		/* USB DR Controller */
+	tsec83xx_t		tsec[2];
+	u8			res8[0x8000];
+	sdhc83xx_t		sdhc;		/* SDHC Controller */
+	u8			res9[0x1000];
+	security83xx_t		security;
+	u8			res10[0xA3000];
+	serdes83xx_t		serdes[2];	/* SerDes Registers */
+	u8			res11[0xCE00];
+	rom83xx_t		rom;		/* On Chip ROM */
+} immap_t;
+
 #elif defined(CONFIG_MPC8360)
 typedef struct immap {
 	sysconf83xx_t		sysconf;	/* System configuration */
diff --git a/include/mpc83xx.h b/include/mpc83xx.h
index 4d32c6a37..4c230943c 100644
--- a/include/mpc83xx.h
+++ b/include/mpc83xx.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2004-2006 Freescale Semiconductor, Inc.
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
  *
  * See file CREDITS for list of people who contributed to this
  * project.
@@ -98,10 +98,17 @@
 #define SPR_8321E_REV11			0x80660011
 #define SPR_8321_REV11			0x80670011
 
-#define SPR_8311_REV10			0x80B30010
-#define SPR_8311E_REV10			0x80B20010
-#define SPR_8313_REV10			0x80B10010
 #define SPR_8313E_REV10			0x80B00010
+#define SPR_8313_REV10			0x80B10010
+#define SPR_8311E_REV10			0x80B20010
+#define SPR_8311_REV10			0x80B30010
+
+#define SPR_8379E_REV10			0x80C20010
+#define SPR_8379_REV10			0x80C30010
+#define SPR_8378E_REV10			0x80C40010
+#define SPR_8378_REV10			0x80C50010
+#define SPR_8377E_REV10			0x80C60010
+#define SPR_8377_REV10			0x80C70010
 
 /* SPCR - System Priority Configuration Register
  */
@@ -130,8 +137,8 @@
 #define SPCR_TSEC2EP			0x00000003	/* TSEC2 emergency priority */
 #define SPCR_TSEC2EP_SHIFT		(31-31)
 
-#elif defined(CONFIG_MPC831X)
-/* SPCR bits - MPC831x specific */
+#elif defined(CONFIG_MPC831X) || defined(CONFIG_MPC837X)
+/* SPCR bits - MPC831x and MPC837x specific */
 #define SPCR_TSECDP			0x00003000	/* TSEC data priority */
 #define SPCR_TSECDP_SHIFT		(31-19)
 #define SPCR_TSECEP			0x00000C00	/* TSEC emergency priority */
@@ -242,6 +249,55 @@
 #define SICRH_TSOBI1			0x00000002
 #define SICRH_TSOBI2			0x00000001
 
+#elif defined(CONFIG_MPC837X)
+/* SICRL bits - MPC837x specific */
+#define SICRL_USB_A			0xC0000000
+#define SICRL_USB_B			0x30000000
+#define SICRL_UART			0x0C000000
+#define SICRL_GPIO_A			0x02000000
+#define SICRL_GPIO_B			0x01000000
+#define SICRL_GPIO_C			0x00800000
+#define SICRL_GPIO_D			0x00400000
+#define SICRL_GPIO_E			0x00200000
+#define SICRL_GPIO_F			0x00180000
+#define SICRL_GPIO_G			0x00040000
+#define SICRL_GPIO_H			0x00020000
+#define SICRL_GPIO_I			0x00010000
+#define SICRL_GPIO_J			0x00008000
+#define SICRL_GPIO_K			0x00004000
+#define SICRL_GPIO_L			0x00003000
+#define SICRL_DMA_A			0x00000800
+#define SICRL_DMA_B			0x00000400
+#define SICRL_DMA_C			0x00000200
+#define SICRL_DMA_D			0x00000100
+#define SICRL_DMA_E			0x00000080
+#define SICRL_DMA_F			0x00000040
+#define SICRL_DMA_G			0x00000020
+#define SICRL_DMA_H			0x00000010
+#define SICRL_DMA_I			0x00000008
+#define SICRL_DMA_J			0x00000004
+#define SICRL_LDP_A			0x00000002
+#define SICRL_LDP_B			0x00000001
+
+/* SICRH bits - MPC837x specific */
+#define SICRH_DDR			0x80000000
+#define SICRH_TSEC1_A			0x10000000
+#define SICRH_TSEC1_B			0x08000000
+#define SICRH_TSEC2_A			0x00400000
+#define SICRH_TSEC2_B			0x00200000
+#define SICRH_TSEC2_C			0x00100000
+#define SICRH_TSEC2_D			0x00080000
+#define SICRH_TSEC2_E			0x00040000
+#define SICRH_TMR			0x00010000
+#define SICRH_GPIO2_A			0x00008000
+#define SICRH_GPIO2_B			0x00004000
+#define SICRH_GPIO2_C			0x00002000
+#define SICRH_GPIO2_D			0x00001000
+#define SICRH_GPIO2_E			0x00000C00
+#define SICRH_GPIO2_F			0x00000300
+#define SICRH_GPIO2_G			0x000000C0
+#define SICRH_GPIO2_H			0x00000030
+#define SICRH_SPI			0x00000003
 #endif
 
 /* SWCRR - System Watchdog Control Register
@@ -390,6 +446,14 @@
 #define HRCWL_CE_TO_PLL_1X29		0x0000001D
 #define HRCWL_CE_TO_PLL_1X30		0x0000001E
 #define HRCWL_CE_TO_PLL_1X31		0x0000001F
+
+#elif defined(CONFIG_MPC837X)
+#define HRCWL_SVCOD			0x30000000
+#define HRCWL_SVCOD_SHIFT		28
+#define HRCWL_SVCOD_DIV_4		0x00000000
+#define HRCWL_SVCOD_DIV_8		0x10000000
+#define HRCWL_SVCOD_DIV_2		0x20000000
+#define HRCWL_SVCOD_DIV_1		0x30000000
 #endif
 
 /* HRCWH - Hardware Reset Configuration Word High
@@ -436,11 +500,14 @@
 #if defined(CONFIG_MPC834X)
 #define HRCWH_ROM_LOC_PCI2		0x00200000
 #endif
+#if defined(CONIFG_MPC837X)
+#define HRCWH_ROM_LOC_ON_CHIP_ROM	0x00300000
+#endif
 #define HRCWH_ROM_LOC_LOCAL_8BIT	0x00500000
 #define HRCWH_ROM_LOC_LOCAL_16BIT	0x00600000
 #define HRCWH_ROM_LOC_LOCAL_32BIT	0x00700000
 
-#if defined(CONFIG_MPC831X)
+#if defined(CONFIG_MPC831X) || defined(CONFIG_MPC837X)
 #define HRCWH_ROM_LOC_NAND_SP_8BIT	0x00100000
 #define HRCWH_ROM_LOC_NAND_SP_16BIT	0x00200000
 #define HRCWH_ROM_LOC_NAND_LP_8BIT	0x00500000
@@ -489,8 +556,13 @@
 
 /* RSR - Reset Status Register
  */
+#if defined(CONFIG_MPC837X)
+#define RSR_RSTSRC			0xF0000000	/* Reset source */
+#define RSR_RSTSRC_SHIFT		28
+#else
 #define RSR_RSTSRC			0xE0000000	/* Reset source */
 #define RSR_RSTSRC_SHIFT		29
+#endif
 #define RSR_BSF				0x00010000	/* Boot seq. fail */
 #define RSR_BSF_SHIFT			16
 #define RSR_SWSR			0x00002000	/* software soft reset */
@@ -577,8 +649,8 @@
 #define SCCR_PCICM			0x00010000
 #define SCCR_PCICM_SHIFT		16
 
-/* SCCR bits - MPC8349 specific */
-#ifdef CONFIG_MPC834X
+#if defined(CONFIG_MPC834X)
+/* SCCR bits - MPC834x specific */
 #define SCCR_TSEC1CM			0xc0000000
 #define SCCR_TSEC1CM_SHIFT		30
 #define SCCR_TSEC1CM_0			0x00000000
@@ -593,6 +665,18 @@
 #define SCCR_TSEC2CM_2			0x20000000
 #define SCCR_TSEC2CM_3			0x30000000
 
+/* The MPH must have the same clock ratio as DR, unless its clock disabled */
+#define SCCR_USBMPHCM			0x00c00000
+#define SCCR_USBMPHCM_SHIFT		22
+#define SCCR_USBDRCM			0x00300000
+#define SCCR_USBDRCM_SHIFT		20
+#define SCCR_USBCM			0x00f00000
+#define SCCR_USBCM_SHIFT		20
+#define SCCR_USBCM_0			0x00000000
+#define SCCR_USBCM_1			0x00500000
+#define SCCR_USBCM_2			0x00A00000
+#define SCCR_USBCM_3			0x00F00000
+
 #elif defined(CONFIG_MPC831X)
 /* TSEC1 bits are for TSEC2 as well */
 #define SCCR_TSEC1CM			0xc0000000
@@ -606,17 +690,67 @@
 #define SCCR_TSEC2ON			0x10000000
 #define SCCR_TSEC2ON_SHIFT		28
 
-#endif
-
-#define SCCR_USBMPHCM			0x00c00000
-#define SCCR_USBMPHCM_SHIFT		22
 #define SCCR_USBDRCM			0x00300000
 #define SCCR_USBDRCM_SHIFT		20
+#define SCCR_USBDRCM_0			0x00000000
+#define SCCR_USBDRCM_1			0x00100000
+#define SCCR_USBDRCM_2			0x00200000
+#define SCCR_USBDRCM_3			0x00300000
 
-#define SCCR_USBCM_0			0x00000000
-#define SCCR_USBCM_1			0x00500000
-#define SCCR_USBCM_2			0x00A00000
-#define SCCR_USBCM_3			0x00F00000
+#elif defined(CONFIG_MPC837X)
+/* SCCR bits - MPC837x specific */
+#define SCCR_TSEC1CM			0xc0000000
+#define SCCR_TSEC1CM_SHIFT		30
+#define SCCR_TSEC1CM_0			0x00000000
+#define SCCR_TSEC1CM_1			0x40000000
+#define SCCR_TSEC1CM_2			0x80000000
+#define SCCR_TSEC1CM_3			0xC0000000
+
+#define SCCR_TSEC2CM			0x30000000
+#define SCCR_TSEC2CM_SHIFT		28
+#define SCCR_TSEC2CM_0			0x00000000
+#define SCCR_TSEC2CM_1			0x10000000
+#define SCCR_TSEC2CM_2			0x20000000
+#define SCCR_TSEC2CM_3			0x30000000
+
+#define SCCR_SDHCCM			0x0c000000
+#define SCCR_SDHCCM_SHIFT		26
+#define SCCR_SDHCCM_0			0x00000000
+#define SCCR_SDHCCM_1			0x04000000
+#define SCCR_SDHCCM_2			0x08000000
+#define SCCR_SDHCCM_3			0x0c000000
+
+#define SCCR_USBDRCM			0x00c00000
+#define SCCR_USBDRCM_SHIFT		22
+#define SCCR_USBDRCM_0			0x00000000
+#define SCCR_USBDRCM_1			0x00400000
+#define SCCR_USBDRCM_2			0x00800000
+#define SCCR_USBDRCM_3			0x00c00000
+
+#define SCCR_PCIEXP1CM			0x00300000
+#define SCCR_PCIEXP1CM_SHIFT		20
+#define SCCR_PCIEXP1CM_0		0x00000000
+#define SCCR_PCIEXP1CM_1		0x00100000
+#define SCCR_PCIEXP1CM_2		0x00200000
+#define SCCR_PCIEXP1CM_3		0x00300000
+
+#define SCCR_PCIEXP2CM			0x000c0000
+#define SCCR_PCIEXP2CM_SHIFT		18
+#define SCCR_PCIEXP2CM_0		0x00000000
+#define SCCR_PCIEXP2CM_1		0x00040000
+#define SCCR_PCIEXP2CM_2		0x00080000
+#define SCCR_PCIEXP2CM_3		0x000c0000
+
+/* All of the four SATA controllers must have the same clock ratio */
+#define SCCR_SATA1CM			0x000000c0
+#define SCCR_SATA1CM_SHIFT		6
+#define SCCR_SATACM			0x000000ff
+#define SCCR_SATACM_SHIFT		0
+#define SCCR_SATACM_0			0x00000000
+#define SCCR_SATACM_1			0x00000055
+#define SCCR_SATACM_2			0x000000aa
+#define SCCR_SATACM_3			0x000000ff
+#endif
 
 /* CSn_BDNS - Chip Select memory Bounds Register
  */
@@ -860,7 +994,7 @@
 #define BR_MS_UPMA			0x00000080	/* UPMA */
 #define BR_MS_UPMB			0x000000A0	/* UPMB */
 #define BR_MS_UPMC			0x000000C0	/* UPMC */
-#if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832X)
+#if !defined(CONFIG_MPC834X)
 #define BR_ATOM				0x0000000C
 #define BR_ATOM_SHIFT			2
 #endif
@@ -869,7 +1003,7 @@
 
 #if defined(CONFIG_MPC834X)
 #define BR_RES				~(BR_BA | BR_PS | BR_DECC | BR_WP | BR_MSEL | BR_V)
-#elif defined(CONFIG_MPC8360)
+#else
 #define BR_RES				~(BR_BA | BR_PS | BR_DECC | BR_WP | BR_MSEL | BR_ATOM | BR_V)
 #endif
 
@@ -1255,7 +1389,7 @@
 #define LTESR_CS		0x00080000
 #define LTESR_CC		0x00000001
 
-/* DDR Control Driver Register
+/* DDRCDR - DDR Control Driver Register
  */
 #define DDRCDR_EN		0x40000000
 #define DDRCDR_PZ		0x3C000000

From 555da61702771fe0f76f3de23b4e7590f3704161 Mon Sep 17 00:00:00 2001
From: Dave Liu <r63238@freescale.com>
Date: Tue, 18 Sep 2007 12:36:58 +0800
Subject: [PATCH 046/108] mpc83xx: Add the support of MPC8315E SoC

The MPC8315E SoC including e300c3 core and new IP blocks,
such as TDM, PCI Express and SATA controller.

Signed-off-by: Dave Liu <daveliu@freescale.com>
---
 cpu/mpc83xx/cpu.c             | 12 +++++
 cpu/mpc83xx/speed.c           | 40 +++++++++++++--
 include/asm-ppc/global_data.h |  5 ++
 include/asm-ppc/immap_83xx.h  | 61 ++++++++++++++++++++++-
 include/mpc83xx.h             | 93 ++++++++++++++++++++++++++++++++---
 5 files changed, 201 insertions(+), 10 deletions(-)

diff --git a/cpu/mpc83xx/cpu.c b/cpu/mpc83xx/cpu.c
index 98236ef50..8d69d2290 100644
--- a/cpu/mpc83xx/cpu.c
+++ b/cpu/mpc83xx/cpu.c
@@ -153,6 +153,18 @@ int checkcpu(void)
 	case SPR_8313E_REV10:
 		puts("MPC8313E, ");
 		break;
+	case SPR_8315E_REV10:
+		puts("MPC8315E, ");
+		break;
+	case SPR_8315_REV10:
+		puts("MPC8315, ");
+		break;
+	case SPR_8314E_REV10:
+		puts("MPC8314E, ");
+		break;
+	case SPR_8314_REV10:
+		puts("MPC8314, ");
+		break;
 	case SPR_8379E_REV10:
 		puts("MPC8379E, ");
 		break;
diff --git a/cpu/mpc83xx/speed.c b/cpu/mpc83xx/speed.c
index 23dfb3041..4f5a86618 100644
--- a/cpu/mpc83xx/speed.c
+++ b/cpu/mpc83xx/speed.c
@@ -113,6 +113,9 @@ int get_clocks(void)
 #if !defined(CONFIG_MPC832X)
 	u32 i2c2_clk;
 #endif
+#if defined(CONFIG_MPC8315)
+	u32 tdm_clk;
+#endif
 #if defined(CONFIG_MPC837X)
 	u32 sdhc_clk;
 #endif
@@ -132,6 +135,8 @@ int get_clocks(void)
 #if defined(CONFIG_MPC837X)
 	u32 pciexp1_clk;
 	u32 pciexp2_clk;
+#endif
+#if defined(CONFIG_MPC837X) || defined(CONFIG_MPC8315)
 	u32 sata_clk;
 #endif
 
@@ -197,7 +202,7 @@ int get_clocks(void)
 	}
 #endif
 
-#if defined(CONFIG_MPC834X) || defined(CONFIG_MPC837X)
+#if defined(CONFIG_MPC834X) || defined(CONFIG_MPC837X) || defined(CONFIG_MPC8315)
 	switch ((sccr & SCCR_TSEC2CM) >> SCCR_TSEC2CM_SHIFT) {
 	case 0:
 		tsec2_clk = 0;
@@ -215,7 +220,7 @@ int get_clocks(void)
 		/* unkown SCCR_TSEC2CM value */
 		return -4;
 	}
-#elif defined(CONFIG_MPC831X)
+#elif defined(CONFIG_MPC8313)
 	tsec2_clk = tsec1_clk;
 
 	if (!(sccr & SCCR_TSEC1ON))
@@ -288,6 +293,25 @@ int get_clocks(void)
 		return -8;
 	}
 #endif
+#if defined(CONFIG_MPC8315)
+	switch ((sccr & SCCR_TDMCM) >> SCCR_TDMCM_SHIFT) {
+	case 0:
+		tdm_clk = 0;
+		break;
+	case 1:
+		tdm_clk = csb_clk;
+		break;
+	case 2:
+		tdm_clk = csb_clk / 2;
+		break;
+	case 3:
+		tdm_clk = csb_clk / 3;
+		break;
+	default:
+		/* unkown SCCR_TDMCM value */
+		return -8;
+	}
+#endif
 
 #if defined(CONFIG_MPC834X)
 	i2c1_clk = tsec2_clk;
@@ -342,7 +366,7 @@ int get_clocks(void)
 	}
 #endif
 
-#if defined(CONFIG_MPC837X)
+#if defined(CONFIG_MPC837X) || defined(CONFIG_MPC8315)
 	switch ((sccr & SCCR_SATA1CM) >> SCCR_SATA1CM_SHIFT) {
 	case 0:
 		sata_clk = 0;
@@ -428,6 +452,9 @@ int get_clocks(void)
 #if defined(CONFIG_MPC834X)
 	gd->usbmph_clk = usbmph_clk;
 #endif
+#if defined(CONFIG_MPC8315)
+	gd->tdm_clk = tdm_clk;
+#endif
 #if defined(CONFIG_MPC837X)
 	gd->sdhc_clk = sdhc_clk;
 #endif
@@ -450,6 +477,8 @@ int get_clocks(void)
 #if defined(CONFIG_MPC837X)
 	gd->pciexp1_clk = pciexp1_clk;
 	gd->pciexp2_clk = pciexp2_clk;
+#endif
+#if defined(CONFIG_MPC837X) || defined(CONFIG_MPC8315)
 	gd->sata_clk = sata_clk;
 #endif
 	gd->pci_clk = pci_sync_in;
@@ -488,6 +517,9 @@ int do_clocks (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
 #if !defined(CONFIG_MPC832X)
 	printf("  I2C2:                %4d MHz\n", gd->i2c2_clk / 1000000);
 #endif
+#if defined(CONFIG_MPC8315)
+	printf("  TDM:                 %4d MHz\n", gd->tdm_clk / 1000000);
+#endif
 #if defined(CONFIG_MPC837X)
 	printf("  SDHC:                %4d MHz\n", gd->sdhc_clk / 1000000);
 #endif
@@ -502,6 +534,8 @@ int do_clocks (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
 #if defined(CONFIG_MPC837X)
 	printf("  PCIEXP1:             %4d MHz\n", gd->pciexp1_clk / 1000000);
 	printf("  PCIEXP2:             %4d MHz\n", gd->pciexp2_clk / 1000000);
+#endif
+#if defined(CONFIG_MPC837X) || defined(CONFIG_MPC8315)
 	printf("  SATA:                %4d MHz\n", gd->sata_clk / 1000000);
 #endif
 	return 0;
diff --git a/include/asm-ppc/global_data.h b/include/asm-ppc/global_data.h
index 6ce072f66..91acf9b7c 100644
--- a/include/asm-ppc/global_data.h
+++ b/include/asm-ppc/global_data.h
@@ -63,6 +63,9 @@ typedef	struct	global_data {
 #if defined (CONFIG_MPC834X)
 	u32 usbmph_clk;
 #endif /* CONFIG_MPC834X */
+#if defined(CONFIG_MPC815)
+	u32 tdm_clk;
+#endif
 #if defined(CONFIG_MPC837X)
 	u32 sdhc_clk;
 #endif
@@ -77,6 +80,8 @@ typedef	struct	global_data {
 #if defined(CONFIG_MPC837X)
 	u32 pciexp1_clk;
 	u32 pciexp2_clk;
+#endif
+#if defined(CONFIG_MPC837X) || defined(CONFIG_MPC8315)
 	u32 sata_clk;
 #endif
 #if defined(CONFIG_MPC8360)
diff --git a/include/asm-ppc/immap_83xx.h b/include/asm-ppc/immap_83xx.h
index 75171115b..34ea29599 100644
--- a/include/asm-ppc/immap_83xx.h
+++ b/include/asm-ppc/immap_83xx.h
@@ -589,6 +589,20 @@ typedef struct rom83xx {
 	u8 mem[0x10000];
 } rom83xx_t;
 
+/*
+ * TDM
+ */
+typedef struct tdm83xx {
+	u8 fixme[0x200];
+} tdm83xx_t;
+
+/*
+ * TDM DMAC
+ */
+typedef struct tdmdmac83xx {
+	u8 fixme[0x2000];
+} tdmdmac83xx_t;
+
 #if defined(CONFIG_MPC834X)
 typedef struct immap {
 	sysconf83xx_t		sysconf;	/* System configuration */
@@ -626,7 +640,7 @@ typedef struct immap {
 	u8			res7[0xC0000];
 } immap_t;
 
-#elif defined(CONFIG_MPC831X)
+#elif defined(CONFIG_MPC8313)
 typedef struct immap {
 	sysconf83xx_t		sysconf;	/* System configuration */
 	wdt83xx_t		wdt;		/* Watch Dog Timer (WDT) Registers */
@@ -661,6 +675,51 @@ typedef struct immap {
 	u8			res7[0xC0000];
 } immap_t;
 
+#elif defined(CONFIG_MPC8315)
+typedef struct immap {
+	sysconf83xx_t		sysconf;	/* System configuration */
+	wdt83xx_t		wdt;		/* Watch Dog Timer (WDT) Registers */
+	rtclk83xx_t		rtc;		/* Real Time Clock Module Registers */
+	rtclk83xx_t		pit;		/* Periodic Interval Timer */
+	gtm83xx_t		gtm[2];		/* Global Timers Module */
+	ipic83xx_t		ipic;		/* Integrated Programmable Interrupt Controller */
+	arbiter83xx_t		arbiter;	/* System Arbiter Registers */
+	reset83xx_t		reset;		/* Reset Module */
+	clk83xx_t		clk;		/* System Clock Module */
+	pmc83xx_t		pmc;		/* Power Management Control Module */
+	gpio83xx_t		gpio[1];	/* General purpose I/O module */
+	u8			res0[0x1300];
+	ddr83xx_t		ddr;		/* DDR Memory Controller Memory */
+	fsl_i2c_t		i2c[2];		/* I2C Controllers */
+	u8			res1[0x1300];
+	duart83xx_t		duart[2];	/* DUART */
+	u8			res2[0x900];
+	lbus83xx_t		lbus;		/* Local Bus Controller Registers */
+	u8			res3[0x1000];
+	spi83xx_t		spi;		/* Serial Peripheral Interface */
+	dma83xx_t		dma;		/* DMA */
+	pciconf83xx_t		pci_conf[1];	/* PCI Software Configuration Registers */
+	u8			res4[0x80];
+	ios83xx_t		ios;		/* Sequencer */
+	pcictrl83xx_t		pci_ctrl[1];	/* PCI Controller Control and Status Registers */
+	u8			res5[0xa00];
+	pex83xx_t		pciexp[2];	/* PCI Express Controller */
+	u8			res6[0xb000];
+	tdm83xx_t		tdm;		/* TDM Controller */
+	u8			res7[0x1e00];
+	sata83xx_t		sata[2];	/* SATA Controller */
+	u8			res8[0x9000];
+	usb83xx_t		usb[1];		/* USB DR Controller */
+	tsec83xx_t		tsec[2];
+	u8			res9[0x6000];
+	tdmdmac83xx_t		tdmdmac;	/* TDM DMAC */
+	u8			res10[0x2000];
+	security83xx_t		security;
+	u8			res11[0xA3000];
+	serdes83xx_t		serdes[1];	/* SerDes Registers */
+	u8			res12[0x1CF00];
+} immap_t;
+
 #elif defined(CONFIG_MPC837X)
 typedef struct immap {
 	sysconf83xx_t		sysconf;	/* System configuration */
diff --git a/include/mpc83xx.h b/include/mpc83xx.h
index 4c230943c..dba1aea4f 100644
--- a/include/mpc83xx.h
+++ b/include/mpc83xx.h
@@ -102,6 +102,10 @@
 #define SPR_8313_REV10			0x80B10010
 #define SPR_8311E_REV10			0x80B20010
 #define SPR_8311_REV10			0x80B30010
+#define SPR_8315E_REV10			0x80B40010
+#define SPR_8315_REV10			0x80B50010
+#define SPR_8314E_REV10			0x80B60010
+#define SPR_8314_REV10			0x80B70010
 
 #define SPR_8379E_REV10			0x80C20010
 #define SPR_8379_REV10			0x80C30010
@@ -220,8 +224,8 @@
 #define SICRL_URT_CTPR			0x06000000
 #define SICRL_IRQ_CTPR			0x00C00000
 
-#elif defined(CONFIG_MPC831X)
-/* SICRL bits - MPC831x specific */
+#elif defined(CONFIG_MPC8313)
+/* SICRL bits - MPC8313 specific */
 #define SICRL_LBC			0x30000000
 #define SICRL_UART			0x0C000000
 #define SICRL_SPI_A			0x03000000
@@ -232,7 +236,7 @@
 #define SICRL_ETSEC1_A			0x0000000C
 #define SICRL_ETSEC2_A			0x00000003
 
-/* SICRH bits - MPC831x specific */
+/* SICRH bits - MPC8313 specific */
 #define SICRH_INTR_A			0x02000000
 #define SICRH_INTR_B			0x00C00000
 #define SICRH_IIC			0x00300000
@@ -249,6 +253,41 @@
 #define SICRH_TSOBI1			0x00000002
 #define SICRH_TSOBI2			0x00000001
 
+#elif defined(CONFIG_MPC8315)
+/* SICRL bits - MPC8315 specific */
+#define SICRL_DMA_CH0			0xc0000000
+#define SICRL_DMA_SPI			0x30000000
+#define SICRL_UART			0x0c000000
+#define SICRL_IRQ4			0x02000000
+#define SICRL_IRQ5			0x01800000
+#define SICRL_IRQ6_7			0x00400000
+#define SICRL_IIC1			0x00300000
+#define SICRL_TDM			0x000c0000
+#define SICRL_TDM_SHARED		0x00030000
+#define SICRL_PCI_A			0x0000c000
+#define SICRL_ELBC_A			0x00003000
+#define SICRL_ETSEC1_A			0x000000c0
+#define SICRL_ETSEC1_B			0x00000030
+#define SICRL_ETSEC1_C			0x0000000c
+#define SICRL_TSEXPOBI			0x00000001
+
+/* SICRH bits - MPC8315 specific */
+#define SICRH_GPIO_0			0xc0000000
+#define SICRH_GPIO_1			0x30000000
+#define SICRH_GPIO_2			0x0c000000
+#define SICRH_GPIO_3			0x03000000
+#define SICRH_GPIO_4			0x00c00000
+#define SICRH_GPIO_5			0x00300000
+#define SICRH_GPIO_6			0x000c0000
+#define SICRH_GPIO_7			0x00030000
+#define SICRH_GPIO_8			0x0000c000
+#define SICRH_GPIO_9			0x00003000
+#define SICRH_GPIO_10			0x00000c00
+#define SICRH_GPIO_11			0x00000300
+#define SICRH_ETSEC2_A			0x000000c0
+#define SICRH_TSOBI1			0x00000002
+#define SICRH_TSOBI2			0x00000001
+
 #elif defined(CONFIG_MPC837X)
 /* SICRL bits - MPC837x specific */
 #define SICRL_USB_A			0xC0000000
@@ -447,7 +486,7 @@
 #define HRCWL_CE_TO_PLL_1X30		0x0000001E
 #define HRCWL_CE_TO_PLL_1X31		0x0000001F
 
-#elif defined(CONFIG_MPC837X)
+#elif defined(CONFIG_MPC837X) || defined(CONFIG_MPC8315)
 #define HRCWL_SVCOD			0x30000000
 #define HRCWL_SVCOD_SHIFT		28
 #define HRCWL_SVCOD_DIV_4		0x00000000
@@ -556,7 +595,7 @@
 
 /* RSR - Reset Status Register
  */
-#if defined(CONFIG_MPC837X)
+#if defined(CONFIG_MPC831X) || defined(CONFIG_MPC837X)
 #define RSR_RSTSRC			0xF0000000	/* Reset source */
 #define RSR_RSTSRC_SHIFT		28
 #else
@@ -677,7 +716,7 @@
 #define SCCR_USBCM_2			0x00A00000
 #define SCCR_USBCM_3			0x00F00000
 
-#elif defined(CONFIG_MPC831X)
+#elif defined(CONFIG_MPC8313)
 /* TSEC1 bits are for TSEC2 as well */
 #define SCCR_TSEC1CM			0xc0000000
 #define SCCR_TSEC1CM_SHIFT		30
@@ -697,6 +736,48 @@
 #define SCCR_USBDRCM_2			0x00200000
 #define SCCR_USBDRCM_3			0x00300000
 
+#elif defined(CONFIG_MPC8315)
+/* SCCR bits - MPC8315 specific */
+#define SCCR_TSEC1CM			0xc0000000
+#define SCCR_TSEC1CM_SHIFT		30
+#define SCCR_TSEC1CM_0			0x00000000
+#define SCCR_TSEC1CM_1			0x40000000
+#define SCCR_TSEC1CM_2			0x80000000
+#define SCCR_TSEC1CM_3			0xC0000000
+
+#define SCCR_TSEC2CM			0x30000000
+#define SCCR_TSEC2CM_SHIFT		28
+#define SCCR_TSEC2CM_0			0x00000000
+#define SCCR_TSEC2CM_1			0x10000000
+#define SCCR_TSEC2CM_2			0x20000000
+#define SCCR_TSEC2CM_3			0x30000000
+
+#define SCCR_USBDRCM			0x00300000
+#define SCCR_USBDRCM_SHIFT		20
+#define SCCR_USBDRCM_0			0x00000000
+#define SCCR_USBDRCM_1			0x00100000
+#define SCCR_USBDRCM_2			0x00200000
+#define SCCR_USBDRCM_3			0x00300000
+
+#define SCCR_PCIEXP1CM			0x00080000
+#define SCCR_PCIEXP2CM			0x00040000
+
+#define SCCR_SATA1CM			0x0000c000
+#define SCCR_SATA1CM_SHIFT		14
+#define SCCR_SATACM			0x0000f000
+#define SCCR_SATACM_SHIFT		8
+#define SCCR_SATACM_0			0x00000000
+#define SCCR_SATACM_1			0x00005000
+#define SCCR_SATACM_2			0x0000a000
+#define SCCR_SATACM_3			0x0000f000
+
+#define SCCR_TDMCM			0x000000c0
+#define SCCR_TDMCM_SHIFT		6
+#define SCCR_TDMCM_0			0x00000000
+#define SCCR_TDMCM_1			0x00000040
+#define SCCR_TDMCM_2			0x00000080
+#define SCCR_TDMCM_3			0x000000c0
+
 #elif defined(CONFIG_MPC837X)
 /* SCCR bits - MPC837x specific */
 #define SCCR_TSEC1CM			0xc0000000

From 19580e660cc8da49f16536a8bd78c047c7bc12e5 Mon Sep 17 00:00:00 2001
From: Dave Liu <r63238@freescale.com>
Date: Tue, 18 Sep 2007 12:37:57 +0800
Subject: [PATCH 047/108] mpc83xx: Add the support of MPC837xEMDS board

The MPC837xEMDS board support:
* DDR2 400MHz hardcoded and SPD init
* Local bus NOR Flash
* I2C, UART, MII and RTC
* eTSEC RGMII
* PCI host

Signed-off-by: Dave Liu <daveliu@freescale.com>
---
 Makefile                                  |  10 +
 board/freescale/mpc837xemds/Makefile      |  50 ++
 board/freescale/mpc837xemds/config.mk     |  28 +
 board/freescale/mpc837xemds/mpc837xemds.c | 144 +++++
 board/freescale/mpc837xemds/pci.c         |  65 +++
 cpu/mpc83xx/cpu_init.c                    |   6 +-
 cpu/mpc83xx/spd_sdram.c                   |   7 +-
 drivers/net/tsec.c                        |  10 +
 include/configs/MPC837XEMDS.h             | 605 ++++++++++++++++++++++
 9 files changed, 922 insertions(+), 3 deletions(-)
 create mode 100644 board/freescale/mpc837xemds/Makefile
 create mode 100644 board/freescale/mpc837xemds/config.mk
 create mode 100644 board/freescale/mpc837xemds/mpc837xemds.c
 create mode 100644 board/freescale/mpc837xemds/pci.c
 create mode 100644 include/configs/MPC837XEMDS.h

diff --git a/Makefile b/Makefile
index 35e90315f..dd995d305 100644
--- a/Makefile
+++ b/Makefile
@@ -1922,6 +1922,16 @@ MPC8360EMDS_ATM_config: unconfig
 	fi ;
 	@$(MKCONFIG) -a MPC8360EMDS ppc mpc83xx mpc8360emds freescale
 
+MPC837XEMDS_config \
+MPC837XEMDS_HOST_config:	unconfig
+	@mkdir -p $(obj)include
+	@echo "" >$(obj)include/config.h ; \
+	if [ "$(findstring _HOST_,$@)" ] ; then \
+		echo -n "... PCI HOST " ; \
+		echo "#define CONFIG_PCI" >>$(obj)include/config.h ; \
+	fi ;
+	@$(MKCONFIG) -a MPC837XEMDS ppc mpc83xx mpc837xemds freescale
+
 sbc8349_config:		unconfig
 	@$(MKCONFIG) $(@:_config=) ppc mpc83xx sbc8349
 
diff --git a/board/freescale/mpc837xemds/Makefile b/board/freescale/mpc837xemds/Makefile
new file mode 100644
index 000000000..5ec7a871d
--- /dev/null
+++ b/board/freescale/mpc837xemds/Makefile
@@ -0,0 +1,50 @@
+#
+# (C) Copyright 2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).a
+
+COBJS	:= $(BOARD).o pci.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/freescale/mpc837xemds/config.mk b/board/freescale/mpc837xemds/config.mk
new file mode 100644
index 000000000..63c5fc3c3
--- /dev/null
+++ b/board/freescale/mpc837xemds/config.mk
@@ -0,0 +1,28 @@
+#
+# (C) Copyright 2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# MPC837xEMDS
+#
+
+TEXT_BASE = 0xFE000000
diff --git a/board/freescale/mpc837xemds/mpc837xemds.c b/board/freescale/mpc837xemds/mpc837xemds.c
new file mode 100644
index 000000000..0e4ec0213
--- /dev/null
+++ b/board/freescale/mpc837xemds/mpc837xemds.c
@@ -0,0 +1,144 @@
+/*
+ * Copyright (C) 2007 Freescale Semiconductor, Inc.
+ * Dave Liu <daveliu@freescale.com>
+ *
+ * CREDITS: Kim Phillips contribute to LIBFDT code
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <spd.h>
+#if defined(CONFIG_SPD_EEPROM)
+#include <spd_sdram.h>
+#endif
+#if defined(CONFIG_OF_FLAT_TREE)
+#include <ft_build.h>
+#elif defined(CONFIG_OF_LIBFDT)
+#include <libfdt.h>
+#endif
+#if defined(CONFIG_PQ_MDS_PIB)
+#include "../common/pq-mds-pib.h"
+#endif
+
+int board_early_init_f(void)
+{
+	u8 *bcsr = (u8 *)CFG_BCSR;
+
+	/* Enable flash write */
+	bcsr[0x9] &= ~0x04;
+	/* Clear all of the interrupt of BCSR */
+	bcsr[0xe] = 0xff;
+
+	return 0;
+}
+
+int board_early_init_r(void)
+{
+#ifdef CONFIG_PQ_MDS_PIB
+	pib_init();
+#endif
+	return 0;
+}
+
+#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC)
+extern void ddr_enable_ecc(unsigned int dram_size);
+#endif
+int fixed_sdram(void);
+
+long int initdram(int board_type)
+{
+	volatile immap_t *im = (immap_t *) CFG_IMMR;
+	u32 msize = 0;
+
+	if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
+		return -1;
+
+#if defined(CONFIG_SPD_EEPROM)
+	msize = spd_sdram();
+#else
+	msize = fixed_sdram();
+#endif
+
+#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC)
+	/* Initialize DDR ECC byte */
+	ddr_enable_ecc(msize * 1024 * 1024);
+#endif
+
+	/* return total bus DDR size(bytes) */
+	return (msize * 1024 * 1024);
+}
+
+#if !defined(CONFIG_SPD_EEPROM)
+/*************************************************************************
+ *  fixed sdram init -- doesn't use serial presence detect.
+ ************************************************************************/
+int fixed_sdram(void)
+{
+	volatile immap_t *im = (immap_t *) CFG_IMMR;
+	u32 msize = CFG_DDR_SIZE * 1024 * 1024;
+	u32 msize_log2 = __ilog2(msize);
+
+	im->sysconf.ddrlaw[0].bar = CFG_DDR_SDRAM_BASE >> 12;
+	im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1);
+
+#if (CFG_DDR_SIZE != 512)
+#warning Currenly any ddr size other than 512 is not supported
+#endif
+	im->sysconf.ddrcdr = CFG_DDRCDR_VALUE;
+	udelay(50000);
+
+	im->ddr.sdram_clk_cntl = CFG_DDR_SDRAM_CLK_CNTL;
+	udelay(1000);
+
+	im->ddr.csbnds[0].csbnds = CFG_DDR_CS0_BNDS;
+	im->ddr.cs_config[0] = CFG_DDR_CS0_CONFIG;
+	udelay(1000);
+
+	im->ddr.timing_cfg_0 = CFG_DDR_TIMING_0;
+	im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1;
+	im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2;
+	im->ddr.timing_cfg_3 = CFG_DDR_TIMING_3;
+	im->ddr.sdram_cfg = CFG_DDR_SDRAM_CFG;
+	im->ddr.sdram_cfg2 = CFG_DDR_SDRAM_CFG2;
+	im->ddr.sdram_mode = CFG_DDR_MODE;
+	im->ddr.sdram_mode2 = CFG_DDR_MODE2;
+	im->ddr.sdram_interval = CFG_DDR_INTERVAL;
+	__asm__ __volatile__("sync");
+	udelay(1000);
+
+	im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
+	udelay(2000);
+	return CFG_DDR_SIZE;
+}
+#endif /*!CFG_SPD_EEPROM */
+
+int checkboard(void)
+{
+	puts("Board: Freescale MPC837xEMDS\n");
+	return 0;
+}
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+void ft_board_setup(void *blob, bd_t *bd)
+{
+#if defined(CONFIG_OF_FLAT_TREE)
+	u32 *p;
+	int len;
+
+	p = ft_get_prop(blob, "/memory/reg", &len);
+	if (p != NULL) {
+		*p++ = cpu_to_be32(bd->bi_memstart);
+		*p = cpu_to_be32(bd->bi_memsize);
+	}
+#endif
+	ft_cpu_setup(blob, bd);
+#ifdef CONFIG_PCI
+	ft_pci_setup(blob, bd);
+#endif
+}
+#endif /* CONFIG_OF_BOARD_SETUP */
diff --git a/board/freescale/mpc837xemds/pci.c b/board/freescale/mpc837xemds/pci.c
new file mode 100644
index 000000000..ab909790e
--- /dev/null
+++ b/board/freescale/mpc837xemds/pci.c
@@ -0,0 +1,65 @@
+/*
+ * Copyright (C) 2007 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ */
+
+#include <asm/mmu.h>
+#include <asm/io.h>
+#include <common.h>
+#include <mpc83xx.h>
+#include <pci.h>
+#include <i2c.h>
+#include <asm/fsl_i2c.h>
+
+#if defined(CONFIG_PCI)
+static struct pci_region pci_regions[] = {
+	{
+		bus_start: CFG_PCI_MEM_BASE,
+		phys_start: CFG_PCI_MEM_PHYS,
+		size: CFG_PCI_MEM_SIZE,
+		flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
+	},
+	{
+		bus_start: CFG_PCI_MMIO_BASE,
+		phys_start: CFG_PCI_MMIO_PHYS,
+		size: CFG_PCI_MMIO_SIZE,
+		flags: PCI_REGION_MEM
+	},
+	{
+		bus_start: CFG_PCI_IO_BASE,
+		phys_start: CFG_PCI_IO_PHYS,
+		size: CFG_PCI_IO_SIZE,
+		flags: PCI_REGION_IO
+	}
+};
+
+void pci_init_board(void)
+{
+	volatile immap_t *immr = (volatile immap_t *)CFG_IMMR;
+	volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
+	volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
+	struct pci_region *reg[] = { pci_regions };
+
+	/* Enable all 5 PCI_CLK_OUTPUTS */
+	clk->occr |= 0xf8000000;
+	udelay(2000);
+
+	/* Configure PCI Local Access Windows */
+	pci_law[0].bar = CFG_PCI_MEM_PHYS & LAWBAR_BAR;
+	pci_law[0].ar = LBLAWAR_EN | LBLAWAR_512MB;
+
+	pci_law[1].bar = CFG_PCI_IO_PHYS & LAWBAR_BAR;
+	pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB;
+
+	udelay(2000);
+
+	mpc83xx_pci_init(1, reg, 0);
+}
+#endif /* CONFIG_PCI */
diff --git a/cpu/mpc83xx/cpu_init.c b/cpu/mpc83xx/cpu_init.c
index 722497966..2b92be01a 100644
--- a/cpu/mpc83xx/cpu_init.c
+++ b/cpu/mpc83xx/cpu_init.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2004-2006 Freescale Semiconductor, Inc.
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
  *
  * See file CREDITS for list of people who contributed to this
  * project.
@@ -155,6 +155,10 @@ void cpu_init_f (volatile immap_t * im)
 #ifdef CFG_DDRCDR
 	im->sysconf.ddrcdr = CFG_DDRCDR;
 #endif
+	/* Output buffer impedance register */
+#ifdef CFG_OBIR
+	im->sysconf.obir = CFG_OBIR;
+#endif
 
 #ifdef CONFIG_QE
 	/* Config QE ioports */
diff --git a/cpu/mpc83xx/spd_sdram.c b/cpu/mpc83xx/spd_sdram.c
index ee2d0385e..29dd47078 100644
--- a/cpu/mpc83xx/spd_sdram.c
+++ b/cpu/mpc83xx/spd_sdram.c
@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2006 Freescale Semiconductor, Inc.
+ * (C) Copyright 2006-2007 Freescale Semiconductor, Inc.
  *
  * (C) Copyright 2006
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
@@ -198,6 +198,7 @@ long int spd_sdram()
 	if(spd.mem_type == SPD_MEMTYPE_DDR2) {
 		immap->sysconf.ddrcdr = CFG_DDRCDR_VALUE;
 	}
+	udelay(50000);
 #endif
 
 	/*
@@ -576,7 +577,7 @@ long int spd_sdram()
 		if (effective_data_rate == 266 || effective_data_rate == 333) {
 			cpo = 0x7;		/* READ_LAT + 5/4 */
 		} else if (effective_data_rate == 400) {
-			cpo = 0x9;		/* READ_LAT + 7/4 */
+			cpo = 0x7;		/* READ_LAT + 5/4 */
 		} else {
 			/* Automatic calibration */
 			cpo = 0x1f;
@@ -705,9 +706,11 @@ long int spd_sdram()
 	 * SDRAM Cfg 2
 	 */
 	odt_cfg = 0;
+#ifndef CONFIG_NEVER_ASSERT_ODT_TO_CPU
 	if (odt_rd_cfg | odt_wr_cfg) {
 		odt_cfg = 0x2;		/* ODT to IOs during reads */
 	}
+#endif
 	if (spd.mem_type == SPD_MEMTYPE_DDR2) {
 		ddr->sdram_cfg2 = (0
 			    | (0 << 26)	/* True DQS */
diff --git a/drivers/net/tsec.c b/drivers/net/tsec.c
index ca6284b72..108cebd87 100644
--- a/drivers/net/tsec.c
+++ b/drivers/net/tsec.c
@@ -674,6 +674,15 @@ uint mii_cis8204_setmode(uint mii_reg, struct tsec_private * priv)
 		return MIIM_CIS8204_EPHYCON_INIT;
 }
 
+uint mii_m88e1111s_setmode(uint mii_reg, struct tsec_private *priv)
+{
+	uint mii_data = read_phy_reg(priv, mii_reg);
+
+	if (priv->flags & TSEC_REDUCED)
+		mii_data = (mii_data & 0xfff0) | 0x000b;
+	return mii_data;
+}
+
 /* Initialized required registers to appropriate values, zeroing
  * those we don't care about (unless zero is bad, in which case,
  * choose a more appropriate value)
@@ -1034,6 +1043,7 @@ struct phy_info phy_info_M88E1111S = {
 	(struct phy_cmd[]){	/* config */
 			   /* Reset and configure the PHY */
 			   {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
+			   {0x1b, 0x848f, &mii_m88e1111s_setmode},
 			   {0x14, 0x0cd2, NULL}, /* Delay RGMII TX and RX */
 			   {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL},
 			   {MIIM_ANAR, MIIM_ANAR_INIT, NULL},
diff --git a/include/configs/MPC837XEMDS.h b/include/configs/MPC837XEMDS.h
new file mode 100644
index 000000000..7e344925c
--- /dev/null
+++ b/include/configs/MPC837XEMDS.h
@@ -0,0 +1,605 @@
+/*
+ * Copyright (C) 2007 Freescale Semiconductor, Inc.
+ * Dave Liu <daveliu@freescale.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#undef DEBUG
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_E300		1 /* E300 family */
+#define CONFIG_MPC83XX		1 /* MPC83XX family */
+#define CONFIG_MPC837X		1 /* MPC837X CPU specific */
+#define CONFIG_MPC837XEMDS	1 /* MPC837XEMDS board specific */
+
+/*
+ * System Clock Setup
+ */
+#ifdef CONFIG_PCISLAVE
+#define CONFIG_83XX_PCICLK	66000000 /* in HZ */
+#else
+#define CONFIG_83XX_CLKIN	66000000 /* in Hz */
+#endif
+
+#ifndef CONFIG_SYS_CLK_FREQ
+#define CONFIG_SYS_CLK_FREQ	66000000
+#endif
+
+/*
+ * Hardware Reset Configuration Word
+ * if CLKIN is 66MHz, then
+ * CSB = 396MHz, CORE = 594MHz, DDRC = 396MHz, LBC = 396MHz
+ */
+#define CFG_HRCW_LOW (\
+	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
+	HRCWL_DDR_TO_SCB_CLK_1X1 |\
+	HRCWL_SVCOD_DIV_2 |\
+	HRCWL_CSB_TO_CLKIN_6X1 |\
+	HRCWL_CORE_TO_CSB_1_5X1)
+
+#ifdef CONFIG_PCISLAVE
+#define CFG_HRCW_HIGH (\
+	HRCWH_PCI_AGENT |\
+	HRCWH_PCI1_ARBITER_DISABLE |\
+	HRCWH_CORE_ENABLE |\
+	HRCWH_FROM_0XFFF00100 |\
+	HRCWH_BOOTSEQ_DISABLE |\
+	HRCWH_SW_WATCHDOG_DISABLE |\
+	HRCWH_ROM_LOC_LOCAL_16BIT |\
+	HRCWH_RL_EXT_LEGACY |\
+	HRCWH_TSEC1M_IN_RGMII |\
+	HRCWH_TSEC2M_IN_RGMII |\
+	HRCWH_BIG_ENDIAN |\
+	HRCWH_LDP_CLEAR)
+#else
+#define CFG_HRCW_HIGH (\
+	HRCWH_PCI_HOST |\
+	HRCWH_PCI1_ARBITER_ENABLE |\
+	HRCWH_CORE_ENABLE |\
+	HRCWH_FROM_0X00000100 |\
+	HRCWH_BOOTSEQ_DISABLE |\
+	HRCWH_SW_WATCHDOG_DISABLE |\
+	HRCWH_ROM_LOC_LOCAL_16BIT |\
+	HRCWH_RL_EXT_LEGACY |\
+	HRCWH_TSEC1M_IN_RGMII |\
+	HRCWH_TSEC2M_IN_RGMII |\
+	HRCWH_BIG_ENDIAN |\
+	HRCWH_LDP_CLEAR)
+#endif
+
+/*
+ * eTSEC Clock Config
+ */
+#define CFG_SCCR_TSEC1CM	1	/* CSB:eTSEC1 = 1:1 */
+#define CFG_SCCR_TSEC2CM	1	/* CSB:eTSEC2 = 1:1 */
+
+/*
+ * System IO Config
+ */
+#define CFG_SICRH		0x00000000
+#define CFG_SICRL		0x00000000
+
+/*
+ * Output Buffer Impedance
+ */
+#define CFG_OBIR		0x31100000
+
+#define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */
+#define CONFIG_BOARD_EARLY_INIT_R
+
+/*
+ * IMMR new address
+ */
+#define CFG_IMMR		0xE0000000
+
+/*
+ * DDR Setup
+ */
+#define CFG_DDR_BASE		0x00000000 /* DDR is system memory */
+#define CFG_SDRAM_BASE		CFG_DDR_BASE
+#define CFG_DDR_SDRAM_BASE	CFG_DDR_BASE
+#define CFG_DDR_SDRAM_CLK_CNTL	DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
+#define CFG_83XX_DDR_USES_CS0
+#define CFG_DDRCDR_VALUE	0x80080001 /* ODT 150ohm on SoC */
+
+#undef CONFIG_DDR_ECC		/* support DDR ECC function */
+#undef CONFIG_DDR_ECC_CMD	/* Use DDR ECC user commands */
+
+#define CONFIG_SPD_EEPROM	/* Use SPD EEPROM for DDR setup */
+#define CONFIG_NEVER_ASSERT_ODT_TO_CPU /* Never assert ODT to internal IOs */
+
+#if defined(CONFIG_SPD_EEPROM)
+#define SPD_EEPROM_ADDRESS	0x51 /* I2C address of DDR SODIMM SPD */
+#else
+/*
+ * Manually set up DDR parameters
+ * WHITE ELECTRONIC DESGGNS - W3HG64M72EEU403PD4 SO-DIMM
+ * consist of nine chips from SAMSUNG K4T51083QE-ZC(L)D5
+ */
+#define CFG_DDR_SIZE		512 /* MB */
+#define CFG_DDR_CS0_BNDS	0x0000001f
+#define CFG_DDR_CS0_CONFIG	( CSCONFIG_EN \
+				| 0x00010000  /* ODT_WR to CSn */ \
+				| CSCONFIG_ROW_BIT_14 | CSCONFIG_COL_BIT_10 )
+				/* 0x80010202 */
+#define CFG_DDR_TIMING_3	0x00000000
+#define CFG_DDR_TIMING_0	( ( 0 << TIMING_CFG0_RWT_SHIFT ) \
+				| ( 0 << TIMING_CFG0_WRT_SHIFT ) \
+				| ( 0 << TIMING_CFG0_RRT_SHIFT ) \
+				| ( 0 << TIMING_CFG0_WWT_SHIFT ) \
+				| ( 6 << TIMING_CFG0_ACT_PD_EXIT_SHIFT ) \
+				| ( 2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT ) \
+				| ( 8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT ) \
+				| ( 2 << TIMING_CFG0_MRS_CYC_SHIFT ) )
+				/* 0x00620802 */
+#define CFG_DDR_TIMING_1	( ( 3 << TIMING_CFG1_PRETOACT_SHIFT ) \
+				| ( 9 << TIMING_CFG1_ACTTOPRE_SHIFT ) \
+				| ( 3 << TIMING_CFG1_ACTTORW_SHIFT ) \
+				| ( 5 << TIMING_CFG1_CASLAT_SHIFT ) \
+				| (13 << TIMING_CFG1_REFREC_SHIFT ) \
+				| ( 3 << TIMING_CFG1_WRREC_SHIFT ) \
+				| ( 2 << TIMING_CFG1_ACTTOACT_SHIFT ) \
+				| ( 2 << TIMING_CFG1_WRTORD_SHIFT ) )
+				/* 0x3935d322 */
+#define CFG_DDR_TIMING_2	( ( 2 << TIMING_CFG2_ADD_LAT_SHIFT ) \
+				| ( 6 << TIMING_CFG2_CPO_SHIFT ) \
+				| ( 2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT ) \
+				| ( 4 << TIMING_CFG2_RD_TO_PRE_SHIFT ) \
+				| ( 2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT ) \
+				| ( 3 << TIMING_CFG2_CKE_PLS_SHIFT ) \
+				| ( 8 << TIMING_CFG2_FOUR_ACT_SHIFT) )
+				/* 0x231088c8 */
+#define CFG_DDR_INTERVAL	( ( 0x03E0 << SDRAM_INTERVAL_REFINT_SHIFT ) \
+				| ( 0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT ) )
+				/* 0x03E00100 */
+#define CFG_DDR_SDRAM_CFG	0x43000000
+#define CFG_DDR_SDRAM_CFG2	0x00001000 /* 1 posted refresh */
+#define CFG_DDR_MODE		( ( 0x0450 << SDRAM_MODE_ESD_SHIFT ) \
+				| ( 0x1432 << SDRAM_MODE_SD_SHIFT ) )
+				/* ODT 150ohm CL=3, AL=2 on SDRAM */
+#define CFG_DDR_MODE2		0x00000000
+#endif
+
+/*
+ * Memory test
+ */
+#undef CFG_DRAM_TEST		/* memory test, takes time */
+#define CFG_MEMTEST_START	0x00040000 /* memtest region */
+#define CFG_MEMTEST_END		0x00140000
+
+/*
+ * The reserved memory
+ */
+#define CFG_MONITOR_BASE	TEXT_BASE /* start of monitor */
+
+#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
+#define CFG_RAMBOOT
+#else
+#undef CFG_RAMBOOT
+#endif
+
+#define CFG_MONITOR_LEN		(256 * 1024) /* Reserve 256 kB for Mon */
+#define CFG_MALLOC_LEN		(512 * 1024) /* Reserved for malloc */
+
+/*
+ * Initial RAM Base Address Setup
+ */
+#define CFG_INIT_RAM_LOCK	1
+#define CFG_INIT_RAM_ADDR	0xE6000000 /* Initial RAM address */
+#define CFG_INIT_RAM_END	0x1000 /* End of used area in RAM */
+#define CFG_GBL_DATA_SIZE	0x100 /* num bytes initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+
+/*
+ * Local Bus Configuration & Clock Setup
+ */
+#define CFG_LCRR		(LCRR_DBYP | LCRR_CLKDIV_8)
+#define CFG_LBC_LBCR		0x00000000
+
+/*
+ * FLASH on the Local Bus
+ */
+#define CFG_FLASH_CFI		/* use the Common Flash Interface */
+#define CFG_FLASH_CFI_DRIVER	/* use the CFI driver */
+#define CFG_FLASH_BASE		0xFE000000 /* FLASH base address */
+#define CFG_FLASH_SIZE		32 /* max FLASH size is 32M */
+
+#define CFG_LBLAWBAR0_PRELIM	CFG_FLASH_BASE /* Window base at flash base */
+#define CFG_LBLAWAR0_PRELIM	0x80000018 /* 32MB window size */
+
+#define CFG_BR0_PRELIM		(CFG_FLASH_BASE | /* Flash Base address */ \
+				(2 << BR_PS_SHIFT) | /* 16 bit port size */ \
+				BR_V) /* valid */
+#define CFG_OR0_PRELIM		((~(CFG_FLASH_SIZE - 1) << 20) | OR_UPM_XAM | \
+				OR_GPCM_CSNT | OR_GPCM_ACS_0b11 | OR_GPCM_XACS | OR_GPCM_SCY_15 | \
+				OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD)
+
+#define CFG_MAX_FLASH_BANKS	1 /* number of banks */
+#define CFG_MAX_FLASH_SECT	256 /* max sectors per device */
+
+#undef CFG_FLASH_CHECKSUM
+#define CFG_FLASH_ERASE_TOUT	60000 /* Flash Erase Timeout (ms) */
+#define CFG_FLASH_WRITE_TOUT	500 /* Flash Write Timeout (ms) */
+
+/*
+ * BCSR on the Local Bus
+ */
+#define CFG_BCSR		0xF8000000
+#define CFG_LBLAWBAR1_PRELIM	CFG_BCSR /* Access window base at BCSR base */
+#define CFG_LBLAWAR1_PRELIM	0x8000000E /* Access window size 32K */
+
+#define CFG_BR1_PRELIM		(CFG_BCSR | 0x00000801) /* Port size=8bit, MSEL=GPCM */
+#define CFG_OR1_PRELIM		0xFFFFE9f7 /* length 32K */
+
+/*
+ * NAND Flash on the Local Bus
+ */
+#define CFG_NAND_BASE		0xE0600000	/* 0xE0600000 */
+#define CFG_BR3_PRELIM		( CFG_NAND_BASE \
+				| (2<<BR_DECC_SHIFT)	/* Use HW ECC */ \
+				| BR_PS_8		/* Port Size = 8 bit */ \
+				| BR_MS_FCM		/* MSEL = FCM */ \
+				| BR_V )		/* valid */
+#define CFG_OR3_PRELIM		( 0xFFFF8000		/* length 32K */ \
+				| OR_FCM_CSCT \
+				| OR_FCM_CST \
+				| OR_FCM_CHT \
+				| OR_FCM_SCY_1 \
+				| OR_FCM_TRLX \
+				| OR_FCM_EHTR )
+				/* 0xFFFF8396 */
+
+#define CFG_LBLAWBAR3_PRELIM	CFG_NAND_BASE
+#define CFG_LBLAWAR3_PRELIM	0x8000000E	/* 32KB  */
+
+/*
+ * Serial Port
+ */
+#define CONFIG_CONS_INDEX	1
+#undef CONFIG_SERIAL_SOFTWARE_FIFO
+#define CFG_NS16550
+#define CFG_NS16550_SERIAL
+#define CFG_NS16550_REG_SIZE	1
+#define CFG_NS16550_CLK		get_bus_freq(0)
+
+#define CFG_BAUDRATE_TABLE  \
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
+
+#define CFG_NS16550_COM1	(CFG_IMMR+0x4500)
+#define CFG_NS16550_COM2	(CFG_IMMR+0x4600)
+
+/* Use the HUSH parser */
+#define CFG_HUSH_PARSER
+#ifdef CFG_HUSH_PARSER
+#define CFG_PROMPT_HUSH_PS2 "> "
+#endif
+
+/* Pass open firmware flat tree */
+#define CONFIG_OF_LIBFDT	1
+#define CONFIG_OF_BOARD_SETUP	1
+#define CONFIG_OF_HAS_BD_T	1
+#define CONFIG_OF_HAS_UBOOT_ENV	1
+
+#define OF_CPU			"PowerPC,837x@0"
+#define OF_SOC			"soc837x@e0000000"
+#define OF_TBCLK		(bd->bi_busfreq / 4)
+#define OF_STDOUT_PATH		"/soc837x@e0000000/serial@4500"
+
+/* I2C */
+#define CONFIG_HARD_I2C		/* I2C with hardware support */
+#undef CONFIG_SOFT_I2C		/* I2C bit-banged */
+#define CONFIG_FSL_I2C
+#define CFG_I2C_SPEED		400000 /* I2C speed and slave address */
+#define CFG_I2C_SLAVE		0x7F
+#define CFG_I2C_NOPROBES	{0x51} /* Don't probe these addrs */
+#define CFG_I2C_OFFSET		0x3000
+#define CFG_I2C2_OFFSET		0x3100
+
+/*
+ * Config on-board RTC
+ */
+#define CONFIG_RTC_DS1374	/* use ds1374 rtc via i2c */
+#define CFG_I2C_RTC_ADDR	0x68 /* at address 0x68 */
+
+/*
+ * General PCI
+ * Addresses are mapped 1-1.
+ */
+#define CFG_PCI_MEM_BASE	0x80000000
+#define CFG_PCI_MEM_PHYS	CFG_PCI_MEM_BASE
+#define CFG_PCI_MEM_SIZE	0x10000000 /* 256M */
+#define CFG_PCI_MMIO_BASE	0x90000000
+#define CFG_PCI_MMIO_PHYS	CFG_PCI_MMIO_BASE
+#define CFG_PCI_MMIO_SIZE	0x10000000 /* 256M */
+#define CFG_PCI_IO_BASE		0xE0300000
+#define CFG_PCI_IO_PHYS		0xE0300000
+#define CFG_PCI_IO_SIZE		0x100000 /* 1M */
+
+#define CFG_PCI_SLV_MEM_LOCAL	CFG_SDRAM_BASE
+#define CFG_PCI_SLV_MEM_BUS	0x00000000
+#define CFG_PCI_SLV_MEM_SIZE	0x80000000
+
+#ifdef CONFIG_PCI
+#define CONFIG_83XX_GENERIC_PCI	1 /* Use generic PCI setup */
+#define CONFIG_PQ_MDS_PIB	1 /* PQ MDS Platform IO Board */
+
+#define CONFIG_NET_MULTI
+#define CONFIG_PCI_PNP		/* do pci plug-and-play */
+
+#undef CONFIG_EEPRO100
+#undef CONFIG_PCI_SCAN_SHOW	/* show pci devices on startup */
+#define CFG_PCI_SUBSYS_VENDORID 0x1957	/* Freescale */
+#endif /* CONFIG_PCI */
+
+#ifndef CONFIG_NET_MULTI
+#define CONFIG_NET_MULTI	1
+#endif
+
+/*
+ * TSEC
+ */
+#define CONFIG_TSEC_ENET	/* TSEC ethernet support */
+#define CFG_TSEC1_OFFSET	0x24000
+#define CFG_TSEC1		(CFG_IMMR+CFG_TSEC1_OFFSET)
+#define CFG_TSEC2_OFFSET	0x25000
+#define CFG_TSEC2		(CFG_IMMR+CFG_TSEC2_OFFSET)
+
+/*
+ * TSEC ethernet configuration
+ */
+#define CONFIG_MII		1 /* MII PHY management */
+#define CONFIG_TSEC1		1
+#define CONFIG_TSEC1_NAME	"eTSEC0"
+#define CONFIG_TSEC2		1
+#define CONFIG_TSEC2_NAME	"eTSEC1"
+#define TSEC1_PHY_ADDR		2
+#define TSEC2_PHY_ADDR		3
+#define TSEC1_PHYIDX		0
+#define TSEC2_PHYIDX		0
+#define TSEC1_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
+#define TSEC2_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
+
+/* Options are: TSEC[0-1] */
+#define CONFIG_ETHPRIME		"eTSEC1"
+
+/*
+ * Environment
+ */
+#ifndef CFG_RAMBOOT
+	#define CFG_ENV_IS_IN_FLASH	1
+	#define CFG_ENV_ADDR		(CFG_MONITOR_BASE + 0x40000)
+	#define CFG_ENV_SECT_SIZE	0x20000 /* 128K(one sector) for env */
+	#define CFG_ENV_SIZE		0x2000
+#else
+	#define CFG_NO_FLASH		1	/* Flash is not usable now */
+	#define CFG_ENV_IS_NOWHERE	1	/* Store ENV in memory only */
+	#define CFG_ENV_ADDR		(CFG_MONITOR_BASE - 0x1000)
+	#define CFG_ENV_SIZE		0x2000
+#endif
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
+#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_DATE
+
+#if defined(CONFIG_PCI)
+    #define CONFIG_CMD_PCI
+#endif
+
+#if defined(CFG_RAMBOOT)
+    #undef CONFIG_CMD_ENV
+    #undef CONFIG_CMD_LOADS
+#endif
+
+#define CONFIG_CMDLINE_EDITING	1	/* add command line history */
+
+#undef CONFIG_WATCHDOG		/* watchdog disabled */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP		/* undef to save memory */
+#define CFG_LOAD_ADDR		0x2000000 /* default load address */
+#define CFG_PROMPT		"=> "	/* Monitor Command Prompt */
+
+#if defined(CONFIG_CMD_KGDB)
+	#define CFG_CBSIZE	1024 /* Console I/O Buffer Size */
+#else
+	#define CFG_CBSIZE	256 /* Console I/O Buffer Size */
+#endif
+
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS	16		/* max number of command args */
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size */
+#define CFG_HZ		1000		/* decrementer freq: 1ms ticks */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ		(8 << 20) /* Initial Memory map for Linux */
+
+/*
+ * Core HID Setup
+ */
+#define CFG_HID0_INIT		0x000000000
+#define CFG_HID0_FINAL		HID0_ENABLE_MACHINE_CHECK
+#define CFG_HID2		HID2_HBE
+
+/*
+ * Cache Config
+ */
+#define CFG_DCACHE_SIZE		32768
+#define CFG_CACHELINE_SIZE	32
+#if defined(CONFIG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT	5 /*log base 2 of the above value */
+#endif
+
+/*
+ * MMU Setup
+ */
+
+/* DDR: cache cacheable */
+#define CFG_SDRAM_LOWER		CFG_SDRAM_BASE
+#define CFG_SDRAM_UPPER		(CFG_SDRAM_BASE + 0x10000000)
+
+#define CFG_IBAT0L	(CFG_SDRAM_LOWER | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CFG_IBAT0U	(CFG_SDRAM_LOWER | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CFG_DBAT0L	CFG_IBAT0L
+#define CFG_DBAT0U	CFG_IBAT0U
+
+#define CFG_IBAT1L	(CFG_SDRAM_UPPER | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CFG_IBAT1U	(CFG_SDRAM_UPPER | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CFG_DBAT1L	CFG_IBAT1L
+#define CFG_DBAT1U	CFG_IBAT1U
+
+/* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */
+#define CFG_IBAT2L	(CFG_IMMR | BATL_PP_10 | \
+			BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CFG_IBAT2U	(CFG_IMMR | BATU_BL_8M | BATU_VS | BATU_VP)
+#define CFG_DBAT2L	CFG_IBAT2L
+#define CFG_DBAT2U	CFG_IBAT2U
+
+/* BCSR: cache-inhibit and guarded */
+#define CFG_IBAT3L	(CFG_BCSR | BATL_PP_10 | \
+			BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CFG_IBAT3U	(CFG_BCSR | BATU_BL_128K | BATU_VS | BATU_VP)
+#define CFG_DBAT3L	CFG_IBAT3L
+#define CFG_DBAT3U	CFG_IBAT3U
+
+/* FLASH: icache cacheable, but dcache-inhibit and guarded */
+#define CFG_IBAT4L	(CFG_FLASH_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CFG_IBAT4U	(CFG_FLASH_BASE | BATU_BL_32M | BATU_VS | BATU_VP)
+#define CFG_DBAT4L	(CFG_FLASH_BASE | BATL_PP_10 | \
+			BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CFG_DBAT4U	CFG_IBAT4U
+
+/* Stack in dcache: cacheable, no memory coherence */
+#define CFG_IBAT5L	(CFG_INIT_RAM_ADDR | BATL_PP_10)
+#define CFG_IBAT5U	(CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
+#define CFG_DBAT5L	CFG_IBAT5L
+#define CFG_DBAT5U	CFG_IBAT5U
+
+#ifdef CONFIG_PCI
+/* PCI MEM space: cacheable */
+#define CFG_IBAT6L	(CFG_PCI_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CFG_IBAT6U	(CFG_PCI_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CFG_DBAT6L	CFG_IBAT6L
+#define CFG_DBAT6U	CFG_IBAT6U
+/* PCI MMIO space: cache-inhibit and guarded */
+#define CFG_IBAT7L	(CFG_PCI_MMIO_PHYS | BATL_PP_10 | \
+			BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CFG_IBAT7U	(CFG_PCI_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CFG_DBAT7L	CFG_IBAT7L
+#define CFG_DBAT7U	CFG_IBAT7U
+#else
+#define CFG_IBAT6L	(0)
+#define CFG_IBAT6U	(0)
+#define CFG_IBAT7L	(0)
+#define CFG_IBAT7U	(0)
+#define CFG_DBAT6L	CFG_IBAT6L
+#define CFG_DBAT6U	CFG_IBAT6U
+#define CFG_DBAT7L	CFG_IBAT7L
+#define CFG_DBAT7U	CFG_IBAT7U
+#endif
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD	0x01 /* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM	0x02 /* Software reboot */
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE	230400	/* speed of kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
+#endif
+
+/*
+ * Environment Configuration
+ */
+
+#define CONFIG_ENV_OVERWRITE
+
+#if defined(CONFIG_TSEC_ENET)
+#define CONFIG_HAS_ETH0
+#define CONFIG_ETHADDR		00:E0:0C:00:83:79
+#define CONFIG_HAS_ETH1
+#define CONFIG_ETH1ADDR		00:E0:0C:00:83:78
+#endif
+
+#define CONFIG_BAUDRATE 115200
+
+#define CONFIG_LOADADDR 200000	/* default location for tftp and bootm */
+
+#define CONFIG_BOOTDELAY 6	/* -1 disables auto-boot */
+#undef CONFIG_BOOTARGS		/* the boot command will set bootargs */
+
+#define CONFIG_EXTRA_ENV_SETTINGS					\
+   "netdev=eth0\0"							\
+   "consoledev=ttyS0\0"							\
+   "ramdiskaddr=1000000\0"						\
+   "ramdiskfile=ramfs.83xx\0"						\
+   "fdtaddr=400000\0"							\
+   "fdtfile=mpc837xemds.dtb\0"						\
+   ""
+
+#define CONFIG_NFSBOOTCOMMAND						\
+   "setenv bootargs root=/dev/nfs rw "					\
+      "nfsroot=$serverip:$rootpath "					\
+      "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
+      "console=$consoledev,$baudrate $othbootargs;"			\
+   "tftp $loadaddr $bootfile;"						\
+   "tftp $fdtaddr $fdtfile;"						\
+   "bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_RAMBOOTCOMMAND						\
+   "setenv bootargs root=/dev/ram rw "					\
+      "console=$consoledev,$baudrate $othbootargs;"			\
+   "tftp $ramdiskaddr $ramdiskfile;"					\
+   "tftp $loadaddr $bootfile;"						\
+   "tftp $fdtaddr $fdtfile;"						\
+   "bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+
+#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
+
+#endif	/* __CONFIG_H */

From f8900ce9094c462355eb792eea264ff16ac8fd16 Mon Sep 17 00:00:00 2001
From: Dave Liu <r63238@freescale.com>
Date: Tue, 18 Sep 2007 12:38:53 +0800
Subject: [PATCH 048/108] mpc83xx: Add the MPC837xEMDS board readme

Add the README.mpc837xemds to /doc

Signed-off-by: Dave Liu <daveliu@freescale.com>
---
 doc/README.mpc837xemds | 104 +++++++++++++++++++++++++++++++++++++++++
 1 file changed, 104 insertions(+)
 create mode 100644 doc/README.mpc837xemds

diff --git a/doc/README.mpc837xemds b/doc/README.mpc837xemds
new file mode 100644
index 000000000..3f0cdf7db
--- /dev/null
+++ b/doc/README.mpc837xemds
@@ -0,0 +1,104 @@
+Freescale MPC837xEMDS Board
+-----------------------------------------
+1.	Board Switches and Jumpers
+1.0 	There are four Dual-In-Line Packages(DIP) Switches on MPC837xEMDS board
+	For some reason, the HW designers describe the switch settings
+	in terms of 0 and 1, and then map that to physical switches where
+	the label "On" refers to logic 0 and "Off" is logic 1.
+
+	Switch bits are numbered 1 through, like, 4 6 8 or 10, but the
+	bits may contribute to signals that are numbered based at 0,
+	and some of those signals may be high-bit-number-0 too.  Heed
+	well the names and labels and do not get confused.
+
+		"Off" == 1
+		"On"  == 0
+
+	SW4[8] is the bit labled 8 on Switch 4.
+	SW2[1:6] refers to bits labeled 1 through 6 in order on switch 2.
+	SW2[1:8]= 0000_0001 refers to bits labeled 1 through 7 is set as "On"
+		and bits labeled 8 is set as "Off".
+
+1.1	For the MPC837xEMDS Processor Board
+
+	First, make sure the board default setting is consistent with the
+	document shipped with your board. Then apply the following setting:
+	SW3[1-8]= 0011_0000  (BOOTSEQ, ROMLOC setting)
+	SW4[1-8]= 0000_0110  (core PLL setting)
+	SW5[1-8]= 1001_1000  (system PLL, boot up from low end of flash)
+	SW6[1-8]= 0000_1000  (HRCW is read from NOR FLASH)
+	SW7[1-8]= 0110_1101  (TSEC1/2 interface setting - RGMII)
+	J3 2-3, TSEC1 LVDD1 with 2.5V
+	J6 2-3, TSEC2 LVDD2 with 2.5V
+	J9 2-3, CLKIN from osc on board
+	J10 removed, CS0 connect to NOR flash; when mounted, CS0 connect to NAND
+	J11 removed, Hardware Reset Configuration Word load from FLASH(NOR or NAND)
+	    mounted, HRCW load from BCSR.
+
+	on board Oscillator: 66M
+
+2.	Memory Map
+
+2.1.	The memory map should look pretty much like this:
+
+	0x0000_0000	0x7fff_ffff	DDR			2G
+	0x8000_0000	0x8fff_ffff	PCI MEM prefetch	256M
+	0x9000_0000	0x9fff_ffff	PCI MEM non-prefetch	256M
+	0xc000_0000	0xdfff_ffff	Empty			512M
+	0xe000_0000	0xe00f_ffff	Int Mem Reg Space	1M
+	0xe010_0000	0xe02f_ffff	Empty			2M
+	0xe030_0000	0xe03f_ffff	PCI IO			1M
+	0xe040_0000	0xe05f_ffff	Empty			2M
+	0xe060_0000	0xe060_8000	NAND Flash		32K
+	0xf400_0000	0xf7ff_ffff	Empty			64M
+	0xf800_0000	0xf800_7fff	BCSR on CS1		32K
+	0xfe00_0000	0xffff_ffff	NOR Flash on CS0	32M
+
+3. Definitions
+
+3.1 Explanation of NEW definitions in:
+
+	include/configs/MPC837XEMDS.h
+
+    CONFIG_MPC83XX	    MPC83xx family for both MPC837x and MPC8360
+    CONFIG_MPC837X	    MPC837x specific
+    CONFIG_MPC837XEMDS	    MPC837XEMDS board specific
+
+4. Compilation
+
+	Assuming you're using BASH shell:
+
+		export CROSS_COMPILE=your-cross-compile-prefix
+		cd u-boot
+		make distclean
+		make MPC837XEMDS_config
+		make
+
+5. Downloading and Flashing Images
+
+5.0 Download over serial line using Kermit:
+
+	loadb
+	[Drop to kermit:
+	    ^\c
+	    send <u-boot-bin-image>
+	    c
+	]
+
+
+    Or via tftp:
+
+	tftp 40000 u-boot.bin
+
+5.1 Reflash U-boot Image using U-boot
+
+	tftp 40000 u-boot.bin
+	protect off fe000000 fe1fffff
+	erase fe000000 fe1fffff
+
+	cp.b 40000 fe000000 xxxx
+
+You have to supply the correct byte count with 'xxxx' from the TFTP result log.
+
+6. Notes
+	1) The console baudrate for MPC837XEMDS is 115200bps.

From b21add4b42af7b767448251b599b91066a160e0d Mon Sep 17 00:00:00 2001
From: Dave Liu <r63238@freescale.com>
Date: Tue, 18 Sep 2007 12:40:21 +0800
Subject: [PATCH 049/108] mpc83xx: add MAINTAINER and MAKEALL entries for the
 mpc837xemds

Add the MAINTAINER and MAKEALL entries for mpc837xemds

Signed-off-by: Dave Liu <daveliu@freescale.com>
---
 MAINTAINERS | 1 +
 MAKEALL     | 1 +
 2 files changed, 2 insertions(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index fa0e9ea2d..1e551ed9e 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -228,6 +228,7 @@ The LEOX team <team@leox.org>
 Dave Liu <daveliu@freescale.com>
 
 	MPC8360EMDS		MPC8360
+	MPC837XEMDS		MPC837x
 
 Nye Liu <nyet@zumanetworks.com>
 
diff --git a/MAKEALL b/MAKEALL
index 4cbddc2a7..47f329629 100755
--- a/MAKEALL
+++ b/MAKEALL
@@ -313,6 +313,7 @@ LIST_83xx="		\
 	MPC8349ITXGP	\
 	MPC8360EMDS	\
 	MPC8360EMDS_ATM	\
+	MPC837XEMDS	\
 	sbc8349		\
 	TQM834x		\
 "

From 22b448dbfbe2a98f01ff4adc3c3979f8c541ad7b Mon Sep 17 00:00:00 2001
From: Dave Liu <r63238@freescale.com>
Date: Tue, 18 Sep 2007 12:41:15 +0800
Subject: [PATCH 050/108] mpc83xx: update the CREDITS and MAINTAINERS

update the CREDITS and MAINTAINERS.

Signed-off-by: Dave Liu <daveliu@freescale.com>
---
 CREDITS     | 5 +++++
 MAINTAINERS | 1 +
 2 files changed, 6 insertions(+)

diff --git a/CREDITS b/CREDITS
index 13150aec6..1130c9ec1 100644
--- a/CREDITS
+++ b/CREDITS
@@ -303,6 +303,11 @@ D: Support for Nios Stratix Development Kit (DK-1S10)
 D: Support for SSV ADNP/ESC1 (Nios Cyclone)
 W: http://www.li-pro.net
 
+N: Dave Liu
+E: daveliu@freescale.com
+D: Support for MPC832x, MPC8360, MPC837x
+W: www.freescale.com
+
 N: Raymond Lo
 E: lo@routefree.com
 D: Support for DOS partitions
diff --git a/MAINTAINERS b/MAINTAINERS
index 1e551ed9e..43b3b7959 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -227,6 +227,7 @@ The LEOX team <team@leox.org>
 
 Dave Liu <daveliu@freescale.com>
 
+	MPC832XEMDS		MPC832x
 	MPC8360EMDS		MPC8360
 	MPC837XEMDS		MPC837x
 

From 24f868433b50ecbaa88e118aadc7bd254013c6ae Mon Sep 17 00:00:00 2001
From: Kim Phillips <kim.phillips@freescale.com>
Date: Fri, 9 Nov 2007 14:28:08 -0600
Subject: [PATCH 051/108] mpc83xx: mpc8360 rev.2.1 erratum 2: replace rgmii-id
 with rgmii-rxid

u-boot itself uses GMII mode on the 8360.  Fix up UCC phy-connection-type
properties in the device tree so the PHY gets configured for internal delay on
RX only by the OS, as prescribed by mpc8360 rev. 2.1 pb mds erratum #2.

Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
---
 board/freescale/mpc8360emds/mpc8360emds.c | 31 +++++++++++++++++++++++
 1 file changed, 31 insertions(+)

diff --git a/board/freescale/mpc8360emds/mpc8360emds.c b/board/freescale/mpc8360emds/mpc8360emds.c
index 538a556c6..ff9a85cc4 100644
--- a/board/freescale/mpc8360emds/mpc8360emds.c
+++ b/board/freescale/mpc8360emds/mpc8360emds.c
@@ -303,6 +303,7 @@ void sdram_init(void)
 #if defined(CONFIG_OF_BOARD_SETUP)
 void ft_board_setup(void *blob, bd_t *bd)
 {
+	const immap_t *immr = (immap_t *)CFG_IMMR;
 #if defined(CONFIG_OF_FLAT_TREE)
 	u32 *p;
 	int len;
@@ -317,5 +318,35 @@ void ft_board_setup(void *blob, bd_t *bd)
 #ifdef CONFIG_PCI
 	ft_pci_setup(blob, bd);
 #endif
+	/*
+	 * mpc8360ea pb mds errata 2: RGMII timing
+	 * if on mpc8360ea rev. 2.1,
+	 * change both ucc phy-connection-types from rgmii-id to rgmii-rxid
+	 */
+	if (immr->sysconf.spridr == SPR_8360_REV21 ||
+	    immr->sysconf.spridr == SPR_8360E_REV21) {
+		int nodeoffset;
+		void *prop;
+
+		/* fixup UCC 1 if using rgmii-id mode */
+		nodeoffset = fdt_find_node_by_path(blob, "/" OF_QE "/ucc@2000");
+		if (nodeoffset >= 0) {
+			prop = fdt_getprop(blob, nodeoffset,
+					        "phy-connection-type", 0);
+			if (prop && (strcmp(prop, "rgmii-id") == 0))
+				fdt_setprop(blob, nodeoffset, "phy-connection-type",
+					    "rgmii-rxid", sizeof("rgmii-rxid"));
+		}
+
+		/* fixup UCC 2 if using rgmii-id mode */
+		nodeoffset = fdt_find_node_by_path(blob, "/" OF_QE "/ucc@3000");
+		if (nodeoffset >= 0) {
+			prop = fdt_getprop(blob, nodeoffset,
+					        "phy-connection-type", 0);
+			if (prop && (strcmp(prop, "rgmii-id") == 0))
+				fdt_setprop(blob, nodeoffset, "phy-connection-type",
+					    "rgmii-rxid", sizeof("rgmii-rxid"));
+		}
+	}
 }
 #endif

From 921d4b19ad1be704df58725485d9292dc0414adf Mon Sep 17 00:00:00 2001
From: Kim Phillips <kim.phillips@freescale.com>
Date: Mon, 19 Nov 2007 12:30:09 -0600
Subject: [PATCH 052/108] mpc83xx: fix CFG_ENV_ADDR and CFG_ENV_SECT_SIZE
 definitions for 837x

Fix the definitions of CFG_ENV_ADDR and CFG_ENV_SECT_SIZE for 837x.
This change guarantees that the environment will be located on the
first flash sector after the U-Boot image.

Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
---
 include/configs/MPC837XEMDS.h | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/include/configs/MPC837XEMDS.h b/include/configs/MPC837XEMDS.h
index 7e344925c..524ff7c92 100644
--- a/include/configs/MPC837XEMDS.h
+++ b/include/configs/MPC837XEMDS.h
@@ -197,6 +197,7 @@
 #undef CFG_RAMBOOT
 #endif
 
+/* CFG_MONITOR_LEN must be a multiple of CFG_ENV_SECT_SIZE */
 #define CFG_MONITOR_LEN		(256 * 1024) /* Reserve 256 kB for Mon */
 #define CFG_MALLOC_LEN		(512 * 1024) /* Reserved for malloc */
 
@@ -386,7 +387,7 @@
  */
 #ifndef CFG_RAMBOOT
 	#define CFG_ENV_IS_IN_FLASH	1
-	#define CFG_ENV_ADDR		(CFG_MONITOR_BASE + 0x40000)
+	#define CFG_ENV_ADDR		(CFG_MONITOR_BASE + CFG_MONITOR_LEN)
 	#define CFG_ENV_SECT_SIZE	0x20000 /* 128K(one sector) for env */
 	#define CFG_ENV_SIZE		0x2000
 #else

From c16e44fa835fb9eec982d919863a04e2f78e5ce7 Mon Sep 17 00:00:00 2001
From: Kim Phillips <kim.phillips@freescale.com>
Date: Tue, 27 Nov 2007 14:17:29 -0600
Subject: [PATCH 053/108] mpc83xx: fix remaining fdt_find_node_by_path
 references

rename to fdt_path_offset

Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
---
 board/freescale/mpc8360emds/mpc8360emds.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/board/freescale/mpc8360emds/mpc8360emds.c b/board/freescale/mpc8360emds/mpc8360emds.c
index ff9a85cc4..4a368b0d7 100644
--- a/board/freescale/mpc8360emds/mpc8360emds.c
+++ b/board/freescale/mpc8360emds/mpc8360emds.c
@@ -329,7 +329,7 @@ void ft_board_setup(void *blob, bd_t *bd)
 		void *prop;
 
 		/* fixup UCC 1 if using rgmii-id mode */
-		nodeoffset = fdt_find_node_by_path(blob, "/" OF_QE "/ucc@2000");
+		nodeoffset = fdt_path_offset(blob, "/" OF_QE "/ucc@2000");
 		if (nodeoffset >= 0) {
 			prop = fdt_getprop(blob, nodeoffset,
 					        "phy-connection-type", 0);
@@ -339,7 +339,7 @@ void ft_board_setup(void *blob, bd_t *bd)
 		}
 
 		/* fixup UCC 2 if using rgmii-id mode */
-		nodeoffset = fdt_find_node_by_path(blob, "/" OF_QE "/ucc@3000");
+		nodeoffset = fdt_path_offset(blob, "/" OF_QE "/ucc@3000");
 		if (nodeoffset >= 0) {
 			prop = fdt_getprop(blob, nodeoffset,
 					        "phy-connection-type", 0);

From f602082b4b7ed4ee16432067cc67a0a24fedc715 Mon Sep 17 00:00:00 2001
From: Kim Phillips <kim.phillips@freescale.com>
Date: Mon, 10 Dec 2007 14:16:22 -0600
Subject: [PATCH 054/108] mpc83xx: supress compiler warning
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

mpc8360emds.c: In function ‘ft_board_setup’:
mpc8360emds.c:335: warning: assignment discards qualifiers from pointer target type
mpc8360emds.c:345: warning: assignment discards qualifiers from pointer target type

Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
---
 board/freescale/mpc8360emds/mpc8360emds.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/board/freescale/mpc8360emds/mpc8360emds.c b/board/freescale/mpc8360emds/mpc8360emds.c
index 4a368b0d7..e673840cf 100644
--- a/board/freescale/mpc8360emds/mpc8360emds.c
+++ b/board/freescale/mpc8360emds/mpc8360emds.c
@@ -326,7 +326,7 @@ void ft_board_setup(void *blob, bd_t *bd)
 	if (immr->sysconf.spridr == SPR_8360_REV21 ||
 	    immr->sysconf.spridr == SPR_8360E_REV21) {
 		int nodeoffset;
-		void *prop;
+		const char *prop;
 
 		/* fixup UCC 1 if using rgmii-id mode */
 		nodeoffset = fdt_path_offset(blob, "/" OF_QE "/ucc@2000");

From e6af9932d31171e35db880e7b2f29f903b1b7660 Mon Sep 17 00:00:00 2001
From: Kumar Gala <galak@kernel.crashing.org>
Date: Mon, 26 Nov 2007 11:00:54 -0600
Subject: [PATCH 055/108] Remove CONFIG options related to OF that we dont use

The MPC8360E MDS config defined:
	CONFIG_OF_HAS_BD_T
	CONFIG_OF_HAS_UBOOT_ENV

Which we don't use or ever needed.  This seems like copy-paste feature creep.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
---
 include/configs/MPC8360EMDS.h | 2 --
 1 file changed, 2 deletions(-)

diff --git a/include/configs/MPC8360EMDS.h b/include/configs/MPC8360EMDS.h
index 8098951c5..c192f3365 100644
--- a/include/configs/MPC8360EMDS.h
+++ b/include/configs/MPC8360EMDS.h
@@ -349,8 +349,6 @@
 #define CONFIG_OF_LIBFDT	1
 #undef  CONFIG_OF_FLAT_TREE
 #define CONFIG_OF_BOARD_SETUP	1
-#define CONFIG_OF_HAS_BD_T	1
-#define CONFIG_OF_HAS_UBOOT_ENV	1
 
 #define OF_CPU			"PowerPC,8360@0"
 #define OF_SOC			"soc8360@e0000000"

From ccf21c311e68d48399eff1e72936052885f6e3f7 Mon Sep 17 00:00:00 2001
From: Joakim Tjernlund <Joakim.Tjernlund@transmode.se>
Date: Thu, 6 Dec 2007 16:43:40 +0100
Subject: [PATCH 056/108] Add support CONFIG_UEC_ETH3 in MPC83xx

Signed-off-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se>
---
 cpu/mpc83xx/cpu.c | 116 +++++++++++++++++++++++++++++++++++++++++++++-
 drivers/qe/uec.c  |  23 +++++++++
 net/eth.c         |   3 ++
 3 files changed, 141 insertions(+), 1 deletion(-)

diff --git a/cpu/mpc83xx/cpu.c b/cpu/mpc83xx/cpu.c
index 8d69d2290..3d3f20a63 100644
--- a/cpu/mpc83xx/cpu.c
+++ b/cpu/mpc83xx/cpu.c
@@ -520,6 +520,15 @@ static const struct {
 		"local-mac-address",
 		fdt_set_eth0
 	},
+#elif CFG_UEC1_UCC_NUM == 1  /* UCC2 */
+	{	"/" OF_QE "/ucc@3000",
+		"mac-address",
+		fdt_set_eth0
+	},
+	{	"/" OF_QE "/ucc@3000",
+		"local-mac-address",
+		fdt_set_eth0
+	},
 #elif CFG_UEC1_UCC_NUM == 2  /* UCC3 */
 	{	"/" OF_QE "/ucc@2200",
 		"mac-address",
@@ -529,10 +538,28 @@ static const struct {
 		"local-mac-address",
 		fdt_set_eth0
 	},
+#elif CFG_UEC1_UCC_NUM == 3  /* UCC4 */
+	{	"/" OF_QE "/ucc@3200",
+		"mac-address",
+		fdt_set_eth0
+	},
+	{	"/" OF_QE "/ucc@3200",
+		"local-mac-address",
+		fdt_set_eth0
+	},
 #endif
 #endif /* CONFIG_UEC_ETH1 */
 #ifdef CONFIG_UEC_ETH2
-#if CFG_UEC2_UCC_NUM == 1  /* UCC2 */
+#if CFG_UEC2_UCC_NUM == 0  /* UCC1 */
+	{	"/" OF_QE "/ucc@2000",
+		"mac-address",
+		fdt_set_eth1
+	},
+	{	"/" OF_QE "/ucc@2000",
+		"local-mac-address",
+		fdt_set_eth1
+	},
+#elif CFG_UEC2_UCC_NUM == 1  /* UCC2 */
 	{	"/" OF_QE "/ucc@3000",
 		"mac-address",
 		fdt_set_eth1
@@ -541,6 +568,15 @@ static const struct {
 		"local-mac-address",
 		fdt_set_eth1
 	},
+#elif CFG_UEC2_UCC_NUM == 2  /* UCC3 */
+	{	"/" OF_QE "/ucc@2200",
+		"mac-address",
+		fdt_set_eth1
+	},
+	{	"/" OF_QE "/ucc@2200",
+		"local-mac-address",
+		fdt_set_eth1
+	},
 #elif CFG_UEC2_UCC_NUM == 3  /* UCC4 */
 	{	"/" OF_QE "/ucc@3200",
 		"mac-address",
@@ -552,6 +588,84 @@ static const struct {
 	},
 #endif
 #endif /* CONFIG_UEC_ETH2 */
+#ifdef CONFIG_UEC_ETH3
+#if CFG_UEC3_UCC_NUM == 0  /* UCC1 */
+	{	"/" OF_QE "/ucc@2000",
+		"mac-address",
+		fdt_set_eth2
+	},
+	{	"/" OF_QE "/ucc@2000",
+		"local-mac-address",
+		fdt_set_eth2
+	},
+#elif CFG_UEC3_UCC_NUM == 1  /* UCC2 */
+	{	"/" OF_QE "/ucc@3000",
+		"mac-address",
+		fdt_set_eth2
+	},
+	{	"/" OF_QE "/ucc@3000",
+		"local-mac-address",
+		fdt_set_eth2
+	},
+#elif CFG_UEC3_UCC_NUM == 2  /* UCC3 */
+	{	"/" OF_QE "/ucc@2200",
+		"mac-address",
+		fdt_set_eth2
+	},
+	{	"/" OF_QE "/ucc@2200",
+		"local-mac-address",
+		fdt_set_eth2
+	},
+#elif CFG_UEC3_UCC_NUM == 3  /* UCC4 */
+	{	"/" OF_QE "/ucc@3200",
+		"mac-address",
+		fdt_set_eth2
+	},
+	{	"/" OF_QE "/ucc@3200",
+		"local-mac-address",
+		fdt_set_eth2
+	},
+#endif
+#endif /* CONFIG_UEC_ETH3 */
+#ifdef CONFIG_UEC_ETH4
+#if CFG_UEC4_UCC_NUM == 0  /* UCC1 */
+	{	"/" OF_QE "/ucc@2000",
+		"mac-address",
+		fdt_set_eth3
+	},
+	{	"/" OF_QE "/ucc@2000",
+		"local-mac-address",
+		fdt_set_eth3
+	},
+#elif CFG_UEC4_UCC_NUM == 1  /* UCC2 */
+	{	"/" OF_QE "/ucc@3000",
+		"mac-address",
+		fdt_set_eth3
+	},
+	{	"/" OF_QE "/ucc@3000",
+		"local-mac-address",
+		fdt_set_eth3
+	},
+#elif CFG_UEC4_UCC_NUM == 2  /* UCC3 */
+	{	"/" OF_QE "/ucc@2200",
+		"mac-address",
+		fdt_set_eth3
+	},
+	{	"/" OF_QE "/ucc@2200",
+		"local-mac-address",
+		fdt_set_eth3
+	},
+#elif CFG_UEC4_UCC_NUM == 3  /* UCC4 */
+	{	"/" OF_QE "/ucc@3200",
+		"mac-address",
+		fdt_set_eth3
+	},
+	{	"/" OF_QE "/ucc@3200",
+		"local-mac-address",
+		fdt_set_eth3
+	},
+#endif
+#endif /* CONFIG_UEC_ETH4 */
 #endif /* CONFIG_QE */
 };
 
diff --git a/drivers/qe/uec.c b/drivers/qe/uec.c
index dc2765bb0..a27c12aa2 100644
--- a/drivers/qe/uec.c
+++ b/drivers/qe/uec.c
@@ -69,6 +69,25 @@ static uec_info_t eth2_uec_info = {
 };
 #endif
 
+#ifdef CONFIG_UEC_ETH3
+static uec_info_t eth3_uec_info = {
+	.uf_info		= {
+		.ucc_num	= CFG_UEC3_UCC_NUM,
+		.rx_clock	= CFG_UEC3_RX_CLK,
+		.tx_clock	= CFG_UEC3_TX_CLK,
+		.eth_type	= CFG_UEC3_ETH_TYPE,
+	},
+	.num_threads_tx		= UEC_NUM_OF_THREADS_4,
+	.num_threads_rx		= UEC_NUM_OF_THREADS_4,
+	.riscTx			= QE_RISC_ALLOCATION_RISC1_AND_RISC2,
+	.riscRx			= QE_RISC_ALLOCATION_RISC1_AND_RISC2,
+	.tx_bd_ring_len		= 16,
+	.rx_bd_ring_len		= 16,
+	.phy_address		= CFG_UEC3_PHY_ADDR,
+	.enet_interface		= CFG_UEC3_INTERFACE_MODE,
+};
+#endif
+
 static int uec_mac_enable(uec_private_t *uec, comm_dir_e mode)
 {
 	uec_t		*uec_regs;
@@ -1237,6 +1256,10 @@ int uec_initialize(int index)
 	} else if (index == 1) {
 #ifdef CONFIG_UEC_ETH2
 		uec_info = &eth2_uec_info;
+#endif
+	} else if (index == 2) {
+#ifdef CONFIG_UEC_ETH3
+		uec_info = &eth3_uec_info;
 #endif
 	} else {
 		printf("%s: index is illegal.\n", __FUNCTION__);
diff --git a/net/eth.c b/net/eth.c
index 3373a0525..d2fced8bb 100644
--- a/net/eth.c
+++ b/net/eth.c
@@ -214,6 +214,9 @@ int eth_initialize(bd_t *bis)
 #if defined(CONFIG_UEC_ETH2)
 	uec_initialize(1);
 #endif
+#if defined(CONFIG_UEC_ETH3)
+	uec_initialize(2);
+#endif
 
 #if defined(FEC_ENET) || defined(CONFIG_ETHER_ON_FCC)
 	fec_initialize(bis);

From a1e1ac849249310e5e2e5c7148e9fb353a8317a7 Mon Sep 17 00:00:00 2001
From: Kim Phillips <kim.phillips@freescale.com>
Date: Thu, 20 Dec 2007 01:30:48 -0600
Subject: [PATCH 057/108] mpc83xx: Remove CONFIG options related to OF that we
 dont use (on 837x)

continuation of commit 37395fa2b0d9d617f28d44ca11592260ef16105a to 837x

Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
---
 include/configs/MPC837XEMDS.h | 2 --
 1 file changed, 2 deletions(-)

diff --git a/include/configs/MPC837XEMDS.h b/include/configs/MPC837XEMDS.h
index 524ff7c92..772fd0238 100644
--- a/include/configs/MPC837XEMDS.h
+++ b/include/configs/MPC837XEMDS.h
@@ -297,8 +297,6 @@
 /* Pass open firmware flat tree */
 #define CONFIG_OF_LIBFDT	1
 #define CONFIG_OF_BOARD_SETUP	1
-#define CONFIG_OF_HAS_BD_T	1
-#define CONFIG_OF_HAS_UBOOT_ENV	1
 
 #define OF_CPU			"PowerPC,837x@0"
 #define OF_SOC			"soc837x@e0000000"

From 27a256a90cc86392ac9bf0039a3afe638ec2c18d Mon Sep 17 00:00:00 2001
From: Paul Gortmaker <paul.gortmaker@windriver.com>
Date: Thu, 20 Dec 2007 12:56:19 -0500
Subject: [PATCH 058/108] sbc8349: Remove board specific ECC code

ECC code is now shared for all 83xx boards, so remove board specific one.
See commit daab8c67d2defef73dc26ab07f0c3afd1b05d019 for reference.

Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
---
 board/sbc8349/sbc8349.c | 327 ----------------------------------------
 1 file changed, 327 deletions(-)

diff --git a/board/sbc8349/sbc8349.c b/board/sbc8349/sbc8349.c
index 86166ea44..da3771467 100644
--- a/board/sbc8349/sbc8349.c
+++ b/board/sbc8349/sbc8349.c
@@ -32,7 +32,6 @@
 #include <i2c.h>
 #include <spd.h>
 #include <miiphy.h>
-#include <command.h>
 #if defined(CONFIG_SPD_EEPROM)
 #include <spd_sdram.h>
 #endif
@@ -235,332 +234,6 @@ void sdram_init(void)
 }
 #endif
 
-#if defined(CONFIG_DDR_ECC) && defined(CONFIG_DDR_ECC_CMD)
-/*
- * ECC user commands
- */
-void ecc_print_status(void)
-{
-	volatile immap_t *immap = (immap_t *)CFG_IMMR;
-	volatile ddr83xx_t *ddr = &immap->ddr;
-
-	printf("\nECC mode: %s\n\n", (ddr->sdram_cfg & SDRAM_CFG_ECC_EN) ? "ON" : "OFF");
-
-	/* Interrupts */
-	printf("Memory Error Interrupt Enable:\n");
-	printf("  Multiple-Bit Error Interrupt Enable: %d\n",
-			(ddr->err_int_en & ECC_ERR_INT_EN_MBEE) ? 1 : 0);
-	printf("  Single-Bit Error Interrupt Enable: %d\n",
-			(ddr->err_int_en & ECC_ERR_INT_EN_SBEE) ? 1 : 0);
-	printf("  Memory Select Error Interrupt Enable: %d\n\n",
-			(ddr->err_int_en & ECC_ERR_INT_EN_MSEE) ? 1 : 0);
-
-	/* Error disable */
-	printf("Memory Error Disable:\n");
-	printf("  Multiple-Bit Error Disable: %d\n",
-			(ddr->err_disable & ECC_ERROR_DISABLE_MBED) ? 1 : 0);
-	printf("  Sinle-Bit Error Disable: %d\n",
-			(ddr->err_disable & ECC_ERROR_DISABLE_SBED) ? 1 : 0);
-	printf("  Memory Select Error Disable: %d\n\n",
-			(ddr->err_disable & ECC_ERROR_DISABLE_MSED) ? 1 : 0);
-
-	/* Error injection */
-	printf("Memory Data Path Error Injection Mask High/Low: %08lx %08lx\n",
-			ddr->data_err_inject_hi, ddr->data_err_inject_lo);
-
-	printf("Memory Data Path Error Injection Mask ECC:\n");
-	printf("  ECC Mirror Byte: %d\n",
-			(ddr->ecc_err_inject & ECC_ERR_INJECT_EMB) ? 1 : 0);
-	printf("  ECC Injection Enable: %d\n",
-			(ddr->ecc_err_inject & ECC_ERR_INJECT_EIEN) ? 1 : 0);
-	printf("  ECC Error Injection Mask: 0x%02x\n\n",
-			ddr->ecc_err_inject & ECC_ERR_INJECT_EEIM);
-
-	/* SBE counter/threshold */
-	printf("Memory Single-Bit Error Management (0..255):\n");
-	printf("  Single-Bit Error Threshold: %d\n",
-			(ddr->err_sbe & ECC_ERROR_MAN_SBET) >> ECC_ERROR_MAN_SBET_SHIFT);
-	printf("  Single-Bit Error Counter: %d\n\n",
-			(ddr->err_sbe & ECC_ERROR_MAN_SBEC) >> ECC_ERROR_MAN_SBEC_SHIFT);
-
-	/* Error detect */
-	printf("Memory Error Detect:\n");
-	printf("  Multiple Memory Errors: %d\n",
-			(ddr->err_detect & ECC_ERROR_DETECT_MME) ? 1 : 0);
-	printf("  Multiple-Bit Error: %d\n",
-			(ddr->err_detect & ECC_ERROR_DETECT_MBE) ? 1 : 0);
-	printf("  Single-Bit Error: %d\n",
-			(ddr->err_detect & ECC_ERROR_DETECT_SBE) ? 1 : 0);
-	printf("  Memory Select Error: %d\n\n",
-			(ddr->err_detect & ECC_ERROR_DETECT_MSE) ? 1 : 0);
-
-	/* Capture data */
-	printf("Memory Error Address Capture: 0x%08lx\n", ddr->capture_address);
-	printf("Memory Data Path Read Capture High/Low: %08lx %08lx\n",
-			ddr->capture_data_hi, ddr->capture_data_lo);
-	printf("Memory Data Path Read Capture ECC: 0x%02x\n\n",
-		ddr->capture_ecc & CAPTURE_ECC_ECE);
-
-	printf("Memory Error Attributes Capture:\n");
-	printf("  Data Beat Number: %d\n",
-			(ddr->capture_attributes & ECC_CAPT_ATTR_BNUM) >> ECC_CAPT_ATTR_BNUM_SHIFT);
-	printf("  Transaction Size: %d\n",
-			(ddr->capture_attributes & ECC_CAPT_ATTR_TSIZ) >> ECC_CAPT_ATTR_TSIZ_SHIFT);
-	printf("  Transaction Source: %d\n",
-			(ddr->capture_attributes & ECC_CAPT_ATTR_TSRC) >> ECC_CAPT_ATTR_TSRC_SHIFT);
-	printf("  Transaction Type: %d\n",
-			(ddr->capture_attributes & ECC_CAPT_ATTR_TTYP) >> ECC_CAPT_ATTR_TTYP_SHIFT);
-	printf("  Error Information Valid: %d\n\n",
-			ddr->capture_attributes & ECC_CAPT_ATTR_VLD);
-}
-
-int do_ecc ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
-{
-	volatile immap_t *immap = (immap_t *)CFG_IMMR;
-	volatile ddr83xx_t *ddr = &immap->ddr;
-	volatile u32 val;
-	u64 *addr, count, val64;
-	register u64 *i;
-
-	if (argc > 4) {
-		printf ("Usage:\n%s\n", cmdtp->usage);
-		return 1;
-	}
-
-	if (argc == 2) {
-		if (strcmp(argv[1], "status") == 0) {
-			ecc_print_status();
-			return 0;
-		} else if (strcmp(argv[1], "captureclear") == 0) {
-			ddr->capture_address = 0;
-			ddr->capture_data_hi = 0;
-			ddr->capture_data_lo = 0;
-			ddr->capture_ecc = 0;
-			ddr->capture_attributes = 0;
-			return 0;
-		}
-	}
-
-	if (argc == 3) {
-		if (strcmp(argv[1], "sbecnt") == 0) {
-			val = simple_strtoul(argv[2], NULL, 10);
-			if (val > 255) {
-				printf("Incorrect Counter value, should be 0..255\n");
-				return 1;
-			}
-
-			val = (val << ECC_ERROR_MAN_SBEC_SHIFT);
-			val |= (ddr->err_sbe & ECC_ERROR_MAN_SBET);
-
-			ddr->err_sbe = val;
-			return 0;
-		} else if (strcmp(argv[1], "sbethr") == 0) {
-			val = simple_strtoul(argv[2], NULL, 10);
-			if (val > 255) {
-				printf("Incorrect Counter value, should be 0..255\n");
-				return 1;
-			}
-
-			val = (val << ECC_ERROR_MAN_SBET_SHIFT);
-			val |= (ddr->err_sbe & ECC_ERROR_MAN_SBEC);
-
-			ddr->err_sbe = val;
-			return 0;
-		} else if (strcmp(argv[1], "errdisable") == 0) {
-			val = ddr->err_disable;
-
-			if (strcmp(argv[2], "+sbe") == 0) {
-				val |= ECC_ERROR_DISABLE_SBED;
-			} else if (strcmp(argv[2], "+mbe") == 0) {
-				val |= ECC_ERROR_DISABLE_MBED;
-			} else if (strcmp(argv[2], "+mse") == 0) {
-				val |= ECC_ERROR_DISABLE_MSED;
-			} else if (strcmp(argv[2], "+all") == 0) {
-				val |= (ECC_ERROR_DISABLE_SBED |
-					ECC_ERROR_DISABLE_MBED |
-					ECC_ERROR_DISABLE_MSED);
-			} else if (strcmp(argv[2], "-sbe") == 0) {
-				val &= ~ECC_ERROR_DISABLE_SBED;
-			} else if (strcmp(argv[2], "-mbe") == 0) {
-				val &= ~ECC_ERROR_DISABLE_MBED;
-			} else if (strcmp(argv[2], "-mse") == 0) {
-				val &= ~ECC_ERROR_DISABLE_MSED;
-			} else if (strcmp(argv[2], "-all") == 0) {
-				val &= ~(ECC_ERROR_DISABLE_SBED |
-					ECC_ERROR_DISABLE_MBED |
-					ECC_ERROR_DISABLE_MSED);
-			} else {
-				printf("Incorrect err_disable field\n");
-				return 1;
-			}
-
-			ddr->err_disable = val;
-			__asm__ __volatile__ ("sync");
-			__asm__ __volatile__ ("isync");
-			return 0;
-		} else if (strcmp(argv[1], "errdetectclr") == 0) {
-			val = ddr->err_detect;
-
-			if (strcmp(argv[2], "mme") == 0) {
-				val |= ECC_ERROR_DETECT_MME;
-			} else if (strcmp(argv[2], "sbe") == 0) {
-				val |= ECC_ERROR_DETECT_SBE;
-			} else if (strcmp(argv[2], "mbe") == 0) {
-				val |= ECC_ERROR_DETECT_MBE;
-			} else if (strcmp(argv[2], "mse") == 0) {
-				val |= ECC_ERROR_DETECT_MSE;
-			} else if (strcmp(argv[2], "all") == 0) {
-				val |= (ECC_ERROR_DETECT_MME |
-					ECC_ERROR_DETECT_MBE |
-					ECC_ERROR_DETECT_SBE |
-					ECC_ERROR_DETECT_MSE);
-			} else {
-				printf("Incorrect err_detect field\n");
-				return 1;
-			}
-
-			ddr->err_detect = val;
-			return 0;
-		} else if (strcmp(argv[1], "injectdatahi") == 0) {
-			val = simple_strtoul(argv[2], NULL, 16);
-
-			ddr->data_err_inject_hi = val;
-			return 0;
-		} else if (strcmp(argv[1], "injectdatalo") == 0) {
-			val = simple_strtoul(argv[2], NULL, 16);
-
-			ddr->data_err_inject_lo = val;
-			return 0;
-		} else if (strcmp(argv[1], "injectecc") == 0) {
-			val = simple_strtoul(argv[2], NULL, 16);
-			if (val > 0xff) {
-				printf("Incorrect ECC inject mask, should be 0x00..0xff\n");
-				return 1;
-			}
-			val |= (ddr->ecc_err_inject & ~ECC_ERR_INJECT_EEIM);
-
-			ddr->ecc_err_inject = val;
-			return 0;
-		} else if (strcmp(argv[1], "inject") == 0) {
-			val = ddr->ecc_err_inject;
-
-			if (strcmp(argv[2], "en") == 0)
-				val |= ECC_ERR_INJECT_EIEN;
-			else if (strcmp(argv[2], "dis") == 0)
-				val &= ~ECC_ERR_INJECT_EIEN;
-			else
-				printf("Incorrect command\n");
-
-			ddr->ecc_err_inject = val;
-			__asm__ __volatile__ ("sync");
-			__asm__ __volatile__ ("isync");
-			return 0;
-		} else if (strcmp(argv[1], "mirror") == 0) {
-			val = ddr->ecc_err_inject;
-
-			if (strcmp(argv[2], "en") == 0)
-				val |= ECC_ERR_INJECT_EMB;
-			else if (strcmp(argv[2], "dis") == 0)
-				val &= ~ECC_ERR_INJECT_EMB;
-			else
-				printf("Incorrect command\n");
-
-			ddr->ecc_err_inject = val;
-			return 0;
-		}
-	}
-
-	if (argc == 4) {
-		if (strcmp(argv[1], "test") == 0) {
-			addr = (u64 *)simple_strtoul(argv[2], NULL, 16);
-			count = simple_strtoul(argv[3], NULL, 16);
-
-			if ((u32)addr % 8) {
-				printf("Address not alligned on double word boundary\n");
-				return 1;
-			}
-
-			disable_interrupts();
-			icache_disable();
-
-			for (i = addr; i < addr + count; i++) {
-				/* enable injects */
-				ddr->ecc_err_inject |= ECC_ERR_INJECT_EIEN;
-				__asm__ __volatile__ ("sync");
-				__asm__ __volatile__ ("isync");
-
-				/* write memory location injecting errors */
-				*i = 0x1122334455667788ULL;
-				__asm__ __volatile__ ("sync");
-
-				/* disable injects */
-				ddr->ecc_err_inject &= ~ECC_ERR_INJECT_EIEN;
-				__asm__ __volatile__ ("sync");
-				__asm__ __volatile__ ("isync");
-
-				/* read data, this generates ECC error */
-				val64 = *i;
-				__asm__ __volatile__ ("sync");
-
-				/* disable errors for ECC */
-				ddr->err_disable |= ~ECC_ERROR_ENABLE;
-				__asm__ __volatile__ ("sync");
-				__asm__ __volatile__ ("isync");
-
-				/* re-initialize memory, write the location again
-				 * NOT injecting errors this time */
-				*i = 0xcafecafecafecafeULL;
-				__asm__ __volatile__ ("sync");
-
-				/* enable errors for ECC */
-				ddr->err_disable &= ECC_ERROR_ENABLE;
-				__asm__ __volatile__ ("sync");
-				__asm__ __volatile__ ("isync");
-			}
-
-			icache_enable();
-			enable_interrupts();
-
-			return 0;
-		}
-	}
-
-	printf ("Usage:\n%s\n", cmdtp->usage);
-	return 1;
-}
-
-U_BOOT_CMD(
-	ecc,     4,     0,      do_ecc,
-	"ecc     - support for DDR ECC features\n",
-	"status              - print out status info\n"
-	"ecc captureclear        - clear capture regs data\n"
-	"ecc sbecnt <val>        - set Single-Bit Error counter\n"
-	"ecc sbethr <val>        - set Single-Bit Threshold\n"
-	"ecc errdisable <flag>   - clear/set disable Memory Error Disable, flag:\n"
-	"  [-|+]sbe - Single-Bit Error\n"
-	"  [-|+]mbe - Multiple-Bit Error\n"
-	"  [-|+]mse - Memory Select Error\n"
-	"  [-|+]all - all errors\n"
-	"ecc errdetectclr <flag> - clear Memory Error Detect, flag:\n"
-	"  mme - Multiple Memory Errors\n"
-	"  sbe - Single-Bit Error\n"
-	"  mbe - Multiple-Bit Error\n"
-	"  mse - Memory Select Error\n"
-	"  all - all errors\n"
-	"ecc injectdatahi <hi>  - set Memory Data Path Error Injection Mask High\n"
-	"ecc injectdatalo <lo>  - set Memory Data Path Error Injection Mask Low\n"
-	"ecc injectecc <ecc>    - set ECC Error Injection Mask\n"
-	"ecc inject <en|dis>    - enable/disable error injection\n"
-	"ecc mirror <en|dis>    - enable/disable mirror byte\n"
-	"ecc test <addr> <cnt>  - test mem region:\n"
-	"  - enables injects\n"
-	"  - writes pattern injecting errors\n"
-	"  - disables injects\n"
-	"  - reads pattern back, generates error\n"
-	"  - re-inits memory"
-);
-#endif /* if defined(CONFIG_DDR_ECC) && defined(CONFIG_DDR_ECC_CMD) */
-
 #if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP)
 void
 ft_board_setup(void *blob, bd_t *bd)

From 2408b3f20bcbdd9c6c397cd03ab0d71d54680a40 Mon Sep 17 00:00:00 2001
From: Paul Gortmaker <paul.gortmaker@windriver.com>
Date: Thu, 20 Dec 2007 12:58:16 -0500
Subject: [PATCH 059/108] sbc8349: migrate board to libfdt

This adds libfdt support code for the Wind River sbc8349 board.

Parallel of commit 3fde9e8b22cfbd7af489214758f9839a206576cb for
the other Freescale 83xx boards.

Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
---
 board/sbc8349/sbc8349.c | 18 ++++++++++--------
 1 file changed, 10 insertions(+), 8 deletions(-)

diff --git a/board/sbc8349/sbc8349.c b/board/sbc8349/sbc8349.c
index da3771467..097ab8043 100644
--- a/board/sbc8349/sbc8349.c
+++ b/board/sbc8349/sbc8349.c
@@ -37,6 +37,8 @@
 #endif
 #if defined(CONFIG_OF_FLAT_TREE)
 #include <ft_build.h>
+#elif defined(CONFIG_OF_LIBFDT)
+#include <libfdt.h>
 #endif
 
 int fixed_sdram(void);
@@ -234,22 +236,22 @@ void sdram_init(void)
 }
 #endif
 
-#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP)
-void
-ft_board_setup(void *blob, bd_t *bd)
+#if defined(CONFIG_OF_BOARD_SETUP)
+void ft_board_setup(void *blob, bd_t *bd)
 {
+#if defined(CONFIG_OF_FLAT_TREE)
 	u32 *p;
 	int len;
 
-#ifdef CONFIG_PCI
-	ft_pci_setup(blob, bd);
-#endif
-	ft_cpu_setup(blob, bd);
-
 	p = ft_get_prop(blob, "/memory/reg", &len);
 	if (p != NULL) {
 		*p++ = cpu_to_be32(bd->bi_memstart);
 		*p = cpu_to_be32(bd->bi_memsize);
 	}
+#endif
+	ft_cpu_setup(blob, bd);
+#ifdef CONFIG_PCI
+	ft_pci_setup(blob, bd);
+#endif
 }
 #endif

From e496865ecc31a2fe2f9abfe798334bb02aaf05ab Mon Sep 17 00:00:00 2001
From: Paul Gortmaker <paul.gortmaker@windriver.com>
Date: Thu, 20 Dec 2007 12:58:51 -0500
Subject: [PATCH 060/108] sbc8349: enable libfdt by default on WRS SBC8349
 board.

Make libfdt the default for the WRS SBC8349 board.
Parallel of commit 35cc4e4823668e8745854899cfaedd4489beb0ef
done for the other 83xx based boards.  Also fix a typo in CONFIG_PCI.

Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
---
 include/configs/sbc8349.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/include/configs/sbc8349.h b/include/configs/sbc8349.h
index e7d8a5a66..45f20dc12 100644
--- a/include/configs/sbc8349.h
+++ b/include/configs/sbc8349.h
@@ -310,7 +310,7 @@
 #endif
 
 /* pass open firmware flat tree */
-#define CONFIG_OF_FLAT_TREE	1
+#define CONFIG_OF_LIBFDT	1
 #define CONFIG_OF_BOARD_SETUP	1
 
 #define OF_CPU			"PowerPC,8349@0"
@@ -458,7 +458,7 @@
 #define CONFIG_CMD_PING
 
 #if defined(CONFIG_PCI)
-    #define CONFG_CMD_PCI
+    #define CONFIG_CMD_PCI
 #endif
 
 #if defined(CFG_RAMBOOT)

From 5b8bc606c61456566af6912f818a153b6b06f242 Mon Sep 17 00:00:00 2001
From: Kim Phillips <kim.phillips@freescale.com>
Date: Thu, 20 Dec 2007 14:09:22 -0600
Subject: [PATCH 061/108] mpc83xx: convert to using do_fixup_*()

convert to using simpler mpc85xx style fdt update code; streamline by
eliminating macros OF_SOC, OF_CPU, etc. which allows us to rm
the old school FLAT_TREE code from 83xx (since the sbc8349 was just
converted over to using libfdt).

Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
---
 board/freescale/mpc832xemds/pci.c         |  28 +-
 board/freescale/mpc8349emds/pci.c         |  47 +--
 board/freescale/mpc8349itx/pci.c          |  47 +--
 board/freescale/mpc8360emds/mpc8360emds.c |  41 ++-
 board/freescale/mpc8360emds/pci.c         |  25 +-
 board/sbc8349/pci.c                       |  43 ++-
 cpu/mpc83xx/Makefile                      |   2 +-
 cpu/mpc83xx/cpu.c                         | 426 ----------------------
 cpu/mpc83xx/fdt.c                         |  72 ++++
 cpu/mpc83xx/pci.c                         |  75 ++--
 include/configs/MPC8313ERDB.h             |   6 +-
 include/configs/MPC8323ERDB.h             |   7 +-
 include/configs/MPC832XEMDS.h             |   7 +-
 include/configs/MPC8349EMDS.h             |   6 +-
 include/configs/MPC8349ITX.h              |   8 +-
 include/configs/MPC8360EMDS.h             |   8 +-
 include/configs/MPC837XEMDS.h             |   6 +-
 include/configs/sbc8349.h                 |   6 +-
 18 files changed, 255 insertions(+), 605 deletions(-)
 create mode 100644 cpu/mpc83xx/fdt.c

diff --git a/board/freescale/mpc832xemds/pci.c b/board/freescale/mpc832xemds/pci.c
index 7818a2e1e..d50b78aa8 100644
--- a/board/freescale/mpc832xemds/pci.c
+++ b/board/freescale/mpc832xemds/pci.c
@@ -22,6 +22,7 @@
 #include <ft_build.h>
 #elif defined(CONFIG_OF_LIBFDT)
 #include <libfdt.h>
+#include <fdt_support.h>
 #endif
 
 #include <asm/fsl_i2c.h>
@@ -262,23 +263,28 @@ void pci_init_board(void)
 #endif				/* CONFIG_PCISLAVE */
 
 #if defined(CONFIG_OF_LIBFDT)
-void
-ft_pci_setup(void *blob, bd_t *bd)
+void ft_pci_setup(void *blob, bd_t *bd)
 {
 	int nodeoffset;
-	int err;
 	int tmp[2];
+	const char *path;
 
-	nodeoffset = fdt_path_offset(blob, "/" OF_SOC "/pci@8500");
+	if (pci_num_buses < 1)
+		return;
+
+	nodeoffset = fdt_path_offset(blob, "/aliases");
 	if (nodeoffset >= 0) {
-		tmp[0] = cpu_to_be32(hose[0].first_busno);
-		tmp[1] = cpu_to_be32(hose[0].last_busno);
-		err = fdt_setprop(blob, nodeoffset, "bus-range",
-				  tmp, sizeof(tmp));
+		path = fdt_getprop(blob, nodeoffset, "pci0", NULL);
+		if (path) {
+			tmp[0] = cpu_to_be32(pci_hose[0].first_busno);
+			tmp[1] = cpu_to_be32(pci_hose[0].last_busno);
+			do_fixup_by_path(blob, path, "bus-range",
+				&tmp, sizeof(tmp), 1);
 
-		tmp[0] = cpu_to_be32(gd->pci_clk);
-		err = fdt_setprop(blob, nodeoffset, "clock-frequency",
-				  tmp, sizeof(tmp[0]));
+			tmp[0] = cpu_to_be32(gd->pci_clk);
+			do_fixup_by_path(blob, path, "clock-frequency",
+				&tmp, sizeof(tmp[0]), 1);
+		}
 	}
 }
 #elif defined(CONFIG_OF_FLAT_TREE)
diff --git a/board/freescale/mpc8349emds/pci.c b/board/freescale/mpc8349emds/pci.c
index 7bcdccbcc..3eaf77a59 100644
--- a/board/freescale/mpc8349emds/pci.c
+++ b/board/freescale/mpc8349emds/pci.c
@@ -29,6 +29,7 @@
 #include <ft_build.h>
 #elif defined(CONFIG_OF_LIBFDT)
 #include <libfdt.h>
+#include <fdt_support.h>
 #endif
 
 
@@ -389,37 +390,39 @@ pci_init_board(void)
 }
 
 #if defined(CONFIG_OF_LIBFDT)
-void
-ft_pci_setup(void *blob, bd_t *bd)
+void ft_pci_setup(void *blob, bd_t *bd)
 {
 	int nodeoffset;
-	int err;
 	int tmp[2];
+	const char *path;
 
-	nodeoffset = fdt_path_offset(blob, "/" OF_SOC "/pci@8500");
+	nodeoffset = fdt_path_offset(blob, "/aliases");
 	if (nodeoffset >= 0) {
-		tmp[0] = cpu_to_be32(pci_hose[0].first_busno);
-		tmp[1] = cpu_to_be32(pci_hose[0].last_busno);
-		err = fdt_setprop(blob, nodeoffset, "bus-range",
-				  tmp, sizeof(tmp));
+		path = fdt_getprop(blob, nodeoffset, "pci0", NULL);
+		if (path) {
+			tmp[0] = cpu_to_be32(pci_hose[0].first_busno);
+			tmp[1] = cpu_to_be32(pci_hose[0].last_busno);
+			do_fixup_by_path(blob, path, "bus-range",
+				&tmp, sizeof(tmp), 1);
 
-		tmp[0] = cpu_to_be32(gd->pci_clk);
-		err = fdt_setprop(blob, nodeoffset, "clock-frequency",
-				  tmp, sizeof(tmp[0]));
-	}
+			tmp[0] = cpu_to_be32(gd->pci_clk);
+			do_fixup_by_path(blob, path, "clock-frequency",
+				&tmp, sizeof(tmp[0]), 1);
+		}
 #ifdef CONFIG_MPC83XX_PCI2
-	nodeoffset = fdt_path_offset(blob, "/" OF_SOC "/pci@8600");
-	if (nodeoffset >= 0) {
-		tmp[0] = cpu_to_be32(pci_hose[1].first_busno);
-		tmp[1] = cpu_to_be32(pci_hose[1].last_busno);
-		err = fdt_setprop(blob, nodeoffset, "bus-range",
-				  tmp, sizeof(tmp));
+		path = fdt_getprop(blob, nodeoffset, "pci1", NULL);
+		if (path) {
+			tmp[0] = cpu_to_be32(pci_hose[0].first_busno);
+			tmp[1] = cpu_to_be32(pci_hose[0].last_busno);
+			do_fixup_by_path(blob, path, "bus-range",
+				&tmp, sizeof(tmp), 1);
 
-		tmp[0] = cpu_to_be32(gd->pci_clk);
-		err = fdt_setprop(blob, nodeoffset, "clock-frequency",
-				  tmp, sizeof(tmp[0]));
-	}
+			tmp[0] = cpu_to_be32(gd->pci_clk);
+			do_fixup_by_path(blob, path, "clock-frequency",
+				&tmp, sizeof(tmp[0]), 1);
+		}
 #endif
+	}
 }
 #elif defined(CONFIG_OF_FLAT_TREE)
 void
diff --git a/board/freescale/mpc8349itx/pci.c b/board/freescale/mpc8349itx/pci.c
index a764a6186..a6bb101b4 100644
--- a/board/freescale/mpc8349itx/pci.c
+++ b/board/freescale/mpc8349itx/pci.c
@@ -33,6 +33,7 @@
 #include <ft_build.h>
 #elif defined(CONFIG_OF_LIBFDT)
 #include <libfdt.h>
+#include <fdt_support.h>
 #endif
 
 DECLARE_GLOBAL_DATA_PTR;
@@ -335,37 +336,39 @@ void pci_init_board(void)
 }
 
 #if defined(CONFIG_OF_LIBFDT)
-void
-ft_pci_setup(void *blob, bd_t *bd)
+void ft_pci_setup(void *blob, bd_t *bd)
 {
 	int nodeoffset;
-	int err;
 	int tmp[2];
+	const char *path;
 
-	nodeoffset = fdt_path_offset(blob, "/" OF_SOC "/pci@8500");
+	nodeoffset = fdt_path_offset(blob, "/aliases");
 	if (nodeoffset >= 0) {
-		tmp[0] = cpu_to_be32(pci_hose[0].first_busno);
-		tmp[1] = cpu_to_be32(pci_hose[0].last_busno);
-		err = fdt_setprop(blob, nodeoffset, "bus-range",
-				  tmp, sizeof(tmp));
+		path = fdt_getprop(blob, nodeoffset, "pci0", NULL);
+		if (path) {
+			tmp[0] = cpu_to_be32(pci_hose[0].first_busno);
+			tmp[1] = cpu_to_be32(pci_hose[0].last_busno);
+			do_fixup_by_path(blob, path, "bus-range",
+				&tmp, sizeof(tmp), 1);
 
-		tmp[0] = cpu_to_be32(gd->pci_clk);
-		err = fdt_setprop(blob, nodeoffset, "clock-frequency",
-				  tmp, sizeof(tmp[0]));
-	}
+			tmp[0] = cpu_to_be32(gd->pci_clk);
+			do_fixup_by_path(blob, path, "clock-frequency",
+				&tmp, sizeof(tmp[0]), 1);
+		}
 #ifdef CONFIG_MPC83XX_PCI2
-	nodeoffset = fdt_path_offset(blob, "/" OF_SOC "/pci@8500");
-	if (nodeoffset >= 0) {
-		tmp[0] = cpu_to_be32(pci_hose[1].first_busno);
-		tmp[1] = cpu_to_be32(pci_hose[1].last_busno);
-		err = fdt_setprop(blob, nodeoffset, "bus-range",
-				  tmp, sizeof(tmp));
+		path = fdt_getprop(blob, nodeoffset, "pci1", NULL);
+		if (path) {
+			tmp[0] = cpu_to_be32(pci_hose[0].first_busno);
+			tmp[1] = cpu_to_be32(pci_hose[0].last_busno);
+			do_fixup_by_path(blob, path, "bus-range",
+				&tmp, sizeof(tmp), 1);
 
-		tmp[0] = cpu_to_be32(gd->pci_clk);
-		err = fdt_setprop(blob, nodeoffset, "clock-frequency",
-				  tmp, sizeof(tmp[0]));
-	}
+			tmp[0] = cpu_to_be32(gd->pci_clk);
+			do_fixup_by_path(blob, path, "clock-frequency",
+				&tmp, sizeof(tmp[0]), 1);
+		}
 #endif
+	}
 }
 #elif defined(CONFIG_OF_FLAT_TREE)
 void
diff --git a/board/freescale/mpc8360emds/mpc8360emds.c b/board/freescale/mpc8360emds/mpc8360emds.c
index e673840cf..a899800a8 100644
--- a/board/freescale/mpc8360emds/mpc8360emds.c
+++ b/board/freescale/mpc8360emds/mpc8360emds.c
@@ -327,25 +327,32 @@ void ft_board_setup(void *blob, bd_t *bd)
 	    immr->sysconf.spridr == SPR_8360E_REV21) {
 		int nodeoffset;
 		const char *prop;
+		const char *path;
 
-		/* fixup UCC 1 if using rgmii-id mode */
-		nodeoffset = fdt_path_offset(blob, "/" OF_QE "/ucc@2000");
+		nodeoffset = fdt_path_offset(fdt, "/aliases");
 		if (nodeoffset >= 0) {
-			prop = fdt_getprop(blob, nodeoffset,
-					        "phy-connection-type", 0);
-			if (prop && (strcmp(prop, "rgmii-id") == 0))
-				fdt_setprop(blob, nodeoffset, "phy-connection-type",
-					    "rgmii-rxid", sizeof("rgmii-rxid"));
-		}
-
-		/* fixup UCC 2 if using rgmii-id mode */
-		nodeoffset = fdt_path_offset(blob, "/" OF_QE "/ucc@3000");
-		if (nodeoffset >= 0) {
-			prop = fdt_getprop(blob, nodeoffset,
-					        "phy-connection-type", 0);
-			if (prop && (strcmp(prop, "rgmii-id") == 0))
-				fdt_setprop(blob, nodeoffset, "phy-connection-type",
-					    "rgmii-rxid", sizeof("rgmii-rxid"));
+#if defined(CONFIG_HAS_ETH0)
+			/* fixup UCC 1 if using rgmii-id mode */
+			path = fdt_getprop(blob, nodeoffset, "ethernet0", NULL);
+			if (path) {
+				prop = fdt_getprop(blob, nodeoffset,
+							"phy-connection-type", 0);
+				if (prop && (strcmp(prop, "rgmii-id") == 0))
+					fdt_setprop(blob, nodeoffset, "phy-connection-type",
+						    "rgmii-rxid", sizeof("rgmii-rxid"));
+			}
+#endif
+#if defined(CONFIG_HAS_ETH1)
+			/* fixup UCC 2 if using rgmii-id mode */
+			path = fdt_getprop(blob, nodeoffset, "ethernet1", NULL);
+			if (path) {
+				prop = fdt_getprop(blob, nodeoffset,
+							"phy-connection-type", 0);
+				if (prop && (strcmp(prop, "rgmii-id") == 0))
+					fdt_setprop(blob, nodeoffset, "phy-connection-type",
+						    "rgmii-rxid", sizeof("rgmii-rxid"));
+			}
+#endif
 		}
 	}
 }
diff --git a/board/freescale/mpc8360emds/pci.c b/board/freescale/mpc8360emds/pci.c
index f18e532ef..64cb8ade6 100644
--- a/board/freescale/mpc8360emds/pci.c
+++ b/board/freescale/mpc8360emds/pci.c
@@ -22,6 +22,7 @@
 #include <ft_build.h>
 #elif defined(CONFIG_OF_LIBFDT)
 #include <libfdt.h>
+#include <fdt_support.h>
 #endif
 
 #include <asm/fsl_i2c.h>
@@ -262,23 +263,25 @@ void pci_init_board(void)
 #endif				/* CONFIG_PCISLAVE */
 
 #if defined(CONFIG_OF_LIBFDT)
-void
-ft_pci_setup(void *blob, bd_t *bd)
+void ft_pci_setup(void *blob, bd_t *bd)
 {
 	int nodeoffset;
-	int err;
 	int tmp[2];
+	const char *path;
 
-	nodeoffset = fdt_path_offset(blob, "/" OF_SOC "/pci@8500");
+	nodeoffset = fdt_path_offset(blob, "/aliases");
 	if (nodeoffset >= 0) {
-		tmp[0] = cpu_to_be32(hose[0].first_busno);
-		tmp[1] = cpu_to_be32(hose[0].last_busno);
-		err = fdt_setprop(blob, nodeoffset, "bus-range",
-				  tmp, sizeof(tmp));
+		path = fdt_getprop(blob, nodeoffset, "pci0", NULL);
+		if (path) {
+			tmp[0] = cpu_to_be32(pci_hose[0].first_busno);
+			tmp[1] = cpu_to_be32(pci_hose[0].last_busno);
+			do_fixup_by_path(blob, path, "bus-range",
+				&tmp, sizeof(tmp), 1);
 
-		tmp[0] = cpu_to_be32(gd->pci_clk);
-		err = fdt_setprop(blob, nodeoffset, "clock-frequency",
-				  tmp, sizeof(tmp[0]));
+			tmp[0] = cpu_to_be32(gd->pci_clk);
+			do_fixup_by_path(blob, path, "clock-frequency",
+				&tmp, sizeof(tmp[0]), 1);
+		}
 	}
 }
 #elif defined(CONFIG_OF_FLAT_TREE)
diff --git a/board/sbc8349/pci.c b/board/sbc8349/pci.c
index eadf23098..e59f9f9a5 100644
--- a/board/sbc8349/pci.c
+++ b/board/sbc8349/pci.c
@@ -30,6 +30,12 @@
 #include <pci.h>
 #include <asm/mpc8349_pci.h>
 #include <i2c.h>
+#if defined(CONFIG_OF_FLAT_TREE)
+#include <ft_build.h>
+#elif defined(CONFIG_OF_LIBFDT)
+#include <libfdt.h>
+#include <fdt_support.h>
+#endif
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -323,7 +329,42 @@ pci_init_board(void)
 
 }
 
-#ifdef CONFIG_OF_FLAT_TREE
+#if defined(CONFIG_OF_LIBFDT)
+void ft_pci_setup(void *blob, bd_t *bd)
+{
+	int nodeoffset;
+	int tmp[2];
+	const char *path;
+
+	nodeoffset = fdt_path_offset(blob, "/aliases");
+	if (nodeoffset >= 0) {
+		path = fdt_getprop(blob, nodeoffset, "pci0", NULL);
+		if (path) {
+			tmp[0] = cpu_to_be32(pci_hose[0].first_busno);
+			tmp[1] = cpu_to_be32(pci_hose[0].last_busno);
+			do_fixup_by_path(blob, path, "bus-range",
+				&tmp, sizeof(tmp), 1);
+
+			tmp[0] = cpu_to_be32(gd->pci_clk);
+			do_fixup_by_path(blob, path, "clock-frequency",
+				&tmp, sizeof(tmp[0]), 1);
+		}
+#ifdef CONFIG_MPC83XX_PCI2
+		path = fdt_getprop(blob, nodeoffset, "pci1", NULL);
+		if (path) {
+			tmp[0] = cpu_to_be32(pci_hose[0].first_busno);
+			tmp[1] = cpu_to_be32(pci_hose[0].last_busno);
+			do_fixup_by_path(blob, path, "bus-range",
+				&tmp, sizeof(tmp), 1);
+
+			tmp[0] = cpu_to_be32(gd->pci_clk);
+			do_fixup_by_path(blob, path, "clock-frequency",
+				&tmp, sizeof(tmp[0]), 1);
+		}
+#endif
+	}
+}
+#elif defined(CONFIG_OF_FLAT_TREE)
 void
 ft_pci_setup(void *blob, bd_t *bd)
 {
diff --git a/cpu/mpc83xx/Makefile b/cpu/mpc83xx/Makefile
index 232997005..94a3cb833 100644
--- a/cpu/mpc83xx/Makefile
+++ b/cpu/mpc83xx/Makefile
@@ -29,7 +29,7 @@ LIB	= $(obj)lib$(CPU).a
 
 START	= start.o
 COBJS	= traps.o cpu.o cpu_init.o speed.o interrupts.o \
-	  spd_sdram.o ecc.o qe_io.o pci.o
+	  spd_sdram.o ecc.o qe_io.o pci.o fdt.o
 
 SRCS	:= $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
diff --git a/cpu/mpc83xx/cpu.c b/cpu/mpc83xx/cpu.c
index 3d3f20a63..bff3cefda 100644
--- a/cpu/mpc83xx/cpu.c
+++ b/cpu/mpc83xx/cpu.c
@@ -31,12 +31,7 @@
 #include <command.h>
 #include <mpc83xx.h>
 #include <asm/processor.h>
-#if defined(CONFIG_OF_FLAT_TREE)
-#include <ft_build.h>
-#elif defined(CONFIG_OF_LIBFDT)
 #include <libfdt.h>
-#include <fdt_support.h>
-#endif
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -359,427 +354,6 @@ void watchdog_reset (void)
 }
 #endif
 
-#if defined(CONFIG_OF_LIBFDT)
-
-/*
- * "Setter" functions used to add/modify FDT entries.
- */
-static int fdt_set_eth0(void *blob, int nodeoffset, const char *name, bd_t *bd)
-{
-	/* Fix it up if it exists, don't create it if it doesn't exist */
-	if (fdt_get_property(blob, nodeoffset, name, 0)) {
-		return fdt_setprop(blob, nodeoffset, name, bd->bi_enetaddr, 6);
-	}
-	return 0;
-}
-#ifdef CONFIG_HAS_ETH1
-/* second onboard ethernet port */
-static int fdt_set_eth1(void *blob, int nodeoffset, const char *name, bd_t *bd)
-{
-	/* Fix it up if it exists, don't create it if it doesn't exist */
-	if (fdt_get_property(blob, nodeoffset, name, 0)) {
-		return fdt_setprop(blob, nodeoffset, name, bd->bi_enet1addr, 6);
-	}
-	return 0;
-}
-#endif
-#ifdef CONFIG_HAS_ETH2
-/* third onboard ethernet port */
-static int fdt_set_eth2(void *blob, int nodeoffset, const char *name, bd_t *bd)
-{
-	/* Fix it up if it exists, don't create it if it doesn't exist */
-	if (fdt_get_property(blob, nodeoffset, name, 0)) {
-		return fdt_setprop(blob, nodeoffset, name, bd->bi_enet2addr, 6);
-	}
-	return 0;
-}
-#endif
-#ifdef CONFIG_HAS_ETH3
-/* fourth onboard ethernet port */
-static int fdt_set_eth3(void *blob, int nodeoffset, const char *name, bd_t *bd)
-{
-	/* Fix it up if it exists, don't create it if it doesn't exist */
-	if (fdt_get_property(blob, nodeoffset, name, 0)) {
-		return fdt_setprop(blob, nodeoffset, name, bd->bi_enet3addr, 6);
-	}
-	return 0;
-}
-#endif
-
-static int fdt_set_busfreq(void *blob, int nodeoffset, const char *name, bd_t *bd)
-{
-	u32  tmp;
-	/* Create or update the property */
-	tmp = cpu_to_be32(bd->bi_busfreq);
-	return fdt_setprop(blob, nodeoffset, name, &tmp, sizeof(tmp));
-}
-
-static int fdt_set_tbfreq(void *blob, int nodeoffset, const char *name, bd_t *bd)
-{
-	u32  tmp;
-	/* Create or update the property */
-	tmp = cpu_to_be32(OF_TBCLK);
-	return fdt_setprop(blob, nodeoffset, name, &tmp, sizeof(tmp));
-}
-
-
-static int fdt_set_clockfreq(void *blob, int nodeoffset, const char *name, bd_t *bd)
-{
-	u32  tmp;
-	/* Create or update the property */
-	tmp = cpu_to_be32(gd->core_clk);
-	return fdt_setprop(blob, nodeoffset, name, &tmp, sizeof(tmp));
-}
-
-#ifdef CONFIG_QE
-static int fdt_set_qe_busfreq(void *blob, int nodeoffset, const char *name, bd_t *bd)
-{
-	u32  tmp;
-	/* Create or update the property */
-	tmp = cpu_to_be32(gd->qe_clk);
-	return fdt_setprop(blob, nodeoffset, name, &tmp, sizeof(tmp));
-}
-
-static int fdt_set_qe_brgfreq(void *blob, int nodeoffset, const char *name, bd_t *bd)
-{
-	u32  tmp;
-	/* Create or update the property */
-	tmp = cpu_to_be32(gd->brg_clk);
-	return fdt_setprop(blob, nodeoffset, name, &tmp, sizeof(tmp));
-}
-#endif
-
-/*
- * Fixups to the fdt.
- */
-static const struct {
-	char *node;
-	char *prop;
-	int (*set_fn)(void *blob, int nodeoffset, const char *name, bd_t *bd);
-} fixup_props[] = {
-	{	"/cpus/" OF_CPU,
-		"timebase-frequency",
-		fdt_set_tbfreq
-	},
-	{	"/cpus/" OF_CPU,
-		"bus-frequency",
-		fdt_set_busfreq
-	},
-	{	"/cpus/" OF_CPU,
-		"clock-frequency",
-		fdt_set_clockfreq
-	},
-	{	"/" OF_SOC,
-		"bus-frequency",
-		fdt_set_busfreq
-	},
-	{	"/" OF_SOC "/serial@4500",
-		"clock-frequency",
-		fdt_set_busfreq
-	},
-	{	"/" OF_SOC "/serial@4600",
-		"clock-frequency",
-		fdt_set_busfreq
-	},
-#ifdef CONFIG_TSEC1
-	{	"/" OF_SOC "/ethernet@24000",
-		"mac-address",
-		fdt_set_eth0
-	},
-	{	"/" OF_SOC "/ethernet@24000",
-		"local-mac-address",
-		fdt_set_eth0
-	},
-#endif
-#ifdef CONFIG_TSEC2
-	{	"/" OF_SOC "/ethernet@25000",
-		"mac-address",
-		fdt_set_eth1
-	},
-	{	"/" OF_SOC "/ethernet@25000",
-		"local-mac-address",
-		fdt_set_eth1
-	},
-#endif
-#ifdef CONFIG_QE
-	{	"/" OF_QE,
-		"brg-frequency",
-		fdt_set_qe_brgfreq
-	},
-	{	"/" OF_QE,
-		"bus-frequency",
-		fdt_set_qe_busfreq
-	},
-#ifdef CONFIG_UEC_ETH1
-#if CFG_UEC1_UCC_NUM == 0  /* UCC1 */
-	{	"/" OF_QE "/ucc@2000",
-		"mac-address",
-		fdt_set_eth0
-	},
-	{	"/" OF_QE "/ucc@2000",
-		"local-mac-address",
-		fdt_set_eth0
-	},
-#elif CFG_UEC1_UCC_NUM == 1  /* UCC2 */
-	{	"/" OF_QE "/ucc@3000",
-		"mac-address",
-		fdt_set_eth0
-	},
-	{	"/" OF_QE "/ucc@3000",
-		"local-mac-address",
-		fdt_set_eth0
-	},
-#elif CFG_UEC1_UCC_NUM == 2  /* UCC3 */
-	{	"/" OF_QE "/ucc@2200",
-		"mac-address",
-		fdt_set_eth0
-	},
-	{	"/" OF_QE "/ucc@2200",
-		"local-mac-address",
-		fdt_set_eth0
-	},
-#elif CFG_UEC1_UCC_NUM == 3  /* UCC4 */
-	{	"/" OF_QE "/ucc@3200",
-		"mac-address",
-		fdt_set_eth0
-	},
-	{	"/" OF_QE "/ucc@3200",
-		"local-mac-address",
-		fdt_set_eth0
-	},
-#endif
-#endif /* CONFIG_UEC_ETH1 */
-#ifdef CONFIG_UEC_ETH2
-#if CFG_UEC2_UCC_NUM == 0  /* UCC1 */
-	{	"/" OF_QE "/ucc@2000",
-		"mac-address",
-		fdt_set_eth1
-	},
-	{	"/" OF_QE "/ucc@2000",
-		"local-mac-address",
-		fdt_set_eth1
-	},
-#elif CFG_UEC2_UCC_NUM == 1  /* UCC2 */
-	{	"/" OF_QE "/ucc@3000",
-		"mac-address",
-		fdt_set_eth1
-	},
-	{	"/" OF_QE "/ucc@3000",
-		"local-mac-address",
-		fdt_set_eth1
-	},
-#elif CFG_UEC2_UCC_NUM == 2  /* UCC3 */
-	{	"/" OF_QE "/ucc@2200",
-		"mac-address",
-		fdt_set_eth1
-	},
-	{	"/" OF_QE "/ucc@2200",
-		"local-mac-address",
-		fdt_set_eth1
-	},
-#elif CFG_UEC2_UCC_NUM == 3  /* UCC4 */
-	{	"/" OF_QE "/ucc@3200",
-		"mac-address",
-		fdt_set_eth1
-	},
-	{	"/" OF_QE "/ucc@3200",
-		"local-mac-address",
-		fdt_set_eth1
-	},
-#endif
-#endif /* CONFIG_UEC_ETH2 */
-#ifdef CONFIG_UEC_ETH3
-#if CFG_UEC3_UCC_NUM == 0  /* UCC1 */
-	{	"/" OF_QE "/ucc@2000",
-		"mac-address",
-		fdt_set_eth2
-	},
-	{	"/" OF_QE "/ucc@2000",
-		"local-mac-address",
-		fdt_set_eth2
-	},
-#elif CFG_UEC3_UCC_NUM == 1  /* UCC2 */
-	{	"/" OF_QE "/ucc@3000",
-		"mac-address",
-		fdt_set_eth2
-	},
-	{	"/" OF_QE "/ucc@3000",
-		"local-mac-address",
-		fdt_set_eth2
-	},
-#elif CFG_UEC3_UCC_NUM == 2  /* UCC3 */
-	{	"/" OF_QE "/ucc@2200",
-		"mac-address",
-		fdt_set_eth2
-	},
-	{	"/" OF_QE "/ucc@2200",
-		"local-mac-address",
-		fdt_set_eth2
-	},
-#elif CFG_UEC3_UCC_NUM == 3  /* UCC4 */
-	{	"/" OF_QE "/ucc@3200",
-		"mac-address",
-		fdt_set_eth2
-	},
-	{	"/" OF_QE "/ucc@3200",
-		"local-mac-address",
-		fdt_set_eth2
-	},
-#endif
-#endif /* CONFIG_UEC_ETH3 */
-#ifdef CONFIG_UEC_ETH4
-#if CFG_UEC4_UCC_NUM == 0  /* UCC1 */
-	{	"/" OF_QE "/ucc@2000",
-		"mac-address",
-		fdt_set_eth3
-	},
-	{	"/" OF_QE "/ucc@2000",
-		"local-mac-address",
-		fdt_set_eth3
-	},
-#elif CFG_UEC4_UCC_NUM == 1  /* UCC2 */
-	{	"/" OF_QE "/ucc@3000",
-		"mac-address",
-		fdt_set_eth3
-	},
-	{	"/" OF_QE "/ucc@3000",
-		"local-mac-address",
-		fdt_set_eth3
-	},
-#elif CFG_UEC4_UCC_NUM == 2  /* UCC3 */
-	{	"/" OF_QE "/ucc@2200",
-		"mac-address",
-		fdt_set_eth3
-	},
-	{	"/" OF_QE "/ucc@2200",
-		"local-mac-address",
-		fdt_set_eth3
-	},
-#elif CFG_UEC4_UCC_NUM == 3  /* UCC4 */
-	{	"/" OF_QE "/ucc@3200",
-		"mac-address",
-		fdt_set_eth3
-	},
-	{	"/" OF_QE "/ucc@3200",
-		"local-mac-address",
-		fdt_set_eth3
-	},
-#endif
-#endif /* CONFIG_UEC_ETH4 */
-#endif /* CONFIG_QE */
-};
-
-void
-ft_cpu_setup(void *blob, bd_t *bd)
-{
-	int nodeoffset;
-	int err;
-	int j;
-
-	for (j = 0; j < (sizeof(fixup_props) / sizeof(fixup_props[0])); j++) {
-		nodeoffset = fdt_path_offset(blob, fixup_props[j].node);
-		if (nodeoffset >= 0) {
-			err = fixup_props[j].set_fn(blob, nodeoffset,
-						    fixup_props[j].prop, bd);
-			if (err < 0)
-				debug("Problem setting %s = %s: %s\n",
-				      fixup_props[j].node, fixup_props[j].prop,
-				      fdt_strerror(err));
-		} else {
-			debug("Couldn't find %s: %s\n",
-			      fixup_props[j].node, fdt_strerror(nodeoffset));
-		}
-	}
-
-	fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
-}
-#elif defined(CONFIG_OF_FLAT_TREE)
-void
-ft_cpu_setup(void *blob, bd_t *bd)
-{
-	u32 *p;
-	int len;
-	ulong clock;
-
-	clock = bd->bi_busfreq;
-	p = ft_get_prop(blob, "/cpus/" OF_CPU "/bus-frequency", &len);
-	if (p != NULL)
-		*p = cpu_to_be32(clock);
-
-	p = ft_get_prop(blob, "/" OF_SOC "/bus-frequency", &len);
-	if (p != NULL)
-		*p = cpu_to_be32(clock);
-
-	p = ft_get_prop(blob, "/" OF_SOC "/serial@4500/clock-frequency", &len);
-	if (p != NULL)
-		*p = cpu_to_be32(clock);
-
-	p = ft_get_prop(blob, "/" OF_SOC "/serial@4600/clock-frequency", &len);
-	if (p != NULL)
-		*p = cpu_to_be32(clock);
-
-#ifdef CONFIG_TSEC1
-	p = ft_get_prop(blob, "/" OF_SOC "/ethernet@24000/mac-address", &len);
-	if (p != NULL)
-		memcpy(p, bd->bi_enetaddr, 6);
-
-	p = ft_get_prop(blob, "/" OF_SOC "/ethernet@24000/local-mac-address", &len);
-	if (p != NULL)
-		memcpy(p, bd->bi_enetaddr, 6);
-#endif
-
-#ifdef CONFIG_TSEC2
-	p = ft_get_prop(blob, "/" OF_SOC "/ethernet@25000/mac-address", &len);
-	if (p != NULL)
-		memcpy(p, bd->bi_enet1addr, 6);
-
-	p = ft_get_prop(blob, "/" OF_SOC "/ethernet@25000/local-mac-address", &len);
-	if (p != NULL)
-		memcpy(p, bd->bi_enet1addr, 6);
-#endif
-
-#ifdef CONFIG_UEC_ETH1
-#if CFG_UEC1_UCC_NUM == 0  /* UCC1 */
-	p = ft_get_prop(blob, "/" OF_QE "/ucc@2000/mac-address", &len);
-	if (p != NULL)
-		memcpy(p, bd->bi_enetaddr, 6);
-
-	p = ft_get_prop(blob, "/" OF_QE "/ucc@2000/local-mac-address", &len);
-	if (p != NULL)
-		memcpy(p, bd->bi_enetaddr, 6);
-#elif CFG_UEC1_UCC_NUM == 2  /* UCC3 */
-	p = ft_get_prop(blob, "/" OF_QE "/ucc@2200/mac-address", &len);
-	if (p != NULL)
-		memcpy(p, bd->bi_enetaddr, 6);
-
-	p = ft_get_prop(blob, "/" OF_QE "/ucc@2200/local-mac-address", &len);
-	if (p != NULL)
-		memcpy(p, bd->bi_enetaddr, 6);
-#endif
-#endif
-
-#ifdef CONFIG_UEC_ETH2
-#if CFG_UEC2_UCC_NUM == 1  /* UCC2 */
-	p = ft_get_prop(blob, "/" OF_QE "/ucc@3000/mac-address", &len);
-	if (p != NULL)
-		memcpy(p, bd->bi_enet1addr, 6);
-
-	p = ft_get_prop(blob, "/" OF_QE "/ucc@3000/local-mac-address", &len);
-	if (p != NULL)
-		memcpy(p, bd->bi_enet1addr, 6);
-#elif CFG_UEC2_UCC_NUM == 3  /* UCC4 */
-	p = ft_get_prop(blob, "/" OF_QE "/ucc@3200/mac-address", &len);
-	if (p != NULL)
-		memcpy(p, bd->bi_enet1addr, 6);
-
-	p = ft_get_prop(blob, "/" OF_QE "/ucc@3200/local-mac-address", &len);
-	if (p != NULL)
-		memcpy(p, bd->bi_enet1addr, 6);
-#endif
-#endif
-}
-#endif
-
 #if defined(CONFIG_DDR_ECC)
 void dma_init(void)
 {
diff --git a/cpu/mpc83xx/fdt.c b/cpu/mpc83xx/fdt.c
new file mode 100644
index 000000000..f21c54e80
--- /dev/null
+++ b/cpu/mpc83xx/fdt.c
@@ -0,0 +1,72 @@
+/*
+ * Copyright 2007 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+#if defined(CONFIG_OF_LIBFDT)
+
+#include <libfdt.h>
+#include <fdt_support.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void ft_cpu_setup(void *blob, bd_t *bd)
+{
+#if defined(CONFIG_HAS_ETH0) || defined(CONFIG_HAS_ETH1) ||\
+    defined(CONFIG_HAS_ETH2) || defined(CONFIG_HAS_ETH3)
+	fdt_fixup_ethernet(blob, bd);
+#endif
+
+	do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
+		"timebase-frequency", (bd->bi_busfreq / 4), 1);
+	do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
+		"bus-frequency", bd->bi_busfreq, 1);
+	do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
+		"clock-frequency", gd->core_clk, 1);
+	do_fixup_by_prop_u32(blob, "device_type", "soc", 4,
+		"bus-frequency", bd->bi_busfreq, 1);
+#ifdef CONFIG_QE
+	do_fixup_by_prop_u32(blob, "device_type", "qe", 4,
+		"bus-frequency", gd->qe_clk, 1);
+	do_fixup_by_prop_u32(blob, "device_type", "qe", 4,
+		"brg-frequency", gd->brg_clk, 1);
+#endif
+
+#ifdef CFG_NS16550
+	do_fixup_by_compat_u32(blob, "ns16550",
+		"clock-frequency", bd->bi_busfreq, 1);
+#endif
+
+#ifdef CONFIG_CPM2
+	do_fixup_by_compat_u32(blob, "fsl,cpm2-scc-uart",
+		"current-speed", bd->bi_baudrate, 1);
+
+	do_fixup_by_compat_u32(blob, "fsl,cpm2-brg",
+		"clock-frequency", bd->bi_brgfreq, 1);
+#endif
+
+	fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
+}
+#endif /* CONFIG_OF_LIBFDT */
diff --git a/cpu/mpc83xx/pci.c b/cpu/mpc83xx/pci.c
index 0defb0ec8..18558db53 100644
--- a/cpu/mpc83xx/pci.c
+++ b/cpu/mpc83xx/pci.c
@@ -28,8 +28,7 @@
 
 #if defined(CONFIG_OF_LIBFDT)
 #include <libfdt.h>
-#elif defined(CONFIG_OF_FLAT_TREE)
-#include <ft_build.h>
+#include <fdt_support.h>
 #endif
 
 #include <asm/mpc8349_pci.h>
@@ -173,63 +172,41 @@ void mpc83xx_pci_init(int num_buses, struct pci_region **reg, int warmboot)
 void ft_pci_setup(void *blob, bd_t *bd)
 {
 	int nodeoffset;
-	int err;
 	int tmp[2];
+	const char *path;
 
 	if (pci_num_buses < 1)
 		return;
 
-	nodeoffset = fdt_path_offset(blob, "/" OF_SOC "/pci@8500");
+	nodeoffset = fdt_path_offset(blob, "/aliases");
 	if (nodeoffset >= 0) {
-		tmp[0] = cpu_to_be32(pci_hose[0].first_busno);
-		tmp[1] = cpu_to_be32(pci_hose[0].last_busno);
-		err = fdt_setprop(blob, nodeoffset, "bus-range",
-				  tmp, sizeof(tmp));
+		path = fdt_getprop(blob, nodeoffset, "pci0", NULL);
+		if (path) {
+			tmp[0] = cpu_to_be32(pci_hose[0].first_busno);
+			tmp[1] = cpu_to_be32(pci_hose[0].last_busno);
+			do_fixup_by_path(blob, path, "bus-range",
+				&tmp, sizeof(tmp), 1);
 
-		tmp[0] = cpu_to_be32(gd->pci_clk);
-		err = fdt_setprop(blob, nodeoffset, "clock-frequency",
-				  tmp, sizeof(tmp[0]));
-	}
+			tmp[0] = cpu_to_be32(gd->pci_clk);
+			do_fixup_by_path(blob, path, "clock-frequency",
+				&tmp, sizeof(tmp[0]), 1);
+		}
 
-	if (pci_num_buses < 2)
-		return;
+		if (pci_num_buses < 2)
+			return;
 
-	nodeoffset = fdt_path_offset(blob, "/" OF_SOC "/pci@8600");
-	if (nodeoffset >= 0) {
-		tmp[0] = cpu_to_be32(pci_hose[0].first_busno);
-		tmp[1] = cpu_to_be32(pci_hose[0].last_busno);
-		err = fdt_setprop(blob, nodeoffset, "bus-range",
-				  tmp, sizeof(tmp));
+		path = fdt_getprop(blob, nodeoffset, "pci1", NULL);
+		if (path) {
+			tmp[0] = cpu_to_be32(pci_hose[0].first_busno);
+			tmp[1] = cpu_to_be32(pci_hose[0].last_busno);
+			do_fixup_by_path(blob, path, "bus-range",
+				&tmp, sizeof(tmp), 1);
 
-		tmp[0] = cpu_to_be32(gd->pci_clk);
-		err = fdt_setprop(blob, nodeoffset, "clock-frequency",
-				  tmp, sizeof(tmp[0]));
+			tmp[0] = cpu_to_be32(gd->pci_clk);
+			do_fixup_by_path(blob, path, "clock-frequency",
+				&tmp, sizeof(tmp[0]), 1);
+		}
 	}
 }
-#elif CONFIG_OF_FLAT_TREE
-void ft_pci_setup(void *blob, bd_t *bd)
-{
-	u32 *p;
-	int len;
-
-	if (pci_num_buses < 1)
-		return;
-
-	p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@8500/bus-range", &len);
-	if (p) {
-		p[0] = pci_hose[0].first_busno;
-		p[1] = pci_hose[0].last_busno;
-	}
-
-	if (pci_num_buses < 2)
-		return;
-
-	p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@8600/bus-range", &len);
-	if (p) {
-		p[0] = pci_hose[1].first_busno;
-		p[1] = pci_hose[1].last_busno;
-	}
-}
-#endif /* CONFIG_OF_FLAT_TREE */
-
+#endif /* CONFIG_OF_LIBFDT */
 #endif /* CONFIG_83XX_GENERIC_PCI */
diff --git a/include/configs/MPC8313ERDB.h b/include/configs/MPC8313ERDB.h
index 0c3bc16c9..c9a9c83f2 100644
--- a/include/configs/MPC8313ERDB.h
+++ b/include/configs/MPC8313ERDB.h
@@ -231,11 +231,7 @@
 /* pass open firmware flat tree */
 #define CONFIG_OF_LIBFDT	1
 #define CONFIG_OF_BOARD_SETUP	1
-
-#define OF_CPU			"PowerPC,8313@0"
-#define OF_SOC			"soc8313@e0000000"
-#define OF_TBCLK		(bd->bi_busfreq / 4)
-#define OF_STDOUT_PATH		"/soc8313@e0000000/serial@4500"
+#define CONFIG_OF_STDOUT_VIA_ALIAS	1
 
 /*
  * Serial Port
diff --git a/include/configs/MPC8323ERDB.h b/include/configs/MPC8323ERDB.h
index 558f94bb7..564de02f5 100644
--- a/include/configs/MPC8323ERDB.h
+++ b/include/configs/MPC8323ERDB.h
@@ -270,12 +270,7 @@
 /* pass open firmware flat tree */
 #define CONFIG_OF_LIBFDT	1
 #define CONFIG_OF_BOARD_SETUP	1
-
-#define OF_CPU			"PowerPC,8323@0"
-#define OF_SOC			"soc8323@e0000000"
-#define OF_QE			"qe@e0100000"
-#define OF_TBCLK		(bd->bi_busfreq / 4)
-#define OF_STDOUT_PATH		"/soc8323@e0000000/serial@4500"
+#define CONFIG_OF_STDOUT_VIA_ALIAS	1
 
 /* I2C */
 #define CONFIG_HARD_I2C		/* I2C with hardware support */
diff --git a/include/configs/MPC832XEMDS.h b/include/configs/MPC832XEMDS.h
index 5345fc62f..a48b3117b 100644
--- a/include/configs/MPC832XEMDS.h
+++ b/include/configs/MPC832XEMDS.h
@@ -321,12 +321,7 @@
 /* pass open firmware flat tree */
 #define CONFIG_OF_LIBFDT	1
 #define CONFIG_OF_BOARD_SETUP	1
-
-#define OF_CPU			"PowerPC,8323@0"
-#define OF_SOC			"soc8323@e0000000"
-#define OF_QE			"qe@e0100000"
-#define OF_TBCLK		(bd->bi_busfreq / 4)
-#define OF_STDOUT_PATH		"/soc8323@e0000000/serial@4500"
+#define CONFIG_OF_STDOUT_VIA_ALIAS	1
 
 /* I2C */
 #define CONFIG_HARD_I2C		/* I2C with hardware support */
diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h
index 7d5b17b50..03409bbba 100644
--- a/include/configs/MPC8349EMDS.h
+++ b/include/configs/MPC8349EMDS.h
@@ -341,11 +341,7 @@
 /* pass open firmware flat tree */
 #define CONFIG_OF_LIBFDT	1
 #define CONFIG_OF_BOARD_SETUP	1
-
-#define OF_CPU			"PowerPC,8349@0"
-#define OF_SOC			"soc8349@e0000000"
-#define OF_TBCLK		(bd->bi_busfreq / 4)
-#define OF_STDOUT_PATH		"/soc8349@e0000000/serial@4500"
+#define CONFIG_OF_STDOUT_VIA_ALIAS	1
 
 /* I2C */
 #define CONFIG_HARD_I2C			/* I2C with hardware support*/
diff --git a/include/configs/MPC8349ITX.h b/include/configs/MPC8349ITX.h
index 2a2e753c8..49dc0de53 100644
--- a/include/configs/MPC8349ITX.h
+++ b/include/configs/MPC8349ITX.h
@@ -298,12 +298,8 @@ boards, we say we have two, but don't display a message if we find only one. */
 
 /* pass open firmware flat tree */
 #define CONFIG_OF_LIBFDT	1
-#define CONFIG_OF_BOARD_SETUP
-
-#define OF_CPU			"PowerPC,8349@0"
-#define OF_SOC			"soc8349@e0000000"
-#define OF_TBCLK		(bd->bi_busfreq / 4)
-#define OF_STDOUT_PATH		"/soc8349@e0000000/serial@4500"
+#define CONFIG_OF_BOARD_SETUP	1
+#define CONFIG_OF_STDOUT_VIA_ALIAS	1
 
 /*
  * PCI
diff --git a/include/configs/MPC8360EMDS.h b/include/configs/MPC8360EMDS.h
index c192f3365..fedb8a9c5 100644
--- a/include/configs/MPC8360EMDS.h
+++ b/include/configs/MPC8360EMDS.h
@@ -347,14 +347,8 @@
 
 /* pass open firmware flat tree */
 #define CONFIG_OF_LIBFDT	1
-#undef  CONFIG_OF_FLAT_TREE
 #define CONFIG_OF_BOARD_SETUP	1
-
-#define OF_CPU			"PowerPC,8360@0"
-#define OF_SOC			"soc8360@e0000000"
-#define OF_QE			"qe@e0100000"
-#define OF_TBCLK		(bd->bi_busfreq / 4)
-#define OF_STDOUT_PATH		"/soc8360@e0000000/serial@4500"
+#define CONFIG_OF_STDOUT_VIA_ALIAS	1
 
 /* I2C */
 #define CONFIG_HARD_I2C		/* I2C with hardware support */
diff --git a/include/configs/MPC837XEMDS.h b/include/configs/MPC837XEMDS.h
index 772fd0238..0958e6b96 100644
--- a/include/configs/MPC837XEMDS.h
+++ b/include/configs/MPC837XEMDS.h
@@ -297,11 +297,7 @@
 /* Pass open firmware flat tree */
 #define CONFIG_OF_LIBFDT	1
 #define CONFIG_OF_BOARD_SETUP	1
-
-#define OF_CPU			"PowerPC,837x@0"
-#define OF_SOC			"soc837x@e0000000"
-#define OF_TBCLK		(bd->bi_busfreq / 4)
-#define OF_STDOUT_PATH		"/soc837x@e0000000/serial@4500"
+#define CONFIG_OF_STDOUT_VIA_ALIAS	1
 
 /* I2C */
 #define CONFIG_HARD_I2C		/* I2C with hardware support */
diff --git a/include/configs/sbc8349.h b/include/configs/sbc8349.h
index 45f20dc12..9efe3c49d 100644
--- a/include/configs/sbc8349.h
+++ b/include/configs/sbc8349.h
@@ -312,11 +312,7 @@
 /* pass open firmware flat tree */
 #define CONFIG_OF_LIBFDT	1
 #define CONFIG_OF_BOARD_SETUP	1
-
-#define OF_CPU			"PowerPC,8349@0"
-#define OF_SOC			"soc8349@e0000000"
-#define OF_TBCLK		(bd->bi_busfreq / 4)
-#define OF_STDOUT_PATH		"/soc8349@e0000000/serial@4500"
+#define CONFIG_OF_STDOUT_VIA_ALIAS	1
 
 /* I2C */
 #define CONFIG_HARD_I2C			/* I2C with hardware support*/

From b3458d2cd55d01732e30a76d898afd99e871cd67 Mon Sep 17 00:00:00 2001
From: Kim Phillips <kim.phillips@freescale.com>
Date: Thu, 20 Dec 2007 15:57:28 -0600
Subject: [PATCH 062/108] mpc83xx: remove FLAT_TREE code

need to rm it from pci code, too!

Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
---
 board/freescale/mpc8313erdb/mpc8313erdb.c | 14 +-------------
 board/freescale/mpc8323erdb/mpc8323erdb.c | 10 ----------
 board/freescale/mpc832xemds/mpc832xemds.c | 14 +-------------
 board/freescale/mpc832xemds/pci.c         |  3 ---
 board/freescale/mpc8349emds/mpc8349emds.c | 14 +-------------
 board/freescale/mpc8349itx/mpc8349itx.c   | 14 +-------------
 board/freescale/mpc8360emds/mpc8360emds.c | 13 +------------
 board/freescale/mpc837xemds/mpc837xemds.c | 14 +-------------
 board/sbc8349/sbc8349.c                   | 14 +-------------
 9 files changed, 7 insertions(+), 103 deletions(-)

diff --git a/board/freescale/mpc8313erdb/mpc8313erdb.c b/board/freescale/mpc8313erdb/mpc8313erdb.c
index 861c143df..42019fb80 100644
--- a/board/freescale/mpc8313erdb/mpc8313erdb.c
+++ b/board/freescale/mpc8313erdb/mpc8313erdb.c
@@ -23,9 +23,7 @@
  */
 
 #include <common.h>
-#if defined(CONFIG_OF_FLAT_TREE)
-#include <ft_build.h>
-#elif defined(CONFIG_OF_LIBFDT)
+#if defined(CONFIG_OF_LIBFDT)
 #include <libfdt.h>
 #endif
 #include <pci.h>
@@ -103,16 +101,6 @@ void pci_init_board(void)
 #if defined(CONFIG_OF_BOARD_SETUP)
 void ft_board_setup(void *blob, bd_t *bd)
 {
-#if defined(CONFIG_OF_FLAT_TREE)
-	u32 *p;
-	int len;
-
-	p = ft_get_prop(blob, "/memory/reg", &len);
-	if (p != NULL) {
-		*p++ = cpu_to_be32(bd->bi_memstart);
-		*p = cpu_to_be32(bd->bi_memsize);
-	}
-#endif
 	ft_cpu_setup(blob, bd);
 #ifdef CONFIG_PCI
 	ft_pci_setup(blob, bd);
diff --git a/board/freescale/mpc8323erdb/mpc8323erdb.c b/board/freescale/mpc8323erdb/mpc8323erdb.c
index e73861300..2fc4fd6cb 100644
--- a/board/freescale/mpc8323erdb/mpc8323erdb.c
+++ b/board/freescale/mpc8323erdb/mpc8323erdb.c
@@ -184,16 +184,6 @@ void pci_init_board(void)
 #if defined(CONFIG_OF_BOARD_SETUP)
 void ft_board_setup(void *blob, bd_t *bd)
 {
-#if defined(CONFIG_OF_FLAT_TREE)
-	u32 *p;
-	int len;
-
-	p = ft_get_prop(blob, "/memory/reg", &len);
-	if (p != NULL) {
-		*p++ = cpu_to_be32(bd->bi_memstart);
-		*p = cpu_to_be32(bd->bi_memsize);
-	}
-#endif
 	ft_cpu_setup(blob, bd);
 #ifdef CONFIG_PCI
 	ft_pci_setup(blob, bd);
diff --git a/board/freescale/mpc832xemds/mpc832xemds.c b/board/freescale/mpc832xemds/mpc832xemds.c
index 6ba25d464..6adf7e7b7 100644
--- a/board/freescale/mpc832xemds/mpc832xemds.c
+++ b/board/freescale/mpc832xemds/mpc832xemds.c
@@ -27,9 +27,7 @@
 #else
 #include <asm/mmu.h>
 #endif
-#if defined(CONFIG_OF_FLAT_TREE)
-#include <ft_build.h>
-#elif defined(CONFIG_OF_LIBFDT)
+#if defined(CONFIG_OF_LIBFDT)
 #include <libfdt.h>
 #endif
 #if defined(CONFIG_PQ_MDS_PIB)
@@ -169,16 +167,6 @@ int checkboard(void)
 #if defined(CONFIG_OF_BOARD_SETUP)
 void ft_board_setup(void *blob, bd_t *bd)
 {
-#if defined(CONFIG_OF_FLAT_TREE)
-	u32 *p;
-	int len;
-
-	p = ft_get_prop(blob, "/memory/reg", &len);
-	if (p != NULL) {
-		*p++ = cpu_to_be32(bd->bi_memstart);
-		*p = cpu_to_be32(bd->bi_memsize);
-	}
-#endif
 	ft_cpu_setup(blob, bd);
 #ifdef CONFIG_PCI
 	ft_pci_setup(blob, bd);
diff --git a/board/freescale/mpc832xemds/pci.c b/board/freescale/mpc832xemds/pci.c
index d50b78aa8..21641d439 100644
--- a/board/freescale/mpc832xemds/pci.c
+++ b/board/freescale/mpc832xemds/pci.c
@@ -269,9 +269,6 @@ void ft_pci_setup(void *blob, bd_t *bd)
 	int tmp[2];
 	const char *path;
 
-	if (pci_num_buses < 1)
-		return;
-
 	nodeoffset = fdt_path_offset(blob, "/aliases");
 	if (nodeoffset >= 0) {
 		path = fdt_getprop(blob, nodeoffset, "pci0", NULL);
diff --git a/board/freescale/mpc8349emds/mpc8349emds.c b/board/freescale/mpc8349emds/mpc8349emds.c
index 39c091627..3d72eb7d8 100644
--- a/board/freescale/mpc8349emds/mpc8349emds.c
+++ b/board/freescale/mpc8349emds/mpc8349emds.c
@@ -32,9 +32,7 @@
 #if defined(CONFIG_SPD_EEPROM)
 #include <spd_sdram.h>
 #endif
-#if defined(CONFIG_OF_FLAT_TREE)
-#include <ft_build.h>
-#elif defined(CONFIG_OF_LIBFDT)
+#if defined(CONFIG_OF_LIBFDT)
 #include <libfdt.h>
 #endif
 
@@ -256,16 +254,6 @@ void sdram_init(void)
 #if defined(CONFIG_OF_BOARD_SETUP)
 void ft_board_setup(void *blob, bd_t *bd)
 {
-#if defined(CONFIG_OF_FLAT_TREE)
-	u32 *p;
-	int len;
-
-	p = ft_get_prop(blob, "/memory/reg", &len);
-	if (p != NULL) {
-		*p++ = cpu_to_be32(bd->bi_memstart);
-		*p = cpu_to_be32(bd->bi_memsize);
-	}
-#endif
 	ft_cpu_setup(blob, bd);
 #ifdef CONFIG_PCI
 	ft_pci_setup(blob, bd);
diff --git a/board/freescale/mpc8349itx/mpc8349itx.c b/board/freescale/mpc8349itx/mpc8349itx.c
index c82f7847a..8c19ad6c9 100644
--- a/board/freescale/mpc8349itx/mpc8349itx.c
+++ b/board/freescale/mpc8349itx/mpc8349itx.c
@@ -37,9 +37,7 @@
 #else
 #include <asm/mmu.h>
 #endif
-#if defined(CONFIG_OF_FLAT_TREE)
-#include <ft_build.h>
-#elif defined(CONFIG_OF_LIBFDT)
+#if defined(CONFIG_OF_LIBFDT)
 #include <libfdt.h>
 #endif
 
@@ -389,16 +387,6 @@ int misc_init_r(void)
 #if defined(CONFIG_OF_BOARD_SETUP)
 void ft_board_setup(void *blob, bd_t *bd)
 {
-#if defined(CONFIG_OF_FLAT_TREE)
-	u32 *p;
-	int len;
-
-	p = ft_get_prop(blob, "/memory/reg", &len);
-	if (p != NULL) {
-		*p++ = cpu_to_be32(bd->bi_memstart);
-		*p = cpu_to_be32(bd->bi_memsize);
-	}
-#endif
 	ft_cpu_setup(blob, bd);
 #ifdef CONFIG_PCI
 	ft_pci_setup(blob, bd);
diff --git a/board/freescale/mpc8360emds/mpc8360emds.c b/board/freescale/mpc8360emds/mpc8360emds.c
index a899800a8..2fcef8b4d 100644
--- a/board/freescale/mpc8360emds/mpc8360emds.c
+++ b/board/freescale/mpc8360emds/mpc8360emds.c
@@ -25,9 +25,7 @@
 #else
 #include <asm/mmu.h>
 #endif
-#if defined(CONFIG_OF_FLAT_TREE)
-#include <ft_build.h>
-#elif defined(CONFIG_OF_LIBFDT)
+#if defined(CONFIG_OF_LIBFDT)
 #include <libfdt.h>
 #endif
 #if defined(CONFIG_PQ_MDS_PIB)
@@ -304,16 +302,7 @@ void sdram_init(void)
 void ft_board_setup(void *blob, bd_t *bd)
 {
 	const immap_t *immr = (immap_t *)CFG_IMMR;
-#if defined(CONFIG_OF_FLAT_TREE)
-	u32 *p;
-	int len;
 
-	p = ft_get_prop(blob, "/memory/reg", &len);
-	if (p != NULL) {
-		*p++ = cpu_to_be32(bd->bi_memstart);
-		*p = cpu_to_be32(bd->bi_memsize);
-	}
-#endif
 	ft_cpu_setup(blob, bd);
 #ifdef CONFIG_PCI
 	ft_pci_setup(blob, bd);
diff --git a/board/freescale/mpc837xemds/mpc837xemds.c b/board/freescale/mpc837xemds/mpc837xemds.c
index 0e4ec0213..6925d23b3 100644
--- a/board/freescale/mpc837xemds/mpc837xemds.c
+++ b/board/freescale/mpc837xemds/mpc837xemds.c
@@ -16,9 +16,7 @@
 #if defined(CONFIG_SPD_EEPROM)
 #include <spd_sdram.h>
 #endif
-#if defined(CONFIG_OF_FLAT_TREE)
-#include <ft_build.h>
-#elif defined(CONFIG_OF_LIBFDT)
+#if defined(CONFIG_OF_LIBFDT)
 #include <libfdt.h>
 #endif
 #if defined(CONFIG_PQ_MDS_PIB)
@@ -126,16 +124,6 @@ int checkboard(void)
 #if defined(CONFIG_OF_BOARD_SETUP)
 void ft_board_setup(void *blob, bd_t *bd)
 {
-#if defined(CONFIG_OF_FLAT_TREE)
-	u32 *p;
-	int len;
-
-	p = ft_get_prop(blob, "/memory/reg", &len);
-	if (p != NULL) {
-		*p++ = cpu_to_be32(bd->bi_memstart);
-		*p = cpu_to_be32(bd->bi_memsize);
-	}
-#endif
 	ft_cpu_setup(blob, bd);
 #ifdef CONFIG_PCI
 	ft_pci_setup(blob, bd);
diff --git a/board/sbc8349/sbc8349.c b/board/sbc8349/sbc8349.c
index 097ab8043..5446c205e 100644
--- a/board/sbc8349/sbc8349.c
+++ b/board/sbc8349/sbc8349.c
@@ -35,9 +35,7 @@
 #if defined(CONFIG_SPD_EEPROM)
 #include <spd_sdram.h>
 #endif
-#if defined(CONFIG_OF_FLAT_TREE)
-#include <ft_build.h>
-#elif defined(CONFIG_OF_LIBFDT)
+#if defined(CONFIG_OF_LIBFDT)
 #include <libfdt.h>
 #endif
 
@@ -239,16 +237,6 @@ void sdram_init(void)
 #if defined(CONFIG_OF_BOARD_SETUP)
 void ft_board_setup(void *blob, bd_t *bd)
 {
-#if defined(CONFIG_OF_FLAT_TREE)
-	u32 *p;
-	int len;
-
-	p = ft_get_prop(blob, "/memory/reg", &len);
-	if (p != NULL) {
-		*p++ = cpu_to_be32(bd->bi_memstart);
-		*p = cpu_to_be32(bd->bi_memsize);
-	}
-#endif
 	ft_cpu_setup(blob, bd);
 #ifdef CONFIG_PCI
 	ft_pci_setup(blob, bd);

From 94fab25f5f1a7d1c0cc63c17e813ea8943fe49c7 Mon Sep 17 00:00:00 2001
From: Kim Phillips <kim.phillips@freescale.com>
Date: Thu, 20 Dec 2007 16:28:34 -0600
Subject: [PATCH 063/108] mpc83xx: rm remaining FLAT_TREE code

..in board pci.c files

Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
---
 board/freescale/mpc832xemds/pci.c | 19 ++-----------------
 board/freescale/mpc8349emds/pci.c | 27 ++-------------------------
 board/freescale/mpc8349itx/pci.c  | 27 ++-------------------------
 board/freescale/mpc8360emds/pci.c | 19 ++-----------------
 board/sbc8349/pci.c               | 27 ++-------------------------
 5 files changed, 10 insertions(+), 109 deletions(-)

diff --git a/board/freescale/mpc832xemds/pci.c b/board/freescale/mpc832xemds/pci.c
index 21641d439..f1f654fd7 100644
--- a/board/freescale/mpc832xemds/pci.c
+++ b/board/freescale/mpc832xemds/pci.c
@@ -18,9 +18,7 @@
 #include <common.h>
 #include <pci.h>
 #include <i2c.h>
-#if defined(CONFIG_OF_FLAT_TREE)
-#include <ft_build.h>
-#elif defined(CONFIG_OF_LIBFDT)
+#if defined(CONFIG_OF_LIBFDT)
 #include <libfdt.h>
 #include <fdt_support.h>
 #endif
@@ -284,18 +282,5 @@ void ft_pci_setup(void *blob, bd_t *bd)
 		}
 	}
 }
-#elif defined(CONFIG_OF_FLAT_TREE)
-void
-ft_pci_setup(void *blob, bd_t *bd)
-{
-	u32 *p;
-	int len;
-
-	p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@8500/bus-range", &len);
-	if (p != NULL) {
-		p[0] = hose[0].first_busno;
-		p[1] = hose[0].last_busno;
-	}
-}
-#endif				/* CONFIG_OF_FLAT_TREE */
+#endif				/* CONFIG_OF_LIBFDT */
 #endif				/* CONFIG_PCI */
diff --git a/board/freescale/mpc8349emds/pci.c b/board/freescale/mpc8349emds/pci.c
index 3eaf77a59..564e436f8 100644
--- a/board/freescale/mpc8349emds/pci.c
+++ b/board/freescale/mpc8349emds/pci.c
@@ -25,9 +25,7 @@
 #include <pci.h>
 #include <asm/mpc8349_pci.h>
 #include <i2c.h>
-#if defined(CONFIG_OF_FLAT_TREE)
-#include <ft_build.h>
-#elif defined(CONFIG_OF_LIBFDT)
+#if defined(CONFIG_OF_LIBFDT)
 #include <libfdt.h>
 #include <fdt_support.h>
 #endif
@@ -424,26 +422,5 @@ void ft_pci_setup(void *blob, bd_t *bd)
 #endif
 	}
 }
-#elif defined(CONFIG_OF_FLAT_TREE)
-void
-ft_pci_setup(void *blob, bd_t *bd)
-{
-       	u32 *p;
-       	int len;
-
-       	p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@8500/bus-range", &len);
-       	if (p != NULL) {
-		p[0] = pci_hose[0].first_busno;
-		p[1] = pci_hose[0].last_busno;
-       	}
-
-#ifdef CONFIG_MPC83XX_PCI2
-	p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@8600/bus-range", &len);
-	if (p != NULL) {
-		p[0] = pci_hose[1].first_busno;
-		p[1] = pci_hose[1].last_busno;
-	}
-#endif
-}
-#endif /* CONFIG_OF_FLAT_TREE */
+#endif /* CONFIG_OF_LIBFDT */
 #endif /* CONFIG_PCI */
diff --git a/board/freescale/mpc8349itx/pci.c b/board/freescale/mpc8349itx/pci.c
index a6bb101b4..d33edf367 100644
--- a/board/freescale/mpc8349itx/pci.c
+++ b/board/freescale/mpc8349itx/pci.c
@@ -29,9 +29,7 @@
 #include <pci.h>
 #include <asm/mpc8349_pci.h>
 #include <i2c.h>
-#if defined(CONFIG_OF_FLAT_TREE)
-#include <ft_build.h>
-#elif defined(CONFIG_OF_LIBFDT)
+#if defined(CONFIG_OF_LIBFDT)
 #include <libfdt.h>
 #include <fdt_support.h>
 #endif
@@ -370,26 +368,5 @@ void ft_pci_setup(void *blob, bd_t *bd)
 #endif
 	}
 }
-#elif defined(CONFIG_OF_FLAT_TREE)
-void
-ft_pci_setup(void *blob, bd_t *bd)
-{
-       	u32 *p;
-       	int len;
-
-       	p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@8500/bus-range", &len);
-       	if (p != NULL) {
-		p[0] = pci_hose[0].first_busno;
-		p[1] = pci_hose[0].last_busno;
-       	}
-
-#ifdef CONFIG_MPC83XX_PCI2
-	p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@8600/bus-range", &len);
-	if (p != NULL) {
-		p[0] = pci_hose[1].first_busno;
-		p[1] = pci_hose[1].last_busno;
-	}
-#endif
-}
-#endif /* CONFIG_OF_FLAT_TREE */
+#endif /* CONFIG_OF_LIBFDT */
 #endif /* CONFIG_PCI */
diff --git a/board/freescale/mpc8360emds/pci.c b/board/freescale/mpc8360emds/pci.c
index 64cb8ade6..89d2225d4 100644
--- a/board/freescale/mpc8360emds/pci.c
+++ b/board/freescale/mpc8360emds/pci.c
@@ -18,9 +18,7 @@
 #include <common.h>
 #include <pci.h>
 #include <i2c.h>
-#if defined(CONFIG_OF_FLAT_TREE)
-#include <ft_build.h>
-#elif defined(CONFIG_OF_LIBFDT)
+#if defined(CONFIG_OF_LIBFDT)
 #include <libfdt.h>
 #include <fdt_support.h>
 #endif
@@ -284,18 +282,5 @@ void ft_pci_setup(void *blob, bd_t *bd)
 		}
 	}
 }
-#elif defined(CONFIG_OF_FLAT_TREE)
-void
-ft_pci_setup(void *blob, bd_t *bd)
-{
-	u32 *p;
-	int len;
-
-	p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@8500/bus-range", &len);
-	if (p != NULL) {
-		p[0] = hose[0].first_busno;
-		p[1] = hose[0].last_busno;
-	}
-}
-#endif				/* CONFIG_OF_FLAT_TREE */
+#endif				/* CONFIG_OF_LIBFDT */
 #endif				/* CONFIG_PCI */
diff --git a/board/sbc8349/pci.c b/board/sbc8349/pci.c
index e59f9f9a5..527f7e434 100644
--- a/board/sbc8349/pci.c
+++ b/board/sbc8349/pci.c
@@ -30,9 +30,7 @@
 #include <pci.h>
 #include <asm/mpc8349_pci.h>
 #include <i2c.h>
-#if defined(CONFIG_OF_FLAT_TREE)
-#include <ft_build.h>
-#elif defined(CONFIG_OF_LIBFDT)
+#if defined(CONFIG_OF_LIBFDT)
 #include <libfdt.h>
 #include <fdt_support.h>
 #endif
@@ -364,26 +362,5 @@ void ft_pci_setup(void *blob, bd_t *bd)
 #endif
 	}
 }
-#elif defined(CONFIG_OF_FLAT_TREE)
-void
-ft_pci_setup(void *blob, bd_t *bd)
-{
-		u32 *p;
-		int len;
-
-		p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@8500/bus-range", &len);
-		if (p != NULL) {
-			p[0] = pci_hose[0].first_busno;
-			p[1] = pci_hose[0].last_busno;
-		}
-
-#ifdef CONFIG_MPC83XX_PCI2
-	p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@8600/bus-range", &len);
-	if (p != NULL) {
-		p[0] = pci_hose[1].first_busno;
-		p[1] = pci_hose[1].last_busno;
-	}
-#endif
-}
-#endif /* CONFIG_OF_FLAT_TREE */
+#endif /* CONFIG_OF_LIBFDT */
 #endif /* CONFIG_PCI */

From 6775c68683a53c7abc778774641aac6f833a2cbf Mon Sep 17 00:00:00 2001
From: Kim Phillips <kim.phillips@freescale.com>
Date: Tue, 8 Jan 2008 09:59:49 -0600
Subject: [PATCH 064/108] mpc83xx: fix missed pci_hose -> hose conversion for
 new libfdt code

Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
---
 board/freescale/mpc832xemds/pci.c | 4 ++--
 board/freescale/mpc8360emds/pci.c | 4 ++--
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/board/freescale/mpc832xemds/pci.c b/board/freescale/mpc832xemds/pci.c
index f1f654fd7..b0304229d 100644
--- a/board/freescale/mpc832xemds/pci.c
+++ b/board/freescale/mpc832xemds/pci.c
@@ -271,8 +271,8 @@ void ft_pci_setup(void *blob, bd_t *bd)
 	if (nodeoffset >= 0) {
 		path = fdt_getprop(blob, nodeoffset, "pci0", NULL);
 		if (path) {
-			tmp[0] = cpu_to_be32(pci_hose[0].first_busno);
-			tmp[1] = cpu_to_be32(pci_hose[0].last_busno);
+			tmp[0] = cpu_to_be32(hose[0].first_busno);
+			tmp[1] = cpu_to_be32(hose[0].last_busno);
 			do_fixup_by_path(blob, path, "bus-range",
 				&tmp, sizeof(tmp), 1);
 
diff --git a/board/freescale/mpc8360emds/pci.c b/board/freescale/mpc8360emds/pci.c
index 89d2225d4..4a0d460fa 100644
--- a/board/freescale/mpc8360emds/pci.c
+++ b/board/freescale/mpc8360emds/pci.c
@@ -271,8 +271,8 @@ void ft_pci_setup(void *blob, bd_t *bd)
 	if (nodeoffset >= 0) {
 		path = fdt_getprop(blob, nodeoffset, "pci0", NULL);
 		if (path) {
-			tmp[0] = cpu_to_be32(pci_hose[0].first_busno);
-			tmp[1] = cpu_to_be32(pci_hose[0].last_busno);
+			tmp[0] = cpu_to_be32(hose[0].first_busno);
+			tmp[1] = cpu_to_be32(hose[0].last_busno);
 			do_fixup_by_path(blob, path, "bus-range",
 				&tmp, sizeof(tmp), 1);
 

From 802b769bac17b0560d3535a42c502469ee190cd1 Mon Sep 17 00:00:00 2001
From: Stefan Roese <sr@denx.de>
Date: Tue, 8 Jan 2008 18:39:30 +0100
Subject: [PATCH 065/108] ppc4xx: Return 0 on success in 4xx ethernet driver

Signed-off-by: Stefan Roese <sr@denx.de>
---
 cpu/ppc4xx/4xx_enet.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/cpu/ppc4xx/4xx_enet.c b/cpu/ppc4xx/4xx_enet.c
index bfe0864d1..ff707dda5 100644
--- a/cpu/ppc4xx/4xx_enet.c
+++ b/cpu/ppc4xx/4xx_enet.c
@@ -1036,7 +1036,7 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
 	hw_p->bis = bis;
 	hw_p->first_init = 1;
 
-	return (1);
+	return 0;
 }
 
 
@@ -1755,7 +1755,8 @@ int ppc_4xx_eth_initialize (bd_t * bis)
 #endif
 #endif
 	}			/* end for each supported device */
-	return (1);
+
+	return 0;
 }
 
 #if !defined(CONFIG_NET_MULTI)

From 22fb2246df91bfc840d87f0c5910818bad55577a Mon Sep 17 00:00:00 2001
From: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
Date: Fri, 28 Dec 2007 11:56:30 +0100
Subject: [PATCH 066/108] Add fdt_find_and_setprop() to fdt_support.h

fdt_find_and_setprop() is used by several 4xx boards and it's
missing in the appropriate header. This patch eliminates a
warning when building U-Boot for such boards.

Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
Acked-by: Stefan Roese <sr@denx.de>
---
 include/fdt_support.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/include/fdt_support.h b/include/fdt_support.h
index 3d6c1a841..58e26abf8 100644
--- a/include/fdt_support.h
+++ b/include/fdt_support.h
@@ -46,6 +46,8 @@ void do_fixup_by_compat_u32(void *fdt, const char *compat,
 			    const char *prop, u32 val, int create);
 int fdt_fixup_memory(void *blob, u64 start, u64 size);
 void fdt_fixup_ethernet(void *fdt, bd_t *bd);
+int fdt_find_and_setprop(void *fdt, const char *node, const char *prop,
+			 const void *val, int len, int create);
 
 #ifdef CONFIG_OF_HAS_UBOOT_ENV
 int fdt_env(void *fdt);

From ea6d8be153ceaf16958f8009cea6d75f3ff58d92 Mon Sep 17 00:00:00 2001
From: Gerald Van Baren <vanbaren@cideas.com>
Date: Sat, 5 Jan 2008 14:52:04 -0500
Subject: [PATCH 067/108] Support setting FDT properties with optional values.

Fix a bug found and documented by Bartlomiej Sieka where the optional
value on "fdt set <path> <prop> [<val>]" wasn't optional.

=> fdt mknode / testnode
=> fdt print /testnode
testnode {
};
=> fdt set /testnode testprop
=> fdt print /testnode
testnode {
        testprop;
};

Signed-off-by: Gerald Van Baren <vanbaren@cideas.com>
---
 common/cmd_fdt.c | 16 +++++++++-------
 1 file changed, 9 insertions(+), 7 deletions(-)

diff --git a/common/cmd_fdt.c b/common/cmd_fdt.c
index 463912653..74e28b517 100644
--- a/common/cmd_fdt.c
+++ b/common/cmd_fdt.c
@@ -184,23 +184,28 @@ int do_fdt (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
 	} else if (argv[1][0] == 's') {
 		char *pathp;		/* path */
 		char *prop;		/* property */
-		char *newval;		/* value from the user (as a string) */
 		int  nodeoffset;	/* node offset from libfdt */
 		static char data[SCRATCHPAD];	/* storage for the property */
 		int  len;		/* new length of the property */
 		int  ret;		/* return value */
 
 		/*
-		 * Parameters: Node path, property, value.
+		 * Parameters: Node path, property, optional value.
 		 */
-		if (argc < 5) {
+		if (argc < 4) {
 			printf ("Usage:\n%s\n", cmdtp->usage);
 			return 1;
 		}
 
 		pathp  = argv[2];
 		prop   = argv[3];
-		newval = argv[4];
+		if (argc == 4) {
+			len = 0;
+		} else {
+			ret = fdt_parse_prop(pathp, prop, argv[4], data, &len);
+			if (ret != 0)
+				return ret;
+		}
 
 		nodeoffset = fdt_path_offset (fdt, pathp);
 		if (nodeoffset < 0) {
@@ -211,9 +216,6 @@ int do_fdt (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
 				fdt_strerror(nodeoffset));
 			return 1;
 		}
-		ret = fdt_parse_prop(pathp, prop, newval, data, &len);
-		if (ret != 0)
-			return ret;
 
 		ret = fdt_setprop(fdt, nodeoffset, prop, data, len);
 		if (ret < 0) {

From 238cb7a423c6eaa36496efb788cfb9798cea7f95 Mon Sep 17 00:00:00 2001
From: Gerald Van Baren <vanbaren@cideas.com>
Date: Sat, 5 Jan 2008 15:33:29 -0500
Subject: [PATCH 068/108] Improve the FDT help message.

Add a note that "fdt copy" makes the new address active.
Remove most of the extra hints at the end of the fdt help.

Signed-off-by: Gerald Van Baren <vanbaren@cideas.com>
---
 common/cmd_fdt.c | 10 +++-------
 1 file changed, 3 insertions(+), 7 deletions(-)

diff --git a/common/cmd_fdt.c b/common/cmd_fdt.c
index 74e28b517..9cd22ee94 100644
--- a/common/cmd_fdt.c
+++ b/common/cmd_fdt.c
@@ -683,7 +683,7 @@ U_BOOT_CMD(
 #ifdef CONFIG_OF_BOARD_SETUP
 	"fdt boardsetup                      - Do board-specific set up\n"
 #endif
-	"fdt move   <fdt> <newaddr> <length> - Copy the fdt to <addr>\n"
+	"fdt move   <fdt> <newaddr> <length> - Copy the fdt to <addr> and make it active\n"
 	"fdt print  <path> [<prop>]          - Recursive print starting at <path>\n"
 	"fdt list   <path> [<prop>]          - Print one level starting at <path>\n"
 	"fdt set    <path> <prop> [<val>]    - Set <property> [to <val>]\n"
@@ -696,10 +696,6 @@ U_BOOT_CMD(
 #ifdef CONFIG_OF_HAS_BD_T
 	"fdt bd_t   - Add/replace the /bd_t branch in the tree\n"
 #endif
-	"Hints:\n"
-	" If the property you are setting/printing has a '#' character or spaces,\n"
-	"     you MUST escape it with a \\ character or quote it with \".\n"
-	"Examples: fdt print /               # print the whole tree\n"
-	"          fdt print /cpus \"#address-cells\"\n"
-	"          fdt set   /cpus \"#address-cells\" \"[00 00 00 01]\"\n"
+	"NOTE: If the path or property you are setting/printing has a '#' character\n"
+	"     or spaces, you MUST escape it with a \\ character or quote it with \".\n"
 );

From b60af3d4c1680487ee37e11aa1b3db6dec04d8f0 Mon Sep 17 00:00:00 2001
From: Gerald Van Baren <vanbaren@cideas.com>
Date: Sat, 29 Dec 2007 22:45:27 -0500
Subject: [PATCH 069/108] Fine grained per property /chosen updating.

Implement a suggestion by Scott Wood to make the /chosen handling fine
grained.  Don't overwrite pre-existing properties on a per-property basis,
so if /chosen exists but a necessary /chosen/property doesn't, it gets
created.  If a /chosen property exists, it is NOT overwritten unless the
"force" flag is true.

Signed-off-by: Gerald Van Baren <vanbaren@cideas.com>
---
 common/fdt_support.c | 73 ++++++++++++++++++++++++--------------------
 1 file changed, 40 insertions(+), 33 deletions(-)

diff --git a/common/fdt_support.c b/common/fdt_support.c
index b5ee6e960..92f1c7f54 100644
--- a/common/fdt_support.c
+++ b/common/fdt_support.c
@@ -111,6 +111,7 @@ int fdt_chosen(void *fdt, ulong initrd_start, ulong initrd_end, int force)
 	int   err;
 	u32   tmp;		/* used to set 32 bit integer properties */
 	char  *str;		/* used to set string properties */
+	const char *path;
 
 	err = fdt_check_header(fdt);
 	if (err < 0) {
@@ -148,14 +149,7 @@ int fdt_chosen(void *fdt, ulong initrd_start, ulong initrd_end, int force)
 	nodeoffset = fdt_path_offset (fdt, "/chosen");
 
 	/*
-	 * If we have a "chosen" node already the "force the writing"
-	 * is not set, our job is done.
-	 */
-	if ((nodeoffset >= 0) && !force)
-		return 0;
-
-	/*
-	 * No "chosen" node in the blob: create it.
+	 * If there is no "chosen" node in the blob, create it.
 	 */
 	if (nodeoffset < 0) {
 		/*
@@ -170,42 +164,55 @@ int fdt_chosen(void *fdt, ulong initrd_start, ulong initrd_end, int force)
 	}
 
 	/*
-	 * Update pre-existing properties, create them if non-existant.
+	 * Create /chosen properites that don't exist in the fdt.
+	 * If the property exists, update it only if the "force" parameter
+	 * is true.
 	 */
 	str = getenv("bootargs");
 	if (str != NULL) {
-		err = fdt_setprop(fdt, nodeoffset,
-			"bootargs", str, strlen(str)+1);
-		if (err < 0)
-			printf("WARNING: could not set bootargs %s.\n",
-				fdt_strerror(err));
+		path = fdt_getprop(fdt, nodeoffset, "bootargs", NULL);
+		if ((path == NULL) || force) {
+			err = fdt_setprop(fdt, nodeoffset,
+				"bootargs", str, strlen(str)+1);
+			if (err < 0)
+				printf("WARNING: could not set bootargs %s.\n",
+					fdt_strerror(err));
+		}
 	}
 	if (initrd_start && initrd_end) {
-		tmp = __cpu_to_be32(initrd_start);
-		err = fdt_setprop(fdt, nodeoffset,
-			 "linux,initrd-start", &tmp, sizeof(tmp));
-		if (err < 0)
-			printf("WARNING: "
-				"could not set linux,initrd-start %s.\n",
-				fdt_strerror(err));
-		tmp = __cpu_to_be32(initrd_end);
-		err = fdt_setprop(fdt, nodeoffset,
-			"linux,initrd-end", &tmp, sizeof(tmp));
-		if (err < 0)
-			printf("WARNING: could not set linux,initrd-end %s.\n",
-				fdt_strerror(err));
+		path = fdt_getprop(fdt, nodeoffset, "linux,initrd-start", NULL);
+		if ((path == NULL) || force) {
+			tmp = __cpu_to_be32(initrd_start);
+			err = fdt_setprop(fdt, nodeoffset,
+				"linux,initrd-start", &tmp, sizeof(tmp));
+			if (err < 0)
+				printf("WARNING: "
+					"could not set linux,initrd-start %s.\n",
+					fdt_strerror(err));
+			tmp = __cpu_to_be32(initrd_end);
+			err = fdt_setprop(fdt, nodeoffset,
+				"linux,initrd-end", &tmp, sizeof(tmp));
+			if (err < 0)
+				printf("WARNING: could not set linux,initrd-end %s.\n",
+					fdt_strerror(err));
+		}
 	}
 
 #ifdef CONFIG_OF_STDOUT_VIA_ALIAS
-	err = fdt_fixup_stdout(fdt, nodeoffset);
+	path = fdt_getprop(fdt, nodeoffset, "linux,stdout-path", NULL);
+	if ((path == NULL) || force)
+		err = fdt_fixup_stdout(fdt, nodeoffset);
 #endif
 
 #ifdef OF_STDOUT_PATH
-	err = fdt_setprop(fdt, nodeoffset,
-		"linux,stdout-path", OF_STDOUT_PATH, strlen(OF_STDOUT_PATH)+1);
-	if (err < 0)
-		printf("WARNING: could not set linux,stdout-path %s.\n",
-			fdt_strerror(err));
+	path = fdt_getprop(fdt, nodeoffset, "linux,stdout-path", NULL);
+	if ((path == NULL) || force) {
+		err = fdt_setprop(fdt, nodeoffset,
+			"linux,stdout-path", OF_STDOUT_PATH, strlen(OF_STDOUT_PATH)+1);
+		if (err < 0)
+			printf("WARNING: could not set linux,stdout-path %s.\n",
+				fdt_strerror(err));
+	}
 #endif
 
 	return err;

From 9d4450b5adc36623e9c1de1f92539db77ad0c57e Mon Sep 17 00:00:00 2001
From: David Gibson <david@gibson.dropbear.id.au>
Date: Mon, 17 Dec 2007 14:41:52 +1100
Subject: [PATCH 070/108] libfdt: Add more documentation (patch the sixth)

This patch adds some more documenting comments to libfdt.h.
Specifically this documents all the write-in-place functions.

Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
 include/libfdt.h | 104 +++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 104 insertions(+)

diff --git a/include/libfdt.h b/include/libfdt.h
index 805004900..ffac678d9 100644
--- a/include/libfdt.h
+++ b/include/libfdt.h
@@ -655,8 +655,65 @@ int fdt_node_offset_by_compatible(const void *fdt, int startoffset,
 /* Write-in-place functions                                           */
 /**********************************************************************/
 
+/**
+ * fdt_setprop_inplace - change a property's value, but not its size
+ * @fdt: pointer to the device tree blob
+ * @nodeoffset: offset of the node whose property to change
+ * @name: name of the property to change
+ * @val: pointer to data to replace the property value with
+ * @len: length of the property value
+ *
+ * fdt_setprop_inplace() replaces the value of a given property with
+ * the data in val, of length len.  This function cannot change the
+ * size of a property, and so will only work if len is equal to the
+ * current length of the property.
+ *
+ * This function will alter only the bytes in the blob which contain
+ * the given property value, and will not alter or move any other part
+ * of the tree.
+ *
+ * returns:
+ *	0, on success
+ *	-FDT_ERR_NOSPACE, if len is not equal to the property's current length
+ *	-FDT_ERR_NOTFOUND, node does not have the named property
+ *	-FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag
+ *	-FDT_ERR_BADMAGIC,
+ *	-FDT_ERR_BADVERSION,
+ *	-FDT_ERR_BADSTATE,
+ *	-FDT_ERR_BADSTRUCTURE,
+ *	-FDT_ERR_TRUNCATED, standard meanings
+ */
 int fdt_setprop_inplace(void *fdt, int nodeoffset, const char *name,
 			const void *val, int len);
+
+/**
+ * fdt_setprop_inplace_cell - change the value of a single-cell property
+ * @fdt: pointer to the device tree blob
+ * @nodeoffset: offset of the node whose property to change
+ * @name: name of the property to change
+ * @val: cell (32-bit integer) value to replace the property with
+ *
+ * fdt_setprop_inplace_cell() replaces the value of a given property
+ * with the 32-bit integer cell value in val, converting val to
+ * big-endian if necessary.  This function cannot change the size of a
+ * property, and so will only work if the property already exists and
+ * has length 4.
+ *
+ * This function will alter only the bytes in the blob which contain
+ * the given property value, and will not alter or move any other part
+ * of the tree.
+ *
+ * returns:
+ *	0, on success
+ *	-FDT_ERR_NOSPACE, if the property's length is not equal to 4
+  *	-FDT_ERR_NOTFOUND, node does not have the named property
+ *	-FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag
+ *	-FDT_ERR_BADMAGIC,
+ *	-FDT_ERR_BADVERSION,
+ *	-FDT_ERR_BADSTATE,
+ *	-FDT_ERR_BADSTRUCTURE,
+ *	-FDT_ERR_TRUNCATED, standard meanings
+ */
 static inline int fdt_setprop_inplace_cell(void *fdt, int nodeoffset,
 					   const char *name, uint32_t val)
 {
@@ -664,7 +721,54 @@ static inline int fdt_setprop_inplace_cell(void *fdt, int nodeoffset,
 	return fdt_setprop_inplace(fdt, nodeoffset, name, &val, sizeof(val));
 }
 
+/**
+ * fdt_nop_property - replace a property with nop tags
+ * @fdt: pointer to the device tree blob
+ * @nodeoffset: offset of the node whose property to nop
+ * @name: name of the property to nop
+ *
+ * fdt_nop_property() will replace a given property's representation
+ * in the blob with FDT_NOP tags, effectively removing it from the
+ * tree.
+ *
+ * This function will alter only the bytes in the blob which contain
+ * the property, and will not alter or move any other part of the
+ * tree.
+ *
+ * returns:
+ *	0, on success
+ *	-FDT_ERR_NOTFOUND, node does not have the named property
+ *	-FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag
+ *	-FDT_ERR_BADMAGIC,
+ *	-FDT_ERR_BADVERSION,
+ *	-FDT_ERR_BADSTATE,
+ *	-FDT_ERR_BADSTRUCTURE,
+ *	-FDT_ERR_TRUNCATED, standard meanings
+ */
 int fdt_nop_property(void *fdt, int nodeoffset, const char *name);
+
+/**
+ * fdt_nop_node - replace a node (subtree) with nop tags
+ * @fdt: pointer to the device tree blob
+ * @nodeoffset: offset of the node to nop
+ *
+ * fdt_nop_node() will replace a given node's representation in the
+ * blob, including all its subnodes, if any, with FDT_NOP tags,
+ * effectively removing it from the tree.
+ *
+ * This function will alter only the bytes in the blob which contain
+ * the node and its properties and subnodes, and will not alter or
+ * move any other part of the tree.
+ *
+ * returns:
+ *	0, on success
+ *	-FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag
+ *	-FDT_ERR_BADMAGIC,
+ *	-FDT_ERR_BADVERSION,
+ *	-FDT_ERR_BADSTATE,
+ *	-FDT_ERR_BADSTRUCTURE,
+ *	-FDT_ERR_TRUNCATED, standard meanings
+ */
 int fdt_nop_node(void *fdt, int nodeoffset);
 
 /**********************************************************************/

From aec7135bc300e3340d18f203347ee00c5b5f68c0 Mon Sep 17 00:00:00 2001
From: David Gibson <david@gibson.dropbear.id.au>
Date: Mon, 17 Dec 2007 14:42:07 +1100
Subject: [PATCH 071/108] libfdt: Add more documentation (patch the seventh)

This patch adds more documenting comments to libfdt.h.  Specifically,
these document the read/write functions (not including fdt_open_into()
and fdt_pack(), for now).

Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
 include/libfdt.h | 219 +++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 219 insertions(+)

diff --git a/include/libfdt.h b/include/libfdt.h
index ffac678d9..6c0523685 100644
--- a/include/libfdt.h
+++ b/include/libfdt.h
@@ -797,23 +797,242 @@ int fdt_finish(void *fdt);
 int fdt_open_into(const void *fdt, void *buf, int bufsize);
 int fdt_pack(void *fdt);
 
+/**
+ * fdt_add_mem_rsv - add one memory reserve map entry
+ * @fdt: pointer to the device tree blob
+ * @addres, @size: 64-bit values (native endian)
+ *
+ * Adds a reserve map entry to the given blob reserving a region at
+ * address address of length size.
+ *
+ * This function will insert data into the reserve map and will
+ * therfore change the indexes of some entries in the table.
+ *
+ * returns:
+ *	0, on success
+ *	-FDT_ERR_NOSPACE, there is insufficient free space in the blob to
+ *		contain the new reservation entry
+ *	-FDT_ERR_BADMAGIC,
+ *	-FDT_ERR_BADVERSION,
+ *	-FDT_ERR_BADSTATE,
+ *	-FDT_ERR_BADSTRUCTURE,
+ *	-FDT_ERR_BADLAYOUT,
+ *	-FDT_ERR_TRUNCATED, standard meanings
+ */
 int fdt_add_mem_rsv(void *fdt, uint64_t address, uint64_t size);
+
+/**
+ * fdt_del_mem_rsv - remove a memory reserve map entry
+ * @fdt: pointer to the device tree blob
+ * @n: entry to remove
+ *
+ * fdt_del_mem_rsv() removes the n-th memory reserve map entry from
+ * the blob.
+ *
+ * This function will delete data from the reservation table and will
+ * therfore change the indexes of some entries in the table.
+ *
+ * returns:
+ *	0, on success
+ *	-FDT_ERR_NOTFOUND, there is no entry of the given index (i.e. there
+ *		are less than n+1 reserve map entries)
+ *	-FDT_ERR_BADMAGIC,
+ *	-FDT_ERR_BADVERSION,
+ *	-FDT_ERR_BADSTATE,
+ *	-FDT_ERR_BADSTRUCTURE,
+ *	-FDT_ERR_BADLAYOUT,
+ *	-FDT_ERR_TRUNCATED, standard meanings
+ */
 int fdt_del_mem_rsv(void *fdt, int n);
 
+/**
+ * fdt_setprop - create or change a property
+ * @fdt: pointer to the device tree blob
+ * @nodeoffset: offset of the node whose property to change
+ * @name: name of the property to change
+ * @val: pointer to data to set the property value to
+ * @len: length of the property value
+ *
+ * fdt_setprop() sets the value of the named property in the given
+ * node to the given value and length, creeating the property if it
+ * does not already exist.
+ *
+ * This function may insert or delete data from the blob, and will
+ * therefore change the offsets of some existing nodes.
+ *
+ * returns:
+ *	0, on success
+ *	-FDT_ERR_NOSPACE, there is insufficient free space in the blob to
+ *		contain the new property value
+ *	-FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag
+ *	-FDT_ERR_BADLAYOUT,
+ *	-FDT_ERR_BADMAGIC,
+ *	-FDT_ERR_BADVERSION,
+ *	-FDT_ERR_BADSTATE,
+ *	-FDT_ERR_BADSTRUCTURE,
+ *	-FDT_ERR_BADLAYOUT,
+ *	-FDT_ERR_TRUNCATED, standard meanings
+ */
 int fdt_setprop(void *fdt, int nodeoffset, const char *name,
 		const void *val, int len);
+
+/**
+ * fdt_setprop_cell - set a property to a single cell value
+ * @fdt: pointer to the device tree blob
+ * @nodeoffset: offset of the node whose property to change
+ * @name: name of the property to change
+ * @val: 32-bit integer value for the property (native endian)
+ *
+ * fdt_setprop_cell() sets the value of the named property in the
+ * given node to the given cell value (converting to big-endian if
+ * necessary), or creates a new property with that value if it does
+ * not already exist.
+ *
+ * This function may insert or delete data from the blob, and will
+ * therefore change the offsets of some existing nodes.
+ *
+ * returns:
+ *	0, on success
+ *	-FDT_ERR_NOSPACE, there is insufficient free space in the blob to
+ *		contain the new property value
+ *	-FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag
+ *	-FDT_ERR_BADLAYOUT,
+ *	-FDT_ERR_BADMAGIC,
+ *	-FDT_ERR_BADVERSION,
+ *	-FDT_ERR_BADSTATE,
+ *	-FDT_ERR_BADSTRUCTURE,
+ *	-FDT_ERR_BADLAYOUT,
+ *	-FDT_ERR_TRUNCATED, standard meanings
+ */
 static inline int fdt_setprop_cell(void *fdt, int nodeoffset, const char *name,
 				   uint32_t val)
 {
 	val = cpu_to_fdt32(val);
 	return fdt_setprop(fdt, nodeoffset, name, &val, sizeof(val));
 }
+
+/**
+ * fdt_setprop_string - set a property to a string value
+ * @fdt: pointer to the device tree blob
+ * @nodeoffset: offset of the node whose property to change
+ * @name: name of the property to change
+ * @str: string value for the property
+ *
+ * fdt_setprop_string() sets the value of the named property in the
+ * given node to the given string value (using the length of the
+ * string to determine the new length of the property), or creates a
+ * new property with that value if it does not already exist.
+ *
+ * This function may insert or delete data from the blob, and will
+ * therefore change the offsets of some existing nodes.
+ *
+ * returns:
+ *	0, on success
+ *	-FDT_ERR_NOSPACE, there is insufficient free space in the blob to
+ *		contain the new property value
+ *	-FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag
+ *	-FDT_ERR_BADLAYOUT,
+ *	-FDT_ERR_BADMAGIC,
+ *	-FDT_ERR_BADVERSION,
+ *	-FDT_ERR_BADSTATE,
+ *	-FDT_ERR_BADSTRUCTURE,
+ *	-FDT_ERR_BADLAYOUT,
+ *	-FDT_ERR_TRUNCATED, standard meanings
+ */
 #define fdt_setprop_string(fdt, nodeoffset, name, str) \
 	fdt_setprop((fdt), (nodeoffset), (name), (str), strlen(str)+1)
+
+/**
+ * fdt_delprop - delete a property
+ * @fdt: pointer to the device tree blob
+ * @nodeoffset: offset of the node whose property to nop
+ * @name: name of the property to nop
+ *
+ * fdt_del_property() will delete the given property.
+ *
+ * This function will delete data from the blob, and will therefore
+ * change the offsets of some existing nodes.
+ *
+ * returns:
+ *	0, on success
+ *	-FDT_ERR_NOTFOUND, node does not have the named property
+ *	-FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag
+ *	-FDT_ERR_BADLAYOUT,
+ *	-FDT_ERR_BADMAGIC,
+ *	-FDT_ERR_BADVERSION,
+ *	-FDT_ERR_BADSTATE,
+ *	-FDT_ERR_BADSTRUCTURE,
+ *	-FDT_ERR_TRUNCATED, standard meanings
+ */
 int fdt_delprop(void *fdt, int nodeoffset, const char *name);
+
+/**
+ * fdt_add_subnode_namelen - creates a new node based on substring
+ * @fdt: pointer to the device tree blob
+ * @parentoffset: structure block offset of a node
+ * @name: name of the subnode to locate
+ * @namelen: number of characters of name to consider
+ *
+ * Identical to fdt_add_subnode(), but use only the first namelen
+ * characters of name as the name of the new node.  This is useful for
+ * creating subnodes based on a portion of a larger string, such as a
+ * full path.
+ */
 int fdt_add_subnode_namelen(void *fdt, int parentoffset,
 			    const char *name, int namelen);
+
+/**
+ * fdt_add_subnode - creates a new node
+ * @fdt: pointer to the device tree blob
+ * @parentoffset: structure block offset of a node
+ * @name: name of the subnode to locate
+ *
+ * fdt_add_subnode() creates a new node as a subnode of the node at
+ * structure block offset parentoffset, with the given name (which
+ * should include the unit address, if any).
+ *
+ * This function will insert data into the blob, and will therefore
+ * change the offsets of some existing nodes.
+
+ * returns:
+ *	structure block offset of the created nodeequested subnode (>=0), on success
+ *	-FDT_ERR_NOTFOUND, if the requested subnode does not exist
+ *	-FDT_ERR_BADOFFSET, if parentoffset did not point to an FDT_BEGIN_NODE tag
+ *	-FDT_ERR_EXISTS, if the node at parentoffset already has a subnode of
+ *		the given name
+ *	-FDT_ERR_NOSPACE, if there is insufficient free space in the
+ *		blob to contain the new node
+ *	-FDT_ERR_NOSPACE
+ *	-FDT_ERR_BADLAYOUT
+ *      -FDT_ERR_BADMAGIC,
+ *	-FDT_ERR_BADVERSION,
+ *	-FDT_ERR_BADSTATE,
+ *	-FDT_ERR_BADSTRUCTURE,
+ *	-FDT_ERR_TRUNCATED, standard meanings.
+ */
 int fdt_add_subnode(void *fdt, int parentoffset, const char *name);
+
+/**
+ * fdt_del_node - delete a node (subtree)
+ * @fdt: pointer to the device tree blob
+ * @nodeoffset: offset of the node to nop
+ *
+ * fdt_del_node() will remove the given node, including all its
+ * subnodes if any, from the blob.
+ *
+ * This function will delete data from the blob, and will therefore
+ * change the offsets of some existing nodes.
+ *
+ * returns:
+ *	0, on success
+ *	-FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag
+ *	-FDT_ERR_BADLAYOUT,
+ *	-FDT_ERR_BADMAGIC,
+ *	-FDT_ERR_BADVERSION,
+ *	-FDT_ERR_BADSTATE,
+ *	-FDT_ERR_BADSTRUCTURE,
+ *	-FDT_ERR_TRUNCATED, standard meanings
+ */
 int fdt_del_node(void *fdt, int nodeoffset);
 
 /**********************************************************************/

From ad3006fe7e84667021753b74247b0bafd97ba35f Mon Sep 17 00:00:00 2001
From: Gerald Van Baren <vanbaren@cideas.com>
Date: Mon, 7 Jan 2008 23:47:32 -0500
Subject: [PATCH 072/108] LIBFDT: use memmove() instead of memcpy()

This is partial patch from the DTC/libfdt
commit  67b6b33b9b413a450a72135b5dc59c0a1e33e647
Author: David Gibson <david@gibson.dropbear.id.au>
Date:   Wed Nov 21 11:56:14 2007 +1100

    The patch also fixes one genuine bug caught by valgrind -
    _packblocks() in fdt_rw.c was using memcpy() where it should have been
    using memmove().

Signed-off-by: Gerald Van Baren <vanbaren@cideas.com>
---
 libfdt/fdt_rw.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/libfdt/fdt_rw.c b/libfdt/fdt_rw.c
index dfe5628a3..6673f8ec9 100644
--- a/libfdt/fdt_rw.c
+++ b/libfdt/fdt_rw.c
@@ -358,12 +358,12 @@ static void _packblocks(const void *fdt, void *buf,
 	memmove(buf + mem_rsv_off, fdt + fdt_off_mem_rsvmap(fdt), mem_rsv_size);
 	fdt_set_off_mem_rsvmap(buf, mem_rsv_off);
 
-	memcpy(buf + struct_off, fdt + fdt_off_dt_struct(fdt), struct_size);
+	memmove(buf + struct_off, fdt + fdt_off_dt_struct(fdt), struct_size);
 	fdt_set_off_dt_struct(buf, struct_off);
 	fdt_set_size_dt_struct(buf, struct_size);
 
-	memcpy(buf + strings_off, fdt + fdt_off_dt_strings(fdt),
-	       fdt_size_dt_strings(fdt));
+	memmove(buf + strings_off, fdt + fdt_off_dt_strings(fdt),
+		fdt_size_dt_strings(fdt));
 	fdt_set_off_dt_strings(buf, strings_off);
 	fdt_set_size_dt_strings(buf, fdt_size_dt_strings(fdt));
 }

From 7d5d75633174867316a0c0f2fca5ceb2cf312cde Mon Sep 17 00:00:00 2001
From: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
Date: Tue, 8 Jan 2008 11:13:09 +0100
Subject: [PATCH 073/108] ppc4xx: Disable error message when no NAND chip is
 installed on PMC440

Add CFG_NAND_QUIET_TEST option to disable error message when
no NAND chip is installed on PMC440 boards.

Disable a couple of config defines that are only used for NAND_U_BOOT.

Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
---
 include/configs/PMC440.h | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/include/configs/PMC440.h b/include/configs/PMC440.h
index 3d2ed1e7d..87fca3c47 100644
--- a/include/configs/PMC440.h
+++ b/include/configs/PMC440.h
@@ -167,6 +167,7 @@
  * set up. While still running from cache, I experienced problems accessing
  * the NAND controller.	sr - 2006-08-25
  */
+#if defined (CONFIG_NAND_U_BOOT)
 #define CFG_NAND_BOOT_SPL_SRC	0xfffff000	/* SPL location                 */
 #define CFG_NAND_BOOT_SPL_SIZE	(4 << 10)	/* SPL size                     */
 #define CFG_NAND_BOOT_SPL_DST	(CFG_OCM_BASE + (12 << 10)) /* Copy SPL here    */
@@ -195,6 +196,7 @@
 #define CFG_NAND_OOBSIZE	16
 #define CFG_NAND_ECCTOTAL	(CFG_NAND_ECCBYTES * CFG_NAND_ECCSTEPS)
 #define CFG_NAND_ECCPOS		{0, 1, 2, 3, 6, 7}
+#endif
 
 #ifdef CFG_ENV_IS_IN_NAND
 /*
@@ -501,6 +503,7 @@
 #define NAND_MAX_CHIPS		1
 #define CFG_NAND_BASE		(CFG_NAND_ADDR + CFG_NAND_CS)
 #define CFG_NAND_SELECT_DEVICE	1 /* nand driver supports mutipl. chips */
+#define CFG_NAND_QUIET_TEST	1
 
 /*
  * Internal Definitions

From ff5fb8a6ccba56e3482d0e297d8cfb7faa040811 Mon Sep 17 00:00:00 2001
From: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
Date: Tue, 8 Jan 2008 12:49:58 +0100
Subject: [PATCH 074/108] ppc4xx: Update PLB/PCI divider for PMC440 board

This patch updates the PLB/PCI divider when running at
400MHz CPU frequency from 4 to 3 which results in 44MHz PCI sync clock.

Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
---
 board/esd/pmc440/cmd_pmc440.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/board/esd/pmc440/cmd_pmc440.c b/board/esd/pmc440/cmd_pmc440.c
index d588d8ca9..350af4863 100644
--- a/board/esd/pmc440/cmd_pmc440.c
+++ b/board/esd/pmc440/cmd_pmc440.c
@@ -280,10 +280,10 @@ int do_setup_bootstrap_eeprom(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]
 
 	if (argc > 1) {
 		if (!strcmp(argv[1], "400")) {
-			/* PLB=133MHz, PLB/PCI=4 */
+			/* PLB=133MHz, PLB/PCI=3 */
 			printf("Bootstrapping for 400MHz\n");
 			sdsdp[0]=0x8678624e;
-			sdsdp[1]=0x0947a030;
+			sdsdp[1]=0x095fa030;
 			sdsdp[2]=0x40082350;
 			sdsdp[3]=0x0d050000;
 		} else if (!strcmp(argv[1], "533")) {

From 580d1d3186a2bc6dbdb626941b716dae1788e51e Mon Sep 17 00:00:00 2001
From: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
Date: Tue, 8 Jan 2008 15:39:01 +0100
Subject: [PATCH 075/108] ppc4xx: Fix UIC2 vector number base

Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
---
 cpu/ppc4xx/vecnum.h | 32 ++++++++++++++++----------------
 1 file changed, 16 insertions(+), 16 deletions(-)

diff --git a/cpu/ppc4xx/vecnum.h b/cpu/ppc4xx/vecnum.h
index 93e51b90c..8d04b6906 100644
--- a/cpu/ppc4xx/vecnum.h
+++ b/cpu/ppc4xx/vecnum.h
@@ -106,16 +106,16 @@
 #define VECNUM_RXDE         VECNUM_MRDE
 
 /* UIC 2 */
-#define VECNUM_EIR5         (62 +  0)  /* External interrupt 5          */
-#define VECNUM_EIR6         (62 +  1)  /* External interrupt 6          */
-#define VECNUM_OPB          (62 +  2)  /* OPB to PLB bridge int stat    */
-#define VECNUM_EIR2         (62 +  3)  /* External interrupt 2          */
-#define VECNUM_EIR3         (62 +  4)  /* External interrupt 3          */
-#define VECNUM_DDR2         (62 +  5)  /* DDR2 sdram                    */
-#define VECNUM_MCTX0        (62 +  6)  /* MAl intp coalescence TX0      */
-#define VECNUM_MCTX1        (62 +  7)  /* MAl intp coalescence TX1      */
-#define VECNUM_MCTR0        (62 +  8)  /* MAl intp coalescence TR0      */
-#define VECNUM_MCTR1        (62 +  9)  /* MAl intp coalescence TR1      */
+#define VECNUM_EIR5         (64 +  0)  /* External interrupt 5          */
+#define VECNUM_EIR6         (64 +  1)  /* External interrupt 6          */
+#define VECNUM_OPB          (64 +  2)  /* OPB to PLB bridge int stat    */
+#define VECNUM_EIR2         (64 +  3)  /* External interrupt 2          */
+#define VECNUM_EIR3         (64 +  4)  /* External interrupt 3          */
+#define VECNUM_DDR2         (64 +  5)  /* DDR2 sdram                    */
+#define VECNUM_MCTX0        (64 +  6)  /* MAl intp coalescence TX0      */
+#define VECNUM_MCTX1        (64 +  7)  /* MAl intp coalescence TX1      */
+#define VECNUM_MCTR0        (64 +  8)  /* MAl intp coalescence TR0      */
+#define VECNUM_MCTR1        (64 +  9)  /* MAl intp coalescence TR1      */
 
 #elif defined(CONFIG_440SPE)
 
@@ -152,12 +152,12 @@
 #define VECNUM_EWU0         (32 + 29)   /* Emac  wakeup                 */
 
 /* UIC 2 */
-#define VECNUM_EIR5         (62 + 24)   /* External interrupt 5         */
-#define VECNUM_EIR4         (62 + 25)   /* External interrupt 4         */
-#define VECNUM_EIR3         (62 + 26)   /* External interrupt 3         */
-#define VECNUM_EIR2         (62 + 27)   /* External interrupt 2         */
-#define VECNUM_EIR1         (62 + 28)   /* External interrupt 1         */
-#define VECNUM_EIR0         (62 + 29)   /* External interrupt 0         */
+#define VECNUM_EIR5         (64 + 24)   /* External interrupt 5         */
+#define VECNUM_EIR4         (64 + 25)   /* External interrupt 4         */
+#define VECNUM_EIR3         (64 + 26)   /* External interrupt 3         */
+#define VECNUM_EIR2         (64 + 27)   /* External interrupt 2         */
+#define VECNUM_EIR1         (64 + 28)   /* External interrupt 1         */
+#define VECNUM_EIR0         (64 + 29)   /* External interrupt 0         */
 
 #elif defined(CONFIG_440SP)
 

From 6e9233d30afe57cb6e148fbfa4895e7810196fac Mon Sep 17 00:00:00 2001
From: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
Date: Tue, 8 Jan 2008 15:50:49 +0100
Subject: [PATCH 076/108] ppc4xx: Move cpu/ppc4xx/vecnum.h into include path

This patch allows the use of 4xx interrupt vector number defines
in board specific code outside cpu/ppc4xx.

Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
---
 cpu/ppc4xx/4xx_enet.c                                  | 2 +-
 cpu/ppc4xx/4xx_uart.c                                  | 2 +-
 cpu/ppc4xx/interrupts.c                                | 2 +-
 cpu/ppc4xx/iop480_uart.c                               | 2 +-
 cpu/ppc4xx/usbdev.c                                    | 2 +-
 cpu/ppc4xx/vecnum.h => include/asm-ppc/ppc4xx-intvec.h | 0
 6 files changed, 5 insertions(+), 5 deletions(-)
 rename cpu/ppc4xx/vecnum.h => include/asm-ppc/ppc4xx-intvec.h (100%)

diff --git a/cpu/ppc4xx/4xx_enet.c b/cpu/ppc4xx/4xx_enet.c
index ff707dda5..44659ffcd 100644
--- a/cpu/ppc4xx/4xx_enet.c
+++ b/cpu/ppc4xx/4xx_enet.c
@@ -90,7 +90,7 @@
 #include <405_mal.h>
 #include <miiphy.h>
 #include <malloc.h>
-#include "vecnum.h"
+#include <asm/ppc4xx-intvec.h>
 
 /*
  * Only compile for platform with AMCC EMAC ethernet controller and
diff --git a/cpu/ppc4xx/4xx_uart.c b/cpu/ppc4xx/4xx_uart.c
index ac2b12b87..3d1124e0b 100644
--- a/cpu/ppc4xx/4xx_uart.c
+++ b/cpu/ppc4xx/4xx_uart.c
@@ -46,7 +46,7 @@
 #include <asm/processor.h>
 #include <asm/io.h>
 #include <watchdog.h>
-#include "vecnum.h"
+#include <asm/ppc4xx-intvec.h>
 
 #ifdef CONFIG_SERIAL_MULTI
 #include <serial.h>
diff --git a/cpu/ppc4xx/interrupts.c b/cpu/ppc4xx/interrupts.c
index 2026cc927..2f3dc326b 100644
--- a/cpu/ppc4xx/interrupts.c
+++ b/cpu/ppc4xx/interrupts.c
@@ -34,7 +34,7 @@
 #include <ppc4xx.h>
 #include <ppc_asm.tmpl>
 #include <commproc.h>
-#include "vecnum.h"
+#include <asm/ppc4xx-intvec.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
diff --git a/cpu/ppc4xx/iop480_uart.c b/cpu/ppc4xx/iop480_uart.c
index 8dd226729..3af0767c5 100644
--- a/cpu/ppc4xx/iop480_uart.c
+++ b/cpu/ppc4xx/iop480_uart.c
@@ -26,7 +26,7 @@
 #include <asm/processor.h>
 #include <asm/io.h>
 #include <watchdog.h>
-#include "vecnum.h"
+#include <asm/ppc4xx-intvec.h>
 
 #ifdef CONFIG_SERIAL_MULTI
 #include <serial.h>
diff --git a/cpu/ppc4xx/usbdev.c b/cpu/ppc4xx/usbdev.c
index 5924a6cb8..d71ba7710 100644
--- a/cpu/ppc4xx/usbdev.c
+++ b/cpu/ppc4xx/usbdev.c
@@ -7,7 +7,7 @@
 
 #include <usb.h>
 #include "usbdev.h"
-#include "vecnum.h"
+#include <asm/ppc4xx-intvec.h>
 
 #define USB_DT_DEVICE        0x01
 #define USB_DT_CONFIG        0x02
diff --git a/cpu/ppc4xx/vecnum.h b/include/asm-ppc/ppc4xx-intvec.h
similarity index 100%
rename from cpu/ppc4xx/vecnum.h
rename to include/asm-ppc/ppc4xx-intvec.h

From 1f84021a85abeb837d2ce0dc84297b4f1d45d516 Mon Sep 17 00:00:00 2001
From: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
Date: Tue, 8 Jan 2008 15:40:09 +0100
Subject: [PATCH 077/108] ppc4xx: assign PCI interrupts on seuqoia boards

Some operating systems rely on assigned PCI interrupts.

Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
---
 board/amcc/sequoia/sequoia.c | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/board/amcc/sequoia/sequoia.c b/board/amcc/sequoia/sequoia.c
index 2268bc06b..e46efef10 100644
--- a/board/amcc/sequoia/sequoia.c
+++ b/board/amcc/sequoia/sequoia.c
@@ -29,6 +29,7 @@
 #include <asm/gpio.h>
 #include <asm/processor.h>
 #include <asm/io.h>
+#include <asm/ppc4xx-intvec.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -387,6 +388,16 @@ int testdram(void)
 }
 #endif
 
+#if defined(CONFIG_PCI) && defined(CONFIG_PCI_PNP)
+/*
+ * Assign interrupts to PCI devices.
+ */
+void sequoia_pci_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
+{
+	pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, VECNUM_EIR2);
+}
+#endif
+
 /*************************************************************************
  *  pci_pre_init
  *
@@ -438,6 +449,9 @@ int pci_pre_init(struct pci_controller *hose)
 	addr = (addr & ~plb1_acr_wrp_mask) | plb1_acr_wrp_2deep;
 	mtdcr(plb1_acr, addr);
 
+#ifdef CONFIG_PCI_PNP
+	hose->fixup_irq = sequoia_pci_fixup_irq;
+#endif
 	return 1;
 }
 #endif /* defined(CONFIG_PCI) */

From 64b3727b9779d86127cd576e392a987de5ebb9fd Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Markus=20Klotzb=C3=BCcher?= <mk@denx.de>
Date: Tue, 27 Nov 2007 10:23:20 +0100
Subject: [PATCH 078/108] tools: fix fw_printenv tool to compile again

This patch updates the fw_printenv/fw_setenv userspace tool to include
the correct MTD header in order to compile against current kernel
headers. Backward compatibility is preserved by introducing an option
MTD_VERSION which can be set to "old" for compilation using the old MTD
headers. Along with this a number of warnings are fixed.

Signed-off-by: Markus Klotzbuecher <mk@denx.de>
---
 Makefile           |  2 +-
 tools/env/Makefile |  4 ++++
 tools/env/README   |  4 ++++
 tools/env/fw_env.c | 56 +++++++++++++++++++++++++---------------------
 tools/env/fw_env.h |  6 ++---
 5 files changed, 42 insertions(+), 30 deletions(-)

diff --git a/Makefile b/Makefile
index 35e90315f..46156f2ac 100644
--- a/Makefile
+++ b/Makefile
@@ -329,7 +329,7 @@ updater:
 		$(MAKE) -C tools/updater all || exit 1
 
 env:
-		$(MAKE) -C tools/env all || exit 1
+		$(MAKE) -C tools/env all MTD_VERSION=${MTD_VERSION} || exit 1
 
 depend dep:	version
 		for dir in $(SUBDIRS) ; do $(MAKE) -C $$dir _depend ; done
diff --git a/tools/env/Makefile b/tools/env/Makefile
index 1f16768aa..ea2d5b5a0 100644
--- a/tools/env/Makefile
+++ b/tools/env/Makefile
@@ -28,6 +28,10 @@ HEADERS	:= fw_env.h
 
 CPPFLAGS := -Wall -DUSE_HOSTCC
 
+ifeq ($(MTD_VERSION),old)
+CPPFLAGS += -DMTD_OLD
+endif
+
 all:	$(obj)fw_printenv
 
 $(obj)fw_printenv:	$(SRCS) $(HEADERS)
diff --git a/tools/env/README b/tools/env/README
index d8386f7f2..f8a644e0c 100644
--- a/tools/env/README
+++ b/tools/env/README
@@ -6,6 +6,10 @@ For the run-time utiltity configuration uncomment the line
 #define CONFIG_FILE  "/etc/fw_env.config"
 in fw_env.h.
 
+For building against older versions of the MTD headers (meaning before
+v2.6.8-rc1) it is required to pass the argument "MTD_VERSION=old" to
+make.
+
 See comments in the fw_env.config file for definitions for the
 particular board.
 
diff --git a/tools/env/fw_env.c b/tools/env/fw_env.c
index f723b5bca..bf9d50620 100644
--- a/tools/env/fw_env.c
+++ b/tools/env/fw_env.c
@@ -31,16 +31,20 @@
 #include <sys/ioctl.h>
 #include <sys/stat.h>
 #include <unistd.h>
-#include <linux/mtd/mtd.h>
-#include "fw_env.h"
 
-typedef unsigned char uchar;
+#ifdef MTD_OLD
+# include <linux/mtd/mtd.h>
+#else
+# include <mtd/mtd-user.h>
+#endif
+
+#include "fw_env.h"
 
 #define	CMD_GETENV	"fw_printenv"
 #define	CMD_SETENV	"fw_setenv"
 
 typedef struct envdev_s {
-	uchar devname[16];		/* Device name */
+	char devname[16];		/* Device name */
 	ulong devoff;			/* Device offset */
 	ulong env_size;			/* environment size */
 	ulong erase_size;		/* device erase size */
@@ -60,22 +64,22 @@ static int curdev;
 
 typedef struct environment_s {
 	ulong crc;			/* CRC32 over data bytes    */
-	uchar flags;			/* active or obsolete */
-	uchar *data;
+	unsigned char flags;		/* active or obsolete */
+	char *data;
 } env_t;
 
 static env_t environment;
 
 static int HaveRedundEnv = 0;
 
-static uchar active_flag = 1;
-static uchar obsolete_flag = 0;
+static unsigned char active_flag = 1;
+static unsigned char obsolete_flag = 0;
 
 
 #define XMK_STR(x)	#x
 #define MK_STR(x)	XMK_STR(x)
 
-static uchar default_environment[] = {
+static char default_environment[] = {
 #if defined(CONFIG_BOOTARGS)
 	"bootargs=" CONFIG_BOOTARGS "\0"
 #endif
@@ -155,7 +159,7 @@ static uchar default_environment[] = {
 };
 
 static int flash_io (int mode);
-static uchar *envmatch (uchar * s1, uchar * s2);
+static char *envmatch (char * s1, char * s2);
 static int env_init (void);
 static int parse_config (void);
 
@@ -175,15 +179,15 @@ static inline ulong getenvsize (void)
  * Search the environment for a variable.
  * Return the value, if found, or NULL, if not found.
  */
-unsigned char *fw_getenv (unsigned char *name)
+char *fw_getenv (char *name)
 {
-	uchar *env, *nxt;
+	char *env, *nxt;
 
 	if (env_init ())
 		return (NULL);
 
 	for (env = environment.data; *env; env = nxt + 1) {
-		uchar *val;
+		char *val;
 
 		for (nxt = env; *nxt; ++nxt) {
 			if (nxt >= &environment.data[ENV_SIZE]) {
@@ -206,7 +210,7 @@ unsigned char *fw_getenv (unsigned char *name)
  */
 void fw_printenv (int argc, char *argv[])
 {
-	uchar *env, *nxt;
+	char *env, *nxt;
 	int i, n_flag;
 
 	if (env_init ())
@@ -241,8 +245,8 @@ void fw_printenv (int argc, char *argv[])
 	}
 
 	for (i = 1; i < argc; ++i) {	/* print single env variables   */
-		uchar *name = argv[i];
-		uchar *val = NULL;
+		char *name = argv[i];
+		char *val = NULL;
 
 		for (env = environment.data; *env; env = nxt + 1) {
 
@@ -279,9 +283,9 @@ void fw_printenv (int argc, char *argv[])
 int fw_setenv (int argc, char *argv[])
 {
 	int i, len;
-	uchar *env, *nxt;
-	uchar *oldval = NULL;
-	uchar *name;
+	char *env, *nxt;
+	char *oldval = NULL;
+	char *name;
 
 	if (argc < 2) {
 		return (EINVAL);
@@ -361,7 +365,7 @@ int fw_setenv (int argc, char *argv[])
 	while ((*env = *name++) != '\0')
 		env++;
 	for (i = 2; i < argc; ++i) {
-		uchar *val = argv[i];
+		char *val = argv[i];
 
 		*env = (i == 2) ? '=' : ' ';
 		while ((*++env = *val++) != '\0');
@@ -373,7 +377,7 @@ int fw_setenv (int argc, char *argv[])
   WRITE_FLASH:
 
 	/* Update CRC */
-	environment.crc = crc32 (0, environment.data, ENV_SIZE);
+	environment.crc = crc32 (0, (uint8_t*) environment.data, ENV_SIZE);
 
 	/* write environment back to flash */
 	if (flash_io (O_RDWR)) {
@@ -569,7 +573,7 @@ static int flash_io (int mode)
  * If the names match, return the value of s2, else NULL.
  */
 
-static uchar *envmatch (uchar * s1, uchar * s2)
+static char *envmatch (char * s1, char * s2)
 {
 
 	while (*s1 == *s2++)
@@ -586,10 +590,10 @@ static uchar *envmatch (uchar * s1, uchar * s2)
 static int env_init (void)
 {
 	int crc1, crc1_ok;
-	uchar *addr1;
+	char *addr1;
 
 	int crc2, crc2_ok;
-	uchar flag1, flag2, *addr2;
+	char flag1, flag2, *addr2;
 
 	if (parse_config ())		/* should fill envdevices */
 		return 1;
@@ -608,7 +612,7 @@ static int env_init (void)
 		return (errno);
 	}
 
-	crc1_ok = ((crc1 = crc32 (0, environment.data, ENV_SIZE))
+	crc1_ok = ((crc1 = crc32 (0, (uint8_t *) environment.data, ENV_SIZE))
 			   == environment.crc);
 	if (!HaveRedundEnv) {
 		if (!crc1_ok) {
@@ -632,7 +636,7 @@ static int env_init (void)
 			return (errno);
 		}
 
-		crc2_ok = ((crc2 = crc32 (0, environment.data, ENV_SIZE))
+		crc2_ok = ((crc2 = crc32 (0, (uint8_t *) environment.data, ENV_SIZE))
 				   == environment.crc);
 		flag2 = environment.flags;
 
diff --git a/tools/env/fw_env.h b/tools/env/fw_env.h
index 13c45a278..58607ded5 100644
--- a/tools/env/fw_env.h
+++ b/tools/env/fw_env.h
@@ -47,8 +47,8 @@
 	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " 	\
 	"bootm"
 
-extern		void  fw_printenv(int argc, char *argv[]);
-extern unsigned char *fw_getenv  (unsigned char *name);
-extern		int   fw_setenv  (int argc, char *argv[]);
+extern void  fw_printenv(int argc, char *argv[]);
+extern char *fw_getenv  (char *name);
+extern int fw_setenv  (int argc, char *argv[]);
 
 extern unsigned	long  crc32	 (unsigned long, const unsigned char *, unsigned);

From 46f6e5019048b103d7693d5310de0f1cfbaf4c19 Mon Sep 17 00:00:00 2001
From: Wolfgang Denk <wd@denx.de>
Date: Tue, 8 Jan 2008 22:58:27 +0100
Subject: [PATCH 079/108] Fix compile problem with new env code.

Signed-off-by: Wolfgang Denk <wd@denx.de>
---
 tools/env/fw_env.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/tools/env/fw_env.c b/tools/env/fw_env.c
index bf9d50620..e083a5b11 100644
--- a/tools/env/fw_env.c
+++ b/tools/env/fw_env.c
@@ -35,6 +35,7 @@
 #ifdef MTD_OLD
 # include <linux/mtd/mtd.h>
 #else
+# define  __user	/* nothing */
 # include <mtd/mtd-user.h>
 #endif
 

From 32d6f1bc09175f3b77469771e839bc7255a9f22e Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Markus=20Klotzb=C3=BCcher?= <mk@denx.de>
Date: Tue, 5 Jan 1988 08:17:15 +0100
Subject: [PATCH 080/108] Fix problems with usb storage devices on MPC5200
 /TQM5200

The MPC5200 OHCI controller operates in big endian, so
CFG_OHCI_BE_CONTROLLER must be defined for it to work properly.

Signed-off-by: Markus Klotzbuecher <mk@denx.de>
---
 include/configs/TQM5200.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/include/configs/TQM5200.h b/include/configs/TQM5200.h
index 7ecc275a1..9a0e9b84a 100644
--- a/include/configs/TQM5200.h
+++ b/include/configs/TQM5200.h
@@ -131,6 +131,7 @@
 /* USB */
 #if defined(CONFIG_STK52XX) || defined(CONFIG_FO300)
 #define CONFIG_USB_OHCI_NEW
+#define CFG_OHCI_BE_CONTROLLER
 #define CONFIG_USB_STORAGE
 #define CONFIG_CMD_FAT
 #define CONFIG_CMD_USB

From 0ddb89601a8d29e808db450366752ffdc6267c53 Mon Sep 17 00:00:00 2001
From: Wolfgang Denk <wd@denx.de>
Date: Wed, 9 Jan 2008 10:16:33 +0100
Subject: [PATCH 081/108] Fix memset bug in ext2fs_read_file()

ext2fs_read_file() had the function arguments swapped.

Pointed out by Mike Montour, 19 Dec 2007 22:34:25 -0800

Signed-off-by: Wolfgang Denk <wd@denx.de>
---
 fs/ext2/ext2fs.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/fs/ext2/ext2fs.c b/fs/ext2/ext2fs.c
index 513a2f9e3..78335510e 100644
--- a/fs/ext2/ext2fs.c
+++ b/fs/ext2/ext2fs.c
@@ -436,7 +436,7 @@ int ext2fs_read_file
 				return (-1);
 			}
 		} else {
-			memset (buf, blocksize - skipfirst, 0);
+			memset (buf, 0, blocksize - skipfirst);
 		}
 		buf += blocksize - skipfirst;
 	}

From e02c521d94b45d7b05aa522e4ccde6b74bf5fe57 Mon Sep 17 00:00:00 2001
From: Stefan Roese <sr@denx.de>
Date: Wed, 9 Jan 2008 10:23:16 +0100
Subject: [PATCH 082/108] ppc4xx: Add 44x cache locking to better support
 init-ram in d-cache

This patch adds support for locking the init-ram/stack in d-cache,
so that other regions may use d-cache as well

Note, that this current implementation locks exactly 4k of d-cache,
so please make sure that you don't define a bigger init-ram area. Take
a look at the lwmon5 440EPx implementation as a reference.

Signed-off-by: Stefan Roese <sr@denx.de>
---
 cpu/ppc4xx/start.S | 52 ++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 52 insertions(+)

diff --git a/cpu/ppc4xx/start.S b/cpu/ppc4xx/start.S
index 52601ed70..a73060436 100644
--- a/cpu/ppc4xx/start.S
+++ b/cpu/ppc4xx/start.S
@@ -636,6 +636,33 @@ _start:
 	dcbz	r0,r3
 	addi	r3,r3,32
 	bdnz	..d_ag
+
+	/*
+	 * Lock the init-ram/stack in d-cache, so that other regions
+	 * may use d-cache as well
+	 * Note, that this current implementation locks exactly 4k
+	 * of d-cache, so please make sure that you don't define a
+	 * bigger init-ram area. Take a look at the lwmon5 440EPx
+	 * implementation as a reference.
+	 */
+	msync
+	isync
+	/* 8. set TFLOOR/NFLOOR to 8 (-> 8*16*32 bytes locked -> 4k) */
+	lis	r1,0x0201
+	ori	r1,r1,0xf808
+	mtspr	dvlim,r1
+	lis	r1,0x0808
+	ori	r1,r1,0x0808
+	mtspr	dnv0,r1
+	mtspr	dnv1,r1
+	mtspr	dnv2,r1
+	mtspr	dnv3,r1
+	mtspr	dtv0,r1
+	mtspr	dtv1,r1
+	mtspr	dtv2,r1
+	mtspr	dtv3,r1
+	msync
+	isync
 #endif /* CFG_INIT_RAM_DCACHE */
 
 	/* 440EP & 440GR are only 440er PPC's without internal SRAM */
@@ -1345,6 +1372,31 @@ relocate_code:
 	mr	r4,r10
 	mr	r5,r11
 #endif
+
+#ifdef CFG_INIT_RAM_DCACHE
+	/*
+	 * Unlock the previously locked d-cache
+	 */
+	msync
+	isync
+	/* set TFLOOR/NFLOOR to 0 again */
+	lis	r6,0x0001
+	ori	r6,r6,0xf800
+	mtspr	dvlim,r6
+	lis	r6,0x0000
+	ori	r6,r6,0x0000
+	mtspr	dnv0,r6
+	mtspr	dnv1,r6
+	mtspr	dnv2,r6
+	mtspr	dnv3,r6
+	mtspr	dtv0,r6
+	mtspr	dtv1,r6
+	mtspr	dtv2,r6
+	mtspr	dtv3,r6
+	msync
+	isync
+#endif /* CFG_INIT_RAM_DCACHE */
+
 #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
     defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
     defined(CONFIG_440SP) || defined(CONFIG_440SPE)

From 1754f50b710194f886b6f2831803d8960171a14d Mon Sep 17 00:00:00 2001
From: Stefan Roese <sr@denx.de>
Date: Wed, 9 Jan 2008 10:25:46 +0100
Subject: [PATCH 083/108] ppc4xx: Add CFG_POST_ALT_WORD_ADDR to support non OCM
 POST WORD storage

The privious 4xx POST implementation only supported storing the POST
WORD in OCM. Since we need to reserve the OCM on LWMON5 for the logbuffer
we need to store the POST WORD in some other non volatile location.
This patch adds CFG_POST_ALT_WORD_ADDR to specify an address for such
a location.

Signed-off-by: Stefan Roese <sr@denx.de>
---
 cpu/ppc4xx/commproc.c | 14 +++++++++++++-
 1 file changed, 13 insertions(+), 1 deletion(-)

diff --git a/cpu/ppc4xx/commproc.c b/cpu/ppc4xx/commproc.c
index 68aab5b7e..22156dd9d 100644
--- a/cpu/ppc4xx/commproc.c
+++ b/cpu/ppc4xx/commproc.c
@@ -26,10 +26,21 @@
 
 #include <common.h>
 #include <commproc.h>
-
+#include <asm/io.h>
 
 #if defined(CONFIG_POST) || defined(CONFIG_LOGBUFFER)
 
+#if defined(CFG_POST_ALT_WORD_ADDR)
+void post_word_store (ulong a)
+{
+	out_be32((void *)CFG_POST_ALT_WORD_ADDR, a);
+}
+
+ulong post_word_load (void)
+{
+	return in_be32((void *)CFG_POST_ALT_WORD_ADDR);
+}
+#else /* CFG_POST_ALT_WORD_ADDR */
 void post_word_store (ulong a)
 {
 	volatile void *save_addr = (volatile void *)(CFG_OCM_DATA_ADDR + CFG_POST_WORD_ADDR);
@@ -41,6 +52,7 @@ ulong post_word_load (void)
 	volatile void *save_addr = (volatile void *)(CFG_OCM_DATA_ADDR + CFG_POST_WORD_ADDR);
 	return *(volatile ulong *) save_addr;
 }
+#endif /* CFG_POST_ALT_WORD_ADDR */
 
 #endif	/* CONFIG_POST || CONFIG_LOGBUFFER*/
 

From 8f24e0637ae113500d8bd60d80d57afcc0aa8bde Mon Sep 17 00:00:00 2001
From: Stefan Roese <sr@denx.de>
Date: Wed, 9 Jan 2008 10:28:20 +0100
Subject: [PATCH 084/108] ppc4xx: Change LWMON5 to not use OCM for init-ram and
 POST anymore

This patch configures the LWMON5 port to use d-cache as init-ram and
the unused GPT0_COMP6 as POST WORD storage.

Signed-off-by: Stefan Roese <sr@denx.de>
---
 board/lwmon5/init.S      |  2 +-
 include/configs/lwmon5.h | 19 ++++++++++++-------
 include/ppc440.h         |  4 +---
 3 files changed, 14 insertions(+), 11 deletions(-)

diff --git a/board/lwmon5/init.S b/board/lwmon5/init.S
index 6798e8098..5aade72b5 100644
--- a/board/lwmon5/init.S
+++ b/board/lwmon5/init.S
@@ -57,7 +57,7 @@ tlbtab:
 
 #ifdef CFG_INIT_RAM_DCACHE
 	/* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
-	tlbentry(CFG_INIT_RAM_ADDR, SZ_64K, CFG_INIT_RAM_ADDR, 0, AC_R|AC_W|AC_X|SA_G)
+	tlbentry(CFG_INIT_RAM_ADDR, SZ_4K, CFG_INIT_RAM_ADDR, 0, AC_R|AC_W|AC_X|SA_G)
 #endif
 
 	/* TLB-entry for PCI Memory */
diff --git a/include/configs/lwmon5.h b/include/configs/lwmon5.h
index 5210024d8..0bf536b6b 100644
--- a/include/configs/lwmon5.h
+++ b/include/configs/lwmon5.h
@@ -71,15 +71,20 @@
 /*-----------------------------------------------------------------------
  * Initial RAM & stack pointer
  *----------------------------------------------------------------------*/
-/* 440EPx/440GRx have 16KB of internal SRAM, so no need for D-Cache	*/
-#define CFG_INIT_RAM_ADDR	CFG_OCM_BASE	/* OCM			*/
-#define CFG_OCM_DATA_ADDR	CFG_OCM_BASE
-
+/*
+ * On LWMON5 we use D-cache as init-ram and stack pointer. We also move
+ * the POST_WORD from OCM to a 440EPx register that preserves it's
+ * content during reset (GPT0_COM6). This way we reserve the OCM (16k)
+ * for logbuffer only.
+ */
+#define CFG_INIT_RAM_DCACHE	1		/* d-cache as init ram	*/
+#define CFG_INIT_RAM_ADDR	0x70000000		/* DCache       */
 #define CFG_INIT_RAM_END	(4 << 10)
-#define CFG_GBL_DATA_SIZE	256		/* num bytes initial data */
+#define CFG_GBL_DATA_SIZE	256		/* num bytes initial data*/
 #define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_POST_WORD_ADDR	(CFG_GBL_DATA_OFFSET - 0x4)
-#define CFG_INIT_SP_OFFSET	CFG_POST_WORD_ADDR
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CFG_POST_ALT_WORD_ADDR	(CFG_PERIPHERAL_BASE + GPT0_COMP6)
+						/* unused GPT0 COMP reg	*/
 
 /*-----------------------------------------------------------------------
  * Serial Port
diff --git a/include/ppc440.h b/include/ppc440.h
index 90e56b098..b0d16fb4a 100644
--- a/include/ppc440.h
+++ b/include/ppc440.h
@@ -1354,8 +1354,6 @@
 #define plb1_bearl                (PLB_ARBITER_BASE+ 0x0C)
 #define plb1_bearh                (PLB_ARBITER_BASE+ 0x0D)
 
-#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
-    defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
 /* Pin Function Control Register 1 */
 #define SDR0_PFC1                    0x4101
 #define   SDR0_PFC1_U1ME_MASK         0x02000000    /* UART1 Mode Enable */
@@ -1421,7 +1419,7 @@
 #define   SDR0_MFR_PKT_REJ_EN1         0x00080000   /* Pkt Rej. Enable on EMAC3(1) */
 #define   SDR0_MFR_PKT_REJ_POL         0x00200000   /* Packet Reject Polarity */
 
-#endif /* defined(CONFIG_440EP) || defined(CONFIG_440GR) */
+#define GPT0_COMP6			0x00000098
 
 #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
 #define SDR0_USB2D0CR                 0x0320

From b2e2142c500c48a57f18f9dd30e66c13caea0971 Mon Sep 17 00:00:00 2001
From: Stefan Roese <sr@denx.de>
Date: Wed, 9 Jan 2008 10:38:58 +0100
Subject: [PATCH 085/108] POST: Execute SPR test after relocation

On LWMON5 we now use d-cache as init-ram and stack. The SPR POST test uses
self modifying code and this doesn't work with stack in d-cache, since
I can't move the code from d-cache to i-cache. We move the SPR test to
be executed a little later, after relocation. Then stack is located in
SDRAM and this self-modifying code is no problem anymore.

Signed-off-by: Stefan Roese <sr@denx.de>
---
 post/tests.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/post/tests.c b/post/tests.c
index e1c3d28f5..0c49e3244 100644
--- a/post/tests.c
+++ b/post/tests.c
@@ -194,7 +194,7 @@ struct post_test post_list[] =
 	"SPR test",
 	"spr",
 	"This test checks SPR contents.",
-	POST_ROM | POST_ALWAYS | POST_PREREL,
+	POST_RAM | POST_ALWAYS,
 	&spr_post_test,
 	NULL,
 	NULL,

From 435dc8fcdb3bc61d3d490773a8f369f98a20c868 Mon Sep 17 00:00:00 2001
From: Wolfgang Denk <wd@denx.de>
Date: Wed, 9 Jan 2008 11:36:21 +0100
Subject: [PATCH 086/108] Coding Style cleanup, update CHANGELOG

Signed-off-by: Wolfgang Denk <wd@denx.de>
---
 CHANGELOG                           | 2549 +++++++++++++++++++++++++++
 board/apollon/lowlevel_init.S       |  240 +--
 board/freescale/common/fsl_diu_fb.c |    6 -
 include/configs/apollon.h           |   18 +-
 4 files changed, 2678 insertions(+), 135 deletions(-)

diff --git a/CHANGELOG b/CHANGELOG
index ef5c7ea98..d682b96f6 100644
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -1,3 +1,1375 @@
+commit b2e2142c500c48a57f18f9dd30e66c13caea0971
+Author: Stefan Roese <sr@denx.de>
+Date:	Wed Jan 9 10:38:58 2008 +0100
+
+    POST: Execute SPR test after relocation
+
+    On LWMON5 we now use d-cache as init-ram and stack. The SPR POST test uses
+    self modifying code and this doesn't work with stack in d-cache, since
+    I can't move the code from d-cache to i-cache. We move the SPR test to
+    be executed a little later, after relocation. Then stack is located in
+    SDRAM and this self-modifying code is no problem anymore.
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 8f24e0637ae113500d8bd60d80d57afcc0aa8bde
+Author: Stefan Roese <sr@denx.de>
+Date:	Wed Jan 9 10:28:20 2008 +0100
+
+    ppc4xx: Change LWMON5 to not use OCM for init-ram and POST anymore
+
+    This patch configures the LWMON5 port to use d-cache as init-ram and
+    the unused GPT0_COMP6 as POST WORD storage.
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 1754f50b710194f886b6f2831803d8960171a14d
+Author: Stefan Roese <sr@denx.de>
+Date:	Wed Jan 9 10:25:46 2008 +0100
+
+    ppc4xx: Add CFG_POST_ALT_WORD_ADDR to support non OCM POST WORD storage
+
+    The privious 4xx POST implementation only supported storing the POST
+    WORD in OCM. Since we need to reserve the OCM on LWMON5 for the logbuffer
+    we need to store the POST WORD in some other non volatile location.
+    This patch adds CFG_POST_ALT_WORD_ADDR to specify an address for such
+    a location.
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit e02c521d94b45d7b05aa522e4ccde6b74bf5fe57
+Author: Stefan Roese <sr@denx.de>
+Date:	Wed Jan 9 10:23:16 2008 +0100
+
+    ppc4xx: Add 44x cache locking to better support init-ram in d-cache
+
+    This patch adds support for locking the init-ram/stack in d-cache,
+    so that other regions may use d-cache as well
+
+    Note, that this current implementation locks exactly 4k of d-cache,
+    so please make sure that you don't define a bigger init-ram area. Take
+    a look at the lwmon5 440EPx implementation as a reference.
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 0ddb89601a8d29e808db450366752ffdc6267c53
+Author: Wolfgang Denk <wd@denx.de>
+Date:	Wed Jan 9 10:16:33 2008 +0100
+
+    Fix memset bug in ext2fs_read_file()
+
+    ext2fs_read_file() had the function arguments swapped.
+
+    Pointed out by Mike Montour, 19 Dec 2007 22:34:25 -0800
+
+    Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit 32d6f1bc09175f3b77469771e839bc7255a9f22e
+Author: Markus Klotzbücher <mk@denx.de>
+Date:	Tue Jan 5 08:17:15 1988 +0100
+
+    Fix problems with usb storage devices on MPC5200 /TQM5200
+
+    The MPC5200 OHCI controller operates in big endian, so
+    CFG_OHCI_BE_CONTROLLER must be defined for it to work properly.
+
+    Signed-off-by: Markus Klotzbuecher <mk@denx.de>
+
+commit 46f6e5019048b103d7693d5310de0f1cfbaf4c19
+Author: Wolfgang Denk <wd@denx.de>
+Date:	Tue Jan 8 22:58:27 2008 +0100
+
+    Fix compile problem with new env code.
+
+    Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit 64b3727b9779d86127cd576e392a987de5ebb9fd
+Author: Markus Klotzbücher <mk@denx.de>
+Date:	Tue Nov 27 10:23:20 2007 +0100
+
+    tools: fix fw_printenv tool to compile again
+
+    This patch updates the fw_printenv/fw_setenv userspace tool to include
+    the correct MTD header in order to compile against current kernel
+    headers. Backward compatibility is preserved by introducing an option
+    MTD_VERSION which can be set to "old" for compilation using the old MTD
+    headers. Along with this a number of warnings are fixed.
+
+    Signed-off-by: Markus Klotzbuecher <mk@denx.de>
+
+commit 1f84021a85abeb837d2ce0dc84297b4f1d45d516
+Author: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+Date:	Tue Jan 8 15:40:09 2008 +0100
+
+    ppc4xx: assign PCI interrupts on seuqoia boards
+
+    Some operating systems rely on assigned PCI interrupts.
+
+    Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+
+commit 6e9233d30afe57cb6e148fbfa4895e7810196fac
+Author: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+Date:	Tue Jan 8 15:50:49 2008 +0100
+
+    ppc4xx: Move cpu/ppc4xx/vecnum.h into include path
+
+    This patch allows the use of 4xx interrupt vector number defines
+    in board specific code outside cpu/ppc4xx.
+
+    Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+
+commit 580d1d3186a2bc6dbdb626941b716dae1788e51e
+Author: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+Date:	Tue Jan 8 15:39:01 2008 +0100
+
+    ppc4xx: Fix UIC2 vector number base
+
+    Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+
+commit ff5fb8a6ccba56e3482d0e297d8cfb7faa040811
+Author: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+Date:	Tue Jan 8 12:49:58 2008 +0100
+
+    ppc4xx: Update PLB/PCI divider for PMC440 board
+
+    This patch updates the PLB/PCI divider when running at
+    400MHz CPU frequency from 4 to 3 which results in 44MHz PCI sync clock.
+
+    Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+
+commit 7d5d75633174867316a0c0f2fca5ceb2cf312cde
+Author: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+Date:	Tue Jan 8 11:13:09 2008 +0100
+
+    ppc4xx: Disable error message when no NAND chip is installed on PMC440
+
+    Add CFG_NAND_QUIET_TEST option to disable error message when
+    no NAND chip is installed on PMC440 boards.
+
+    Disable a couple of config defines that are only used for NAND_U_BOOT.
+
+    Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+
+commit ad3006fe7e84667021753b74247b0bafd97ba35f
+Author: Gerald Van Baren <vanbaren@cideas.com>
+Date:	Mon Jan 7 23:47:32 2008 -0500
+
+    LIBFDT: use memmove() instead of memcpy()
+
+    This is partial patch from the DTC/libfdt
+    commit  67b6b33b9b413a450a72135b5dc59c0a1e33e647
+    Author: David Gibson <david@gibson.dropbear.id.au>
+    Date:   Wed Nov 21 11:56:14 2007 +1100
+
+	The patch also fixes one genuine bug caught by valgrind -
+	_packblocks() in fdt_rw.c was using memcpy() where it should have been
+	using memmove().
+
+    Signed-off-by: Gerald Van Baren <vanbaren@cideas.com>
+
+commit aec7135bc300e3340d18f203347ee00c5b5f68c0
+Author: David Gibson <david@gibson.dropbear.id.au>
+Date:	Mon Dec 17 14:42:07 2007 +1100
+
+    libfdt: Add more documentation (patch the seventh)
+
+    This patch adds more documenting comments to libfdt.h.  Specifically,
+    these document the read/write functions (not including fdt_open_into()
+    and fdt_pack(), for now).
+
+    Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
+
+commit 9d4450b5adc36623e9c1de1f92539db77ad0c57e
+Author: David Gibson <david@gibson.dropbear.id.au>
+Date:	Mon Dec 17 14:41:52 2007 +1100
+
+    libfdt: Add more documentation (patch the sixth)
+
+    This patch adds some more documenting comments to libfdt.h.
+    Specifically this documents all the write-in-place functions.
+
+    Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
+
+commit b60af3d4c1680487ee37e11aa1b3db6dec04d8f0
+Author: Gerald Van Baren <vanbaren@cideas.com>
+Date:	Sat Dec 29 22:45:27 2007 -0500
+
+    Fine grained per property /chosen updating.
+
+    Implement a suggestion by Scott Wood to make the /chosen handling fine
+    grained.  Don't overwrite pre-existing properties on a per-property basis,
+    so if /chosen exists but a necessary /chosen/property doesn't, it gets
+    created.  If a /chosen property exists, it is NOT overwritten unless the
+    "force" flag is true.
+
+    Signed-off-by: Gerald Van Baren <vanbaren@cideas.com>
+
+commit 238cb7a423c6eaa36496efb788cfb9798cea7f95
+Author: Gerald Van Baren <vanbaren@cideas.com>
+Date:	Sat Jan 5 15:33:29 2008 -0500
+
+    Improve the FDT help message.
+
+    Add a note that "fdt copy" makes the new address active.
+    Remove most of the extra hints at the end of the fdt help.
+
+    Signed-off-by: Gerald Van Baren <vanbaren@cideas.com>
+
+commit ea6d8be153ceaf16958f8009cea6d75f3ff58d92
+Author: Gerald Van Baren <vanbaren@cideas.com>
+Date:	Sat Jan 5 14:52:04 2008 -0500
+
+    Support setting FDT properties with optional values.
+
+    Fix a bug found and documented by Bartlomiej Sieka where the optional
+    value on "fdt set <path> <prop> [<val>]" wasn't optional.
+
+    => fdt mknode / testnode
+    => fdt print /testnode
+    testnode {
+    };
+    => fdt set /testnode testprop
+    => fdt print /testnode
+    testnode {
+	    testprop;
+    };
+
+    Signed-off-by: Gerald Van Baren <vanbaren@cideas.com>
+
+commit 22fb2246df91bfc840d87f0c5910818bad55577a
+Author: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+Date:	Fri Dec 28 11:56:30 2007 +0100
+
+    Add fdt_find_and_setprop() to fdt_support.h
+
+    fdt_find_and_setprop() is used by several 4xx boards and it's
+    missing in the appropriate header. This patch eliminates a
+    warning when building U-Boot for such boards.
+
+    Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+    Acked-by: Stefan Roese <sr@denx.de>
+
+commit 802b769bac17b0560d3535a42c502469ee190cd1
+Author: Stefan Roese <sr@denx.de>
+Date:	Tue Jan 8 18:39:30 2008 +0100
+
+    ppc4xx: Return 0 on success in 4xx ethernet driver
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 6775c68683a53c7abc778774641aac6f833a2cbf
+Author: Kim Phillips <kim.phillips@freescale.com>
+Date:	Tue Jan 8 09:59:49 2008 -0600
+
+    mpc83xx: fix missed pci_hose -> hose conversion for new libfdt code
+
+    Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
+
+commit 94fab25f5f1a7d1c0cc63c17e813ea8943fe49c7
+Author: Kim Phillips <kim.phillips@freescale.com>
+Date:	Thu Dec 20 16:28:34 2007 -0600
+
+    mpc83xx: rm remaining FLAT_TREE code
+
+    ..in board pci.c files
+
+    Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
+
+commit b3458d2cd55d01732e30a76d898afd99e871cd67
+Author: Kim Phillips <kim.phillips@freescale.com>
+Date:	Thu Dec 20 15:57:28 2007 -0600
+
+    mpc83xx: remove FLAT_TREE code
+
+    need to rm it from pci code, too!
+
+    Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
+
+commit 5b8bc606c61456566af6912f818a153b6b06f242
+Author: Kim Phillips <kim.phillips@freescale.com>
+Date:	Thu Dec 20 14:09:22 2007 -0600
+
+    mpc83xx: convert to using do_fixup_*()
+
+    convert to using simpler mpc85xx style fdt update code; streamline by
+    eliminating macros OF_SOC, OF_CPU, etc. which allows us to rm
+    the old school FLAT_TREE code from 83xx (since the sbc8349 was just
+    converted over to using libfdt).
+
+    Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
+
+commit e496865ecc31a2fe2f9abfe798334bb02aaf05ab
+Author: Paul Gortmaker <paul.gortmaker@windriver.com>
+Date:	Thu Dec 20 12:58:51 2007 -0500
+
+    sbc8349: enable libfdt by default on WRS SBC8349 board.
+
+    Make libfdt the default for the WRS SBC8349 board.
+    Parallel of commit 35cc4e4823668e8745854899cfaedd4489beb0ef
+    done for the other 83xx based boards.  Also fix a typo in CONFIG_PCI.
+
+    Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
+
+commit 2408b3f20bcbdd9c6c397cd03ab0d71d54680a40
+Author: Paul Gortmaker <paul.gortmaker@windriver.com>
+Date:	Thu Dec 20 12:58:16 2007 -0500
+
+    sbc8349: migrate board to libfdt
+
+    This adds libfdt support code for the Wind River sbc8349 board.
+
+    Parallel of commit 3fde9e8b22cfbd7af489214758f9839a206576cb for
+    the other Freescale 83xx boards.
+
+    Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
+
+commit 27a256a90cc86392ac9bf0039a3afe638ec2c18d
+Author: Paul Gortmaker <paul.gortmaker@windriver.com>
+Date:	Thu Dec 20 12:56:19 2007 -0500
+
+    sbc8349: Remove board specific ECC code
+
+    ECC code is now shared for all 83xx boards, so remove board specific one.
+    See commit daab8c67d2defef73dc26ab07f0c3afd1b05d019 for reference.
+
+    Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
+
+commit a1e1ac849249310e5e2e5c7148e9fb353a8317a7
+Author: Kim Phillips <kim.phillips@freescale.com>
+Date:	Thu Dec 20 01:30:48 2007 -0600
+
+    mpc83xx: Remove CONFIG options related to OF that we dont use (on 837x)
+
+    continuation of commit 37395fa2b0d9d617f28d44ca11592260ef16105a to 837x
+
+    Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
+
+commit ccf21c311e68d48399eff1e72936052885f6e3f7
+Author: Joakim Tjernlund <Joakim.Tjernlund@transmode.se>
+Date:	Thu Dec 6 16:43:40 2007 +0100
+
+    Add support CONFIG_UEC_ETH3 in MPC83xx
+
+    Signed-off-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se>
+
+commit e6af9932d31171e35db880e7b2f29f903b1b7660
+Author: Kumar Gala <galak@kernel.crashing.org>
+Date:	Mon Nov 26 11:00:54 2007 -0600
+
+    Remove CONFIG options related to OF that we dont use
+
+    The MPC8360E MDS config defined:
+	CONFIG_OF_HAS_BD_T
+	CONFIG_OF_HAS_UBOOT_ENV
+
+    Which we don't use or ever needed.	This seems like copy-paste feature creep.
+
+    Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit f602082b4b7ed4ee16432067cc67a0a24fedc715
+Author: Kim Phillips <kim.phillips@freescale.com>
+Date:	Mon Dec 10 14:16:22 2007 -0600
+
+    mpc83xx: supress compiler warning
+
+    mpc8360emds.c: In function ‘ft_board_setup’:
+    mpc8360emds.c:335: warning: assignment discards qualifiers from pointer target type
+    mpc8360emds.c:345: warning: assignment discards qualifiers from pointer target type
+
+    Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
+
+commit c16e44fa835fb9eec982d919863a04e2f78e5ce7
+Author: Kim Phillips <kim.phillips@freescale.com>
+Date:	Tue Nov 27 14:17:29 2007 -0600
+
+    mpc83xx: fix remaining fdt_find_node_by_path references
+
+    rename to fdt_path_offset
+
+    Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
+
+commit 921d4b19ad1be704df58725485d9292dc0414adf
+Author: Kim Phillips <kim.phillips@freescale.com>
+Date:	Mon Nov 19 12:30:09 2007 -0600
+
+    mpc83xx: fix CFG_ENV_ADDR and CFG_ENV_SECT_SIZE definitions for 837x
+
+    Fix the definitions of CFG_ENV_ADDR and CFG_ENV_SECT_SIZE for 837x.
+    This change guarantees that the environment will be located on the
+    first flash sector after the U-Boot image.
+
+    Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
+
+commit 24f868433b50ecbaa88e118aadc7bd254013c6ae
+Author: Kim Phillips <kim.phillips@freescale.com>
+Date:	Fri Nov 9 14:28:08 2007 -0600
+
+    mpc83xx: mpc8360 rev.2.1 erratum 2: replace rgmii-id with rgmii-rxid
+
+    u-boot itself uses GMII mode on the 8360.  Fix up UCC phy-connection-type
+    properties in the device tree so the PHY gets configured for internal delay on
+    RX only by the OS, as prescribed by mpc8360 rev. 2.1 pb mds erratum #2.
+
+    Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
+
+commit 22b448dbfbe2a98f01ff4adc3c3979f8c541ad7b
+Author: Dave Liu <r63238@freescale.com>
+Date:	Tue Sep 18 12:41:15 2007 +0800
+
+    mpc83xx: update the CREDITS and MAINTAINERS
+
+    update the CREDITS and MAINTAINERS.
+
+    Signed-off-by: Dave Liu <daveliu@freescale.com>
+
+commit b21add4b42af7b767448251b599b91066a160e0d
+Author: Dave Liu <r63238@freescale.com>
+Date:	Tue Sep 18 12:40:21 2007 +0800
+
+    mpc83xx: add MAINTAINER and MAKEALL entries for the mpc837xemds
+
+    Add the MAINTAINER and MAKEALL entries for mpc837xemds
+
+    Signed-off-by: Dave Liu <daveliu@freescale.com>
+
+commit f8900ce9094c462355eb792eea264ff16ac8fd16
+Author: Dave Liu <r63238@freescale.com>
+Date:	Tue Sep 18 12:38:53 2007 +0800
+
+    mpc83xx: Add the MPC837xEMDS board readme
+
+    Add the README.mpc837xemds to /doc
+
+    Signed-off-by: Dave Liu <daveliu@freescale.com>
+
+commit 19580e660cc8da49f16536a8bd78c047c7bc12e5
+Author: Dave Liu <r63238@freescale.com>
+Date:	Tue Sep 18 12:37:57 2007 +0800
+
+    mpc83xx: Add the support of MPC837xEMDS board
+
+    The MPC837xEMDS board support:
+    * DDR2 400MHz hardcoded and SPD init
+    * Local bus NOR Flash
+    * I2C, UART, MII and RTC
+    * eTSEC RGMII
+    * PCI host
+
+    Signed-off-by: Dave Liu <daveliu@freescale.com>
+
+commit 555da61702771fe0f76f3de23b4e7590f3704161
+Author: Dave Liu <r63238@freescale.com>
+Date:	Tue Sep 18 12:36:58 2007 +0800
+
+    mpc83xx: Add the support of MPC8315E SoC
+
+    The MPC8315E SoC including e300c3 core and new IP blocks,
+    such as TDM, PCI Express and SATA controller.
+
+    Signed-off-by: Dave Liu <daveliu@freescale.com>
+
+commit 03051c3d35c9981ceaa059005660e699f3eacf1c
+Author: Dave Liu <r63238@freescale.com>
+Date:	Tue Sep 18 12:36:11 2007 +0800
+
+    mpc83xx: Add the support of MPC837x SoC
+
+    The MPC837x SoC including e300c4 core and new IP blocks,
+    such as SDHC, PCI Express and SATA controller.
+
+    Signed-off-by: Dave Liu <daveliu@freescale.com>
+
+commit 651d96f7e4c84adcdb98ef07ec878c20326e3359
+Author: Anton Vorontsov <avorontsov@ru.mvista.com>
+Date:	Wed Nov 14 18:54:53 2007 +0300
+
+    MPC8360E-MDS: configure and enable second UART
+
+    Despite user manual, BCSR9.7 is negated (high) on HRST, so
+    UART2 is disabled. Fix that and configure QE pins properly.
+
+    Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
+
+commit b2893e1fcb28fad8c8b317104df8cee0142c7631
+Author: Timur Tabi <timur@freescale.com>
+Date:	Mon Nov 5 09:34:06 2007 -0600
+
+    83xx: fix CFG_ENV_ADDR and CFG_ENV_SECT_SIZE definitions
+
+    Fix the definitions of CFG_ENV_ADDR and CFG_ENV_SECT_SIZE for all of the
+    currently-defined 83xx boards.  This change guarantees that the environment
+    will be located on the first flash sector after the U-Boot image.
+
+    Signed-off-by: Timur Tabi <timur@freescale.com>
+    Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
+
+commit e05329516a13616b53240cd85b739217c2bf87f1
+Author: Larry Johnson <lrj@acm.org>
+Date:	Fri Jan 4 13:27:02 2008 -0500
+
+    ppc4xx: Remove weak binding from common Denali data-eye search code
+
+    Now that there are no board-specific versions of
+    "denali_core_search_data_eye()", the weak binding on the common version
+    can be removed.
+
+    Signed-off-by: Larry Johnson <lrj@acm.org>
+
+commit 5ba576c01602fd328800a427964c36a0a05c5dce
+Author: Stefan Roese <sr@denx.de>
+Date:	Sat Jan 5 09:13:46 2008 +0100
+
+    ppc4xx: Remove unused CONFIG_ECC_ERROR_RESET from 44x_spd_ddr2.c
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 845c6c95dbfe6c915ce68a0a115852fa17932fb4
+Author: Stefan Roese <sr@denx.de>
+Date:	Sat Jan 5 09:12:41 2008 +0100
+
+    ppc4xx: Update Katmai/44x_spd_ddr2.c code for optimal DDR2 setup
+
+    On Katmai the complete auto-calibration somehow doesn't seem to
+    produce the best results, meaning optimal values for RQFD/RFFD.
+    This was discovered by GDA using a high bandwidth scope,
+    analyzing the DDR2 signals. GDA provided a fixed value for RQFD,
+    so now on Katmai "only" RFFD is auto-calibrated.
+
+    This patch also adds RDCC calibration as mentioned on page 7 of
+    the AMCC PowerPC440SP/SPe DDR2 application note:
+    "DDR1/DDR2 Initialization Sequence and Dynamic Tuning"
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 49db47b8ae6afff2b898be312948ff501357dc80
+Author: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+Date:	Wed Jan 2 16:48:42 2008 +0100
+
+    ppc4xx: Remove sdram.h from PMC440 board
+
+    Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+
+commit 34065a2ce0d8972f2ec6652076014ab243d2ce8a
+Author: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+Date:	Wed Jan 2 16:48:34 2008 +0100
+
+    ppc4xx: use common denali core defines and data eye search code for PMC440
+
+    Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+
+commit 9ac6b6f3d3f1b072d89268b2efe47e95e6659489
+Author: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+Date:	Wed Jan 2 12:05:14 2008 +0100
+
+    ppc4xx: More cleanup for esd's LCD code
+
+    Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+
+commit fe9c26b330a21ce73e52b5bd347d725cb81e3cfb
+Author: Stefan Roese <sr@denx.de>
+Date:	Fri Jan 4 12:00:01 2008 +0100
+
+    ppc4xx: Fix Sequoia NAND booting target
+
+    The Sequoia NAND booting target now uses the recently extracted
+    cpu/ppc4xx/denali_data_eye.c file too.
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 0ddd969aec532bd7eae30fc09590488a3aaa629a
+Author: Lawrence R. Johnson <lrj@acm.org>
+Date:	Thu Jan 3 15:02:02 2008 -0500
+
+    ppc4xx: Use CFG_4xx_GPIO_TABLE to configure Korat board
+
+    Signed-off-by: Larry Johnson <lrj@acm.org>
+
+commit b05e8bf58be9d8956fdfde3d8c8e87c140414663
+Author: Lawrence R. Johnson <lrj@acm.org>
+Date:	Fri Jan 4 02:11:56 2008 -0500
+
+    ppc4xx: Use CFG_4xx_GPIO_TABLE to configure Sequoia board
+
+    Note: this patch changes the configuration of some GPIO registers:
+
+       Register      Old Value	 New Value
+    ---------------  ----------  ----------
+    DCR GPIO0_TCR    0x0000000F  0x0000F0CF
+    DCR GPIO0_TSRH   0x55005000  0x00000000
+    DCR GPIO1_TCR    0xC2000000  0xE2000000
+    DCR GPIO1_TSRL   0x0C000000  0x00200000
+    DCR GPIO1_ISR2L  0x00050000  0x00110000
+
+    Signed-off-by: Larry Johnson <lrj@acm.org>
+
+commit 5ab884b254ca2e707ab50545cd705f30108cf491
+Author: Lawrence R. Johnson <lrj@acm.org>
+Date:	Thu Jan 3 18:54:00 2008 -0500
+
+    ppc4xx: Add functionality to GPIO support
+
+    This patch makes two additions to GPIO support:
+
+    First, it adds function gpio_read_in_bit() to read the a bit from the
+    GPIO Input Register (GPIOx_IR) in the same way that function
+    gpio_read_out_bit() reads a bit from the GPIO Output Register
+    (GPIOx_OR).
+
+    Second, it modifies function gpio_set_chip_configuration() to provide
+    an additional option for configuring the GPIO from the
+    "CFG_4xx_GPIO_TABLE".
+
+    According to the 440EPx User's Manual, when an alternate output is used,
+    the three-state control is configured in one of two ways, depending on
+    the particular output.  The first option is to select the corresponding
+    alternate three-state control in the GPIOx_TRSH/L registers.  The second
+    option is to select the GPIO Three-State Control Register (GPIOx_TCR) in
+    the GPIOx_TRSH/L registers, and set the corresponding bit in the
+    GPIOx_TCR register to enable the output.  For example, the Manual
+    specifies configuring the GPIO00 Alternate 1 Signal (PreAddr07) to use
+    the alternate three-state control (first option), and specifies
+    configuring the GPIO32 Alternate 1 Signal (USB2OM0) with the output
+    enabled in the GPIOx_TCR register (second option).
+
+    Currently, gpio_set_chip_configuration() configures all alternate signal
+    outputs to use the first option.  This patch allow the second option to
+    be selected by setting the "out_val" element in the table entry to
+    "GPIO_OUT_1".  The first option is used when the "out_val" element is
+    set to "GPIO_OUT_0".  Because "out_val" is not currently used when an
+    alternate signal is selected, and because all current GPIO tables set
+    "out_val" to "GPIO_OUT_0" for all alternate signals, this patch should
+    not change any existing configurations.
+
+    Signed-off-by: Larry Johnson <lrj@acm.org>
+
+commit 196404cdc1de495d6182e84731c200fc5748df15
+Author: Larry Johnson <lrj@arlinx.com>
+Date:	Sun Dec 30 01:01:54 2007 -0500
+
+    PPC4xx: Remove sdram.h from board/lwmon5
+
+    These definitions are now in "include/ppc440.h".
+
+    Signed-off-by: Larry Johnson <lrj@acm.org>
+
+commit ef16fccf96e55eab93fe25d03ebe2e9b56e5332b
+Author: Larry Johnson <lrj@arlinx.com>
+Date:	Sun Dec 30 01:01:32 2007 -0500
+
+    PPC4xx: Use common code for LWMON5 board SDRAM support
+
+    This patch also modifies the functionality of the code so that the data-eye
+    search is now done with with the cache disabled.
+
+    Signed-off-by: Larry Johnson <lrj@acm.org>
+
+commit 62cc3951ab72135d9c101f1845b794e63a0fa189
+Author: Larry Johnson <lrj@arlinx.com>
+Date:	Sun Dec 30 01:01:14 2007 -0500
+
+    PPC4xx: Remove sdram.h from board/amcc/sequoia
+
+    These definitions are now in "include/ppc440.h".
+
+    Signed-off-by: Larry Johnson <lrj@acm.org>
+
+commit ce3902e1765bbfb07cf5bbe98be9a68e3009996a
+Author: Larry Johnson <lrj@arlinx.com>
+Date:	Sun Dec 30 01:00:50 2007 -0500
+
+    PPC4xx: Use common code for Sequoia board SDRAM support
+
+    Signed-off-by: Larry Johnson <lrj@acm.org>
+
+commit 8b0c5c127690335758100c25eaec2b84db97c101
+Author: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+Date:	Thu Dec 27 16:58:41 2007 +0100
+
+    net: Add CONFIG_NET_DO_NOT_TRY_ANOTHER option
+
+    When CONFIG_NET_DO_NOT_TRY_ANOTHER is defined U-Boot's
+    networking stack does not automatically switch to
+    another interface. This patch does not touch the default
+    behavior.
+
+    Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+    Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
+
+commit 505be87a65e4f87ad7d8da1d57ea4dcd487d7e32
+Author: Upakul Barkakaty <upakul@gmail.com>
+Date:	Thu Nov 29 12:16:13 2007 +0530
+
+    NET: Proper return code handling in eth_init() function in file eth.c
+
+    This patch modifies the return code handling in the eth_init()
+    function, to be compatible with the handling of the return codes in
+    the other network stack files. It now returns a 0 on Success and -1 on
+    error.
+
+    Signed-off-by: Upakul Barkakaty <upakul.barkakaty@conexant.com>
+    Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
+
+commit 5ca2d0953e4579a80810966cca2077e20d912c97
+Author: Shinya Kuribayashi <shinya.kuribayashi@necel.com>
+Date:	Mon Nov 19 20:27:04 2007 +0900
+
+    net/eth.c: Fix env_enetaddr signed overflow
+
+    Assigning the output of simple_strtoul(CB:A9:87:65:43:21) to `char', we are
+    warned as below:
+
+      U-Boot 1.2.0 (Aug 30 2007 - 08:27:37)
+
+      DRAM:  256 MB
+      Flash: 32 MB
+      In:    serial
+      Out:   serial
+      Err:   serial
+      Net:   NEC-Candy
+      Warning: NEC-Candy MAC addresses don't match:
+      Address in SROM is	 00:00:4C:80:92:A2
+      Address in environment is  FFFFFFCB:FFFFFFA9:FFFFFF87:65:43:21
+
+    This patch changes env_enetaddr type from `char' to `unsigned char'.
+
+    Cc: Masaki Ishikawa <ishikawa-masaki@cnt.mxe.nes.nec.co.jp>
+    Signed-off-by: Shinya Kuribayashi <shinya.kuribayashi@necel.com>
+    Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
+
+commit f85b60710571b37293d2233933b76e2aa3db5635
+Author: Rafal Jaworowski <raj@semihalf.com>
+Date:	Thu Dec 27 18:19:02 2007 +0100
+
+    Introduce new eth_receive routine
+
+    The purpose of this routine is receiving a single network frame, outside of
+    U-Boot's NetLoop(). Exporting it to standalone programs that run on top of
+    U-Boot will let them utilise networking facilities. For sending a raw frame
+    the already existing eth_send() can be used.
+
+    The direct consumer of this routine is the newly introduced API layer for
+    external applications (enabled with CONFIG_API).
+
+    Signed-off-by: Rafal Jaworowski <raj@semihalf.com>
+    Signed-off-by: Piotr Kruszynski <ppk@semihalf.com>
+    Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
+
+commit 5c740711f0ea5b51414b341b71597c4a0751be74
+Author: Jon Loeliger <jdl@freescale.com>
+Date:	Thu Jan 3 10:41:04 2008 -0600
+
+    8610: Move include of config.h earlier.
+
+    Include config.h earlier in the set of #includes
+    so as to avoid a incidental and duplicate definition
+    of CFG_CACHELINE_SIZE.
+
+    Signed-off-by: Jon Loeliger
+
+commit 61d3421bdea090bd0399b14c3e10a3bebcc8d5ff
+Author: Jon Loeliger <jdl@freescale.com>
+Date:	Tue Dec 4 10:53:34 2007 -0600
+
+    Don't slam #undef DEBUG in the 8641HPCN config file.
+
+    Doing so prevents it from being individually set
+    and useful in other files.
+
+    Signed-off-by: Jon Loeliger <jdl@freescale.com>
+
+commit ea9f7395ec362584e5e4f266bd0b0c4422cf6a4c
+Author: Jon Loeliger <jdl@freescale.com>
+Date:	Wed Nov 28 14:47:18 2007 -0600
+
+    Convert MPC8641HPCN to use libfdt.
+
+    Assumes the presence of the aliases node in the DTS to
+    locate the ethernet, pci and serial nodes for fixups.
+
+    Use consistent fdtaddr and fdtfile in environment variables.
+
+    Signed-off-by: Jon Loeliger <jdl@freescale.com>
+
+commit ce37422d0002e10490e268392e0c4e3028e52cec
+Author: Stefan Roese <sr@denx.de>
+Date:	Wed Jan 2 14:06:26 2008 +0100
+
+    cfi_flash: Fix bug in flash_isset() to use correct 32bit function
+
+    This bug was detected on the LWMON5 target which has 2 Intel 16bit wide
+    flash chips connected to a 32bit wide port.
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 1182e9f8e3b92fc372d64943293de53daa2e26cf
+Author: Wolfgang Denk <wd@denx.de>
+Date:	Wed Jan 2 15:58:44 2008 +0100
+
+    Fix compile problem introduced by "cleanup" commit 3dfd708c
+
+    Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit 1aaab9bfae0b3b2ee2b418c22c651280ee7b65c7
+Author: Wolfgang Denk <wd@denx.de>
+Date:	Wed Jan 2 15:54:45 2008 +0100
+
+    Make scripts and Makefiles POSIX compliant
+
+    The bash builtin versions of the "test" (resp. "[") command allow
+    using "==" for string comparisons, but POSIX compatible implemen-
+    tations (like /usr/bin/test) insist on using "=" only. On such systems
+    you will see:
+
+	$ /usr/bin/test a == a && echo OK
+	/usr/bin/test: ==: binary operator expected
+
+    This patch fixes Makefiles and scripts to use POSIX style.
+
+    Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit 3dfd708cc1b2a966ad454ca9ed125dd17dbadbcc
+Author: Wolfgang Denk <wd@denx.de>
+Date:	Wed Jan 2 12:38:43 2008 +0100
+
+    Minor coding style cleanup.
+
+    Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit e174ac34adf5d5653df12bc3cf19c52063a71269
+Author: Stefan Roese <sr@denx.de>
+Date:	Fri Dec 28 17:29:56 2007 +0100
+
+    ppc4xx: Coding style cleanup
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 8ba132cab18ae438b6dd5b0214c28a8fc0d976e5
+Author: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+Date:	Fri Dec 28 17:07:24 2007 +0100
+
+    ppc4xx: Complete PMC440 board support
+
+    This patch brings the PMC440 board configuration file.
+    Finally it enables the PMC440 board support.
+
+    Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+
+commit 407843a582560fc5231299561ab3c2b6b6cd3397
+Author: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+Date:	Fri Dec 28 17:07:18 2007 +0100
+
+    ppc4xx: Add FPGA support and BSP commands for PMC440 boards
+
+    This patch adds some BSP commands and FPGA booting support
+    for esd's PMC440 boards.
+
+    Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+
+commit 72c5d52aedcce35e4b4fa5895605554825b6a76f
+Author: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+Date:	Fri Dec 28 17:07:14 2007 +0100
+
+    ppc4xx: Add initial esd PMC440 board files
+
+    This patch adds the first files for the new esd PMC440 boards.
+    The next two patches will complete the PMC440 board support.
+
+    Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+
+commit f6e0f1f61896ce7729ba1bcea2ffbd138d3947f5
+Author: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+Date:	Fri Dec 28 17:10:36 2007 +0100
+
+    ppc4xx: Add EEPROM write protection for PLU405 boards + misc. updates
+
+    - add EEPROM write protection for esd PLU405 boards.
+    - initialize NAND GPIOs
+    - use correct io accessors
+    - cleanup
+
+    Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+
+commit 77660c4b59055d621d2a8595bd4c18bb277268fc
+Author: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+Date:	Fri Dec 28 17:10:44 2007 +0100
+
+    ppc4xx: use correct io accessors for esd's LCD code
+
+    This patch fixes esd's LCD dectection code to work correctly with
+    newer gcc versions.
+
+    Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+
+commit b56bd0fcfc1c73db722e3462c8a9bf607ba7775e
+Author: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+Date:	Fri Dec 28 17:10:42 2007 +0100
+
+    ppc4xx: Maintenance patch for VOH405 boards
+
+    - add EEPROM write protection
+    - initialize NAND GPIOs
+    - use correct io accessors
+    - slow down I2C clock to 100kHz
+    - enable ext. I2C bus
+    - cleanup
+
+    Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+
+commit c05569066dbcba3fdf36d4d1943df265dc316a86
+Author: Stefan Roese <sr@denx.de>
+Date:	Fri Dec 28 16:08:08 2007 +0100
+
+    ppc4xx: Enable 405EP PCI arbiter per default on all boards
+
+    In an attmemt to clean up the 4xx start.S file, I removed the enabling
+    of the internal 405EP PCI arbiter. This is needed for multiple other
+    405EP platforms, like most of the esd 405EP. Now the internal PCI
+    arbiter is enabled again per default as it has been before.
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+    Acked-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+
+commit bec9264616fb78273a1d93e87ff4b0b67c7bec1b
+Author: Stefan Roese <sr@denx.de>
+Date:	Fri Dec 28 15:53:46 2007 +0100
+
+    ppc4xx: Fix bug in cpu_init.c (405EP instead of 450EP)
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+    Acked-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+
+commit fb83a65c60ab5ca12358b75f1257e5eee6cdbf79
+Author: Stefan Roese <sr@denx.de>
+Date:	Fri Dec 28 06:06:04 2007 +0100
+
+    ppc4xx: Fix compilation problem of kilauea/haleakala nand booting target
+
+    Use correct link to nand_ecc now located in drivers/mtd/nand/ for the
+    platforms mentioned above.
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit b568fd25574181a3b12ae3d66b2913903442cb83
+Author: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+Date:	Thu Dec 27 17:03:46 2007 +0100
+
+    Remove CPCI440 board
+
+    This board never left prototyping state and it
+    became a millstone round my neck. So remove it.
+
+    Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+
+commit c591dffe0cbacd896ccbad06011fe6d6afa080da
+Author: Larry Johnson <lrj@arlinx.com>
+Date:	Thu Dec 27 11:28:51 2007 -0500
+
+    Add support for Korat PPC440EPx board
+
+    These patches add support for the PPC440EPx-based "Korat" board to
+    U-Boot.  They are based primarily on support for the Sequoia board.
+
+    Signed-off-by: Larry Johnson <lrj@acm.org>
+
+commit 87dc096829e6a6363f4fdd73653b0093a85adbe0
+Author: Larry Johnson <lrj@arlinx.com>
+Date:	Sat Dec 22 15:16:25 2007 -0500
+
+    Add configuration file for Korat board
+
+    This patch supplies the configuration file for the Korat PPC440EPx-
+    processor board.
+
+    Signed-off-by: Larry Johnson <lrj@acm.org>
+
+commit 8eb52d5d982b764b39c88d9d1064d56c5397bfa5
+Author: Larry Johnson <lrj@arlinx.com>
+Date:	Sat Dec 22 15:16:11 2007 -0500
+
+    Add denali_data_eye.o and denali_spd_ddr2.o to PPC4xx Makefile
+
+    Signed-off-by: Larry Johnson <lrj@acm.org>
+
+commit aba19604d848b2838cfb9ebe818909e6a216058e
+Author: Larry Johnson <lrj@arlinx.com>
+Date:	Thu Dec 27 10:54:48 2007 -0500
+
+    Add 440EPx DDR2 SPD DIMM support
+
+    This patch adds SPD DDR2 support for the 440EPx ("Denali") SDRAM
+    controller.  It should also work on the 440GRx.  It is based on the DDR2
+    SPD code for the 440EP/440EPx, but makes no provision for DDR1 support.
+
+    This code has been tested on prototype Korat boards with three Kingston
+    DIMMS: 512 MiB ECC (one rank), 512 MiB non-ECC (one rank) and 1 GiB ECC
+    (two ranks).  The Korat board has a single DIMM socket, but support has
+    been provided (though not tested) for boards with two DIMM sockets.
+
+    Signed-off-by: Larry Johnson <lrj@acm.org>
+
+commit 8a24a6963002cb867d5a6b70e3560f0b1467f55f
+Author: Larry Johnson <lrj@arlinx.com>
+Date:	Sat Dec 22 15:15:30 2007 -0500
+
+    Copy 440EPx/GRx SDRAM data-eye search to common directory
+
+    This patch creates a non-board-specific file for performing the SDRAM
+    data-eye search.  It also adds ECC error checking to the test of valid
+    data on readback when ECC is enabled.
+
+    Signed-off-by: Larry Johnson <lrj@acm.org>
+
+commit c46f53333b22b1f9098676bea8884fc7db820cf3
+Author: Larry Johnson <lrj@arlinx.com>
+Date:	Sat Dec 22 15:15:13 2007 -0500
+
+    Add definitions for 440EPx/GRx SDRAM controller to ppc440.h
+
+    This patch adds the Denali SDRAM controller definitions to "ppc440.h".
+    It also fixes two typos in the definitions, so the board-specific
+    "sdram.h" files containing these definitions are also fixed to avoid
+    compiler warnings.
+
+    Signed-off-by: Larry Johnson <lrj@acm.org>
+
+commit c348578bf612d0c56d8d376d23cae16defbd86af
+Author: Larry Johnson <lrj@arlinx.com>
+Date:	Thu Dec 27 10:50:55 2007 -0500
+
+    Add Ethernet 1000BASE-X support for PPC4xx
+
+    This patch adds a new switch: "CONFIG_PHY_DYNAMIC_ANEG".  When this symbol
+    is defined, the PHY will advertise it's capabilities for autonegotiation
+    based on the capabilities shown in the PHY's status registers, including
+    1000BASE-X.  When "CONFIG_PHY_DYNAMIC_ANEG" is not defined, the PHY will
+    advertise hard-coded capabilities, as before.
+
+    Signed-off-by: Larry Johnson <lrj@acm.org>
+
+commit 9e2c347151db5ae8acf5f18b99493cd53e6637e3
+Author: Larry Johnson <lrj@arlinx.com>
+Date:	Thu Dec 27 09:52:17 2007 -0500
+
+    Add driver for National Semiconductor LM73 temperature sensor
+
+    This driver is based on the driver for the LM75.
+
+    Signed-off-by: Larry Johnson <lrj@acm.org>
+
+commit 12618278688ea9b3d76536960a5ad2e3790fac40
+Author: Larry Johnson <lrj@arlinx.com>
+Date:	Sat Dec 22 15:14:00 2007 -0500
+
+    Add driver for STMicroelectronics M41T60 RTC
+
+    This driver is based on the driver for the M41T11.	In the intended
+    application, the RTC will be powered by a large capacitor, rather than a
+    battery.  The driver therefore checks to see whether the RTC has lost
+    power.  The chip's OUT bit is normally reset from its power-up state.  If
+    the OUT bit is read as set, or if the date and time are not valid, then the
+    RTC is assumed to have lost power, and its date and time are reset to
+    1900-01-01 00:00:00.
+
+    Support for adjusting the speed of the clock to improve accuracy is
+    provided through an environment variable.
+
+    Signed-off-by: Larry Johnson <lrj@acm.org>
+
+commit d3471173e14b7544bb60339eda8d3d3906694b0a
+Author: Larry Johnson <lrj@arlinx.com>
+Date:	Sat Dec 22 15:34:39 2007 -0500
+
+    Use out_be32() and friends to access memory-mapped registers in sequoia.c
+
+    Signed-off-by: Larry Johnson <lrj@acm.org>
+
+commit c68f59fe3ec16769f82b5fca7421983c336d3aac
+Author: Larry Johnson <lrj@arlinx.com>
+Date:	Sat Dec 22 15:34:20 2007 -0500
+
+    Use definitions from "asm-ppc/mmu.h" in init.S for Sequoia
+
+    Signed-off-by: Larry Johnson <lrj@acm.org>
+
+commit 0d9cdeac1d3fa8d62ed7d883acc950c364f5bda8
+Author: Larry Johnson <lrj@arlinx.com>
+Date:	Sat Dec 22 15:23:50 2007 -0500
+
+    Cosmetic changes to ECC POST for AMCC Denali core
+
+    Signed-off-by: Larry Johnson <lrj@acm.org>
+
+commit 2e583d6c81034f80a267b89fa55498ae063ccef1
+Author: Stefan Roese <sr@denx.de>
+Date:	Wed Dec 26 20:20:19 2007 +0100
+
+    ppc4xx: Fix compilation problem in 405 cache POST test
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 42d55ea0bde06e47d5a3b49b0d91002acd8e5708
+Author: Stefan Roese <sr@denx.de>
+Date:	Sat Dec 22 12:20:09 2007 +0100
+
+    ppc4xx: Move virtual address of POST cache test to bigger address
+
+    On Sequoia & LWMON5 the virtual address of the POST cache test is now
+    moved to a bigger address. This enables usage of more memory on those
+    boards.
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit d91722102cf63f77a0148ed3f3d54a26d87575e9
+Author: Stefan Roese <sr@denx.de>
+Date:	Sat Dec 22 12:18:26 2007 +0100
+
+    ppc4xx: Fix problem in 44x cache POST routine
+
+    As repoted by Larry Johnson, running "diag run cache" caused a crash
+    in U-Boot. This problem was introduced by a patch that removed the
+    TLB entry for the cache test after the test has completed. Since this
+    TLB was only setup once, a 2nd attempt to run this cache test
+    failed with a crash. Now this TLB entry is created every time the
+    routine is called.
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit b0265b576bb8fa9465f99e99c323768b562fadc2
+Author: Stefan Roese <sr@denx.de>
+Date:	Fri Dec 21 07:51:29 2007 +0100
+
+    ppc4xx: Update Makalu fdt support
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit bf8324e4a50758daff8cddd04c6a2ff8ed775bea
+Author: Stefan Roese <sr@denx.de>
+Date:	Wed Dec 19 09:05:40 2007 +0100
+
+    ppc4xx: Add fdt support to AMCC Katmai eval board
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 328a340392a5df9aaf00792be989df73e750859e
+Author: Stefan Roese <sr@denx.de>
+Date:	Tue Dec 18 08:44:51 2007 +0100
+
+    ppc4xx: fdt: Cleanup setup of cpu node setup
+
+    Now the cpu node setup ("timebase-frequency" and "clock-frequency") is
+    without using the absolute path to the cpu node. This makes it possible
+    to use this U-Boot version with both versions of cpu-node naming
+    "cpu@0" and the former "PowerPC,440EPx@0".
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 7812bc4a2e2436ebbc0ce5b4e99c1dfc2e77eb5b
+Author: Stefan Roese <sr@denx.de>
+Date:	Mon Dec 17 17:26:21 2007 +0100
+
+    ppc4xx: Fix lwmon5 compilation problem
+
+    Now that the 440EPx ECC test is not board specific anymore
+    remove this Makefile.
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 42ed33ffe135f618680f9d6e9712eb35a85bcb62
+Author: Anatolij Gustschin <agustschin@t-online.de>
+Date:	Wed Dec 5 17:43:20 2007 +0100
+
+    Fix ppc4xx clear_bss() code
+
+    ppc4xx clear_bss() fails if BSS segment size is not
+    divisible by 4 without remainder. This patch provides
+    fix for this problem.
+
+    Signed-off-by: Anatolij Gustschin <agust@denx.de>
+
+commit 85dc2a7f82d11e17f0ca2a448118aed7f7a4b85d
+Author: Niklaus Giger <niklausgiger@gmx.ch>
+Date:	Fri Nov 30 18:35:11 2007 +0100
+
+    PPC4xx: Minimal changes to add vxWorks support
+
+    Signed-off-by: Niklaus Giger <niklaus.giger@netstal.com>
+
+commit 052440b022ca8981d39b6f8c10d1aa6326f47480
+Author: Markus Klotzbücher <mk@denx.de>
+Date:	Fri Nov 23 13:09:18 2007 +0100
+
+    ppc4xx: Add CONFIG_BOOTP_SUBNETMASK to Sequoia board config
+
+    When using dhcp/bootp the "netmask" environment variable is not
+    set because CONFIG_BOOTP_SUBNETMASK is not defined. But usually this is
+    desireable, so the following patch adds this this option to the board
+    config.
+
+    Signed-off-by: Markus Klotzbuecher <mk@denx.de>
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit a724a9b40c7fbeb6ade193ca52321b441eaecb4e
+Author: Larry Johnson <lrj@arlinx.com>
+Date:	Sat Oct 27 12:48:15 2007 -0400
+
+    Fix/enhance ECC POST for 440EPx/GRx
+
+    This patch allows the ECC POST to be used for different boards with the
+    PPC440 Denali SDRAM controller.  Modifications include skipping the test
+    if ECC is not enabled (as for non-ECC DIMMs) and adding synchronization
+    to prevent timing errors.
+
+    Signed-off-by: Larry Johnson <lrj@acm.org>
+
+commit 454a6cf8d498f70d2b3e18f07837603eb24b12d4
+Author: Larry Johnson <lrj@arlinx.com>
+Date:	Sat Oct 27 12:48:05 2007 -0400
+
+    PPC4xx: Move/rename ECC POST for 440EPx/GRx
+
+    Signed-off-by: Larry Johnson <lrj@acm.org>
+
+commit c29d2d3680046d430022c55e50fcb27f5866517e
+Author: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+Date:	Fri Dec 14 11:20:33 2007 +0100
+
+    ppc4xx: use correct io accessors for 4xx ethernet POST
+
+    Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+
+commit ba79fde58a48c0a6ff8e2a96caba951594142203
+Author: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+Date:	Fri Dec 14 11:19:56 2007 +0100
+
+    ppc4xx: fix flush + invalidate_dcache_range arguments
+
+    flush + invalidate_dcache_range() expect the start and stop+1 address.
+    So the stop address is the first address behind (!) the range.
+
+    Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+
+commit 871e6ce188a7c6bc7321bcf8372857035d20f1cd
+Author: Stefan Roese <sr@denx.de>
+Date:	Fri Dec 14 08:41:29 2007 +0100
+
+    ppc4xx: fdt: use fdt_fixup_ethernet()
+
+    By using aliases in the dts file, the ethernet node fixup is
+    much easier with the recently added functions.
+
+    Please note that the dts file needs the aliases for this to work.
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 136288847e3b04f2ff357a067ad45e10afa0a24c
+Author: Stefan Roese <sr@denx.de>
+Date:	Thu Dec 13 14:52:53 2007 +0100
+
+    ppc4xx: Bring 4xx fdt support up-to-date
+
+    This patch update the 4xx fdt support. It enabled fdt booting
+    on the AMCC Kilauea and Sequoia for now. More can follow later
+    quite easily.
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 0dc80e2759fba859ccc4cdadc633577ca2971f3e
+Author: Stefan Roese <sr@denx.de>
+Date:	Thu Dec 27 07:50:54 2007 +0100
+
+    cfi_flash: Add missing check for erased dest to flash_write_cfibuffer()
+
+    The check for an sufficiently erased destination was missing in the
+    buffered write function of the cfi flash driver (when
+    CFG_FLASH_USE_BUFFER_WRITE is defined). This patch adds this check to that
+    writing to such a region will fail with the currect error message.
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 33ed73bc0e38d0f2b5c183d4629d8f207e5b9994
+Author: Martin Krause <martin.krause@tqs.de>
+Date:	Mon Nov 12 10:56:17 2007 +0100
+
+    Some configuration updates for the TQM5200 based TB5200 board:
+
+    - enable command line history
+    - increase malloc space (because of bigger flash sectors)
+
+    Signed-off-by: Martin Krause <martin.krause@tqs.de>
+
+commit e318d9e9021a0af7508171f84ed09d0e79f0284e
+Author: Martin Krause <martin.krause@tqs.de>
+Date:	Thu Sep 27 11:10:08 2007 +0200
+
+    TQM8xx: use the CFI flash driver on all TQM8xx boards
+
+    Signed-off-by: Martin Krause <martin.krause@tqs.de>
+
+commit 11d9eec479b470eab9242ab937fca70a876d9376
+Author: Martin Krause <martin.krause@tqs.de>
+Date:	Wed Sep 26 17:55:56 2007 +0200
+
+    TQM885D: adjust for doubled flash sector size + some minor fixes
+
+    Signed-off-by: Martin Krause <martin.krause@tqs.de>
+
+commit 22d1a56cbfb0bff34f477b4db6a55d076d829b83
+Author: Jens Gehrlein <jens.gehrlein@tqs.de>
+Date:	Wed Sep 26 17:55:54 2007 +0200
+
+    TQM885D: Exchanged SDRAM timing by a more relaxed timing.
+
+    CAS-Latency=2, Write Recovery Time tWR=2
+    The max. supported bus frequency is 66 MHz. Therefore, changed
+    threshold to switch from 1:1 mode to 2:1 from 80 MHz to 66 MHz.
+
+    Signed-off-by: Martin Krause <martin.krause@tqs.de>
+
+commit b988b8cd443989be65161888eea0127ad03f846f
+Author: Martin Krause <martin.krause@tqs.de>
+Date:	Wed Sep 26 17:55:56 2007 +0200
+
+    TQM885D: use calculated cpuclk instead of measuring it
+
+    On the TQM885D the measurement of cpuclk with the PIT reference
+    timer ist not necessary. Since all module variants use the same
+    external 10 MHz oscillator, the cpuclk only depends on the PLL
+    configuration - which is readable by software.
+
+    Signed-off-by: Martin Krause <martin.krause@tqs.de>
+
+commit 492c7049869348d31168de8dad89651315e468e0
+Author: Jens Gehrlein <jens.gehrlein@tqs.de>
+Date:	Thu Sep 27 14:54:46 2007 +0200
+
+    TQM885D: fix SDRAM refresh
+
+    At 133 MHz the current SDRAM refresh rate is too fast
+    (measured 4 * 1.17 us).
+    CFG_MAMR_PTA changes from 39 to 128. This result
+    in a refresh rate of 4 * 7.8 us at the default clock
+    66 MHz. At 133 MHz the value will be then 4 * 3.8 us.
+    This is a compromise until a new method is found to
+    adjust the refresh rate.
+
+    Signed-off-by: Martin Krause <martin.krause@tqs.de>
+
+commit dabad4b9bc46908e301f73ce76b38b23626a96e9
+Author: Jens Gehrlein <jens.gehrlein@tqs.de>
+Date:	Thu Sep 27 14:54:46 2007 +0200
+
+    TQM860M: Support for 10col SDRAMs, max. 128 MiB
+
+    Signed-off-by: Martin Krause <martin.krause@tqs.de>
+
+commit 61fb15c516fef5631e305f1976d7b3a679725856
+Author: Wolfgang Denk <wd@denx.de>
+Date:	Thu Dec 27 01:52:50 2007 +0100
+
+    Fix coding style issues; update CHANGELOG.
+
+    Signed-off-by: Wolfgang Denk <wd@denx.de>
+
 commit 467bcee11fe26ad422f2de971aa70866079870f2
 Author: Haavard Skinnemoen <hskinnemoen@atmel.com>
 Date:	Fri Dec 14 15:36:18 2007 +0100
@@ -167,6 +1539,18 @@ Date:	Fri Jun 29 18:22:34 2007 +0200
 
     Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
 
+commit 8697e6a19b10f514511b6a9c86de88bd108c4f8d
+Author: Stefan Roese <sr@denx.de>
+Date:	Thu Dec 13 14:52:53 2007 +0100
+
+    ppc4xx: Bring 4xx fdt support up-to-date
+
+    This patch update the 4xx fdt support. It enabled fdt booting
+    on the AMCC Kilauea and Sequoia for now. More can follow later
+    quite easily.
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
 commit 12d30aa79779c2aa7a998bbae4c075f822a53004
 Author: Haavard Skinnemoen <hskinnemoen@atmel.com>
 Date:	Thu Dec 13 12:56:34 2007 +0100
@@ -497,6 +1881,36 @@ Date:	Thu Nov 29 00:15:30 2007 -0600
 
     Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
 
+commit 3b9abdc448a1c2c6a4c2aa292724b4d1a05166a9
+Author: Stefan Roese <sr@denx.de>
+Date:	Tue Dec 11 13:38:19 2007 +0100
+
+    ppc4xx: Correct GPIO offset in gpio_config()
+
+    Thanks to Gary Jennejohn for pointing this out.
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 8809a2713b1ceaf3da55d9d785470294f15de06a
+Author: Stefan Roese <sr@denx.de>
+Date:	Tue Dec 11 11:46:01 2007 +0100
+
+    rtc: Fix merging problem
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 7cfc12a7dcfdb350e2ab76db4dafcc30f7e77c2b
+Author: Stefan Roese <sr@denx.de>
+Date:	Sat Dec 8 14:47:34 2007 +0100
+
+    ppc4xx: 405EX: Correctly enable USB pins
+
+    This patch selects the USB data pins in the 405EX GPIO and MFC (multi
+    function control) registers. This is done for the AMCC Kilauea and
+    Makalu eval boards.
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
 commit 9692c2734a47f23b44a0f68042a3e2ca8d1bfb39
 Author: Stefan Roese <sr@denx.de>
 Date:	Sat Dec 8 08:25:09 2007 +0100
@@ -613,6 +2027,58 @@ Date:	Thu Dec 6 10:21:03 2007 +0100
 
     Signed-off-by: Wolfgang Denk <wd@denx.de>
 
+commit a27044b14a9e93678a82d7b35f202b93e7687abc
+Author: Stefan Roese <sr@denx.de>
+Date:	Thu Dec 6 05:58:43 2007 +0100
+
+    ppc4xx: Enable hardware-fix for PCI/DMA errata on AMCC 440SP/SPe boards
+
+    This patch enables the hardware-fix for the PCI/DMA errata's 19+22 by
+    setting the FIXD bit in the SDR0_MFR register. Here a description of the
+    symptoms:
+
+    Problem Description
+    ------------------------------
+    If a DMA is performed between memory and PCI with the DMA 1 Controller
+    using prefetch, and as a result uses a special purpose buffer selected by
+    the PCIXn Bridge Options 1 Register (PCIXn_BRDGOPT1[RBP7] - bits 31-29),
+    the first part of the transfer sequence is performed twice. The
+    PPC440SPe PCI Controller requests more data than was needed such that in
+    the case of enforce memory protection, a host CPU  exception can occur.
+    No data is corrupted, because data transfer is stopped in the PCI
+    Controller. Prefetch enable is specified by setting DMA Configuration
+    Register (I2O0_DMAx_CFG[DXEPD] - bit 31) to 0.
+
+    Behavior that may be observed in a running system
+    ---------------------------------------------------------------------------
+
+    1. DMA performance is decreased because of the double access on the PCI bus
+    interface.
+    2. If an illegal access to some address on the PCI bus is detected at the
+    system level, a machine check or similar system error may occur.
+
+    Workarounds Available
+    ----------------------------------
+
+    1. Do not program prefetch. Note that a prefetch command cannot be programmed
+    without selecting a special purpose buffer.
+    2. To avoid crossing a physical boundary of the PCI slave device, add 512
+    bytes of address to the PCI address range.
+
+    This patch was originally provided by Pravin M. Bathija <pbathija@amcc.com>
+    from AMCC and slighly changed.
+
+    Signed-off-by: Pravin M. Bathija <pbathija@amcc.com>
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit a90921f71d225bf9e0f0fc7b8beadeb8001bf78a
+Author: Stefan Roese <sr@denx.de>
+Date:	Tue Dec 4 16:29:48 2007 +0100
+
+    ppc4xx: Yosemite/Yellowstone: Add DTT AD7414 support
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
 commit 8d4f040a3c15036a6ea25a9c39e7d89fefa8440d
 Author: Wolfgang Denk <wd@denx.de>
 Date:	Mon Dec 3 00:15:28 2007 +0100
@@ -621,6 +2087,18 @@ Date:	Mon Dec 3 00:15:28 2007 +0100
 
     Signed-off-by: Wolfgang Denk <wd@denx.de>
 
+commit e15e33433e7c05111968dc9b434a52fd42cbd221
+Author: Stefan Roese <sr@denx.de>
+Date:	Fri Nov 30 07:15:41 2007 +0100
+
+    ppc4xx: Kilauea: Add PCIe reset assertion upon power-up
+
+    This manual PCIe reset triggering solves the problem seen with the
+    Intel EPRO/1000 card, which was not detected (link not established)
+    upon power-up reset.
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
 commit 260eea5676ca46903a335686cc020b29c4ca46fe
 Author: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
 Date:	Thu Nov 29 01:21:54 2007 +0900
@@ -682,6 +2160,18 @@ Date:	Sun Nov 25 02:32:13 2007 +0900
 
     Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
 
+commit 8be760903645af09871be50ad0a6f9ebb62b311d
+Author: Stefan Roese <sr@denx.de>
+Date:	Tue Nov 27 11:57:35 2007 +0100
+
+    ppc4xx: Kilauea & Makalu: Fix ext IRQ pin multiplexing
+
+    After an error in the AMCC 405EX users manual now correctly configure
+    IRQ2 (Kilauea)/IRQ0 (Makalu) as alternate 2 signal for external IRQ
+    usage.
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
 commit a5f601fd1b1278deae5aa9fc27a232b0d1c1c788
 Author: Wolfgang Denk <wd@denx.de>
 Date:	Mon Nov 26 19:18:21 2007 +0100
@@ -706,6 +2196,25 @@ Date:	Sun Nov 25 18:45:47 2007 +0100
 
     Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
 
+commit 63362cfc6baa97ae0e37ba2c6ece530fcac9f79e
+Author: Stefan Roese <sr@denx.de>
+Date:	Mon Nov 26 15:06:14 2007 +0100
+
+    ppc4xx: Makalu: Change EBC setup for CS0 to enable 400MHz usage
+
+    As suggested by Senao, use a different EBC_PB0AP setup for 400MHz
+    operation.
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit ca1ce226287270bb01e25b8e3674c701f12edf19
+Author: Stefan Roese <sr@denx.de>
+Date:	Mon Nov 26 15:01:45 2007 +0100
+
+    ppc4xx: Kilauea: Configure pin mux to use ext IRQ2 as interrupt
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
 commit 87ddedd6ad804427ce125ceaa076d7a4f74e9d5d
 Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
 Date:	Sun Nov 25 18:45:47 2007 +0100
@@ -974,6 +2483,28 @@ Date:	Mon Sep 24 09:05:31 2007 -0600
 
     Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
 
+commit 68b88999da87ab88e71e1306192905be3450198e
+Author: Jon Loeliger <jdl@freescale.com>
+Date:	Tue Nov 20 15:02:26 2007 -0600
+
+    8610HPCD: Enable the 8610 Display Interface Unit
+
+    Signed-off-by: Jon Loeliger <jdl@freescale.com>
+
+commit 74f89faa9d1e77ed947e628d3effaa513fe05d05
+Author: Jon Loeliger <jdl@freescale.com>
+Date:	Tue Nov 20 15:00:53 2007 -0600
+
+    Move 8610 DIU interface structure definitions to header file.
+
+    These two structures are still needed during the
+    initialization and setup of the DIU hardware.
+    So move them to the fsl_diu_fb.h file for now.
+    Official "blah".
+
+    Noticed-by: York Sun <yorksun@freescale.com>
+    Signed-off-by: Jon Loeliger <jdl@freescale.com>
+
 commit 080c646dbf474a109c3f85718fb01ce042a38c45
 Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
 Date:	Tue Nov 20 20:14:18 2007 +0100
@@ -1057,6 +2588,16 @@ Date:	Sun Nov 18 16:36:27 2007 +0100
 
     Signed-off-by: Wolfgang Denk <wd@denx.de>
 
+commit 653811a3c2b35856bf12e196dcc8c4694e28e420
+Author: Stefan Roese <sr@denx.de>
+Date:	Sun Nov 18 14:44:44 2007 +0100
+
+    ppc4xx: Correct 405EX PCIe UTL register mapping
+
+    Map 4k mem space for UTL registers for each port.
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
 commit 079c2c4fa71c0d1ebef394508df9088df8a308d3
 Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
 Date:	Sat Nov 17 11:31:10 2007 +0100
@@ -1082,6 +2623,16 @@ Date:	Sat Nov 17 07:58:25 2007 +0100
 
     Signed-off-by: Stefan Roese <sr@denx.de>
 
+commit 9ea61b57968554eaf0f474ec7e088b17d367f474
+Author: Stefan Roese <sr@denx.de>
+Date:	Sat Nov 17 14:52:29 2007 +0100
+
+    ppc4xx: Update AMCC Kilauea config file
+
+    - Use generic GPIO configuration framework (CFG_4xx_GPIO_TABLE)
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
 commit 7e1d884b7cb602007329c517ec1c453e3a6a5d9c
 Author: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
 Date:	Sat Nov 17 20:05:26 2007 +0900
@@ -1337,6 +2888,33 @@ Date:	Wed Nov 7 08:19:19 2007 +0100
 
     Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
 
+commit f31d38b9eea9b32f6a1ac848a298cc71ca4c9a03
+Author: Stefan Roese <sr@denx.de>
+Date:	Fri Nov 16 14:16:54 2007 +0100
+
+    ppc4xx: Enable 405EX PCIe UTL register configuration
+
+    Till now the UTL registers on 405EX were not initialized but left with
+    their default values. This patch new initializes some of the UTL
+    registers on 405EX.
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit ecdcbd4f8c1f8cefd785752f4e7536aae2a4ecf9
+Author: Stefan Roese <sr@denx.de>
+Date:	Fri Nov 16 14:00:59 2007 +0100
+
+    ppc4xx: Update AMCC Makalu for board rev 1.1
+
+    This patch adds changes needed for Makalu rev 1.1:
+
+    - Enable 2nd DDR2 bank resulting in 256MByte of SDRAM
+    - Enable 2nd ethernet port EMAC1
+    - Use generic GPIO configuration framework (CFG_4xx_GPIO_TABLE)
+    - Reset PCIe ports via GPIO upon bootup
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
 commit 4d4faae65e115e327425cd514c1a35146a85166b
 Author: Grant Likely <grant.likely@secretlab.ca>
 Date:	Mon Sep 24 09:05:31 2007 -0600
@@ -1470,6 +3048,98 @@ Date:	Thu Nov 15 08:20:25 2007 -0700
     This reverts commit 8d17979d0359492a822a0a409d26e3a3549b4cd4.
     Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
 
+commit c9672f81f1bdb4e8ddf62aa72ca0206e8b72aa1c
+Author: Stefan Roese <sr@denx.de>
+Date:	Thu Nov 15 14:25:09 2007 +0100
+
+    ppc4xx: Small AMCC Kilauea cleanup
+
+    Remove not needed pci_target_init() function.
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit aee747f19b460a0e9da20ff21e90fdaac1cec359
+Author: Stefan Roese <sr@denx.de>
+Date:	Thu Nov 15 14:23:55 2007 +0100
+
+    ppc4xx: Enable 440 GPIO init table CFG_440_GPIO_TABLE for 405 platforms
+
+    - Rename CFG_440_GPIO_TABLE to CFG_4xx_GPIO_TABLE
+    - Cleanup of the 4xx GPIO functions
+    - Move some GPIO defines from the cpu headers ppc405.h/ppc440.h into gpio.h
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 8ada0ebf38e4073beea0309188b25d82a112a2ae
+Author: Stefan Roese <sr@denx.de>
+Date:	Thu Nov 15 14:20:08 2007 +0100
+
+    ppc4xx: AMCC Taihu board config file cleanup
+
+    This patch makes the AMCC Taihu a little more compatible to the other
+    AMCC eval boards.
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 5e71c51d74c963d3174060c078dcacf13bdd02ef
+Author: Marian Balakowicz <m8@semihalf.com>
+Date:	Thu Nov 15 13:37:28 2007 +0100
+
+    [INKA4x0] NG hardware: flash support
+
+    Disabled and remove inka4x0 custom flash driver, use CFI flash
+    driver instead.
+
+    Signed-off-by: Marian Balakowicz <m8@semihalf.com>
+
+commit 5fb6d7191e206cdde0e23140fd8111caed93a595
+Author: Marian Balakowicz <m8@semihalf.com>
+Date:	Thu Nov 15 13:29:55 2007 +0100
+
+    [INKA4x0] NG hardware: SDRAM support
+
+    Add support for three new DDR chips that may  be present on a NG
+    INKA4x0 hardware: HYB25D512160BF-5, K4H511638C-7CB3, T46V32M16BN-6IT.
+
+    Cleanup board/inka4x0/mt48lc16m16a2-75.h file.
+
+    Signed-off-by: Marian Balakowicz <m8@semihalf.com>
+
+commit f23cb34c367bb27585a4fdb8a75277370e7d0596
+Author: Marian Balakowicz <m8@semihalf.com>
+Date:	Thu Nov 15 13:24:43 2007 +0100
+
+    [INKA4x0] NG hardware: platform code update
+
+    - Cleanup compile warnings.
+    - Add missing '\0' in default environment.
+    - Increase CFG_MONITOR_LEN to 256 KiB.
+    - Add required CFG_USE_PPCENV.
+
+    Signed-off-by: Marian Balakowicz <m8@semihalf.com>
+
+commit 2ae64f5135e51bb18753884d1265b99e89b5aedd
+Author: Peter Pearse <peter.pearse@arm.com>
+Date:	Thu Nov 15 08:58:00 2007 +0000
+
+    Remove warnings re CONFIG_EXTRA_ENV_SETTINGS
+    Remove warnings re onenand_read() & write()
+
+commit 2db916e14410e3ec1738508c7bf4dfeb2b299ae7
+Author: Peter Pearse <peter.pearse@arm.com>
+Date:	Thu Nov 15 08:45:13 2007 +0000
+
+    Correction patch
+
+commit 1d8a49eca1c7bdc8db1c47a92f9014a29ead03ae
+Author: Roy Zang <tie-fei.zang@freescale.com>
+Date:	Thu Sep 13 18:52:28 2007 +0800
+
+    Enable ULi1575 Ethernet support in 8610HPCD config
+
+    Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
+    Acked-by: Jon Loeliger <jdl@freescale.com>
+
 commit 54fd6c93c28a0a45352fff5dd92673401ff563f2
 Author: Stefan Roese <sr@denx.de>
 Date:	Tue Nov 13 08:18:20 2007 +0100
@@ -1478,6 +3148,14 @@ Date:	Tue Nov 13 08:18:20 2007 +0100
 
     Signed-off-by: Stefan Roese <sr@denx.de>
 
+commit 7d0a4066b5a6b698e5fc1b66cfe9705774bbce93
+Author: Stefan Roese <sr@denx.de>
+Date:	Tue Nov 13 08:06:11 2007 +0100
+
+    ppc4xx: Fix 405EX PCIe UTLSET register setup
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
 commit 1ce55151c85d068f70317a8d65c61058b891afb4
 Author: Heiko Schocher <hs@denx.de>
 Date:	Tue Nov 13 07:50:29 2007 +0100
@@ -1486,6 +3164,74 @@ Date:	Tue Nov 13 07:50:29 2007 +0100
 
     Signed-off-by: Heiko Schocher <hs@denx.de>
 
+commit 2d14684341109a69616e4d6016cd61402d55086f
+Author: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+Date:	Fri Nov 9 15:37:53 2007 +0100
+
+    ppc4xx: Use generic usb-ohci driver for sequoia board
+
+    This patch makes the sequoia board use the generic usb-ohci driver
+    instead of cpu/ppc4xx/usb_ohci.c.
+
+    Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 9be659ac0868dc367caa957c5c725e46b07f6a5f
+Author: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+Date:	Fri Nov 9 15:37:23 2007 +0100
+
+    ppc4xx: Make USB working with CONFIG_4xx_DCACHE defined
+
+    This patch disables the 44x d-cache on 'usb start' and
+    reenables it on 'usb stop'. This should be seen as a
+    temporary fix until the generic usb-ohci driver can
+    life with d-cache enabled.
+
+    Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit fbde2169d2c48fcc9ff03489534a78ffb0a8a0d4
+Author: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+Date:	Fri Nov 9 15:36:44 2007 +0100
+
+    ppc4xx: Remove redundant code from 4xx network driver
+
+    This patch removes some redundant code and decrements the end
+    address of cache flush and invalidate by 1.
+
+    Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 5ca9881aad8c413ac2a82868a5e3719178254502
+Author: Peter Pearse <peter.pearse@arm.com>
+Date:	Fri Nov 9 15:24:26 2007 +0000
+
+    Add apollon board support
+    Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
+
+commit b53313dbfc74525d85f1e7e0102f902d5c863beb
+Author: Stefan Roese <sr@denx.de>
+Date:	Fri Nov 9 12:19:58 2007 +0100
+
+    ppc4xx: Remove In:/Out:/Err: boot output for AMCC Kilauea
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit c7f69c340277935a6c19a956421852da944a365f
+Author: Stefan Roese <sr@denx.de>
+Date:	Fri Nov 9 12:18:54 2007 +0100
+
+    ppc4xx: Make output a little shorter on I2C bootrom detection
+
+    Most 4xx PPC capable of using an I2C bootrom for bootstrap setting
+    already print a line with the information which I2C bootrom is
+    used for bootstrap configuration. So we don't need this extra line
+    with "I2C boot EEPROM en-/dis-abled".
+
+    This patch also has a little code cleanup integrated.
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
 commit 8d737a28152ec12873f8544cca1fb39a49e5e693
 Author: TsiChungLiew <Tsi-Chung.Liew@freescale.com>
 Date:	Thu Nov 8 12:50:18 2007 -0600
@@ -1534,6 +3280,131 @@ Date:	Wed Nov 7 17:51:00 2007 -0600
 
     Signed-off-by: TsiChungLiew <Tsi-Chung.Liew@freescale.com>
 
+commit 070ba56115b4da63b46e974287fa4550d4023386
+Author: York Sun <yorksun@freescale.com>
+Date:	Wed Oct 31 14:59:04 2007 -0500
+
+    8610: Add console frame buffer support to FSL 8610 DIU driver.
+
+    Add cfb console support to FSL 8610 DIU driver.
+    Inspect board version from PIXIS to obtain correct pixel format.
+
+    Use #define CONFIG_VIDEO in config file to enable fb console.
+
+    To switch monitor, set monitor variable to
+    0 - DVI, 1 - Single link LVDS, 2 - Double link LVDS
+    followed by "diufb init".
+
+    Preserve logo bitmap at the top of the fb console.
+
+    Signed-off-by: York Sun <yorksun@freescale.com>
+    Signed-off-by: Jon Loeliger <jdl@freescale.com>
+
+commit a877880c6949e948bd63cd6ea4e216573d2f53dd
+Author: York Sun <yorksun@freescale.com>
+Date:	Mon Oct 29 13:58:39 2007 -0500
+
+    8610: Add 8610 DIU display driver
+
+    1280x1024 and 1024x768 @ 32 bpp are supported now.
+    DVI, Single-link LVDS, Double-link LVDS are all supported.
+
+    Environmental variable "monitor" is used to specify monitor port.
+
+    A new command "diufb" is introduced to reinitialize monitor
+    and display a BMP file in the memory. So far, 1-bit, 4-bit,
+    8-bit and 24-bit BMP formats are supported.
+
+	diufb init
+	    - initialize the diu driver
+	Enable the port specified in the environmental variable "monitor"
+
+	diufb addr
+	    - display bmp file in memory.
+	The bmp image should be no bigger than the resolution, 1280x1024
+	for DVI and double-link LVDS, 1024x768 for single-link LVDS.
+
+    Note, this driver allocate memory but doesn't free it after use
+    It is written on purpose -- to avoid a failure of reallocation
+    due to memory fragement.
+
+    ECC of DDR is disabled for DIU performance. L2 data cache is also disabled.
+
+    Signed-off-by: York Sun <yorksun@freescale.com>
+    Signed-off-by: Jon loeliger <jdl@freescale.com>
+
+commit 52e5ddfecdda308f75782fae206b677b1810f5f9
+Author: York Sun <yorksun@freescale.com>
+Date:	Wed Oct 31 10:43:59 2007 -0500
+
+    FSL: Add a freescale bitmap logo.
+
+    This Freescale logo is a 340 x 128 x 4bpp BMP file
+    that can be displayed by the DIU Framebuffer driver.
+
+    Signed-off-by: York Sun <yorksun@freescale.com>
+    Signed-off-by: Jon Loeliger <jdl@freescale.com>
+
+commit 1815338fbd1c0f94f8276d2891b99caa5a05f622
+Author: York Sun <yorksun@freescale.com>
+Date:	Mon Oct 29 13:57:53 2007 -0500
+
+    8610: Make some extra debug environment variables conditional.
+
+    One may #define ENV_DEBUG to get them back again.
+
+    Signed-off-by: York Sun <yorksun@freescale.com>
+
+commit 761421ccca80a9fb37b19c37aa61d46ef75e0647
+Author: Jason Jin <Jason.jin@freescale.com>
+Date:	Mon Oct 29 19:26:21 2007 +0800
+
+    8610: Actually enable pixis_reset CONFIGs
+
+    Signed-off-by: Jason Jin <Jason.jin@freescale.com>
+
+commit f3bceaab230b4748d0afc4109b6837308f018b40
+Author: Jason Jin <Jason.jin@freescale.com>
+Date:	Fri Oct 26 18:31:59 2007 +0800
+
+    Fix the BAT definition of PCI IO on 8610 board
+
+    The address in the BAT register is aligned with the BAT size.
+    The original definition actually did not define BAT for PCIE2 IO.
+    This patch fix this.
+
+    Signed-off-by: Jason Jin <Jason.jin@freescale.com>
+
+commit 9f23ca334a6f5f021ef9e9d0fad9da80d63b2d56
+Author: Jason Jin <Jason.jin@freescale.com>
+Date:	Mon Oct 29 19:26:21 2007 +0800
+
+    Unify pixis_reset altbank across board families
+
+    Basically, refactor the CFG_PIXIS_VBOOT_MASK values
+    into the separate board config files.
+
+    Signed-off-by: Jason Jin <Jason.jin@freescale.com>
+    Signed-off-by: Jon Loeliger <jdl@freescale.com>
+
+commit a8318ec205c8e8794b5f9f1b8584abadb440e8ba
+Author: Jason Jin <Jason.jin@freescale.com>
+Date:	Fri Oct 26 18:32:00 2007 +0800
+
+    make 8610 board use pixis reset
+
+    Signed-off-by: Jason Jin <Jason.jin@freescale.com>
+
+commit 9c84709eedce9c680dd695984ab7d2328f4f04f5
+Author: Jon Loeliger <jdl@freescale.com>
+Date:	Thu Nov 1 12:23:29 2007 -0500
+
+    86xx: Fix broken variable reference when #def DEBUGing.
+
+    Sometimes you can't reference the DDR2 controller variables.
+
+    Signed-off-by: Jon Loeliger <jdl@freescale.com>
+
 commit 1f103105a3746ab12279b63b8c1d372c0ce2cc58
 Author: Roy Zang <tie-fei.zang@freescale.com>
 Date:	Mon Nov 5 17:39:24 2007 +0800
@@ -1573,6 +3444,16 @@ Date:	Wed Oct 31 11:21:29 2007 -0500
     Signed-off-by: Larry Johnson <lrj@acm.org>
     Signed-off-by: Ben Warren <bwarren@qstreams.com>
 
+commit 654f38b3a387886996a5a75771fbfc29cb4f225e
+Author: Stefan Roese <sr@denx.de>
+Date:	Mon Nov 5 07:43:05 2007 +0100
+
+    ppc4xx: Make output a little shorter on PCIe detection
+
+    Now not max 3 lines but 2 lines are printed per PCIe port.
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
 commit 992742a5b09d9040adbd156fb90756af66ade310
 Author: Wolfgang Denk <wd@denx.de>
 Date:	Sat Nov 3 23:09:27 2007 +0100
@@ -1708,6 +3589,17 @@ Date:	Wed Oct 17 11:18:42 2007 +0200
     Signed-off-by: Sergej Stepanov <Sergej.Stepanov@ids.de>
     --
 
+commit 3d6cb3b24add6415f86a0f013ea40f5639b90047
+Author: Stefan Roese <sr@denx.de>
+Date:	Sat Nov 3 12:08:28 2007 +0100
+
+    ppc4xx: Add AMCC Kilauea/Haleakala NAND booting support
+
+    This patch adds NAND booting support for the AMCC 405EX(r) eval boards.
+    Again, only one image supports both targets.
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
 commit 8b6684a698500be9c142ec2c9f46cfc348e17f0c
 Author: Haavard Skinnemoen <hskinnemoen@atmel.com>
 Date:	Wed Oct 24 15:48:37 2007 +0200
@@ -1744,6 +3636,630 @@ Date:	Mon Oct 29 17:40:35 2007 -0400
     Signed-off-by: Justin Flammia <jflammia@savantav.com>
     Signed-off-by: Ben Warren <bwarren@qstreams.com>
 
+commit 5d96d40d3f36da33348e68f9ea993f383e11f997
+Author: Stefan Roese <sr@denx.de>
+Date:	Wed Oct 31 20:58:34 2007 +0100
+
+    ppc4xx: Fix acadia_nand build problem
+
+    Since the cache handling functions were moved from start.S into cache.S
+    the acadia NAND booting Makfile needs to be adapted accordingly.
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit ea2e142843533ca593fcb5cb3e1daf1b7f5e5949
+Author: Stefan Roese <sr@denx.de>
+Date:	Wed Oct 31 20:57:11 2007 +0100
+
+    ppc4xx: Add CONFIG_4xx_DCACHE compile options to enable cached SDRAM
+
+    This patch adds the CONFIG_4xx_DCACHE options to some SDRAM init files
+    and to the Sequoia TLB init code. Now the cache can be enabled on 44x
+    boards by defining CONFIG_4xx_DCACHE in the board config file. This
+    option will disappear, when more boards use is successfully and no
+    more known problems exist.
+
+    This is tested successfully on Sequoia and Katmai. The only problem that
+    needs to be fixed is, that USB is not working on Sequoia right now, since
+    it will need some cache handling code too, similar to the 4xx EMAC driver.
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 3db93b8bedd32e914b38976141b3fdf4ea3ff738
+Author: Stefan Roese <sr@denx.de>
+Date:	Wed Oct 31 20:51:10 2007 +0100
+
+    ppc4xx: Enable CPU POST test for 4xx with dcache enabled
+
+    Now with caches enabled (i- and d-cache) on 44x, we need a chance to
+    disable the cache for the CPU POST tests, since these tests consist
+    of self modifying code. This is done via the new change_tlb() function.
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit f71b2888b4b3c870909a0341427b2a914246f81f
+Author: Stefan Roese <sr@denx.de>
+Date:	Wed Oct 31 20:47:26 2007 +0100
+
+    ppc4xx: Change 4xx POST ethernet test to handle cached memory too
+
+    This patch enables the 4xx EMAC POST driver to work too, when dcache is
+    enabled.
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit a2685904061b35a17583d65fe47cdc2686a69eaa
+Author: Stefan Roese <sr@denx.de>
+Date:	Wed Oct 31 20:45:53 2007 +0100
+
+    ppc4xx: Remove temporary TLB entry in POST cache test only for 440
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit ff768cb168d8157c24a25016dbfbeb465e47f420
+Author: Stefan Roese <sr@denx.de>
+Date:	Wed Oct 31 18:01:24 2007 +0100
+
+    ppc4xx: Change 4xx ethernet driver to handle cached memory too
+
+    This patch enables the 4xx EMAC driver to work too, when dcache is
+    enabled.
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 483e09a223c666269ef81d3573a6591b1046b0ef
+Author: Stefan Roese <sr@denx.de>
+Date:	Wed Oct 31 17:59:22 2007 +0100
+
+    ppc4xx: Add change_tlb function to modify I attribute of TLB(s)
+
+    This function is used to either turn cache on or off in a specific
+    memory area.
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit d25dfe08fbd1220cb994e7e6b105049aa9aa8e79
+Author: Stefan Roese <sr@denx.de>
+Date:	Wed Oct 31 17:57:52 2007 +0100
+
+    ppc4xx: Remove cache definition from 4xx board config files
+
+    All 4xx board config files don't need the cache definitions anymore.
+    These are now defined in common headers.
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 9b94ac61d2176185c30adf0793e079ec30e68687
+Author: Stefan Roese <sr@denx.de>
+Date:	Wed Oct 31 17:55:58 2007 +0100
+
+    ppc4xx: Rework 4xx cache support
+
+    New cache handling functions added and all existing functions
+    moved from start.S into seperate cache.S.
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 06713773da4ac3d390c63d82641eb553224b27c2
+Author: Stefan Roese <sr@denx.de>
+Date:	Tue Oct 23 18:03:12 2007 +0200
+
+    ppc4xx: Remove compiler warning from previous commit
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 6fa397df67c0f269e4528bf181a6e8c88f9723f9
+Author: Stefan Roese <sr@denx.de>
+Date:	Tue Oct 23 14:40:30 2007 +0200
+
+    ppc4xx: Remove temporary TLB entry in POST cache test
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 1338e6a81834099ba19733b69aafd8ef5f098094
+Author: Stefan Roese <sr@denx.de>
+Date:	Tue Oct 23 14:05:08 2007 +0200
+
+    ppc4xx: Change autonegotiation timeout from 4 to 5 seconds
+
+    I lately noticed, that newer 4xx board with GBit support sometimes don't
+    finish link autonegotiation in 4 seconds. Changing this timeout to 5
+    seconds seems fine here.
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 2d83476a4c1c9911d158a3f8a4312d354bc1bdb7
+Author: Stefan Roese <sr@denx.de>
+Date:	Tue Oct 23 14:03:17 2007 +0200
+
+    ppc4xx: Change 4xx_enet & miiphy to use out_be32() and friends
+
+    This patch changes all in32/out32 calls to use the recommended in_be32/
+    out_be32 macros instead.
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 7d47cee2cc57f907380f2c06f5b6c683d03e423a
+Author: Stefan Roese <sr@denx.de>
+Date:	Thu Oct 25 12:24:59 2007 +0200
+
+    ppc4xx: Fix POST ethernet test for Haleakala
+
+    The POST ethernet test needed to be changed to dynamically determine
+    the count of ethernet devices. This code is cloned from the 4xx
+    ethernet driver.
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit f10493c6d77a1e07a6c2ff4d772937a5e7359d6a
+Author: Stefan Roese <sr@denx.de>
+Date:	Tue Oct 23 11:31:05 2007 +0200
+
+    ppc4xx: Correct UART input clock calculation and passing to fdt
+
+    We now use a value in the gd (global data) structure for the UART input
+    frequency, since the PPC4xx_SYS_INFO struct is always rewritten completely
+    in get_sys_info().
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 353f2688b4e0fc7b969bc70a02be4b40bf0dd124
+Author: Stefan Roese <sr@denx.de>
+Date:	Tue Oct 23 10:10:08 2007 +0200
+
+    ppc4xx: Add initial AMCC Haleakala PPC405EXr eval board support
+
+    The Haleakala is nearly identical with the Kilauea eval board. The only
+    difference is that the 405EXr only supports one EMAC and one PCIe
+    interface. This patch adds support for the Haleakala board by using
+    the identical image for Kilauea and Haleakala. The distinction is done
+    by comparing the PVR.
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 9f798766aa85e62eb8fa8c721e148df609b78137
+Author: Eugene O'Brien <eugene.obrien@advantechamt.com>
+Date:	Tue Oct 23 08:29:10 2007 +0200
+
+    ppc4xx: Fixed offset of refresh rate type for Bamboo on-board DDR SDRAM
+
+    This patch also adds a note to the fixed DDR setup for Bamboo NAND booting:
+
+    Note:
+    As found out by Eugene O'Brien <eugene.obrien@advantechamt.com>, the fixed
+    DDR setup has problems (U-Boot crashes randomly upon TFTP), when the DIMM
+    modules are still plugged in. So it is recommended to remove the DIMM
+    modules while using the NAND booting code with the fixed SDRAM setup!
+
+    Signed-off-by: Eugene O'Brien <eugene.obrien@advantechamt.com>
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit afe9fa59cb63b4f9d16bf01c93eb212f25a38c2a
+Author: Stefan Roese <sr@denx.de>
+Date:	Mon Oct 22 16:24:44 2007 +0200
+
+    ppc4xx: Add SNTP support to AMCC Katmai, Kilauea & Makalu boards
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 3248f63ad89cb031491edb7016587fe6e9a238b9
+Author: Stefan Roese <sr@denx.de>
+Date:	Mon Oct 22 16:22:40 2007 +0200
+
+    ppc4xx: Rework of 4xx serial driver (4)
+
+    Change 4xx_uart.c:
+
+    - Use in_8/out_8 macros instead of in8/out8
+    - No need for UART_BASE marco anymore, now really handled via function
+      parameter
+    - serial_init_common() introduced
+    - Further coding style cleanup
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit e61cb8163a66b8a135696ae232e2bead1ce0a049
+Author: Stefan Roese <sr@denx.de>
+Date:	Mon Oct 22 15:45:49 2007 +0200
+
+    ppc4xx: Rework of 4xx serial driver (3)
+
+    Change all linker scripts to reference the changed driver name iop480_uart.o.
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 882ae41274921f9016131806bdeb27e19606f47a
+Author: Stefan Roese <sr@denx.de>
+Date:	Mon Oct 22 15:44:39 2007 +0200
+
+    ppc4xx: Rework of 4xx serial driver (2)
+
+    Change all linker scripts to reference the changed driver name 4xx_uart.o.
+
+    Note: In most cased all these explicit referencing of these object files
+    in the linker scripts is not neccessary. Only for manually embedded
+    environment into the U-Boot image, which is not done is most cases.
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit ad31e40bed042cb670d0036fea96435007afb838
+Author: Stefan Roese <sr@denx.de>
+Date:	Mon Oct 22 15:09:59 2007 +0200
+
+    ppc4xx: Rework of 4xx serial driver (1)
+
+    This patch starts the rework of the PPC4xx serial driver. First we split
+    the file into two seperate files, one 4xx_uart.c with the 405/440 UART
+    handling code and the other one iop480_uart.c with the UART code for the
+    PLX-Tech IOP480 PPC (PPC403 based).
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 764e7417ee5f6e25b1715720e7d7dd3487109385
+Author: Stefan Roese <sr@denx.de>
+Date:	Mon Oct 22 10:30:38 2007 +0200
+
+    ppc4xx: Correct UART input clock calculation and passing to fdt
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 211ea91ac6c225bec7e668a03d0ba7d7310679fa
+Author: Stefan Roese <sr@denx.de>
+Date:	Mon Oct 22 07:34:34 2007 +0200
+
+    ppc4xx: Add initial AMCC Makalu 405EX support
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit fa8aea20456e6f1dba43f46bcc72024dd9499998
+Author: Stefan Roese <sr@denx.de>
+Date:	Mon Oct 22 07:33:52 2007 +0200
+
+    ppc4xx: Add freqUART to CPU speed detection
+
+    This value is needed later for the device tree configuration of
+    the uart clock.
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 837c730b4d7c6b1ddf3d1e247cb4445005d9bf0d
+Author: Stefan Roese <sr@denx.de>
+Date:	Sun Oct 21 14:26:29 2007 +0200
+
+    ppc: Small Kilauea cleanup of config file
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 758c037aeead34b49631b8da3a90b1bba14c0410
+Author: Stefan Roese <sr@denx.de>
+Date:	Sun Oct 21 08:16:12 2007 +0200
+
+    rtc: Add Xicor/Intersil X1205 RTC support
+
+    This patch adds support for the Xicor/Intersil X1205 RTC used on the
+    AMCC Makalu eval board. This driver is basically cloned from the Linux
+    driver version (2.6.23).
+
+    This patch also introduces the Linux bcd.h header for the BCD2BIN/
+    BIN2BCD conversions. In the future some of the other U-Boot RTC driver
+    should be converted to also use this header instead of implementing
+    their own local copy of these functions/macros.
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 087dfdb79b5fd1ab99a26990c62a732c01a8c7f6
+Author: Stefan Roese <sr@denx.de>
+Date:	Sun Oct 21 08:12:41 2007 +0200
+
+    ppc4xx: Consolidate some of the 405 and 440 macros/structs into 4xx
+
+    This patch moves some common 4xx macros and the PPC405_SYS_INFO/
+    PPC440_SYS_INFO structure into the common ppc4xx.h header.
+
+    Lot's of other macros are good candidates to be consolidated this way
+    in the future.
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 770c7af5800f598d22730d1f4b70f16c9b33512e
+Author: Stefan Roese <sr@denx.de>
+Date:	Sun Oct 21 08:05:18 2007 +0200
+
+    ppc4xx: Fix size setup in Kilauea DDR2 init routine
+
+    The size was initilized wrong. Instead of 256MB, the DDR2 controller
+    was setup to 512MB. Now the correct values is used.
+
+    This patch also does a little cleanup and adds a comment here.
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit f6ba9b56607d4b27550301c7c7f6b55b654fd62a
+Author: Eugene O'Brien <eugene.obrien@advantechamt.com>
+Date:	Thu Oct 18 17:29:04 2007 +0200
+
+    ppc4xx: Define CONFIG_BOOKE for all PPC440 based processors
+
+    CONFIG_BOOKE must be defined for PPC440 processors so that the proper SPR
+    number is used to access system registers.
+
+    Signed-off-by: Eugene O'Brien <eugene.obrien@advantechamt.com>
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit c36c68160333ac5fe41ec3db12a728b7075b3912
+Author: Stefan Roese <sr@denx.de>
+Date:	Thu Oct 18 07:42:27 2007 +0200
+
+    ppc4xx: Change inbound PCIe location for endpoint tests on Katmai
+
+    On Yucca & Katmai, the inbound memory map pointed to 0x4.0000.0000, which
+    is the internal SRAM. Since I now ported and tested this endpoint mode
+    on Kilauea successfully to map to 0 (SDRAM), I also changed this for
+    Katmai.
+
+    Yucca will stay at internal SRAM for now. Not sure if somebody relies on
+    this setup.
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 5cb4af4791f61843432155142b6cfac901f66c10
+Author: Stefan Roese <sr@denx.de>
+Date:	Thu Oct 18 07:39:38 2007 +0200
+
+    ppc4xx: Add PCIe endpoint support on Kilauea (405EX)
+
+    This patch adds endpoint support for the AMCC Kilauea eval board. It can
+    be tested by connecting a reworked PCIe cable (only 1x lane singles
+    connected) to another root-complex.
+
+    In this test setup, a 64MB inbound window is configured at BAR0 which maps
+    to 0 on the PLB side. So accessing this BAR0 from the root-complex will
+    access the first 64MB of the SDRAM on the PPC side.
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit d4cb2d17946466740afeb195a57d6cb290bf4cc0
+Author: Stefan Roese <sr@denx.de>
+Date:	Sat Oct 13 16:43:23 2007 +0200
+
+    ppc4xx: Dynamic configuration of 4xx PCIe mode as root or endpoint mode
+
+    This patch adds support for dynamic configuration of PCIe ports for the
+    AMCC PPC4xx boards equipped with PCIe interfaces. These are the PPC440SPe
+    boards Yucca & Katmai and the 405EX board Kilauea.
+
+    This dynamic configuration is done via the "pcie_mode" environement
+    variable. This variable can be set to "EP" or "RP" for endpoint or
+    rootpoint mode. Multiple values can be joined via the ":" delimiter.
+    Here an example:
+
+    pcie_mode=RP:EP:EP
+
+    This way, PCIe port 0 will be configured as rootpoint, PCIe port 1 and 2
+    as endpoint.
+
+    Per default Yucca will be configured as:
+    pcie_mode=RP:EP:EP
+
+    Per default Katmai will be configured as:
+    pcie_mode=RP:RP:REP
+
+    Per default Kilauea will be configured as:
+    pcie_mode=RP:RP
+
+    Signed-off-by: Tirumala R Marri <tmarri@amcc.com>
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit fd671802b67a0ef37a06124fa2ce85f00aa22c6f
+Author: Stefan Roese <sr@denx.de>
+Date:	Thu Oct 11 11:15:59 2007 +0200
+
+    ppc4xx: Enable device tree support (fdt) on Kilauea per default
+
+    This patch enables the fdt support on the AMCC Kilauea eval board.
+    Additionally now EBC ranges fdt fixup is included to support NOR
+    FLASH mapping via the Linux physmap_of driver.
+
+    This Kilauea port now support booting arch/ppc and arch/powerpc
+    Linux kernels. The default environment "net_nfs" is for arch/ppc
+    and "net_nfs_fdt" is for arch/powerpc. In the long run, arch/ppc
+    support will be removed.
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 4994ffd890b9d95d807387a9b7bd8a4803ee406e
+Author: Stefan Roese <sr@denx.de>
+Date:	Thu Oct 11 11:11:45 2007 +0200
+
+    ppc4xx: Add additional debug info to 4xx fdt support
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit db3232ddb058d0ed0bc31f7c5c296748a1afac67
+Author: Stefan Roese <sr@denx.de>
+Date:	Fri Oct 5 21:28:58 2007 +0200
+
+    ppc4xx: Fix small merge problems with CPCI440 and Acadia boards
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 1941cce71b1ae975602854045061e82f94ecd012
+Author: Stefan Roese <sr@denx.de>
+Date:	Fri Oct 5 17:35:10 2007 +0200
+
+    ppc4xx: Fix small merge problem in 4xx_enet.c
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 566806ca1a1bf4d895daaf0b2ba5494abbffebaf
+Author: Stefan Roese <sr@denx.de>
+Date:	Fri Oct 5 17:11:30 2007 +0200
+
+    ppc4xx: Add initial AMCC Kilauea 405EX support
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit dbbd125721aea6645fdb962f36bd41f59e272f9d
+Author: Stefan Roese <sr@denx.de>
+Date:	Fri Oct 5 17:10:59 2007 +0200
+
+    ppc4xx: Add PPC405EX support
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 1d7b874e9c9a7c66f5d8da9ec78a3733765d3e31
+Author: Stefan Roese <sr@denx.de>
+Date:	Fri Oct 5 17:09:36 2007 +0200
+
+    ppc4xx: Cleanup of 4xx PCI and PCIe support (renaming)
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 4f14ed6230b9c109aac9a6fb878497dabd44c2db
+Author: Stefan Roese <sr@denx.de>
+Date:	Fri Oct 5 17:07:50 2007 +0200
+
+    ppc4xx: Add initial fdt support to 4xx (first needed on 405EX)
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit a424a8bb2924b90724b944165d3141f1fa8dfe5b
+Author: Stefan Roese <sr@denx.de>
+Date:	Fri Oct 5 17:04:57 2007 +0200
+
+    POST: Add 405EX support to 4xx UART POST test
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 4f2e92c11f6e2392fc8187829211a5ca7f0c1e12
+Author: Stefan Roese <sr@denx.de>
+Date:	Fri Oct 5 15:10:02 2007 +0200
+
+    DTT: Prepare DS1775 driver for use of different I2C addresses
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 19e93b1e16d267220440d827b920fbad8abfa70f
+Author: Stefan Roese <sr@denx.de>
+Date:	Fri Oct 5 14:23:43 2007 +0200
+
+    ppc4xx: 4xx_pcie: Change PCIe status output to match common style
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit ff68f66bcb0da847845aa2fac11eba6c25938c99
+Author: Stefan Roese <sr@denx.de>
+Date:	Fri Oct 5 09:22:33 2007 +0200
+
+    ppc4xx: 4xx_pcie: Disable debug output as default
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 97923770cb52b64d69eec958a11b2eda8d46e0f7
+Author: Stefan Roese <sr@denx.de>
+Date:	Fri Oct 5 09:18:23 2007 +0200
+
+    ppc4xx: 4xx_pcie: More general cleanup and 405EX PCIe support added
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 4dbee8a90df613eb517aadbecebd70f168913d30
+Author: Stefan Roese <sr@denx.de>
+Date:	Fri Oct 5 07:57:20 2007 +0200
+
+    ppc4xx: 4xx_pcie: Change CFG_PCIE_MEMSIZE to 128MB on Yucca & Katmai
+
+    128MB seems to be the smallest possible value for the memory size
+    for on PCIe port. With this change now the BAR's of the PCIe cards
+    are accessible under U-Boot.
+
+    One big note: This only works for PCIe port 0 & 1. For port 2 this
+    currently doesn't work, since the base address is now 0xc0000000
+    (0xb0000000 + 2 * 0x08000000), and this is already occupied by
+    CFG_PCIE0_CFGBASE. But solving this issue for port 2 would mean
+    to change the base addresses completely and this change would have
+    too much impact right now.
+
+    This patch adds debug output to the 4xx pcie driver too.
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 6d95289281ed2958ebf76d2b55f86bbd88591fd2
+Author: Stefan Roese <sr@denx.de>
+Date:	Wed Oct 3 21:16:32 2007 +0200
+
+    ppc4xx: 4xx_pcie: Fix problem with SDRN access using port number as idx
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 3048bcbf0bad262378c5af68f2bf6778fb7d829a
+Author: Stefan Roese <sr@denx.de>
+Date:	Wed Oct 3 15:01:02 2007 +0200
+
+    ppc4xx: Rename 405gp_pci to 4xx_pci since its used on all 4xx platforms
+
+    These files were introduced with the IBM 405GP but are currently used on all
+    4xx PPC platforms. So the name doesn't match the content anymore. This patch
+    renames the files to 4xx_pci.c/h.
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 94276eb0a7a35b9e8c053d589ae225b0f017a237
+Author: Stefan Roese <sr@denx.de>
+Date:	Wed Oct 3 14:14:58 2007 +0200
+
+    ppc4xx: Add a comment for 405EX PCIe endpoint configuration
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 03d344bb6a5f082ea10ec9d753558ea7dfd1c626
+Author: Stefan Roese <sr@denx.de>
+Date:	Wed Oct 3 10:38:09 2007 +0200
+
+    ppc4xx: Make 440SPe PCIe code more generic to use on different 4xx PPCs (3)
+
+    (3) This patch introduces macros like SDRN_PESDR_DLPSET(port) to access
+	the SDR registers of the PCIe ports. This makes the overall design
+	clearer, since it removed a lot of switch statements which are not
+	needed anymore.
+
+	Also, the functions ppc4xx_init_pcie_rootport() and
+	ppc4xx_init_pcie_entport() are merged into a single function
+	ppc4xx_init_pcie_port(), since most of the code was duplicated.
+	This makes maintainance and porting to other 4xx platforms
+	easier.
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 026f71106871f31d17d0ea0db9a7547ff92934bc
+Author: Stefan Roese <sr@denx.de>
+Date:	Wed Oct 3 07:48:09 2007 +0200
+
+    ppc4xx: Make 440SPe PCIe code more generic to use on different 4xx PPCs (2)
+
+    This patch is the first patch of a series to make the 440SPe PCIe code
+    usable on different 4xx PPC platforms. In preperation for the new 405EX
+    which is also equipped with PCIe interfaces.
+
+    (2) This patch renames the functions from 440spe_ to 4xx_ with a
+	little additional cleanup
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit c7c6da23028f146d912514b95aefa3da7cf37699
+Author: Stefan Roese <sr@denx.de>
+Date:	Wed Oct 3 07:34:10 2007 +0200
+
+    ppc4xx: Make 440SPe PCIe code more generic to use on different 4xx PPCs (1)
+
+    This patch is the first patch of a series to make the 440SPe PCIe code
+    usable on different 4xx PPC platforms. In preperation for the new 405EX
+    which is also equipped with PCIe interfaces.
+
+    (1) This patch renames the files from 440spe_pcie to 4xx_pcie
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
 commit 31548249decf18a6b877a18436b6139dd483fe4a
 Author: Justin Flammia <jflammia@savantav.com>
 Date:	Mon Oct 29 17:40:35 2007 -0400
@@ -2232,6 +4748,39 @@ Date:	Wed Oct 17 15:40:19 2007 +0200
 
     Signed-off-by: Stefan Roese <sr@denx.de>
 
+commit 3c89d75409eb26639d36dfa11d4ee3d8b962dc3c
+Author: Jon Loeliger <jdl@freescale.com>
+Date:	Tue Oct 16 15:27:43 2007 -0500
+
+    Initial mpc8610hpcd Makefile files.
+
+    Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
+    Signed-off-by: Mahesh Jade <mahesh.jade@freescale.com>
+    Signed-off-by: Jason Jin <Jason.jin@freescale.com>
+    Signed-off-by: Jon Loeliger <jdl@freescale.com>
+
+commit 9553df86d3a319c3a1a7cde7e4edd6eeb5aa64c7
+Author: Jon Loeliger <jdl@freescale.com>
+Date:	Tue Oct 16 15:26:51 2007 -0500
+
+    Initial mpc8610hpcd cpu/, README and include/ files.
+
+    Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
+    Signed-off-by: Mahesh Jade <mahesh.jade@freescale.com>
+    Signed-off-by: Jason Jin <Jason.jin@freescale.com>
+    Signed-off-by: Jon Loeliger <jdl@freescale.com>
+
+commit 3dd2db53ceb0dff80f25c2a07f83f29b907b403e
+Author: Jon Loeliger <jdl@freescale.com>
+Date:	Tue Oct 16 13:54:01 2007 -0500
+
+    Initial mpc8610hpcd board files.
+
+    Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
+    Signed-off-by: Mahesh Jade <mahesh.jade@freescale.com>
+    Signed-off-by: Jason Jin <Jason.jin@freescale.com>
+    Signed-off-by: Jon Loeliger <jdl@freescale.com>
+
 commit 7ee6ba1a056e4061ab4cfde30127e332e7957afd
 Author: runet@innovsys.com <runet@innovsys.com>
 Date:	Tue Oct 16 14:50:40 2007 -0500
diff --git a/board/apollon/lowlevel_init.S b/board/apollon/lowlevel_init.S
index f254428c9..8381feae0 100644
--- a/board/apollon/lowlevel_init.S
+++ b/board/apollon/lowlevel_init.S
@@ -31,16 +31,16 @@
 #include <asm/arch/clocks.h>
 #include "mem.h"
 
-#define APOLLON_CS0_BASE        0x00000000
+#define APOLLON_CS0_BASE	0x00000000
 
 #ifdef PRCM_CONFIG_I
-#define SDRC_ACTIM_CTRLA_0_VAL  0x7BA35907
-#define SDRC_ACTIM_CTRLB_0_VAL  0x00000013
-#define SDRC_RFR_CTRL_0_VAL     0x00044C01
+#define SDRC_ACTIM_CTRLA_0_VAL	0x7BA35907
+#define SDRC_ACTIM_CTRLB_0_VAL	0x00000013
+#define SDRC_RFR_CTRL_0_VAL	0x00044C01
 #elif defined(PRCM_CONFIG_II)
-#define SDRC_ACTIM_CTRLA_0_VAL  0x4A59B485
-#define SDRC_ACTIM_CTRLB_0_VAL  0x0000000C
-#define SDRC_RFR_CTRL_0_VAL     0x00030001
+#define SDRC_ACTIM_CTRLA_0_VAL	0x4A59B485
+#define SDRC_ACTIM_CTRLB_0_VAL	0x0000000C
+#define SDRC_RFR_CTRL_0_VAL	0x00030001
 #endif
 
 #define SDRAM_BASE_ADDRESS	0x80008000
@@ -66,100 +66,100 @@ flash_setup:
 	ldr	r1, =WD_UNLOCK2
 	str	r1, [r0, #WSPR]
 
-        /* Pin muxing for SDRC */
-        mov     r1, #0x00
-        ldr     r0, =0x480000A1         /* ball C12, mode 0 */
-        strb    r1, [r0]
+	/* Pin muxing for SDRC */
+	mov	r1, #0x00
+	ldr	r0, =0x480000A1		/* ball C12, mode 0 */
+	strb	r1, [r0]
 
-        ldr     r0, =0x48000032         /* ball D11, mode 0 */
-        strb    r1, [r0]
+	ldr	r0, =0x48000032		/* ball D11, mode 0 */
+	strb	r1, [r0]
 
-        ldr     r0, =0x480000A3         /* ball B13, mode 0 */
-        strb    r1, [r0]
+	ldr	r0, =0x480000A3		/* ball B13, mode 0 */
+	strb	r1, [r0]
 
-        /* SDRC setting */
-        ldr     r0, =OMAP2420_SDRC_BASE
-        ldr     r1, =0x00000010
-        str     r1, [r0, #0x10]
+	/* SDRC setting */
+	ldr	r0, =OMAP2420_SDRC_BASE
+	ldr	r1, =0x00000010
+	str	r1, [r0, #0x10]
 
-        ldr     r1, =0x00000100
-        str     r1, [r0, #0x44]
+	ldr	r1, =0x00000100
+	str	r1, [r0, #0x44]
 
-        /* SDRC CS0 configuration */
-        ldr     r1, =0x00d04011
-        str     r1, [r0, #0x80]
+	/* SDRC CS0 configuration */
+	ldr	r1, =0x00d04011
+	str	r1, [r0, #0x80]
 
-        ldr     r1, =SDRC_ACTIM_CTRLA_0_VAL
-        str     r1, [r0, #0x9C]
+	ldr	r1, =SDRC_ACTIM_CTRLA_0_VAL
+	str	r1, [r0, #0x9C]
 
-        ldr     r1, =SDRC_ACTIM_CTRLB_0_VAL
-        str     r1, [r0, #0xA0]
+	ldr	r1, =SDRC_ACTIM_CTRLB_0_VAL
+	str	r1, [r0, #0xA0]
 
-        ldr     r1, =SDRC_RFR_CTRL_0_VAL
-        str     r1, [r0, #0xA4]
+	ldr	r1, =SDRC_RFR_CTRL_0_VAL
+	str	r1, [r0, #0xA4]
 
-        ldr     r1, =0x00000041
-        str     r1, [r0, #0x70]
+	ldr	r1, =0x00000041
+	str	r1, [r0, #0x70]
 
-        /* Manual command sequence */
-        ldr     r1, =0x00000007
-        str     r1, [r0, #0xA8]
+	/* Manual command sequence */
+	ldr	r1, =0x00000007
+	str	r1, [r0, #0xA8]
 
-        ldr     r1, =0x00000000
-        str     r1, [r0, #0xA8]
+	ldr	r1, =0x00000000
+	str	r1, [r0, #0xA8]
 
-        ldr     r1, =0x00000001
-        str     r1, [r0, #0xA8]
+	ldr	r1, =0x00000001
+	str	r1, [r0, #0xA8]
 
-        ldr     r1, =0x00000002
-        str     r1, [r0, #0xA8]
-        str     r1, [r0, #0xA8]
+	ldr	r1, =0x00000002
+	str	r1, [r0, #0xA8]
+	str	r1, [r0, #0xA8]
 
-        /*
-         * CS0 SDRC Mode register
-         *   Burst length = 4 - DDR memory
-         *   Serial mode
-         *   CAS latency = 3
-         */
-        ldr     r1, =0x00000032
-        str     r1, [r0, #0x84]
+	/*
+	 * CS0 SDRC Mode register
+	 *   Burst length = 4 - DDR memory
+	 *   Serial mode
+	 *   CAS latency = 3
+	 */
+	ldr	r1, =0x00000032
+	str	r1, [r0, #0x84]
 
-        /* Note: You MUST set EMR values */
-        /* EMR1 & EMR2 */
-        ldr     r1, =0x00000000
-        str     r1, [r0, #0x88]
-        str     r1, [r0, #0x8C]
+	/* Note: You MUST set EMR values */
+	/* EMR1 & EMR2 */
+	ldr	r1, =0x00000000
+	str	r1, [r0, #0x88]
+	str	r1, [r0, #0x8C]
 
 #ifdef OLD_SDRC_DLLA_CTRL
-        /* SDRC_DLLA_CTRL */
-        ldr     r1, =0x00007306
-        str     r1, [r0, #0x60]
+	/* SDRC_DLLA_CTRL */
+	ldr	r1, =0x00007306
+	str	r1, [r0, #0x60]
 
-        ldr     r1, =0x00007303
-        str     r1, [r0, #0x60]
+	ldr	r1, =0x00007303
+	str	r1, [r0, #0x60]
 #else
-        /* SDRC_DLLA_CTRL */
-        ldr     r1, =0x00000506
-        str     r1, [r0, #0x60]
+	/* SDRC_DLLA_CTRL */
+	ldr	r1, =0x00000506
+	str	r1, [r0, #0x60]
 
-        ldr     r1, =0x00000503
-        str     r1, [r0, #0x60]
+	ldr	r1, =0x00000503
+	str	r1, [r0, #0x60]
 #endif
 
 #ifdef __BROKEN_FEATURE__
-        /* SDRC_DLLB_CTRL */
-        ldr     r1, =0x00000506
-        str     r1, [r0, #0x68]
+	/* SDRC_DLLB_CTRL */
+	ldr	r1, =0x00000506
+	str	r1, [r0, #0x68]
 
-        ldr     r1, =0x00000503
-        str     r1, [r0, #0x68]
+	ldr	r1, =0x00000503
+	str	r1, [r0, #0x68]
 #endif
 
-        /* little delay after init */
-        mov     r2, #0x1800
+	/* little delay after init */
+	mov	r2, #0x1800
 1:
-        subs    r2, r2, #0x1
-        bne     1b
+	subs	r2, r2, #0x1
+	bne	1b
 
 	/* Setup base address */
 	ldr	r0, =0x00000000		/* NOR address */
@@ -178,21 +178,21 @@ copy_loop:
 #endif
 
 prcm_setup:
-        ldr     r0, =OMAP2420_CM_BASE
-        ldr     r1, [r0, #0x544]        /* CLKSEL2_PLL */
-        bic     r1, r1, #0x03
-        orr     r1, r1, #0x02
-        str     r1, [r0, #0x544]
+	ldr	r0, =OMAP2420_CM_BASE
+	ldr	r1, [r0, #0x544]	/* CLKSEL2_PLL */
+	bic	r1, r1, #0x03
+	orr	r1, r1, #0x02
+	str	r1, [r0, #0x544]
 
-        ldr     r1, [r0, #0x500]
-        bic     r1, r1, #0x03
-        orr     r1, r1, #0x01
-        str     r1, [r0, #0x500]
+	ldr	r1, [r0, #0x500]
+	bic	r1, r1, #0x03
+	orr	r1, r1, #0x01
+	str	r1, [r0, #0x500]
 
-        ldr     r1, [r0, #0x140]
-        bic     r1, r1, #0x1f
-        orr     r1, r1, #0x02
-        str     r1, [r0, #0x140]
+	ldr	r1, [r0, #0x140]
+	bic	r1, r1, #0x1f
+	orr	r1, r1, #0x02
+	str	r1, [r0, #0x140]
 
 #ifdef PRCM_CONFIG_I
 	ldr	r1, =0x000003C3
@@ -204,58 +204,58 @@ prcm_setup:
 	ldr	r1, =0x00000002
 	str	r1, [r0, #0x340]
 
-        ldr     r1, =CM_CLKSEL1_CORE
+	ldr	r1, =CM_CLKSEL1_CORE
 #ifdef PRCM_CONFIG_I
-	ldr     r2, =0x08300C44
+	ldr	r2, =0x08300C44
 #else
-	ldr     r2, =0x04600C26
+	ldr	r2, =0x04600C26
 #endif
-        str     r2, [r1]
+	str	r2, [r1]
 
-        ldr     r0, =OMAP2420_CM_BASE
-        ldr     r1, [r0, #0x084]
-        and     r1, r1, #0x01
-        cmp     r1, #0x01
-        bne     clkvalid
+	ldr	r0, =OMAP2420_CM_BASE
+	ldr	r1, [r0, #0x084]
+	and	r1, r1, #0x01
+	cmp	r1, #0x01
+	bne	clkvalid
 
-        b       .
+	b	.
 
 clkvalid:
-        mov     r1, #0x01
-        str     r1, [r0, #0x080]
+	mov	r1, #0x01
+	str	r1, [r0, #0x080]
 
 waitvalid:
-        ldr     r1, [r0, #0x084]
-        and     r1, r1, #0x01
-        cmp     r1, #0x00
-        bne     waitvalid
+	ldr	r1, [r0, #0x084]
+	and	r1, r1, #0x01
+	cmp	r1, #0x00
+	bne	waitvalid
 
-        ldr     r0, =CM_CLKSEL1_PLL
+	ldr	r0, =CM_CLKSEL1_PLL
 #ifdef PRCM_CONFIG_I
-        ldr     r1, =0x01837100
+	ldr	r1, =0x01837100
 #else
-        ldr     r1, =0x01832100
+	ldr	r1, =0x01832100
 #endif
-        str     r1, [r0]
+	str	r1, [r0]
 
-        ldr     r0, =PRCM_CLKCFG_CTRL
-        mov     r1, #0x01
-        str     r1, [r0]
-        mov     r6, #0x50
+	ldr	r0, =PRCM_CLKCFG_CTRL
+	mov	r1, #0x01
+	str	r1, [r0]
+	mov	r6, #0x50
 loop1:
-        subs    r6, r6, #0x01
-        cmp     r6, #0x01
-        bne     loop1
+	subs	r6, r6, #0x01
+	cmp	r6, #0x01
+	bne	loop1
 
-        ldr     r0, =CM_CLKEN_PLL
+	ldr	r0, =CM_CLKEN_PLL
 	mov	r1, #0x0f
-        str     r1, [r0]
+	str	r1, [r0]
 
-        mov     r6, #0x100
+	mov	r6, #0x100
 loop2:
-        subs    r6, r6, #0x01
-        cmp     r6, #0x01
-        bne     loop2
+	subs	r6, r6, #0x01
+	cmp	r6, #0x01
+	bne	loop2
 
 	ldr	r0, =0x48008200
 	ldr	r1, =0xbfffffff
diff --git a/board/freescale/common/fsl_diu_fb.c b/board/freescale/common/fsl_diu_fb.c
index c1dc48c62..5a8576ea2 100644
--- a/board/freescale/common/fsl_diu_fb.c
+++ b/board/freescale/common/fsl_diu_fb.c
@@ -23,7 +23,6 @@
  * MA 02111-1307 USA
  */
 
-
 #include <common.h>
 #include <i2c.h>
 #include <malloc.h>
@@ -32,14 +31,12 @@
 
 #include "fsl_diu_fb.h"
 
-
 #ifdef DEBUG
 #define DPRINTF(fmt, args...) printf("%s: " fmt,__FUNCTION__,## args)
 #else
 #define DPRINTF(fmt, args...)
 #endif
 
-
 struct fb_videomode {
 	const char *name;	/* optional */
 	unsigned int refresh;		/* optional */
@@ -182,8 +179,6 @@ struct diu_addr {
 
 #define MAX_CURS		32
 
-
-
 static struct fb_info fsl_fb_info;
 static struct diu_addr gamma, cursor;
 static struct diu_ad fsl_diu_fb_ad __attribute__ ((aligned(32)));
@@ -206,7 +201,6 @@ static int fsl_diu_disable_panel(struct fb_info *info);
 static int allocate_buf(struct diu_addr *buf, u32 size, u32 bytes_align);
 static u32 get_busfreq(void);
 
-
 int fsl_diu_init(int xres,
 		 unsigned int pixel_format,
 		 int gamma_fix,
diff --git a/include/configs/apollon.h b/include/configs/apollon.h
index 7727bc3e2..f10120617 100755
--- a/include/configs/apollon.h
+++ b/include/configs/apollon.h
@@ -39,14 +39,14 @@
 
 /* Clock config to target*/
 #define PRCM_CONFIG_I		1
-//#define PRCM_CONFIG_II	1
+/* #define PRCM_CONFIG_II	1 */
 
 /* Boot method */
 /* uncomment if you use NOR boot */
-//#define CFG_NOR_BOOT		1
+/* #define CFG_NOR_BOOT		1 */
 
 /* uncomment if you use NOR on CS3 */
-//#define CFG_USE_NOR		1
+/* #define CFG_USE_NOR		1 */
 
 #ifdef CFG_NOR_BOOT
 #undef CFG_USE_NOR
@@ -111,13 +111,13 @@
 #define	CFG_I2C_SLAVE	1
 #define	CONFIG_DRIVER_OMAP24XX_I2C
 
-/* allow to overwrite serial and ethaddr */ 
+/* allow to overwrite serial and ethaddr */
 #define	CONFIG_ENV_OVERWRITE
 #define	CONFIG_CONS_INDEX	1
 #define	CONFIG_BAUDRATE		115200
 #define	CFG_BAUDRATE_TABLE	{9600, 19200, 38400, 57600, 115200}
 
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ 
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
 #include	<config_cmd_default.h>
 
 #define	CONFIG_CMD_DHCP
@@ -180,8 +180,8 @@
 
 #define	CFG_LOAD_ADDR	(OMAP2420_SDRC_CS0)	/* default load address */
 
-/* The 2420 has 12 GP timers, they can be driven by the SysClk (12/13/19.2) 
- * or by 32KHz clk, or from external sig. This rate is divided by a local 
+/* The 2420 has 12 GP timers, they can be driven by the SysClk (12/13/19.2)
+ * or by 32KHz clk, or from external sig. This rate is divided by a local
  * divisor.
  */
 #define	V_PVT	7	/* use with 12MHz/128 */
@@ -193,7 +193,7 @@
 /*-----------------------------------------------------------------------
  * Stack sizes
  *
- * The stack sizes are set up in start.S using the settings below 
+ * The stack sizes are set up in start.S using the settings below
  */
 #define	CONFIG_STACKSIZE SZ_128K	/* regular stack */
 #ifdef	CONFIG_USE_IRQ
@@ -223,7 +223,7 @@
  */
 # define	CFG_FLASH_CFI	1	/* Flash memory is CFI compliant */
 # define	CFG_FLASH_CFI_DRIVER	1	/* Use drivers/cfi_flash.c */
-//#define CFG_FLASH_USE_BUFFER_WRITE 1 /* Use buffered writes (~10x faster) */
+/* #define CFG_FLASH_USE_BUFFER_WRITE 1 */ /* Use buffered writes (~10x faster) */
 # define	CFG_FLASH_PROTECTION	1	/* Use h/w sector protection*/
 
 #else	/* !CFG_USE_NOR */

From a2df4da31b1a1e41e3e9e1358cfc52b806046ce1 Mon Sep 17 00:00:00 2001
From: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Date: Sun, 9 Dec 2007 11:01:10 +0100
Subject: [PATCH 087/108] Add missing file in gitignore and comments

based on Linux source tree's .gitignore files

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
---
 .gitignore         | 32 ++++++++++++++++++++++++++++++--
 include/.gitignore |  1 +
 2 files changed, 31 insertions(+), 2 deletions(-)

diff --git a/.gitignore b/.gitignore
index 67fed082c..cda275ec7 100644
--- a/.gitignore
+++ b/.gitignore
@@ -1,13 +1,41 @@
+#
+# NOTE! Don't add files that are generated in specific
+# subdirectories here. Add them in the ".gitignore" file
+# in that subdirectory instead.
+#
+# Normal rules
+#
+
+*.rej
 *.orig
 *.a
 *.o
-*.depend
-System.map
+
+#
+# Top-level generic files
+#
+
+/System.map
 /u-boot
 /u-boot.map
 /u-boot.bin
 /u-boot.srec
+
+#
+# Generated files
+#
+
+*.depend
 /LOG
 /errlog
 /reloc_off
 
+# stgit generated dirs
+patches-*
+
+# quilt's files
+patches
+series
+
+# cscope files
+cscope.*
diff --git a/include/.gitignore b/include/.gitignore
index d8fda80d5..ab7d4c76f 100644
--- a/include/.gitignore
+++ b/include/.gitignore
@@ -1,3 +1,4 @@
+/autoconf.mk*
 /asm
 /asm-ppc/arch
 /bmp_logo.h

From 7b74ebe723e576baedf5a8b6240589b19b845a1b Mon Sep 17 00:00:00 2001
From: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Date: Sat, 8 Dec 2007 16:34:08 +0100
Subject: [PATCH 088/108] IXP: Add full baud-rate support for ixp42x, ixp45x
 and ixp46x

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
---
 cpu/ixp/serial.c | 24 ++++++++++--------------
 1 file changed, 10 insertions(+), 14 deletions(-)

diff --git a/cpu/ixp/serial.c b/cpu/ixp/serial.c
index 201595857..df379f380 100644
--- a/cpu/ixp/serial.c
+++ b/cpu/ixp/serial.c
@@ -31,25 +31,22 @@
 #include <common.h>
 #include <asm/arch/ixp425.h>
 
+/*
+ *               14.7456 MHz
+ * Baud Rate = --------------
+ *              16 x Divisor
+ */
+#define SERIAL_CLOCK 921600 
+
 DECLARE_GLOBAL_DATA_PTR;
 
 void serial_setbrg (void)
 {
 	unsigned int quot = 0;
 	int uart = CFG_IXP425_CONSOLE;
-
-	if (gd->baudrate == 1200)
-		quot = 192;
-	else if (gd->baudrate == 9600)
-		quot = 96;
-	else if (gd->baudrate == 19200)
-		quot = 48;
-	else if (gd->baudrate == 38400)
-		quot = 24;
-	else if (gd->baudrate == 57600)
-		quot = 16;
-	else if (gd->baudrate == 115200)
-		quot = 8;
+	
+	if ((gd->baudrate <= SERIAL_CLOCK) && (SERIAL_CLOCK % gd->baudrate == 0))
+		quot = SERIAL_CLOCK / gd->baudrate;
 	else
 		hang ();
 
@@ -65,7 +62,6 @@ void serial_setbrg (void)
 	IER(uart) = IER_UUE;
 }
 
-
 /*
  * Initialise the serial port with the given baudrate. The settings
  * are always 8 data bits, no parity, 1 stop bit, no start bits.

From 23776ff292966a85d811126933830bed48211826 Mon Sep 17 00:00:00 2001
From: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Date: Tue, 11 Dec 2007 10:53:12 +0100
Subject: [PATCH 089/108] ARM: support board-specific ethernet PHY init

Add until the new phylib will be arrived

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
---
 lib_arm/board.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/lib_arm/board.c b/lib_arm/board.c
index 6f35aa06b..7e7a28271 100644
--- a/lib_arm/board.c
+++ b/lib_arm/board.c
@@ -430,6 +430,10 @@ extern void dm644x_eth_set_mac_addr (const u_int8_t *addr);
 	puts ("Net:   ");
 #endif
 	eth_initialize(gd->bd);
+#if defined(CONFIG_RESET_PHY_R)
+	debug ("Reset Ethernet PHY\n");
+	reset_phy();
+#endif
 #endif
 	/* main_loop() can return to retry autoboot, if so just run it again. */
 	for (;;) {

From 23d0baf967fecdaf1804f045f6339337c5607eec Mon Sep 17 00:00:00 2001
From: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Date: Sat, 22 Dec 2007 15:52:58 +0100
Subject: [PATCH 090/108] Allow CONFIG_AUTO_COMPLETE and command history
 CONFIG_CMDLINE_EDITING at the sametime

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
---
 common/main.c | 26 ++++++++++++++++++++++++--
 1 file changed, 24 insertions(+), 2 deletions(-)

diff --git a/common/main.c b/common/main.c
index 379695cc4..4253eac2d 100644
--- a/common/main.c
+++ b/common/main.c
@@ -696,7 +696,7 @@ static void cread_add_str(char *str, int strsize, int insert, unsigned long *num
 	}
 }
 
-static int cread_line(char *buf, unsigned int *len)
+static int cread_line(const char *const prompt, char *buf, unsigned int *len)
 {
 	unsigned long num = 0;
 	unsigned long eol_num = 0;
@@ -818,6 +818,7 @@ static int cread_line(char *buf, unsigned int *len)
 			insert = !insert;
 			break;
 		case CTL_CH('x'):
+		case CTL_CH('u'):
 			BEGINNING_OF_LINE();
 			ERASE_TO_EOL();
 			break;
@@ -867,6 +868,27 @@ static int cread_line(char *buf, unsigned int *len)
 			REFRESH_TO_EOL();
 			continue;
 		}
+#ifdef CONFIG_AUTO_COMPLETE
+		case '\t': {
+			int num2, col;
+
+			/* do not autocomplete when in the middle */
+			if (num < eol_num) {
+				getcmd_cbeep();
+				break;
+			}
+
+			buf[num] = '\0';
+			col = strlen(prompt) + eol_num;
+			num2 = num;
+			if (cmd_auto_complete(prompt, buf, &num2, &col)) {
+				col = num2 - num;
+				num += col;
+				eol_num += col;
+			}
+			break;
+		}
+#endif
 		default:
 			cread_add_char(ichar, insert, &num, &eol_num, buf, *len);
 			break;
@@ -909,7 +931,7 @@ int readline (const char *const prompt)
 
 	puts (prompt);
 
-	rc = cread_line(p, &len);
+	rc = cread_line(prompt, p, &len);
 	return rc < 0 ? rc : len;
 #else
 	char   *p = console_buffer;

From f540c42d9564854b19ce9bbb70affe172529fe70 Mon Sep 17 00:00:00 2001
From: Harald Welte <laforge@openmoko.org>
Date: Wed, 19 Dec 2007 14:09:58 +0100
Subject: [PATCH 091/108] Fix building with CRAMFS but not JFFS2 support

Signed-off-by: Harald Welte <laforge@openmoko.org>
---
 common/cmd_jffs2.c | 9 +++++++++
 fs/cramfs/cramfs.c | 2 +-
 2 files changed, 10 insertions(+), 1 deletion(-)

diff --git a/common/cmd_jffs2.c b/common/cmd_jffs2.c
index efe9eb7be..1b67e73f1 100644
--- a/common/cmd_jffs2.c
+++ b/common/cmd_jffs2.c
@@ -167,10 +167,19 @@ struct list_head devices;
 static struct mtd_device *current_dev = NULL;
 static u8 current_partnum = 0;
 
+#if defined(CONFIG_CMD_CRAMFS)
 extern int cramfs_check (struct part_info *info);
 extern int cramfs_load (char *loadoffset, struct part_info *info, char *filename);
 extern int cramfs_ls (struct part_info *info, char *filename);
 extern int cramfs_info (struct part_info *info);
+#else
+/* defining empty macros for function names is ugly but avoids ifdef clutter
+ * all over the code */
+#define cramfs_check(x)		(0)
+#define cramfs_load(x,y,z)	(-1)
+#define cramfs_ls(x,y)		(0)
+#define cramfs_info(x)		(0)
+#endif
 
 static struct part_info* jffs2_part_info(struct mtd_device *dev, unsigned int part_num);
 
diff --git a/fs/cramfs/cramfs.c b/fs/cramfs/cramfs.c
index 369d1f167..e53c783e5 100644
--- a/fs/cramfs/cramfs.c
+++ b/fs/cramfs/cramfs.c
@@ -27,7 +27,7 @@
 #include <common.h>
 #include <malloc.h>
 
-#if defined(CONFIG_CMD_JFFS2)
+#if defined(CONFIG_CMD_CRAMFS)
 
 #include <asm/byteorder.h>
 #include <linux/stat.h>

From 62d4f4365341576f5a5307b2b205a5aa2e3c6be6 Mon Sep 17 00:00:00 2001
From: Harald Welte <laforge@openmoko.org>
Date: Wed, 19 Dec 2007 14:12:53 +0100
Subject: [PATCH 092/108] Re-introduce the 'nand read.oob' and 'nand write.oob'
 commands that used to exist with the legacy NAND code

Signed-off-by: Harald Welte <laforge@openmoko.org>
---
 common/cmd_nand.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/common/cmd_nand.c b/common/cmd_nand.c
index 1fdd7a67f..b248a2cdb 100644
--- a/common/cmd_nand.c
+++ b/common/cmd_nand.c
@@ -347,6 +347,14 @@ int do_nand(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
 				opts.quiet      = quiet;
 				ret = nand_write_opts(nand, &opts);
 			}
+		} else if (s != NULL && !strcmp(s, ".oob")) {
+			/* read out-of-band data */
+			if (read)
+				ret = nand->read_oob(nand, off, size, &size,
+						     (u_char *) addr);
+			else
+				ret = nand->write_oob(nand, off, size, &size,
+						      (u_char *) addr);
 		} else {
 			if (read)
 				ret = nand_read(nand, off, &size, (u_char *)addr);

From d16471ee05ce7ac5392bc0e9fe3ff4b58a768f33 Mon Sep 17 00:00:00 2001
From: Harald Welte <laforge@openmoko.org>
Date: Wed, 19 Dec 2007 14:14:47 +0100
Subject: [PATCH 093/108] add 'terminal program' functionality

This patch adds a 'cu' like serial terminal command to u-boot
using which you can access other serial ports from the system console.

OpenMoko uses this in their Neo1973 phones to get access to the GSM
Modem and GPS chip from the bootloader.

Signed-off-by: Harald Welte <laforge@openmoko.org>
---
 common/Makefile          |   1 +
 common/cmd_terminal.c    | 102 +++++++++++++++++++++++++++++++++++++++
 include/config_cmd_all.h |   1 +
 3 files changed, 104 insertions(+)
 create mode 100644 common/cmd_terminal.c

diff --git a/common/Makefile b/common/Makefile
index 7be89a41c..fbfa536a3 100644
--- a/common/Makefile
+++ b/common/Makefile
@@ -86,6 +86,7 @@ COBJS-$(CONFIG_CMD_REISER) += cmd_reiser.o
 COBJS-y += cmd_sata.o
 COBJS-$(CONFIG_CMD_SCSI) += cmd_scsi.o
 COBJS-$(CONFIG_CMD_SPI) += cmd_spi.o
+COBJS-$(CONFIG_CMD_TERMINAL) += cmd_terminal.o
 COBJS-$(CONFIG_CMD_UNIVERSE) += cmd_universe.o
 COBJS-$(CONFIG_CMD_USB) += cmd_usb.o
 COBJS-y += cmd_vfd.o
diff --git a/common/cmd_terminal.c b/common/cmd_terminal.c
new file mode 100644
index 000000000..88716072b
--- /dev/null
+++ b/common/cmd_terminal.c
@@ -0,0 +1,102 @@
+/*
+ * (C) Copyright 2007 OpenMoko, Inc.
+ * Written by Harald Welte <laforge@openmoko.org>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Boot support
+ */
+#include <common.h>
+#include <command.h>
+#include <devices.h>
+
+#if defined(CONFIG_CMD_TERMINAL)
+
+int do_terminal(cmd_tbl_t * cmd, int flag, int argc, char *argv[])
+{
+	int i, l;
+	int last_tilde = 0;
+	device_t *dev = NULL;
+
+	if (argc < 1)
+		return -1;
+
+	/* Scan for selected output/input device */
+	for (i = 1; i <= ListNumItems (devlist); i++) {
+		device_t *tmp = ListGetPtrToItem (devlist, i);
+		if (!strcmp(tmp->name, argv[1])) {
+			dev = tmp;
+			break;
+		}
+	}
+	if (!dev)
+		return -1;
+
+	serial_reinit_all();
+	printf("Entering terminal mode for port %s\n", dev->name);
+	puts("Use '~.' to leave the terminal and get back to u-boot\n");
+
+	while (1) {
+		int c;
+
+		/* read from console and display on serial port */
+		if (stdio_devices[0]->tstc()) {
+			c = stdio_devices[0]->getc();
+			if (last_tilde == 1) {
+				if (c == '.') {
+					putc(c);
+					putc('\n');
+					break;
+				} else {
+					last_tilde = 0;
+					/* write the delayed tilde */
+					dev->putc('~');
+					/* fall-through to print current
+					 * character */
+				}
+			}
+			if (c == '~') {
+				last_tilde = 1;
+				puts("[u-boot]");
+				putc(c);
+			}
+			dev->putc(c);
+		}
+
+		/* read from serial port and display on console */
+		if (dev->tstc()) {
+			c = dev->getc();
+			putc(c);
+		}
+	}
+	return 0;
+}
+
+
+/***************************************************/
+
+U_BOOT_CMD(
+	terminal,	3,	1,	do_terminal,
+	"terminal - start terminal emulator\n",
+	""
+);
+
+#endif /* CONFIG_CMD_TERMINAL */
diff --git a/include/config_cmd_all.h b/include/config_cmd_all.h
index d7ef65d5d..f3965efe9 100644
--- a/include/config_cmd_all.h
+++ b/include/config_cmd_all.h
@@ -73,6 +73,7 @@
 #define CONFIG_CMD_SETGETDCR	/* DCR support on 4xx		*/
 #define CONFIG_CMD_SNTP		/* SNTP support			*/
 #define CONFIG_CMD_SPI		/* SPI utility			*/
+#define CONFIG_CMD_TERMINAL	/* built-in Serial Terminal	*/
 #define CONFIG_CMD_UNIVERSE	/* Tundra Universe Support	*/
 #define CONFIG_CMD_USB		/* USB Support			*/
 #define CONFIG_CMD_VFD		/* VFD support (TRAB)		*/

From 1208a2dfde02bedd3c5bda29a606632b8e0be058 Mon Sep 17 00:00:00 2001
From: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
Date: Thu, 27 Dec 2007 16:57:23 +0100
Subject: [PATCH 094/108] serial: Make default_serial_console() a weak function

With this patch it is possible to reimplement default_serial_console()
in board specific code. This will be done in the upcomming PMC440
U-Boot port. This also allows the lwmon board maintainer to
remove the '#if !defined(CONFIG_LWMON) ...' from common/serial.c.

Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
---
 common/serial.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/common/serial.c b/common/serial.c
index b9916e2b5..56010807b 100644
--- a/common/serial.c
+++ b/common/serial.c
@@ -33,7 +33,7 @@ static struct serial_device *serial_devices = NULL;
 static struct serial_device *serial_current = NULL;
 
 #if !defined(CONFIG_LWMON) && !defined(CONFIG_PXA27X)
-struct serial_device *default_serial_console (void)
+struct serial_device *__default_serial_console (void)
 {
 #if defined(CONFIG_8xx_CONS_SMC1) || defined(CONFIG_8xx_CONS_SMC2)
 	return &serial_smc_device;
@@ -64,6 +64,8 @@ struct serial_device *default_serial_console (void)
 #error No default console
 #endif
 }
+
+struct serial_device *default_serial_console(void) __attribute__((weak, alias("__default_serial_console")));
 #endif
 
 int serial_register (struct serial_device *dev)

From 95c6bc7d4a3588b452baca610f8c795a83630477 Mon Sep 17 00:00:00 2001
From: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
Date: Thu, 27 Dec 2007 16:55:17 +0100
Subject: [PATCH 095/108] Add Epson RX8025 RTC support

Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
---
 drivers/rtc/Makefile |   1 +
 drivers/rtc/rx8025.c | 227 +++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 228 insertions(+)
 create mode 100644 drivers/rtc/rx8025.c

diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile
index e5ee61135..8c7f1484b 100644
--- a/drivers/rtc/Makefile
+++ b/drivers/rtc/Makefile
@@ -50,6 +50,7 @@ COBJS-y += mpc8xx.o
 COBJS-y += pcf8563.o
 COBJS-y += s3c24x0_rtc.o
 COBJS-y += rs5c372.o
+COBJS-y += rx8025.o
 COBJS-y += mcfrtc.o
 COBJS-y += x1205.o
 
diff --git a/drivers/rtc/rx8025.c b/drivers/rtc/rx8025.c
new file mode 100644
index 000000000..6c94ae171
--- /dev/null
+++ b/drivers/rtc/rx8025.c
@@ -0,0 +1,227 @@
+/*
+ * (C) Copyright 2007
+ * Matthias Fuchs, esd gmbh, matthias.fuchs@esd-electronics.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Epson RX8025 RTC driver.
+ */
+
+#include <common.h>
+#include <command.h>
+#include <rtc.h>
+#include <i2c.h>
+
+#if defined(CONFIG_RTC_RX8025) && defined(CONFIG_CMD_DATE)
+
+/*---------------------------------------------------------------------*/
+#undef DEBUG_RTC
+
+#ifdef DEBUG_RTC
+#define DEBUGR(fmt,args...) printf(fmt ,##args)
+#else
+#define DEBUGR(fmt,args...)
+#endif
+/*---------------------------------------------------------------------*/
+
+#ifndef CFG_I2C_RTC_ADDR
+# define CFG_I2C_RTC_ADDR	0x32
+#endif
+
+/*
+ * RTC register addresses
+ */
+#define RTC_SEC_REG_ADDR	0x00
+#define RTC_MIN_REG_ADDR	0x01
+#define RTC_HR_REG_ADDR		0x02
+#define RTC_DAY_REG_ADDR	0x03
+#define RTC_DATE_REG_ADDR	0x04
+#define RTC_MON_REG_ADDR	0x05
+#define RTC_YR_REG_ADDR		0x06
+
+#define RTC_CTL1_REG_ADDR	0x0e
+#define RTC_CTL2_REG_ADDR	0x0f
+
+/*
+ * Control register 1 bits
+ */
+#define RTC_CTL1_BIT_2412	0x20
+
+/*
+ * Control register 2 bits
+ */
+#define RTC_CTL2_BIT_PON	0x10
+#define RTC_CTL2_BIT_VDET	0x40
+#define RTC_CTL2_BIT_XST	0x20
+#define RTC_CTL2_BIT_VDSL	0x80
+
+/*
+ * Note: the RX8025 I2C RTC requires register
+ * reads and write to consist of a single bus
+ * cycle. It is not allowed to write the register
+ * address in a first cycle that is terminated by
+ * a STOP condition. The chips needs a 'restart'
+ * sequence (start sequence without a prior stop).
+ * This driver has been written for a 4xx board.
+ * U-Boot's 4xx i2c driver is currently not capable
+ * to generate such cycles to some work arounds
+ * are used.
+ */
+
+/* static uchar rtc_read (uchar reg); */
+#define rtc_read(reg) buf[((reg) + 1) & 0xf]
+
+static void rtc_write (uchar reg, uchar val);
+static uchar bin2bcd (unsigned int n);
+static unsigned bcd2bin (uchar c);
+
+/*
+ * Get the current time from the RTC
+ */
+void rtc_get (struct rtc_time *tmp)
+{
+	uchar sec, min, hour, mday, wday, mon, year, ctl2;
+	uchar buf[16];
+
+	if (i2c_read(CFG_I2C_RTC_ADDR, 0, 0, buf, 16))
+		printf("Error reading from RTC\n");
+
+	sec = rtc_read(RTC_SEC_REG_ADDR);
+	min = rtc_read(RTC_MIN_REG_ADDR);
+	hour = rtc_read(RTC_HR_REG_ADDR);
+	wday = rtc_read(RTC_DAY_REG_ADDR);
+	mday = rtc_read(RTC_DATE_REG_ADDR);
+	mon = rtc_read(RTC_MON_REG_ADDR);
+	year = rtc_read(RTC_YR_REG_ADDR);
+
+	DEBUGR ("Get RTC year: %02x mon: %02x mday: %02x wday: %02x "
+		"hr: %02x min: %02x sec: %02x\n",
+		year, mon, mday, wday, hour, min, sec);
+
+	/* dump status */
+	ctl2 = rtc_read(RTC_CTL2_REG_ADDR);
+	if (ctl2 & RTC_CTL2_BIT_PON)
+		printf("RTC: power-on detected\n");
+
+	if (ctl2 & RTC_CTL2_BIT_VDET)
+		printf("RTC: voltage drop detected\n");
+
+	if (!(ctl2 & RTC_CTL2_BIT_XST))
+		printf("RTC: oscillator stop detected\n");
+
+	tmp->tm_sec  = bcd2bin (sec & 0x7F);
+	tmp->tm_min  = bcd2bin (min & 0x7F);
+	tmp->tm_hour = bcd2bin (hour & 0x3F);
+	tmp->tm_mday = bcd2bin (mday & 0x3F);
+	tmp->tm_mon  = bcd2bin (mon & 0x1F);
+	tmp->tm_year = bcd2bin (year) + ( bcd2bin (year) >= 70 ? 1900 : 2000);
+	tmp->tm_wday = bcd2bin (wday & 0x07);
+	tmp->tm_yday = 0;
+	tmp->tm_isdst= 0;
+
+	DEBUGR ("Get DATE: %4d-%02d-%02d (wday=%d)  TIME: %2d:%02d:%02d\n",
+		tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
+		tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
+}
+
+
+/*
+ * Set the RTC
+ */
+void rtc_set (struct rtc_time *tmp)
+{
+	DEBUGR ("Set DATE: %4d-%02d-%02d (wday=%d)  TIME: %2d:%02d:%02d\n",
+		tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
+		tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
+
+	if (tmp->tm_year < 1970 || tmp->tm_year > 2069)
+		printf("WARNING: year should be between 1970 and 2069!\n");
+
+	rtc_write (RTC_YR_REG_ADDR, bin2bcd (tmp->tm_year % 100));
+	rtc_write (RTC_MON_REG_ADDR, bin2bcd (tmp->tm_mon));
+	rtc_write (RTC_DAY_REG_ADDR, bin2bcd (tmp->tm_wday));
+	rtc_write (RTC_DATE_REG_ADDR, bin2bcd (tmp->tm_mday));
+	rtc_write (RTC_HR_REG_ADDR, bin2bcd (tmp->tm_hour));
+	rtc_write (RTC_MIN_REG_ADDR, bin2bcd (tmp->tm_min));
+	rtc_write (RTC_SEC_REG_ADDR, bin2bcd (tmp->tm_sec));
+
+	rtc_write (RTC_CTL1_REG_ADDR, RTC_CTL1_BIT_2412);
+}
+
+
+/*
+ * Reset the RTC. We setting the date back to 1970-01-01.
+ */
+void rtc_reset (void)
+{
+	struct rtc_time tmp;
+	uchar buf[16];
+	uchar ctl2;
+
+	if (i2c_read(CFG_I2C_RTC_ADDR, 0,    0,   buf, 16))
+		printf("Error reading from RTC\n");
+
+	ctl2 = rtc_read(RTC_CTL2_REG_ADDR);
+	ctl2 &= ~(RTC_CTL2_BIT_PON | RTC_CTL2_BIT_VDET);
+	ctl2 |= RTC_CTL2_BIT_XST | RTC_CTL2_BIT_VDSL;
+	rtc_write (RTC_CTL2_REG_ADDR, ctl2);
+
+	tmp.tm_year = 1970;
+	tmp.tm_mon = 1;
+	tmp.tm_mday= 1;
+	tmp.tm_hour = 0;
+	tmp.tm_min = 0;
+	tmp.tm_sec = 0;
+
+	rtc_set(&tmp);
+
+	printf ( "RTC:   %4d-%02d-%02d %2d:%02d:%02d UTC\n",
+		tmp.tm_year, tmp.tm_mon, tmp.tm_mday,
+		tmp.tm_hour, tmp.tm_min, tmp.tm_sec);
+
+	return;
+}
+
+
+/*
+ * Helper functions
+ */
+static void rtc_write (uchar reg, uchar val)
+{
+	uchar buf[2];
+	buf[0] = reg << 4;
+	buf[1] = val;
+	if (i2c_write(CFG_I2C_RTC_ADDR, 0, 0, buf, 2) != 0)
+		printf("Error writing to RTC\n");
+
+}
+
+static unsigned bcd2bin (uchar n)
+{
+	return ((((n >> 4) & 0x0F) * 10) + (n & 0x0F));
+}
+
+static unsigned char bin2bcd (unsigned int n)
+{
+	return (((n / 10) << 4) | (n % 10));
+}
+
+#endif /* CONFIG_RTC_RX8025 && (CFG_COMMANDS & CFG_CMD_DATE) */

From 0133502e39ff89b67c26cb4015e0e7e8d9571184 Mon Sep 17 00:00:00 2001
From: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
Date: Thu, 27 Dec 2007 17:12:34 +0100
Subject: [PATCH 096/108] Improve configuration of FPGA subsystem

This patch removes the FPGA subsystem configuration through
the CONFIG_FPGA bitmask configuration option.

See README for the new options:

	CONFIG_FPGA,
	CONFIG_FPGA_<vendor>,
	CONFIG_FPGA_<family>

Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
---
 README                      | 21 +++++++++++++++------
 board/gen860t/fpga.c        |  2 +-
 board/gen860t/gen860t.c     |  2 +-
 common/ACEX1K.c             |  4 ++--
 common/altera.c             | 18 +++++++++---------
 common/cmd_fpga.c           |  2 +-
 common/cyclon2.c            |  4 ++--
 common/fpga.c               | 30 +++++++++++-------------------
 common/spartan2.c           |  2 +-
 common/spartan3.c           |  2 +-
 common/virtex2.c            |  2 +-
 common/xilinx.c             | 28 ++++++++++++++--------------
 include/configs/GEN860T.h   |  4 +++-
 include/configs/M54455EVB.h |  4 +++-
 include/configs/alpr.h      |  4 +++-
 include/xilinx.h            |  4 ++--
 16 files changed, 70 insertions(+), 63 deletions(-)

diff --git a/README b/README
index 26f93c21a..9a8b3b903 100644
--- a/README
+++ b/README
@@ -1377,15 +1377,24 @@ The following options need to be configured:
 		SPI configuration items (port pins to use, etc). For
 		an example, see include/configs/sacsng.h.
 
-- FPGA Support: CONFIG_FPGA_COUNT
+- FPGA Support: CONFIG_FPGA
+
+		Enables FPGA subsystem.
+
+		CONFIG_FPGA_<vendor>
+
+		Enables support for specific chip vendors.
+		(ALTERA, XILINX)
+
+		CONFIG_FPGA_<family>
+
+		Enables support for FPGA family.
+		(SPARTAN2, SPARTAN3, VIRTEX2, CYCLONE2, ACEX1K, ACEX)
+
+		CONFIG_FPGA_COUNT
 
 		Specify the number of FPGA devices to support.
 
-		CONFIG_FPGA
-
-		Used to specify the types of FPGA devices.  For example,
-		#define CONFIG_FPGA  CFG_XILINX_VIRTEX2
-
 		CFG_FPGA_PROG_FEEDBACK
 
 		Enable printing of hash marks during FPGA configuration.
diff --git a/board/gen860t/fpga.c b/board/gen860t/fpga.c
index 2ba7e0e42..3816e52ee 100644
--- a/board/gen860t/fpga.c
+++ b/board/gen860t/fpga.c
@@ -34,7 +34,7 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#if (CONFIG_FPGA)
+#if defined(CONFIG_FPGA)
 
 #if 0
 #define GEN860T_FPGA_DEBUG
diff --git a/board/gen860t/gen860t.c b/board/gen860t/gen860t.c
index d448f9fa3..73cc16d47 100644
--- a/board/gen860t/gen860t.c
+++ b/board/gen860t/gen860t.c
@@ -254,7 +254,7 @@ int misc_init_r (void)
 	mii_init ();
 #endif
 
-#if (CONFIG_FPGA)
+#if defined(CONFIG_FPGA)
 	gen860t_init_fpga ();
 #endif
 	return 0;
diff --git a/common/ACEX1K.c b/common/ACEX1K.c
index 2a421e2da..76dc16643 100644
--- a/common/ACEX1K.c
+++ b/common/ACEX1K.c
@@ -28,7 +28,7 @@
 #include <common.h>		/* core U-Boot definitions */
 #include <ACEX1K.h>		/* ACEX device family */
 
-#if (CONFIG_FPGA & (CFG_ALTERA | CFG_ACEX1K))
+#if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ALTERA) && defined(CONFIG_FPGA_ACEX1K)
 
 /* Define FPGA_DEBUG to get debug printf's */
 #ifdef	FPGA_DEBUG
@@ -363,4 +363,4 @@ static int ACEX1K_ps_reloc (Altera_desc * desc, ulong reloc_offset)
 
 }
 
-#endif /* (CONFIG_FPGA & (CFG_ALTERA | CFG_ACEX1K)) */
+#endif /* CONFIG_FPGA && CONFIG_FPGA_ALTERA && CONFIG_FPGA_ACEX1K */
diff --git a/common/altera.c b/common/altera.c
index 06e8a9501..0df7bae01 100644
--- a/common/altera.c
+++ b/common/altera.c
@@ -40,7 +40,7 @@
 #define PRINTF(fmt,args...)
 #endif
 
-#if (CONFIG_FPGA & CFG_FPGA_ALTERA)
+#if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ALTERA)
 
 /* Local Static Functions */
 static int altera_validate (Altera_desc * desc, char *fn);
@@ -56,11 +56,11 @@ int altera_load( Altera_desc *desc, void *buf, size_t bsize )
 		switch (desc->family) {
 		case Altera_ACEX1K:
 		case Altera_CYC2:
-#if (CONFIG_FPGA & CFG_ACEX1K)
+#if defined(CONFIG_FPGA_ACEX1K)
 			PRINTF ("%s: Launching the ACEX1K Loader...\n",
 					__FUNCTION__);
 			ret_val = ACEX1K_load (desc, buf, bsize);
-#elif (CONFIG_FPGA & CFG_CYCLON2)
+#elif defined CONFIG_FPGA_CYCLON2
 			PRINTF ("%s: Launching the CYCLON II Loader...\n",
 					__FUNCTION__);
 			ret_val = CYC2_load (desc, buf, bsize);
@@ -88,7 +88,7 @@ int altera_dump( Altera_desc *desc, void *buf, size_t bsize )
 	} else {
 		switch (desc->family) {
 		case Altera_ACEX1K:
-#if (CONFIG_FPGA & CFG_ACEX)
+#if defined(CONFIG_FPGA_ACEX)
 			PRINTF ("%s: Launching the ACEX1K Reader...\n",
 					__FUNCTION__);
 			ret_val = ACEX1K_dump (desc, buf, bsize);
@@ -156,9 +156,9 @@ int altera_info( Altera_desc *desc )
 			switch (desc->family) {
 			case Altera_ACEX1K:
 			case Altera_CYC2:
-#if (CONFIG_FPGA & CFG_ACEX1K)
+#if defined(CONFIG_FPGA_ACEX1K)
 				ACEX1K_info (desc);
-#elif (CONFIG_FPGA & CFG_CYCLON2)
+#elif defined(CONFIG_FPGA_CYCLON2)
 				CYC2_info (desc);
 #else
 				/* just in case */
@@ -192,7 +192,7 @@ int altera_reloc( Altera_desc *desc, ulong reloc_offset)
 	} else {
 		switch (desc->family) {
 		case Altera_ACEX1K:
-#if (CONFIG_FPGA & CFG_ACEX1K)
+#if defined(CONFIG_FPGA_ACEX1K)
 			ret_val = ACEX1K_reloc (desc, reloc_offset);
 #else
 			printf ("%s: No support for ACEX devices.\n",
@@ -200,7 +200,7 @@ int altera_reloc( Altera_desc *desc, ulong reloc_offset)
 #endif
 			break;
 		case Altera_CYC2:
-#if (CONFIG_FPGA & CFG_CYCLON2)
+#if defined(CONFIG_FPGA_CYCLON2)
 			ret_val = CYC2_reloc (desc, reloc_offset);
 #else
 			printf ("%s: No support for CYCLON II devices.\n",
@@ -249,4 +249,4 @@ static int altera_validate (Altera_desc * desc, char *fn)
 
 /* ------------------------------------------------------------------------- */
 
-#endif /* CONFIG_FPGA & CFG_FPGA_ALTERA */
+#endif /* CONFIG_FPGA & CONFIG_FPGA_ALTERA */
diff --git a/common/cmd_fpga.c b/common/cmd_fpga.c
index 377a692f7..fb24395b5 100644
--- a/common/cmd_fpga.c
+++ b/common/cmd_fpga.c
@@ -58,7 +58,7 @@ static int fpga_get_op (char *opstr);
 /* Convert bitstream data and load into the fpga */
 int fpga_loadbitstream(unsigned long dev, char* fpgadata, size_t size)
 {
-#if (CONFIG_FPGA & CFG_FPGA_XILINX)
+#if defined(CONFIG_FPGA_XILINX)
 	unsigned int length;
 	unsigned char* swapdata;
 	unsigned int swapsize;
diff --git a/common/cyclon2.c b/common/cyclon2.c
index dce13b50d..06f5e8aea 100644
--- a/common/cyclon2.c
+++ b/common/cyclon2.c
@@ -27,7 +27,7 @@
 #include <altera.h>
 #include <ACEX1K.h>		/* ACEX device family */
 
-#if (CONFIG_FPGA & (CFG_ALTERA | CFG_CYCLON2))
+#if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ALTERA) && defined(CONFIG_FPGA_CYCLON2)
 
 /* Define FPGA_DEBUG to get debug printf's */
 #ifdef	FPGA_DEBUG
@@ -302,4 +302,4 @@ static int CYC2_ps_reloc (Altera_desc * desc, ulong reloc_offset)
 	return ret_val;
 }
 
-#endif /* (CONFIG_FPGA & (CFG_ALTERA | CFG_CYCLON2)) */
+#endif /* CONFIG_FPGA && CONFIG_FPGA_ALTERA && CONFIG_FPGA_CYCLON2 */
diff --git a/common/fpga.c b/common/fpga.c
index 2eff239c4..d8b6ae354 100644
--- a/common/fpga.c
+++ b/common/fpga.c
@@ -67,14 +67,11 @@ static int fpga_dev_info( int devnum );
 static void fpga_no_sup( char *fn, char *msg )
 {
 	if ( fn && msg ) {
-		printf( "%s: No support for %s.  CONFIG_FPGA defined as 0x%x.\n",
-				fn, msg, CONFIG_FPGA );
+		printf( "%s: No support for %s.\n", fn, msg);
 	} else if ( msg ) {
-		printf( "No support for %s. CONFIG_FPGA defined as 0x%x.\n",
-				msg, CONFIG_FPGA );
+		printf( "No support for %s.\n", msg);
 	} else {
-		printf( "No FPGA suport!  CONFIG_FPGA defined as 0x%x.\n",
-				CONFIG_FPGA );
+		printf( "No FPGA suport!\n");
 	}
 }
 
@@ -112,11 +109,6 @@ static __attribute__((__const__)) fpga_desc * __attribute__((__const__)) fpga_va
 		printf( "%s: Null buffer.\n", fn );
 		return (fpga_desc * const)NULL;
 	}
-	if ( !bsize ) {
-		printf( "%s: Null buffer size.\n", fn );
-		return (fpga_desc * const)NULL;
-	}
-
 	return desc;
 }
 
@@ -135,7 +127,7 @@ static int fpga_dev_info( int devnum )
 
 		switch ( desc->devtype ) {
 		case fpga_xilinx:
-#if CONFIG_FPGA & CFG_FPGA_XILINX
+#if defined(CONFIG_FPGA_XILINX)
 			printf( "Xilinx Device\nDescriptor @ 0x%p\n", desc );
 			ret_val = xilinx_info( desc->devdesc );
 #else
@@ -143,7 +135,7 @@ static int fpga_dev_info( int devnum )
 #endif
 			break;
 		case fpga_altera:
-#if CONFIG_FPGA & CFG_FPGA_ALTERA
+#if defined(CONFIG_FPGA_ALTERA)
 			printf( "Altera Device\nDescriptor @ 0x%p\n", desc );
 			ret_val = altera_info( desc->devdesc );
 #else
@@ -175,14 +167,14 @@ int fpga_reloc( fpga_type devtype, void *desc, ulong reloc_off )
 
 	switch ( devtype ) {
 	case fpga_xilinx:
-#if CONFIG_FPGA & CFG_FPGA_XILINX
+#if defined(CONFIG_FPGA_XILINX)
 		ret_val = xilinx_reloc( desc, reloc_off );
 #else
 		fpga_no_sup( (char *)__FUNCTION__, "Xilinx devices" );
 #endif
 		break;
 	case fpga_altera:
-#if CONFIG_FPGA & CFG_FPGA_ALTERA
+#if defined(CONFIG_FPGA_ALTERA)
 		ret_val = altera_reloc( desc, reloc_off );
 #else
 		fpga_no_sup( (char *)__FUNCTION__, "Altera devices" );
@@ -268,14 +260,14 @@ int fpga_load( int devnum, void *buf, size_t bsize )
 	if ( desc ) {
 		switch ( desc->devtype ) {
 		case fpga_xilinx:
-#if CONFIG_FPGA & CFG_FPGA_XILINX
+#if defined(CONFIG_FPGA_XILINX)
 			ret_val = xilinx_load( desc->devdesc, buf, bsize );
 #else
 			fpga_no_sup( (char *)__FUNCTION__, "Xilinx devices" );
 #endif
 			break;
 		case fpga_altera:
-#if CONFIG_FPGA & CFG_FPGA_ALTERA
+#if defined(CONFIG_FPGA_ALTERA)
 			ret_val = altera_load( desc->devdesc, buf, bsize );
 #else
 			fpga_no_sup( (char *)__FUNCTION__, "Altera devices" );
@@ -301,14 +293,14 @@ int fpga_dump( int devnum, void *buf, size_t bsize )
 	if ( desc ) {
 		switch ( desc->devtype ) {
 		case fpga_xilinx:
-#if CONFIG_FPGA & CFG_FPGA_XILINX
+#if defined(CONFIG_FPGA_XILINX)
 			ret_val = xilinx_dump( desc->devdesc, buf, bsize );
 #else
 			fpga_no_sup( (char *)__FUNCTION__, "Xilinx devices" );
 #endif
 			break;
 		case fpga_altera:
-#if CONFIG_FPGA & CFG_FPGA_ALTERA
+#if defined(CONFIG_FPGA_ALTERA)
 			ret_val = altera_dump( desc->devdesc, buf, bsize );
 #else
 			fpga_no_sup( (char *)__FUNCTION__, "Altera devices" );
diff --git a/common/spartan2.c b/common/spartan2.c
index 06550b985..457009f85 100644
--- a/common/spartan2.c
+++ b/common/spartan2.c
@@ -25,7 +25,7 @@
 #include <common.h>		/* core U-Boot definitions */
 #include <spartan2.h>		/* Spartan-II device family */
 
-#if (CONFIG_FPGA & (CFG_XILINX | CFG_SPARTAN2))
+#if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_SPARTAN2)
 
 /* Define FPGA_DEBUG to get debug printf's */
 #ifdef	FPGA_DEBUG
diff --git a/common/spartan3.c b/common/spartan3.c
index f7c4f8cf2..17379eb8b 100644
--- a/common/spartan3.c
+++ b/common/spartan3.c
@@ -30,7 +30,7 @@
 #include <common.h>		/* core U-Boot definitions */
 #include <spartan3.h>		/* Spartan-II device family */
 
-#if (CONFIG_FPGA & (CFG_XILINX | CFG_SPARTAN3))
+#if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_SPARTAN3)
 
 /* Define FPGA_DEBUG to get debug printf's */
 #ifdef	FPGA_DEBUG
diff --git a/common/virtex2.c b/common/virtex2.c
index b5dc366aa..1283ff610 100644
--- a/common/virtex2.c
+++ b/common/virtex2.c
@@ -31,7 +31,7 @@
 #include <common.h>
 #include <virtex2.h>
 
-#if (CONFIG_FPGA & (CFG_XILINX | CFG_VIRTEX2))
+#if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_VIRTEX2)
 
 #if 0
 #define FPGA_DEBUG
diff --git a/common/xilinx.c b/common/xilinx.c
index e03e78cb2..c89823868 100644
--- a/common/xilinx.c
+++ b/common/xilinx.c
@@ -32,7 +32,7 @@
 #include <spartan2.h>
 #include <spartan3.h>
 
-#if (CONFIG_FPGA & CFG_FPGA_XILINX)
+#if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_XILINX)
 
 #if 0
 #define FPGA_DEBUG
@@ -59,7 +59,7 @@ int xilinx_load (Xilinx_desc * desc, void *buf, size_t bsize)
 	} else
 		switch (desc->family) {
 		case Xilinx_Spartan2:
-#if (CONFIG_FPGA & CFG_SPARTAN2)
+#if defined(CONFIG_FPGA_SPARTAN2)
 			PRINTF ("%s: Launching the Spartan-II Loader...\n",
 					__FUNCTION__);
 			ret_val = Spartan2_load (desc, buf, bsize);
@@ -69,7 +69,7 @@ int xilinx_load (Xilinx_desc * desc, void *buf, size_t bsize)
 #endif
 			break;
 		case Xilinx_Spartan3:
-#if (CONFIG_FPGA & CFG_SPARTAN3)
+#if defined(CONFIG_FPGA_SPARTAN3)
 			PRINTF ("%s: Launching the Spartan-III Loader...\n",
 					__FUNCTION__);
 			ret_val = Spartan3_load (desc, buf, bsize);
@@ -79,7 +79,7 @@ int xilinx_load (Xilinx_desc * desc, void *buf, size_t bsize)
 #endif
 			break;
 		case Xilinx_Virtex2:
-#if (CONFIG_FPGA & CFG_VIRTEX2)
+#if defined(CONFIG_FPGA_VIRTEX2)
 			PRINTF ("%s: Launching the Virtex-II Loader...\n",
 					__FUNCTION__);
 			ret_val = Virtex2_load (desc, buf, bsize);
@@ -106,7 +106,7 @@ int xilinx_dump (Xilinx_desc * desc, void *buf, size_t bsize)
 	} else
 		switch (desc->family) {
 		case Xilinx_Spartan2:
-#if (CONFIG_FPGA & CFG_SPARTAN2)
+#if defined(CONFIG_FPGA_SPARTAN2)
 			PRINTF ("%s: Launching the Spartan-II Reader...\n",
 					__FUNCTION__);
 			ret_val = Spartan2_dump (desc, buf, bsize);
@@ -116,7 +116,7 @@ int xilinx_dump (Xilinx_desc * desc, void *buf, size_t bsize)
 #endif
 			break;
 		case Xilinx_Spartan3:
-#if (CONFIG_FPGA & CFG_SPARTAN3)
+#if defined(CONFIG_FPGA_SPARTAN3)
 			PRINTF ("%s: Launching the Spartan-III Reader...\n",
 					__FUNCTION__);
 			ret_val = Spartan3_dump (desc, buf, bsize);
@@ -126,7 +126,7 @@ int xilinx_dump (Xilinx_desc * desc, void *buf, size_t bsize)
 #endif
 			break;
 		case Xilinx_Virtex2:
-#if (CONFIG_FPGA & CFG_VIRTEX2)
+#if defined( CONFIG_FPGA_VIRTEX2)
 			PRINTF ("%s: Launching the Virtex-II Reader...\n",
 					__FUNCTION__);
 			ret_val = Virtex2_dump (desc, buf, bsize);
@@ -198,7 +198,7 @@ int xilinx_info (Xilinx_desc * desc)
 			printf ("Device Function Table @ 0x%p\n", desc->iface_fns);
 			switch (desc->family) {
 			case Xilinx_Spartan2:
-#if (CONFIG_FPGA & CFG_SPARTAN2)
+#if defined(CONFIG_FPGA_SPARTAN2)
 				Spartan2_info (desc);
 #else
 				/* just in case */
@@ -207,7 +207,7 @@ int xilinx_info (Xilinx_desc * desc)
 #endif
 				break;
 			case Xilinx_Spartan3:
-#if (CONFIG_FPGA & CFG_SPARTAN3)
+#if defined(CONFIG_FPGA_SPARTAN3)
 				Spartan3_info (desc);
 #else
 				/* just in case */
@@ -216,7 +216,7 @@ int xilinx_info (Xilinx_desc * desc)
 #endif
 				break;
 			case Xilinx_Virtex2:
-#if (CONFIG_FPGA & CFG_VIRTEX2)
+#if defined(CONFIG_FPGA_VIRTEX2)
 				Virtex2_info (desc);
 #else
 				/* just in case */
@@ -249,7 +249,7 @@ int xilinx_reloc (Xilinx_desc * desc, ulong reloc_offset)
 	} else
 		switch (desc->family) {
 		case Xilinx_Spartan2:
-#if (CONFIG_FPGA & CFG_SPARTAN2)
+#if defined(CONFIG_FPGA_SPARTAN2)
 			ret_val = Spartan2_reloc (desc, reloc_offset);
 #else
 			printf ("%s: No support for Spartan-II devices.\n",
@@ -257,7 +257,7 @@ int xilinx_reloc (Xilinx_desc * desc, ulong reloc_offset)
 #endif
 			break;
 		case Xilinx_Spartan3:
-#if (CONFIG_FPGA & CFG_SPARTAN3)
+#if defined(CONFIG_FPGA_SPARTAN3)
 			ret_val = Spartan3_reloc (desc, reloc_offset);
 #else
 			printf ("%s: No support for Spartan-III devices.\n",
@@ -265,7 +265,7 @@ int xilinx_reloc (Xilinx_desc * desc, ulong reloc_offset)
 #endif
 			break;
 		case Xilinx_Virtex2:
-#if (CONFIG_FPGA & CFG_VIRTEX2)
+#if defined(CONFIG_FPGA_VIRTEX2)
 			ret_val = Virtex2_reloc (desc, reloc_offset);
 #else
 			printf ("%s: No support for Virtex-II devices.\n",
@@ -308,4 +308,4 @@ static int xilinx_validate (Xilinx_desc * desc, char *fn)
 	return ret_val;
 }
 
-#endif							/* CONFIG_FPGA & CFG_FPGA_XILINX */
+#endif	/* CONFIG_FPGA && CONFIG_FPGA_XILINX */
diff --git a/include/configs/GEN860T.h b/include/configs/GEN860T.h
index bfbf3a839..3eb3131d4 100644
--- a/include/configs/GEN860T.h
+++ b/include/configs/GEN860T.h
@@ -273,7 +273,9 @@
  * Virtex2 FPGA configuration support
  */
 #define CONFIG_FPGA_COUNT		1
-#define CONFIG_FPGA				CFG_XILINX_VIRTEX2
+#define CONFIG_FPGA
+#define CONFIG_FPGA_XILINX
+#define CONFIG_FPGA_VIRTEX2
 #define CFG_FPGA_PROG_FEEDBACK
 
 
diff --git a/include/configs/M54455EVB.h b/include/configs/M54455EVB.h
index db309584b..35637f92c 100644
--- a/include/configs/M54455EVB.h
+++ b/include/configs/M54455EVB.h
@@ -192,7 +192,9 @@
 
 /* FPGA - Spartan 2 */
 /* experiment
-#define CONFIG_FPGA		CFG_SPARTAN3
+#define CONFIG_FPGA
+#define CONFIG_FPGA_XILINX
+#define CONFIG_FPGA_SPARTAN3
 #define CONFIG_FPGA_COUNT	1
 #define CFG_FPGA_PROG_FEEDBACK
 #define CFG_FPGA_CHECK_CTRLC
diff --git a/include/configs/alpr.h b/include/configs/alpr.h
index aff9823d5..cfe08c856 100644
--- a/include/configs/alpr.h
+++ b/include/configs/alpr.h
@@ -296,7 +296,9 @@
 /*-----------------------------------------------------------------------
  * FPGA stuff
  *-----------------------------------------------------------------------*/
-#define CONFIG_FPGA             CFG_ALTERA_CYCLON2
+#define CONFIG_FPGA
+#define CONFIG_FPGA_ALTERA
+#define CONFIG_FPGA_CYCLON2
 #define CFG_FPGA_CHECK_CTRLC
 #define CFG_FPGA_PROG_FEEDBACK
 #define CONFIG_FPGA_COUNT       1		/* Ich habe 2 ... aber in
diff --git a/include/xilinx.h b/include/xilinx.h
index 3704e1d93..95ebe3d92 100644
--- a/include/xilinx.h
+++ b/include/xilinx.h
@@ -31,11 +31,11 @@
  *********************************************************************/
 #define CFG_SPARTAN2 			CFG_FPGA_DEV( 0x1 )
 #define CFG_VIRTEX_E 			CFG_FPGA_DEV( 0x2 )
-#define CFG_VIRTEX2	 			CFG_FPGA_DEV( 0x4 )
+#define CFG_VIRTEX2			CFG_FPGA_DEV( 0x4 )
 #define CFG_SPARTAN3 			CFG_FPGA_DEV( 0x8 )
 #define CFG_XILINX_SPARTAN2 	(CFG_FPGA_XILINX | CFG_SPARTAN2)
 #define CFG_XILINX_VIRTEX_E 	(CFG_FPGA_XILINX | CFG_VIRTEX_E)
-#define CFG_XILINX_VIRTEX2	 	(CFG_FPGA_XILINX | CFG_VIRTEX2)
+#define CFG_XILINX_VIRTEX2	(CFG_FPGA_XILINX | CFG_VIRTEX2)
 #define CFG_XILINX_SPARTAN3 	(CFG_FPGA_XILINX | CFG_SPARTAN3)
 /* XXX - Add new models here */
 

From 21d39d598c4e74d4e7761608c79dba2715d40a4c Mon Sep 17 00:00:00 2001
From: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
Date: Thu, 27 Dec 2007 17:12:43 +0100
Subject: [PATCH 097/108] Add pre and post configuration callbacks for Spartan
 FPGAs

This patch adds a post configuration callback for Spartan2/3 FPGAs.
pre and post configuration callback are now optional and
not called when the function pointer is set to NULL.

Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
---
 common/spartan2.c  | 18 ++++++++++++++++--
 common/spartan3.c  | 18 ++++++++++++++++--
 include/spartan2.h |  1 +
 include/spartan3.h |  1 +
 4 files changed, 34 insertions(+), 4 deletions(-)

diff --git a/common/spartan2.c b/common/spartan2.c
index 457009f85..ef107bcbc 100644
--- a/common/spartan2.c
+++ b/common/spartan2.c
@@ -561,6 +561,13 @@ static int Spartan2_ss_load (Xilinx_desc * desc, void *buf, size_t bsize)
 		}
 		putc ('\n');			/* terminate the dotted line */
 
+		/*
+		 * Run the post configuration function if there is one.
+		 */
+		if (*fn->post) {
+			(*fn->post) (cookie);
+		}
+
 #ifdef CFG_FPGA_PROG_FEEDBACK
 		if (ret_val == FPGA_SUCCESS) {
 			puts ("Done.\n");
@@ -615,8 +622,10 @@ static int Spartan2_ss_reloc (Xilinx_desc * desc, ulong reloc_offset)
 			PRINTF ("%s: Relocating descriptor at 0x%p\n", __FUNCTION__,
 					desc);
 
-			addr = (ulong) (fn->pre) + reloc_offset;
-			fn_r->pre = (Xilinx_pre_fn) addr;
+			if (fn->pre) {
+				addr = (ulong) (fn->pre) + reloc_offset;
+				fn_r->pre = (Xilinx_pre_fn) addr;
+			}
 
 			addr = (ulong) (fn->pgm) + reloc_offset;
 			fn_r->pgm = (Xilinx_pgm_fn) addr;
@@ -633,6 +642,11 @@ static int Spartan2_ss_reloc (Xilinx_desc * desc, ulong reloc_offset)
 			addr = (ulong) (fn->wr) + reloc_offset;
 			fn_r->wr = (Xilinx_wr_fn) addr;
 
+			if (fn->post) {
+				addr = (ulong) (fn->post) + reloc_offset;
+				fn_r->post = (Xilinx_post_fn) addr;
+			}
+
 			fn_r->relocated = TRUE;
 
 		} else {
diff --git a/common/spartan3.c b/common/spartan3.c
index 17379eb8b..56a172e0b 100644
--- a/common/spartan3.c
+++ b/common/spartan3.c
@@ -566,6 +566,13 @@ static int Spartan3_ss_load (Xilinx_desc * desc, void *buf, size_t bsize)
 		}
 		putc ('\n');			/* terminate the dotted line */
 
+		/*
+		 * Run the post configuration function if there is one.
+		 */
+		if (*fn->post) {
+			(*fn->post) (cookie);
+		}
+
 #ifdef CFG_FPGA_PROG_FEEDBACK
 		if (ret_val == FPGA_SUCCESS) {
 			puts ("Done.\n");
@@ -620,8 +627,10 @@ static int Spartan3_ss_reloc (Xilinx_desc * desc, ulong reloc_offset)
 			PRINTF ("%s: Relocating descriptor at 0x%p\n", __FUNCTION__,
 					desc);
 
-			addr = (ulong) (fn->pre) + reloc_offset;
-			fn_r->pre = (Xilinx_pre_fn) addr;
+			if (fn->pre) {
+				addr = (ulong) (fn->pre) + reloc_offset;
+				fn_r->pre = (Xilinx_pre_fn) addr;
+			}
 
 			addr = (ulong) (fn->pgm) + reloc_offset;
 			fn_r->pgm = (Xilinx_pgm_fn) addr;
@@ -638,6 +647,11 @@ static int Spartan3_ss_reloc (Xilinx_desc * desc, ulong reloc_offset)
 			addr = (ulong) (fn->wr) + reloc_offset;
 			fn_r->wr = (Xilinx_wr_fn) addr;
 
+			if (fn->post) {
+				addr = (ulong) (fn->post) + reloc_offset;
+				fn_r->post = (Xilinx_post_fn) addr;
+			}
+
 			fn_r->relocated = TRUE;
 
 		} else {
diff --git a/include/spartan2.h b/include/spartan2.h
index d2e81e38a..f3cde688f 100644
--- a/include/spartan2.h
+++ b/include/spartan2.h
@@ -58,6 +58,7 @@ typedef struct {
 	Xilinx_init_fn	init;
 	Xilinx_done_fn	done;
 	Xilinx_wr_fn	wr;
+	Xilinx_post_fn	post;
 	int           	relocated;
 } Xilinx_Spartan2_Slave_Serial_fns;
 
diff --git a/include/spartan3.h b/include/spartan3.h
index 65a3f5a4d..529aade65 100644
--- a/include/spartan3.h
+++ b/include/spartan3.h
@@ -58,6 +58,7 @@ typedef struct {
 	Xilinx_init_fn	init;
 	Xilinx_done_fn	done;
 	Xilinx_wr_fn	wr;
+	Xilinx_post_fn	post;
 	int           	relocated;
 } Xilinx_Spartan3_Slave_Serial_fns;
 

From 3bff4ffa33729a42645e328a21e8d16488872958 Mon Sep 17 00:00:00 2001
From: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
Date: Thu, 27 Dec 2007 17:12:56 +0100
Subject: [PATCH 098/108] Add new Xilinx Spartan FPGA types

Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
---
 include/spartan2.h |  4 ++++
 include/spartan3.h | 10 +++++++++-
 2 files changed, 13 insertions(+), 1 deletion(-)

diff --git a/include/spartan2.h b/include/spartan2.h
index f3cde688f..bd159e182 100644
--- a/include/spartan2.h
+++ b/include/spartan2.h
@@ -70,6 +70,7 @@ typedef struct {
 #define XILINX_XC2S50_SIZE  	559232/8
 #define XILINX_XC2S100_SIZE 	781248/8
 #define XILINX_XC2S150_SIZE 	1040128/8
+#define XILINX_XC2S200_SIZE 	1335872/8
 
 /* Spartan-IIE (1.8V) */
 #define XILINX_XC2S50E_SIZE     630048/8
@@ -96,6 +97,9 @@ typedef struct {
 #define XILINX_XC2S150_DESC(iface, fn_table, cookie) \
 { Xilinx_Spartan2, iface, XILINX_XC2S150_SIZE, fn_table, cookie }
 
+#define XILINX_XC2S200_DESC(iface, fn_table, cookie) \
+{ Xilinx_Spartan2, iface, XILINX_XC2S200_SIZE, fn_table, cookie }
+
 #define XILINX_XC2S50E_DESC(iface, fn_table, cookie) \
 { Xilinx_Spartan2, iface, XILINX_XC2S50E_SIZE, fn_table, cookie }
 
diff --git a/include/spartan3.h b/include/spartan3.h
index 529aade65..c203eeb58 100644
--- a/include/spartan3.h
+++ b/include/spartan3.h
@@ -81,9 +81,12 @@ typedef struct {
 #define	XILINX_XC3S1200E_SIZE	3841184/8
 #define	XILINX_XC3S1600E_SIZE	5969696/8
 
+/* Spartan-IIIE (1.2V) */
+#define XILINX_XC3S1200E_SIZE  	3841184/8
+
 /* Descriptor Macros
  *********************************************************************/
-/* Spartan-II devices */
+/* Spartan-III devices */
 #define XILINX_XC3S50_DESC(iface, fn_table, cookie) \
 { Xilinx_Spartan3, iface, XILINX_XC3S50_SIZE, fn_table, cookie }
 
@@ -125,4 +128,9 @@ typedef struct {
 #define XILINX_XC3S1600E_DESC(iface, fn_table, cookie) \
 { Xilinx_Spartan3, iface, XILINX_XC3S1600E_SIZE, fn_table, cookie }
 
+
+/* Spartan-IIIE devices */
+#define XILINX_XC3S1200E_DESC(iface, fn_table, cookie) \
+{ Xilinx_Spartan3, iface, XILINX_XC3S1200E_SIZE, fn_table, cookie }
+
 #endif /* _SPARTAN3_H_ */

From 437fc7327f0611f82937858f2d80e4cd61b40984 Mon Sep 17 00:00:00 2001
From: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
Date: Thu, 27 Dec 2007 17:13:05 +0100
Subject: [PATCH 099/108] Fix MSB check in Xilinx Spartan slave serial mode

Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
---
 common/spartan2.c | 2 +-
 common/spartan3.c | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/common/spartan2.c b/common/spartan2.c
index ef107bcbc..2f1ea2c09 100644
--- a/common/spartan2.c
+++ b/common/spartan2.c
@@ -441,7 +441,7 @@ static int Spartan2_ss_load (Xilinx_desc * desc, void *buf, size_t bsize)
 	int ret_val = FPGA_FAIL;	/* assume the worst */
 	Xilinx_Spartan2_Slave_Serial_fns *fn = desc->iface_fns;
 	int i;
-	char  val;
+	unsigned char val;
 
 	PRINTF ("%s: start with interface functions @ 0x%p\n",
 			__FUNCTION__, fn);
diff --git a/common/spartan3.c b/common/spartan3.c
index 56a172e0b..d329e70cf 100644
--- a/common/spartan3.c
+++ b/common/spartan3.c
@@ -446,7 +446,7 @@ static int Spartan3_ss_load (Xilinx_desc * desc, void *buf, size_t bsize)
 	int ret_val = FPGA_FAIL;	/* assume the worst */
 	Xilinx_Spartan3_Slave_Serial_fns *fn = desc->iface_fns;
 	int i;
-	char  val;
+	unsigned char val;
 
 	PRINTF ("%s: start with interface functions @ 0x%p\n",
 			__FUNCTION__, fn);

From c26acc1a43b31ddca5add42fd0360ff0eee90c80 Mon Sep 17 00:00:00 2001
From: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
Date: Thu, 27 Dec 2007 17:13:11 +0100
Subject: [PATCH 100/108] Remove bit swapping in Xilinx Spartan bitfile loading

This patch removes the unnecessary bit swapping when
booting .bit files with the 'fpga loadb' command.

Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
---
 common/cmd_fpga.c | 37 +------------------------------------
 1 file changed, 1 insertion(+), 36 deletions(-)

diff --git a/common/cmd_fpga.c b/common/cmd_fpga.c
index fb24395b5..f55447ab1 100644
--- a/common/cmd_fpga.c
+++ b/common/cmd_fpga.c
@@ -60,12 +60,9 @@ int fpga_loadbitstream(unsigned long dev, char* fpgadata, size_t size)
 {
 #if defined(CONFIG_FPGA_XILINX)
 	unsigned int length;
-	unsigned char* swapdata;
 	unsigned int swapsize;
 	char buffer[80];
-	unsigned char *ptr;
 	unsigned char *dataptr;
-	unsigned char data;
 	unsigned int i;
 	int rc;
 
@@ -143,39 +140,7 @@ int fpga_loadbitstream(unsigned long dev, char* fpgadata, size_t size)
 	dataptr+=4;
 	printf("  bytes in bitstream = %d\n", swapsize);
 
-	/* check consistency of length obtained */
-	if (swapsize >= size) {
-		printf("%s: Could not find right length of data in bitstream\n",
-			__FUNCTION__);
-		return FPGA_FAIL;
-	}
-
-	/* allocate memory */
-	swapdata = (unsigned char *)malloc(swapsize);
-	if (swapdata == NULL) {
-		printf("%s: Could not allocate %d bytes memory !\n",
-			__FUNCTION__, swapsize);
-		return FPGA_FAIL;
-	}
-
-	/* read data into memory and swap bits */
-	ptr = swapdata;
-	for (i = 0; i < swapsize; i++) {
-		data = 0x00;
-		data |= (*dataptr & 0x01) << 7;
-		data |= (*dataptr & 0x02) << 5;
-		data |= (*dataptr & 0x04) << 3;
-		data |= (*dataptr & 0x08) << 1;
-		data |= (*dataptr & 0x10) >> 1;
-		data |= (*dataptr & 0x20) >> 3;
-		data |= (*dataptr & 0x40) >> 5;
-		data |= (*dataptr & 0x80) >> 7;
-		*ptr++ = data;
-		dataptr++;
-	}
-
-	rc = fpga_load(dev, swapdata, swapsize);
-	free(swapdata);
+	rc = fpga_load(dev, dataptr, swapsize);
 	return rc;
 #else
 	printf("Bitstream support only for Xilinx devices\n");

From 07eb02687f008721974a2fb54cd7fdc28033ab3c Mon Sep 17 00:00:00 2001
From: Wolfgang Denk <wd@denx.de>
Date: Wed, 9 Jan 2008 13:43:38 +0100
Subject: [PATCH 101/108] Coding Style clenaup; update CHANGELOG

Signed-off-by: Wolfgang Denk <wd@denx.de>
---
 CHANGELOG        | 153 +++++++++++++++++++++++++++++++++++++++++++++++
 cpu/ixp/serial.c |   4 +-
 2 files changed, 155 insertions(+), 2 deletions(-)

diff --git a/CHANGELOG b/CHANGELOG
index d682b96f6..548139a32 100644
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -1,3 +1,156 @@
+commit c26acc1a43b31ddca5add42fd0360ff0eee90c80
+Author: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+Date:	Thu Dec 27 17:13:11 2007 +0100
+
+    Remove bit swapping in Xilinx Spartan bitfile loading
+
+    This patch removes the unnecessary bit swapping when
+    booting .bit files with the 'fpga loadb' command.
+
+    Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+
+commit 437fc7327f0611f82937858f2d80e4cd61b40984
+Author: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+Date:	Thu Dec 27 17:13:05 2007 +0100
+
+    Fix MSB check in Xilinx Spartan slave serial mode
+
+    Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+
+commit 3bff4ffa33729a42645e328a21e8d16488872958
+Author: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+Date:	Thu Dec 27 17:12:56 2007 +0100
+
+    Add new Xilinx Spartan FPGA types
+
+    Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+
+commit 21d39d598c4e74d4e7761608c79dba2715d40a4c
+Author: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+Date:	Thu Dec 27 17:12:43 2007 +0100
+
+    Add pre and post configuration callbacks for Spartan FPGAs
+
+    This patch adds a post configuration callback for Spartan2/3 FPGAs.
+    pre and post configuration callback are now optional and
+    not called when the function pointer is set to NULL.
+
+    Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+
+commit 0133502e39ff89b67c26cb4015e0e7e8d9571184
+Author: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+Date:	Thu Dec 27 17:12:34 2007 +0100
+
+    Improve configuration of FPGA subsystem
+
+    This patch removes the FPGA subsystem configuration through
+    the CONFIG_FPGA bitmask configuration option.
+
+    See README for the new options:
+
+	CONFIG_FPGA,
+	CONFIG_FPGA_<vendor>,
+	CONFIG_FPGA_<family>
+
+    Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+
+commit 95c6bc7d4a3588b452baca610f8c795a83630477
+Author: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+Date:	Thu Dec 27 16:55:17 2007 +0100
+
+    Add Epson RX8025 RTC support
+
+    Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+
+commit 1208a2dfde02bedd3c5bda29a606632b8e0be058
+Author: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+Date:	Thu Dec 27 16:57:23 2007 +0100
+
+    serial: Make default_serial_console() a weak function
+
+    With this patch it is possible to reimplement default_serial_console()
+    in board specific code. This will be done in the upcomming PMC440
+    U-Boot port. This also allows the lwmon board maintainer to
+    remove the '#if !defined(CONFIG_LWMON) ...' from common/serial.c.
+
+    Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+
+commit d16471ee05ce7ac5392bc0e9fe3ff4b58a768f33
+Author: Harald Welte <laforge@openmoko.org>
+Date:	Wed Dec 19 14:14:47 2007 +0100
+
+    add 'terminal program' functionality
+
+    This patch adds a 'cu' like serial terminal command to u-boot
+    using which you can access other serial ports from the system console.
+
+    OpenMoko uses this in their Neo1973 phones to get access to the GSM
+    Modem and GPS chip from the bootloader.
+
+    Signed-off-by: Harald Welte <laforge@openmoko.org>
+
+commit 62d4f4365341576f5a5307b2b205a5aa2e3c6be6
+Author: Harald Welte <laforge@openmoko.org>
+Date:	Wed Dec 19 14:12:53 2007 +0100
+
+    Re-introduce the 'nand read.oob' and 'nand write.oob' commands
+    that used to exist with the legacy NAND code
+
+    Signed-off-by: Harald Welte <laforge@openmoko.org>
+
+commit f540c42d9564854b19ce9bbb70affe172529fe70
+Author: Harald Welte <laforge@openmoko.org>
+Date:	Wed Dec 19 14:09:58 2007 +0100
+
+    Fix building with CRAMFS but not JFFS2 support
+
+    Signed-off-by: Harald Welte <laforge@openmoko.org>
+
+commit 23d0baf967fecdaf1804f045f6339337c5607eec
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date:	Sat Dec 22 15:52:58 2007 +0100
+
+    Allow CONFIG_AUTO_COMPLETE and command history CONFIG_CMDLINE_EDITING at the sametime
+
+    Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+    Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+
+commit 23776ff292966a85d811126933830bed48211826
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date:	Tue Dec 11 10:53:12 2007 +0100
+
+    ARM: support board-specific ethernet PHY init
+
+    Add until the new phylib will be arrived
+
+    Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+
+commit 7b74ebe723e576baedf5a8b6240589b19b845a1b
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date:	Sat Dec 8 16:34:08 2007 +0100
+
+    IXP: Add full baud-rate support for ixp42x, ixp45x and ixp46x
+
+    Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+
+commit a2df4da31b1a1e41e3e9e1358cfc52b806046ce1
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date:	Sun Dec 9 11:01:10 2007 +0100
+
+    Add missing file in gitignore and comments
+
+    based on Linux source tree's .gitignore files
+
+    Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+
+commit 435dc8fcdb3bc61d3d490773a8f369f98a20c868
+Author: Wolfgang Denk <wd@denx.de>
+Date:	Wed Jan 9 11:36:21 2008 +0100
+
+    Coding Style cleanup, update CHANGELOG
+
+    Signed-off-by: Wolfgang Denk <wd@denx.de>
+
 commit b2e2142c500c48a57f18f9dd30e66c13caea0971
 Author: Stefan Roese <sr@denx.de>
 Date:	Wed Jan 9 10:38:58 2008 +0100
diff --git a/cpu/ixp/serial.c b/cpu/ixp/serial.c
index df379f380..cf520b699 100644
--- a/cpu/ixp/serial.c
+++ b/cpu/ixp/serial.c
@@ -36,7 +36,7 @@
  * Baud Rate = --------------
  *              16 x Divisor
  */
-#define SERIAL_CLOCK 921600 
+#define SERIAL_CLOCK 921600
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -44,7 +44,7 @@ void serial_setbrg (void)
 {
 	unsigned int quot = 0;
 	int uart = CFG_IXP425_CONSOLE;
-	
+
 	if ((gd->baudrate <= SERIAL_CLOCK) && (SERIAL_CLOCK % gd->baudrate == 0))
 		quot = SERIAL_CLOCK / gd->baudrate;
 	else

From 6a5e1d75bf106fa157e9ce68bcaf4b13e8a1d214 Mon Sep 17 00:00:00 2001
From: Guennadi Liakhovetski <lg@denx.de>
Date: Tue, 20 Nov 2007 13:14:20 +0100
Subject: [PATCH 102/108] Fix endianness conversions in rtl8169 driver

It is unclear on what platforms this driver has been tested, since
noone up to now defines CONFIG_RTL8169 in the board configuration
header. Now it has been fixed for a big-endian mpc8241 based
linkstation platform. This patch presents the necessary endianness
conversion fixes.

Signed-off-by: Guennadi Liakhovetski <lg@denx.de>
---
 drivers/net/rtl8169.c | 100 +++++++++++++++++++-----------------------
 1 file changed, 45 insertions(+), 55 deletions(-)

diff --git a/drivers/net/rtl8169.c b/drivers/net/rtl8169.c
index 63ea2cca9..1d7f31cea 100644
--- a/drivers/net/rtl8169.c
+++ b/drivers/net/rtl8169.c
@@ -48,7 +48,10 @@
 *
 *    Indent Options: indent -kr -i8
 ***************************************************************************/
-
+/*
+ * 26 August 2006 Mihai Georgian <u-boot@linuxnotincluded.org.uk>
+ * Modified to use le32_to_cpu and cpu_to_le32 properly
+ */
 #include <common.h>
 #include <malloc.h>
 #include <net.h>
@@ -68,12 +71,7 @@
 static u32 ioaddr;
 
 /* Condensed operations for readability. */
-#define virt_to_le32desc(addr)	cpu_to_le32(virt_to_bus(addr))
-#define le32desc_to_virt(addr)	bus_to_virt(le32_to_cpu(addr))
-
 #define currticks()	get_timer(0)
-#define bus_to_phys(a)	pci_mem_to_phys((pci_dev_t)dev->priv, a)
-#define phys_to_bus(a)	pci_phys_to_mem((pci_dev_t)dev->priv, a)
 
 /* media options */
 #define MAX_UNITS 8
@@ -102,7 +100,7 @@ static int media[MAX_UNITS] = { -1, -1, -1, -1, -1, -1, -1, -1 };
 #define RTL_MIN_IO_SIZE 0x80
 #define TX_TIMEOUT  (6*HZ)
 
-/* write/read MMIO register */
+/* write/read MMIO register. Notice: {read,write}[wl] do the necessary swapping */
 #define RTL_W8(reg, val8)	writeb ((val8), ioaddr + (reg))
 #define RTL_W16(reg, val16)	writew ((val16), ioaddr + (reg))
 #define RTL_W32(reg, val32)	writel ((val32), ioaddr + (reg))
@@ -218,7 +216,7 @@ enum RTL8169_register_content {
 	PHY_Enable_Auto_Nego = 0x1000,
 
 	/* PHY_STAT_REG = 1; */
-	PHY_Auto_Neco_Comp = 0x0020,
+	PHY_Auto_Nego_Comp = 0x0020,
 
 	/* PHY_AUTO_NEGO_REG = 4; */
 	PHY_Cap_10_Half = 0x0020,
@@ -413,23 +411,23 @@ static int rtl_recv(struct eth_device *dev)
 	ioaddr = dev->iobase;
 
 	cur_rx = tpc->cur_rx;
-	if ((tpc->RxDescArray[cur_rx].status & OWNbit) == 0) {
-		if (!(tpc->RxDescArray[cur_rx].status & RxRES)) {
+	if ((le32_to_cpu(tpc->RxDescArray[cur_rx].status) & OWNbit) == 0) {
+		if (!(le32_to_cpu(tpc->RxDescArray[cur_rx].status) & RxRES)) {
 			unsigned char rxdata[RX_BUF_LEN];
-			length = (int) (tpc->RxDescArray[cur_rx].
-						status & 0x00001FFF) - 4;
+			length = (int) (le32_to_cpu(tpc->RxDescArray[cur_rx].
+						status) & 0x00001FFF) - 4;
 
 			memcpy(rxdata, tpc->RxBufferRing[cur_rx], length);
 			NetReceive(rxdata, length);
 
 			if (cur_rx == NUM_RX_DESC - 1)
 				tpc->RxDescArray[cur_rx].status =
-				    (OWNbit | EORbit) + RX_BUF_SIZE;
+					cpu_to_le32((OWNbit | EORbit) + RX_BUF_SIZE);
 			else
 				tpc->RxDescArray[cur_rx].status =
-				    OWNbit + RX_BUF_SIZE;
+					cpu_to_le32(OWNbit + RX_BUF_SIZE);
 			tpc->RxDescArray[cur_rx].buf_addr =
-			    virt_to_bus(tpc->RxBufferRing[cur_rx]);
+				cpu_to_le32(tpc->RxBufferRing[cur_rx]);
 		} else {
 			puts("Error Rx");
 		}
@@ -454,6 +452,7 @@ static int rtl_send(struct eth_device *dev, volatile void *packet, int length)
 	u8 *ptxb;
 	int entry = tpc->cur_tx % NUM_TX_DESC;
 	u32 len = length;
+	int ret;
 
 #ifdef DEBUG_RTL8169_TX
 	int stime = currticks();
@@ -470,34 +469,38 @@ static int rtl_send(struct eth_device *dev, volatile void *packet, int length)
 	while (len < ETH_ZLEN)
 		ptxb[len++] = '\0';
 
-	tpc->TxDescArray[entry].buf_addr = virt_to_bus(ptxb);
+	tpc->TxDescArray[entry].buf_addr = cpu_to_le32(ptxb);
 	if (entry != (NUM_TX_DESC - 1)) {
 		tpc->TxDescArray[entry].status =
-		    (OWNbit | FSbit | LSbit) | ((len > ETH_ZLEN) ?
-						len : ETH_ZLEN);
+			cpu_to_le32((OWNbit | FSbit | LSbit) |
+				    ((len > ETH_ZLEN) ? len : ETH_ZLEN));
 	} else {
 		tpc->TxDescArray[entry].status =
-		    (OWNbit | EORbit | FSbit | LSbit) |
-		    ((len > ETH_ZLEN) ? length : ETH_ZLEN);
+			cpu_to_le32((OWNbit | EORbit | FSbit | LSbit) |
+				    ((len > ETH_ZLEN) ? len : ETH_ZLEN));
 	}
 	RTL_W8(TxPoll, 0x40);	/* set polling bit */
 
 	tpc->cur_tx++;
 	to = currticks() + TX_TIMEOUT;
-	while ((tpc->TxDescArray[entry].status & OWNbit) && (currticks() < to));	/* wait */
+	while ((le32_to_cpu(tpc->TxDescArray[entry].status) & OWNbit)
+				&& (currticks() < to));	/* wait */
 
 	if (currticks() >= to) {
 #ifdef DEBUG_RTL8169_TX
 		puts ("tx timeout/error\n");
 		printf ("%s elapsed time : %d\n", __FUNCTION__, currticks()-stime);
 #endif
-		return 0;
+		ret = 0;
 	} else {
 #ifdef DEBUG_RTL8169_TX
 		puts("tx done\n");
 #endif
-		return length;
+		ret = length;
 	}
+	/* Delay to make net console (nc) work properly */
+	udelay(20);
+	return ret;
 }
 
 static void rtl8169_set_rx_mode(struct eth_device *dev)
@@ -564,8 +567,8 @@ static void rtl8169_hw_start(struct eth_device *dev)
 
 	tpc->cur_rx = 0;
 
-	RTL_W32(TxDescStartAddr, virt_to_le32desc(tpc->TxDescArray));
-	RTL_W32(RxDescStartAddr, virt_to_le32desc(tpc->RxDescArray));
+	RTL_W32(TxDescStartAddr, tpc->TxDescArray);
+	RTL_W32(RxDescStartAddr, tpc->RxDescArray);
 	RTL_W8(Cfg9346, Cfg9346_Lock);
 	udelay(10);
 
@@ -603,13 +606,14 @@ static void rtl8169_init_ring(struct eth_device *dev)
 	for (i = 0; i < NUM_RX_DESC; i++) {
 		if (i == (NUM_RX_DESC - 1))
 			tpc->RxDescArray[i].status =
-			    (OWNbit | EORbit) + RX_BUF_SIZE;
+				cpu_to_le32((OWNbit | EORbit) + RX_BUF_SIZE);
 		else
-			tpc->RxDescArray[i].status = OWNbit + RX_BUF_SIZE;
+			tpc->RxDescArray[i].status =
+				cpu_to_le32(OWNbit + RX_BUF_SIZE);
 
 		tpc->RxBufferRing[i] = &rxb[i * RX_BUF_SIZE];
 		tpc->RxDescArray[i].buf_addr =
-		    virt_to_bus(tpc->RxBufferRing[i]);
+			cpu_to_le32(tpc->RxBufferRing[i]);
 	}
 
 #ifdef DEBUG_RTL8169
@@ -623,8 +627,6 @@ RESET - Finish setting up the ethernet interface
 static void rtl_reset(struct eth_device *dev, bd_t *bis)
 {
 	int i;
-	u8 diff;
-	u32 TxPhyAddr, RxPhyAddr;
 
 #ifdef DEBUG_RTL8169
 	int stime = currticks();
@@ -632,25 +634,14 @@ static void rtl_reset(struct eth_device *dev, bd_t *bis)
 #endif
 
 	tpc->TxDescArrays = tx_ring;
-	if (tpc->TxDescArrays == 0)
-		puts("Allot Error");
 	/* Tx Desscriptor needs 256 bytes alignment; */
-	TxPhyAddr = virt_to_bus(tpc->TxDescArrays);
-	diff = 256 - (TxPhyAddr - ((TxPhyAddr >> 8) << 8));
-	TxPhyAddr += diff;
-	tpc->TxDescArray = (struct TxDesc *) (tpc->TxDescArrays + diff);
+	tpc->TxDescArray = (struct TxDesc *) ((unsigned long)(tpc->TxDescArrays +
+							      255) & ~255);
 
 	tpc->RxDescArrays = rx_ring;
 	/* Rx Desscriptor needs 256 bytes alignment; */
-	RxPhyAddr = virt_to_bus(tpc->RxDescArrays);
-	diff = 256 - (RxPhyAddr - ((RxPhyAddr >> 8) << 8));
-	RxPhyAddr += diff;
-	tpc->RxDescArray = (struct RxDesc *) (tpc->RxDescArrays + diff);
-
-	if (tpc->TxDescArrays == NULL || tpc->RxDescArrays == NULL) {
-		puts("Allocate RxDescArray or TxDescArray failed\n");
-		return;
-	}
+	tpc->RxDescArray = (struct RxDesc *) ((unsigned long)(tpc->RxDescArrays +
+							      255) & ~255);
 
 	rtl8169_init_ring(dev);
 	rtl8169_hw_start(dev);
@@ -733,7 +724,7 @@ static int rtl_init(struct eth_device *dev, bd_t *bis)
 
 	/* Get MAC address.  FIXME: read EEPROM */
 	for (i = 0; i < MAC_ADDR_LEN; i++)
-		dev->enetaddr[i] = RTL_R8(MAC0 + i);
+		bis->bi_enetaddr[i] = dev->enetaddr[i] = RTL_R8(MAC0 + i);
 
 #ifdef DEBUG_RTL8169
 	printf("MAC Address");
@@ -808,7 +799,7 @@ static int rtl_init(struct eth_device *dev, bd_t *bis)
 		/* wait for auto-negotiation process */
 		for (i = 10000; i > 0; i--) {
 			/* check if auto-negotiation complete */
-			if (mdio_read(PHY_STAT_REG) & PHY_Auto_Neco_Comp) {
+			if (mdio_read(PHY_STAT_REG) & PHY_Auto_Nego_Comp) {
 				udelay(100);
 				option = RTL_R8(PHYstatus);
 				if (option & _1000bpsF) {
@@ -818,13 +809,12 @@ static int rtl_init(struct eth_device *dev, bd_t *bis)
 #endif
 				} else {
 #ifdef DEBUG_RTL8169
-					printf
-					    ("%s: %sMbps %s-duplex operation.\n",
-					     dev->name,
-					     (option & _100bps) ? "100" :
-					     "10",
-					     (option & FullDup) ? "Full" :
-					     "Half");
+					printf("%s: %sMbps %s-duplex operation.\n",
+					       dev->name,
+					       (option & _100bps) ? "100" :
+					       "10",
+					       (option & FullDup) ? "Full" :
+					       "Half");
 #endif
 				}
 				break;
@@ -869,7 +859,7 @@ int rtl8169_initialize(bd_t *bis)
 		sprintf (dev->name, "RTL8169#%d", card_number);
 
 		dev->priv = (void *) devno;
-		dev->iobase = (int)bus_to_phys(iobase);
+		dev->iobase = (int)pci_mem_to_phys(devno, iobase);
 
 		dev->init = rtl_reset;
 		dev->halt = rtl_halt;

From d197ffd8172c6fdef38733424640a9a47295d6e9 Mon Sep 17 00:00:00 2001
From: Guennadi Liakhovetski <lg@denx.de>
Date: Thu, 29 Nov 2007 21:15:56 +0100
Subject: [PATCH 103/108] Fix and optimize MII operations on FEC (MPC8xx)
 controllers

This patch fixes several issues at least on a MPC885 based system with two
FEC interfaces used in MII mode.

1. PHY discovery should first read PHY_PHYIDR2 register and only then
   PHY_PHYIDR1 like cpu/mpc8xx/fec.c::mii_discover_phy() does it,
   otherwise the values read are wrong. Also notice, that PHY discovery
   cannot work on MPC88x / MPC87x in setups with both FECs active at all
   in its present form, because for both interfaces the registers from FEC
   1 are used to communicate over MII.

2. Remove code duplication for resetting the FEC by isolating it into a
   separate function.

3. Initialize MII on FEC 1 when communicating over FEC 2 in fec_init().

4. Optimize mii_init() to only reset the FEC 1 controller once.

5. Fix a typo in mii_init() using index i instead of j thus potentially
   leading to unpredictable results.

Signed-off-by: Guennadi Liakhovetski <lg@denx.de>
---
 cpu/mpc8xx/fec.c | 107 +++++++++++++++++++++++------------------------
 1 file changed, 53 insertions(+), 54 deletions(-)

diff --git a/cpu/mpc8xx/fec.c b/cpu/mpc8xx/fec.c
index 08a371581..da473ca0b 100644
--- a/cpu/mpc8xx/fec.c
+++ b/cpu/mpc8xx/fec.c
@@ -143,6 +143,7 @@ static int fec_send(struct eth_device* dev, volatile void *packet, int length);
 static int fec_recv(struct eth_device* dev);
 static int fec_init(struct eth_device* dev, bd_t * bd);
 static void fec_halt(struct eth_device* dev);
+static void __mii_init(void);
 
 int fec_initialize(bd_t *bis)
 {
@@ -539,6 +540,30 @@ static void fec_pin_init(int fecidx)
 	}
 }
 
+static int fec_reset(volatile fec_t *fecp)
+{
+	int i;
+
+	/* Whack a reset.
+	 * A delay is required between a reset of the FEC block and
+	 * initialization of other FEC registers because the reset takes
+	 * some time to complete. If you don't delay, subsequent writes
+	 * to FEC registers might get killed by the reset routine which is
+	 * still in progress.
+	 */
+
+	fecp->fec_ecntrl = FEC_ECNTRL_PINMUX | FEC_ECNTRL_RESET;
+	for (i = 0;
+	     (fecp->fec_ecntrl & FEC_ECNTRL_RESET) && (i < FEC_RESET_DELAY);
+	     ++i) {
+		udelay (1);
+	}
+	if (i == FEC_RESET_DELAY)
+		return -1;
+
+	return 0;
+}
+
 static int fec_init (struct eth_device *dev, bd_t * bd)
 {
 	struct ether_fcc_info_s *efis = dev->priv;
@@ -573,23 +598,17 @@ static int fec_init (struct eth_device *dev, bd_t * bd)
 #endif /* CONFIG_FADS */
 	}
 
-	/* Whack a reset.
-	 * A delay is required between a reset of the FEC block and
-	 * initialization of other FEC registers because the reset takes
-	 * some time to complete. If you don't delay, subsequent writes
-	 * to FEC registers might get killed by the reset routine which is
-	 * still in progress.
+#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
+	/* the MII interface is connected to FEC1
+	 * so for the miiphy_xxx function to work we must
+	 * call mii_init since fec_halt messes the thing up
 	 */
-	fecp->fec_ecntrl = FEC_ECNTRL_PINMUX | FEC_ECNTRL_RESET;
-	for (i = 0;
-	     (fecp->fec_ecntrl & FEC_ECNTRL_RESET) && (i < FEC_RESET_DELAY);
-	     ++i) {
-		udelay (1);
-	}
-	if (i == FEC_RESET_DELAY) {
+	if (efis->ether_index != 0)
+		__mii_init();
+#endif
+
+	if (fec_reset(fecp) < 0)
 		printf ("FEC_RESET_DELAY timeout\n");
-		return 0;
-	}
 
 	/* We use strictly polling mode only
 	 */
@@ -603,7 +622,7 @@ static int fec_init (struct eth_device *dev, bd_t * bd)
 
 	/* Set station address
 	 */
-#define ea eth_get_dev()->enetaddr
+#define ea dev->enetaddr
 	fecp->fec_addr_low = (ea[0] << 24) | (ea[1] << 16) | (ea[2] << 8) | (ea[3]);
 	fecp->fec_addr_high = (ea[4] << 8) | (ea[5]);
 #undef ea
@@ -716,15 +735,8 @@ static int fec_init (struct eth_device *dev, bd_t * bd)
 	} else {
 		efis->actual_phy_addr = efis->phy_addr;
 	}
+
 #if defined(CONFIG_MII) && defined(CONFIG_RMII)
-
-	/* the MII interface is connected to FEC1
-	 * so for the miiphy_xxx function to work we must
-	 * call mii_init since fec_halt messes the thing up
-	 */
-	if (efis->ether_index != 0)
-		mii_init();
-
 	/*
 	 * adapt the RMII speed to the speed of the phy
 	 */
@@ -874,15 +886,14 @@ static int mii_discover_phy(struct eth_device *dev)
 			udelay(10000);	/* wait 10ms */
 		}
 		for (phyno = 0; phyno < 32 && phyaddr < 0; ++phyno) {
-			phytype = mii_send(mk_mii_read(phyno, PHY_PHYIDR1));
+			phytype = mii_send(mk_mii_read(phyno, PHY_PHYIDR2));
 #ifdef ET_DEBUG
 			printf("PHY type 0x%x pass %d type ", phytype, pass);
 #endif
 			if (phytype != 0xffff) {
 				phyaddr = phyno;
-				phytype <<= 16;
 				phytype |= mii_send(mk_mii_read(phyno,
-								PHY_PHYIDR2));
+								PHY_PHYIDR1)) << 16;
 
 #ifdef ET_DEBUG
 				printf("PHY @ 0x%x pass %d type ",phyno,pass);
@@ -929,36 +940,17 @@ static int mii_discover_phy(struct eth_device *dev)
 #if (defined(CONFIG_MII) || defined(CONFIG_CMD_MII)) && !defined(CONFIG_BITBANGMII)
 
 /****************************************************************************
- * mii_init -- Initialize the MII for MII command without ethernet
+ * mii_init -- Initialize the MII via FEC 1 for MII command without ethernet
  * This function is a subset of eth_init
  ****************************************************************************
  */
-void mii_init (void)
+static void __mii_init(void)
 {
 	volatile immap_t *immr = (immap_t *) CFG_IMMR;
 	volatile fec_t *fecp = &(immr->im_cpm.cp_fec);
-	int i, j;
 
-	for (j = 0; j < sizeof(ether_fcc_info) / sizeof(ether_fcc_info[0]); j++) {
-
-	/* Whack a reset.
-	 * A delay is required between a reset of the FEC block and
-	 * initialization of other FEC registers because the reset takes
-	 * some time to complete. If you don't delay, subsequent writes
-	 * to FEC registers might get killed by the reset routine which is
-	 * still in progress.
-	 */
-
-	fecp->fec_ecntrl = FEC_ECNTRL_PINMUX | FEC_ECNTRL_RESET;
-	for (i = 0;
-	     (fecp->fec_ecntrl & FEC_ECNTRL_RESET) && (i < FEC_RESET_DELAY);
-	     ++i) {
-		udelay (1);
-	}
-	if (i == FEC_RESET_DELAY) {
+	if (fec_reset(fecp) < 0)
 		printf ("FEC_RESET_DELAY timeout\n");
-		return;
-	}
 
 	/* We use strictly polling mode only
 	 */
@@ -968,14 +960,21 @@ void mii_init (void)
 	 */
 	fecp->fec_ievent = 0xffc0;
 
-	/* Setup the pin configuration of the FEC(s)
-	*/
-		fec_pin_init(ether_fcc_info[i].ether_index);
-
 	/* Now enable the transmit and receive processing
 	 */
 	fecp->fec_ecntrl = FEC_ECNTRL_PINMUX | FEC_ECNTRL_ETHER_EN;
-	}
+}
+
+void mii_init (void)
+{
+	int i;
+
+	__mii_init();
+
+	/* Setup the pin configuration of the FEC(s)
+	*/
+	for (i = 0; i < sizeof(ether_fcc_info) / sizeof(ether_fcc_info[0]); i++)
+		fec_pin_init(ether_fcc_info[i].ether_index);
 }
 
 /*****************************************************************************

From 43ef1c381f9195504a2488f5cb909227eb97d475 Mon Sep 17 00:00:00 2001
From: Hans-Christian Egtvedt <hcegtvedt@atmel.com>
Date: Fri, 30 Nov 2007 17:29:59 +0100
Subject: [PATCH 104/108] cmd_bmp: Add support for displaying gzip compressed
 bmps

The existing code can show information about a gzip compressed BMP
image, but can't actually display it.

Therefore, move the decompression code out of bmp_info() and use it in
bmp_display() as well in order to display a compressed BMP image.

Also, clean things up a bit and fix a memory leak while we're at it.

[hskinnemoen@atmel.com: a bit of refactoring]
Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
---
 common/cmd_bmp.c | 134 ++++++++++++++++++++++++++++++-----------------
 1 file changed, 85 insertions(+), 49 deletions(-)

diff --git a/common/cmd_bmp.c b/common/cmd_bmp.c
index 907f9a2db..2437e2278 100644
--- a/common/cmd_bmp.c
+++ b/common/cmd_bmp.c
@@ -36,6 +36,62 @@ static int bmp_display (ulong addr, int x, int y);
 
 int gunzip(void *, int, unsigned char *, unsigned long *);
 
+/*
+ * Allocate and decompress a BMP image using gunzip().
+ *
+ * Returns a pointer to the decompressed image data. Must be freed by
+ * the caller after use.
+ *
+ * Returns NULL if decompression failed, or if the decompressed data
+ * didn't contain a valid BMP signature.
+ */
+#ifdef CONFIG_VIDEO_BMP_GZIP
+static bmp_image_t *gunzip_bmp(unsigned long addr, unsigned long *lenp)
+{
+	void *dst;
+	unsigned long len;
+	bmp_image_t *bmp;
+
+	/*
+	 * Decompress bmp image
+	 */
+	len = CFG_VIDEO_LOGO_MAX_SIZE;
+	dst = malloc(CFG_VIDEO_LOGO_MAX_SIZE);
+	if (dst == NULL) {
+		puts("Error: malloc in gunzip failed!\n");
+		return NULL;
+	}
+	if (gunzip(dst, CFG_VIDEO_LOGO_MAX_SIZE, (uchar *)addr, &len) != 0) {
+		free(dst);
+		return NULL;
+	}
+	if (len == CFG_VIDEO_LOGO_MAX_SIZE)
+		puts("Image could be truncated"
+				" (increase CFG_VIDEO_LOGO_MAX_SIZE)!\n");
+
+	bmp = dst;
+
+	/*
+	 * Check for bmp mark 'BM'
+	 */
+	if (!((bmp->header.signature[0] == 'B') &&
+	      (bmp->header.signature[1] == 'M'))) {
+		free(dst);
+		return NULL;
+	}
+
+	puts("Gzipped BMP image detected!\n");
+
+	return bmp;
+}
+#else
+static bmp_image_t *gunzip_bmp(unsigned long addr)
+{
+	return NULL;
+}
+#endif
+
+
 /*
  * Subroutine:  do_bmp
  *
@@ -101,63 +157,24 @@ U_BOOT_CMD(
 static int bmp_info(ulong addr)
 {
 	bmp_image_t *bmp=(bmp_image_t *)addr;
-#ifdef CONFIG_VIDEO_BMP_GZIP
-	unsigned char *dst = NULL;
-	ulong len;
-#endif /* CONFIG_VIDEO_BMP_GZIP */
+	unsigned long len;
 
 	if (!((bmp->header.signature[0]=='B') &&
-	      (bmp->header.signature[1]=='M'))) {
+	      (bmp->header.signature[1]=='M')))
+		bmp = gunzip_bmp(addr, &len);
 
-#ifdef CONFIG_VIDEO_BMP_GZIP
-		/*
-		 * Decompress bmp image
-		 */
-		len = CFG_VIDEO_LOGO_MAX_SIZE;
-		dst = malloc(CFG_VIDEO_LOGO_MAX_SIZE);
-		if (dst == NULL) {
-			printf("Error: malloc in gunzip failed!\n");
-			return(1);
-		}
-		if (gunzip(dst, CFG_VIDEO_LOGO_MAX_SIZE, (uchar *)addr, &len) != 0) {
-			printf("There is no valid bmp file at the given address\n");
-			return(1);
-		}
-		if (len == CFG_VIDEO_LOGO_MAX_SIZE) {
-			printf("Image could be truncated (increase CFG_VIDEO_LOGO_MAX_SIZE)!\n");
-		}
-
-		/*
-		 * Set addr to decompressed image
-		 */
-		bmp = (bmp_image_t *)dst;
-
-		/*
-		 * Check for bmp mark 'BM'
-		 */
-		if (!((bmp->header.signature[0] == 'B') &&
-		      (bmp->header.signature[1] == 'M'))) {
-			printf("There is no valid bmp file at the given address\n");
-			free(dst);
-			return(1);
-		}
-
-		printf("Gzipped BMP image detected!\n");
-#else /* CONFIG_VIDEO_BMP_GZIP */
+	if (bmp == NULL) {
 		printf("There is no valid bmp file at the given address\n");
-		return(1);
-#endif /* CONFIG_VIDEO_BMP_GZIP */
+		return 1;
 	}
+
 	printf("Image size    : %d x %d\n", le32_to_cpu(bmp->header.width),
 	       le32_to_cpu(bmp->header.height));
 	printf("Bits per pixel: %d\n", le16_to_cpu(bmp->header.bit_count));
 	printf("Compression   : %d\n", le32_to_cpu(bmp->header.compression));
 
-#ifdef CONFIG_VIDEO_BMP_GZIP
-	if (dst) {
-		free(dst);
-	}
-#endif /* CONFIG_VIDEO_BMP_GZIP */
+	if ((unsigned long)bmp != addr)
+		free(bmp);
 
 	return(0);
 }
@@ -174,14 +191,33 @@ static int bmp_info(ulong addr)
  */
 static int bmp_display(ulong addr, int x, int y)
 {
+	int ret;
+	bmp_image_t *bmp = (bmp_image_t *)addr;
+	unsigned long len;
+
+	if (!((bmp->header.signature[0]=='B') &&
+	      (bmp->header.signature[1]=='M')))
+		bmp = gunzip_bmp(addr, &len);
+
+	if (!bmp) {
+		printf("There is no valid bmp file at the given address\n");
+		return 1;
+	}
+
 #if defined(CONFIG_LCD)
 	extern int lcd_display_bitmap (ulong, int, int);
 
-	return (lcd_display_bitmap (addr, x, y));
+	ret = lcd_display_bitmap ((unsigned long)bmp, x, y);
 #elif defined(CONFIG_VIDEO)
 	extern int video_display_bitmap (ulong, int, int);
-	return (video_display_bitmap (addr, x, y));
+
+	ret = video_display_bitmap ((unsigned long)bmp, x, y);
 #else
 # error bmp_display() requires CONFIG_LCD or CONFIG_VIDEO
 #endif
+
+	if ((unsigned long)bmp != addr)
+		free(bmp);
+
+	return ret;
 }

From 883e3925d99a8dd69c5b0201cba5b1887f88f95c Mon Sep 17 00:00:00 2001
From: "raptorbrino@aim.com" <raptorbrino@aim.com>
Date: Thu, 13 Dec 2007 21:23:28 -0500
Subject: [PATCH 105/108] Fix build problems under Cygwin

This patch allows u-boot to build without error in a cygwin
environment.  Cygwin does not define __u64 in it's
include/asm/types.h file.  The -idirafter flag in the u-boot
build causes the inclusion of the cygwin types.h file as opposed
to u-bot/include/asm/types.h file which does define __u64.
Subsequently, sha1.c compile fails due to unknown symbol.

Signed-off-by: Brian Miller <raptorbrino@netscape.net>
---
 tools/Makefile | 1 +
 1 file changed, 1 insertion(+)

diff --git a/tools/Makefile b/tools/Makefile
index e8e02801a..21cc09057 100644
--- a/tools/Makefile
+++ b/tools/Makefile
@@ -97,6 +97,7 @@ endif
 #
 ifeq ($(HOSTOS),cygwin)
 SFX = .exe
+HOST_CFLAGS += -ansi
 else
 SFX =
 endif

From 38d299c2db81bd889c601b5dfc12c4e83ef83333 Mon Sep 17 00:00:00 2001
From: Mike Frysinger <vapier@gentoo.org>
Date: Tue, 18 Dec 2007 03:23:25 -0500
Subject: [PATCH 106/108] cleanup easylogo

- make the Makefile not suck
- include proper headers for prototypes
- fix obvious broken handling of strchr() when handling '.' in filenames

Signed-Off-By: Mike Frysinger <vapier@gentoo.org>
---
 tools/easylogo/Makefile   | 10 ++++++++--
 tools/easylogo/easylogo.c | 15 ++++++++++-----
 2 files changed, 18 insertions(+), 7 deletions(-)

diff --git a/tools/easylogo/Makefile b/tools/easylogo/Makefile
index 292344ad0..566b12506 100644
--- a/tools/easylogo/Makefile
+++ b/tools/easylogo/Makefile
@@ -1,2 +1,8 @@
-all:	easylogo.c
-	gcc easylogo.c -o easylogo
+CFLAGS += -Wall
+
+all: easylogo
+
+clean:
+	rm -f easylogo *.o
+
+.PHONY: all clean
diff --git a/tools/easylogo/easylogo.c b/tools/easylogo/easylogo.c
index 9f1d1fff0..59f9ae7d9 100644
--- a/tools/easylogo/easylogo.c
+++ b/tools/easylogo/easylogo.c
@@ -8,6 +8,8 @@
 */
 
 #include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
 
 #pragma pack(1)
 
@@ -41,7 +43,7 @@ typedef struct {
 } yuyv_t ;
 
 typedef struct {
-	unsigned char	*data,
+	void				*data,
 					*palette ;
 	int				width,
 					height,
@@ -352,9 +354,10 @@ int main (int argc, char *argv[])
 	    strcpy (varname, 	argv[2]);
 	else
 	{
-	    int pos = strchr(inputfile, '.');
+	    char *dot = strchr(inputfile, '.');
+	    int pos = dot - inputfile;
 
-	    if (pos >= 0)
+	    if (dot)
 	    {
 		strncpy (varname, inputfile, pos);
 		varname[pos] = 0 ;
@@ -365,13 +368,15 @@ int main (int argc, char *argv[])
 	    strcpy (outputfile, argv[3]);
 	else
 	{
-	    int pos = strchr (varname, '.');
+	    char *dot = strchr (varname, '.');
+	    int pos = dot - varname;
 
-	    if (pos > 0)
+	    if (dot)
 	    {
 		char app[DEF_FILELEN] ;
 
 		strncpy(app, varname, pos);
+		app[pos] = 0;
 		sprintf(outputfile, "%s.h", app);
 	    }
 	}

From fc6414eca55f1fc108fb12fc8cdc43bd8b4463f9 Mon Sep 17 00:00:00 2001
From: Mike Frysinger <vapier@gentoo.org>
Date: Tue, 18 Dec 2007 04:29:55 -0500
Subject: [PATCH 107/108] fix easylogo on big endian dev systems

didnt realize how out of shape easylogo actually was until i tried using it.
this patch does byte swapping as need be on the input tga header since the tga
is in little endian but the host could just as well be big endian.  i didnt
bother using bswap macros or such stuff from system headers as nothing in
POSIX dictates byte swapping functionality.

Signed-Off-By: Mike Frysinger <vapier@gentoo.org>
---
 tools/easylogo/easylogo.c | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)

diff --git a/tools/easylogo/easylogo.c b/tools/easylogo/easylogo.c
index 59f9ae7d9..6f2aaa6b1 100644
--- a/tools/easylogo/easylogo.c
+++ b/tools/easylogo/easylogo.c
@@ -127,6 +127,16 @@ void printlogo_yuyv (unsigned short *data, int w, int h)
     }
 }
 
+static inline unsigned short le16_to_cpu (unsigned short val)
+{
+    union {
+	unsigned char pval[2];
+	unsigned short val;
+    } swapped;
+    swapped.val = val;
+    return (swapped.pval[1] << 8) + swapped.pval[0];
+}
+
 int image_load_tga (image_t *image, char *filename)
 {
     FILE *file ;
@@ -140,6 +150,14 @@ int image_load_tga (image_t *image, char *filename)
 
     fread(&header, sizeof(header), 1, file);
 
+    /* byte swap: tga is little endian, host is ??? */
+    header.ColorMapOrigin = le16_to_cpu (header.ColorMapOrigin);
+    header.ColorMapLenght = le16_to_cpu (header.ColorMapLenght);
+    header.ImageXOrigin = le16_to_cpu (header.ImageXOrigin);
+    header.ImageYOrigin = le16_to_cpu (header.ImageYOrigin);
+    header.ImageWidth = le16_to_cpu (header.ImageWidth);
+    header.ImageHeight = le16_to_cpu (header.ImageHeight);
+
     image->width 	= header.ImageWidth ;
     image->height 	= header.ImageHeight ;
 

From 6007f3251c0967adc13f2ed8be1b924ddc30124d Mon Sep 17 00:00:00 2001
From: Wolfgang Denk <wd@denx.de>
Date: Wed, 9 Jan 2008 15:14:46 +0100
Subject: [PATCH 108/108] Coding Style cleanup, update CHANGELOG

Signed-off-by: Wolfgang Denk <wd@denx.de>
---
 CHANGELOG                 | 108 +++++++
 tools/easylogo/easylogo.c | 611 +++++++++++++++++++-------------------
 2 files changed, 410 insertions(+), 309 deletions(-)

diff --git a/CHANGELOG b/CHANGELOG
index 548139a32..43c0bd5bc 100644
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -1,3 +1,111 @@
+commit fc6414eca55f1fc108fb12fc8cdc43bd8b4463f9
+Author: Mike Frysinger <vapier@gentoo.org>
+Date:	Tue Dec 18 04:29:55 2007 -0500
+
+    fix easylogo on big endian dev systems
+
+    didnt realize how out of shape easylogo actually was until i tried using it.
+    this patch does byte swapping as need be on the input tga header since the tga
+    is in little endian but the host could just as well be big endian.	i didnt
+    bother using bswap macros or such stuff from system headers as nothing in
+    POSIX dictates byte swapping functionality.
+
+    Signed-Off-By: Mike Frysinger <vapier@gentoo.org>
+
+commit 38d299c2db81bd889c601b5dfc12c4e83ef83333
+Author: Mike Frysinger <vapier@gentoo.org>
+Date:	Tue Dec 18 03:23:25 2007 -0500
+
+    cleanup easylogo
+
+    - make the Makefile not suck
+    - include proper headers for prototypes
+    - fix obvious broken handling of strchr() when handling '.' in filenames
+
+    Signed-Off-By: Mike Frysinger <vapier@gentoo.org>
+
+commit 883e3925d99a8dd69c5b0201cba5b1887f88f95c
+Author: raptorbrino@aim.com <raptorbrino@aim.com>
+Date:	Thu Dec 13 21:23:28 2007 -0500
+
+    Fix build problems under Cygwin
+
+    This patch allows u-boot to build without error in a cygwin
+    environment.  Cygwin does not define __u64 in it's
+    include/asm/types.h file.  The -idirafter flag in the u-boot
+    build causes the inclusion of the cygwin types.h file as opposed
+    to u-bot/include/asm/types.h file which does define __u64.
+    Subsequently, sha1.c compile fails due to unknown symbol.
+
+    Signed-off-by: Brian Miller <raptorbrino@netscape.net>
+
+commit 43ef1c381f9195504a2488f5cb909227eb97d475
+Author: Hans-Christian Egtvedt <hcegtvedt@atmel.com>
+Date:	Fri Nov 30 17:29:59 2007 +0100
+
+    cmd_bmp: Add support for displaying gzip compressed bmps
+
+    The existing code can show information about a gzip compressed BMP
+    image, but can't actually display it.
+
+    Therefore, move the decompression code out of bmp_info() and use it in
+    bmp_display() as well in order to display a compressed BMP image.
+
+    Also, clean things up a bit and fix a memory leak while we're at it.
+
+    [hskinnemoen@atmel.com: a bit of refactoring]
+    Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
+
+commit d197ffd8172c6fdef38733424640a9a47295d6e9
+Author: Guennadi Liakhovetski <lg@denx.de>
+Date:	Thu Nov 29 21:15:56 2007 +0100
+
+    Fix and optimize MII operations on FEC (MPC8xx) controllers
+
+    This patch fixes several issues at least on a MPC885 based system with two
+    FEC interfaces used in MII mode.
+
+    1. PHY discovery should first read PHY_PHYIDR2 register and only then
+       PHY_PHYIDR1 like cpu/mpc8xx/fec.c::mii_discover_phy() does it,
+       otherwise the values read are wrong. Also notice, that PHY discovery
+       cannot work on MPC88x / MPC87x in setups with both FECs active at all
+       in its present form, because for both interfaces the registers from FEC
+       1 are used to communicate over MII.
+
+    2. Remove code duplication for resetting the FEC by isolating it into a
+       separate function.
+
+    3. Initialize MII on FEC 1 when communicating over FEC 2 in fec_init().
+
+    4. Optimize mii_init() to only reset the FEC 1 controller once.
+
+    5. Fix a typo in mii_init() using index i instead of j thus potentially
+       leading to unpredictable results.
+
+    Signed-off-by: Guennadi Liakhovetski <lg@denx.de>
+
+commit 6a5e1d75bf106fa157e9ce68bcaf4b13e8a1d214
+Author: Guennadi Liakhovetski <lg@denx.de>
+Date:	Tue Nov 20 13:14:20 2007 +0100
+
+    Fix endianness conversions in rtl8169 driver
+
+    It is unclear on what platforms this driver has been tested, since
+    noone up to now defines CONFIG_RTL8169 in the board configuration
+    header. Now it has been fixed for a big-endian mpc8241 based
+    linkstation platform. This patch presents the necessary endianness
+    conversion fixes.
+
+    Signed-off-by: Guennadi Liakhovetski <lg@denx.de>
+
+commit 07eb02687f008721974a2fb54cd7fdc28033ab3c
+Author: Wolfgang Denk <wd@denx.de>
+Date:	Wed Jan 9 13:43:38 2008 +0100
+
+    Coding Style clenaup; update CHANGELOG
+
+    Signed-off-by: Wolfgang Denk <wd@denx.de>
+
 commit c26acc1a43b31ddca5add42fd0360ff0eee90c80
 Author: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
 Date:	Thu Dec 27 17:13:11 2007 +0100
diff --git a/tools/easylogo/easylogo.c b/tools/easylogo/easylogo.c
index 6f2aaa6b1..080bea9bb 100644
--- a/tools/easylogo/easylogo.c
+++ b/tools/easylogo/easylogo.c
@@ -16,430 +16,423 @@
 /*#define ENABLE_ASCII_BANNERS */
 
 typedef struct {
-	unsigned char	id;
-	unsigned char	ColorMapType;
-	unsigned char	ImageTypeCode;
-	unsigned short	ColorMapOrigin;
-	unsigned short	ColorMapLenght;
-	unsigned char	ColorMapEntrySize;
-	unsigned short	ImageXOrigin;
-	unsigned short	ImageYOrigin;
-	unsigned short	ImageWidth;
-	unsigned short	ImageHeight;
-	unsigned char	ImagePixelSize;
-	unsigned char	ImageDescriptorByte;
+	unsigned char id;
+	unsigned char ColorMapType;
+	unsigned char ImageTypeCode;
+	unsigned short ColorMapOrigin;
+	unsigned short ColorMapLenght;
+	unsigned char ColorMapEntrySize;
+	unsigned short ImageXOrigin;
+	unsigned short ImageYOrigin;
+	unsigned short ImageWidth;
+	unsigned short ImageHeight;
+	unsigned char ImagePixelSize;
+	unsigned char ImageDescriptorByte;
 } tga_header_t;
 
 typedef struct {
-	unsigned char r,g,b ;
-} rgb_t ;
+	unsigned char r, g, b;
+} rgb_t;
 
 typedef struct {
-	unsigned char b,g,r ;
-} bgr_t ;
+	unsigned char b, g, r;
+} bgr_t;
 
 typedef struct {
-	unsigned char 	Cb,y1,Cr,y2;
-} yuyv_t ;
+	unsigned char Cb, y1, Cr, y2;
+} yuyv_t;
 
 typedef struct {
-	void				*data,
-					*palette ;
-	int				width,
-					height,
-					pixels,
-					bpp,
-					pixel_size,
-					size,
-					palette_size,
-					yuyv;
-} image_t ;
+	void *data, *palette;
+	int width, height, pixels, bpp, pixel_size, size, palette_size, yuyv;
+} image_t;
 
 void StringUpperCase (char *str)
 {
-    int count = strlen(str);
-    char c ;
+	int count = strlen (str);
+	char c;
 
-    while(count--)
-    {
-	c=*str;
-	if ((c >= 'a')&&(c<='z'))
-	    *str = 'A' + (c-'a');
-	str++ ;
-    }
+	while (count--) {
+		c = *str;
+		if ((c >= 'a') && (c <= 'z'))
+			*str = 'A' + (c - 'a');
+		str++;
+	}
 }
 
 void StringLowerCase (char *str)
 {
-    int count = strlen(str);
-    char c ;
+	int count = strlen (str);
+	char c;
 
-    while(count--)
-    {
-	c=*str;
-	if ((c >= 'A')&&(c<='Z'))
-	    *str = 'a' + (c-'A');
-	str++ ;
-    }
+	while (count--) {
+		c = *str;
+		if ((c >= 'A') && (c <= 'Z'))
+			*str = 'a' + (c - 'A');
+		str++;
+	}
 }
-void pixel_rgb_to_yuyv (rgb_t *rgb_pixel, yuyv_t *yuyv_pixel)
+void pixel_rgb_to_yuyv (rgb_t * rgb_pixel, yuyv_t * yuyv_pixel)
 {
-    unsigned int pR, pG, pB ;
+	unsigned int pR, pG, pB;
 
-    /* Transform (0-255) components to (0-100) */
-    pR = rgb_pixel->r * 100 / 255 ;
-    pG = rgb_pixel->g * 100 / 255 ;
-    pB = rgb_pixel->b * 100 / 255 ;
+	/* Transform (0-255) components to (0-100) */
+	pR = rgb_pixel->r * 100 / 255;
+	pG = rgb_pixel->g * 100 / 255;
+	pB = rgb_pixel->b * 100 / 255;
 
-    /* Calculate YUV values (0-255) from RGB beetween 0-100 */
-    yuyv_pixel->y1 = yuyv_pixel->y2 	= 209 * (pR + pG + pB) / 300 + 16  ;
-    yuyv_pixel->Cb 			= pB - (pR/4)   - (pG*3/4)   + 128 ;
-    yuyv_pixel->Cr 			= pR - (pG*3/4) - (pB/4)     + 128 ;
+	/* Calculate YUV values (0-255) from RGB beetween 0-100 */
+	yuyv_pixel->y1 = yuyv_pixel->y2 = 209 * (pR + pG + pB) / 300 + 16;
+	yuyv_pixel->Cb = pB - (pR / 4) - (pG * 3 / 4) + 128;
+	yuyv_pixel->Cr = pR - (pG * 3 / 4) - (pB / 4) + 128;
 
-    return ;
+	return;
 }
 
-void printlogo_rgb (rgb_t	*data, int w, int h)
+void printlogo_rgb (rgb_t * data, int w, int h)
 {
-    int x,y;
-    for (y=0; y<h; y++)
-    {
-	for (x=0; x<w; x++, data++)
-	    if ((data->r < 30)/*&&(data->g == 0)&&(data->b == 0)*/)
-		printf(" ");
-	    else
-		printf("X");
-	printf("\n");
-    }
+	int x, y;
+
+	for (y = 0; y < h; y++) {
+		for (x = 0; x < w; x++, data++)
+			if ((data->r <
+			     30) /*&&(data->g == 0)&&(data->b == 0) */ )
+				printf (" ");
+			else
+				printf ("X");
+		printf ("\n");
+	}
 }
 
 void printlogo_yuyv (unsigned short *data, int w, int h)
 {
-    int x,y;
-    for (y=0; y<h; y++)
-    {
-	for (x=0; x<w; x++, data++)
-	    if (*data == 0x1080)    /* Because of inverted on i386! */
-		printf(" ");
-	    else
-		printf("X");
-	printf("\n");
-    }
+	int x, y;
+
+	for (y = 0; y < h; y++) {
+		for (x = 0; x < w; x++, data++)
+			if (*data == 0x1080)	/* Because of inverted on i386! */
+				printf (" ");
+			else
+				printf ("X");
+		printf ("\n");
+	}
 }
 
 static inline unsigned short le16_to_cpu (unsigned short val)
 {
-    union {
-	unsigned char pval[2];
-	unsigned short val;
-    } swapped;
-    swapped.val = val;
-    return (swapped.pval[1] << 8) + swapped.pval[0];
+	union {
+		unsigned char pval[2];
+		unsigned short val;
+	} swapped;
+
+	swapped.val = val;
+	return (swapped.pval[1] << 8) + swapped.pval[0];
 }
 
-int image_load_tga (image_t *image, char *filename)
+int image_load_tga (image_t * image, char *filename)
 {
-    FILE *file ;
-    tga_header_t header ;
-    int i;
-    unsigned char app ;
-    rgb_t *p ;
+	FILE *file;
+	tga_header_t header;
+	int i;
+	unsigned char app;
+	rgb_t *p;
 
-    if( ( file = fopen( filename, "rb" ) ) == NULL )
-	return -1;
+	if ((file = fopen (filename, "rb")) == NULL)
+		return -1;
 
-    fread(&header, sizeof(header), 1, file);
+	fread (&header, sizeof (header), 1, file);
 
-    /* byte swap: tga is little endian, host is ??? */
-    header.ColorMapOrigin = le16_to_cpu (header.ColorMapOrigin);
-    header.ColorMapLenght = le16_to_cpu (header.ColorMapLenght);
-    header.ImageXOrigin = le16_to_cpu (header.ImageXOrigin);
-    header.ImageYOrigin = le16_to_cpu (header.ImageYOrigin);
-    header.ImageWidth = le16_to_cpu (header.ImageWidth);
-    header.ImageHeight = le16_to_cpu (header.ImageHeight);
+	/* byte swap: tga is little endian, host is ??? */
+	header.ColorMapOrigin = le16_to_cpu (header.ColorMapOrigin);
+	header.ColorMapLenght = le16_to_cpu (header.ColorMapLenght);
+	header.ImageXOrigin = le16_to_cpu (header.ImageXOrigin);
+	header.ImageYOrigin = le16_to_cpu (header.ImageYOrigin);
+	header.ImageWidth = le16_to_cpu (header.ImageWidth);
+	header.ImageHeight = le16_to_cpu (header.ImageHeight);
 
-    image->width 	= header.ImageWidth ;
-    image->height 	= header.ImageHeight ;
+	image->width = header.ImageWidth;
+	image->height = header.ImageHeight;
 
-    switch (header.ImageTypeCode){
-	case 2:	/* Uncompressed RGB */
-			image->yuyv = 0 ;
-			image->palette_size = 0 ;
-			image->palette = NULL ;
-	    break;
+	switch (header.ImageTypeCode) {
+	case 2:		/* Uncompressed RGB */
+		image->yuyv = 0;
+		image->palette_size = 0;
+		image->palette = NULL;
+		break;
 
 	default:
-	    printf("Format not supported!\n");
-	    return -1 ;
-    }
+		printf ("Format not supported!\n");
+		return -1;
+	}
 
-    image->bpp  		= header.ImagePixelSize ;
-    image->pixel_size 		= ((image->bpp-1) / 8) + 1 ;
-    image->pixels 		= image->width * image->height;
-    image->size 		= image->pixels * image->pixel_size ;
-    image->data 		= malloc(image->size) ;
+	image->bpp = header.ImagePixelSize;
+	image->pixel_size = ((image->bpp - 1) / 8) + 1;
+	image->pixels = image->width * image->height;
+	image->size = image->pixels * image->pixel_size;
+	image->data = malloc (image->size);
 
-    if (image->bpp != 24)
-    {
-	printf("Bpp not supported: %d!\n", image->bpp);
-	return -1 ;
-    }
+	if (image->bpp != 24) {
+		printf ("Bpp not supported: %d!\n", image->bpp);
+		return -1;
+	}
 
-    fread(image->data, image->size, 1, file);
+	fread (image->data, image->size, 1, file);
 
 /* Swapping R and B values */
 
-    p = image->data ;
-    for(i=0; i < image->pixels; i++, p++)
-    {
-	app = p->r ;
-	p->r = p->b ;
-	p->b = app ;
-    }
+	p = image->data;
+	for (i = 0; i < image->pixels; i++, p++) {
+		app = p->r;
+		p->r = p->b;
+		p->b = app;
+	}
 
 /* Swapping image */
 
-    if(!(header.ImageDescriptorByte & 0x20))
-    {
-	unsigned char *temp = malloc(image->size);
-	int linesize = image->pixel_size * image->width ;
-	void	*dest = image->data,
-		*source = temp + image->size - linesize ;
+	if (!(header.ImageDescriptorByte & 0x20)) {
+		unsigned char *temp = malloc (image->size);
+		int linesize = image->pixel_size * image->width;
+		void *dest = image->data,
+			*source = temp + image->size - linesize;
 
-	printf("S");
-	if (temp == NULL)
-	{
-	    printf("Cannot alloc temp buffer!\n");
-	    return -1;
+		printf ("S");
+		if (temp == NULL) {
+			printf ("Cannot alloc temp buffer!\n");
+			return -1;
+		}
+
+		memcpy (temp, image->data, image->size);
+		for (i = 0; i < image->height;
+		     i++, dest += linesize, source -= linesize)
+			memcpy (dest, source, linesize);
+
+		free (temp);
 	}
-
-	memcpy(temp, image->data, image->size);
-	for(i = 0; i<image->height; i++, dest+=linesize, source-=linesize)
-	    memcpy(dest, source, linesize);
-
-	free( temp );
-    }
-
 #ifdef ENABLE_ASCII_BANNERS
-    printlogo_rgb (image->data,image->width, image->height);
+	printlogo_rgb (image->data, image->width, image->height);
 #endif
 
-    fclose (file);
-    return 0;
+	fclose (file);
+	return 0;
 }
 
-int image_free (image_t *image)
+int image_free (image_t * image)
 {
-    if(image->data != NULL)
-		free(image->data);
+	if (image->data != NULL)
+		free (image->data);
 
-    if(image->palette != NULL)
-		free(image->palette);
+	if (image->palette != NULL)
+		free (image->palette);
 
 	return 0;
 }
 
-int image_rgb_to_yuyv (image_t *rgb_image, image_t *yuyv_image)
+int image_rgb_to_yuyv (image_t * rgb_image, image_t * yuyv_image)
 {
-	rgb_t	*rgb_ptr = (rgb_t *) rgb_image->data ;
-	yuyv_t	yuyv ;
-	unsigned short *dest ;
-	int	count = 0 ;
+	rgb_t *rgb_ptr = (rgb_t *) rgb_image->data;
+	yuyv_t yuyv;
+	unsigned short *dest;
+	int count = 0;
 
-	yuyv_image->pixel_size 		= 2 ;
-	yuyv_image->bpp			= 16 ;
-	yuyv_image->yuyv		= 1 ;
-	yuyv_image->width		= rgb_image->width ;
-	yuyv_image->height		= rgb_image->height ;
-	yuyv_image->pixels 		= yuyv_image->width * yuyv_image->height ;
-	yuyv_image->size 		= yuyv_image->pixels * yuyv_image->pixel_size ;
-	dest = (unsigned short *) (yuyv_image->data	= malloc(yuyv_image->size)) ;
-	yuyv_image->palette		= 0 ;
-	yuyv_image->palette_size= 0 ;
+	yuyv_image->pixel_size = 2;
+	yuyv_image->bpp = 16;
+	yuyv_image->yuyv = 1;
+	yuyv_image->width = rgb_image->width;
+	yuyv_image->height = rgb_image->height;
+	yuyv_image->pixels = yuyv_image->width * yuyv_image->height;
+	yuyv_image->size = yuyv_image->pixels * yuyv_image->pixel_size;
+	dest = (unsigned short *) (yuyv_image->data =
+				   malloc (yuyv_image->size));
+	yuyv_image->palette = 0;
+	yuyv_image->palette_size = 0;
 
-	while((count++) < rgb_image->pixels)
-	{
+	while ((count++) < rgb_image->pixels) {
 		pixel_rgb_to_yuyv (rgb_ptr++, &yuyv);
 
-		if ((count & 1)==0)	/* Was == 0 */
-		    memcpy (dest, ((void *)&yuyv) + 2, sizeof(short));
+		if ((count & 1) == 0)	/* Was == 0 */
+			memcpy (dest, ((void *) &yuyv) + 2, sizeof (short));
 		else
-		    memcpy (dest, (void *)&yuyv, sizeof(short));
+			memcpy (dest, (void *) &yuyv, sizeof (short));
 
-		dest ++ ;
+		dest++;
 	}
 
 #ifdef ENABLE_ASCII_BANNERS
-	printlogo_yuyv (yuyv_image->data, yuyv_image->width, yuyv_image->height);
+	printlogo_yuyv (yuyv_image->data, yuyv_image->width,
+			yuyv_image->height);
 #endif
-	return 0 ;
+	return 0;
 }
 
-int image_save_header (image_t *image, char *filename, char *varname)
+int image_save_header (image_t * image, char *filename, char *varname)
 {
-	FILE    *file = fopen (filename, "w");
-	char	app[256], str[256]="", def_name[64] ;
-	int 	count = image->size, col=0;
-	unsigned char *dataptr = image->data ;
-	if (file==NULL)
-		return -1 ;
+	FILE *file = fopen (filename, "w");
+	char app[256], str[256] = "", def_name[64];
+	int count = image->size, col = 0;
+	unsigned char *dataptr = image->data;
 
-/*  Author information */
-	fprintf(file, "/*\n * Generated by EasyLogo, (C) 2000 by Paolo Scaffardi\n *\n");
-	fprintf(file, " * To use this, include it and call: easylogo_plot(screen,&%s, width,x,y)\n *\n", varname);
-	fprintf(file, " * Where:\t'screen'\tis the pointer to the frame buffer\n");
-	fprintf(file, " *\t\t'width'\tis the screen width\n");
-	fprintf(file, " *\t\t'x'\t\tis the horizontal position\n");
-	fprintf(file, " *\t\t'y'\t\tis the vertical position\n */\n\n");
+	if (file == NULL)
+		return -1;
 
-/*	Headers */
-	fprintf(file, "#include <video_easylogo.h>\n\n");
-/*	Macros */
-	strcpy(def_name, varname);
+	/*  Author information */
+	fprintf (file,
+		 "/*\n * Generated by EasyLogo, (C) 2000 by Paolo Scaffardi\n *\n");
+	fprintf (file,
+		 " * To use this, include it and call: easylogo_plot(screen,&%s, width,x,y)\n *\n",
+		 varname);
+	fprintf (file,
+		 " * Where:\t'screen'\tis the pointer to the frame buffer\n");
+	fprintf (file, " *\t\t'width'\tis the screen width\n");
+	fprintf (file, " *\t\t'x'\t\tis the horizontal position\n");
+	fprintf (file, " *\t\t'y'\t\tis the vertical position\n */\n\n");
+
+	/*	Headers */
+	fprintf (file, "#include <video_easylogo.h>\n\n");
+	/*	Macros */
+	strcpy (def_name, varname);
 	StringUpperCase (def_name);
-	fprintf(file, "#define	DEF_%s_WIDTH\t\t%d\n", def_name, image->width);
-	fprintf(file, "#define	DEF_%s_HEIGHT\t\t%d\n", def_name, image->height);
-	fprintf(file, "#define	DEF_%s_PIXELS\t\t%d\n", def_name, image->pixels);
-	fprintf(file, "#define	DEF_%s_BPP\t\t%d\n", def_name, image->bpp);
-	fprintf(file, "#define	DEF_%s_PIXEL_SIZE\t%d\n", def_name, image->pixel_size);
-	fprintf(file, "#define	DEF_%s_SIZE\t\t%d\n\n", def_name, image->size);
-/*  Declaration */
-	fprintf(file, "unsigned char DEF_%s_DATA[DEF_%s_SIZE] = {\n", def_name, def_name);
+	fprintf (file, "#define	DEF_%s_WIDTH\t\t%d\n", def_name,
+		 image->width);
+	fprintf (file, "#define	DEF_%s_HEIGHT\t\t%d\n", def_name,
+		 image->height);
+	fprintf (file, "#define	DEF_%s_PIXELS\t\t%d\n", def_name,
+		 image->pixels);
+	fprintf (file, "#define	DEF_%s_BPP\t\t%d\n", def_name, image->bpp);
+	fprintf (file, "#define	DEF_%s_PIXEL_SIZE\t%d\n", def_name,
+		 image->pixel_size);
+	fprintf (file, "#define	DEF_%s_SIZE\t\t%d\n\n", def_name,
+		 image->size);
+	/*  Declaration */
+	fprintf (file, "unsigned char DEF_%s_DATA[DEF_%s_SIZE] = {\n",
+		 def_name, def_name);
 
-/*	Data */
-	while(count)
-		switch (col){
-			case 0:
-				sprintf(str, " 0x%02x", *dataptr++);
-				col++;
-				count-- ;
-				break;
+	/*	Data */
+	while (count)
+		switch (col) {
+		case 0:
+			sprintf (str, " 0x%02x", *dataptr++);
+			col++;
+			count--;
+			break;
 
-			case 16:
-				fprintf(file, "%s", str);
-				if (count > 0)
-				    fprintf(file,",");
-				fprintf(file, "\n");
+		case 16:
+			fprintf (file, "%s", str);
+			if (count > 0)
+				fprintf (file, ",");
+			fprintf (file, "\n");
 
-				col = 0 ;
-				break;
+			col = 0;
+			break;
 
-			default:
-				strcpy(app, str);
-				sprintf(str, "%s, 0x%02x", app, *dataptr++);
-				col++ ;
-				count-- ;
-				break;
+		default:
+			strcpy (app, str);
+			sprintf (str, "%s, 0x%02x", app, *dataptr++);
+			col++;
+			count--;
+			break;
 		}
 
 	if (col)
-		fprintf(file, "%s\n", str);
+		fprintf (file, "%s\n", str);
 
-/* 	End of declaration */
-	fprintf(file, "};\n\n");
-/*	Variable */
-	fprintf(file, "fastimage_t %s = {\n", varname);
-	fprintf(file, "		DEF_%s_DATA,\n", def_name);
-	fprintf(file, "		DEF_%s_WIDTH,\n", def_name);
-	fprintf(file, "		DEF_%s_HEIGHT,\n", def_name);
-	fprintf(file, "		DEF_%s_BPP,\n", def_name);
-	fprintf(file, "		DEF_%s_PIXEL_SIZE,\n", def_name);
-	fprintf(file, "		DEF_%s_SIZE\n};\n", def_name);
+	/* 	End of declaration */
+	fprintf (file, "};\n\n");
+	/*	Variable */
+	fprintf (file, "fastimage_t %s = {\n", varname);
+	fprintf (file, "		DEF_%s_DATA,\n", def_name);
+	fprintf (file, "		DEF_%s_WIDTH,\n", def_name);
+	fprintf (file, "		DEF_%s_HEIGHT,\n", def_name);
+	fprintf (file, "		DEF_%s_BPP,\n", def_name);
+	fprintf (file, "		DEF_%s_PIXEL_SIZE,\n", def_name);
+	fprintf (file, "		DEF_%s_SIZE\n};\n", def_name);
 
 	fclose (file);
 
-	return 0 ;
+	return 0;
 }
 
 #define DEF_FILELEN	256
 
 int main (int argc, char *argv[])
 {
-    char
-	inputfile[DEF_FILELEN],
-	outputfile[DEF_FILELEN],
-	varname[DEF_FILELEN];
+	char inputfile[DEF_FILELEN],
+		outputfile[DEF_FILELEN], varname[DEF_FILELEN];
 
-    image_t 		rgb_logo, yuyv_logo ;
+	image_t rgb_logo, yuyv_logo;
 
-    switch (argc){
-    case 2:
-    case 3:
-    case 4:
-	strcpy (inputfile, 	argv[1]);
+	switch (argc) {
+	case 2:
+	case 3:
+	case 4:
+		strcpy (inputfile, argv[1]);
 
-	if (argc > 2)
-	    strcpy (varname, 	argv[2]);
-	else
-	{
-	    char *dot = strchr(inputfile, '.');
-	    int pos = dot - inputfile;
+		if (argc > 2)
+			strcpy (varname, argv[2]);
+		else {
+			char *dot = strchr (inputfile, '.');
+			int pos = dot - inputfile;
 
-	    if (dot)
-	    {
-		strncpy (varname, inputfile, pos);
-		varname[pos] = 0 ;
-	    }
+			if (dot) {
+				strncpy (varname, inputfile, pos);
+				varname[pos] = 0;
+			}
+		}
+
+		if (argc > 3)
+			strcpy (outputfile, argv[3]);
+		else {
+			char *dot = strchr (varname, '.');
+			int pos = dot - varname;
+
+			if (dot) {
+				char app[DEF_FILELEN];
+
+				strncpy (app, varname, pos);
+				app[pos] = 0;
+				sprintf (outputfile, "%s.h", app);
+			}
+		}
+		break;
+
+	default:
+		printf ("EasyLogo 1.0 (C) 2000 by Paolo Scaffardi\n\n");
+
+		printf("Syntax:	easylogo inputfile [outputvar {outputfile}] \n");
+		printf("\n");
+		printf("Where:	'inputfile' 	is the TGA image to load\n");
+		printf("      	'outputvar' 	is the variable name to create\n");
+		printf("       	'outputfile' 	is the output header file (default is 'inputfile.h')\n");
+
+		return -1;
 	}
 
-	if (argc > 3)
-	    strcpy (outputfile, argv[3]);
-	else
-	{
-	    char *dot = strchr (varname, '.');
-	    int pos = dot - varname;
+	printf ("Doing '%s' (%s) from '%s'...",
+		outputfile, varname, inputfile);
 
-	    if (dot)
-	    {
-		char app[DEF_FILELEN] ;
+	/* Import TGA logo */
 
-		strncpy(app, varname, pos);
-		app[pos] = 0;
-		sprintf(outputfile, "%s.h", app);
-	    }
+	printf ("L");
+	if (image_load_tga (&rgb_logo, inputfile) < 0) {
+		printf ("input file not found!\n");
+		exit (1);
 	}
-	break;
 
-    default:
-	printf("EasyLogo 1.0 (C) 2000 by Paolo Scaffardi\n\n");
+	/* Convert it to YUYV format */
 
-	printf("Syntax:	easylogo inputfile [outputvar {outputfile}] \n");
-	printf("\n");
-	printf("Where:	'inputfile' 	is the TGA image to load\n");
-	printf("      	'outputvar' 	is the variable name to create\n");
-	printf("       	'outputfile' 	is the output header file (default is 'inputfile.h')\n");
+	printf ("C");
+	image_rgb_to_yuyv (&rgb_logo, &yuyv_logo);
 
-	return -1 ;
-    }
+	/* Save it into a header format */
 
-    printf("Doing '%s' (%s) from '%s'...",
-	outputfile, varname, inputfile);
+	printf ("S");
+	image_save_header (&yuyv_logo, outputfile, varname);
 
-/* Import TGA logo */
+	/* Free original image and copy */
 
-    printf("L");
-    if (image_load_tga (&rgb_logo, inputfile)<0)
-    {
-	printf("input file not found!\n");
-	exit(1);
-    }
+	image_free (&rgb_logo);
+	image_free (&yuyv_logo);
 
-/* Convert it to YUYV format */
+	printf ("\n");
 
-    printf("C");
-    image_rgb_to_yuyv (&rgb_logo, &yuyv_logo) ;
-
-/* Save it into a header format */
-
-    printf("S");
-    image_save_header (&yuyv_logo, outputfile, varname) ;
-
-/* Free original image and copy */
-
-    image_free (&rgb_logo);
-    image_free (&yuyv_logo);
-
-    printf("\n");
-
-    return 0 ;
+	return 0;
 }