liliana/r-link-uboot
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Merge branch 'master' of git://www.denx.de/git/u-boot-sh

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This commit is contained in:
Wolfgang Denk 2008-07-09 23:09:36 +02:00
commit 2caea1ebee
24 changed files with 86 additions and 121 deletions
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2
MAKEALL
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@ -749,7 +749,7 @@ LIST_sh3=" \
LIST_sh4=" \ LIST_sh4=" \
ms7750se \ ms7750se \
ms7722se \ ms7722se \
Migo-R \ MigoR \
r7780mp \ r7780mp \
r2dplus \ r2dplus \
sh7763rdp \ sh7763rdp \

2
board/MigoR/Makefile
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@ -26,7 +26,7 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a LIB = $(obj)lib$(BOARD).a
OBJS := migo_r.o COBJS := migo_r.o
SOBJS := lowlevel_init.o SOBJS := lowlevel_init.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)

2
board/mpr2/Makefile
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@ -32,7 +32,7 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a LIB = $(obj)lib$(BOARD).a
OBJS := mpr2.o COBJS := mpr2.o
SOBJS := lowlevel_init.o SOBJS := lowlevel_init.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)

2
board/ms7720se/Makefile
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@ -29,7 +29,7 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a LIB = $(obj)lib$(BOARD).a
OBJS := ms7720se.o COBJS := ms7720se.o
SOBJS := lowlevel_init.o SOBJS := lowlevel_init.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)

1
board/ms7720se/ms7720se.c
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@ -40,7 +40,6 @@ int checkboard(void)
int board_init(void) int board_init(void)
{ {
return 0; return 0;
} }

2
board/ms7722se/Makefile
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@ -26,7 +26,7 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a LIB = $(obj)lib$(BOARD).a
OBJS := ms7722se.o COBJS := ms7722se.o
SOBJS := lowlevel_init.o SOBJS := lowlevel_init.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)

8
board/ms7722se/ms7722se.c
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@ -1,5 +1,5 @@
/* /*
* Copyright (C) 2007 * Copyright (C) 2007,2008
* Nobuhiro Iwamatsu <iwamatsu@nigauri.org> * Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
* *
* Copyright (C) 2007 * Copyright (C) 2007
@ -43,7 +43,7 @@ int board_init(void)
return 0; return 0;
} }
int dram_init (void) int dram_init(void)
{ {
DECLARE_GLOBAL_DATA_PTR; DECLARE_GLOBAL_DATA_PTR;
@ -53,7 +53,7 @@ int dram_init (void)
return 0; return 0;
} }
void led_set_state (unsigned short value) void led_set_state(unsigned short value)
{ {
*((volatile unsigned short *) LED_BASE) = (value & 0xFF); writew(value & 0xFF, LED_BASE);
} }

2
board/ms7750se/Makefile
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@ -21,7 +21,7 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a LIB = $(obj)lib$(BOARD).a
OBJS := ms7750se.o COBJS := ms7750se.o
SOBJS := lowlevel_init.o SOBJS := lowlevel_init.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)

2
board/r2dplus/Makefile
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@ -21,7 +21,7 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a LIB = $(obj)lib$(BOARD).a
OBJS := r2dplus.o COBJS := r2dplus.o
SOBJS := lowlevel_init.o SOBJS := lowlevel_init.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)

28
board/r2dplus/r2dplus.c
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@ -24,6 +24,7 @@
#include <common.h> #include <common.h>
#include <ide.h> #include <ide.h>
#include <asm/processor.h> #include <asm/processor.h>
#include <asm/io.h>
#include <asm/pci.h> #include <asm/pci.h>
int checkboard(void) int checkboard(void)
@ -37,7 +38,7 @@ int board_init(void)
return 0; return 0;
} }
int dram_init (void) int dram_init(void)
{ {
DECLARE_GLOBAL_DATA_PTR; DECLARE_GLOBAL_DATA_PTR;
@ -52,25 +53,26 @@ int board_late_init(void)
return 0; return 0;
} }
#define FPGA_BASE 0xA4000000 #define FPGA_BASE 0xA4000000
#define FPGA_CFCTL (FPGA_BASE + 0x04) #define FPGA_CFCTL (FPGA_BASE + 0x04)
#define FPGA_CFPOW (FPGA_BASE + 0x06) #define CFCTL_EN (0x432)
#define FPGA_CFCDINTCLR (FPGA_BASE + 0x2A) #define FPGA_CFPOW (FPGA_BASE + 0x06)
#define CFPOW_ON (0x02)
#define FPGA_CFCDINTCLR (FPGA_BASE + 0x2A)
#define CFCDINTCLR_EN (0x01)
void ide_set_reset (int idereset) void ide_set_reset(int idereset)
{ {
/* if reset = 1 IDE reset will be asserted */ /* if reset = 1 IDE reset will be asserted */
if (idereset){ if (idereset) {
(*(vu_short *)FPGA_CFCTL) = 0x432; outw(CFCTL_EN, FPGA_CFCTL); /* CF enable */
(*(vu_short *)FPGA_CFPOW) |= 0x02; outw(inw(FPGA_CFPOW)|CFPOW_ON, FPGA_CFPOW); /* Power OM */
(*(vu_short *)FPGA_CFCDINTCLR) = 0x01; outw(CFCDINTCLR_EN, FPGA_CFCDINTCLR); /* Int clear */
} }
} }
#if defined(CONFIG_PCI)
static struct pci_controller hose; static struct pci_controller hose;
void pci_init_board(void) void pci_init_board(void)
{ {
pci_sh7751_init( &hose ); pci_sh7751_init(&hose);
} }
#endif /* CONFIG_PCI */

2
board/r7780mp/Makefile
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@ -22,7 +22,7 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a LIB = $(obj)lib$(BOARD).a
OBJS := r7780mp.o COBJS := r7780mp.o
SOBJS := lowlevel_init.o SOBJS := lowlevel_init.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)

22
board/r7780mp/r7780mp.c
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@ -38,12 +38,12 @@ int checkboard(void)
int board_init(void) int board_init(void)
{ {
/* SCIF Enable */ /* SCIF Enable */
*(vu_short*)PHCR = 0x0000; writew(0x0, PHCR);
return 0; return 0;
} }
int dram_init (void) int dram_init(void)
{ {
DECLARE_GLOBAL_DATA_PTR; DECLARE_GLOBAL_DATA_PTR;
@ -53,29 +53,27 @@ int dram_init (void)
return 0; return 0;
} }
void led_set_state (unsigned short value) void led_set_state(unsigned short value)
{ {
} }
void ide_set_reset (int idereset) void ide_set_reset(int idereset)
{ {
/* if reset = 1 IDE reset will be asserted */ /* if reset = 1 IDE reset will be asserted */
if (idereset){ if (idereset) {
(*(vu_short *)FPGA_CFCTL) = 0x432; writew(0x432, FPGA_CFCTL);
#if defined(CONFIG_R7780MP) #if defined(CONFIG_R7780MP)
(*(vu_short *)FPGA_CFPOW) |= 0x01; writew(inw(FPGA_CFPOW)|0x01, FPGA_CFPOW);
#else #else
(*(vu_short *)FPGA_CFPOW) |= 0x02; writew(inw(FPGA_CFPOW)|0x02, FPGA_CFPOW);
#endif #endif
(*(vu_short *)FPGA_CFCDINTCLR) = 0x01; writew(0x01, FPGA_CFCDINTCLR);
} }
} }
#if defined(CONFIG_PCI)
static struct pci_controller hose; static struct pci_controller hose;
void pci_init_board(void) void pci_init_board(void)
{ {
pci_sh7780_init( &hose ); pci_sh7780_init(&hose);
} }
#endif

2
board/sh7763rdp/Makefile
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@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a LIB = $(obj)lib$(BOARD).a
OBJS := sh7763rdp.o COBJS := sh7763rdp.o
SOBJS := lowlevel_init.o SOBJS := lowlevel_init.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)

17
board/sh7763rdp/sh7763rdp.c
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@ -49,19 +49,20 @@ int board_init(void)
{ {
vu_short dat; vu_short dat;
*(vu_short *)(CPU_CMDREG) |= 0x0001; /* Enable mode */
writew(inw(CPU_CMDREG)|0x0001, CPU_CMDREG);
/* GPIO Setting (eth1) */ /* GPIO Setting (eth1) */
dat = *(vu_short *)(PSEL1); dat = inw(PSEL1);
*(vu_short *)PSEL1 = ((dat & ~0xff00) | 0x2400); writew(((dat & ~0xff00) | 0x2400), PSEL1);
*(vu_short *)PFCR = 0; writew(0, PFCR);
*(vu_short *)PGCR = 0; writew(0, PGCR);
*(vu_short *)PHCR = 0; writew(0, PHCR);
return 0; return 0;
} }
int dram_init (void) int dram_init(void)
{ {
DECLARE_GLOBAL_DATA_PTR; DECLARE_GLOBAL_DATA_PTR;
@ -71,6 +72,6 @@ int dram_init (void)
return 0; return 0;
} }
void led_set_state (unsigned short value) void led_set_state(unsigned short value)
{ {
} }

2
cpu/sh3/Makefile
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@ -32,7 +32,7 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(CPU).a LIB = $(obj)lib$(CPU).a
SOBJS = start.o SOBJS = start.o
OBJS = cpu.o interrupts.o watchdog.o time.o cache.o COBJS = cpu.o interrupts.o watchdog.o time.o cache.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS)) OBJS := $(addprefix $(obj),$(COBJS))

2
cpu/sh4/Makefile
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@ -29,7 +29,7 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(CPU).a LIB = $(obj)lib$(CPU).a
SOBJS = start.o SOBJS = start.o
OBJS = cpu.o interrupts.o watchdog.o time.o cache.o COBJS = cpu.o interrupts.o watchdog.o time.o cache.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS)) OBJS := $(addprefix $(obj),$(COBJS))

4
include/configs/MigoR.h
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@ -45,10 +45,6 @@
#define CONFIG_BAUDRATE 115200 #define CONFIG_BAUDRATE 115200
#define CONFIG_BOOTDELAY 3 #define CONFIG_BOOTDELAY 3
#define CONFIG_BOOTARGS "console=ttySC0,115200 root=1f01" #define CONFIG_BOOTARGS "console=ttySC0,115200 root=1f01"
#define CONFIG_NETMASK 255.255.255.0
#define CONFIG_IPADDR 192.168.10.100
#define CONFIG_SERVERIP 192.168.10.77
#define CONFIG_GATEWAYIP 192.168.10.77
#define CONFIG_VERSION_VARIABLE #define CONFIG_VERSION_VARIABLE
#undef CONFIG_SHOW_BOOT_PROGRESS #undef CONFIG_SHOW_BOOT_PROGRESS

4
include/configs/ms7722se.h
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@ -40,10 +40,6 @@
#define CONFIG_BAUDRATE 115200 #define CONFIG_BAUDRATE 115200
#define CONFIG_BOOTDELAY 3 #define CONFIG_BOOTDELAY 3
#define CONFIG_BOOTARGS "console=ttySC0,115200 root=1f01" #define CONFIG_BOOTARGS "console=ttySC0,115200 root=1f01"
#define CONFIG_NETMASK 255.255.255.0
#define CONFIG_IPADDR 192.168.0.22
#define CONFIG_SERVERIP 192.168.0.1
#define CONFIG_GATEWAYIP 192.168.0.1
#define CONFIG_VERSION_VARIABLE #define CONFIG_VERSION_VARIABLE
#undef CONFIG_SHOW_BOOT_PROGRESS #undef CONFIG_SHOW_BOOT_PROGRESS

42
include/configs/r2dplus.h
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@ -35,12 +35,6 @@
#define CONFIG_BOOTARGS "console=ttySC0,115200" #define CONFIG_BOOTARGS "console=ttySC0,115200"
#define CONFIG_ENV_OVERWRITE 1 #define CONFIG_ENV_OVERWRITE 1
/* Network setting */
#define CONFIG_NETMASK 255.0.0.0
#define CONFIG_IPADDR 10.0.192.51
#define CONFIG_SERVERIP 10.0.0.1
#define CONFIG_GATEWAYIP 10.0.0.1
/* SDRAM */ /* SDRAM */
#define CFG_SDRAM_BASE (0x8C000000) #define CFG_SDRAM_BASE (0x8C000000)
#define CFG_SDRAM_SIZE (0x04000000) #define CFG_SDRAM_SIZE (0x04000000)
@ -60,45 +54,27 @@
#define CFG_LOAD_ADDR (CFG_SDRAM_BASE + 32 * 1024 * 1024) #define CFG_LOAD_ADDR (CFG_SDRAM_BASE + 32 * 1024 * 1024)
/* Address of u-boot image in Flash */ /* Address of u-boot image in Flash */
#define CFG_MONITOR_BASE (CFG_FLASH_BASE) #define CFG_MONITOR_BASE (CFG_FLASH_BASE)
#define CFG_MONITOR_LEN (128 * 1024) #define CFG_MONITOR_LEN (256 * 1024)
/* Size of DRAM reserved for malloc() use */ /* Size of DRAM reserved for malloc() use */
#define CFG_MALLOC_LEN (256 * 1024) #define CFG_MALLOC_LEN (1024 * 1024)
/* size in bytes reserved for initial data */ /* size in bytes reserved for initial data */
#define CFG_GBL_DATA_SIZE (256) #define CFG_GBL_DATA_SIZE (256)
#define CFG_BOOTMAPSZ (8 * 1024 * 1024) #define CFG_BOOTMAPSZ (8 * 1024 * 1024)
/* /*
* NOR Flash * NOR Flash ( Spantion S29GL256P )
*/ */
#define CFG_FLASH_CFI #define CFG_FLASH_CFI
#define CFG_FLASH_CFI_DRIVER #define CFG_FLASH_CFI_DRIVER
#if defined(CONFIG_R2DPLUS_OLD)
#define CFG_FLASH_BASE (0xA0000000) #define CFG_FLASH_BASE (0xA0000000)
#define CFG_MAX_FLASH_BANKS (1) /* Max number of #define CFG_MAX_FLASH_BANKS (1)
* Flash memory banks #define CFG_MAX_FLASH_SECT 256
*/ #define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE }
#define CFG_MAX_FLASH_SECT 142
#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE }
#else /* CONFIG_R2DPLUS_OLD */
#define CFG_FLASH_BASE (0xA0000000)
#define CFG_FLASH_CFI_WIDTH 0x04 /* 32bit */
#define CFG_MAX_FLASH_BANKS (2)
#define CFG_MAX_FLASH_SECT 270
#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE,\
CFG_FLASH_BASE + 0x100000,\
CFG_FLASH_BASE + 0x400000,\
CFG_FLASH_BASE + 0x700000, }
#endif /* CONFIG_R2DPLUS_OLD */
#define CFG_ENV_IS_IN_FLASH #define CFG_ENV_IS_IN_FLASH
#define CFG_ENV_SECT_SIZE 0x20000 #define CFG_ENV_SECT_SIZE 0x40000
#define CFG_ENV_SIZE (CFG_ENV_SECT_SIZE) #define CFG_ENV_SIZE (CFG_ENV_SECT_SIZE)
#define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN) #define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN)
#define CFG_FLASH_ERASE_TOUT 120000
#define CFG_FLASH_WRITE_TOUT 500
/* /*
* SuperH Clock setting * SuperH Clock setting

41
include/configs/r7780mp.h
View File

@ -1,7 +1,7 @@
/* /*
* Configuation settings for the Renesas R7780MP board * Configuation settings for the Renesas R7780MP board
* *
* Copyright (C) 2007 Nobuhiro Iwamatsu <iwamatsu@nigauri.org> * Copyright (C) 2007,2008 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
* Copyright (C) 2008 Yusuke Goda <goda.yusuke@renesas.com> * Copyright (C) 2008 Yusuke Goda <goda.yusuke@renesas.com>
* *
* See file CREDITS for list of people who contributed to this * See file CREDITS for list of people who contributed to this
@ -31,7 +31,8 @@
#define CONFIG_SH4A 1 #define CONFIG_SH4A 1
#define CONFIG_CPU_SH7780 1 #define CONFIG_CPU_SH7780 1
#define CONFIG_R7780MP 1 #define CONFIG_R7780MP 1
#define __LITTLE_ENDIAN 1 #define CFG_R7780MP_OLD_FLASH 1
#define __LITTLE_ENDIAN__ 1
/* /*
* Command line configuration. * Command line configuration.
@ -59,12 +60,6 @@
/* check for keypress on bootdelay==0 */ /* check for keypress on bootdelay==0 */
/*#define CONFIG_ZERO_BOOTDELAY_CHECK*/ /*#define CONFIG_ZERO_BOOTDELAY_CHECK*/
/* Network setting */
#define CONFIG_NETMASK 255.0.0.0
#define CONFIG_IPADDR 10.0.192.82
#define CONFIG_SERVERIP 10.0.0.1
#define CONFIG_GATEWAYIP 10.0.0.1
#define CFG_SDRAM_BASE (0x08000000) #define CFG_SDRAM_BASE (0x08000000)
#define CFG_SDRAM_SIZE (128 * 1024 * 1024) #define CFG_SDRAM_SIZE (128 * 1024 * 1024)
@ -80,22 +75,30 @@
#define CFG_MEMTEST_START (CFG_SDRAM_BASE) #define CFG_MEMTEST_START (CFG_SDRAM_BASE)
#define CFG_MEMTEST_END (TEXT_BASE - 0x100000) #define CFG_MEMTEST_END (TEXT_BASE - 0x100000)
/* NOR Flash (S29PL127J60TFI130) */ /* Flash board support */
#define CFG_FLASH_BASE (0xA0000000) #define CFG_FLASH_BASE (0xA0000000)
#define CFG_FLASH_CFI_WIDTH FLASH_CFI_32BIT #ifdef CFG_R7780MP_OLD_FLASH
#define CFG_MAX_FLASH_BANKS (2) /* NOR Flash (S29PL127J60TFI130) */
#define CFG_MAX_FLASH_SECT 270 # define CFG_FLASH_CFI_WIDTH FLASH_CFI_32BIT
#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE,\ # define CFG_MAX_FLASH_BANKS (2)
# define CFG_MAX_FLASH_SECT 270
# define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE,\
CFG_FLASH_BASE + 0x100000,\ CFG_FLASH_BASE + 0x100000,\
CFG_FLASH_BASE + 0x400000,\ CFG_FLASH_BASE + 0x400000,\
CFG_FLASH_BASE + 0x700000, } CFG_FLASH_BASE + 0x700000, }
#else /* CFG_R7780MP_OLD_FLASH */
/* NOR Flash (Spantion S29GL256P) */
# define CFG_MAX_FLASH_BANKS (1)
# define CFG_MAX_FLASH_SECT 256
# define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE }
#endif /* CFG_R7780MP_OLD_FLASH */
#define CFG_LOAD_ADDR (CFG_SDRAM_BASE + 4 * 1024 * 1024) #define CFG_LOAD_ADDR (CFG_SDRAM_BASE + 4 * 1024 * 1024)
/* Address of u-boot image in Flash */ /* Address of u-boot image in Flash */
#define CFG_MONITOR_BASE (CFG_FLASH_BASE) #define CFG_MONITOR_BASE (CFG_FLASH_BASE)
#define CFG_MONITOR_LEN (112 * 1024) #define CFG_MONITOR_LEN (256 * 1024)
/* Size of DRAM reserved for malloc() use */ /* Size of DRAM reserved for malloc() use */
#define CFG_MALLOC_LEN (256 * 1024) #define CFG_MALLOC_LEN (1204 * 1024)
/* size in bytes reserved for initial data */ /* size in bytes reserved for initial data */
#define CFG_GBL_DATA_SIZE (256) #define CFG_GBL_DATA_SIZE (256)
@ -110,7 +113,7 @@
#define CFG_FLASH_EMPTY_INFO #define CFG_FLASH_EMPTY_INFO
#define CFG_ENV_IS_IN_FLASH #define CFG_ENV_IS_IN_FLASH
#define CFG_ENV_SECT_SIZE (16 * 1024) #define CFG_ENV_SECT_SIZE (256 * 1024)
#define CFG_ENV_SIZE (CFG_ENV_SECT_SIZE) #define CFG_ENV_SIZE (CFG_ENV_SECT_SIZE)
#define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN) #define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN)
#define CFG_FLASH_ERASE_TOUT 120000 #define CFG_FLASH_ERASE_TOUT 120000
@ -141,8 +144,10 @@
#endif /* CONFIG_CMD_PCI */ #endif /* CONFIG_CMD_PCI */
#if defined(CONFIG_CMD_NET) #if defined(CONFIG_CMD_NET)
/* #define CONFIG_NET_MULTI /*
#define CONFIG_RTL8169 */ #define CONFIG_NET_MULTI
#define CONFIG_RTL8169
*/
/* AX88696L Support(NE2000 base chip) */ /* AX88696L Support(NE2000 base chip) */
#define CONFIG_DRIVER_NE2000 #define CONFIG_DRIVER_NE2000
#define CONFIG_DRIVER_AX88796L #define CONFIG_DRIVER_AX88796L

10
include/configs/sh7763rdp.h
View File

@ -38,11 +38,7 @@
#define CONFIG_CMD_SDRAM #define CONFIG_CMD_SDRAM
#define CONFIG_CMD_FLASH #define CONFIG_CMD_FLASH
#define CONFIG_CMD_MEMORY #define CONFIG_CMD_MEMORY
#define CONFIG_CMD_NET
#define CONFIG_CMD_PING
#define CONFIG_CMD_ENV #define CONFIG_CMD_ENV
#define CONFIG_CMD_NFS
#define CONFIG_CMD_JFFS2
#define CONFIG_BOOTDELAY -1 #define CONFIG_BOOTDELAY -1
#define CONFIG_BOOTARGS "console=ttySC2,115200 root=1f01" #define CONFIG_BOOTARGS "console=ttySC2,115200 root=1f01"
@ -66,12 +62,6 @@
#define CFG_BAUDRATE_TABLE { 115200 } /* List of legal baudrate #define CFG_BAUDRATE_TABLE { 115200 } /* List of legal baudrate
settings for this board */ settings for this board */
/* Ethernet */
#define CONFIG_SH_ETHER 1
#define CONFIG_SH_ETHER_USE_PORT (1)
#define CONFIG_SH_ETHER_PHY_ADDR (0x01)
#define CFG_RX_ETH_BUFFER (8)
/* SDRAM */ /* SDRAM */
#define CFG_SDRAM_BASE (0x8C000000) #define CFG_SDRAM_BASE (0x8C000000)
#define CFG_SDRAM_SIZE (64 * 1024 * 1024) #define CFG_SDRAM_SIZE (64 * 1024 * 1024)

2
lib_sh/Makefile
View File

@ -26,7 +26,7 @@ SOBJS-y +=
COBJS-y += board.o COBJS-y += board.o
COBJS-y += bootm.o COBJS-y += bootm.o
#COBJS-y += time.o # COBJS-y += time.o
SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y)) OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))

4
lib_sh/board.c
View File

@ -112,6 +112,7 @@ static int sh_mem_env_init(void)
return 0; return 0;
} }
#if defined(CONFIG_CMD_NET)
static int sh_net_init(void) static int sh_net_init(void)
{ {
DECLARE_GLOBAL_DATA_PTR; DECLARE_GLOBAL_DATA_PTR;
@ -127,6 +128,7 @@ static int sh_net_init(void)
return 0; return 0;
} }
#endif
typedef int (init_fnc_t) (void); typedef int (init_fnc_t) (void);
@ -170,8 +172,8 @@ void sh_generic_init (void)
bd_t *bd; bd_t *bd;
init_fnc_t **init_fnc_ptr; init_fnc_t **init_fnc_ptr;
char *s;
int i; int i;
char *s;
memset (gd, 0, CFG_GBL_DATA_SIZE); memset (gd, 0, CFG_GBL_DATA_SIZE);

2
lib_sh/time.c
View File

@ -22,7 +22,7 @@
*/ */
#include <common.h> #include <common.h>
#include <asm/processer.h> #include <asm/processor.h>
static void tmu_timer_start (unsigned int timer) static void tmu_timer_start (unsigned int timer)
{ {