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sh: SH7763 SCIF support

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SH7763 has 3 SCIF channels. SCIF0 and 1 are same register constitution,
but only SCIF2 is different. This patch work all SCIF channel.

Signed-off-by: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
This commit is contained in:
Nobuhiro Iwamatsu 2008-06-06 16:16:08 +09:00 committed by Nobuhiro Iwamatsu
parent 8155efbd7a
commit 08c5fabe18
1 changed files with 73 additions and 55 deletions
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28
drivers/serial/serial_sh.c
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@ -26,6 +26,8 @@
#define SCIF_BASE SCIF0_BASE #define SCIF_BASE SCIF0_BASE
#elif defined (CONFIG_CONS_SCIF1) #elif defined (CONFIG_CONS_SCIF1)
#define SCIF_BASE SCIF1_BASE #define SCIF_BASE SCIF1_BASE
#elif defined (CONFIG_CONS_SCIF2)
#define SCIF_BASE SCIF2_BASE
#else #else
#error "Default SCIF doesn't set....." #error "Default SCIF doesn't set....."
#endif #endif
@ -54,6 +56,20 @@
# define SCRER (vu_short *)(SCIF_BASE + 0x2C) # define SCRER (vu_short *)(SCIF_BASE + 0x2C)
# define LSR_ORER 1 # define LSR_ORER 1
# define FIFOLEVEL_MASK 0xFF # define FIFOLEVEL_MASK 0xFF
#elif defined(CONFIG_CPU_SH7763)
# if defined (CONFIG_CONS_SCIF2)
# define SCSPTR (vu_short *)(SCIF_BASE + 0x20)
# define SCLSR (vu_short *)(SCIF_BASE + 0x24)
# define LSR_ORER 1
# define FIFOLEVEL_MASK 0x1F
# else
# define SCRFDR (vu_short *)(SCIF_BASE + 0x20)
# define SCSPTR (vu_short *)(SCIF_BASE + 0x24)
# define SCLSR (vu_short *)(SCIF_BASE + 0x28)
# define SCRER (vu_short *)(SCIF_BASE + 0x2C)
# define LSR_ORER 1
# define FIFOLEVEL_MASK 0xFF
# endif
#elif defined(CONFIG_CPU_SH7750) || \ #elif defined(CONFIG_CPU_SH7750) || \
defined(CONFIG_CPU_SH7751) || \ defined(CONFIG_CPU_SH7751) || \
defined(CONFIG_CPU_SH7722) defined(CONFIG_CPU_SH7722)
@ -65,7 +81,7 @@
# define SCLSR (vu_short *)(SCIF_BASE + 0x24) # define SCLSR (vu_short *)(SCIF_BASE + 0x24)
# define LSR_ORER 0x0200 # define LSR_ORER 0x0200
# define FIFOLEVEL_MASK 0x1F # define FIFOLEVEL_MASK 0x1F
#elif defined(CONFIG_CPU_SH7710) #elif defined(CONFIG_CPU_SH7710) || \
defined(CONFIG_CPU_SH7712) defined(CONFIG_CPU_SH7712)
# define SCLSR SCFSR /* SCSSR */ # define SCLSR SCFSR /* SCSSR */
# define LSR_ORER 1 # define LSR_ORER 1
@ -114,7 +130,7 @@ int serial_init (void)
static int serial_rx_fifo_level(void) static int serial_rx_fifo_level(void)
{ {
#if defined(CONFIG_SH4A) #if defined(SCRFDR)
return (*SCRFDR >> 0) & FIFOLEVEL_MASK; return (*SCRFDR >> 0) & FIFOLEVEL_MASK;
#else #else
return (*SCFDR >> 0) & FIFOLEVEL_MASK; return (*SCFDR >> 0) & FIFOLEVEL_MASK;
@ -158,7 +174,8 @@ int serial_tstc (void)
#define FSR_ERR_CLEAR 0x0063 #define FSR_ERR_CLEAR 0x0063
#define RDRF_CLEAR 0x00fc #define RDRF_CLEAR 0x00fc
void handle_error( void ){ void handle_error(void)
{
(void)*SCFSR; (void)*SCFSR;
*SCFSR = FSR_ERR_CLEAR; *SCFSR = FSR_ERR_CLEAR;
@ -166,12 +183,13 @@ void handle_error( void ){
*SCLSR = 0x00; *SCLSR = 0x00;
} }
int serial_getc_check( void ){ int serial_getc_check(void)
{
unsigned short status; unsigned short status;
status = *SCFSR; status = *SCFSR;
if (status & (FSR_FER | FSR_FER | FSR_ER | FSR_BRK)) if (status & (FSR_FER | FSR_ER | FSR_BRK))
handle_error(); handle_error();
if (*SCLSR & LSR_ORER) if (*SCLSR & LSR_ORER)
handle_error(); handle_error();